1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #ifdef DEBUG 100 #define debugf(fmt, args...) printf(fmt, ##args) 101 #else 102 #define debugf(fmt, args...) 103 #endif 104 105 #define TODO panic("%s: not implemented", __func__); 106 107 extern unsigned char _etext[]; 108 extern unsigned char _end[]; 109 110 extern uint32_t *bootinfo; 111 112 #ifdef SMP 113 extern uint32_t bp_ntlb1s; 114 #endif 115 116 vm_paddr_t kernload; 117 vm_offset_t kernstart; 118 vm_size_t kernsize; 119 120 /* Message buffer and tables. */ 121 static vm_offset_t data_start; 122 static vm_size_t data_end; 123 124 /* Phys/avail memory regions. */ 125 static struct mem_region *availmem_regions; 126 static int availmem_regions_sz; 127 static struct mem_region *physmem_regions; 128 static int physmem_regions_sz; 129 130 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 131 static vm_offset_t zero_page_va; 132 static struct mtx zero_page_mutex; 133 134 static struct mtx tlbivax_mutex; 135 136 /* 137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 138 * by idle thred only, no lock required. 139 */ 140 static vm_offset_t zero_page_idle_va; 141 142 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 143 static vm_offset_t copy_page_src_va; 144 static vm_offset_t copy_page_dst_va; 145 static struct mtx copy_page_mutex; 146 147 /**************************************************************************/ 148 /* PMAP */ 149 /**************************************************************************/ 150 151 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 152 vm_prot_t, u_int flags, int8_t psind); 153 154 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 155 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 156 157 /* 158 * If user pmap is processed with mmu_booke_remove and the resident count 159 * drops to 0, there are no more pages to remove, so we need not continue. 160 */ 161 #define PMAP_REMOVE_DONE(pmap) \ 162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 163 164 extern void tid_flush(tlbtid_t tid, int tlb0_ways, int tlb0_entries_per_way); 165 extern int elf32_nxstack; 166 167 /**************************************************************************/ 168 /* TLB and TID handling */ 169 /**************************************************************************/ 170 171 /* Translation ID busy table */ 172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 173 174 /* 175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 176 * core revisions and should be read from h/w registers during early config. 177 */ 178 uint32_t tlb0_entries; 179 uint32_t tlb0_ways; 180 uint32_t tlb0_entries_per_way; 181 182 #define TLB0_ENTRIES (tlb0_entries) 183 #define TLB0_WAYS (tlb0_ways) 184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186 #define TLB1_ENTRIES 16 187 188 /* In-ram copy of the TLB1 */ 189 static tlb_entry_t tlb1[TLB1_ENTRIES]; 190 191 /* Next free entry in the TLB1 */ 192 static unsigned int tlb1_idx; 193 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 194 195 static tlbtid_t tid_alloc(struct pmap *); 196 197 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 198 199 static int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t); 200 static void tlb1_write_entry(unsigned int); 201 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 202 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 203 204 static vm_size_t tsize2size(unsigned int); 205 static unsigned int size2tsize(vm_size_t); 206 static unsigned int ilog2(unsigned int); 207 208 static void set_mas4_defaults(void); 209 210 static inline void tlb0_flush_entry(vm_offset_t); 211 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 212 213 /**************************************************************************/ 214 /* Page table management */ 215 /**************************************************************************/ 216 217 static struct rwlock_padalign pvh_global_lock; 218 219 /* Data for the pv entry allocation mechanism */ 220 static uma_zone_t pvzone; 221 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 222 223 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 224 225 #ifndef PMAP_SHPGPERPROC 226 #define PMAP_SHPGPERPROC 200 227 #endif 228 229 static void ptbl_init(void); 230 static struct ptbl_buf *ptbl_buf_alloc(void); 231 static void ptbl_buf_free(struct ptbl_buf *); 232 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 233 234 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 235 static void ptbl_free(mmu_t, pmap_t, unsigned int); 236 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 237 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 238 239 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 240 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 241 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 242 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 243 244 static pv_entry_t pv_alloc(void); 245 static void pv_free(pv_entry_t); 246 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 247 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 248 249 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 250 #define PTBL_BUFS (128 * 16) 251 252 struct ptbl_buf { 253 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 254 vm_offset_t kva; /* va of mapping */ 255 }; 256 257 /* ptbl free list and a lock used for access synchronization. */ 258 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 259 static struct mtx ptbl_buf_freelist_lock; 260 261 /* Base address of kva space allocated fot ptbl bufs. */ 262 static vm_offset_t ptbl_buf_pool_vabase; 263 264 /* Pointer to ptbl_buf structures. */ 265 static struct ptbl_buf *ptbl_bufs; 266 267 #ifdef SMP 268 void pmap_bootstrap_ap(volatile uint32_t *); 269 #endif 270 271 /* 272 * Kernel MMU interface 273 */ 274 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 275 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 276 vm_size_t, vm_offset_t); 277 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 278 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 279 vm_offset_t, vm_page_t *, vm_offset_t, int); 280 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 281 vm_prot_t, u_int flags, int8_t psind); 282 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 283 vm_page_t, vm_prot_t); 284 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 285 vm_prot_t); 286 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 287 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 288 vm_prot_t); 289 static void mmu_booke_init(mmu_t); 290 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 291 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 292 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 293 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 294 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 295 int); 296 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 297 vm_paddr_t *); 298 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 299 vm_object_t, vm_pindex_t, vm_size_t); 300 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 301 static void mmu_booke_page_init(mmu_t, vm_page_t); 302 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 303 static void mmu_booke_pinit(mmu_t, pmap_t); 304 static void mmu_booke_pinit0(mmu_t, pmap_t); 305 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 306 vm_prot_t); 307 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 308 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 309 static void mmu_booke_release(mmu_t, pmap_t); 310 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 311 static void mmu_booke_remove_all(mmu_t, vm_page_t); 312 static void mmu_booke_remove_write(mmu_t, vm_page_t); 313 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 314 static void mmu_booke_zero_page(mmu_t, vm_page_t); 315 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 316 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 317 static void mmu_booke_activate(mmu_t, struct thread *); 318 static void mmu_booke_deactivate(mmu_t, struct thread *); 319 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 320 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 321 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 322 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 323 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 324 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 325 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 326 static void mmu_booke_kremove(mmu_t, vm_offset_t); 327 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 328 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 329 vm_size_t); 330 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 331 void **); 332 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 333 void *); 334 static void mmu_booke_scan_init(mmu_t); 335 336 static mmu_method_t mmu_booke_methods[] = { 337 /* pmap dispatcher interface */ 338 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 339 MMUMETHOD(mmu_copy, mmu_booke_copy), 340 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 341 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 342 MMUMETHOD(mmu_enter, mmu_booke_enter), 343 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 344 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 345 MMUMETHOD(mmu_extract, mmu_booke_extract), 346 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 347 MMUMETHOD(mmu_init, mmu_booke_init), 348 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 349 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 350 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 351 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 352 MMUMETHOD(mmu_map, mmu_booke_map), 353 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 354 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 355 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 356 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 357 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 358 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 359 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 360 MMUMETHOD(mmu_protect, mmu_booke_protect), 361 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 362 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 363 MMUMETHOD(mmu_release, mmu_booke_release), 364 MMUMETHOD(mmu_remove, mmu_booke_remove), 365 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 366 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 367 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 368 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 369 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 370 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 371 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 372 MMUMETHOD(mmu_activate, mmu_booke_activate), 373 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 374 375 /* Internal interfaces */ 376 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 377 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 378 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 379 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 380 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 381 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 382 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 383 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 384 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 385 386 /* dumpsys() support */ 387 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 388 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 389 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 390 391 { 0, 0 } 392 }; 393 394 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 395 396 static __inline uint32_t 397 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 398 { 399 uint32_t attrib; 400 int i; 401 402 if (ma != VM_MEMATTR_DEFAULT) { 403 switch (ma) { 404 case VM_MEMATTR_UNCACHEABLE: 405 return (PTE_I | PTE_G); 406 case VM_MEMATTR_WRITE_COMBINING: 407 case VM_MEMATTR_WRITE_BACK: 408 case VM_MEMATTR_PREFETCHABLE: 409 return (PTE_I); 410 case VM_MEMATTR_WRITE_THROUGH: 411 return (PTE_W | PTE_M); 412 } 413 } 414 415 /* 416 * Assume the page is cache inhibited and access is guarded unless 417 * it's in our available memory array. 418 */ 419 attrib = _TLB_ENTRY_IO; 420 for (i = 0; i < physmem_regions_sz; i++) { 421 if ((pa >= physmem_regions[i].mr_start) && 422 (pa < (physmem_regions[i].mr_start + 423 physmem_regions[i].mr_size))) { 424 attrib = _TLB_ENTRY_MEM; 425 break; 426 } 427 } 428 429 return (attrib); 430 } 431 432 static inline void 433 tlb_miss_lock(void) 434 { 435 #ifdef SMP 436 struct pcpu *pc; 437 438 if (!smp_started) 439 return; 440 441 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 442 if (pc != pcpup) { 443 444 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 445 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 446 447 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 448 ("tlb_miss_lock: tried to lock self")); 449 450 tlb_lock(pc->pc_booke_tlb_lock); 451 452 CTR1(KTR_PMAP, "%s: locked", __func__); 453 } 454 } 455 #endif 456 } 457 458 static inline void 459 tlb_miss_unlock(void) 460 { 461 #ifdef SMP 462 struct pcpu *pc; 463 464 if (!smp_started) 465 return; 466 467 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 468 if (pc != pcpup) { 469 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 470 __func__, pc->pc_cpuid); 471 472 tlb_unlock(pc->pc_booke_tlb_lock); 473 474 CTR1(KTR_PMAP, "%s: unlocked", __func__); 475 } 476 } 477 #endif 478 } 479 480 /* Return number of entries in TLB0. */ 481 static __inline void 482 tlb0_get_tlbconf(void) 483 { 484 uint32_t tlb0_cfg; 485 486 tlb0_cfg = mfspr(SPR_TLB0CFG); 487 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 488 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 489 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 490 } 491 492 /* Initialize pool of kva ptbl buffers. */ 493 static void 494 ptbl_init(void) 495 { 496 int i; 497 498 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 499 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 500 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 501 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 502 503 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 504 TAILQ_INIT(&ptbl_buf_freelist); 505 506 for (i = 0; i < PTBL_BUFS; i++) { 507 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 508 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 509 } 510 } 511 512 /* Get a ptbl_buf from the freelist. */ 513 static struct ptbl_buf * 514 ptbl_buf_alloc(void) 515 { 516 struct ptbl_buf *buf; 517 518 mtx_lock(&ptbl_buf_freelist_lock); 519 buf = TAILQ_FIRST(&ptbl_buf_freelist); 520 if (buf != NULL) 521 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 522 mtx_unlock(&ptbl_buf_freelist_lock); 523 524 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 525 526 return (buf); 527 } 528 529 /* Return ptbl buff to free pool. */ 530 static void 531 ptbl_buf_free(struct ptbl_buf *buf) 532 { 533 534 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 535 536 mtx_lock(&ptbl_buf_freelist_lock); 537 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 538 mtx_unlock(&ptbl_buf_freelist_lock); 539 } 540 541 /* 542 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 543 */ 544 static void 545 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 546 { 547 struct ptbl_buf *pbuf; 548 549 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 550 551 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 552 553 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 554 if (pbuf->kva == (vm_offset_t)ptbl) { 555 /* Remove from pmap ptbl buf list. */ 556 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 557 558 /* Free corresponding ptbl buf. */ 559 ptbl_buf_free(pbuf); 560 break; 561 } 562 } 563 564 /* Allocate page table. */ 565 static pte_t * 566 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 567 { 568 vm_page_t mtbl[PTBL_PAGES]; 569 vm_page_t m; 570 struct ptbl_buf *pbuf; 571 unsigned int pidx; 572 pte_t *ptbl; 573 int i, j; 574 575 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 576 (pmap == kernel_pmap), pdir_idx); 577 578 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 579 ("ptbl_alloc: invalid pdir_idx")); 580 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 581 ("pte_alloc: valid ptbl entry exists!")); 582 583 pbuf = ptbl_buf_alloc(); 584 if (pbuf == NULL) 585 panic("pte_alloc: couldn't alloc kernel virtual memory"); 586 587 ptbl = (pte_t *)pbuf->kva; 588 589 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 590 591 /* Allocate ptbl pages, this will sleep! */ 592 for (i = 0; i < PTBL_PAGES; i++) { 593 pidx = (PTBL_PAGES * pdir_idx) + i; 594 while ((m = vm_page_alloc(NULL, pidx, 595 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 596 PMAP_UNLOCK(pmap); 597 rw_wunlock(&pvh_global_lock); 598 if (nosleep) { 599 ptbl_free_pmap_ptbl(pmap, ptbl); 600 for (j = 0; j < i; j++) 601 vm_page_free(mtbl[j]); 602 atomic_subtract_int(&vm_cnt.v_wire_count, i); 603 return (NULL); 604 } 605 VM_WAIT; 606 rw_wlock(&pvh_global_lock); 607 PMAP_LOCK(pmap); 608 } 609 mtbl[i] = m; 610 } 611 612 /* Map allocated pages into kernel_pmap. */ 613 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 614 615 /* Zero whole ptbl. */ 616 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 617 618 /* Add pbuf to the pmap ptbl bufs list. */ 619 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 620 621 return (ptbl); 622 } 623 624 /* Free ptbl pages and invalidate pdir entry. */ 625 static void 626 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 627 { 628 pte_t *ptbl; 629 vm_paddr_t pa; 630 vm_offset_t va; 631 vm_page_t m; 632 int i; 633 634 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 635 (pmap == kernel_pmap), pdir_idx); 636 637 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 638 ("ptbl_free: invalid pdir_idx")); 639 640 ptbl = pmap->pm_pdir[pdir_idx]; 641 642 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 643 644 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 645 646 /* 647 * Invalidate the pdir entry as soon as possible, so that other CPUs 648 * don't attempt to look up the page tables we are releasing. 649 */ 650 mtx_lock_spin(&tlbivax_mutex); 651 tlb_miss_lock(); 652 653 pmap->pm_pdir[pdir_idx] = NULL; 654 655 tlb_miss_unlock(); 656 mtx_unlock_spin(&tlbivax_mutex); 657 658 for (i = 0; i < PTBL_PAGES; i++) { 659 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 660 pa = pte_vatopa(mmu, kernel_pmap, va); 661 m = PHYS_TO_VM_PAGE(pa); 662 vm_page_free_zero(m); 663 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 664 mmu_booke_kremove(mmu, va); 665 } 666 667 ptbl_free_pmap_ptbl(pmap, ptbl); 668 } 669 670 /* 671 * Decrement ptbl pages hold count and attempt to free ptbl pages. 672 * Called when removing pte entry from ptbl. 673 * 674 * Return 1 if ptbl pages were freed. 675 */ 676 static int 677 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 678 { 679 pte_t *ptbl; 680 vm_paddr_t pa; 681 vm_page_t m; 682 int i; 683 684 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 685 (pmap == kernel_pmap), pdir_idx); 686 687 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 688 ("ptbl_unhold: invalid pdir_idx")); 689 KASSERT((pmap != kernel_pmap), 690 ("ptbl_unhold: unholding kernel ptbl!")); 691 692 ptbl = pmap->pm_pdir[pdir_idx]; 693 694 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 695 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 696 ("ptbl_unhold: non kva ptbl")); 697 698 /* decrement hold count */ 699 for (i = 0; i < PTBL_PAGES; i++) { 700 pa = pte_vatopa(mmu, kernel_pmap, 701 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 702 m = PHYS_TO_VM_PAGE(pa); 703 m->wire_count--; 704 } 705 706 /* 707 * Free ptbl pages if there are no pte etries in this ptbl. 708 * wire_count has the same value for all ptbl pages, so check the last 709 * page. 710 */ 711 if (m->wire_count == 0) { 712 ptbl_free(mmu, pmap, pdir_idx); 713 714 //debugf("ptbl_unhold: e (freed ptbl)\n"); 715 return (1); 716 } 717 718 return (0); 719 } 720 721 /* 722 * Increment hold count for ptbl pages. This routine is used when a new pte 723 * entry is being inserted into the ptbl. 724 */ 725 static void 726 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 727 { 728 vm_paddr_t pa; 729 pte_t *ptbl; 730 vm_page_t m; 731 int i; 732 733 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 734 pdir_idx); 735 736 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 737 ("ptbl_hold: invalid pdir_idx")); 738 KASSERT((pmap != kernel_pmap), 739 ("ptbl_hold: holding kernel ptbl!")); 740 741 ptbl = pmap->pm_pdir[pdir_idx]; 742 743 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 744 745 for (i = 0; i < PTBL_PAGES; i++) { 746 pa = pte_vatopa(mmu, kernel_pmap, 747 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 748 m = PHYS_TO_VM_PAGE(pa); 749 m->wire_count++; 750 } 751 } 752 753 /* Allocate pv_entry structure. */ 754 pv_entry_t 755 pv_alloc(void) 756 { 757 pv_entry_t pv; 758 759 pv_entry_count++; 760 if (pv_entry_count > pv_entry_high_water) 761 pagedaemon_wakeup(); 762 pv = uma_zalloc(pvzone, M_NOWAIT); 763 764 return (pv); 765 } 766 767 /* Free pv_entry structure. */ 768 static __inline void 769 pv_free(pv_entry_t pve) 770 { 771 772 pv_entry_count--; 773 uma_zfree(pvzone, pve); 774 } 775 776 777 /* Allocate and initialize pv_entry structure. */ 778 static void 779 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 780 { 781 pv_entry_t pve; 782 783 //int su = (pmap == kernel_pmap); 784 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 785 // (u_int32_t)pmap, va, (u_int32_t)m); 786 787 pve = pv_alloc(); 788 if (pve == NULL) 789 panic("pv_insert: no pv entries!"); 790 791 pve->pv_pmap = pmap; 792 pve->pv_va = va; 793 794 /* add to pv_list */ 795 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 796 rw_assert(&pvh_global_lock, RA_WLOCKED); 797 798 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 799 800 //debugf("pv_insert: e\n"); 801 } 802 803 /* Destroy pv entry. */ 804 static void 805 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 806 { 807 pv_entry_t pve; 808 809 //int su = (pmap == kernel_pmap); 810 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 811 812 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 813 rw_assert(&pvh_global_lock, RA_WLOCKED); 814 815 /* find pv entry */ 816 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 817 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 818 /* remove from pv_list */ 819 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 820 if (TAILQ_EMPTY(&m->md.pv_list)) 821 vm_page_aflag_clear(m, PGA_WRITEABLE); 822 823 /* free pv entry struct */ 824 pv_free(pve); 825 break; 826 } 827 } 828 829 //debugf("pv_remove: e\n"); 830 } 831 832 /* 833 * Clean pte entry, try to free page table page if requested. 834 * 835 * Return 1 if ptbl pages were freed, otherwise return 0. 836 */ 837 static int 838 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 839 { 840 unsigned int pdir_idx = PDIR_IDX(va); 841 unsigned int ptbl_idx = PTBL_IDX(va); 842 vm_page_t m; 843 pte_t *ptbl; 844 pte_t *pte; 845 846 //int su = (pmap == kernel_pmap); 847 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 848 // su, (u_int32_t)pmap, va, flags); 849 850 ptbl = pmap->pm_pdir[pdir_idx]; 851 KASSERT(ptbl, ("pte_remove: null ptbl")); 852 853 pte = &ptbl[ptbl_idx]; 854 855 if (pte == NULL || !PTE_ISVALID(pte)) 856 return (0); 857 858 if (PTE_ISWIRED(pte)) 859 pmap->pm_stats.wired_count--; 860 861 /* Handle managed entry. */ 862 if (PTE_ISMANAGED(pte)) { 863 /* Get vm_page_t for mapped pte. */ 864 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 865 866 if (PTE_ISMODIFIED(pte)) 867 vm_page_dirty(m); 868 869 if (PTE_ISREFERENCED(pte)) 870 vm_page_aflag_set(m, PGA_REFERENCED); 871 872 pv_remove(pmap, va, m); 873 } 874 875 mtx_lock_spin(&tlbivax_mutex); 876 tlb_miss_lock(); 877 878 tlb0_flush_entry(va); 879 pte->flags = 0; 880 pte->rpn = 0; 881 882 tlb_miss_unlock(); 883 mtx_unlock_spin(&tlbivax_mutex); 884 885 pmap->pm_stats.resident_count--; 886 887 if (flags & PTBL_UNHOLD) { 888 //debugf("pte_remove: e (unhold)\n"); 889 return (ptbl_unhold(mmu, pmap, pdir_idx)); 890 } 891 892 //debugf("pte_remove: e\n"); 893 return (0); 894 } 895 896 /* 897 * Insert PTE for a given page and virtual address. 898 */ 899 static int 900 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 901 boolean_t nosleep) 902 { 903 unsigned int pdir_idx = PDIR_IDX(va); 904 unsigned int ptbl_idx = PTBL_IDX(va); 905 pte_t *ptbl, *pte; 906 907 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 908 pmap == kernel_pmap, pmap, va); 909 910 /* Get the page table pointer. */ 911 ptbl = pmap->pm_pdir[pdir_idx]; 912 913 if (ptbl == NULL) { 914 /* Allocate page table pages. */ 915 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 916 if (ptbl == NULL) { 917 KASSERT(nosleep, ("nosleep and NULL ptbl")); 918 return (ENOMEM); 919 } 920 } else { 921 /* 922 * Check if there is valid mapping for requested 923 * va, if there is, remove it. 924 */ 925 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 926 if (PTE_ISVALID(pte)) { 927 pte_remove(mmu, pmap, va, PTBL_HOLD); 928 } else { 929 /* 930 * pte is not used, increment hold count 931 * for ptbl pages. 932 */ 933 if (pmap != kernel_pmap) 934 ptbl_hold(mmu, pmap, pdir_idx); 935 } 936 } 937 938 /* 939 * Insert pv_entry into pv_list for mapped page if part of managed 940 * memory. 941 */ 942 if ((m->oflags & VPO_UNMANAGED) == 0) { 943 flags |= PTE_MANAGED; 944 945 /* Create and insert pv entry. */ 946 pv_insert(pmap, va, m); 947 } 948 949 pmap->pm_stats.resident_count++; 950 951 mtx_lock_spin(&tlbivax_mutex); 952 tlb_miss_lock(); 953 954 tlb0_flush_entry(va); 955 if (pmap->pm_pdir[pdir_idx] == NULL) { 956 /* 957 * If we just allocated a new page table, hook it in 958 * the pdir. 959 */ 960 pmap->pm_pdir[pdir_idx] = ptbl; 961 } 962 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 963 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 964 pte->flags |= (PTE_VALID | flags); 965 966 tlb_miss_unlock(); 967 mtx_unlock_spin(&tlbivax_mutex); 968 return (0); 969 } 970 971 /* Return the pa for the given pmap/va. */ 972 static vm_paddr_t 973 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 974 { 975 vm_paddr_t pa = 0; 976 pte_t *pte; 977 978 pte = pte_find(mmu, pmap, va); 979 if ((pte != NULL) && PTE_ISVALID(pte)) 980 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 981 return (pa); 982 } 983 984 /* Get a pointer to a PTE in a page table. */ 985 static pte_t * 986 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 987 { 988 unsigned int pdir_idx = PDIR_IDX(va); 989 unsigned int ptbl_idx = PTBL_IDX(va); 990 991 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 992 993 if (pmap->pm_pdir[pdir_idx]) 994 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 995 996 return (NULL); 997 } 998 999 /**************************************************************************/ 1000 /* PMAP related */ 1001 /**************************************************************************/ 1002 1003 /* 1004 * This is called during booke_init, before the system is really initialized. 1005 */ 1006 static void 1007 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1008 { 1009 vm_offset_t phys_kernelend; 1010 struct mem_region *mp, *mp1; 1011 int cnt, i, j; 1012 u_int s, e, sz; 1013 u_int phys_avail_count; 1014 vm_size_t physsz, hwphyssz, kstack0_sz; 1015 vm_offset_t kernel_pdir, kstack0, va; 1016 vm_paddr_t kstack0_phys; 1017 void *dpcpu; 1018 pte_t *pte; 1019 1020 debugf("mmu_booke_bootstrap: entered\n"); 1021 1022 /* Set interesting system properties */ 1023 hw_direct_map = 0; 1024 elf32_nxstack = 1; 1025 1026 /* Initialize invalidation mutex */ 1027 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1028 1029 /* Read TLB0 size and associativity. */ 1030 tlb0_get_tlbconf(); 1031 1032 /* 1033 * Align kernel start and end address (kernel image). 1034 * Note that kernel end does not necessarily relate to kernsize. 1035 * kernsize is the size of the kernel that is actually mapped. 1036 */ 1037 kernstart = trunc_page(start); 1038 data_start = round_page(kernelend); 1039 data_end = data_start; 1040 1041 /* 1042 * Addresses of preloaded modules (like file systems) use 1043 * physical addresses. Make sure we relocate those into 1044 * virtual addresses. 1045 */ 1046 preload_addr_relocate = kernstart - kernload; 1047 1048 /* Allocate the dynamic per-cpu area. */ 1049 dpcpu = (void *)data_end; 1050 data_end += DPCPU_SIZE; 1051 1052 /* Allocate space for the message buffer. */ 1053 msgbufp = (struct msgbuf *)data_end; 1054 data_end += msgbufsize; 1055 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1056 data_end); 1057 1058 data_end = round_page(data_end); 1059 1060 /* Allocate space for ptbl_bufs. */ 1061 ptbl_bufs = (struct ptbl_buf *)data_end; 1062 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1063 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1064 data_end); 1065 1066 data_end = round_page(data_end); 1067 1068 /* Allocate PTE tables for kernel KVA. */ 1069 kernel_pdir = data_end; 1070 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1071 PDIR_SIZE - 1) / PDIR_SIZE; 1072 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1073 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1074 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1075 1076 debugf(" data_end: 0x%08x\n", data_end); 1077 if (data_end - kernstart > kernsize) { 1078 kernsize += tlb1_mapin_region(kernstart + kernsize, 1079 kernload + kernsize, (data_end - kernstart) - kernsize); 1080 } 1081 data_end = kernstart + kernsize; 1082 debugf(" updated data_end: 0x%08x\n", data_end); 1083 1084 /* 1085 * Clear the structures - note we can only do it safely after the 1086 * possible additional TLB1 translations are in place (above) so that 1087 * all range up to the currently calculated 'data_end' is covered. 1088 */ 1089 dpcpu_init(dpcpu, 0); 1090 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1091 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1092 1093 /*******************************************************/ 1094 /* Set the start and end of kva. */ 1095 /*******************************************************/ 1096 virtual_avail = round_page(data_end); 1097 virtual_end = VM_MAX_KERNEL_ADDRESS; 1098 1099 /* Allocate KVA space for page zero/copy operations. */ 1100 zero_page_va = virtual_avail; 1101 virtual_avail += PAGE_SIZE; 1102 zero_page_idle_va = virtual_avail; 1103 virtual_avail += PAGE_SIZE; 1104 copy_page_src_va = virtual_avail; 1105 virtual_avail += PAGE_SIZE; 1106 copy_page_dst_va = virtual_avail; 1107 virtual_avail += PAGE_SIZE; 1108 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1109 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1110 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1111 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1112 1113 /* Initialize page zero/copy mutexes. */ 1114 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1115 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1116 1117 /* Allocate KVA space for ptbl bufs. */ 1118 ptbl_buf_pool_vabase = virtual_avail; 1119 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1120 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1121 ptbl_buf_pool_vabase, virtual_avail); 1122 1123 /* Calculate corresponding physical addresses for the kernel region. */ 1124 phys_kernelend = kernload + kernsize; 1125 debugf("kernel image and allocated data:\n"); 1126 debugf(" kernload = 0x%08x\n", kernload); 1127 debugf(" kernstart = 0x%08x\n", kernstart); 1128 debugf(" kernsize = 0x%08x\n", kernsize); 1129 1130 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1131 panic("mmu_booke_bootstrap: phys_avail too small"); 1132 1133 /* 1134 * Remove kernel physical address range from avail regions list. Page 1135 * align all regions. Non-page aligned memory isn't very interesting 1136 * to us. Also, sort the entries for ascending addresses. 1137 */ 1138 1139 /* Retrieve phys/avail mem regions */ 1140 mem_regions(&physmem_regions, &physmem_regions_sz, 1141 &availmem_regions, &availmem_regions_sz); 1142 sz = 0; 1143 cnt = availmem_regions_sz; 1144 debugf("processing avail regions:\n"); 1145 for (mp = availmem_regions; mp->mr_size; mp++) { 1146 s = mp->mr_start; 1147 e = mp->mr_start + mp->mr_size; 1148 debugf(" %08x-%08x -> ", s, e); 1149 /* Check whether this region holds all of the kernel. */ 1150 if (s < kernload && e > phys_kernelend) { 1151 availmem_regions[cnt].mr_start = phys_kernelend; 1152 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1153 e = kernload; 1154 } 1155 /* Look whether this regions starts within the kernel. */ 1156 if (s >= kernload && s < phys_kernelend) { 1157 if (e <= phys_kernelend) 1158 goto empty; 1159 s = phys_kernelend; 1160 } 1161 /* Now look whether this region ends within the kernel. */ 1162 if (e > kernload && e <= phys_kernelend) { 1163 if (s >= kernload) 1164 goto empty; 1165 e = kernload; 1166 } 1167 /* Now page align the start and size of the region. */ 1168 s = round_page(s); 1169 e = trunc_page(e); 1170 if (e < s) 1171 e = s; 1172 sz = e - s; 1173 debugf("%08x-%08x = %x\n", s, e, sz); 1174 1175 /* Check whether some memory is left here. */ 1176 if (sz == 0) { 1177 empty: 1178 memmove(mp, mp + 1, 1179 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1180 cnt--; 1181 mp--; 1182 continue; 1183 } 1184 1185 /* Do an insertion sort. */ 1186 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1187 if (s < mp1->mr_start) 1188 break; 1189 if (mp1 < mp) { 1190 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1191 mp1->mr_start = s; 1192 mp1->mr_size = sz; 1193 } else { 1194 mp->mr_start = s; 1195 mp->mr_size = sz; 1196 } 1197 } 1198 availmem_regions_sz = cnt; 1199 1200 /*******************************************************/ 1201 /* Steal physical memory for kernel stack from the end */ 1202 /* of the first avail region */ 1203 /*******************************************************/ 1204 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1205 kstack0_phys = availmem_regions[0].mr_start + 1206 availmem_regions[0].mr_size; 1207 kstack0_phys -= kstack0_sz; 1208 availmem_regions[0].mr_size -= kstack0_sz; 1209 1210 /*******************************************************/ 1211 /* Fill in phys_avail table, based on availmem_regions */ 1212 /*******************************************************/ 1213 phys_avail_count = 0; 1214 physsz = 0; 1215 hwphyssz = 0; 1216 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1217 1218 debugf("fill in phys_avail:\n"); 1219 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1220 1221 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1222 availmem_regions[i].mr_start, 1223 availmem_regions[i].mr_start + 1224 availmem_regions[i].mr_size, 1225 availmem_regions[i].mr_size); 1226 1227 if (hwphyssz != 0 && 1228 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1229 debugf(" hw.physmem adjust\n"); 1230 if (physsz < hwphyssz) { 1231 phys_avail[j] = availmem_regions[i].mr_start; 1232 phys_avail[j + 1] = 1233 availmem_regions[i].mr_start + 1234 hwphyssz - physsz; 1235 physsz = hwphyssz; 1236 phys_avail_count++; 1237 } 1238 break; 1239 } 1240 1241 phys_avail[j] = availmem_regions[i].mr_start; 1242 phys_avail[j + 1] = availmem_regions[i].mr_start + 1243 availmem_regions[i].mr_size; 1244 phys_avail_count++; 1245 physsz += availmem_regions[i].mr_size; 1246 } 1247 physmem = btoc(physsz); 1248 1249 /* Calculate the last available physical address. */ 1250 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1251 ; 1252 Maxmem = powerpc_btop(phys_avail[i + 1]); 1253 1254 debugf("Maxmem = 0x%08lx\n", Maxmem); 1255 debugf("phys_avail_count = %d\n", phys_avail_count); 1256 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1257 physmem); 1258 1259 /*******************************************************/ 1260 /* Initialize (statically allocated) kernel pmap. */ 1261 /*******************************************************/ 1262 PMAP_LOCK_INIT(kernel_pmap); 1263 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1264 1265 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1266 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1267 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1268 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1269 1270 /* Initialize kernel pdir */ 1271 for (i = 0; i < kernel_ptbls; i++) 1272 kernel_pmap->pm_pdir[kptbl_min + i] = 1273 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1274 1275 for (i = 0; i < MAXCPU; i++) { 1276 kernel_pmap->pm_tid[i] = TID_KERNEL; 1277 1278 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1279 tidbusy[i][0] = kernel_pmap; 1280 } 1281 1282 /* 1283 * Fill in PTEs covering kernel code and data. They are not required 1284 * for address translation, as this area is covered by static TLB1 1285 * entries, but for pte_vatopa() to work correctly with kernel area 1286 * addresses. 1287 */ 1288 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1289 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1290 pte->rpn = kernload + (va - kernstart); 1291 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1292 PTE_VALID; 1293 } 1294 /* Mark kernel_pmap active on all CPUs */ 1295 CPU_FILL(&kernel_pmap->pm_active); 1296 1297 /* 1298 * Initialize the global pv list lock. 1299 */ 1300 rw_init(&pvh_global_lock, "pmap pv global"); 1301 1302 /*******************************************************/ 1303 /* Final setup */ 1304 /*******************************************************/ 1305 1306 /* Enter kstack0 into kernel map, provide guard page */ 1307 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1308 thread0.td_kstack = kstack0; 1309 thread0.td_kstack_pages = KSTACK_PAGES; 1310 1311 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1312 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1313 kstack0_phys, kstack0_phys + kstack0_sz); 1314 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1315 1316 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1317 for (i = 0; i < KSTACK_PAGES; i++) { 1318 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1319 kstack0 += PAGE_SIZE; 1320 kstack0_phys += PAGE_SIZE; 1321 } 1322 1323 pmap_bootstrapped = 1; 1324 1325 debugf("virtual_avail = %08x\n", virtual_avail); 1326 debugf("virtual_end = %08x\n", virtual_end); 1327 1328 debugf("mmu_booke_bootstrap: exit\n"); 1329 } 1330 1331 #ifdef SMP 1332 void 1333 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1334 { 1335 int i; 1336 1337 /* 1338 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1339 * have the snapshot of its contents in the s/w tlb1[] table, so use 1340 * these values directly to (re)program AP's TLB1 hardware. 1341 */ 1342 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1343 /* Skip invalid entries */ 1344 if (!(tlb1[i].mas1 & MAS1_VALID)) 1345 continue; 1346 1347 tlb1_write_entry(i); 1348 } 1349 1350 set_mas4_defaults(); 1351 } 1352 #endif 1353 1354 /* 1355 * Get the physical page address for the given pmap/virtual address. 1356 */ 1357 static vm_paddr_t 1358 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1359 { 1360 vm_paddr_t pa; 1361 1362 PMAP_LOCK(pmap); 1363 pa = pte_vatopa(mmu, pmap, va); 1364 PMAP_UNLOCK(pmap); 1365 1366 return (pa); 1367 } 1368 1369 /* 1370 * Extract the physical page address associated with the given 1371 * kernel virtual address. 1372 */ 1373 static vm_paddr_t 1374 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1375 { 1376 int i; 1377 1378 /* Check TLB1 mappings */ 1379 for (i = 0; i < tlb1_idx; i++) { 1380 if (!(tlb1[i].mas1 & MAS1_VALID)) 1381 continue; 1382 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1383 return (tlb1[i].phys + (va - tlb1[i].virt)); 1384 } 1385 1386 return (pte_vatopa(mmu, kernel_pmap, va)); 1387 } 1388 1389 /* 1390 * Initialize the pmap module. 1391 * Called by vm_init, to initialize any structures that the pmap 1392 * system needs to map virtual memory. 1393 */ 1394 static void 1395 mmu_booke_init(mmu_t mmu) 1396 { 1397 int shpgperproc = PMAP_SHPGPERPROC; 1398 1399 /* 1400 * Initialize the address space (zone) for the pv entries. Set a 1401 * high water mark so that the system can recover from excessive 1402 * numbers of pv entries. 1403 */ 1404 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1405 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1406 1407 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1408 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1409 1410 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1411 pv_entry_high_water = 9 * (pv_entry_max / 10); 1412 1413 uma_zone_reserve_kva(pvzone, pv_entry_max); 1414 1415 /* Pre-fill pvzone with initial number of pv entries. */ 1416 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1417 1418 /* Initialize ptbl allocation. */ 1419 ptbl_init(); 1420 } 1421 1422 /* 1423 * Map a list of wired pages into kernel virtual address space. This is 1424 * intended for temporary mappings which do not need page modification or 1425 * references recorded. Existing mappings in the region are overwritten. 1426 */ 1427 static void 1428 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1429 { 1430 vm_offset_t va; 1431 1432 va = sva; 1433 while (count-- > 0) { 1434 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1435 va += PAGE_SIZE; 1436 m++; 1437 } 1438 } 1439 1440 /* 1441 * Remove page mappings from kernel virtual address space. Intended for 1442 * temporary mappings entered by mmu_booke_qenter. 1443 */ 1444 static void 1445 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1446 { 1447 vm_offset_t va; 1448 1449 va = sva; 1450 while (count-- > 0) { 1451 mmu_booke_kremove(mmu, va); 1452 va += PAGE_SIZE; 1453 } 1454 } 1455 1456 /* 1457 * Map a wired page into kernel virtual address space. 1458 */ 1459 static void 1460 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1461 { 1462 1463 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1464 } 1465 1466 static void 1467 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1468 { 1469 unsigned int pdir_idx = PDIR_IDX(va); 1470 unsigned int ptbl_idx = PTBL_IDX(va); 1471 uint32_t flags; 1472 pte_t *pte; 1473 1474 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1475 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1476 1477 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1478 flags |= tlb_calc_wimg(pa, ma); 1479 1480 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1481 1482 mtx_lock_spin(&tlbivax_mutex); 1483 tlb_miss_lock(); 1484 1485 if (PTE_ISVALID(pte)) { 1486 1487 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1488 1489 /* Flush entry from TLB0 */ 1490 tlb0_flush_entry(va); 1491 } 1492 1493 pte->rpn = pa & ~PTE_PA_MASK; 1494 pte->flags = flags; 1495 1496 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1497 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1498 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1499 1500 /* Flush the real memory from the instruction cache. */ 1501 if ((flags & (PTE_I | PTE_G)) == 0) { 1502 __syncicache((void *)va, PAGE_SIZE); 1503 } 1504 1505 tlb_miss_unlock(); 1506 mtx_unlock_spin(&tlbivax_mutex); 1507 } 1508 1509 /* 1510 * Remove a page from kernel page table. 1511 */ 1512 static void 1513 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1514 { 1515 unsigned int pdir_idx = PDIR_IDX(va); 1516 unsigned int ptbl_idx = PTBL_IDX(va); 1517 pte_t *pte; 1518 1519 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1520 1521 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1522 (va <= VM_MAX_KERNEL_ADDRESS)), 1523 ("mmu_booke_kremove: invalid va")); 1524 1525 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1526 1527 if (!PTE_ISVALID(pte)) { 1528 1529 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1530 1531 return; 1532 } 1533 1534 mtx_lock_spin(&tlbivax_mutex); 1535 tlb_miss_lock(); 1536 1537 /* Invalidate entry in TLB0, update PTE. */ 1538 tlb0_flush_entry(va); 1539 pte->flags = 0; 1540 pte->rpn = 0; 1541 1542 tlb_miss_unlock(); 1543 mtx_unlock_spin(&tlbivax_mutex); 1544 } 1545 1546 /* 1547 * Initialize pmap associated with process 0. 1548 */ 1549 static void 1550 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1551 { 1552 1553 PMAP_LOCK_INIT(pmap); 1554 mmu_booke_pinit(mmu, pmap); 1555 PCPU_SET(curpmap, pmap); 1556 } 1557 1558 /* 1559 * Initialize a preallocated and zeroed pmap structure, 1560 * such as one in a vmspace structure. 1561 */ 1562 static void 1563 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1564 { 1565 int i; 1566 1567 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1568 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1569 1570 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1571 1572 for (i = 0; i < MAXCPU; i++) 1573 pmap->pm_tid[i] = TID_NONE; 1574 CPU_ZERO(&kernel_pmap->pm_active); 1575 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1576 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1577 TAILQ_INIT(&pmap->pm_ptbl_list); 1578 } 1579 1580 /* 1581 * Release any resources held by the given physical map. 1582 * Called when a pmap initialized by mmu_booke_pinit is being released. 1583 * Should only be called if the map contains no valid mappings. 1584 */ 1585 static void 1586 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1587 { 1588 1589 KASSERT(pmap->pm_stats.resident_count == 0, 1590 ("pmap_release: pmap resident count %ld != 0", 1591 pmap->pm_stats.resident_count)); 1592 } 1593 1594 /* 1595 * Insert the given physical page at the specified virtual address in the 1596 * target physical map with the protection requested. If specified the page 1597 * will be wired down. 1598 */ 1599 static int 1600 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1601 vm_prot_t prot, u_int flags, int8_t psind) 1602 { 1603 int error; 1604 1605 rw_wlock(&pvh_global_lock); 1606 PMAP_LOCK(pmap); 1607 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1608 rw_wunlock(&pvh_global_lock); 1609 PMAP_UNLOCK(pmap); 1610 return (error); 1611 } 1612 1613 static int 1614 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1615 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1616 { 1617 pte_t *pte; 1618 vm_paddr_t pa; 1619 uint32_t flags; 1620 int error, su, sync; 1621 1622 pa = VM_PAGE_TO_PHYS(m); 1623 su = (pmap == kernel_pmap); 1624 sync = 0; 1625 1626 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1627 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1628 // (u_int32_t)pmap, su, pmap->pm_tid, 1629 // (u_int32_t)m, va, pa, prot, flags); 1630 1631 if (su) { 1632 KASSERT(((va >= virtual_avail) && 1633 (va <= VM_MAX_KERNEL_ADDRESS)), 1634 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1635 } else { 1636 KASSERT((va <= VM_MAXUSER_ADDRESS), 1637 ("mmu_booke_enter_locked: user pmap, non user va")); 1638 } 1639 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1640 VM_OBJECT_ASSERT_LOCKED(m->object); 1641 1642 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1643 1644 /* 1645 * If there is an existing mapping, and the physical address has not 1646 * changed, must be protection or wiring change. 1647 */ 1648 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1649 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1650 1651 /* 1652 * Before actually updating pte->flags we calculate and 1653 * prepare its new value in a helper var. 1654 */ 1655 flags = pte->flags; 1656 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1657 1658 /* Wiring change, just update stats. */ 1659 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1660 if (!PTE_ISWIRED(pte)) { 1661 flags |= PTE_WIRED; 1662 pmap->pm_stats.wired_count++; 1663 } 1664 } else { 1665 if (PTE_ISWIRED(pte)) { 1666 flags &= ~PTE_WIRED; 1667 pmap->pm_stats.wired_count--; 1668 } 1669 } 1670 1671 if (prot & VM_PROT_WRITE) { 1672 /* Add write permissions. */ 1673 flags |= PTE_SW; 1674 if (!su) 1675 flags |= PTE_UW; 1676 1677 if ((flags & PTE_MANAGED) != 0) 1678 vm_page_aflag_set(m, PGA_WRITEABLE); 1679 } else { 1680 /* Handle modified pages, sense modify status. */ 1681 1682 /* 1683 * The PTE_MODIFIED flag could be set by underlying 1684 * TLB misses since we last read it (above), possibly 1685 * other CPUs could update it so we check in the PTE 1686 * directly rather than rely on that saved local flags 1687 * copy. 1688 */ 1689 if (PTE_ISMODIFIED(pte)) 1690 vm_page_dirty(m); 1691 } 1692 1693 if (prot & VM_PROT_EXECUTE) { 1694 flags |= PTE_SX; 1695 if (!su) 1696 flags |= PTE_UX; 1697 1698 /* 1699 * Check existing flags for execute permissions: if we 1700 * are turning execute permissions on, icache should 1701 * be flushed. 1702 */ 1703 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1704 sync++; 1705 } 1706 1707 flags &= ~PTE_REFERENCED; 1708 1709 /* 1710 * The new flags value is all calculated -- only now actually 1711 * update the PTE. 1712 */ 1713 mtx_lock_spin(&tlbivax_mutex); 1714 tlb_miss_lock(); 1715 1716 tlb0_flush_entry(va); 1717 pte->flags = flags; 1718 1719 tlb_miss_unlock(); 1720 mtx_unlock_spin(&tlbivax_mutex); 1721 1722 } else { 1723 /* 1724 * If there is an existing mapping, but it's for a different 1725 * physical address, pte_enter() will delete the old mapping. 1726 */ 1727 //if ((pte != NULL) && PTE_ISVALID(pte)) 1728 // debugf("mmu_booke_enter_locked: replace\n"); 1729 //else 1730 // debugf("mmu_booke_enter_locked: new\n"); 1731 1732 /* Now set up the flags and install the new mapping. */ 1733 flags = (PTE_SR | PTE_VALID); 1734 flags |= PTE_M; 1735 1736 if (!su) 1737 flags |= PTE_UR; 1738 1739 if (prot & VM_PROT_WRITE) { 1740 flags |= PTE_SW; 1741 if (!su) 1742 flags |= PTE_UW; 1743 1744 if ((m->oflags & VPO_UNMANAGED) == 0) 1745 vm_page_aflag_set(m, PGA_WRITEABLE); 1746 } 1747 1748 if (prot & VM_PROT_EXECUTE) { 1749 flags |= PTE_SX; 1750 if (!su) 1751 flags |= PTE_UX; 1752 } 1753 1754 /* If its wired update stats. */ 1755 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1756 flags |= PTE_WIRED; 1757 1758 error = pte_enter(mmu, pmap, m, va, flags, 1759 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1760 if (error != 0) 1761 return (KERN_RESOURCE_SHORTAGE); 1762 1763 if ((flags & PMAP_ENTER_WIRED) != 0) 1764 pmap->pm_stats.wired_count++; 1765 1766 /* Flush the real memory from the instruction cache. */ 1767 if (prot & VM_PROT_EXECUTE) 1768 sync++; 1769 } 1770 1771 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1772 __syncicache((void *)va, PAGE_SIZE); 1773 sync = 0; 1774 } 1775 1776 return (KERN_SUCCESS); 1777 } 1778 1779 /* 1780 * Maps a sequence of resident pages belonging to the same object. 1781 * The sequence begins with the given page m_start. This page is 1782 * mapped at the given virtual address start. Each subsequent page is 1783 * mapped at a virtual address that is offset from start by the same 1784 * amount as the page is offset from m_start within the object. The 1785 * last page in the sequence is the page with the largest offset from 1786 * m_start that can be mapped at a virtual address less than the given 1787 * virtual address end. Not every virtual page between start and end 1788 * is mapped; only those for which a resident page exists with the 1789 * corresponding offset from m_start are mapped. 1790 */ 1791 static void 1792 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1793 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1794 { 1795 vm_page_t m; 1796 vm_pindex_t diff, psize; 1797 1798 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1799 1800 psize = atop(end - start); 1801 m = m_start; 1802 rw_wlock(&pvh_global_lock); 1803 PMAP_LOCK(pmap); 1804 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1805 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1806 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1807 PMAP_ENTER_NOSLEEP, 0); 1808 m = TAILQ_NEXT(m, listq); 1809 } 1810 rw_wunlock(&pvh_global_lock); 1811 PMAP_UNLOCK(pmap); 1812 } 1813 1814 static void 1815 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1816 vm_prot_t prot) 1817 { 1818 1819 rw_wlock(&pvh_global_lock); 1820 PMAP_LOCK(pmap); 1821 mmu_booke_enter_locked(mmu, pmap, va, m, 1822 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1823 0); 1824 rw_wunlock(&pvh_global_lock); 1825 PMAP_UNLOCK(pmap); 1826 } 1827 1828 /* 1829 * Remove the given range of addresses from the specified map. 1830 * 1831 * It is assumed that the start and end are properly rounded to the page size. 1832 */ 1833 static void 1834 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1835 { 1836 pte_t *pte; 1837 uint8_t hold_flag; 1838 1839 int su = (pmap == kernel_pmap); 1840 1841 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1842 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1843 1844 if (su) { 1845 KASSERT(((va >= virtual_avail) && 1846 (va <= VM_MAX_KERNEL_ADDRESS)), 1847 ("mmu_booke_remove: kernel pmap, non kernel va")); 1848 } else { 1849 KASSERT((va <= VM_MAXUSER_ADDRESS), 1850 ("mmu_booke_remove: user pmap, non user va")); 1851 } 1852 1853 if (PMAP_REMOVE_DONE(pmap)) { 1854 //debugf("mmu_booke_remove: e (empty)\n"); 1855 return; 1856 } 1857 1858 hold_flag = PTBL_HOLD_FLAG(pmap); 1859 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1860 1861 rw_wlock(&pvh_global_lock); 1862 PMAP_LOCK(pmap); 1863 for (; va < endva; va += PAGE_SIZE) { 1864 pte = pte_find(mmu, pmap, va); 1865 if ((pte != NULL) && PTE_ISVALID(pte)) 1866 pte_remove(mmu, pmap, va, hold_flag); 1867 } 1868 PMAP_UNLOCK(pmap); 1869 rw_wunlock(&pvh_global_lock); 1870 1871 //debugf("mmu_booke_remove: e\n"); 1872 } 1873 1874 /* 1875 * Remove physical page from all pmaps in which it resides. 1876 */ 1877 static void 1878 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1879 { 1880 pv_entry_t pv, pvn; 1881 uint8_t hold_flag; 1882 1883 rw_wlock(&pvh_global_lock); 1884 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1885 pvn = TAILQ_NEXT(pv, pv_link); 1886 1887 PMAP_LOCK(pv->pv_pmap); 1888 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1889 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1890 PMAP_UNLOCK(pv->pv_pmap); 1891 } 1892 vm_page_aflag_clear(m, PGA_WRITEABLE); 1893 rw_wunlock(&pvh_global_lock); 1894 } 1895 1896 /* 1897 * Map a range of physical addresses into kernel virtual address space. 1898 */ 1899 static vm_offset_t 1900 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1901 vm_paddr_t pa_end, int prot) 1902 { 1903 vm_offset_t sva = *virt; 1904 vm_offset_t va = sva; 1905 1906 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1907 // sva, pa_start, pa_end); 1908 1909 while (pa_start < pa_end) { 1910 mmu_booke_kenter(mmu, va, pa_start); 1911 va += PAGE_SIZE; 1912 pa_start += PAGE_SIZE; 1913 } 1914 *virt = va; 1915 1916 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1917 return (sva); 1918 } 1919 1920 /* 1921 * The pmap must be activated before it's address space can be accessed in any 1922 * way. 1923 */ 1924 static void 1925 mmu_booke_activate(mmu_t mmu, struct thread *td) 1926 { 1927 pmap_t pmap; 1928 u_int cpuid; 1929 1930 pmap = &td->td_proc->p_vmspace->vm_pmap; 1931 1932 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1933 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1934 1935 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1936 1937 sched_pin(); 1938 1939 cpuid = PCPU_GET(cpuid); 1940 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1941 PCPU_SET(curpmap, pmap); 1942 1943 if (pmap->pm_tid[cpuid] == TID_NONE) 1944 tid_alloc(pmap); 1945 1946 /* Load PID0 register with pmap tid value. */ 1947 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1948 __asm __volatile("isync"); 1949 1950 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1951 1952 sched_unpin(); 1953 1954 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1955 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1956 } 1957 1958 /* 1959 * Deactivate the specified process's address space. 1960 */ 1961 static void 1962 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1963 { 1964 pmap_t pmap; 1965 1966 pmap = &td->td_proc->p_vmspace->vm_pmap; 1967 1968 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1969 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1970 1971 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 1972 1973 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1974 PCPU_SET(curpmap, NULL); 1975 } 1976 1977 /* 1978 * Copy the range specified by src_addr/len 1979 * from the source map to the range dst_addr/len 1980 * in the destination map. 1981 * 1982 * This routine is only advisory and need not do anything. 1983 */ 1984 static void 1985 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1986 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1987 { 1988 1989 } 1990 1991 /* 1992 * Set the physical protection on the specified range of this map as requested. 1993 */ 1994 static void 1995 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1996 vm_prot_t prot) 1997 { 1998 vm_offset_t va; 1999 vm_page_t m; 2000 pte_t *pte; 2001 2002 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2003 mmu_booke_remove(mmu, pmap, sva, eva); 2004 return; 2005 } 2006 2007 if (prot & VM_PROT_WRITE) 2008 return; 2009 2010 PMAP_LOCK(pmap); 2011 for (va = sva; va < eva; va += PAGE_SIZE) { 2012 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2013 if (PTE_ISVALID(pte)) { 2014 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2015 2016 mtx_lock_spin(&tlbivax_mutex); 2017 tlb_miss_lock(); 2018 2019 /* Handle modified pages. */ 2020 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2021 vm_page_dirty(m); 2022 2023 tlb0_flush_entry(va); 2024 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2025 2026 tlb_miss_unlock(); 2027 mtx_unlock_spin(&tlbivax_mutex); 2028 } 2029 } 2030 } 2031 PMAP_UNLOCK(pmap); 2032 } 2033 2034 /* 2035 * Clear the write and modified bits in each of the given page's mappings. 2036 */ 2037 static void 2038 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2039 { 2040 pv_entry_t pv; 2041 pte_t *pte; 2042 2043 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2044 ("mmu_booke_remove_write: page %p is not managed", m)); 2045 2046 /* 2047 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2048 * set by another thread while the object is locked. Thus, 2049 * if PGA_WRITEABLE is clear, no page table entries need updating. 2050 */ 2051 VM_OBJECT_ASSERT_WLOCKED(m->object); 2052 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2053 return; 2054 rw_wlock(&pvh_global_lock); 2055 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2056 PMAP_LOCK(pv->pv_pmap); 2057 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2058 if (PTE_ISVALID(pte)) { 2059 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2060 2061 mtx_lock_spin(&tlbivax_mutex); 2062 tlb_miss_lock(); 2063 2064 /* Handle modified pages. */ 2065 if (PTE_ISMODIFIED(pte)) 2066 vm_page_dirty(m); 2067 2068 /* Flush mapping from TLB0. */ 2069 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2070 2071 tlb_miss_unlock(); 2072 mtx_unlock_spin(&tlbivax_mutex); 2073 } 2074 } 2075 PMAP_UNLOCK(pv->pv_pmap); 2076 } 2077 vm_page_aflag_clear(m, PGA_WRITEABLE); 2078 rw_wunlock(&pvh_global_lock); 2079 } 2080 2081 static void 2082 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2083 { 2084 pte_t *pte; 2085 pmap_t pmap; 2086 vm_page_t m; 2087 vm_offset_t addr; 2088 vm_paddr_t pa = 0; 2089 int active, valid; 2090 2091 va = trunc_page(va); 2092 sz = round_page(sz); 2093 2094 rw_wlock(&pvh_global_lock); 2095 pmap = PCPU_GET(curpmap); 2096 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2097 while (sz > 0) { 2098 PMAP_LOCK(pm); 2099 pte = pte_find(mmu, pm, va); 2100 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2101 if (valid) 2102 pa = PTE_PA(pte); 2103 PMAP_UNLOCK(pm); 2104 if (valid) { 2105 if (!active) { 2106 /* Create a mapping in the active pmap. */ 2107 addr = 0; 2108 m = PHYS_TO_VM_PAGE(pa); 2109 PMAP_LOCK(pmap); 2110 pte_enter(mmu, pmap, m, addr, 2111 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2112 __syncicache((void *)addr, PAGE_SIZE); 2113 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2114 PMAP_UNLOCK(pmap); 2115 } else 2116 __syncicache((void *)va, PAGE_SIZE); 2117 } 2118 va += PAGE_SIZE; 2119 sz -= PAGE_SIZE; 2120 } 2121 rw_wunlock(&pvh_global_lock); 2122 } 2123 2124 /* 2125 * Atomically extract and hold the physical page with the given 2126 * pmap and virtual address pair if that mapping permits the given 2127 * protection. 2128 */ 2129 static vm_page_t 2130 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2131 vm_prot_t prot) 2132 { 2133 pte_t *pte; 2134 vm_page_t m; 2135 uint32_t pte_wbit; 2136 vm_paddr_t pa; 2137 2138 m = NULL; 2139 pa = 0; 2140 PMAP_LOCK(pmap); 2141 retry: 2142 pte = pte_find(mmu, pmap, va); 2143 if ((pte != NULL) && PTE_ISVALID(pte)) { 2144 if (pmap == kernel_pmap) 2145 pte_wbit = PTE_SW; 2146 else 2147 pte_wbit = PTE_UW; 2148 2149 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2150 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2151 goto retry; 2152 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2153 vm_page_hold(m); 2154 } 2155 } 2156 2157 PA_UNLOCK_COND(pa); 2158 PMAP_UNLOCK(pmap); 2159 return (m); 2160 } 2161 2162 /* 2163 * Initialize a vm_page's machine-dependent fields. 2164 */ 2165 static void 2166 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2167 { 2168 2169 TAILQ_INIT(&m->md.pv_list); 2170 } 2171 2172 /* 2173 * mmu_booke_zero_page_area zeros the specified hardware page by 2174 * mapping it into virtual memory and using bzero to clear 2175 * its contents. 2176 * 2177 * off and size must reside within a single page. 2178 */ 2179 static void 2180 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2181 { 2182 vm_offset_t va; 2183 2184 /* XXX KASSERT off and size are within a single page? */ 2185 2186 mtx_lock(&zero_page_mutex); 2187 va = zero_page_va; 2188 2189 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2190 bzero((caddr_t)va + off, size); 2191 mmu_booke_kremove(mmu, va); 2192 2193 mtx_unlock(&zero_page_mutex); 2194 } 2195 2196 /* 2197 * mmu_booke_zero_page zeros the specified hardware page. 2198 */ 2199 static void 2200 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2201 { 2202 2203 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2204 } 2205 2206 /* 2207 * mmu_booke_copy_page copies the specified (machine independent) page by 2208 * mapping the page into virtual memory and using memcopy to copy the page, 2209 * one machine dependent page at a time. 2210 */ 2211 static void 2212 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2213 { 2214 vm_offset_t sva, dva; 2215 2216 sva = copy_page_src_va; 2217 dva = copy_page_dst_va; 2218 2219 mtx_lock(©_page_mutex); 2220 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2221 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2222 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2223 mmu_booke_kremove(mmu, dva); 2224 mmu_booke_kremove(mmu, sva); 2225 mtx_unlock(©_page_mutex); 2226 } 2227 2228 static inline void 2229 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2230 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2231 { 2232 void *a_cp, *b_cp; 2233 vm_offset_t a_pg_offset, b_pg_offset; 2234 int cnt; 2235 2236 mtx_lock(©_page_mutex); 2237 while (xfersize > 0) { 2238 a_pg_offset = a_offset & PAGE_MASK; 2239 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2240 mmu_booke_kenter(mmu, copy_page_src_va, 2241 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2242 a_cp = (char *)copy_page_src_va + a_pg_offset; 2243 b_pg_offset = b_offset & PAGE_MASK; 2244 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2245 mmu_booke_kenter(mmu, copy_page_dst_va, 2246 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2247 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2248 bcopy(a_cp, b_cp, cnt); 2249 mmu_booke_kremove(mmu, copy_page_dst_va); 2250 mmu_booke_kremove(mmu, copy_page_src_va); 2251 a_offset += cnt; 2252 b_offset += cnt; 2253 xfersize -= cnt; 2254 } 2255 mtx_unlock(©_page_mutex); 2256 } 2257 2258 /* 2259 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2260 * into virtual memory and using bzero to clear its contents. This is intended 2261 * to be called from the vm_pagezero process only and outside of Giant. No 2262 * lock is required. 2263 */ 2264 static void 2265 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2266 { 2267 vm_offset_t va; 2268 2269 va = zero_page_idle_va; 2270 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2271 bzero((caddr_t)va, PAGE_SIZE); 2272 mmu_booke_kremove(mmu, va); 2273 } 2274 2275 /* 2276 * Return whether or not the specified physical page was modified 2277 * in any of physical maps. 2278 */ 2279 static boolean_t 2280 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2281 { 2282 pte_t *pte; 2283 pv_entry_t pv; 2284 boolean_t rv; 2285 2286 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2287 ("mmu_booke_is_modified: page %p is not managed", m)); 2288 rv = FALSE; 2289 2290 /* 2291 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2292 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2293 * is clear, no PTEs can be modified. 2294 */ 2295 VM_OBJECT_ASSERT_WLOCKED(m->object); 2296 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2297 return (rv); 2298 rw_wlock(&pvh_global_lock); 2299 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2300 PMAP_LOCK(pv->pv_pmap); 2301 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2302 PTE_ISVALID(pte)) { 2303 if (PTE_ISMODIFIED(pte)) 2304 rv = TRUE; 2305 } 2306 PMAP_UNLOCK(pv->pv_pmap); 2307 if (rv) 2308 break; 2309 } 2310 rw_wunlock(&pvh_global_lock); 2311 return (rv); 2312 } 2313 2314 /* 2315 * Return whether or not the specified virtual address is eligible 2316 * for prefault. 2317 */ 2318 static boolean_t 2319 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2320 { 2321 2322 return (FALSE); 2323 } 2324 2325 /* 2326 * Return whether or not the specified physical page was referenced 2327 * in any physical maps. 2328 */ 2329 static boolean_t 2330 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2331 { 2332 pte_t *pte; 2333 pv_entry_t pv; 2334 boolean_t rv; 2335 2336 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2337 ("mmu_booke_is_referenced: page %p is not managed", m)); 2338 rv = FALSE; 2339 rw_wlock(&pvh_global_lock); 2340 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2341 PMAP_LOCK(pv->pv_pmap); 2342 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2343 PTE_ISVALID(pte)) { 2344 if (PTE_ISREFERENCED(pte)) 2345 rv = TRUE; 2346 } 2347 PMAP_UNLOCK(pv->pv_pmap); 2348 if (rv) 2349 break; 2350 } 2351 rw_wunlock(&pvh_global_lock); 2352 return (rv); 2353 } 2354 2355 /* 2356 * Clear the modify bits on the specified physical page. 2357 */ 2358 static void 2359 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2360 { 2361 pte_t *pte; 2362 pv_entry_t pv; 2363 2364 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2365 ("mmu_booke_clear_modify: page %p is not managed", m)); 2366 VM_OBJECT_ASSERT_WLOCKED(m->object); 2367 KASSERT(!vm_page_xbusied(m), 2368 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2369 2370 /* 2371 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2372 * If the object containing the page is locked and the page is not 2373 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2374 */ 2375 if ((m->aflags & PGA_WRITEABLE) == 0) 2376 return; 2377 rw_wlock(&pvh_global_lock); 2378 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2379 PMAP_LOCK(pv->pv_pmap); 2380 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2381 PTE_ISVALID(pte)) { 2382 mtx_lock_spin(&tlbivax_mutex); 2383 tlb_miss_lock(); 2384 2385 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2386 tlb0_flush_entry(pv->pv_va); 2387 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2388 PTE_REFERENCED); 2389 } 2390 2391 tlb_miss_unlock(); 2392 mtx_unlock_spin(&tlbivax_mutex); 2393 } 2394 PMAP_UNLOCK(pv->pv_pmap); 2395 } 2396 rw_wunlock(&pvh_global_lock); 2397 } 2398 2399 /* 2400 * Return a count of reference bits for a page, clearing those bits. 2401 * It is not necessary for every reference bit to be cleared, but it 2402 * is necessary that 0 only be returned when there are truly no 2403 * reference bits set. 2404 * 2405 * XXX: The exact number of bits to check and clear is a matter that 2406 * should be tested and standardized at some point in the future for 2407 * optimal aging of shared pages. 2408 */ 2409 static int 2410 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2411 { 2412 pte_t *pte; 2413 pv_entry_t pv; 2414 int count; 2415 2416 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2417 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2418 count = 0; 2419 rw_wlock(&pvh_global_lock); 2420 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2421 PMAP_LOCK(pv->pv_pmap); 2422 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2423 PTE_ISVALID(pte)) { 2424 if (PTE_ISREFERENCED(pte)) { 2425 mtx_lock_spin(&tlbivax_mutex); 2426 tlb_miss_lock(); 2427 2428 tlb0_flush_entry(pv->pv_va); 2429 pte->flags &= ~PTE_REFERENCED; 2430 2431 tlb_miss_unlock(); 2432 mtx_unlock_spin(&tlbivax_mutex); 2433 2434 if (++count > 4) { 2435 PMAP_UNLOCK(pv->pv_pmap); 2436 break; 2437 } 2438 } 2439 } 2440 PMAP_UNLOCK(pv->pv_pmap); 2441 } 2442 rw_wunlock(&pvh_global_lock); 2443 return (count); 2444 } 2445 2446 /* 2447 * Clear the wired attribute from the mappings for the specified range of 2448 * addresses in the given pmap. Every valid mapping within that range must 2449 * have the wired attribute set. In contrast, invalid mappings cannot have 2450 * the wired attribute set, so they are ignored. 2451 * 2452 * The wired attribute of the page table entry is not a hardware feature, so 2453 * there is no need to invalidate any TLB entries. 2454 */ 2455 static void 2456 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2457 { 2458 vm_offset_t va; 2459 pte_t *pte; 2460 2461 PMAP_LOCK(pmap); 2462 for (va = sva; va < eva; va += PAGE_SIZE) { 2463 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2464 PTE_ISVALID(pte)) { 2465 if (!PTE_ISWIRED(pte)) 2466 panic("mmu_booke_unwire: pte %p isn't wired", 2467 pte); 2468 pte->flags &= ~PTE_WIRED; 2469 pmap->pm_stats.wired_count--; 2470 } 2471 } 2472 PMAP_UNLOCK(pmap); 2473 2474 } 2475 2476 /* 2477 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2478 * page. This count may be changed upwards or downwards in the future; it is 2479 * only necessary that true be returned for a small subset of pmaps for proper 2480 * page aging. 2481 */ 2482 static boolean_t 2483 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2484 { 2485 pv_entry_t pv; 2486 int loops; 2487 boolean_t rv; 2488 2489 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2490 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2491 loops = 0; 2492 rv = FALSE; 2493 rw_wlock(&pvh_global_lock); 2494 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2495 if (pv->pv_pmap == pmap) { 2496 rv = TRUE; 2497 break; 2498 } 2499 if (++loops >= 16) 2500 break; 2501 } 2502 rw_wunlock(&pvh_global_lock); 2503 return (rv); 2504 } 2505 2506 /* 2507 * Return the number of managed mappings to the given physical page that are 2508 * wired. 2509 */ 2510 static int 2511 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2512 { 2513 pv_entry_t pv; 2514 pte_t *pte; 2515 int count = 0; 2516 2517 if ((m->oflags & VPO_UNMANAGED) != 0) 2518 return (count); 2519 rw_wlock(&pvh_global_lock); 2520 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2521 PMAP_LOCK(pv->pv_pmap); 2522 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2523 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2524 count++; 2525 PMAP_UNLOCK(pv->pv_pmap); 2526 } 2527 rw_wunlock(&pvh_global_lock); 2528 return (count); 2529 } 2530 2531 static int 2532 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2533 { 2534 int i; 2535 vm_offset_t va; 2536 2537 /* 2538 * This currently does not work for entries that 2539 * overlap TLB1 entries. 2540 */ 2541 for (i = 0; i < tlb1_idx; i ++) { 2542 if (tlb1_iomapped(i, pa, size, &va) == 0) 2543 return (0); 2544 } 2545 2546 return (EFAULT); 2547 } 2548 2549 void 2550 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2551 { 2552 vm_paddr_t ppa; 2553 vm_offset_t ofs; 2554 vm_size_t gran; 2555 2556 /* Minidumps are based on virtual memory addresses. */ 2557 if (do_minidump) { 2558 *va = (void *)pa; 2559 return; 2560 } 2561 2562 /* Raw physical memory dumps don't have a virtual address. */ 2563 /* We always map a 256MB page at 256M. */ 2564 gran = 256 * 1024 * 1024; 2565 ppa = pa & ~(gran - 1); 2566 ofs = pa - ppa; 2567 *va = (void *)gran; 2568 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2569 2570 if (sz > (gran - ofs)) 2571 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2572 _TLB_ENTRY_IO); 2573 } 2574 2575 void 2576 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2577 { 2578 vm_paddr_t ppa; 2579 vm_offset_t ofs; 2580 vm_size_t gran; 2581 2582 /* Minidumps are based on virtual memory addresses. */ 2583 /* Nothing to do... */ 2584 if (do_minidump) 2585 return; 2586 2587 /* Raw physical memory dumps don't have a virtual address. */ 2588 tlb1_idx--; 2589 tlb1[tlb1_idx].mas1 = 0; 2590 tlb1[tlb1_idx].mas2 = 0; 2591 tlb1[tlb1_idx].mas3 = 0; 2592 tlb1_write_entry(tlb1_idx); 2593 2594 gran = 256 * 1024 * 1024; 2595 ppa = pa & ~(gran - 1); 2596 ofs = pa - ppa; 2597 if (sz > (gran - ofs)) { 2598 tlb1_idx--; 2599 tlb1[tlb1_idx].mas1 = 0; 2600 tlb1[tlb1_idx].mas2 = 0; 2601 tlb1[tlb1_idx].mas3 = 0; 2602 tlb1_write_entry(tlb1_idx); 2603 } 2604 } 2605 2606 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2607 2608 void 2609 mmu_booke_scan_init(mmu_t mmu) 2610 { 2611 vm_offset_t va; 2612 pte_t *pte; 2613 int i; 2614 2615 if (!do_minidump) { 2616 /* Initialize phys. segments for dumpsys(). */ 2617 memset(&dump_map, 0, sizeof(dump_map)); 2618 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2619 &availmem_regions_sz); 2620 for (i = 0; i < physmem_regions_sz; i++) { 2621 dump_map[i].pa_start = physmem_regions[i].mr_start; 2622 dump_map[i].pa_size = physmem_regions[i].mr_size; 2623 } 2624 return; 2625 } 2626 2627 /* Virtual segments for minidumps: */ 2628 memset(&dump_map, 0, sizeof(dump_map)); 2629 2630 /* 1st: kernel .data and .bss. */ 2631 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2632 dump_map[0].pa_size = 2633 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2634 2635 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2636 dump_map[1].pa_start = data_start; 2637 dump_map[1].pa_size = data_end - data_start; 2638 2639 /* 3rd: kernel VM. */ 2640 va = dump_map[1].pa_start + dump_map[1].pa_size; 2641 /* Find start of next chunk (from va). */ 2642 while (va < virtual_end) { 2643 /* Don't dump the buffer cache. */ 2644 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2645 va = kmi.buffer_eva; 2646 continue; 2647 } 2648 pte = pte_find(mmu, kernel_pmap, va); 2649 if (pte != NULL && PTE_ISVALID(pte)) 2650 break; 2651 va += PAGE_SIZE; 2652 } 2653 if (va < virtual_end) { 2654 dump_map[2].pa_start = va; 2655 va += PAGE_SIZE; 2656 /* Find last page in chunk. */ 2657 while (va < virtual_end) { 2658 /* Don't run into the buffer cache. */ 2659 if (va == kmi.buffer_sva) 2660 break; 2661 pte = pte_find(mmu, kernel_pmap, va); 2662 if (pte == NULL || !PTE_ISVALID(pte)) 2663 break; 2664 va += PAGE_SIZE; 2665 } 2666 dump_map[2].pa_size = va - dump_map[2].pa_start; 2667 } 2668 } 2669 2670 /* 2671 * Map a set of physical memory pages into the kernel virtual address space. 2672 * Return a pointer to where it is mapped. This routine is intended to be used 2673 * for mapping device memory, NOT real memory. 2674 */ 2675 static void * 2676 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2677 { 2678 2679 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2680 } 2681 2682 static void * 2683 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2684 { 2685 void *res; 2686 uintptr_t va; 2687 vm_size_t sz; 2688 int i; 2689 2690 /* 2691 * Check if this is premapped in TLB1. Note: this should probably also 2692 * check whether a sequence of TLB1 entries exist that match the 2693 * requirement, but now only checks the easy case. 2694 */ 2695 if (ma == VM_MEMATTR_DEFAULT) { 2696 for (i = 0; i < tlb1_idx; i++) { 2697 if (!(tlb1[i].mas1 & MAS1_VALID)) 2698 continue; 2699 if (pa >= tlb1[i].phys && 2700 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2701 return (void *)(tlb1[i].virt + 2702 (pa - tlb1[i].phys)); 2703 } 2704 } 2705 2706 size = roundup(size, PAGE_SIZE); 2707 2708 /* 2709 * We leave a hole for device direct mapping between the maximum user 2710 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2711 * devices are in there, just map them 1:1. If not, map them to the 2712 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2713 * addresses should be pulled from an allocator, but since we do not 2714 * ever free TLB1 entries, it is safe just to increment a counter. 2715 * Note that there isn't a lot of address space here (128 MB) and it 2716 * is not at all difficult to imagine running out, since that is a 4:1 2717 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2718 * mapped there. 2719 */ 2720 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2721 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2722 va = pa; 2723 else 2724 va = atomic_fetchadd_int(&tlb1_map_base, size); 2725 res = (void *)va; 2726 2727 do { 2728 sz = 1 << (ilog2(size) & ~1); 2729 if (bootverbose) 2730 printf("Wiring VA=%x to PA=%x (size=%x), " 2731 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2732 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2733 size -= sz; 2734 pa += sz; 2735 va += sz; 2736 } while (size > 0); 2737 2738 return (res); 2739 } 2740 2741 /* 2742 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2743 */ 2744 static void 2745 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2746 { 2747 #ifdef SUPPORTS_SHRINKING_TLB1 2748 vm_offset_t base, offset; 2749 2750 /* 2751 * Unmap only if this is inside kernel virtual space. 2752 */ 2753 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2754 base = trunc_page(va); 2755 offset = va & PAGE_MASK; 2756 size = roundup(offset + size, PAGE_SIZE); 2757 kva_free(base, size); 2758 } 2759 #endif 2760 } 2761 2762 /* 2763 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2764 * specified pmap. This eliminates the blast of soft faults on process startup 2765 * and immediately after an mmap. 2766 */ 2767 static void 2768 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2769 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2770 { 2771 2772 VM_OBJECT_ASSERT_WLOCKED(object); 2773 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2774 ("mmu_booke_object_init_pt: non-device object")); 2775 } 2776 2777 /* 2778 * Perform the pmap work for mincore. 2779 */ 2780 static int 2781 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2782 vm_paddr_t *locked_pa) 2783 { 2784 2785 /* XXX: this should be implemented at some point */ 2786 return (0); 2787 } 2788 2789 /**************************************************************************/ 2790 /* TID handling */ 2791 /**************************************************************************/ 2792 2793 /* 2794 * Allocate a TID. If necessary, steal one from someone else. 2795 * The new TID is flushed from the TLB before returning. 2796 */ 2797 static tlbtid_t 2798 tid_alloc(pmap_t pmap) 2799 { 2800 tlbtid_t tid; 2801 int thiscpu; 2802 2803 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2804 2805 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2806 2807 thiscpu = PCPU_GET(cpuid); 2808 2809 tid = PCPU_GET(tid_next); 2810 if (tid > TID_MAX) 2811 tid = TID_MIN; 2812 PCPU_SET(tid_next, tid + 1); 2813 2814 /* If we are stealing TID then clear the relevant pmap's field */ 2815 if (tidbusy[thiscpu][tid] != NULL) { 2816 2817 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2818 2819 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2820 2821 /* Flush all entries from TLB0 matching this TID. */ 2822 tid_flush(tid, tlb0_ways, tlb0_entries_per_way); 2823 } 2824 2825 tidbusy[thiscpu][tid] = pmap; 2826 pmap->pm_tid[thiscpu] = tid; 2827 __asm __volatile("msync; isync"); 2828 2829 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2830 PCPU_GET(tid_next)); 2831 2832 return (tid); 2833 } 2834 2835 /**************************************************************************/ 2836 /* TLB0 handling */ 2837 /**************************************************************************/ 2838 2839 static void 2840 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2841 uint32_t mas7) 2842 { 2843 int as; 2844 char desc[3]; 2845 tlbtid_t tid; 2846 vm_size_t size; 2847 unsigned int tsize; 2848 2849 desc[2] = '\0'; 2850 if (mas1 & MAS1_VALID) 2851 desc[0] = 'V'; 2852 else 2853 desc[0] = ' '; 2854 2855 if (mas1 & MAS1_IPROT) 2856 desc[1] = 'P'; 2857 else 2858 desc[1] = ' '; 2859 2860 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2861 tid = MAS1_GETTID(mas1); 2862 2863 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2864 size = 0; 2865 if (tsize) 2866 size = tsize2size(tsize); 2867 2868 debugf("%3d: (%s) [AS=%d] " 2869 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2870 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2871 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2872 } 2873 2874 /* Convert TLB0 va and way number to tlb0[] table index. */ 2875 static inline unsigned int 2876 tlb0_tableidx(vm_offset_t va, unsigned int way) 2877 { 2878 unsigned int idx; 2879 2880 idx = (way * TLB0_ENTRIES_PER_WAY); 2881 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2882 return (idx); 2883 } 2884 2885 /* 2886 * Invalidate TLB0 entry. 2887 */ 2888 static inline void 2889 tlb0_flush_entry(vm_offset_t va) 2890 { 2891 2892 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2893 2894 mtx_assert(&tlbivax_mutex, MA_OWNED); 2895 2896 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2897 __asm __volatile("isync; msync"); 2898 __asm __volatile("tlbsync; msync"); 2899 2900 CTR1(KTR_PMAP, "%s: e", __func__); 2901 } 2902 2903 /* Print out contents of the MAS registers for each TLB0 entry */ 2904 void 2905 tlb0_print_tlbentries(void) 2906 { 2907 uint32_t mas0, mas1, mas2, mas3, mas7; 2908 int entryidx, way, idx; 2909 2910 debugf("TLB0 entries:\n"); 2911 for (way = 0; way < TLB0_WAYS; way ++) 2912 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2913 2914 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2915 mtspr(SPR_MAS0, mas0); 2916 __asm __volatile("isync"); 2917 2918 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2919 mtspr(SPR_MAS2, mas2); 2920 2921 __asm __volatile("isync; tlbre"); 2922 2923 mas1 = mfspr(SPR_MAS1); 2924 mas2 = mfspr(SPR_MAS2); 2925 mas3 = mfspr(SPR_MAS3); 2926 mas7 = mfspr(SPR_MAS7); 2927 2928 idx = tlb0_tableidx(mas2, way); 2929 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2930 } 2931 } 2932 2933 /**************************************************************************/ 2934 /* TLB1 handling */ 2935 /**************************************************************************/ 2936 2937 /* 2938 * TLB1 mapping notes: 2939 * 2940 * TLB1[0] Kernel text and data. 2941 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2942 * windows, other devices mappings. 2943 */ 2944 2945 /* 2946 * Write given entry to TLB1 hardware. 2947 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2948 */ 2949 static void 2950 tlb1_write_entry(unsigned int idx) 2951 { 2952 uint32_t mas0, mas7; 2953 2954 //debugf("tlb1_write_entry: s\n"); 2955 2956 /* Clear high order RPN bits */ 2957 mas7 = 0; 2958 2959 /* Select entry */ 2960 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2961 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2962 2963 mtspr(SPR_MAS0, mas0); 2964 __asm __volatile("isync"); 2965 mtspr(SPR_MAS1, tlb1[idx].mas1); 2966 __asm __volatile("isync"); 2967 mtspr(SPR_MAS2, tlb1[idx].mas2); 2968 __asm __volatile("isync"); 2969 mtspr(SPR_MAS3, tlb1[idx].mas3); 2970 __asm __volatile("isync"); 2971 mtspr(SPR_MAS7, mas7); 2972 __asm __volatile("isync; tlbwe; isync; msync"); 2973 2974 //debugf("tlb1_write_entry: e\n"); 2975 } 2976 2977 /* 2978 * Return the largest uint value log such that 2^log <= num. 2979 */ 2980 static unsigned int 2981 ilog2(unsigned int num) 2982 { 2983 int lz; 2984 2985 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2986 return (31 - lz); 2987 } 2988 2989 /* 2990 * Convert TLB TSIZE value to mapped region size. 2991 */ 2992 static vm_size_t 2993 tsize2size(unsigned int tsize) 2994 { 2995 2996 /* 2997 * size = 4^tsize KB 2998 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2999 */ 3000 3001 return ((1 << (2 * tsize)) * 1024); 3002 } 3003 3004 /* 3005 * Convert region size (must be power of 4) to TLB TSIZE value. 3006 */ 3007 static unsigned int 3008 size2tsize(vm_size_t size) 3009 { 3010 3011 return (ilog2(size) / 2 - 5); 3012 } 3013 3014 /* 3015 * Register permanent kernel mapping in TLB1. 3016 * 3017 * Entries are created starting from index 0 (current free entry is 3018 * kept in tlb1_idx) and are not supposed to be invalidated. 3019 */ 3020 static int 3021 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3022 uint32_t flags) 3023 { 3024 uint32_t ts, tid; 3025 int tsize, index; 3026 3027 index = atomic_fetchadd_int(&tlb1_idx, 1); 3028 if (index >= TLB1_ENTRIES) { 3029 printf("tlb1_set_entry: TLB1 full!\n"); 3030 return (-1); 3031 } 3032 3033 /* Convert size to TSIZE */ 3034 tsize = size2tsize(size); 3035 3036 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3037 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3038 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3039 3040 /* 3041 * Atomicity is preserved by the atomic increment above since nothing 3042 * is ever removed from tlb1. 3043 */ 3044 3045 tlb1[index].phys = pa; 3046 tlb1[index].virt = va; 3047 tlb1[index].size = size; 3048 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3049 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3050 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3051 3052 /* Set supervisor RWX permission bits */ 3053 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3054 3055 tlb1_write_entry(index); 3056 3057 /* 3058 * XXX in general TLB1 updates should be propagated between CPUs, 3059 * since current design assumes to have the same TLB1 set-up on all 3060 * cores. 3061 */ 3062 return (0); 3063 } 3064 3065 /* 3066 * Map in contiguous RAM region into the TLB1 using maximum of 3067 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3068 * 3069 * If necessary round up last entry size and return total size 3070 * used by all allocated entries. 3071 */ 3072 vm_size_t 3073 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3074 { 3075 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3076 vm_size_t mapped, pgsz, base, mask; 3077 int idx, nents; 3078 3079 /* Round up to the next 1M */ 3080 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3081 3082 mapped = 0; 3083 idx = 0; 3084 base = va; 3085 pgsz = 64*1024*1024; 3086 while (mapped < size) { 3087 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3088 while (pgsz > (size - mapped)) 3089 pgsz >>= 2; 3090 pgs[idx++] = pgsz; 3091 mapped += pgsz; 3092 } 3093 3094 /* We under-map. Correct for this. */ 3095 if (mapped < size) { 3096 while (pgs[idx - 1] == pgsz) { 3097 idx--; 3098 mapped -= pgsz; 3099 } 3100 /* XXX We may increase beyond out starting point. */ 3101 pgsz <<= 2; 3102 pgs[idx++] = pgsz; 3103 mapped += pgsz; 3104 } 3105 } 3106 3107 nents = idx; 3108 mask = pgs[0] - 1; 3109 /* Align address to the boundary */ 3110 if (va & mask) { 3111 va = (va + mask) & ~mask; 3112 pa = (pa + mask) & ~mask; 3113 } 3114 3115 for (idx = 0; idx < nents; idx++) { 3116 pgsz = pgs[idx]; 3117 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3118 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3119 pa += pgsz; 3120 va += pgsz; 3121 } 3122 3123 mapped = (va - base); 3124 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3125 mapped, mapped - size); 3126 return (mapped); 3127 } 3128 3129 /* 3130 * TLB1 initialization routine, to be called after the very first 3131 * assembler level setup done in locore.S. 3132 */ 3133 void 3134 tlb1_init() 3135 { 3136 uint32_t mas0, mas1, mas2, mas3; 3137 uint32_t tsz; 3138 u_int i; 3139 3140 if (bootinfo != NULL && bootinfo[0] != 1) { 3141 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3142 } else 3143 tlb1_idx = 1; 3144 3145 /* The first entry/entries are used to map the kernel. */ 3146 for (i = 0; i < tlb1_idx; i++) { 3147 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3148 mtspr(SPR_MAS0, mas0); 3149 __asm __volatile("isync; tlbre"); 3150 3151 mas1 = mfspr(SPR_MAS1); 3152 if ((mas1 & MAS1_VALID) == 0) 3153 continue; 3154 3155 mas2 = mfspr(SPR_MAS2); 3156 mas3 = mfspr(SPR_MAS3); 3157 3158 tlb1[i].mas1 = mas1; 3159 tlb1[i].mas2 = mfspr(SPR_MAS2); 3160 tlb1[i].mas3 = mas3; 3161 tlb1[i].virt = mas2 & MAS2_EPN_MASK; 3162 tlb1[i].phys = mas3 & MAS3_RPN; 3163 3164 if (i == 0) 3165 kernload = tlb1[i].phys; 3166 3167 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3168 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0; 3169 kernsize += tlb1[i].size; 3170 } 3171 3172 #ifdef SMP 3173 bp_ntlb1s = tlb1_idx; 3174 #endif 3175 3176 /* Purge the remaining entries */ 3177 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3178 tlb1_write_entry(i); 3179 3180 /* Setup TLB miss defaults */ 3181 set_mas4_defaults(); 3182 } 3183 3184 vm_offset_t 3185 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3186 { 3187 vm_paddr_t pa_base; 3188 vm_offset_t va, sz; 3189 int i; 3190 3191 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3192 3193 for (i = 0; i < tlb1_idx; i++) { 3194 if (!(tlb1[i].mas1 & MAS1_VALID)) 3195 continue; 3196 if (pa >= tlb1[i].phys && (pa + size) <= 3197 (tlb1[i].phys + tlb1[i].size)) 3198 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3199 } 3200 3201 pa_base = trunc_page(pa); 3202 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3203 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3204 va = tlb1_map_base + (pa - pa_base); 3205 3206 do { 3207 sz = 1 << (ilog2(size) & ~1); 3208 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3209 size -= sz; 3210 pa_base += sz; 3211 tlb1_map_base += sz; 3212 } while (size > 0); 3213 3214 #ifdef SMP 3215 bp_ntlb1s = tlb1_idx; 3216 #endif 3217 3218 return (va); 3219 } 3220 3221 /* 3222 * Setup MAS4 defaults. 3223 * These values are loaded to MAS0-2 on a TLB miss. 3224 */ 3225 static void 3226 set_mas4_defaults(void) 3227 { 3228 uint32_t mas4; 3229 3230 /* Defaults: TLB0, PID0, TSIZED=4K */ 3231 mas4 = MAS4_TLBSELD0; 3232 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3233 #ifdef SMP 3234 mas4 |= MAS4_MD; 3235 #endif 3236 mtspr(SPR_MAS4, mas4); 3237 __asm __volatile("isync"); 3238 } 3239 3240 /* 3241 * Print out contents of the MAS registers for each TLB1 entry 3242 */ 3243 void 3244 tlb1_print_tlbentries(void) 3245 { 3246 uint32_t mas0, mas1, mas2, mas3, mas7; 3247 int i; 3248 3249 debugf("TLB1 entries:\n"); 3250 for (i = 0; i < TLB1_ENTRIES; i++) { 3251 3252 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3253 mtspr(SPR_MAS0, mas0); 3254 3255 __asm __volatile("isync; tlbre"); 3256 3257 mas1 = mfspr(SPR_MAS1); 3258 mas2 = mfspr(SPR_MAS2); 3259 mas3 = mfspr(SPR_MAS3); 3260 mas7 = mfspr(SPR_MAS7); 3261 3262 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3263 } 3264 } 3265 3266 /* 3267 * Print out contents of the in-ram tlb1 table. 3268 */ 3269 void 3270 tlb1_print_entries(void) 3271 { 3272 int i; 3273 3274 debugf("tlb1[] table entries:\n"); 3275 for (i = 0; i < TLB1_ENTRIES; i++) 3276 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3277 } 3278 3279 /* 3280 * Return 0 if the physical IO range is encompassed by one of the 3281 * the TLB1 entries, otherwise return related error code. 3282 */ 3283 static int 3284 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3285 { 3286 uint32_t prot; 3287 vm_paddr_t pa_start; 3288 vm_paddr_t pa_end; 3289 unsigned int entry_tsize; 3290 vm_size_t entry_size; 3291 3292 *va = (vm_offset_t)NULL; 3293 3294 /* Skip invalid entries */ 3295 if (!(tlb1[i].mas1 & MAS1_VALID)) 3296 return (EINVAL); 3297 3298 /* 3299 * The entry must be cache-inhibited, guarded, and r/w 3300 * so it can function as an i/o page 3301 */ 3302 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3303 if (prot != (MAS2_I | MAS2_G)) 3304 return (EPERM); 3305 3306 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3307 if (prot != (MAS3_SR | MAS3_SW)) 3308 return (EPERM); 3309 3310 /* The address should be within the entry range. */ 3311 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3312 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3313 3314 entry_size = tsize2size(entry_tsize); 3315 pa_start = tlb1[i].mas3 & MAS3_RPN; 3316 pa_end = pa_start + entry_size - 1; 3317 3318 if ((pa < pa_start) || ((pa + size) > pa_end)) 3319 return (ERANGE); 3320 3321 /* Return virtual address of this mapping. */ 3322 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3323 return (0); 3324 } 3325