1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #ifdef DEBUG 100 #define debugf(fmt, args...) printf(fmt, ##args) 101 #else 102 #define debugf(fmt, args...) 103 #endif 104 105 #define TODO panic("%s: not implemented", __func__); 106 107 extern unsigned char _etext[]; 108 extern unsigned char _end[]; 109 110 extern uint32_t *bootinfo; 111 112 #ifdef SMP 113 extern uint32_t bp_ntlb1s; 114 #endif 115 116 vm_paddr_t kernload; 117 vm_offset_t kernstart; 118 vm_size_t kernsize; 119 120 /* Message buffer and tables. */ 121 static vm_offset_t data_start; 122 static vm_size_t data_end; 123 124 /* Phys/avail memory regions. */ 125 static struct mem_region *availmem_regions; 126 static int availmem_regions_sz; 127 static struct mem_region *physmem_regions; 128 static int physmem_regions_sz; 129 130 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 131 static vm_offset_t zero_page_va; 132 static struct mtx zero_page_mutex; 133 134 static struct mtx tlbivax_mutex; 135 136 /* 137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 138 * by idle thred only, no lock required. 139 */ 140 static vm_offset_t zero_page_idle_va; 141 142 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 143 static vm_offset_t copy_page_src_va; 144 static vm_offset_t copy_page_dst_va; 145 static struct mtx copy_page_mutex; 146 147 /**************************************************************************/ 148 /* PMAP */ 149 /**************************************************************************/ 150 151 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 152 vm_prot_t, u_int flags, int8_t psind); 153 154 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 155 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 156 157 /* 158 * If user pmap is processed with mmu_booke_remove and the resident count 159 * drops to 0, there are no more pages to remove, so we need not continue. 160 */ 161 #define PMAP_REMOVE_DONE(pmap) \ 162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 163 164 extern int elf32_nxstack; 165 166 /**************************************************************************/ 167 /* TLB and TID handling */ 168 /**************************************************************************/ 169 170 /* Translation ID busy table */ 171 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 172 173 /* 174 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 175 * core revisions and should be read from h/w registers during early config. 176 */ 177 uint32_t tlb0_entries; 178 uint32_t tlb0_ways; 179 uint32_t tlb0_entries_per_way; 180 uint32_t tlb1_entries; 181 182 #define TLB0_ENTRIES (tlb0_entries) 183 #define TLB0_WAYS (tlb0_ways) 184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186 #define TLB1_ENTRIES (tlb1_entries) 187 #define TLB1_MAXENTRIES 64 188 189 /* In-ram copy of the TLB1 */ 190 static tlb_entry_t tlb1[TLB1_MAXENTRIES]; 191 192 /* Next free entry in the TLB1 */ 193 static unsigned int tlb1_idx; 194 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 195 196 static tlbtid_t tid_alloc(struct pmap *); 197 static void tid_flush(tlbtid_t tid); 198 199 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 200 201 static int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t); 202 static void tlb1_write_entry(unsigned int); 203 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 204 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 205 206 static vm_size_t tsize2size(unsigned int); 207 static unsigned int size2tsize(vm_size_t); 208 static unsigned int ilog2(unsigned int); 209 210 static void set_mas4_defaults(void); 211 212 static inline void tlb0_flush_entry(vm_offset_t); 213 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 214 215 /**************************************************************************/ 216 /* Page table management */ 217 /**************************************************************************/ 218 219 static struct rwlock_padalign pvh_global_lock; 220 221 /* Data for the pv entry allocation mechanism */ 222 static uma_zone_t pvzone; 223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227 #ifndef PMAP_SHPGPERPROC 228 #define PMAP_SHPGPERPROC 200 229 #endif 230 231 static void ptbl_init(void); 232 static struct ptbl_buf *ptbl_buf_alloc(void); 233 static void ptbl_buf_free(struct ptbl_buf *); 234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 237 static void ptbl_free(mmu_t, pmap_t, unsigned int); 238 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 245 static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, 246 vm_offset_t pdir); 247 248 static pv_entry_t pv_alloc(void); 249 static void pv_free(pv_entry_t); 250 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 251 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 252 253 static void booke_pmap_init_qpages(void); 254 255 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 256 #define PTBL_BUFS (128 * 16) 257 258 struct ptbl_buf { 259 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 260 vm_offset_t kva; /* va of mapping */ 261 }; 262 263 /* ptbl free list and a lock used for access synchronization. */ 264 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 265 static struct mtx ptbl_buf_freelist_lock; 266 267 /* Base address of kva space allocated fot ptbl bufs. */ 268 static vm_offset_t ptbl_buf_pool_vabase; 269 270 /* Pointer to ptbl_buf structures. */ 271 static struct ptbl_buf *ptbl_bufs; 272 273 #ifdef SMP 274 void pmap_bootstrap_ap(volatile uint32_t *); 275 #endif 276 277 /* 278 * Kernel MMU interface 279 */ 280 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 281 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 282 vm_size_t, vm_offset_t); 283 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 284 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 285 vm_offset_t, vm_page_t *, vm_offset_t, int); 286 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 287 vm_prot_t, u_int flags, int8_t psind); 288 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 289 vm_page_t, vm_prot_t); 290 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 291 vm_prot_t); 292 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 293 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 294 vm_prot_t); 295 static void mmu_booke_init(mmu_t); 296 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 297 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 298 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 299 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 300 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 301 int); 302 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 303 vm_paddr_t *); 304 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 305 vm_object_t, vm_pindex_t, vm_size_t); 306 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 307 static void mmu_booke_page_init(mmu_t, vm_page_t); 308 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 309 static void mmu_booke_pinit(mmu_t, pmap_t); 310 static void mmu_booke_pinit0(mmu_t, pmap_t); 311 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 312 vm_prot_t); 313 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 314 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 315 static void mmu_booke_release(mmu_t, pmap_t); 316 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 317 static void mmu_booke_remove_all(mmu_t, vm_page_t); 318 static void mmu_booke_remove_write(mmu_t, vm_page_t); 319 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 320 static void mmu_booke_zero_page(mmu_t, vm_page_t); 321 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 322 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 323 static void mmu_booke_activate(mmu_t, struct thread *); 324 static void mmu_booke_deactivate(mmu_t, struct thread *); 325 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 326 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 327 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 328 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 329 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 330 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 331 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 332 static void mmu_booke_kremove(mmu_t, vm_offset_t); 333 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 334 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 335 vm_size_t); 336 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 337 void **); 338 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 339 void *); 340 static void mmu_booke_scan_init(mmu_t); 341 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 342 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 343 344 static mmu_method_t mmu_booke_methods[] = { 345 /* pmap dispatcher interface */ 346 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 347 MMUMETHOD(mmu_copy, mmu_booke_copy), 348 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 349 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 350 MMUMETHOD(mmu_enter, mmu_booke_enter), 351 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 352 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 353 MMUMETHOD(mmu_extract, mmu_booke_extract), 354 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 355 MMUMETHOD(mmu_init, mmu_booke_init), 356 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 357 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 358 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 359 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 360 MMUMETHOD(mmu_map, mmu_booke_map), 361 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 362 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 363 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 364 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 365 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 366 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 367 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 368 MMUMETHOD(mmu_protect, mmu_booke_protect), 369 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 370 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 371 MMUMETHOD(mmu_release, mmu_booke_release), 372 MMUMETHOD(mmu_remove, mmu_booke_remove), 373 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 374 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 375 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 376 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 377 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 378 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 379 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 380 MMUMETHOD(mmu_activate, mmu_booke_activate), 381 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 382 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 383 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 384 385 /* Internal interfaces */ 386 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 387 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 388 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 389 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 390 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 391 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 392 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 393 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 394 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 395 396 /* dumpsys() support */ 397 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 398 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 399 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 400 401 { 0, 0 } 402 }; 403 404 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 405 406 static __inline uint32_t 407 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 408 { 409 uint32_t attrib; 410 int i; 411 412 if (ma != VM_MEMATTR_DEFAULT) { 413 switch (ma) { 414 case VM_MEMATTR_UNCACHEABLE: 415 return (PTE_I | PTE_G); 416 case VM_MEMATTR_WRITE_COMBINING: 417 case VM_MEMATTR_WRITE_BACK: 418 case VM_MEMATTR_PREFETCHABLE: 419 return (PTE_I); 420 case VM_MEMATTR_WRITE_THROUGH: 421 return (PTE_W | PTE_M); 422 } 423 } 424 425 /* 426 * Assume the page is cache inhibited and access is guarded unless 427 * it's in our available memory array. 428 */ 429 attrib = _TLB_ENTRY_IO; 430 for (i = 0; i < physmem_regions_sz; i++) { 431 if ((pa >= physmem_regions[i].mr_start) && 432 (pa < (physmem_regions[i].mr_start + 433 physmem_regions[i].mr_size))) { 434 attrib = _TLB_ENTRY_MEM; 435 break; 436 } 437 } 438 439 return (attrib); 440 } 441 442 static inline void 443 tlb_miss_lock(void) 444 { 445 #ifdef SMP 446 struct pcpu *pc; 447 448 if (!smp_started) 449 return; 450 451 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 452 if (pc != pcpup) { 453 454 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 455 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 456 457 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 458 ("tlb_miss_lock: tried to lock self")); 459 460 tlb_lock(pc->pc_booke_tlb_lock); 461 462 CTR1(KTR_PMAP, "%s: locked", __func__); 463 } 464 } 465 #endif 466 } 467 468 static inline void 469 tlb_miss_unlock(void) 470 { 471 #ifdef SMP 472 struct pcpu *pc; 473 474 if (!smp_started) 475 return; 476 477 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 478 if (pc != pcpup) { 479 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 480 __func__, pc->pc_cpuid); 481 482 tlb_unlock(pc->pc_booke_tlb_lock); 483 484 CTR1(KTR_PMAP, "%s: unlocked", __func__); 485 } 486 } 487 #endif 488 } 489 490 /* Return number of entries in TLB0. */ 491 static __inline void 492 tlb0_get_tlbconf(void) 493 { 494 uint32_t tlb0_cfg; 495 496 tlb0_cfg = mfspr(SPR_TLB0CFG); 497 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 498 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 499 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 500 } 501 502 /* Return number of entries in TLB1. */ 503 static __inline void 504 tlb1_get_tlbconf(void) 505 { 506 uint32_t tlb1_cfg; 507 508 tlb1_cfg = mfspr(SPR_TLB1CFG); 509 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 510 } 511 512 /**************************************************************************/ 513 /* Page table related */ 514 /**************************************************************************/ 515 516 /* Initialize pool of kva ptbl buffers. */ 517 static void 518 ptbl_init(void) 519 { 520 int i; 521 522 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 523 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 524 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 525 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 526 527 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 528 TAILQ_INIT(&ptbl_buf_freelist); 529 530 for (i = 0; i < PTBL_BUFS; i++) { 531 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 532 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 533 } 534 } 535 536 /* Get a ptbl_buf from the freelist. */ 537 static struct ptbl_buf * 538 ptbl_buf_alloc(void) 539 { 540 struct ptbl_buf *buf; 541 542 mtx_lock(&ptbl_buf_freelist_lock); 543 buf = TAILQ_FIRST(&ptbl_buf_freelist); 544 if (buf != NULL) 545 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 546 mtx_unlock(&ptbl_buf_freelist_lock); 547 548 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 549 550 return (buf); 551 } 552 553 /* Return ptbl buff to free pool. */ 554 static void 555 ptbl_buf_free(struct ptbl_buf *buf) 556 { 557 558 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 559 560 mtx_lock(&ptbl_buf_freelist_lock); 561 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 562 mtx_unlock(&ptbl_buf_freelist_lock); 563 } 564 565 /* 566 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 567 */ 568 static void 569 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 570 { 571 struct ptbl_buf *pbuf; 572 573 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 574 575 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 576 577 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 578 if (pbuf->kva == (vm_offset_t)ptbl) { 579 /* Remove from pmap ptbl buf list. */ 580 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 581 582 /* Free corresponding ptbl buf. */ 583 ptbl_buf_free(pbuf); 584 break; 585 } 586 } 587 588 /* Allocate page table. */ 589 static pte_t * 590 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 591 { 592 vm_page_t mtbl[PTBL_PAGES]; 593 vm_page_t m; 594 struct ptbl_buf *pbuf; 595 unsigned int pidx; 596 pte_t *ptbl; 597 int i, j; 598 599 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 600 (pmap == kernel_pmap), pdir_idx); 601 602 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 603 ("ptbl_alloc: invalid pdir_idx")); 604 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 605 ("pte_alloc: valid ptbl entry exists!")); 606 607 pbuf = ptbl_buf_alloc(); 608 if (pbuf == NULL) 609 panic("pte_alloc: couldn't alloc kernel virtual memory"); 610 611 ptbl = (pte_t *)pbuf->kva; 612 613 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 614 615 /* Allocate ptbl pages, this will sleep! */ 616 for (i = 0; i < PTBL_PAGES; i++) { 617 pidx = (PTBL_PAGES * pdir_idx) + i; 618 while ((m = vm_page_alloc(NULL, pidx, 619 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 620 PMAP_UNLOCK(pmap); 621 rw_wunlock(&pvh_global_lock); 622 if (nosleep) { 623 ptbl_free_pmap_ptbl(pmap, ptbl); 624 for (j = 0; j < i; j++) 625 vm_page_free(mtbl[j]); 626 atomic_subtract_int(&vm_cnt.v_wire_count, i); 627 return (NULL); 628 } 629 VM_WAIT; 630 rw_wlock(&pvh_global_lock); 631 PMAP_LOCK(pmap); 632 } 633 mtbl[i] = m; 634 } 635 636 /* Map allocated pages into kernel_pmap. */ 637 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 638 639 /* Zero whole ptbl. */ 640 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 641 642 /* Add pbuf to the pmap ptbl bufs list. */ 643 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 644 645 return (ptbl); 646 } 647 648 /* Free ptbl pages and invalidate pdir entry. */ 649 static void 650 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 651 { 652 pte_t *ptbl; 653 vm_paddr_t pa; 654 vm_offset_t va; 655 vm_page_t m; 656 int i; 657 658 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 659 (pmap == kernel_pmap), pdir_idx); 660 661 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 662 ("ptbl_free: invalid pdir_idx")); 663 664 ptbl = pmap->pm_pdir[pdir_idx]; 665 666 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 667 668 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 669 670 /* 671 * Invalidate the pdir entry as soon as possible, so that other CPUs 672 * don't attempt to look up the page tables we are releasing. 673 */ 674 mtx_lock_spin(&tlbivax_mutex); 675 tlb_miss_lock(); 676 677 pmap->pm_pdir[pdir_idx] = NULL; 678 679 tlb_miss_unlock(); 680 mtx_unlock_spin(&tlbivax_mutex); 681 682 for (i = 0; i < PTBL_PAGES; i++) { 683 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 684 pa = pte_vatopa(mmu, kernel_pmap, va); 685 m = PHYS_TO_VM_PAGE(pa); 686 vm_page_free_zero(m); 687 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 688 mmu_booke_kremove(mmu, va); 689 } 690 691 ptbl_free_pmap_ptbl(pmap, ptbl); 692 } 693 694 /* 695 * Decrement ptbl pages hold count and attempt to free ptbl pages. 696 * Called when removing pte entry from ptbl. 697 * 698 * Return 1 if ptbl pages were freed. 699 */ 700 static int 701 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 702 { 703 pte_t *ptbl; 704 vm_paddr_t pa; 705 vm_page_t m; 706 int i; 707 708 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 709 (pmap == kernel_pmap), pdir_idx); 710 711 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 712 ("ptbl_unhold: invalid pdir_idx")); 713 KASSERT((pmap != kernel_pmap), 714 ("ptbl_unhold: unholding kernel ptbl!")); 715 716 ptbl = pmap->pm_pdir[pdir_idx]; 717 718 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 719 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 720 ("ptbl_unhold: non kva ptbl")); 721 722 /* decrement hold count */ 723 for (i = 0; i < PTBL_PAGES; i++) { 724 pa = pte_vatopa(mmu, kernel_pmap, 725 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 726 m = PHYS_TO_VM_PAGE(pa); 727 m->wire_count--; 728 } 729 730 /* 731 * Free ptbl pages if there are no pte etries in this ptbl. 732 * wire_count has the same value for all ptbl pages, so check the last 733 * page. 734 */ 735 if (m->wire_count == 0) { 736 ptbl_free(mmu, pmap, pdir_idx); 737 738 //debugf("ptbl_unhold: e (freed ptbl)\n"); 739 return (1); 740 } 741 742 return (0); 743 } 744 745 /* 746 * Increment hold count for ptbl pages. This routine is used when a new pte 747 * entry is being inserted into the ptbl. 748 */ 749 static void 750 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 751 { 752 vm_paddr_t pa; 753 pte_t *ptbl; 754 vm_page_t m; 755 int i; 756 757 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 758 pdir_idx); 759 760 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 761 ("ptbl_hold: invalid pdir_idx")); 762 KASSERT((pmap != kernel_pmap), 763 ("ptbl_hold: holding kernel ptbl!")); 764 765 ptbl = pmap->pm_pdir[pdir_idx]; 766 767 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 768 769 for (i = 0; i < PTBL_PAGES; i++) { 770 pa = pte_vatopa(mmu, kernel_pmap, 771 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 772 m = PHYS_TO_VM_PAGE(pa); 773 m->wire_count++; 774 } 775 } 776 777 /* Allocate pv_entry structure. */ 778 pv_entry_t 779 pv_alloc(void) 780 { 781 pv_entry_t pv; 782 783 pv_entry_count++; 784 if (pv_entry_count > pv_entry_high_water) 785 pagedaemon_wakeup(); 786 pv = uma_zalloc(pvzone, M_NOWAIT); 787 788 return (pv); 789 } 790 791 /* Free pv_entry structure. */ 792 static __inline void 793 pv_free(pv_entry_t pve) 794 { 795 796 pv_entry_count--; 797 uma_zfree(pvzone, pve); 798 } 799 800 801 /* Allocate and initialize pv_entry structure. */ 802 static void 803 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 804 { 805 pv_entry_t pve; 806 807 //int su = (pmap == kernel_pmap); 808 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 809 // (u_int32_t)pmap, va, (u_int32_t)m); 810 811 pve = pv_alloc(); 812 if (pve == NULL) 813 panic("pv_insert: no pv entries!"); 814 815 pve->pv_pmap = pmap; 816 pve->pv_va = va; 817 818 /* add to pv_list */ 819 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 820 rw_assert(&pvh_global_lock, RA_WLOCKED); 821 822 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 823 824 //debugf("pv_insert: e\n"); 825 } 826 827 /* Destroy pv entry. */ 828 static void 829 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 830 { 831 pv_entry_t pve; 832 833 //int su = (pmap == kernel_pmap); 834 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 835 836 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 837 rw_assert(&pvh_global_lock, RA_WLOCKED); 838 839 /* find pv entry */ 840 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 841 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 842 /* remove from pv_list */ 843 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 844 if (TAILQ_EMPTY(&m->md.pv_list)) 845 vm_page_aflag_clear(m, PGA_WRITEABLE); 846 847 /* free pv entry struct */ 848 pv_free(pve); 849 break; 850 } 851 } 852 853 //debugf("pv_remove: e\n"); 854 } 855 856 /* 857 * Clean pte entry, try to free page table page if requested. 858 * 859 * Return 1 if ptbl pages were freed, otherwise return 0. 860 */ 861 static int 862 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 863 { 864 unsigned int pdir_idx = PDIR_IDX(va); 865 unsigned int ptbl_idx = PTBL_IDX(va); 866 vm_page_t m; 867 pte_t *ptbl; 868 pte_t *pte; 869 870 //int su = (pmap == kernel_pmap); 871 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 872 // su, (u_int32_t)pmap, va, flags); 873 874 ptbl = pmap->pm_pdir[pdir_idx]; 875 KASSERT(ptbl, ("pte_remove: null ptbl")); 876 877 pte = &ptbl[ptbl_idx]; 878 879 if (pte == NULL || !PTE_ISVALID(pte)) 880 return (0); 881 882 if (PTE_ISWIRED(pte)) 883 pmap->pm_stats.wired_count--; 884 885 /* Handle managed entry. */ 886 if (PTE_ISMANAGED(pte)) { 887 /* Get vm_page_t for mapped pte. */ 888 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 889 890 if (PTE_ISMODIFIED(pte)) 891 vm_page_dirty(m); 892 893 if (PTE_ISREFERENCED(pte)) 894 vm_page_aflag_set(m, PGA_REFERENCED); 895 896 pv_remove(pmap, va, m); 897 } 898 899 mtx_lock_spin(&tlbivax_mutex); 900 tlb_miss_lock(); 901 902 tlb0_flush_entry(va); 903 pte->flags = 0; 904 pte->rpn = 0; 905 906 tlb_miss_unlock(); 907 mtx_unlock_spin(&tlbivax_mutex); 908 909 pmap->pm_stats.resident_count--; 910 911 if (flags & PTBL_UNHOLD) { 912 //debugf("pte_remove: e (unhold)\n"); 913 return (ptbl_unhold(mmu, pmap, pdir_idx)); 914 } 915 916 //debugf("pte_remove: e\n"); 917 return (0); 918 } 919 920 /* 921 * Insert PTE for a given page and virtual address. 922 */ 923 static int 924 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 925 boolean_t nosleep) 926 { 927 unsigned int pdir_idx = PDIR_IDX(va); 928 unsigned int ptbl_idx = PTBL_IDX(va); 929 pte_t *ptbl, *pte; 930 931 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 932 pmap == kernel_pmap, pmap, va); 933 934 /* Get the page table pointer. */ 935 ptbl = pmap->pm_pdir[pdir_idx]; 936 937 if (ptbl == NULL) { 938 /* Allocate page table pages. */ 939 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 940 if (ptbl == NULL) { 941 KASSERT(nosleep, ("nosleep and NULL ptbl")); 942 return (ENOMEM); 943 } 944 } else { 945 /* 946 * Check if there is valid mapping for requested 947 * va, if there is, remove it. 948 */ 949 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 950 if (PTE_ISVALID(pte)) { 951 pte_remove(mmu, pmap, va, PTBL_HOLD); 952 } else { 953 /* 954 * pte is not used, increment hold count 955 * for ptbl pages. 956 */ 957 if (pmap != kernel_pmap) 958 ptbl_hold(mmu, pmap, pdir_idx); 959 } 960 } 961 962 /* 963 * Insert pv_entry into pv_list for mapped page if part of managed 964 * memory. 965 */ 966 if ((m->oflags & VPO_UNMANAGED) == 0) { 967 flags |= PTE_MANAGED; 968 969 /* Create and insert pv entry. */ 970 pv_insert(pmap, va, m); 971 } 972 973 pmap->pm_stats.resident_count++; 974 975 mtx_lock_spin(&tlbivax_mutex); 976 tlb_miss_lock(); 977 978 tlb0_flush_entry(va); 979 if (pmap->pm_pdir[pdir_idx] == NULL) { 980 /* 981 * If we just allocated a new page table, hook it in 982 * the pdir. 983 */ 984 pmap->pm_pdir[pdir_idx] = ptbl; 985 } 986 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 987 pte->rpn = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 988 pte->flags |= (PTE_VALID | flags); 989 990 tlb_miss_unlock(); 991 mtx_unlock_spin(&tlbivax_mutex); 992 return (0); 993 } 994 995 /* Return the pa for the given pmap/va. */ 996 static vm_paddr_t 997 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 998 { 999 vm_paddr_t pa = 0; 1000 pte_t *pte; 1001 1002 pte = pte_find(mmu, pmap, va); 1003 if ((pte != NULL) && PTE_ISVALID(pte)) 1004 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1005 return (pa); 1006 } 1007 1008 /* Get a pointer to a PTE in a page table. */ 1009 static pte_t * 1010 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1011 { 1012 unsigned int pdir_idx = PDIR_IDX(va); 1013 unsigned int ptbl_idx = PTBL_IDX(va); 1014 1015 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1016 1017 if (pmap->pm_pdir[pdir_idx]) 1018 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1019 1020 return (NULL); 1021 } 1022 1023 /* Set up kernel page tables. */ 1024 static void 1025 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1026 { 1027 int i; 1028 vm_offset_t va; 1029 pte_t *pte; 1030 1031 /* Initialize kernel pdir */ 1032 for (i = 0; i < kernel_ptbls; i++) 1033 kernel_pmap->pm_pdir[kptbl_min + i] = 1034 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1035 1036 /* 1037 * Fill in PTEs covering kernel code and data. They are not required 1038 * for address translation, as this area is covered by static TLB1 1039 * entries, but for pte_vatopa() to work correctly with kernel area 1040 * addresses. 1041 */ 1042 for (va = addr; va < data_end; va += PAGE_SIZE) { 1043 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1044 pte->rpn = kernload + (va - kernstart); 1045 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1046 PTE_VALID; 1047 } 1048 } 1049 1050 /**************************************************************************/ 1051 /* PMAP related */ 1052 /**************************************************************************/ 1053 1054 /* 1055 * This is called during booke_init, before the system is really initialized. 1056 */ 1057 static void 1058 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1059 { 1060 vm_paddr_t phys_kernelend; 1061 struct mem_region *mp, *mp1; 1062 int cnt, i, j; 1063 vm_paddr_t s, e, sz; 1064 vm_paddr_t physsz, hwphyssz; 1065 u_int phys_avail_count; 1066 vm_size_t kstack0_sz; 1067 vm_offset_t kernel_pdir, kstack0; 1068 vm_paddr_t kstack0_phys; 1069 void *dpcpu; 1070 1071 debugf("mmu_booke_bootstrap: entered\n"); 1072 1073 /* Set interesting system properties */ 1074 hw_direct_map = 0; 1075 elf32_nxstack = 1; 1076 1077 /* Initialize invalidation mutex */ 1078 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1079 1080 /* Read TLB0 size and associativity. */ 1081 tlb0_get_tlbconf(); 1082 1083 /* 1084 * Align kernel start and end address (kernel image). 1085 * Note that kernel end does not necessarily relate to kernsize. 1086 * kernsize is the size of the kernel that is actually mapped. 1087 */ 1088 kernstart = trunc_page(start); 1089 data_start = round_page(kernelend); 1090 data_end = data_start; 1091 1092 /* 1093 * Addresses of preloaded modules (like file systems) use 1094 * physical addresses. Make sure we relocate those into 1095 * virtual addresses. 1096 */ 1097 preload_addr_relocate = kernstart - kernload; 1098 1099 /* Allocate the dynamic per-cpu area. */ 1100 dpcpu = (void *)data_end; 1101 data_end += DPCPU_SIZE; 1102 1103 /* Allocate space for the message buffer. */ 1104 msgbufp = (struct msgbuf *)data_end; 1105 data_end += msgbufsize; 1106 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1107 data_end); 1108 1109 data_end = round_page(data_end); 1110 1111 /* Allocate space for ptbl_bufs. */ 1112 ptbl_bufs = (struct ptbl_buf *)data_end; 1113 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1114 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1115 data_end); 1116 1117 data_end = round_page(data_end); 1118 1119 /* Allocate PTE tables for kernel KVA. */ 1120 kernel_pdir = data_end; 1121 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1122 PDIR_SIZE - 1) / PDIR_SIZE; 1123 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1124 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1125 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1126 1127 debugf(" data_end: 0x%08x\n", data_end); 1128 if (data_end - kernstart > kernsize) { 1129 kernsize += tlb1_mapin_region(kernstart + kernsize, 1130 kernload + kernsize, (data_end - kernstart) - kernsize); 1131 } 1132 data_end = kernstart + kernsize; 1133 debugf(" updated data_end: 0x%08x\n", data_end); 1134 1135 /* 1136 * Clear the structures - note we can only do it safely after the 1137 * possible additional TLB1 translations are in place (above) so that 1138 * all range up to the currently calculated 'data_end' is covered. 1139 */ 1140 dpcpu_init(dpcpu, 0); 1141 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1142 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1143 1144 /*******************************************************/ 1145 /* Set the start and end of kva. */ 1146 /*******************************************************/ 1147 virtual_avail = round_page(data_end); 1148 virtual_end = VM_MAX_KERNEL_ADDRESS; 1149 1150 /* Allocate KVA space for page zero/copy operations. */ 1151 zero_page_va = virtual_avail; 1152 virtual_avail += PAGE_SIZE; 1153 zero_page_idle_va = virtual_avail; 1154 virtual_avail += PAGE_SIZE; 1155 copy_page_src_va = virtual_avail; 1156 virtual_avail += PAGE_SIZE; 1157 copy_page_dst_va = virtual_avail; 1158 virtual_avail += PAGE_SIZE; 1159 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1160 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1161 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1162 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1163 1164 /* Initialize page zero/copy mutexes. */ 1165 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1166 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1167 1168 /* Allocate KVA space for ptbl bufs. */ 1169 ptbl_buf_pool_vabase = virtual_avail; 1170 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1171 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1172 ptbl_buf_pool_vabase, virtual_avail); 1173 1174 /* Calculate corresponding physical addresses for the kernel region. */ 1175 phys_kernelend = kernload + kernsize; 1176 debugf("kernel image and allocated data:\n"); 1177 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1178 debugf(" kernstart = 0x%08x\n", kernstart); 1179 debugf(" kernsize = 0x%08x\n", kernsize); 1180 1181 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1182 panic("mmu_booke_bootstrap: phys_avail too small"); 1183 1184 /* 1185 * Remove kernel physical address range from avail regions list. Page 1186 * align all regions. Non-page aligned memory isn't very interesting 1187 * to us. Also, sort the entries for ascending addresses. 1188 */ 1189 1190 /* Retrieve phys/avail mem regions */ 1191 mem_regions(&physmem_regions, &physmem_regions_sz, 1192 &availmem_regions, &availmem_regions_sz); 1193 sz = 0; 1194 cnt = availmem_regions_sz; 1195 debugf("processing avail regions:\n"); 1196 for (mp = availmem_regions; mp->mr_size; mp++) { 1197 s = mp->mr_start; 1198 e = mp->mr_start + mp->mr_size; 1199 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1200 /* Check whether this region holds all of the kernel. */ 1201 if (s < kernload && e > phys_kernelend) { 1202 availmem_regions[cnt].mr_start = phys_kernelend; 1203 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1204 e = kernload; 1205 } 1206 /* Look whether this regions starts within the kernel. */ 1207 if (s >= kernload && s < phys_kernelend) { 1208 if (e <= phys_kernelend) 1209 goto empty; 1210 s = phys_kernelend; 1211 } 1212 /* Now look whether this region ends within the kernel. */ 1213 if (e > kernload && e <= phys_kernelend) { 1214 if (s >= kernload) 1215 goto empty; 1216 e = kernload; 1217 } 1218 /* Now page align the start and size of the region. */ 1219 s = round_page(s); 1220 e = trunc_page(e); 1221 if (e < s) 1222 e = s; 1223 sz = e - s; 1224 debugf("%09jx-%09jx = %jx\n", 1225 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1226 1227 /* Check whether some memory is left here. */ 1228 if (sz == 0) { 1229 empty: 1230 memmove(mp, mp + 1, 1231 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1232 cnt--; 1233 mp--; 1234 continue; 1235 } 1236 1237 /* Do an insertion sort. */ 1238 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1239 if (s < mp1->mr_start) 1240 break; 1241 if (mp1 < mp) { 1242 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1243 mp1->mr_start = s; 1244 mp1->mr_size = sz; 1245 } else { 1246 mp->mr_start = s; 1247 mp->mr_size = sz; 1248 } 1249 } 1250 availmem_regions_sz = cnt; 1251 1252 /*******************************************************/ 1253 /* Steal physical memory for kernel stack from the end */ 1254 /* of the first avail region */ 1255 /*******************************************************/ 1256 kstack0_sz = kstack_pages * PAGE_SIZE; 1257 kstack0_phys = availmem_regions[0].mr_start + 1258 availmem_regions[0].mr_size; 1259 kstack0_phys -= kstack0_sz; 1260 availmem_regions[0].mr_size -= kstack0_sz; 1261 1262 /*******************************************************/ 1263 /* Fill in phys_avail table, based on availmem_regions */ 1264 /*******************************************************/ 1265 phys_avail_count = 0; 1266 physsz = 0; 1267 hwphyssz = 0; 1268 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1269 1270 debugf("fill in phys_avail:\n"); 1271 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1272 1273 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1274 (uintmax_t)availmem_regions[i].mr_start, 1275 (uintmax_t)availmem_regions[i].mr_start + 1276 availmem_regions[i].mr_size, 1277 (uintmax_t)availmem_regions[i].mr_size); 1278 1279 if (hwphyssz != 0 && 1280 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1281 debugf(" hw.physmem adjust\n"); 1282 if (physsz < hwphyssz) { 1283 phys_avail[j] = availmem_regions[i].mr_start; 1284 phys_avail[j + 1] = 1285 availmem_regions[i].mr_start + 1286 hwphyssz - physsz; 1287 physsz = hwphyssz; 1288 phys_avail_count++; 1289 } 1290 break; 1291 } 1292 1293 phys_avail[j] = availmem_regions[i].mr_start; 1294 phys_avail[j + 1] = availmem_regions[i].mr_start + 1295 availmem_regions[i].mr_size; 1296 phys_avail_count++; 1297 physsz += availmem_regions[i].mr_size; 1298 } 1299 physmem = btoc(physsz); 1300 1301 /* Calculate the last available physical address. */ 1302 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1303 ; 1304 Maxmem = powerpc_btop(phys_avail[i + 1]); 1305 1306 debugf("Maxmem = 0x%08lx\n", Maxmem); 1307 debugf("phys_avail_count = %d\n", phys_avail_count); 1308 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1309 physmem); 1310 1311 /*******************************************************/ 1312 /* Initialize (statically allocated) kernel pmap. */ 1313 /*******************************************************/ 1314 PMAP_LOCK_INIT(kernel_pmap); 1315 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1316 1317 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1318 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1319 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1320 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1321 1322 kernel_pte_alloc(data_end, kernstart, kernel_pdir); 1323 for (i = 0; i < MAXCPU; i++) { 1324 kernel_pmap->pm_tid[i] = TID_KERNEL; 1325 1326 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1327 tidbusy[i][TID_KERNEL] = kernel_pmap; 1328 } 1329 1330 /* Mark kernel_pmap active on all CPUs */ 1331 CPU_FILL(&kernel_pmap->pm_active); 1332 1333 /* 1334 * Initialize the global pv list lock. 1335 */ 1336 rw_init(&pvh_global_lock, "pmap pv global"); 1337 1338 /*******************************************************/ 1339 /* Final setup */ 1340 /*******************************************************/ 1341 1342 /* Enter kstack0 into kernel map, provide guard page */ 1343 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1344 thread0.td_kstack = kstack0; 1345 thread0.td_kstack_pages = kstack_pages; 1346 1347 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1348 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1349 kstack0_phys, kstack0_phys + kstack0_sz); 1350 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1351 1352 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1353 for (i = 0; i < kstack_pages; i++) { 1354 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1355 kstack0 += PAGE_SIZE; 1356 kstack0_phys += PAGE_SIZE; 1357 } 1358 1359 pmap_bootstrapped = 1; 1360 1361 debugf("virtual_avail = %08x\n", virtual_avail); 1362 debugf("virtual_end = %08x\n", virtual_end); 1363 1364 debugf("mmu_booke_bootstrap: exit\n"); 1365 } 1366 1367 #ifdef SMP 1368 void 1369 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1370 { 1371 int i; 1372 1373 /* 1374 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1375 * have the snapshot of its contents in the s/w tlb1[] table, so use 1376 * these values directly to (re)program AP's TLB1 hardware. 1377 */ 1378 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1379 /* Skip invalid entries */ 1380 if (!(tlb1[i].mas1 & MAS1_VALID)) 1381 continue; 1382 1383 tlb1_write_entry(i); 1384 } 1385 1386 set_mas4_defaults(); 1387 } 1388 #endif 1389 1390 static void 1391 booke_pmap_init_qpages(void) 1392 { 1393 struct pcpu *pc; 1394 int i; 1395 1396 CPU_FOREACH(i) { 1397 pc = pcpu_find(i); 1398 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1399 if (pc->pc_qmap_addr == 0) 1400 panic("pmap_init_qpages: unable to allocate KVA"); 1401 } 1402 } 1403 1404 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1405 1406 /* 1407 * Get the physical page address for the given pmap/virtual address. 1408 */ 1409 static vm_paddr_t 1410 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1411 { 1412 vm_paddr_t pa; 1413 1414 PMAP_LOCK(pmap); 1415 pa = pte_vatopa(mmu, pmap, va); 1416 PMAP_UNLOCK(pmap); 1417 1418 return (pa); 1419 } 1420 1421 /* 1422 * Extract the physical page address associated with the given 1423 * kernel virtual address. 1424 */ 1425 static vm_paddr_t 1426 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1427 { 1428 int i; 1429 1430 /* Check TLB1 mappings */ 1431 for (i = 0; i < tlb1_idx; i++) { 1432 if (!(tlb1[i].mas1 & MAS1_VALID)) 1433 continue; 1434 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1435 return (tlb1[i].phys + (va - tlb1[i].virt)); 1436 } 1437 1438 return (pte_vatopa(mmu, kernel_pmap, va)); 1439 } 1440 1441 /* 1442 * Initialize the pmap module. 1443 * Called by vm_init, to initialize any structures that the pmap 1444 * system needs to map virtual memory. 1445 */ 1446 static void 1447 mmu_booke_init(mmu_t mmu) 1448 { 1449 int shpgperproc = PMAP_SHPGPERPROC; 1450 1451 /* 1452 * Initialize the address space (zone) for the pv entries. Set a 1453 * high water mark so that the system can recover from excessive 1454 * numbers of pv entries. 1455 */ 1456 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1457 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1458 1459 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1460 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1461 1462 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1463 pv_entry_high_water = 9 * (pv_entry_max / 10); 1464 1465 uma_zone_reserve_kva(pvzone, pv_entry_max); 1466 1467 /* Pre-fill pvzone with initial number of pv entries. */ 1468 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1469 1470 /* Initialize ptbl allocation. */ 1471 ptbl_init(); 1472 } 1473 1474 /* 1475 * Map a list of wired pages into kernel virtual address space. This is 1476 * intended for temporary mappings which do not need page modification or 1477 * references recorded. Existing mappings in the region are overwritten. 1478 */ 1479 static void 1480 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1481 { 1482 vm_offset_t va; 1483 1484 va = sva; 1485 while (count-- > 0) { 1486 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1487 va += PAGE_SIZE; 1488 m++; 1489 } 1490 } 1491 1492 /* 1493 * Remove page mappings from kernel virtual address space. Intended for 1494 * temporary mappings entered by mmu_booke_qenter. 1495 */ 1496 static void 1497 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1498 { 1499 vm_offset_t va; 1500 1501 va = sva; 1502 while (count-- > 0) { 1503 mmu_booke_kremove(mmu, va); 1504 va += PAGE_SIZE; 1505 } 1506 } 1507 1508 /* 1509 * Map a wired page into kernel virtual address space. 1510 */ 1511 static void 1512 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1513 { 1514 1515 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1516 } 1517 1518 static void 1519 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1520 { 1521 uint32_t flags; 1522 pte_t *pte; 1523 1524 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1525 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1526 1527 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1528 flags |= tlb_calc_wimg(pa, ma); 1529 1530 pte = pte_find(mmu, kernel_pmap, va); 1531 1532 mtx_lock_spin(&tlbivax_mutex); 1533 tlb_miss_lock(); 1534 1535 if (PTE_ISVALID(pte)) { 1536 1537 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1538 1539 /* Flush entry from TLB0 */ 1540 tlb0_flush_entry(va); 1541 } 1542 1543 pte->rpn = PTE_RPN_FROM_PA(pa); 1544 pte->flags = flags; 1545 1546 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1547 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1548 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1549 1550 /* Flush the real memory from the instruction cache. */ 1551 if ((flags & (PTE_I | PTE_G)) == 0) { 1552 __syncicache((void *)va, PAGE_SIZE); 1553 } 1554 1555 tlb_miss_unlock(); 1556 mtx_unlock_spin(&tlbivax_mutex); 1557 } 1558 1559 /* 1560 * Remove a page from kernel page table. 1561 */ 1562 static void 1563 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1564 { 1565 pte_t *pte; 1566 1567 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 1568 1569 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1570 (va <= VM_MAX_KERNEL_ADDRESS)), 1571 ("mmu_booke_kremove: invalid va")); 1572 1573 pte = pte_find(mmu, kernel_pmap, va); 1574 1575 if (!PTE_ISVALID(pte)) { 1576 1577 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1578 1579 return; 1580 } 1581 1582 mtx_lock_spin(&tlbivax_mutex); 1583 tlb_miss_lock(); 1584 1585 /* Invalidate entry in TLB0, update PTE. */ 1586 tlb0_flush_entry(va); 1587 pte->flags = 0; 1588 pte->rpn = 0; 1589 1590 tlb_miss_unlock(); 1591 mtx_unlock_spin(&tlbivax_mutex); 1592 } 1593 1594 /* 1595 * Initialize pmap associated with process 0. 1596 */ 1597 static void 1598 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1599 { 1600 1601 PMAP_LOCK_INIT(pmap); 1602 mmu_booke_pinit(mmu, pmap); 1603 PCPU_SET(curpmap, pmap); 1604 } 1605 1606 /* 1607 * Initialize a preallocated and zeroed pmap structure, 1608 * such as one in a vmspace structure. 1609 */ 1610 static void 1611 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1612 { 1613 int i; 1614 1615 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1616 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1617 1618 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1619 1620 for (i = 0; i < MAXCPU; i++) 1621 pmap->pm_tid[i] = TID_NONE; 1622 CPU_ZERO(&kernel_pmap->pm_active); 1623 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1624 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1625 TAILQ_INIT(&pmap->pm_ptbl_list); 1626 } 1627 1628 /* 1629 * Release any resources held by the given physical map. 1630 * Called when a pmap initialized by mmu_booke_pinit is being released. 1631 * Should only be called if the map contains no valid mappings. 1632 */ 1633 static void 1634 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1635 { 1636 1637 KASSERT(pmap->pm_stats.resident_count == 0, 1638 ("pmap_release: pmap resident count %ld != 0", 1639 pmap->pm_stats.resident_count)); 1640 } 1641 1642 /* 1643 * Insert the given physical page at the specified virtual address in the 1644 * target physical map with the protection requested. If specified the page 1645 * will be wired down. 1646 */ 1647 static int 1648 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1649 vm_prot_t prot, u_int flags, int8_t psind) 1650 { 1651 int error; 1652 1653 rw_wlock(&pvh_global_lock); 1654 PMAP_LOCK(pmap); 1655 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1656 rw_wunlock(&pvh_global_lock); 1657 PMAP_UNLOCK(pmap); 1658 return (error); 1659 } 1660 1661 static int 1662 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1663 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1664 { 1665 pte_t *pte; 1666 vm_paddr_t pa; 1667 uint32_t flags; 1668 int error, su, sync; 1669 1670 pa = VM_PAGE_TO_PHYS(m); 1671 su = (pmap == kernel_pmap); 1672 sync = 0; 1673 1674 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1675 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1676 // (u_int32_t)pmap, su, pmap->pm_tid, 1677 // (u_int32_t)m, va, pa, prot, flags); 1678 1679 if (su) { 1680 KASSERT(((va >= virtual_avail) && 1681 (va <= VM_MAX_KERNEL_ADDRESS)), 1682 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1683 } else { 1684 KASSERT((va <= VM_MAXUSER_ADDRESS), 1685 ("mmu_booke_enter_locked: user pmap, non user va")); 1686 } 1687 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1688 VM_OBJECT_ASSERT_LOCKED(m->object); 1689 1690 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1691 1692 /* 1693 * If there is an existing mapping, and the physical address has not 1694 * changed, must be protection or wiring change. 1695 */ 1696 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1697 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1698 1699 /* 1700 * Before actually updating pte->flags we calculate and 1701 * prepare its new value in a helper var. 1702 */ 1703 flags = pte->flags; 1704 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1705 1706 /* Wiring change, just update stats. */ 1707 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1708 if (!PTE_ISWIRED(pte)) { 1709 flags |= PTE_WIRED; 1710 pmap->pm_stats.wired_count++; 1711 } 1712 } else { 1713 if (PTE_ISWIRED(pte)) { 1714 flags &= ~PTE_WIRED; 1715 pmap->pm_stats.wired_count--; 1716 } 1717 } 1718 1719 if (prot & VM_PROT_WRITE) { 1720 /* Add write permissions. */ 1721 flags |= PTE_SW; 1722 if (!su) 1723 flags |= PTE_UW; 1724 1725 if ((flags & PTE_MANAGED) != 0) 1726 vm_page_aflag_set(m, PGA_WRITEABLE); 1727 } else { 1728 /* Handle modified pages, sense modify status. */ 1729 1730 /* 1731 * The PTE_MODIFIED flag could be set by underlying 1732 * TLB misses since we last read it (above), possibly 1733 * other CPUs could update it so we check in the PTE 1734 * directly rather than rely on that saved local flags 1735 * copy. 1736 */ 1737 if (PTE_ISMODIFIED(pte)) 1738 vm_page_dirty(m); 1739 } 1740 1741 if (prot & VM_PROT_EXECUTE) { 1742 flags |= PTE_SX; 1743 if (!su) 1744 flags |= PTE_UX; 1745 1746 /* 1747 * Check existing flags for execute permissions: if we 1748 * are turning execute permissions on, icache should 1749 * be flushed. 1750 */ 1751 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1752 sync++; 1753 } 1754 1755 flags &= ~PTE_REFERENCED; 1756 1757 /* 1758 * The new flags value is all calculated -- only now actually 1759 * update the PTE. 1760 */ 1761 mtx_lock_spin(&tlbivax_mutex); 1762 tlb_miss_lock(); 1763 1764 tlb0_flush_entry(va); 1765 pte->flags = flags; 1766 1767 tlb_miss_unlock(); 1768 mtx_unlock_spin(&tlbivax_mutex); 1769 1770 } else { 1771 /* 1772 * If there is an existing mapping, but it's for a different 1773 * physical address, pte_enter() will delete the old mapping. 1774 */ 1775 //if ((pte != NULL) && PTE_ISVALID(pte)) 1776 // debugf("mmu_booke_enter_locked: replace\n"); 1777 //else 1778 // debugf("mmu_booke_enter_locked: new\n"); 1779 1780 /* Now set up the flags and install the new mapping. */ 1781 flags = (PTE_SR | PTE_VALID); 1782 flags |= PTE_M; 1783 1784 if (!su) 1785 flags |= PTE_UR; 1786 1787 if (prot & VM_PROT_WRITE) { 1788 flags |= PTE_SW; 1789 if (!su) 1790 flags |= PTE_UW; 1791 1792 if ((m->oflags & VPO_UNMANAGED) == 0) 1793 vm_page_aflag_set(m, PGA_WRITEABLE); 1794 } 1795 1796 if (prot & VM_PROT_EXECUTE) { 1797 flags |= PTE_SX; 1798 if (!su) 1799 flags |= PTE_UX; 1800 } 1801 1802 /* If its wired update stats. */ 1803 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1804 flags |= PTE_WIRED; 1805 1806 error = pte_enter(mmu, pmap, m, va, flags, 1807 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1808 if (error != 0) 1809 return (KERN_RESOURCE_SHORTAGE); 1810 1811 if ((flags & PMAP_ENTER_WIRED) != 0) 1812 pmap->pm_stats.wired_count++; 1813 1814 /* Flush the real memory from the instruction cache. */ 1815 if (prot & VM_PROT_EXECUTE) 1816 sync++; 1817 } 1818 1819 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1820 __syncicache((void *)va, PAGE_SIZE); 1821 sync = 0; 1822 } 1823 1824 return (KERN_SUCCESS); 1825 } 1826 1827 /* 1828 * Maps a sequence of resident pages belonging to the same object. 1829 * The sequence begins with the given page m_start. This page is 1830 * mapped at the given virtual address start. Each subsequent page is 1831 * mapped at a virtual address that is offset from start by the same 1832 * amount as the page is offset from m_start within the object. The 1833 * last page in the sequence is the page with the largest offset from 1834 * m_start that can be mapped at a virtual address less than the given 1835 * virtual address end. Not every virtual page between start and end 1836 * is mapped; only those for which a resident page exists with the 1837 * corresponding offset from m_start are mapped. 1838 */ 1839 static void 1840 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1841 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1842 { 1843 vm_page_t m; 1844 vm_pindex_t diff, psize; 1845 1846 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1847 1848 psize = atop(end - start); 1849 m = m_start; 1850 rw_wlock(&pvh_global_lock); 1851 PMAP_LOCK(pmap); 1852 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1853 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1854 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1855 PMAP_ENTER_NOSLEEP, 0); 1856 m = TAILQ_NEXT(m, listq); 1857 } 1858 rw_wunlock(&pvh_global_lock); 1859 PMAP_UNLOCK(pmap); 1860 } 1861 1862 static void 1863 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1864 vm_prot_t prot) 1865 { 1866 1867 rw_wlock(&pvh_global_lock); 1868 PMAP_LOCK(pmap); 1869 mmu_booke_enter_locked(mmu, pmap, va, m, 1870 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1871 0); 1872 rw_wunlock(&pvh_global_lock); 1873 PMAP_UNLOCK(pmap); 1874 } 1875 1876 /* 1877 * Remove the given range of addresses from the specified map. 1878 * 1879 * It is assumed that the start and end are properly rounded to the page size. 1880 */ 1881 static void 1882 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1883 { 1884 pte_t *pte; 1885 uint8_t hold_flag; 1886 1887 int su = (pmap == kernel_pmap); 1888 1889 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1890 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1891 1892 if (su) { 1893 KASSERT(((va >= virtual_avail) && 1894 (va <= VM_MAX_KERNEL_ADDRESS)), 1895 ("mmu_booke_remove: kernel pmap, non kernel va")); 1896 } else { 1897 KASSERT((va <= VM_MAXUSER_ADDRESS), 1898 ("mmu_booke_remove: user pmap, non user va")); 1899 } 1900 1901 if (PMAP_REMOVE_DONE(pmap)) { 1902 //debugf("mmu_booke_remove: e (empty)\n"); 1903 return; 1904 } 1905 1906 hold_flag = PTBL_HOLD_FLAG(pmap); 1907 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1908 1909 rw_wlock(&pvh_global_lock); 1910 PMAP_LOCK(pmap); 1911 for (; va < endva; va += PAGE_SIZE) { 1912 pte = pte_find(mmu, pmap, va); 1913 if ((pte != NULL) && PTE_ISVALID(pte)) 1914 pte_remove(mmu, pmap, va, hold_flag); 1915 } 1916 PMAP_UNLOCK(pmap); 1917 rw_wunlock(&pvh_global_lock); 1918 1919 //debugf("mmu_booke_remove: e\n"); 1920 } 1921 1922 /* 1923 * Remove physical page from all pmaps in which it resides. 1924 */ 1925 static void 1926 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1927 { 1928 pv_entry_t pv, pvn; 1929 uint8_t hold_flag; 1930 1931 rw_wlock(&pvh_global_lock); 1932 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1933 pvn = TAILQ_NEXT(pv, pv_link); 1934 1935 PMAP_LOCK(pv->pv_pmap); 1936 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1937 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1938 PMAP_UNLOCK(pv->pv_pmap); 1939 } 1940 vm_page_aflag_clear(m, PGA_WRITEABLE); 1941 rw_wunlock(&pvh_global_lock); 1942 } 1943 1944 /* 1945 * Map a range of physical addresses into kernel virtual address space. 1946 */ 1947 static vm_offset_t 1948 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1949 vm_paddr_t pa_end, int prot) 1950 { 1951 vm_offset_t sva = *virt; 1952 vm_offset_t va = sva; 1953 1954 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1955 // sva, pa_start, pa_end); 1956 1957 while (pa_start < pa_end) { 1958 mmu_booke_kenter(mmu, va, pa_start); 1959 va += PAGE_SIZE; 1960 pa_start += PAGE_SIZE; 1961 } 1962 *virt = va; 1963 1964 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1965 return (sva); 1966 } 1967 1968 /* 1969 * The pmap must be activated before it's address space can be accessed in any 1970 * way. 1971 */ 1972 static void 1973 mmu_booke_activate(mmu_t mmu, struct thread *td) 1974 { 1975 pmap_t pmap; 1976 u_int cpuid; 1977 1978 pmap = &td->td_proc->p_vmspace->vm_pmap; 1979 1980 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1981 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1982 1983 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1984 1985 sched_pin(); 1986 1987 cpuid = PCPU_GET(cpuid); 1988 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1989 PCPU_SET(curpmap, pmap); 1990 1991 if (pmap->pm_tid[cpuid] == TID_NONE) 1992 tid_alloc(pmap); 1993 1994 /* Load PID0 register with pmap tid value. */ 1995 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1996 __asm __volatile("isync"); 1997 1998 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1999 2000 sched_unpin(); 2001 2002 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2003 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2004 } 2005 2006 /* 2007 * Deactivate the specified process's address space. 2008 */ 2009 static void 2010 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2011 { 2012 pmap_t pmap; 2013 2014 pmap = &td->td_proc->p_vmspace->vm_pmap; 2015 2016 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2017 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2018 2019 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2020 2021 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2022 PCPU_SET(curpmap, NULL); 2023 } 2024 2025 /* 2026 * Copy the range specified by src_addr/len 2027 * from the source map to the range dst_addr/len 2028 * in the destination map. 2029 * 2030 * This routine is only advisory and need not do anything. 2031 */ 2032 static void 2033 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2034 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2035 { 2036 2037 } 2038 2039 /* 2040 * Set the physical protection on the specified range of this map as requested. 2041 */ 2042 static void 2043 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2044 vm_prot_t prot) 2045 { 2046 vm_offset_t va; 2047 vm_page_t m; 2048 pte_t *pte; 2049 2050 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2051 mmu_booke_remove(mmu, pmap, sva, eva); 2052 return; 2053 } 2054 2055 if (prot & VM_PROT_WRITE) 2056 return; 2057 2058 PMAP_LOCK(pmap); 2059 for (va = sva; va < eva; va += PAGE_SIZE) { 2060 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2061 if (PTE_ISVALID(pte)) { 2062 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2063 2064 mtx_lock_spin(&tlbivax_mutex); 2065 tlb_miss_lock(); 2066 2067 /* Handle modified pages. */ 2068 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2069 vm_page_dirty(m); 2070 2071 tlb0_flush_entry(va); 2072 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2073 2074 tlb_miss_unlock(); 2075 mtx_unlock_spin(&tlbivax_mutex); 2076 } 2077 } 2078 } 2079 PMAP_UNLOCK(pmap); 2080 } 2081 2082 /* 2083 * Clear the write and modified bits in each of the given page's mappings. 2084 */ 2085 static void 2086 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2087 { 2088 pv_entry_t pv; 2089 pte_t *pte; 2090 2091 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2092 ("mmu_booke_remove_write: page %p is not managed", m)); 2093 2094 /* 2095 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2096 * set by another thread while the object is locked. Thus, 2097 * if PGA_WRITEABLE is clear, no page table entries need updating. 2098 */ 2099 VM_OBJECT_ASSERT_WLOCKED(m->object); 2100 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2101 return; 2102 rw_wlock(&pvh_global_lock); 2103 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2104 PMAP_LOCK(pv->pv_pmap); 2105 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2106 if (PTE_ISVALID(pte)) { 2107 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2108 2109 mtx_lock_spin(&tlbivax_mutex); 2110 tlb_miss_lock(); 2111 2112 /* Handle modified pages. */ 2113 if (PTE_ISMODIFIED(pte)) 2114 vm_page_dirty(m); 2115 2116 /* Flush mapping from TLB0. */ 2117 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2118 2119 tlb_miss_unlock(); 2120 mtx_unlock_spin(&tlbivax_mutex); 2121 } 2122 } 2123 PMAP_UNLOCK(pv->pv_pmap); 2124 } 2125 vm_page_aflag_clear(m, PGA_WRITEABLE); 2126 rw_wunlock(&pvh_global_lock); 2127 } 2128 2129 static void 2130 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2131 { 2132 pte_t *pte; 2133 pmap_t pmap; 2134 vm_page_t m; 2135 vm_offset_t addr; 2136 vm_paddr_t pa = 0; 2137 int active, valid; 2138 2139 va = trunc_page(va); 2140 sz = round_page(sz); 2141 2142 rw_wlock(&pvh_global_lock); 2143 pmap = PCPU_GET(curpmap); 2144 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2145 while (sz > 0) { 2146 PMAP_LOCK(pm); 2147 pte = pte_find(mmu, pm, va); 2148 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2149 if (valid) 2150 pa = PTE_PA(pte); 2151 PMAP_UNLOCK(pm); 2152 if (valid) { 2153 if (!active) { 2154 /* Create a mapping in the active pmap. */ 2155 addr = 0; 2156 m = PHYS_TO_VM_PAGE(pa); 2157 PMAP_LOCK(pmap); 2158 pte_enter(mmu, pmap, m, addr, 2159 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2160 __syncicache((void *)addr, PAGE_SIZE); 2161 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2162 PMAP_UNLOCK(pmap); 2163 } else 2164 __syncicache((void *)va, PAGE_SIZE); 2165 } 2166 va += PAGE_SIZE; 2167 sz -= PAGE_SIZE; 2168 } 2169 rw_wunlock(&pvh_global_lock); 2170 } 2171 2172 /* 2173 * Atomically extract and hold the physical page with the given 2174 * pmap and virtual address pair if that mapping permits the given 2175 * protection. 2176 */ 2177 static vm_page_t 2178 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2179 vm_prot_t prot) 2180 { 2181 pte_t *pte; 2182 vm_page_t m; 2183 uint32_t pte_wbit; 2184 vm_paddr_t pa; 2185 2186 m = NULL; 2187 pa = 0; 2188 PMAP_LOCK(pmap); 2189 retry: 2190 pte = pte_find(mmu, pmap, va); 2191 if ((pte != NULL) && PTE_ISVALID(pte)) { 2192 if (pmap == kernel_pmap) 2193 pte_wbit = PTE_SW; 2194 else 2195 pte_wbit = PTE_UW; 2196 2197 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2198 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2199 goto retry; 2200 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2201 vm_page_hold(m); 2202 } 2203 } 2204 2205 PA_UNLOCK_COND(pa); 2206 PMAP_UNLOCK(pmap); 2207 return (m); 2208 } 2209 2210 /* 2211 * Initialize a vm_page's machine-dependent fields. 2212 */ 2213 static void 2214 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2215 { 2216 2217 TAILQ_INIT(&m->md.pv_list); 2218 } 2219 2220 /* 2221 * mmu_booke_zero_page_area zeros the specified hardware page by 2222 * mapping it into virtual memory and using bzero to clear 2223 * its contents. 2224 * 2225 * off and size must reside within a single page. 2226 */ 2227 static void 2228 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2229 { 2230 vm_offset_t va; 2231 2232 /* XXX KASSERT off and size are within a single page? */ 2233 2234 mtx_lock(&zero_page_mutex); 2235 va = zero_page_va; 2236 2237 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2238 bzero((caddr_t)va + off, size); 2239 mmu_booke_kremove(mmu, va); 2240 2241 mtx_unlock(&zero_page_mutex); 2242 } 2243 2244 /* 2245 * mmu_booke_zero_page zeros the specified hardware page. 2246 */ 2247 static void 2248 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2249 { 2250 vm_offset_t off, va; 2251 2252 mtx_lock(&zero_page_mutex); 2253 va = zero_page_va; 2254 2255 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2256 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2257 __asm __volatile("dcbzl 0,%0" :: "r"(va + off)); 2258 mmu_booke_kremove(mmu, va); 2259 2260 mtx_unlock(&zero_page_mutex); 2261 } 2262 2263 /* 2264 * mmu_booke_copy_page copies the specified (machine independent) page by 2265 * mapping the page into virtual memory and using memcopy to copy the page, 2266 * one machine dependent page at a time. 2267 */ 2268 static void 2269 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2270 { 2271 vm_offset_t sva, dva; 2272 2273 sva = copy_page_src_va; 2274 dva = copy_page_dst_va; 2275 2276 mtx_lock(©_page_mutex); 2277 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2278 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2279 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2280 mmu_booke_kremove(mmu, dva); 2281 mmu_booke_kremove(mmu, sva); 2282 mtx_unlock(©_page_mutex); 2283 } 2284 2285 static inline void 2286 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2287 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2288 { 2289 void *a_cp, *b_cp; 2290 vm_offset_t a_pg_offset, b_pg_offset; 2291 int cnt; 2292 2293 mtx_lock(©_page_mutex); 2294 while (xfersize > 0) { 2295 a_pg_offset = a_offset & PAGE_MASK; 2296 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2297 mmu_booke_kenter(mmu, copy_page_src_va, 2298 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2299 a_cp = (char *)copy_page_src_va + a_pg_offset; 2300 b_pg_offset = b_offset & PAGE_MASK; 2301 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2302 mmu_booke_kenter(mmu, copy_page_dst_va, 2303 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2304 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2305 bcopy(a_cp, b_cp, cnt); 2306 mmu_booke_kremove(mmu, copy_page_dst_va); 2307 mmu_booke_kremove(mmu, copy_page_src_va); 2308 a_offset += cnt; 2309 b_offset += cnt; 2310 xfersize -= cnt; 2311 } 2312 mtx_unlock(©_page_mutex); 2313 } 2314 2315 /* 2316 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2317 * into virtual memory and using bzero to clear its contents. This is intended 2318 * to be called from the vm_pagezero process only and outside of Giant. No 2319 * lock is required. 2320 */ 2321 static void 2322 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2323 { 2324 vm_offset_t va; 2325 2326 va = zero_page_idle_va; 2327 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2328 bzero((caddr_t)va, PAGE_SIZE); 2329 mmu_booke_kremove(mmu, va); 2330 } 2331 2332 static vm_offset_t 2333 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2334 { 2335 vm_paddr_t paddr; 2336 vm_offset_t qaddr; 2337 uint32_t flags; 2338 pte_t *pte; 2339 2340 paddr = VM_PAGE_TO_PHYS(m); 2341 2342 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2343 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)); 2344 2345 critical_enter(); 2346 qaddr = PCPU_GET(qmap_addr); 2347 2348 pte = pte_find(mmu, kernel_pmap, qaddr); 2349 2350 KASSERT(pte->flags == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2351 2352 /* 2353 * XXX: tlbivax is broadcast to other cores, but qaddr should 2354 * not be present in other TLBs. Is there a better instruction 2355 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2356 */ 2357 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2358 __asm __volatile("isync; msync"); 2359 2360 pte->rpn = paddr & ~PTE_PA_MASK; 2361 pte->flags = flags; 2362 2363 /* Flush the real memory from the instruction cache. */ 2364 if ((flags & (PTE_I | PTE_G)) == 0) 2365 __syncicache((void *)qaddr, PAGE_SIZE); 2366 2367 return (qaddr); 2368 } 2369 2370 static void 2371 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2372 { 2373 pte_t *pte; 2374 2375 pte = pte_find(mmu, kernel_pmap, addr); 2376 2377 KASSERT(PCPU_GET(qmap_addr) == addr, 2378 ("mmu_booke_quick_remove_page: invalid address")); 2379 KASSERT(pte->flags != 0, 2380 ("mmu_booke_quick_remove_page: PTE not in use")); 2381 2382 pte->flags = 0; 2383 pte->rpn = 0; 2384 critical_exit(); 2385 } 2386 2387 /* 2388 * Return whether or not the specified physical page was modified 2389 * in any of physical maps. 2390 */ 2391 static boolean_t 2392 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2393 { 2394 pte_t *pte; 2395 pv_entry_t pv; 2396 boolean_t rv; 2397 2398 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2399 ("mmu_booke_is_modified: page %p is not managed", m)); 2400 rv = FALSE; 2401 2402 /* 2403 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2404 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2405 * is clear, no PTEs can be modified. 2406 */ 2407 VM_OBJECT_ASSERT_WLOCKED(m->object); 2408 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2409 return (rv); 2410 rw_wlock(&pvh_global_lock); 2411 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2412 PMAP_LOCK(pv->pv_pmap); 2413 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2414 PTE_ISVALID(pte)) { 2415 if (PTE_ISMODIFIED(pte)) 2416 rv = TRUE; 2417 } 2418 PMAP_UNLOCK(pv->pv_pmap); 2419 if (rv) 2420 break; 2421 } 2422 rw_wunlock(&pvh_global_lock); 2423 return (rv); 2424 } 2425 2426 /* 2427 * Return whether or not the specified virtual address is eligible 2428 * for prefault. 2429 */ 2430 static boolean_t 2431 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2432 { 2433 2434 return (FALSE); 2435 } 2436 2437 /* 2438 * Return whether or not the specified physical page was referenced 2439 * in any physical maps. 2440 */ 2441 static boolean_t 2442 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2443 { 2444 pte_t *pte; 2445 pv_entry_t pv; 2446 boolean_t rv; 2447 2448 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2449 ("mmu_booke_is_referenced: page %p is not managed", m)); 2450 rv = FALSE; 2451 rw_wlock(&pvh_global_lock); 2452 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2453 PMAP_LOCK(pv->pv_pmap); 2454 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2455 PTE_ISVALID(pte)) { 2456 if (PTE_ISREFERENCED(pte)) 2457 rv = TRUE; 2458 } 2459 PMAP_UNLOCK(pv->pv_pmap); 2460 if (rv) 2461 break; 2462 } 2463 rw_wunlock(&pvh_global_lock); 2464 return (rv); 2465 } 2466 2467 /* 2468 * Clear the modify bits on the specified physical page. 2469 */ 2470 static void 2471 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2472 { 2473 pte_t *pte; 2474 pv_entry_t pv; 2475 2476 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2477 ("mmu_booke_clear_modify: page %p is not managed", m)); 2478 VM_OBJECT_ASSERT_WLOCKED(m->object); 2479 KASSERT(!vm_page_xbusied(m), 2480 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2481 2482 /* 2483 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2484 * If the object containing the page is locked and the page is not 2485 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2486 */ 2487 if ((m->aflags & PGA_WRITEABLE) == 0) 2488 return; 2489 rw_wlock(&pvh_global_lock); 2490 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2491 PMAP_LOCK(pv->pv_pmap); 2492 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2493 PTE_ISVALID(pte)) { 2494 mtx_lock_spin(&tlbivax_mutex); 2495 tlb_miss_lock(); 2496 2497 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2498 tlb0_flush_entry(pv->pv_va); 2499 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2500 PTE_REFERENCED); 2501 } 2502 2503 tlb_miss_unlock(); 2504 mtx_unlock_spin(&tlbivax_mutex); 2505 } 2506 PMAP_UNLOCK(pv->pv_pmap); 2507 } 2508 rw_wunlock(&pvh_global_lock); 2509 } 2510 2511 /* 2512 * Return a count of reference bits for a page, clearing those bits. 2513 * It is not necessary for every reference bit to be cleared, but it 2514 * is necessary that 0 only be returned when there are truly no 2515 * reference bits set. 2516 * 2517 * XXX: The exact number of bits to check and clear is a matter that 2518 * should be tested and standardized at some point in the future for 2519 * optimal aging of shared pages. 2520 */ 2521 static int 2522 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2523 { 2524 pte_t *pte; 2525 pv_entry_t pv; 2526 int count; 2527 2528 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2529 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2530 count = 0; 2531 rw_wlock(&pvh_global_lock); 2532 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2533 PMAP_LOCK(pv->pv_pmap); 2534 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2535 PTE_ISVALID(pte)) { 2536 if (PTE_ISREFERENCED(pte)) { 2537 mtx_lock_spin(&tlbivax_mutex); 2538 tlb_miss_lock(); 2539 2540 tlb0_flush_entry(pv->pv_va); 2541 pte->flags &= ~PTE_REFERENCED; 2542 2543 tlb_miss_unlock(); 2544 mtx_unlock_spin(&tlbivax_mutex); 2545 2546 if (++count > 4) { 2547 PMAP_UNLOCK(pv->pv_pmap); 2548 break; 2549 } 2550 } 2551 } 2552 PMAP_UNLOCK(pv->pv_pmap); 2553 } 2554 rw_wunlock(&pvh_global_lock); 2555 return (count); 2556 } 2557 2558 /* 2559 * Clear the wired attribute from the mappings for the specified range of 2560 * addresses in the given pmap. Every valid mapping within that range must 2561 * have the wired attribute set. In contrast, invalid mappings cannot have 2562 * the wired attribute set, so they are ignored. 2563 * 2564 * The wired attribute of the page table entry is not a hardware feature, so 2565 * there is no need to invalidate any TLB entries. 2566 */ 2567 static void 2568 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2569 { 2570 vm_offset_t va; 2571 pte_t *pte; 2572 2573 PMAP_LOCK(pmap); 2574 for (va = sva; va < eva; va += PAGE_SIZE) { 2575 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2576 PTE_ISVALID(pte)) { 2577 if (!PTE_ISWIRED(pte)) 2578 panic("mmu_booke_unwire: pte %p isn't wired", 2579 pte); 2580 pte->flags &= ~PTE_WIRED; 2581 pmap->pm_stats.wired_count--; 2582 } 2583 } 2584 PMAP_UNLOCK(pmap); 2585 2586 } 2587 2588 /* 2589 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2590 * page. This count may be changed upwards or downwards in the future; it is 2591 * only necessary that true be returned for a small subset of pmaps for proper 2592 * page aging. 2593 */ 2594 static boolean_t 2595 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2596 { 2597 pv_entry_t pv; 2598 int loops; 2599 boolean_t rv; 2600 2601 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2602 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2603 loops = 0; 2604 rv = FALSE; 2605 rw_wlock(&pvh_global_lock); 2606 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2607 if (pv->pv_pmap == pmap) { 2608 rv = TRUE; 2609 break; 2610 } 2611 if (++loops >= 16) 2612 break; 2613 } 2614 rw_wunlock(&pvh_global_lock); 2615 return (rv); 2616 } 2617 2618 /* 2619 * Return the number of managed mappings to the given physical page that are 2620 * wired. 2621 */ 2622 static int 2623 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2624 { 2625 pv_entry_t pv; 2626 pte_t *pte; 2627 int count = 0; 2628 2629 if ((m->oflags & VPO_UNMANAGED) != 0) 2630 return (count); 2631 rw_wlock(&pvh_global_lock); 2632 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2633 PMAP_LOCK(pv->pv_pmap); 2634 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2635 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2636 count++; 2637 PMAP_UNLOCK(pv->pv_pmap); 2638 } 2639 rw_wunlock(&pvh_global_lock); 2640 return (count); 2641 } 2642 2643 static int 2644 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2645 { 2646 int i; 2647 vm_offset_t va; 2648 2649 /* 2650 * This currently does not work for entries that 2651 * overlap TLB1 entries. 2652 */ 2653 for (i = 0; i < tlb1_idx; i ++) { 2654 if (tlb1_iomapped(i, pa, size, &va) == 0) 2655 return (0); 2656 } 2657 2658 return (EFAULT); 2659 } 2660 2661 void 2662 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2663 { 2664 vm_paddr_t ppa; 2665 vm_offset_t ofs; 2666 vm_size_t gran; 2667 2668 /* Minidumps are based on virtual memory addresses. */ 2669 if (do_minidump) { 2670 *va = (void *)(vm_offset_t)pa; 2671 return; 2672 } 2673 2674 /* Raw physical memory dumps don't have a virtual address. */ 2675 /* We always map a 256MB page at 256M. */ 2676 gran = 256 * 1024 * 1024; 2677 ppa = pa & ~(gran - 1); 2678 ofs = pa - ppa; 2679 *va = (void *)gran; 2680 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2681 2682 if (sz > (gran - ofs)) 2683 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2684 _TLB_ENTRY_IO); 2685 } 2686 2687 void 2688 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2689 { 2690 vm_paddr_t ppa; 2691 vm_offset_t ofs; 2692 vm_size_t gran; 2693 2694 /* Minidumps are based on virtual memory addresses. */ 2695 /* Nothing to do... */ 2696 if (do_minidump) 2697 return; 2698 2699 /* Raw physical memory dumps don't have a virtual address. */ 2700 tlb1_idx--; 2701 tlb1[tlb1_idx].mas1 = 0; 2702 tlb1[tlb1_idx].mas2 = 0; 2703 tlb1[tlb1_idx].mas3 = 0; 2704 tlb1_write_entry(tlb1_idx); 2705 2706 gran = 256 * 1024 * 1024; 2707 ppa = pa & ~(gran - 1); 2708 ofs = pa - ppa; 2709 if (sz > (gran - ofs)) { 2710 tlb1_idx--; 2711 tlb1[tlb1_idx].mas1 = 0; 2712 tlb1[tlb1_idx].mas2 = 0; 2713 tlb1[tlb1_idx].mas3 = 0; 2714 tlb1_write_entry(tlb1_idx); 2715 } 2716 } 2717 2718 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2719 2720 void 2721 mmu_booke_scan_init(mmu_t mmu) 2722 { 2723 vm_offset_t va; 2724 pte_t *pte; 2725 int i; 2726 2727 if (!do_minidump) { 2728 /* Initialize phys. segments for dumpsys(). */ 2729 memset(&dump_map, 0, sizeof(dump_map)); 2730 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2731 &availmem_regions_sz); 2732 for (i = 0; i < physmem_regions_sz; i++) { 2733 dump_map[i].pa_start = physmem_regions[i].mr_start; 2734 dump_map[i].pa_size = physmem_regions[i].mr_size; 2735 } 2736 return; 2737 } 2738 2739 /* Virtual segments for minidumps: */ 2740 memset(&dump_map, 0, sizeof(dump_map)); 2741 2742 /* 1st: kernel .data and .bss. */ 2743 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2744 dump_map[0].pa_size = 2745 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2746 2747 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2748 dump_map[1].pa_start = data_start; 2749 dump_map[1].pa_size = data_end - data_start; 2750 2751 /* 3rd: kernel VM. */ 2752 va = dump_map[1].pa_start + dump_map[1].pa_size; 2753 /* Find start of next chunk (from va). */ 2754 while (va < virtual_end) { 2755 /* Don't dump the buffer cache. */ 2756 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2757 va = kmi.buffer_eva; 2758 continue; 2759 } 2760 pte = pte_find(mmu, kernel_pmap, va); 2761 if (pte != NULL && PTE_ISVALID(pte)) 2762 break; 2763 va += PAGE_SIZE; 2764 } 2765 if (va < virtual_end) { 2766 dump_map[2].pa_start = va; 2767 va += PAGE_SIZE; 2768 /* Find last page in chunk. */ 2769 while (va < virtual_end) { 2770 /* Don't run into the buffer cache. */ 2771 if (va == kmi.buffer_sva) 2772 break; 2773 pte = pte_find(mmu, kernel_pmap, va); 2774 if (pte == NULL || !PTE_ISVALID(pte)) 2775 break; 2776 va += PAGE_SIZE; 2777 } 2778 dump_map[2].pa_size = va - dump_map[2].pa_start; 2779 } 2780 } 2781 2782 /* 2783 * Map a set of physical memory pages into the kernel virtual address space. 2784 * Return a pointer to where it is mapped. This routine is intended to be used 2785 * for mapping device memory, NOT real memory. 2786 */ 2787 static void * 2788 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2789 { 2790 2791 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2792 } 2793 2794 static void * 2795 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2796 { 2797 void *res; 2798 uintptr_t va; 2799 vm_size_t sz; 2800 int i; 2801 2802 /* 2803 * Check if this is premapped in TLB1. Note: this should probably also 2804 * check whether a sequence of TLB1 entries exist that match the 2805 * requirement, but now only checks the easy case. 2806 */ 2807 if (ma == VM_MEMATTR_DEFAULT) { 2808 for (i = 0; i < tlb1_idx; i++) { 2809 if (!(tlb1[i].mas1 & MAS1_VALID)) 2810 continue; 2811 if (pa >= tlb1[i].phys && 2812 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2813 return (void *)(tlb1[i].virt + 2814 (vm_offset_t)(pa - tlb1[i].phys)); 2815 } 2816 } 2817 2818 size = roundup(size, PAGE_SIZE); 2819 2820 /* 2821 * We leave a hole for device direct mapping between the maximum user 2822 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2823 * devices are in there, just map them 1:1. If not, map them to the 2824 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2825 * addresses should be pulled from an allocator, but since we do not 2826 * ever free TLB1 entries, it is safe just to increment a counter. 2827 * Note that there isn't a lot of address space here (128 MB) and it 2828 * is not at all difficult to imagine running out, since that is a 4:1 2829 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2830 * mapped there. 2831 */ 2832 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2833 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2834 va = pa; 2835 else 2836 va = atomic_fetchadd_int(&tlb1_map_base, size); 2837 res = (void *)va; 2838 2839 do { 2840 sz = 1 << (ilog2(size) & ~1); 2841 if (va % sz != 0) { 2842 do { 2843 sz >>= 2; 2844 } while (va % sz != 0); 2845 } 2846 if (bootverbose) 2847 printf("Wiring VA=%x to PA=%jx (size=%x), " 2848 "using TLB1[%d]\n", va, (uintmax_t)pa, sz, tlb1_idx); 2849 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2850 size -= sz; 2851 pa += sz; 2852 va += sz; 2853 } while (size > 0); 2854 2855 return (res); 2856 } 2857 2858 /* 2859 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2860 */ 2861 static void 2862 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2863 { 2864 #ifdef SUPPORTS_SHRINKING_TLB1 2865 vm_offset_t base, offset; 2866 2867 /* 2868 * Unmap only if this is inside kernel virtual space. 2869 */ 2870 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2871 base = trunc_page(va); 2872 offset = va & PAGE_MASK; 2873 size = roundup(offset + size, PAGE_SIZE); 2874 kva_free(base, size); 2875 } 2876 #endif 2877 } 2878 2879 /* 2880 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2881 * specified pmap. This eliminates the blast of soft faults on process startup 2882 * and immediately after an mmap. 2883 */ 2884 static void 2885 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2886 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2887 { 2888 2889 VM_OBJECT_ASSERT_WLOCKED(object); 2890 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2891 ("mmu_booke_object_init_pt: non-device object")); 2892 } 2893 2894 /* 2895 * Perform the pmap work for mincore. 2896 */ 2897 static int 2898 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2899 vm_paddr_t *locked_pa) 2900 { 2901 2902 /* XXX: this should be implemented at some point */ 2903 return (0); 2904 } 2905 2906 /**************************************************************************/ 2907 /* TID handling */ 2908 /**************************************************************************/ 2909 2910 /* 2911 * Allocate a TID. If necessary, steal one from someone else. 2912 * The new TID is flushed from the TLB before returning. 2913 */ 2914 static tlbtid_t 2915 tid_alloc(pmap_t pmap) 2916 { 2917 tlbtid_t tid; 2918 int thiscpu; 2919 2920 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2921 2922 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2923 2924 thiscpu = PCPU_GET(cpuid); 2925 2926 tid = PCPU_GET(tid_next); 2927 if (tid > TID_MAX) 2928 tid = TID_MIN; 2929 PCPU_SET(tid_next, tid + 1); 2930 2931 /* If we are stealing TID then clear the relevant pmap's field */ 2932 if (tidbusy[thiscpu][tid] != NULL) { 2933 2934 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2935 2936 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2937 2938 /* Flush all entries from TLB0 matching this TID. */ 2939 tid_flush(tid); 2940 } 2941 2942 tidbusy[thiscpu][tid] = pmap; 2943 pmap->pm_tid[thiscpu] = tid; 2944 __asm __volatile("msync; isync"); 2945 2946 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2947 PCPU_GET(tid_next)); 2948 2949 return (tid); 2950 } 2951 2952 /**************************************************************************/ 2953 /* TLB0 handling */ 2954 /**************************************************************************/ 2955 2956 static void 2957 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2958 uint32_t mas7) 2959 { 2960 int as; 2961 char desc[3]; 2962 tlbtid_t tid; 2963 vm_size_t size; 2964 unsigned int tsize; 2965 2966 desc[2] = '\0'; 2967 if (mas1 & MAS1_VALID) 2968 desc[0] = 'V'; 2969 else 2970 desc[0] = ' '; 2971 2972 if (mas1 & MAS1_IPROT) 2973 desc[1] = 'P'; 2974 else 2975 desc[1] = ' '; 2976 2977 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2978 tid = MAS1_GETTID(mas1); 2979 2980 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2981 size = 0; 2982 if (tsize) 2983 size = tsize2size(tsize); 2984 2985 debugf("%3d: (%s) [AS=%d] " 2986 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2987 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2988 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2989 } 2990 2991 /* Convert TLB0 va and way number to tlb0[] table index. */ 2992 static inline unsigned int 2993 tlb0_tableidx(vm_offset_t va, unsigned int way) 2994 { 2995 unsigned int idx; 2996 2997 idx = (way * TLB0_ENTRIES_PER_WAY); 2998 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2999 return (idx); 3000 } 3001 3002 /* 3003 * Invalidate TLB0 entry. 3004 */ 3005 static inline void 3006 tlb0_flush_entry(vm_offset_t va) 3007 { 3008 3009 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3010 3011 mtx_assert(&tlbivax_mutex, MA_OWNED); 3012 3013 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3014 __asm __volatile("isync; msync"); 3015 __asm __volatile("tlbsync; msync"); 3016 3017 CTR1(KTR_PMAP, "%s: e", __func__); 3018 } 3019 3020 /* Print out contents of the MAS registers for each TLB0 entry */ 3021 void 3022 tlb0_print_tlbentries(void) 3023 { 3024 uint32_t mas0, mas1, mas2, mas3, mas7; 3025 int entryidx, way, idx; 3026 3027 debugf("TLB0 entries:\n"); 3028 for (way = 0; way < TLB0_WAYS; way ++) 3029 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3030 3031 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3032 mtspr(SPR_MAS0, mas0); 3033 __asm __volatile("isync"); 3034 3035 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3036 mtspr(SPR_MAS2, mas2); 3037 3038 __asm __volatile("isync; tlbre"); 3039 3040 mas1 = mfspr(SPR_MAS1); 3041 mas2 = mfspr(SPR_MAS2); 3042 mas3 = mfspr(SPR_MAS3); 3043 mas7 = mfspr(SPR_MAS7); 3044 3045 idx = tlb0_tableidx(mas2, way); 3046 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3047 } 3048 } 3049 3050 /**************************************************************************/ 3051 /* TLB1 handling */ 3052 /**************************************************************************/ 3053 3054 /* 3055 * TLB1 mapping notes: 3056 * 3057 * TLB1[0] Kernel text and data. 3058 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3059 * windows, other devices mappings. 3060 */ 3061 3062 /* 3063 * Write given entry to TLB1 hardware. 3064 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3065 */ 3066 static void 3067 tlb1_write_entry(unsigned int idx) 3068 { 3069 uint32_t mas0; 3070 3071 //debugf("tlb1_write_entry: s\n"); 3072 3073 /* Select entry */ 3074 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3075 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3076 3077 mtspr(SPR_MAS0, mas0); 3078 __asm __volatile("isync"); 3079 mtspr(SPR_MAS1, tlb1[idx].mas1); 3080 __asm __volatile("isync"); 3081 mtspr(SPR_MAS2, tlb1[idx].mas2); 3082 __asm __volatile("isync"); 3083 mtspr(SPR_MAS3, tlb1[idx].mas3); 3084 __asm __volatile("isync"); 3085 switch ((mfpvr() >> 16) & 0xFFFF) { 3086 case FSL_E500mc: 3087 case FSL_E5500: 3088 mtspr(SPR_MAS8, 0); 3089 __asm __volatile("isync"); 3090 /* FALLTHROUGH */ 3091 case FSL_E500v2: 3092 mtspr(SPR_MAS7, tlb1[idx].mas7); 3093 __asm __volatile("isync"); 3094 break; 3095 default: 3096 break; 3097 } 3098 3099 __asm __volatile("tlbwe; isync; msync"); 3100 3101 //debugf("tlb1_write_entry: e\n"); 3102 } 3103 3104 /* 3105 * Return the largest uint value log such that 2^log <= num. 3106 */ 3107 static unsigned int 3108 ilog2(unsigned int num) 3109 { 3110 int lz; 3111 3112 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3113 return (31 - lz); 3114 } 3115 3116 /* 3117 * Convert TLB TSIZE value to mapped region size. 3118 */ 3119 static vm_size_t 3120 tsize2size(unsigned int tsize) 3121 { 3122 3123 /* 3124 * size = 4^tsize KB 3125 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3126 */ 3127 3128 return ((1 << (2 * tsize)) * 1024); 3129 } 3130 3131 /* 3132 * Convert region size (must be power of 4) to TLB TSIZE value. 3133 */ 3134 static unsigned int 3135 size2tsize(vm_size_t size) 3136 { 3137 3138 return (ilog2(size) / 2 - 5); 3139 } 3140 3141 /* 3142 * Register permanent kernel mapping in TLB1. 3143 * 3144 * Entries are created starting from index 0 (current free entry is 3145 * kept in tlb1_idx) and are not supposed to be invalidated. 3146 */ 3147 static int 3148 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3149 uint32_t flags) 3150 { 3151 uint32_t ts, tid; 3152 int tsize, index; 3153 3154 index = atomic_fetchadd_int(&tlb1_idx, 1); 3155 if (index >= TLB1_ENTRIES) { 3156 printf("tlb1_set_entry: TLB1 full!\n"); 3157 return (-1); 3158 } 3159 3160 /* Convert size to TSIZE */ 3161 tsize = size2tsize(size); 3162 3163 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3164 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3165 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3166 3167 /* 3168 * Atomicity is preserved by the atomic increment above since nothing 3169 * is ever removed from tlb1. 3170 */ 3171 3172 tlb1[index].phys = pa; 3173 tlb1[index].virt = va; 3174 tlb1[index].size = size; 3175 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3176 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3177 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3178 3179 /* Set supervisor RWX permission bits */ 3180 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3181 tlb1[index].mas7 = (pa >> 32) & MAS7_RPN; 3182 3183 tlb1_write_entry(index); 3184 3185 /* 3186 * XXX in general TLB1 updates should be propagated between CPUs, 3187 * since current design assumes to have the same TLB1 set-up on all 3188 * cores. 3189 */ 3190 return (0); 3191 } 3192 3193 /* 3194 * Map in contiguous RAM region into the TLB1 using maximum of 3195 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3196 * 3197 * If necessary round up last entry size and return total size 3198 * used by all allocated entries. 3199 */ 3200 vm_size_t 3201 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3202 { 3203 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3204 vm_size_t mapped, pgsz, base, mask; 3205 int idx, nents; 3206 3207 /* Round up to the next 1M */ 3208 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3209 3210 mapped = 0; 3211 idx = 0; 3212 base = va; 3213 pgsz = 64*1024*1024; 3214 while (mapped < size) { 3215 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3216 while (pgsz > (size - mapped)) 3217 pgsz >>= 2; 3218 pgs[idx++] = pgsz; 3219 mapped += pgsz; 3220 } 3221 3222 /* We under-map. Correct for this. */ 3223 if (mapped < size) { 3224 while (pgs[idx - 1] == pgsz) { 3225 idx--; 3226 mapped -= pgsz; 3227 } 3228 /* XXX We may increase beyond out starting point. */ 3229 pgsz <<= 2; 3230 pgs[idx++] = pgsz; 3231 mapped += pgsz; 3232 } 3233 } 3234 3235 nents = idx; 3236 mask = pgs[0] - 1; 3237 /* Align address to the boundary */ 3238 if (va & mask) { 3239 va = (va + mask) & ~mask; 3240 pa = (pa + mask) & ~mask; 3241 } 3242 3243 for (idx = 0; idx < nents; idx++) { 3244 pgsz = pgs[idx]; 3245 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3246 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3247 pa += pgsz; 3248 va += pgsz; 3249 } 3250 3251 mapped = (va - base); 3252 #ifdef __powerpc64__ 3253 printf("mapped size 0x%016lx (wasted space 0x%16lx)\n", 3254 #else 3255 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3256 #endif 3257 mapped, mapped - size); 3258 return (mapped); 3259 } 3260 3261 /* 3262 * TLB1 initialization routine, to be called after the very first 3263 * assembler level setup done in locore.S. 3264 */ 3265 void 3266 tlb1_init() 3267 { 3268 uint32_t mas0, mas1, mas2, mas3, mas7; 3269 uint32_t tsz; 3270 int i; 3271 3272 tlb1_idx = 1; 3273 3274 tlb1_get_tlbconf(); 3275 3276 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3277 mtspr(SPR_MAS0, mas0); 3278 __asm __volatile("isync; tlbre"); 3279 3280 mas1 = mfspr(SPR_MAS1); 3281 mas2 = mfspr(SPR_MAS2); 3282 mas3 = mfspr(SPR_MAS3); 3283 mas7 = mfspr(SPR_MAS7); 3284 3285 tlb1[0].mas1 = mas1; 3286 tlb1[0].mas2 = mfspr(SPR_MAS2); 3287 tlb1[0].mas3 = mas3; 3288 tlb1[0].mas7 = mas7; 3289 tlb1[0].virt = mas2 & MAS2_EPN_MASK; 3290 tlb1[0].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3291 (mas3 & MAS3_RPN); 3292 3293 kernload = tlb1[0].phys; 3294 3295 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3296 tlb1[0].size = (tsz > 0) ? tsize2size(tsz) : 0; 3297 kernsize += tlb1[0].size; 3298 3299 #ifdef SMP 3300 bp_ntlb1s = tlb1_idx; 3301 #endif 3302 3303 /* Purge the remaining entries */ 3304 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3305 tlb1_write_entry(i); 3306 3307 /* Setup TLB miss defaults */ 3308 set_mas4_defaults(); 3309 } 3310 3311 vm_offset_t 3312 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3313 { 3314 vm_paddr_t pa_base; 3315 vm_offset_t va, sz; 3316 int i; 3317 3318 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3319 3320 for (i = 0; i < tlb1_idx; i++) { 3321 if (!(tlb1[i].mas1 & MAS1_VALID)) 3322 continue; 3323 if (pa >= tlb1[i].phys && (pa + size) <= 3324 (tlb1[i].phys + tlb1[i].size)) 3325 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3326 } 3327 3328 pa_base = rounddown(pa, PAGE_SIZE); 3329 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3330 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3331 va = tlb1_map_base + (pa - pa_base); 3332 3333 do { 3334 sz = 1 << (ilog2(size) & ~1); 3335 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3336 size -= sz; 3337 pa_base += sz; 3338 tlb1_map_base += sz; 3339 } while (size > 0); 3340 3341 #ifdef SMP 3342 bp_ntlb1s = tlb1_idx; 3343 #endif 3344 3345 return (va); 3346 } 3347 3348 /* 3349 * Setup MAS4 defaults. 3350 * These values are loaded to MAS0-2 on a TLB miss. 3351 */ 3352 static void 3353 set_mas4_defaults(void) 3354 { 3355 uint32_t mas4; 3356 3357 /* Defaults: TLB0, PID0, TSIZED=4K */ 3358 mas4 = MAS4_TLBSELD0; 3359 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3360 #ifdef SMP 3361 mas4 |= MAS4_MD; 3362 #endif 3363 mtspr(SPR_MAS4, mas4); 3364 __asm __volatile("isync"); 3365 } 3366 3367 /* 3368 * Print out contents of the MAS registers for each TLB1 entry 3369 */ 3370 void 3371 tlb1_print_tlbentries(void) 3372 { 3373 uint32_t mas0, mas1, mas2, mas3, mas7; 3374 int i; 3375 3376 debugf("TLB1 entries:\n"); 3377 for (i = 0; i < TLB1_ENTRIES; i++) { 3378 3379 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3380 mtspr(SPR_MAS0, mas0); 3381 3382 __asm __volatile("isync; tlbre"); 3383 3384 mas1 = mfspr(SPR_MAS1); 3385 mas2 = mfspr(SPR_MAS2); 3386 mas3 = mfspr(SPR_MAS3); 3387 mas7 = mfspr(SPR_MAS7); 3388 3389 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3390 } 3391 } 3392 3393 /* 3394 * Print out contents of the in-ram tlb1 table. 3395 */ 3396 void 3397 tlb1_print_entries(void) 3398 { 3399 int i; 3400 3401 debugf("tlb1[] table entries:\n"); 3402 for (i = 0; i < TLB1_ENTRIES; i++) 3403 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 3404 tlb1[i].mas7); 3405 } 3406 3407 /* 3408 * Return 0 if the physical IO range is encompassed by one of the 3409 * the TLB1 entries, otherwise return related error code. 3410 */ 3411 static int 3412 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3413 { 3414 uint32_t prot; 3415 vm_paddr_t pa_start; 3416 vm_paddr_t pa_end; 3417 unsigned int entry_tsize; 3418 vm_size_t entry_size; 3419 3420 *va = (vm_offset_t)NULL; 3421 3422 /* Skip invalid entries */ 3423 if (!(tlb1[i].mas1 & MAS1_VALID)) 3424 return (EINVAL); 3425 3426 /* 3427 * The entry must be cache-inhibited, guarded, and r/w 3428 * so it can function as an i/o page 3429 */ 3430 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3431 if (prot != (MAS2_I | MAS2_G)) 3432 return (EPERM); 3433 3434 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3435 if (prot != (MAS3_SR | MAS3_SW)) 3436 return (EPERM); 3437 3438 /* The address should be within the entry range. */ 3439 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3440 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3441 3442 entry_size = tsize2size(entry_tsize); 3443 pa_start = (((vm_paddr_t)tlb1[i].mas7 & MAS7_RPN) << 32) | 3444 (tlb1[i].mas3 & MAS3_RPN); 3445 pa_end = pa_start + entry_size; 3446 3447 if ((pa < pa_start) || ((pa + size) > pa_end)) 3448 return (ERANGE); 3449 3450 /* Return virtual address of this mapping. */ 3451 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3452 return (0); 3453 } 3454 3455 /* 3456 * Invalidate all TLB0 entries which match the given TID. Note this is 3457 * dedicated for cases when invalidations should NOT be propagated to other 3458 * CPUs. 3459 */ 3460 static void 3461 tid_flush(tlbtid_t tid) 3462 { 3463 register_t msr; 3464 uint32_t mas0, mas1, mas2; 3465 int entry, way; 3466 3467 3468 /* Don't evict kernel translations */ 3469 if (tid == TID_KERNEL) 3470 return; 3471 3472 msr = mfmsr(); 3473 __asm __volatile("wrteei 0"); 3474 3475 for (way = 0; way < TLB0_WAYS; way++) 3476 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3477 3478 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3479 mtspr(SPR_MAS0, mas0); 3480 __asm __volatile("isync"); 3481 3482 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3483 mtspr(SPR_MAS2, mas2); 3484 3485 __asm __volatile("isync; tlbre"); 3486 3487 mas1 = mfspr(SPR_MAS1); 3488 3489 if (!(mas1 & MAS1_VALID)) 3490 continue; 3491 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3492 continue; 3493 mas1 &= ~MAS1_VALID; 3494 mtspr(SPR_MAS1, mas1); 3495 __asm __volatile("isync; tlbwe; isync; msync"); 3496 } 3497 mtmsr(msr); 3498 } 3499