1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * 32-bit pmap: 40 * Virtual address space layout: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA 47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 51 * 52 * 64-bit pmap: 53 * Virtual address space layout: 54 * ----------------------------- 55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process 56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries 57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region 58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack 59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved 60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data 61 * endkernel - msgbufp-1 : flat device tree 62 * msgbufp - ptbl_bufs-1 : message buffer 63 * ptbl_bufs - kernel_pdir-1 : kernel page tables 64 * kernel_pdir - kernel_pp2d-1 : kernel page directory 65 * kernel_pp2d - . : kernel pointers to page directory 66 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy 67 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs 68 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables 69 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space 70 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region 71 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region 72 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map 73 * 0xf000_0000_0000_0000 - +Maxmem : physmem map 74 * - 0xffff_ffff_ffff_ffff : device direct map 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include "opt_ddb.h" 81 #include "opt_kstack_pages.h" 82 83 #include <sys/param.h> 84 #include <sys/conf.h> 85 #include <sys/malloc.h> 86 #include <sys/ktr.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 #include <sys/systm.h> 91 #include <sys/kernel.h> 92 #include <sys/kerneldump.h> 93 #include <sys/linker.h> 94 #include <sys/msgbuf.h> 95 #include <sys/lock.h> 96 #include <sys/mutex.h> 97 #include <sys/rwlock.h> 98 #include <sys/sched.h> 99 #include <sys/smp.h> 100 #include <sys/vmmeter.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_page.h> 104 #include <vm/vm_kern.h> 105 #include <vm/vm_pageout.h> 106 #include <vm/vm_extern.h> 107 #include <vm/vm_object.h> 108 #include <vm/vm_param.h> 109 #include <vm/vm_map.h> 110 #include <vm/vm_pager.h> 111 #include <vm/vm_phys.h> 112 #include <vm/vm_pagequeue.h> 113 #include <vm/uma.h> 114 115 #include <machine/_inttypes.h> 116 #include <machine/cpu.h> 117 #include <machine/pcb.h> 118 #include <machine/platform.h> 119 120 #include <machine/tlb.h> 121 #include <machine/spr.h> 122 #include <machine/md_var.h> 123 #include <machine/mmuvar.h> 124 #include <machine/pmap.h> 125 #include <machine/pte.h> 126 127 #include <ddb/ddb.h> 128 129 #include "mmu_if.h" 130 131 #define SPARSE_MAPDEV 132 #ifdef DEBUG 133 #define debugf(fmt, args...) printf(fmt, ##args) 134 #else 135 #define debugf(fmt, args...) 136 #endif 137 138 #ifdef __powerpc64__ 139 #define PRI0ptrX "016lx" 140 #else 141 #define PRI0ptrX "08x" 142 #endif 143 144 #define TODO panic("%s: not implemented", __func__); 145 146 extern unsigned char _etext[]; 147 extern unsigned char _end[]; 148 149 extern uint32_t *bootinfo; 150 151 vm_paddr_t kernload; 152 vm_offset_t kernstart; 153 vm_size_t kernsize; 154 155 /* Message buffer and tables. */ 156 static vm_offset_t data_start; 157 static vm_size_t data_end; 158 159 /* Phys/avail memory regions. */ 160 static struct mem_region *availmem_regions; 161 static int availmem_regions_sz; 162 static struct mem_region *physmem_regions; 163 static int physmem_regions_sz; 164 165 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 166 static vm_offset_t zero_page_va; 167 static struct mtx zero_page_mutex; 168 169 static struct mtx tlbivax_mutex; 170 171 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 172 static vm_offset_t copy_page_src_va; 173 static vm_offset_t copy_page_dst_va; 174 static struct mtx copy_page_mutex; 175 176 /**************************************************************************/ 177 /* PMAP */ 178 /**************************************************************************/ 179 180 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 181 vm_prot_t, u_int flags, int8_t psind); 182 183 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 184 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 185 #ifdef __powerpc64__ 186 unsigned int kernel_pdirs; 187 #endif 188 189 /* 190 * If user pmap is processed with mmu_booke_remove and the resident count 191 * drops to 0, there are no more pages to remove, so we need not continue. 192 */ 193 #define PMAP_REMOVE_DONE(pmap) \ 194 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 195 196 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 197 extern int elf32_nxstack; 198 #endif 199 200 /**************************************************************************/ 201 /* TLB and TID handling */ 202 /**************************************************************************/ 203 204 /* Translation ID busy table */ 205 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 206 207 /* 208 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 209 * core revisions and should be read from h/w registers during early config. 210 */ 211 uint32_t tlb0_entries; 212 uint32_t tlb0_ways; 213 uint32_t tlb0_entries_per_way; 214 uint32_t tlb1_entries; 215 216 #define TLB0_ENTRIES (tlb0_entries) 217 #define TLB0_WAYS (tlb0_ways) 218 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 219 220 #define TLB1_ENTRIES (tlb1_entries) 221 222 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE; 223 224 static tlbtid_t tid_alloc(struct pmap *); 225 static void tid_flush(tlbtid_t tid); 226 227 #ifdef DDB 228 #ifdef __powerpc64__ 229 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t); 230 #else 231 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 232 #endif 233 #endif 234 235 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 236 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 237 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 238 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 239 240 static vm_size_t tsize2size(unsigned int); 241 static unsigned int size2tsize(vm_size_t); 242 static unsigned int ilog2(unsigned long); 243 244 static void set_mas4_defaults(void); 245 246 static inline void tlb0_flush_entry(vm_offset_t); 247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 248 249 /**************************************************************************/ 250 /* Page table management */ 251 /**************************************************************************/ 252 253 static struct rwlock_padalign pvh_global_lock; 254 255 /* Data for the pv entry allocation mechanism */ 256 static uma_zone_t pvzone; 257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 258 259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 260 261 #ifndef PMAP_SHPGPERPROC 262 #define PMAP_SHPGPERPROC 200 263 #endif 264 265 static void ptbl_init(void); 266 static struct ptbl_buf *ptbl_buf_alloc(void); 267 static void ptbl_buf_free(struct ptbl_buf *); 268 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 269 270 #ifdef __powerpc64__ 271 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **, 272 unsigned int, boolean_t); 273 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int); 274 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int); 275 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t); 276 #else 277 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 278 static void ptbl_free(mmu_t, pmap_t, unsigned int); 279 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 280 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 281 #endif 282 283 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 284 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 285 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 286 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 287 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t); 288 289 static pv_entry_t pv_alloc(void); 290 static void pv_free(pv_entry_t); 291 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 292 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 293 294 static void booke_pmap_init_qpages(void); 295 296 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 297 #ifdef __powerpc64__ 298 #define PTBL_BUFS (16UL * 16 * 16) 299 #else 300 #define PTBL_BUFS (128 * 16) 301 #endif 302 303 struct ptbl_buf { 304 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 305 vm_offset_t kva; /* va of mapping */ 306 }; 307 308 /* ptbl free list and a lock used for access synchronization. */ 309 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 310 static struct mtx ptbl_buf_freelist_lock; 311 312 /* Base address of kva space allocated fot ptbl bufs. */ 313 static vm_offset_t ptbl_buf_pool_vabase; 314 315 /* Pointer to ptbl_buf structures. */ 316 static struct ptbl_buf *ptbl_bufs; 317 318 #ifdef SMP 319 extern tlb_entry_t __boot_tlb1[]; 320 void pmap_bootstrap_ap(volatile uint32_t *); 321 #endif 322 323 /* 324 * Kernel MMU interface 325 */ 326 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 327 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 328 vm_size_t, vm_offset_t); 329 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 330 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 331 vm_offset_t, vm_page_t *, vm_offset_t, int); 332 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 333 vm_prot_t, u_int flags, int8_t psind); 334 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 335 vm_page_t, vm_prot_t); 336 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 337 vm_prot_t); 338 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 339 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 340 vm_prot_t); 341 static void mmu_booke_init(mmu_t); 342 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 343 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 344 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 345 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 346 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 347 int); 348 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 349 vm_paddr_t *); 350 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 351 vm_object_t, vm_pindex_t, vm_size_t); 352 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 353 static void mmu_booke_page_init(mmu_t, vm_page_t); 354 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 355 static void mmu_booke_pinit(mmu_t, pmap_t); 356 static void mmu_booke_pinit0(mmu_t, pmap_t); 357 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 358 vm_prot_t); 359 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 360 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 361 static void mmu_booke_release(mmu_t, pmap_t); 362 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 363 static void mmu_booke_remove_all(mmu_t, vm_page_t); 364 static void mmu_booke_remove_write(mmu_t, vm_page_t); 365 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 366 static void mmu_booke_zero_page(mmu_t, vm_page_t); 367 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 368 static void mmu_booke_activate(mmu_t, struct thread *); 369 static void mmu_booke_deactivate(mmu_t, struct thread *); 370 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 371 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 372 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 373 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 374 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 375 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 376 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 377 static void mmu_booke_kremove(mmu_t, vm_offset_t); 378 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 379 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 380 vm_size_t); 381 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 382 void **); 383 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 384 void *); 385 static void mmu_booke_scan_init(mmu_t); 386 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 387 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 388 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 389 vm_size_t sz, vm_memattr_t mode); 390 static int mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, 391 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 392 static int mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 393 int *is_user, vm_offset_t *decoded_addr); 394 395 396 static mmu_method_t mmu_booke_methods[] = { 397 /* pmap dispatcher interface */ 398 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 399 MMUMETHOD(mmu_copy, mmu_booke_copy), 400 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 401 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 402 MMUMETHOD(mmu_enter, mmu_booke_enter), 403 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 404 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 405 MMUMETHOD(mmu_extract, mmu_booke_extract), 406 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 407 MMUMETHOD(mmu_init, mmu_booke_init), 408 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 409 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 410 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 411 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 412 MMUMETHOD(mmu_map, mmu_booke_map), 413 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 414 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 415 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 416 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 417 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 418 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 419 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 420 MMUMETHOD(mmu_protect, mmu_booke_protect), 421 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 422 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 423 MMUMETHOD(mmu_release, mmu_booke_release), 424 MMUMETHOD(mmu_remove, mmu_booke_remove), 425 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 426 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 427 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 428 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 429 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 430 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 431 MMUMETHOD(mmu_activate, mmu_booke_activate), 432 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 433 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 434 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 435 436 /* Internal interfaces */ 437 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 438 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 439 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 440 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 441 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 442 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 443 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 444 MMUMETHOD(mmu_kremove, mmu_booke_kremove), 445 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 446 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 447 MMUMETHOD(mmu_map_user_ptr, mmu_booke_map_user_ptr), 448 MMUMETHOD(mmu_decode_kernel_ptr, mmu_booke_decode_kernel_ptr), 449 450 /* dumpsys() support */ 451 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 452 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 453 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 454 455 { 0, 0 } 456 }; 457 458 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 459 460 static __inline uint32_t 461 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 462 { 463 uint32_t attrib; 464 int i; 465 466 if (ma != VM_MEMATTR_DEFAULT) { 467 switch (ma) { 468 case VM_MEMATTR_UNCACHEABLE: 469 return (MAS2_I | MAS2_G); 470 case VM_MEMATTR_WRITE_COMBINING: 471 case VM_MEMATTR_WRITE_BACK: 472 case VM_MEMATTR_PREFETCHABLE: 473 return (MAS2_I); 474 case VM_MEMATTR_WRITE_THROUGH: 475 return (MAS2_W | MAS2_M); 476 case VM_MEMATTR_CACHEABLE: 477 return (MAS2_M); 478 } 479 } 480 481 /* 482 * Assume the page is cache inhibited and access is guarded unless 483 * it's in our available memory array. 484 */ 485 attrib = _TLB_ENTRY_IO; 486 for (i = 0; i < physmem_regions_sz; i++) { 487 if ((pa >= physmem_regions[i].mr_start) && 488 (pa < (physmem_regions[i].mr_start + 489 physmem_regions[i].mr_size))) { 490 attrib = _TLB_ENTRY_MEM; 491 break; 492 } 493 } 494 495 return (attrib); 496 } 497 498 static inline void 499 tlb_miss_lock(void) 500 { 501 #ifdef SMP 502 struct pcpu *pc; 503 504 if (!smp_started) 505 return; 506 507 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 508 if (pc != pcpup) { 509 510 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 511 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock); 512 513 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 514 ("tlb_miss_lock: tried to lock self")); 515 516 tlb_lock(pc->pc_booke.tlb_lock); 517 518 CTR1(KTR_PMAP, "%s: locked", __func__); 519 } 520 } 521 #endif 522 } 523 524 static inline void 525 tlb_miss_unlock(void) 526 { 527 #ifdef SMP 528 struct pcpu *pc; 529 530 if (!smp_started) 531 return; 532 533 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 534 if (pc != pcpup) { 535 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 536 __func__, pc->pc_cpuid); 537 538 tlb_unlock(pc->pc_booke.tlb_lock); 539 540 CTR1(KTR_PMAP, "%s: unlocked", __func__); 541 } 542 } 543 #endif 544 } 545 546 /* Return number of entries in TLB0. */ 547 static __inline void 548 tlb0_get_tlbconf(void) 549 { 550 uint32_t tlb0_cfg; 551 552 tlb0_cfg = mfspr(SPR_TLB0CFG); 553 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 554 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 555 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 556 } 557 558 /* Return number of entries in TLB1. */ 559 static __inline void 560 tlb1_get_tlbconf(void) 561 { 562 uint32_t tlb1_cfg; 563 564 tlb1_cfg = mfspr(SPR_TLB1CFG); 565 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 566 } 567 568 /**************************************************************************/ 569 /* Page table related */ 570 /**************************************************************************/ 571 572 #ifdef __powerpc64__ 573 /* Initialize pool of kva ptbl buffers. */ 574 static void 575 ptbl_init(void) 576 { 577 int i; 578 579 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 580 TAILQ_INIT(&ptbl_buf_freelist); 581 582 for (i = 0; i < PTBL_BUFS; i++) { 583 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + 584 i * MAX(PTBL_PAGES,PDIR_PAGES) * PAGE_SIZE; 585 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 586 } 587 } 588 589 /* Get an sf_buf from the freelist. */ 590 static struct ptbl_buf * 591 ptbl_buf_alloc(void) 592 { 593 struct ptbl_buf *buf; 594 595 mtx_lock(&ptbl_buf_freelist_lock); 596 buf = TAILQ_FIRST(&ptbl_buf_freelist); 597 if (buf != NULL) 598 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 599 mtx_unlock(&ptbl_buf_freelist_lock); 600 601 return (buf); 602 } 603 604 /* Return ptbl buff to free pool. */ 605 static void 606 ptbl_buf_free(struct ptbl_buf *buf) 607 { 608 mtx_lock(&ptbl_buf_freelist_lock); 609 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 610 mtx_unlock(&ptbl_buf_freelist_lock); 611 } 612 613 /* 614 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 615 */ 616 static void 617 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t * ptbl) 618 { 619 struct ptbl_buf *pbuf; 620 621 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) { 622 if (pbuf->kva == (vm_offset_t) ptbl) { 623 /* Remove from pmap ptbl buf list. */ 624 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 625 626 /* Free corresponding ptbl buf. */ 627 ptbl_buf_free(pbuf); 628 629 break; 630 } 631 } 632 } 633 634 /* Get a pointer to a PTE in a page table. */ 635 static __inline pte_t * 636 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 637 { 638 pte_t **pdir; 639 pte_t *ptbl; 640 641 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 642 643 pdir = pmap->pm_pp2d[PP2D_IDX(va)]; 644 if (!pdir) 645 return NULL; 646 ptbl = pdir[PDIR_IDX(va)]; 647 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL); 648 } 649 650 /* 651 * Search the list of allocated pdir bufs and find on list of allocated pdirs 652 */ 653 static void 654 ptbl_free_pmap_pdir(mmu_t mmu, pmap_t pmap, pte_t ** pdir) 655 { 656 struct ptbl_buf *pbuf; 657 658 TAILQ_FOREACH(pbuf, &pmap->pm_pdir_list, link) { 659 if (pbuf->kva == (vm_offset_t) pdir) { 660 /* Remove from pmap ptbl buf list. */ 661 TAILQ_REMOVE(&pmap->pm_pdir_list, pbuf, link); 662 663 /* Free corresponding pdir buf. */ 664 ptbl_buf_free(pbuf); 665 666 break; 667 } 668 } 669 } 670 /* Free pdir pages and invalidate pdir entry. */ 671 static void 672 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx) 673 { 674 pte_t **pdir; 675 vm_paddr_t pa; 676 vm_offset_t va; 677 vm_page_t m; 678 int i; 679 680 pdir = pmap->pm_pp2d[pp2d_idx]; 681 682 KASSERT((pdir != NULL), ("pdir_free: null pdir")); 683 684 pmap->pm_pp2d[pp2d_idx] = NULL; 685 686 for (i = 0; i < PDIR_PAGES; i++) { 687 va = ((vm_offset_t) pdir + (i * PAGE_SIZE)); 688 pa = pte_vatopa(mmu, kernel_pmap, va); 689 m = PHYS_TO_VM_PAGE(pa); 690 vm_page_free_zero(m); 691 vm_wire_sub(1); 692 pmap_kremove(va); 693 } 694 695 ptbl_free_pmap_pdir(mmu, pmap, pdir); 696 } 697 698 /* 699 * Decrement pdir pages hold count and attempt to free pdir pages. Called 700 * when removing directory entry from pdir. 701 * 702 * Return 1 if pdir pages were freed. 703 */ 704 static int 705 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx) 706 { 707 pte_t **pdir; 708 vm_paddr_t pa; 709 vm_page_t m; 710 int i; 711 712 KASSERT((pmap != kernel_pmap), 713 ("pdir_unhold: unholding kernel pdir!")); 714 715 pdir = pmap->pm_pp2d[pp2d_idx]; 716 717 KASSERT(((vm_offset_t) pdir >= VM_MIN_KERNEL_ADDRESS), 718 ("pdir_unhold: non kva pdir")); 719 720 /* decrement hold count */ 721 for (i = 0; i < PDIR_PAGES; i++) { 722 pa = pte_vatopa(mmu, kernel_pmap, 723 (vm_offset_t) pdir + (i * PAGE_SIZE)); 724 m = PHYS_TO_VM_PAGE(pa); 725 m->wire_count--; 726 } 727 728 /* 729 * Free pdir pages if there are no dir entries in this pdir. 730 * wire_count has the same value for all ptbl pages, so check the 731 * last page. 732 */ 733 if (m->wire_count == 0) { 734 pdir_free(mmu, pmap, pp2d_idx); 735 return (1); 736 } 737 return (0); 738 } 739 740 /* 741 * Increment hold count for pdir pages. This routine is used when new ptlb 742 * entry is being inserted into pdir. 743 */ 744 static void 745 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir) 746 { 747 vm_paddr_t pa; 748 vm_page_t m; 749 int i; 750 751 KASSERT((pmap != kernel_pmap), 752 ("pdir_hold: holding kernel pdir!")); 753 754 KASSERT((pdir != NULL), ("pdir_hold: null pdir")); 755 756 for (i = 0; i < PDIR_PAGES; i++) { 757 pa = pte_vatopa(mmu, kernel_pmap, 758 (vm_offset_t) pdir + (i * PAGE_SIZE)); 759 m = PHYS_TO_VM_PAGE(pa); 760 m->wire_count++; 761 } 762 } 763 764 /* Allocate page table. */ 765 static pte_t * 766 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx, 767 boolean_t nosleep) 768 { 769 vm_page_t mtbl [PTBL_PAGES]; 770 vm_page_t m; 771 struct ptbl_buf *pbuf; 772 unsigned int pidx; 773 pte_t *ptbl; 774 int i, j; 775 int req; 776 777 KASSERT((pdir[pdir_idx] == NULL), 778 ("%s: valid ptbl entry exists!", __func__)); 779 780 pbuf = ptbl_buf_alloc(); 781 if (pbuf == NULL) 782 panic("%s: couldn't alloc kernel virtual memory", __func__); 783 784 ptbl = (pte_t *) pbuf->kva; 785 786 for (i = 0; i < PTBL_PAGES; i++) { 787 pidx = (PTBL_PAGES * pdir_idx) + i; 788 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED; 789 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) { 790 PMAP_UNLOCK(pmap); 791 rw_wunlock(&pvh_global_lock); 792 if (nosleep) { 793 ptbl_free_pmap_ptbl(pmap, ptbl); 794 for (j = 0; j < i; j++) 795 vm_page_free(mtbl[j]); 796 vm_wire_sub(i); 797 return (NULL); 798 } 799 vm_wait(NULL); 800 rw_wlock(&pvh_global_lock); 801 PMAP_LOCK(pmap); 802 } 803 mtbl[i] = m; 804 } 805 806 /* Mapin allocated pages into kernel_pmap. */ 807 mmu_booke_qenter(mmu, (vm_offset_t) ptbl, mtbl, PTBL_PAGES); 808 /* Zero whole ptbl. */ 809 bzero((caddr_t) ptbl, PTBL_PAGES * PAGE_SIZE); 810 811 /* Add pbuf to the pmap ptbl bufs list. */ 812 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 813 814 return (ptbl); 815 } 816 817 /* Free ptbl pages and invalidate pdir entry. */ 818 static void 819 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx) 820 { 821 pte_t *ptbl; 822 vm_paddr_t pa; 823 vm_offset_t va; 824 vm_page_t m; 825 int i; 826 827 ptbl = pdir[pdir_idx]; 828 829 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 830 831 pdir[pdir_idx] = NULL; 832 833 for (i = 0; i < PTBL_PAGES; i++) { 834 va = ((vm_offset_t) ptbl + (i * PAGE_SIZE)); 835 pa = pte_vatopa(mmu, kernel_pmap, va); 836 m = PHYS_TO_VM_PAGE(pa); 837 vm_page_free_zero(m); 838 vm_wire_sub(1); 839 pmap_kremove(va); 840 } 841 842 ptbl_free_pmap_ptbl(pmap, ptbl); 843 } 844 845 /* 846 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called 847 * when removing pte entry from ptbl. 848 * 849 * Return 1 if ptbl pages were freed. 850 */ 851 static int 852 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va) 853 { 854 pte_t *ptbl; 855 vm_paddr_t pa; 856 vm_page_t m; 857 u_int pp2d_idx; 858 pte_t **pdir; 859 u_int pdir_idx; 860 int i; 861 862 pp2d_idx = PP2D_IDX(va); 863 pdir_idx = PDIR_IDX(va); 864 865 KASSERT((pmap != kernel_pmap), 866 ("ptbl_unhold: unholding kernel ptbl!")); 867 868 pdir = pmap->pm_pp2d[pp2d_idx]; 869 ptbl = pdir[pdir_idx]; 870 871 KASSERT(((vm_offset_t) ptbl >= VM_MIN_KERNEL_ADDRESS), 872 ("ptbl_unhold: non kva ptbl")); 873 874 /* decrement hold count */ 875 for (i = 0; i < PTBL_PAGES; i++) { 876 pa = pte_vatopa(mmu, kernel_pmap, 877 (vm_offset_t) ptbl + (i * PAGE_SIZE)); 878 m = PHYS_TO_VM_PAGE(pa); 879 m->wire_count--; 880 } 881 882 /* 883 * Free ptbl pages if there are no pte entries in this ptbl. 884 * wire_count has the same value for all ptbl pages, so check the 885 * last page. 886 */ 887 if (m->wire_count == 0) { 888 /* A pair of indirect entries might point to this ptbl page */ 889 #if 0 890 tlb_flush_entry(pmap, va & ~((2UL * PAGE_SIZE_1M) - 1), 891 TLB_SIZE_1M, MAS6_SIND); 892 tlb_flush_entry(pmap, (va & ~((2UL * PAGE_SIZE_1M) - 1)) | PAGE_SIZE_1M, 893 TLB_SIZE_1M, MAS6_SIND); 894 #endif 895 ptbl_free(mmu, pmap, pdir, pdir_idx); 896 pdir_unhold(mmu, pmap, pp2d_idx); 897 return (1); 898 } 899 return (0); 900 } 901 902 /* 903 * Increment hold count for ptbl pages. This routine is used when new pte 904 * entry is being inserted into ptbl. 905 */ 906 static void 907 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx) 908 { 909 vm_paddr_t pa; 910 pte_t *ptbl; 911 vm_page_t m; 912 int i; 913 914 KASSERT((pmap != kernel_pmap), 915 ("ptbl_hold: holding kernel ptbl!")); 916 917 ptbl = pdir[pdir_idx]; 918 919 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 920 921 for (i = 0; i < PTBL_PAGES; i++) { 922 pa = pte_vatopa(mmu, kernel_pmap, 923 (vm_offset_t) ptbl + (i * PAGE_SIZE)); 924 m = PHYS_TO_VM_PAGE(pa); 925 m->wire_count++; 926 } 927 } 928 #else 929 930 /* Initialize pool of kva ptbl buffers. */ 931 static void 932 ptbl_init(void) 933 { 934 int i; 935 936 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 937 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 938 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 939 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 940 941 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 942 TAILQ_INIT(&ptbl_buf_freelist); 943 944 for (i = 0; i < PTBL_BUFS; i++) { 945 ptbl_bufs[i].kva = 946 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 947 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 948 } 949 } 950 951 /* Get a ptbl_buf from the freelist. */ 952 static struct ptbl_buf * 953 ptbl_buf_alloc(void) 954 { 955 struct ptbl_buf *buf; 956 957 mtx_lock(&ptbl_buf_freelist_lock); 958 buf = TAILQ_FIRST(&ptbl_buf_freelist); 959 if (buf != NULL) 960 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 961 mtx_unlock(&ptbl_buf_freelist_lock); 962 963 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 964 965 return (buf); 966 } 967 968 /* Return ptbl buff to free pool. */ 969 static void 970 ptbl_buf_free(struct ptbl_buf *buf) 971 { 972 973 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 974 975 mtx_lock(&ptbl_buf_freelist_lock); 976 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 977 mtx_unlock(&ptbl_buf_freelist_lock); 978 } 979 980 /* 981 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 982 */ 983 static void 984 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 985 { 986 struct ptbl_buf *pbuf; 987 988 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 989 990 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 991 992 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 993 if (pbuf->kva == (vm_offset_t)ptbl) { 994 /* Remove from pmap ptbl buf list. */ 995 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 996 997 /* Free corresponding ptbl buf. */ 998 ptbl_buf_free(pbuf); 999 break; 1000 } 1001 } 1002 1003 /* Allocate page table. */ 1004 static pte_t * 1005 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 1006 { 1007 vm_page_t mtbl[PTBL_PAGES]; 1008 vm_page_t m; 1009 struct ptbl_buf *pbuf; 1010 unsigned int pidx; 1011 pte_t *ptbl; 1012 int i, j; 1013 1014 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1015 (pmap == kernel_pmap), pdir_idx); 1016 1017 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1018 ("ptbl_alloc: invalid pdir_idx")); 1019 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 1020 ("pte_alloc: valid ptbl entry exists!")); 1021 1022 pbuf = ptbl_buf_alloc(); 1023 if (pbuf == NULL) 1024 panic("pte_alloc: couldn't alloc kernel virtual memory"); 1025 1026 ptbl = (pte_t *)pbuf->kva; 1027 1028 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 1029 1030 for (i = 0; i < PTBL_PAGES; i++) { 1031 pidx = (PTBL_PAGES * pdir_idx) + i; 1032 while ((m = vm_page_alloc(NULL, pidx, 1033 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 1034 PMAP_UNLOCK(pmap); 1035 rw_wunlock(&pvh_global_lock); 1036 if (nosleep) { 1037 ptbl_free_pmap_ptbl(pmap, ptbl); 1038 for (j = 0; j < i; j++) 1039 vm_page_free(mtbl[j]); 1040 vm_wire_sub(i); 1041 return (NULL); 1042 } 1043 vm_wait(NULL); 1044 rw_wlock(&pvh_global_lock); 1045 PMAP_LOCK(pmap); 1046 } 1047 mtbl[i] = m; 1048 } 1049 1050 /* Map allocated pages into kernel_pmap. */ 1051 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 1052 1053 /* Zero whole ptbl. */ 1054 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 1055 1056 /* Add pbuf to the pmap ptbl bufs list. */ 1057 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 1058 1059 return (ptbl); 1060 } 1061 1062 /* Free ptbl pages and invalidate pdir entry. */ 1063 static void 1064 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1065 { 1066 pte_t *ptbl; 1067 vm_paddr_t pa; 1068 vm_offset_t va; 1069 vm_page_t m; 1070 int i; 1071 1072 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1073 (pmap == kernel_pmap), pdir_idx); 1074 1075 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1076 ("ptbl_free: invalid pdir_idx")); 1077 1078 ptbl = pmap->pm_pdir[pdir_idx]; 1079 1080 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 1081 1082 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 1083 1084 /* 1085 * Invalidate the pdir entry as soon as possible, so that other CPUs 1086 * don't attempt to look up the page tables we are releasing. 1087 */ 1088 mtx_lock_spin(&tlbivax_mutex); 1089 tlb_miss_lock(); 1090 1091 pmap->pm_pdir[pdir_idx] = NULL; 1092 1093 tlb_miss_unlock(); 1094 mtx_unlock_spin(&tlbivax_mutex); 1095 1096 for (i = 0; i < PTBL_PAGES; i++) { 1097 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 1098 pa = pte_vatopa(mmu, kernel_pmap, va); 1099 m = PHYS_TO_VM_PAGE(pa); 1100 vm_page_free_zero(m); 1101 vm_wire_sub(1); 1102 mmu_booke_kremove(mmu, va); 1103 } 1104 1105 ptbl_free_pmap_ptbl(pmap, ptbl); 1106 } 1107 1108 /* 1109 * Decrement ptbl pages hold count and attempt to free ptbl pages. 1110 * Called when removing pte entry from ptbl. 1111 * 1112 * Return 1 if ptbl pages were freed. 1113 */ 1114 static int 1115 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1116 { 1117 pte_t *ptbl; 1118 vm_paddr_t pa; 1119 vm_page_t m; 1120 int i; 1121 1122 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1123 (pmap == kernel_pmap), pdir_idx); 1124 1125 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1126 ("ptbl_unhold: invalid pdir_idx")); 1127 KASSERT((pmap != kernel_pmap), 1128 ("ptbl_unhold: unholding kernel ptbl!")); 1129 1130 ptbl = pmap->pm_pdir[pdir_idx]; 1131 1132 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 1133 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 1134 ("ptbl_unhold: non kva ptbl")); 1135 1136 /* decrement hold count */ 1137 for (i = 0; i < PTBL_PAGES; i++) { 1138 pa = pte_vatopa(mmu, kernel_pmap, 1139 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 1140 m = PHYS_TO_VM_PAGE(pa); 1141 m->wire_count--; 1142 } 1143 1144 /* 1145 * Free ptbl pages if there are no pte etries in this ptbl. 1146 * wire_count has the same value for all ptbl pages, so check the last 1147 * page. 1148 */ 1149 if (m->wire_count == 0) { 1150 ptbl_free(mmu, pmap, pdir_idx); 1151 1152 //debugf("ptbl_unhold: e (freed ptbl)\n"); 1153 return (1); 1154 } 1155 1156 return (0); 1157 } 1158 1159 /* 1160 * Increment hold count for ptbl pages. This routine is used when a new pte 1161 * entry is being inserted into the ptbl. 1162 */ 1163 static void 1164 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1165 { 1166 vm_paddr_t pa; 1167 pte_t *ptbl; 1168 vm_page_t m; 1169 int i; 1170 1171 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 1172 pdir_idx); 1173 1174 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1175 ("ptbl_hold: invalid pdir_idx")); 1176 KASSERT((pmap != kernel_pmap), 1177 ("ptbl_hold: holding kernel ptbl!")); 1178 1179 ptbl = pmap->pm_pdir[pdir_idx]; 1180 1181 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 1182 1183 for (i = 0; i < PTBL_PAGES; i++) { 1184 pa = pte_vatopa(mmu, kernel_pmap, 1185 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 1186 m = PHYS_TO_VM_PAGE(pa); 1187 m->wire_count++; 1188 } 1189 } 1190 #endif 1191 1192 /* Allocate pv_entry structure. */ 1193 pv_entry_t 1194 pv_alloc(void) 1195 { 1196 pv_entry_t pv; 1197 1198 pv_entry_count++; 1199 if (pv_entry_count > pv_entry_high_water) 1200 pagedaemon_wakeup(0); /* XXX powerpc NUMA */ 1201 pv = uma_zalloc(pvzone, M_NOWAIT); 1202 1203 return (pv); 1204 } 1205 1206 /* Free pv_entry structure. */ 1207 static __inline void 1208 pv_free(pv_entry_t pve) 1209 { 1210 1211 pv_entry_count--; 1212 uma_zfree(pvzone, pve); 1213 } 1214 1215 1216 /* Allocate and initialize pv_entry structure. */ 1217 static void 1218 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 1219 { 1220 pv_entry_t pve; 1221 1222 //int su = (pmap == kernel_pmap); 1223 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 1224 // (u_int32_t)pmap, va, (u_int32_t)m); 1225 1226 pve = pv_alloc(); 1227 if (pve == NULL) 1228 panic("pv_insert: no pv entries!"); 1229 1230 pve->pv_pmap = pmap; 1231 pve->pv_va = va; 1232 1233 /* add to pv_list */ 1234 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1235 rw_assert(&pvh_global_lock, RA_WLOCKED); 1236 1237 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 1238 1239 //debugf("pv_insert: e\n"); 1240 } 1241 1242 /* Destroy pv entry. */ 1243 static void 1244 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 1245 { 1246 pv_entry_t pve; 1247 1248 //int su = (pmap == kernel_pmap); 1249 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 1250 1251 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1252 rw_assert(&pvh_global_lock, RA_WLOCKED); 1253 1254 /* find pv entry */ 1255 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 1256 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 1257 /* remove from pv_list */ 1258 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 1259 if (TAILQ_EMPTY(&m->md.pv_list)) 1260 vm_page_aflag_clear(m, PGA_WRITEABLE); 1261 1262 /* free pv entry struct */ 1263 pv_free(pve); 1264 break; 1265 } 1266 } 1267 1268 //debugf("pv_remove: e\n"); 1269 } 1270 1271 #ifdef __powerpc64__ 1272 /* 1273 * Clean pte entry, try to free page table page if requested. 1274 * 1275 * Return 1 if ptbl pages were freed, otherwise return 0. 1276 */ 1277 static int 1278 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags) 1279 { 1280 vm_page_t m; 1281 pte_t *pte; 1282 1283 pte = pte_find(mmu, pmap, va); 1284 KASSERT(pte != NULL, ("%s: NULL pte", __func__)); 1285 1286 if (!PTE_ISVALID(pte)) 1287 return (0); 1288 1289 /* Get vm_page_t for mapped pte. */ 1290 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1291 1292 if (PTE_ISWIRED(pte)) 1293 pmap->pm_stats.wired_count--; 1294 1295 /* Handle managed entry. */ 1296 if (PTE_ISMANAGED(pte)) { 1297 1298 /* Handle modified pages. */ 1299 if (PTE_ISMODIFIED(pte)) 1300 vm_page_dirty(m); 1301 1302 /* Referenced pages. */ 1303 if (PTE_ISREFERENCED(pte)) 1304 vm_page_aflag_set(m, PGA_REFERENCED); 1305 1306 /* Remove pv_entry from pv_list. */ 1307 pv_remove(pmap, va, m); 1308 } else if (m->md.pv_tracked) { 1309 pv_remove(pmap, va, m); 1310 if (TAILQ_EMPTY(&m->md.pv_list)) 1311 m->md.pv_tracked = false; 1312 } 1313 mtx_lock_spin(&tlbivax_mutex); 1314 tlb_miss_lock(); 1315 1316 tlb0_flush_entry(va); 1317 *pte = 0; 1318 1319 tlb_miss_unlock(); 1320 mtx_unlock_spin(&tlbivax_mutex); 1321 1322 pmap->pm_stats.resident_count--; 1323 1324 if (flags & PTBL_UNHOLD) { 1325 return (ptbl_unhold(mmu, pmap, va)); 1326 } 1327 return (0); 1328 } 1329 1330 /* 1331 * allocate a page of pointers to page directories, do not preallocate the 1332 * page tables 1333 */ 1334 static pte_t ** 1335 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep) 1336 { 1337 vm_page_t mtbl [PDIR_PAGES]; 1338 vm_page_t m; 1339 struct ptbl_buf *pbuf; 1340 pte_t **pdir; 1341 unsigned int pidx; 1342 int i; 1343 int req; 1344 1345 pbuf = ptbl_buf_alloc(); 1346 1347 if (pbuf == NULL) 1348 panic("%s: couldn't alloc kernel virtual memory", __func__); 1349 1350 /* Allocate pdir pages, this will sleep! */ 1351 for (i = 0; i < PDIR_PAGES; i++) { 1352 pidx = (PDIR_PAGES * pp2d_idx) + i; 1353 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED; 1354 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) { 1355 PMAP_UNLOCK(pmap); 1356 vm_wait(NULL); 1357 PMAP_LOCK(pmap); 1358 } 1359 mtbl[i] = m; 1360 } 1361 1362 /* Mapin allocated pages into kernel_pmap. */ 1363 pdir = (pte_t **) pbuf->kva; 1364 pmap_qenter((vm_offset_t) pdir, mtbl, PDIR_PAGES); 1365 1366 /* Zero whole pdir. */ 1367 bzero((caddr_t) pdir, PDIR_PAGES * PAGE_SIZE); 1368 1369 /* Add pdir to the pmap pdir bufs list. */ 1370 TAILQ_INSERT_TAIL(&pmap->pm_pdir_list, pbuf, link); 1371 1372 return pdir; 1373 } 1374 1375 /* 1376 * Insert PTE for a given page and virtual address. 1377 */ 1378 static int 1379 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 1380 boolean_t nosleep) 1381 { 1382 unsigned int pp2d_idx = PP2D_IDX(va); 1383 unsigned int pdir_idx = PDIR_IDX(va); 1384 unsigned int ptbl_idx = PTBL_IDX(va); 1385 pte_t *ptbl, *pte; 1386 pte_t **pdir; 1387 1388 /* Get the page directory pointer. */ 1389 pdir = pmap->pm_pp2d[pp2d_idx]; 1390 if (pdir == NULL) 1391 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep); 1392 1393 /* Get the page table pointer. */ 1394 ptbl = pdir[pdir_idx]; 1395 1396 if (ptbl == NULL) { 1397 /* Allocate page table pages. */ 1398 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep); 1399 if (ptbl == NULL) { 1400 KASSERT(nosleep, ("nosleep and NULL ptbl")); 1401 return (ENOMEM); 1402 } 1403 } else { 1404 /* 1405 * Check if there is valid mapping for requested va, if there 1406 * is, remove it. 1407 */ 1408 pte = &pdir[pdir_idx][ptbl_idx]; 1409 if (PTE_ISVALID(pte)) { 1410 pte_remove(mmu, pmap, va, PTBL_HOLD); 1411 } else { 1412 /* 1413 * pte is not used, increment hold count for ptbl 1414 * pages. 1415 */ 1416 if (pmap != kernel_pmap) 1417 ptbl_hold(mmu, pmap, pdir, pdir_idx); 1418 } 1419 } 1420 1421 if (pdir[pdir_idx] == NULL) { 1422 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL) 1423 pdir_hold(mmu, pmap, pdir); 1424 pdir[pdir_idx] = ptbl; 1425 } 1426 if (pmap->pm_pp2d[pp2d_idx] == NULL) 1427 pmap->pm_pp2d[pp2d_idx] = pdir; 1428 1429 /* 1430 * Insert pv_entry into pv_list for mapped page if part of managed 1431 * memory. 1432 */ 1433 if ((m->oflags & VPO_UNMANAGED) == 0) { 1434 flags |= PTE_MANAGED; 1435 1436 /* Create and insert pv entry. */ 1437 pv_insert(pmap, va, m); 1438 } 1439 1440 mtx_lock_spin(&tlbivax_mutex); 1441 tlb_miss_lock(); 1442 1443 tlb0_flush_entry(va); 1444 pmap->pm_stats.resident_count++; 1445 pte = &pdir[pdir_idx][ptbl_idx]; 1446 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 1447 *pte |= (PTE_VALID | flags); 1448 1449 tlb_miss_unlock(); 1450 mtx_unlock_spin(&tlbivax_mutex); 1451 1452 return (0); 1453 } 1454 1455 /* Return the pa for the given pmap/va. */ 1456 static vm_paddr_t 1457 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1458 { 1459 vm_paddr_t pa = 0; 1460 pte_t *pte; 1461 1462 pte = pte_find(mmu, pmap, va); 1463 if ((pte != NULL) && PTE_ISVALID(pte)) 1464 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1465 return (pa); 1466 } 1467 1468 1469 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */ 1470 static void 1471 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1472 { 1473 int i, j; 1474 vm_offset_t va; 1475 pte_t *pte; 1476 1477 va = addr; 1478 /* Initialize kernel pdir */ 1479 for (i = 0; i < kernel_pdirs; i++) { 1480 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] = 1481 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES)); 1482 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES)); 1483 j < PDIR_NENTRIES; j++) { 1484 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] = 1485 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE * PDIR_PAGES) + 1486 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE * PTBL_PAGES)); 1487 } 1488 } 1489 1490 /* 1491 * Fill in PTEs covering kernel code and data. They are not required 1492 * for address translation, as this area is covered by static TLB1 1493 * entries, but for pte_vatopa() to work correctly with kernel area 1494 * addresses. 1495 */ 1496 for (va = addr; va < data_end; va += PAGE_SIZE) { 1497 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]); 1498 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1499 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1500 PTE_VALID | PTE_PS_4KB; 1501 } 1502 } 1503 #else 1504 /* 1505 * Clean pte entry, try to free page table page if requested. 1506 * 1507 * Return 1 if ptbl pages were freed, otherwise return 0. 1508 */ 1509 static int 1510 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 1511 { 1512 unsigned int pdir_idx = PDIR_IDX(va); 1513 unsigned int ptbl_idx = PTBL_IDX(va); 1514 vm_page_t m; 1515 pte_t *ptbl; 1516 pte_t *pte; 1517 1518 //int su = (pmap == kernel_pmap); 1519 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 1520 // su, (u_int32_t)pmap, va, flags); 1521 1522 ptbl = pmap->pm_pdir[pdir_idx]; 1523 KASSERT(ptbl, ("pte_remove: null ptbl")); 1524 1525 pte = &ptbl[ptbl_idx]; 1526 1527 if (pte == NULL || !PTE_ISVALID(pte)) 1528 return (0); 1529 1530 if (PTE_ISWIRED(pte)) 1531 pmap->pm_stats.wired_count--; 1532 1533 /* Get vm_page_t for mapped pte. */ 1534 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1535 1536 /* Handle managed entry. */ 1537 if (PTE_ISMANAGED(pte)) { 1538 1539 if (PTE_ISMODIFIED(pte)) 1540 vm_page_dirty(m); 1541 1542 if (PTE_ISREFERENCED(pte)) 1543 vm_page_aflag_set(m, PGA_REFERENCED); 1544 1545 pv_remove(pmap, va, m); 1546 } else if (m->md.pv_tracked) { 1547 /* 1548 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is 1549 * used. This is needed by the NCSW support code for fast 1550 * VA<->PA translation. 1551 */ 1552 pv_remove(pmap, va, m); 1553 if (TAILQ_EMPTY(&m->md.pv_list)) 1554 m->md.pv_tracked = false; 1555 } 1556 1557 mtx_lock_spin(&tlbivax_mutex); 1558 tlb_miss_lock(); 1559 1560 tlb0_flush_entry(va); 1561 *pte = 0; 1562 1563 tlb_miss_unlock(); 1564 mtx_unlock_spin(&tlbivax_mutex); 1565 1566 pmap->pm_stats.resident_count--; 1567 1568 if (flags & PTBL_UNHOLD) { 1569 //debugf("pte_remove: e (unhold)\n"); 1570 return (ptbl_unhold(mmu, pmap, pdir_idx)); 1571 } 1572 1573 //debugf("pte_remove: e\n"); 1574 return (0); 1575 } 1576 1577 /* 1578 * Insert PTE for a given page and virtual address. 1579 */ 1580 static int 1581 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 1582 boolean_t nosleep) 1583 { 1584 unsigned int pdir_idx = PDIR_IDX(va); 1585 unsigned int ptbl_idx = PTBL_IDX(va); 1586 pte_t *ptbl, *pte; 1587 1588 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 1589 pmap == kernel_pmap, pmap, va); 1590 1591 /* Get the page table pointer. */ 1592 ptbl = pmap->pm_pdir[pdir_idx]; 1593 1594 if (ptbl == NULL) { 1595 /* Allocate page table pages. */ 1596 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 1597 if (ptbl == NULL) { 1598 KASSERT(nosleep, ("nosleep and NULL ptbl")); 1599 return (ENOMEM); 1600 } 1601 } else { 1602 /* 1603 * Check if there is valid mapping for requested 1604 * va, if there is, remove it. 1605 */ 1606 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 1607 if (PTE_ISVALID(pte)) { 1608 pte_remove(mmu, pmap, va, PTBL_HOLD); 1609 } else { 1610 /* 1611 * pte is not used, increment hold count 1612 * for ptbl pages. 1613 */ 1614 if (pmap != kernel_pmap) 1615 ptbl_hold(mmu, pmap, pdir_idx); 1616 } 1617 } 1618 1619 /* 1620 * Insert pv_entry into pv_list for mapped page if part of managed 1621 * memory. 1622 */ 1623 if ((m->oflags & VPO_UNMANAGED) == 0) { 1624 flags |= PTE_MANAGED; 1625 1626 /* Create and insert pv entry. */ 1627 pv_insert(pmap, va, m); 1628 } 1629 1630 pmap->pm_stats.resident_count++; 1631 1632 mtx_lock_spin(&tlbivax_mutex); 1633 tlb_miss_lock(); 1634 1635 tlb0_flush_entry(va); 1636 if (pmap->pm_pdir[pdir_idx] == NULL) { 1637 /* 1638 * If we just allocated a new page table, hook it in 1639 * the pdir. 1640 */ 1641 pmap->pm_pdir[pdir_idx] = ptbl; 1642 } 1643 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 1644 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 1645 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 1646 1647 tlb_miss_unlock(); 1648 mtx_unlock_spin(&tlbivax_mutex); 1649 return (0); 1650 } 1651 1652 /* Return the pa for the given pmap/va. */ 1653 static vm_paddr_t 1654 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1655 { 1656 vm_paddr_t pa = 0; 1657 pte_t *pte; 1658 1659 pte = pte_find(mmu, pmap, va); 1660 if ((pte != NULL) && PTE_ISVALID(pte)) 1661 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1662 return (pa); 1663 } 1664 1665 /* Get a pointer to a PTE in a page table. */ 1666 static pte_t * 1667 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1668 { 1669 unsigned int pdir_idx = PDIR_IDX(va); 1670 unsigned int ptbl_idx = PTBL_IDX(va); 1671 1672 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1673 1674 if (pmap->pm_pdir[pdir_idx]) 1675 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1676 1677 return (NULL); 1678 } 1679 1680 /* Set up kernel page tables. */ 1681 static void 1682 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1683 { 1684 int i; 1685 vm_offset_t va; 1686 pte_t *pte; 1687 1688 /* Initialize kernel pdir */ 1689 for (i = 0; i < kernel_ptbls; i++) 1690 kernel_pmap->pm_pdir[kptbl_min + i] = 1691 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1692 1693 /* 1694 * Fill in PTEs covering kernel code and data. They are not required 1695 * for address translation, as this area is covered by static TLB1 1696 * entries, but for pte_vatopa() to work correctly with kernel area 1697 * addresses. 1698 */ 1699 for (va = addr; va < data_end; va += PAGE_SIZE) { 1700 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1701 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1702 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1703 PTE_VALID | PTE_PS_4KB; 1704 } 1705 } 1706 #endif 1707 1708 /**************************************************************************/ 1709 /* PMAP related */ 1710 /**************************************************************************/ 1711 1712 /* 1713 * This is called during booke_init, before the system is really initialized. 1714 */ 1715 static void 1716 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1717 { 1718 vm_paddr_t phys_kernelend; 1719 struct mem_region *mp, *mp1; 1720 int cnt, i, j; 1721 vm_paddr_t s, e, sz; 1722 vm_paddr_t physsz, hwphyssz; 1723 u_int phys_avail_count; 1724 vm_size_t kstack0_sz; 1725 vm_offset_t kernel_pdir, kstack0; 1726 vm_paddr_t kstack0_phys; 1727 void *dpcpu; 1728 1729 debugf("mmu_booke_bootstrap: entered\n"); 1730 1731 /* Set interesting system properties */ 1732 #ifdef __powerpc64__ 1733 hw_direct_map = 1; 1734 #else 1735 hw_direct_map = 0; 1736 #endif 1737 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 1738 elf32_nxstack = 1; 1739 #endif 1740 1741 /* Initialize invalidation mutex */ 1742 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1743 1744 /* Read TLB0 size and associativity. */ 1745 tlb0_get_tlbconf(); 1746 1747 /* 1748 * Align kernel start and end address (kernel image). 1749 * Note that kernel end does not necessarily relate to kernsize. 1750 * kernsize is the size of the kernel that is actually mapped. 1751 */ 1752 kernstart = trunc_page(start); 1753 data_start = round_page(kernelend); 1754 data_end = data_start; 1755 1756 /* Allocate the dynamic per-cpu area. */ 1757 dpcpu = (void *)data_end; 1758 data_end += DPCPU_SIZE; 1759 1760 /* Allocate space for the message buffer. */ 1761 msgbufp = (struct msgbuf *)data_end; 1762 data_end += msgbufsize; 1763 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1764 (uintptr_t)msgbufp, data_end); 1765 1766 data_end = round_page(data_end); 1767 1768 /* Allocate space for ptbl_bufs. */ 1769 ptbl_bufs = (struct ptbl_buf *)data_end; 1770 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1771 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1772 (uintptr_t)ptbl_bufs, data_end); 1773 1774 data_end = round_page(data_end); 1775 1776 /* Allocate PTE tables for kernel KVA. */ 1777 kernel_pdir = data_end; 1778 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS, 1779 PDIR_SIZE); 1780 #ifdef __powerpc64__ 1781 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES); 1782 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE; 1783 #endif 1784 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1785 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1786 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1787 kernel_pdir, data_end); 1788 1789 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end); 1790 if (data_end - kernstart > kernsize) { 1791 kernsize += tlb1_mapin_region(kernstart + kernsize, 1792 kernload + kernsize, (data_end - kernstart) - kernsize); 1793 } 1794 data_end = kernstart + kernsize; 1795 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end); 1796 1797 /* 1798 * Clear the structures - note we can only do it safely after the 1799 * possible additional TLB1 translations are in place (above) so that 1800 * all range up to the currently calculated 'data_end' is covered. 1801 */ 1802 dpcpu_init(dpcpu, 0); 1803 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1804 #ifdef __powerpc64__ 1805 memset((void *)kernel_pdir, 0, 1806 kernel_pdirs * PDIR_PAGES * PAGE_SIZE + 1807 kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1808 #else 1809 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1810 #endif 1811 1812 /*******************************************************/ 1813 /* Set the start and end of kva. */ 1814 /*******************************************************/ 1815 virtual_avail = round_page(data_end); 1816 virtual_end = VM_MAX_KERNEL_ADDRESS; 1817 1818 /* Allocate KVA space for page zero/copy operations. */ 1819 zero_page_va = virtual_avail; 1820 virtual_avail += PAGE_SIZE; 1821 copy_page_src_va = virtual_avail; 1822 virtual_avail += PAGE_SIZE; 1823 copy_page_dst_va = virtual_avail; 1824 virtual_avail += PAGE_SIZE; 1825 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va); 1826 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va); 1827 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va); 1828 1829 /* Initialize page zero/copy mutexes. */ 1830 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1831 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1832 1833 /* Allocate KVA space for ptbl bufs. */ 1834 ptbl_buf_pool_vabase = virtual_avail; 1835 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1836 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1837 ptbl_buf_pool_vabase, virtual_avail); 1838 1839 /* Calculate corresponding physical addresses for the kernel region. */ 1840 phys_kernelend = kernload + kernsize; 1841 debugf("kernel image and allocated data:\n"); 1842 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1843 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart); 1844 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize); 1845 1846 /* 1847 * Remove kernel physical address range from avail regions list. Page 1848 * align all regions. Non-page aligned memory isn't very interesting 1849 * to us. Also, sort the entries for ascending addresses. 1850 */ 1851 1852 /* Retrieve phys/avail mem regions */ 1853 mem_regions(&physmem_regions, &physmem_regions_sz, 1854 &availmem_regions, &availmem_regions_sz); 1855 1856 if (nitems(phys_avail) < availmem_regions_sz) 1857 panic("mmu_booke_bootstrap: phys_avail too small"); 1858 1859 sz = 0; 1860 cnt = availmem_regions_sz; 1861 debugf("processing avail regions:\n"); 1862 for (mp = availmem_regions; mp->mr_size; mp++) { 1863 s = mp->mr_start; 1864 e = mp->mr_start + mp->mr_size; 1865 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1866 /* Check whether this region holds all of the kernel. */ 1867 if (s < kernload && e > phys_kernelend) { 1868 availmem_regions[cnt].mr_start = phys_kernelend; 1869 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1870 e = kernload; 1871 } 1872 /* Look whether this regions starts within the kernel. */ 1873 if (s >= kernload && s < phys_kernelend) { 1874 if (e <= phys_kernelend) 1875 goto empty; 1876 s = phys_kernelend; 1877 } 1878 /* Now look whether this region ends within the kernel. */ 1879 if (e > kernload && e <= phys_kernelend) { 1880 if (s >= kernload) 1881 goto empty; 1882 e = kernload; 1883 } 1884 /* Now page align the start and size of the region. */ 1885 s = round_page(s); 1886 e = trunc_page(e); 1887 if (e < s) 1888 e = s; 1889 sz = e - s; 1890 debugf("%09jx-%09jx = %jx\n", 1891 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1892 1893 /* Check whether some memory is left here. */ 1894 if (sz == 0) { 1895 empty: 1896 memmove(mp, mp + 1, 1897 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1898 cnt--; 1899 mp--; 1900 continue; 1901 } 1902 1903 /* Do an insertion sort. */ 1904 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1905 if (s < mp1->mr_start) 1906 break; 1907 if (mp1 < mp) { 1908 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1909 mp1->mr_start = s; 1910 mp1->mr_size = sz; 1911 } else { 1912 mp->mr_start = s; 1913 mp->mr_size = sz; 1914 } 1915 } 1916 availmem_regions_sz = cnt; 1917 1918 /*******************************************************/ 1919 /* Steal physical memory for kernel stack from the end */ 1920 /* of the first avail region */ 1921 /*******************************************************/ 1922 kstack0_sz = kstack_pages * PAGE_SIZE; 1923 kstack0_phys = availmem_regions[0].mr_start + 1924 availmem_regions[0].mr_size; 1925 kstack0_phys -= kstack0_sz; 1926 availmem_regions[0].mr_size -= kstack0_sz; 1927 1928 /*******************************************************/ 1929 /* Fill in phys_avail table, based on availmem_regions */ 1930 /*******************************************************/ 1931 phys_avail_count = 0; 1932 physsz = 0; 1933 hwphyssz = 0; 1934 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1935 1936 debugf("fill in phys_avail:\n"); 1937 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1938 1939 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1940 (uintmax_t)availmem_regions[i].mr_start, 1941 (uintmax_t)availmem_regions[i].mr_start + 1942 availmem_regions[i].mr_size, 1943 (uintmax_t)availmem_regions[i].mr_size); 1944 1945 if (hwphyssz != 0 && 1946 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1947 debugf(" hw.physmem adjust\n"); 1948 if (physsz < hwphyssz) { 1949 phys_avail[j] = availmem_regions[i].mr_start; 1950 phys_avail[j + 1] = 1951 availmem_regions[i].mr_start + 1952 hwphyssz - physsz; 1953 physsz = hwphyssz; 1954 phys_avail_count++; 1955 } 1956 break; 1957 } 1958 1959 phys_avail[j] = availmem_regions[i].mr_start; 1960 phys_avail[j + 1] = availmem_regions[i].mr_start + 1961 availmem_regions[i].mr_size; 1962 phys_avail_count++; 1963 physsz += availmem_regions[i].mr_size; 1964 } 1965 physmem = btoc(physsz); 1966 1967 /* Calculate the last available physical address. */ 1968 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1969 ; 1970 Maxmem = powerpc_btop(phys_avail[i + 1]); 1971 1972 debugf("Maxmem = 0x%08lx\n", Maxmem); 1973 debugf("phys_avail_count = %d\n", phys_avail_count); 1974 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1975 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1976 1977 #ifdef __powerpc64__ 1978 /* 1979 * Map the physical memory contiguously in TLB1. 1980 * Round so it fits into a single mapping. 1981 */ 1982 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0, 1983 phys_avail[i + 1]); 1984 #endif 1985 1986 /*******************************************************/ 1987 /* Initialize (statically allocated) kernel pmap. */ 1988 /*******************************************************/ 1989 PMAP_LOCK_INIT(kernel_pmap); 1990 #ifndef __powerpc64__ 1991 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1992 #endif 1993 1994 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap); 1995 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir); 1996 for (i = 0; i < MAXCPU; i++) { 1997 kernel_pmap->pm_tid[i] = TID_KERNEL; 1998 1999 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 2000 tidbusy[i][TID_KERNEL] = kernel_pmap; 2001 } 2002 2003 /* Mark kernel_pmap active on all CPUs */ 2004 CPU_FILL(&kernel_pmap->pm_active); 2005 2006 /* 2007 * Initialize the global pv list lock. 2008 */ 2009 rw_init(&pvh_global_lock, "pmap pv global"); 2010 2011 /*******************************************************/ 2012 /* Final setup */ 2013 /*******************************************************/ 2014 2015 /* Enter kstack0 into kernel map, provide guard page */ 2016 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 2017 thread0.td_kstack = kstack0; 2018 thread0.td_kstack_pages = kstack_pages; 2019 2020 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 2021 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 2022 kstack0_phys, kstack0_phys + kstack0_sz); 2023 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n", 2024 kstack0, kstack0 + kstack0_sz); 2025 2026 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 2027 for (i = 0; i < kstack_pages; i++) { 2028 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 2029 kstack0 += PAGE_SIZE; 2030 kstack0_phys += PAGE_SIZE; 2031 } 2032 2033 pmap_bootstrapped = 1; 2034 2035 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail); 2036 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end); 2037 2038 debugf("mmu_booke_bootstrap: exit\n"); 2039 } 2040 2041 #ifdef SMP 2042 void 2043 tlb1_ap_prep(void) 2044 { 2045 tlb_entry_t *e, tmp; 2046 unsigned int i; 2047 2048 /* Prepare TLB1 image for AP processors */ 2049 e = __boot_tlb1; 2050 for (i = 0; i < TLB1_ENTRIES; i++) { 2051 tlb1_read_entry(&tmp, i); 2052 2053 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 2054 memcpy(e++, &tmp, sizeof(tmp)); 2055 } 2056 } 2057 2058 void 2059 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 2060 { 2061 int i; 2062 2063 /* 2064 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 2065 * have the snapshot of its contents in the s/w __boot_tlb1[] table 2066 * created by tlb1_ap_prep(), so use these values directly to 2067 * (re)program AP's TLB1 hardware. 2068 * 2069 * Start at index 1 because index 0 has the kernel map. 2070 */ 2071 for (i = 1; i < TLB1_ENTRIES; i++) { 2072 if (__boot_tlb1[i].mas1 & MAS1_VALID) 2073 tlb1_write_entry(&__boot_tlb1[i], i); 2074 } 2075 2076 set_mas4_defaults(); 2077 } 2078 #endif 2079 2080 static void 2081 booke_pmap_init_qpages(void) 2082 { 2083 struct pcpu *pc; 2084 int i; 2085 2086 CPU_FOREACH(i) { 2087 pc = pcpu_find(i); 2088 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 2089 if (pc->pc_qmap_addr == 0) 2090 panic("pmap_init_qpages: unable to allocate KVA"); 2091 } 2092 } 2093 2094 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 2095 2096 /* 2097 * Get the physical page address for the given pmap/virtual address. 2098 */ 2099 static vm_paddr_t 2100 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 2101 { 2102 vm_paddr_t pa; 2103 2104 PMAP_LOCK(pmap); 2105 pa = pte_vatopa(mmu, pmap, va); 2106 PMAP_UNLOCK(pmap); 2107 2108 return (pa); 2109 } 2110 2111 /* 2112 * Extract the physical page address associated with the given 2113 * kernel virtual address. 2114 */ 2115 static vm_paddr_t 2116 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 2117 { 2118 tlb_entry_t e; 2119 vm_paddr_t p = 0; 2120 int i; 2121 2122 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS) 2123 p = pte_vatopa(mmu, kernel_pmap, va); 2124 2125 if (p == 0) { 2126 /* Check TLB1 mappings */ 2127 for (i = 0; i < TLB1_ENTRIES; i++) { 2128 tlb1_read_entry(&e, i); 2129 if (!(e.mas1 & MAS1_VALID)) 2130 continue; 2131 if (va >= e.virt && va < e.virt + e.size) 2132 return (e.phys + (va - e.virt)); 2133 } 2134 } 2135 2136 return (p); 2137 } 2138 2139 /* 2140 * Initialize the pmap module. 2141 * Called by vm_init, to initialize any structures that the pmap 2142 * system needs to map virtual memory. 2143 */ 2144 static void 2145 mmu_booke_init(mmu_t mmu) 2146 { 2147 int shpgperproc = PMAP_SHPGPERPROC; 2148 2149 /* 2150 * Initialize the address space (zone) for the pv entries. Set a 2151 * high water mark so that the system can recover from excessive 2152 * numbers of pv entries. 2153 */ 2154 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 2155 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 2156 2157 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 2158 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 2159 2160 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 2161 pv_entry_high_water = 9 * (pv_entry_max / 10); 2162 2163 uma_zone_reserve_kva(pvzone, pv_entry_max); 2164 2165 /* Pre-fill pvzone with initial number of pv entries. */ 2166 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 2167 2168 /* Initialize ptbl allocation. */ 2169 ptbl_init(); 2170 } 2171 2172 /* 2173 * Map a list of wired pages into kernel virtual address space. This is 2174 * intended for temporary mappings which do not need page modification or 2175 * references recorded. Existing mappings in the region are overwritten. 2176 */ 2177 static void 2178 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 2179 { 2180 vm_offset_t va; 2181 2182 va = sva; 2183 while (count-- > 0) { 2184 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2185 va += PAGE_SIZE; 2186 m++; 2187 } 2188 } 2189 2190 /* 2191 * Remove page mappings from kernel virtual address space. Intended for 2192 * temporary mappings entered by mmu_booke_qenter. 2193 */ 2194 static void 2195 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 2196 { 2197 vm_offset_t va; 2198 2199 va = sva; 2200 while (count-- > 0) { 2201 mmu_booke_kremove(mmu, va); 2202 va += PAGE_SIZE; 2203 } 2204 } 2205 2206 /* 2207 * Map a wired page into kernel virtual address space. 2208 */ 2209 static void 2210 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 2211 { 2212 2213 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 2214 } 2215 2216 static void 2217 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 2218 { 2219 uint32_t flags; 2220 pte_t *pte; 2221 2222 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 2223 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 2224 2225 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2226 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 2227 flags |= PTE_PS_4KB; 2228 2229 pte = pte_find(mmu, kernel_pmap, va); 2230 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE")); 2231 2232 mtx_lock_spin(&tlbivax_mutex); 2233 tlb_miss_lock(); 2234 2235 if (PTE_ISVALID(pte)) { 2236 2237 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 2238 2239 /* Flush entry from TLB0 */ 2240 tlb0_flush_entry(va); 2241 } 2242 2243 *pte = PTE_RPN_FROM_PA(pa) | flags; 2244 2245 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 2246 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 2247 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 2248 2249 /* Flush the real memory from the instruction cache. */ 2250 if ((flags & (PTE_I | PTE_G)) == 0) 2251 __syncicache((void *)va, PAGE_SIZE); 2252 2253 tlb_miss_unlock(); 2254 mtx_unlock_spin(&tlbivax_mutex); 2255 } 2256 2257 /* 2258 * Remove a page from kernel page table. 2259 */ 2260 static void 2261 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 2262 { 2263 pte_t *pte; 2264 2265 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va); 2266 2267 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 2268 (va <= VM_MAX_KERNEL_ADDRESS)), 2269 ("mmu_booke_kremove: invalid va")); 2270 2271 pte = pte_find(mmu, kernel_pmap, va); 2272 2273 if (!PTE_ISVALID(pte)) { 2274 2275 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 2276 2277 return; 2278 } 2279 2280 mtx_lock_spin(&tlbivax_mutex); 2281 tlb_miss_lock(); 2282 2283 /* Invalidate entry in TLB0, update PTE. */ 2284 tlb0_flush_entry(va); 2285 *pte = 0; 2286 2287 tlb_miss_unlock(); 2288 mtx_unlock_spin(&tlbivax_mutex); 2289 } 2290 2291 /* 2292 * Provide a kernel pointer corresponding to a given userland pointer. 2293 * The returned pointer is valid until the next time this function is 2294 * called in this thread. This is used internally in copyin/copyout. 2295 */ 2296 int 2297 mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 2298 void **kaddr, size_t ulen, size_t *klen) 2299 { 2300 2301 if ((uintptr_t)uaddr + ulen > VM_MAXUSER_ADDRESS + PAGE_SIZE) 2302 return (EFAULT); 2303 2304 *kaddr = (void *)(uintptr_t)uaddr; 2305 if (klen) 2306 *klen = ulen; 2307 2308 return (0); 2309 } 2310 2311 /* 2312 * Figure out where a given kernel pointer (usually in a fault) points 2313 * to from the VM's perspective, potentially remapping into userland's 2314 * address space. 2315 */ 2316 static int 2317 mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2318 vm_offset_t *decoded_addr) 2319 { 2320 2321 if (addr < VM_MAXUSER_ADDRESS) 2322 *is_user = 1; 2323 else 2324 *is_user = 0; 2325 2326 *decoded_addr = addr; 2327 return (0); 2328 } 2329 2330 /* 2331 * Initialize pmap associated with process 0. 2332 */ 2333 static void 2334 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 2335 { 2336 2337 PMAP_LOCK_INIT(pmap); 2338 mmu_booke_pinit(mmu, pmap); 2339 PCPU_SET(curpmap, pmap); 2340 } 2341 2342 /* 2343 * Initialize a preallocated and zeroed pmap structure, 2344 * such as one in a vmspace structure. 2345 */ 2346 static void 2347 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 2348 { 2349 int i; 2350 2351 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 2352 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 2353 2354 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 2355 2356 for (i = 0; i < MAXCPU; i++) 2357 pmap->pm_tid[i] = TID_NONE; 2358 CPU_ZERO(&kernel_pmap->pm_active); 2359 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2360 #ifdef __powerpc64__ 2361 bzero(&pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES); 2362 TAILQ_INIT(&pmap->pm_pdir_list); 2363 #else 2364 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 2365 #endif 2366 TAILQ_INIT(&pmap->pm_ptbl_list); 2367 } 2368 2369 /* 2370 * Release any resources held by the given physical map. 2371 * Called when a pmap initialized by mmu_booke_pinit is being released. 2372 * Should only be called if the map contains no valid mappings. 2373 */ 2374 static void 2375 mmu_booke_release(mmu_t mmu, pmap_t pmap) 2376 { 2377 2378 KASSERT(pmap->pm_stats.resident_count == 0, 2379 ("pmap_release: pmap resident count %ld != 0", 2380 pmap->pm_stats.resident_count)); 2381 } 2382 2383 /* 2384 * Insert the given physical page at the specified virtual address in the 2385 * target physical map with the protection requested. If specified the page 2386 * will be wired down. 2387 */ 2388 static int 2389 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2390 vm_prot_t prot, u_int flags, int8_t psind) 2391 { 2392 int error; 2393 2394 rw_wlock(&pvh_global_lock); 2395 PMAP_LOCK(pmap); 2396 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 2397 PMAP_UNLOCK(pmap); 2398 rw_wunlock(&pvh_global_lock); 2399 return (error); 2400 } 2401 2402 static int 2403 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2404 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 2405 { 2406 pte_t *pte; 2407 vm_paddr_t pa; 2408 uint32_t flags; 2409 int error, su, sync; 2410 2411 pa = VM_PAGE_TO_PHYS(m); 2412 su = (pmap == kernel_pmap); 2413 sync = 0; 2414 2415 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 2416 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 2417 // (u_int32_t)pmap, su, pmap->pm_tid, 2418 // (u_int32_t)m, va, pa, prot, flags); 2419 2420 if (su) { 2421 KASSERT(((va >= virtual_avail) && 2422 (va <= VM_MAX_KERNEL_ADDRESS)), 2423 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 2424 } else { 2425 KASSERT((va <= VM_MAXUSER_ADDRESS), 2426 ("mmu_booke_enter_locked: user pmap, non user va")); 2427 } 2428 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2429 VM_OBJECT_ASSERT_LOCKED(m->object); 2430 2431 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2432 2433 /* 2434 * If there is an existing mapping, and the physical address has not 2435 * changed, must be protection or wiring change. 2436 */ 2437 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 2438 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 2439 2440 /* 2441 * Before actually updating pte->flags we calculate and 2442 * prepare its new value in a helper var. 2443 */ 2444 flags = *pte; 2445 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 2446 2447 /* Wiring change, just update stats. */ 2448 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 2449 if (!PTE_ISWIRED(pte)) { 2450 flags |= PTE_WIRED; 2451 pmap->pm_stats.wired_count++; 2452 } 2453 } else { 2454 if (PTE_ISWIRED(pte)) { 2455 flags &= ~PTE_WIRED; 2456 pmap->pm_stats.wired_count--; 2457 } 2458 } 2459 2460 if (prot & VM_PROT_WRITE) { 2461 /* Add write permissions. */ 2462 flags |= PTE_SW; 2463 if (!su) 2464 flags |= PTE_UW; 2465 2466 if ((flags & PTE_MANAGED) != 0) 2467 vm_page_aflag_set(m, PGA_WRITEABLE); 2468 } else { 2469 /* Handle modified pages, sense modify status. */ 2470 2471 /* 2472 * The PTE_MODIFIED flag could be set by underlying 2473 * TLB misses since we last read it (above), possibly 2474 * other CPUs could update it so we check in the PTE 2475 * directly rather than rely on that saved local flags 2476 * copy. 2477 */ 2478 if (PTE_ISMODIFIED(pte)) 2479 vm_page_dirty(m); 2480 } 2481 2482 if (prot & VM_PROT_EXECUTE) { 2483 flags |= PTE_SX; 2484 if (!su) 2485 flags |= PTE_UX; 2486 2487 /* 2488 * Check existing flags for execute permissions: if we 2489 * are turning execute permissions on, icache should 2490 * be flushed. 2491 */ 2492 if ((*pte & (PTE_UX | PTE_SX)) == 0) 2493 sync++; 2494 } 2495 2496 flags &= ~PTE_REFERENCED; 2497 2498 /* 2499 * The new flags value is all calculated -- only now actually 2500 * update the PTE. 2501 */ 2502 mtx_lock_spin(&tlbivax_mutex); 2503 tlb_miss_lock(); 2504 2505 tlb0_flush_entry(va); 2506 *pte &= ~PTE_FLAGS_MASK; 2507 *pte |= flags; 2508 2509 tlb_miss_unlock(); 2510 mtx_unlock_spin(&tlbivax_mutex); 2511 2512 } else { 2513 /* 2514 * If there is an existing mapping, but it's for a different 2515 * physical address, pte_enter() will delete the old mapping. 2516 */ 2517 //if ((pte != NULL) && PTE_ISVALID(pte)) 2518 // debugf("mmu_booke_enter_locked: replace\n"); 2519 //else 2520 // debugf("mmu_booke_enter_locked: new\n"); 2521 2522 /* Now set up the flags and install the new mapping. */ 2523 flags = (PTE_SR | PTE_VALID); 2524 flags |= PTE_M; 2525 2526 if (!su) 2527 flags |= PTE_UR; 2528 2529 if (prot & VM_PROT_WRITE) { 2530 flags |= PTE_SW; 2531 if (!su) 2532 flags |= PTE_UW; 2533 2534 if ((m->oflags & VPO_UNMANAGED) == 0) 2535 vm_page_aflag_set(m, PGA_WRITEABLE); 2536 } 2537 2538 if (prot & VM_PROT_EXECUTE) { 2539 flags |= PTE_SX; 2540 if (!su) 2541 flags |= PTE_UX; 2542 } 2543 2544 /* If its wired update stats. */ 2545 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 2546 flags |= PTE_WIRED; 2547 2548 error = pte_enter(mmu, pmap, m, va, flags, 2549 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 2550 if (error != 0) 2551 return (KERN_RESOURCE_SHORTAGE); 2552 2553 if ((flags & PMAP_ENTER_WIRED) != 0) 2554 pmap->pm_stats.wired_count++; 2555 2556 /* Flush the real memory from the instruction cache. */ 2557 if (prot & VM_PROT_EXECUTE) 2558 sync++; 2559 } 2560 2561 if (sync && (su || pmap == PCPU_GET(curpmap))) { 2562 __syncicache((void *)va, PAGE_SIZE); 2563 sync = 0; 2564 } 2565 2566 return (KERN_SUCCESS); 2567 } 2568 2569 /* 2570 * Maps a sequence of resident pages belonging to the same object. 2571 * The sequence begins with the given page m_start. This page is 2572 * mapped at the given virtual address start. Each subsequent page is 2573 * mapped at a virtual address that is offset from start by the same 2574 * amount as the page is offset from m_start within the object. The 2575 * last page in the sequence is the page with the largest offset from 2576 * m_start that can be mapped at a virtual address less than the given 2577 * virtual address end. Not every virtual page between start and end 2578 * is mapped; only those for which a resident page exists with the 2579 * corresponding offset from m_start are mapped. 2580 */ 2581 static void 2582 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 2583 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 2584 { 2585 vm_page_t m; 2586 vm_pindex_t diff, psize; 2587 2588 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2589 2590 psize = atop(end - start); 2591 m = m_start; 2592 rw_wlock(&pvh_global_lock); 2593 PMAP_LOCK(pmap); 2594 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2595 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 2596 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 2597 PMAP_ENTER_NOSLEEP, 0); 2598 m = TAILQ_NEXT(m, listq); 2599 } 2600 rw_wunlock(&pvh_global_lock); 2601 PMAP_UNLOCK(pmap); 2602 } 2603 2604 static void 2605 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2606 vm_prot_t prot) 2607 { 2608 2609 rw_wlock(&pvh_global_lock); 2610 PMAP_LOCK(pmap); 2611 mmu_booke_enter_locked(mmu, pmap, va, m, 2612 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 2613 0); 2614 rw_wunlock(&pvh_global_lock); 2615 PMAP_UNLOCK(pmap); 2616 } 2617 2618 /* 2619 * Remove the given range of addresses from the specified map. 2620 * 2621 * It is assumed that the start and end are properly rounded to the page size. 2622 */ 2623 static void 2624 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 2625 { 2626 pte_t *pte; 2627 uint8_t hold_flag; 2628 2629 int su = (pmap == kernel_pmap); 2630 2631 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 2632 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 2633 2634 if (su) { 2635 KASSERT(((va >= virtual_avail) && 2636 (va <= VM_MAX_KERNEL_ADDRESS)), 2637 ("mmu_booke_remove: kernel pmap, non kernel va")); 2638 } else { 2639 KASSERT((va <= VM_MAXUSER_ADDRESS), 2640 ("mmu_booke_remove: user pmap, non user va")); 2641 } 2642 2643 if (PMAP_REMOVE_DONE(pmap)) { 2644 //debugf("mmu_booke_remove: e (empty)\n"); 2645 return; 2646 } 2647 2648 hold_flag = PTBL_HOLD_FLAG(pmap); 2649 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 2650 2651 rw_wlock(&pvh_global_lock); 2652 PMAP_LOCK(pmap); 2653 for (; va < endva; va += PAGE_SIZE) { 2654 pte = pte_find(mmu, pmap, va); 2655 if ((pte != NULL) && PTE_ISVALID(pte)) 2656 pte_remove(mmu, pmap, va, hold_flag); 2657 } 2658 PMAP_UNLOCK(pmap); 2659 rw_wunlock(&pvh_global_lock); 2660 2661 //debugf("mmu_booke_remove: e\n"); 2662 } 2663 2664 /* 2665 * Remove physical page from all pmaps in which it resides. 2666 */ 2667 static void 2668 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 2669 { 2670 pv_entry_t pv, pvn; 2671 uint8_t hold_flag; 2672 2673 rw_wlock(&pvh_global_lock); 2674 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 2675 pvn = TAILQ_NEXT(pv, pv_link); 2676 2677 PMAP_LOCK(pv->pv_pmap); 2678 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 2679 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 2680 PMAP_UNLOCK(pv->pv_pmap); 2681 } 2682 vm_page_aflag_clear(m, PGA_WRITEABLE); 2683 rw_wunlock(&pvh_global_lock); 2684 } 2685 2686 /* 2687 * Map a range of physical addresses into kernel virtual address space. 2688 */ 2689 static vm_offset_t 2690 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2691 vm_paddr_t pa_end, int prot) 2692 { 2693 vm_offset_t sva = *virt; 2694 vm_offset_t va = sva; 2695 2696 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 2697 // sva, pa_start, pa_end); 2698 2699 while (pa_start < pa_end) { 2700 mmu_booke_kenter(mmu, va, pa_start); 2701 va += PAGE_SIZE; 2702 pa_start += PAGE_SIZE; 2703 } 2704 *virt = va; 2705 2706 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 2707 return (sva); 2708 } 2709 2710 /* 2711 * The pmap must be activated before it's address space can be accessed in any 2712 * way. 2713 */ 2714 static void 2715 mmu_booke_activate(mmu_t mmu, struct thread *td) 2716 { 2717 pmap_t pmap; 2718 u_int cpuid; 2719 2720 pmap = &td->td_proc->p_vmspace->vm_pmap; 2721 2722 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")", 2723 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2724 2725 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 2726 2727 sched_pin(); 2728 2729 cpuid = PCPU_GET(cpuid); 2730 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 2731 PCPU_SET(curpmap, pmap); 2732 2733 if (pmap->pm_tid[cpuid] == TID_NONE) 2734 tid_alloc(pmap); 2735 2736 /* Load PID0 register with pmap tid value. */ 2737 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 2738 __asm __volatile("isync"); 2739 2740 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2741 2742 sched_unpin(); 2743 2744 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2745 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2746 } 2747 2748 /* 2749 * Deactivate the specified process's address space. 2750 */ 2751 static void 2752 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2753 { 2754 pmap_t pmap; 2755 2756 pmap = &td->td_proc->p_vmspace->vm_pmap; 2757 2758 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX, 2759 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2760 2761 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2762 2763 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2764 PCPU_SET(curpmap, NULL); 2765 } 2766 2767 /* 2768 * Copy the range specified by src_addr/len 2769 * from the source map to the range dst_addr/len 2770 * in the destination map. 2771 * 2772 * This routine is only advisory and need not do anything. 2773 */ 2774 static void 2775 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2776 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2777 { 2778 2779 } 2780 2781 /* 2782 * Set the physical protection on the specified range of this map as requested. 2783 */ 2784 static void 2785 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2786 vm_prot_t prot) 2787 { 2788 vm_offset_t va; 2789 vm_page_t m; 2790 pte_t *pte; 2791 2792 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2793 mmu_booke_remove(mmu, pmap, sva, eva); 2794 return; 2795 } 2796 2797 if (prot & VM_PROT_WRITE) 2798 return; 2799 2800 PMAP_LOCK(pmap); 2801 for (va = sva; va < eva; va += PAGE_SIZE) { 2802 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2803 if (PTE_ISVALID(pte)) { 2804 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2805 2806 mtx_lock_spin(&tlbivax_mutex); 2807 tlb_miss_lock(); 2808 2809 /* Handle modified pages. */ 2810 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2811 vm_page_dirty(m); 2812 2813 tlb0_flush_entry(va); 2814 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2815 2816 tlb_miss_unlock(); 2817 mtx_unlock_spin(&tlbivax_mutex); 2818 } 2819 } 2820 } 2821 PMAP_UNLOCK(pmap); 2822 } 2823 2824 /* 2825 * Clear the write and modified bits in each of the given page's mappings. 2826 */ 2827 static void 2828 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2829 { 2830 pv_entry_t pv; 2831 pte_t *pte; 2832 2833 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2834 ("mmu_booke_remove_write: page %p is not managed", m)); 2835 2836 /* 2837 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2838 * set by another thread while the object is locked. Thus, 2839 * if PGA_WRITEABLE is clear, no page table entries need updating. 2840 */ 2841 VM_OBJECT_ASSERT_WLOCKED(m->object); 2842 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2843 return; 2844 rw_wlock(&pvh_global_lock); 2845 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2846 PMAP_LOCK(pv->pv_pmap); 2847 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2848 if (PTE_ISVALID(pte)) { 2849 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2850 2851 mtx_lock_spin(&tlbivax_mutex); 2852 tlb_miss_lock(); 2853 2854 /* Handle modified pages. */ 2855 if (PTE_ISMODIFIED(pte)) 2856 vm_page_dirty(m); 2857 2858 /* Flush mapping from TLB0. */ 2859 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2860 2861 tlb_miss_unlock(); 2862 mtx_unlock_spin(&tlbivax_mutex); 2863 } 2864 } 2865 PMAP_UNLOCK(pv->pv_pmap); 2866 } 2867 vm_page_aflag_clear(m, PGA_WRITEABLE); 2868 rw_wunlock(&pvh_global_lock); 2869 } 2870 2871 static void 2872 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2873 { 2874 pte_t *pte; 2875 pmap_t pmap; 2876 vm_page_t m; 2877 vm_offset_t addr; 2878 vm_paddr_t pa = 0; 2879 int active, valid; 2880 2881 va = trunc_page(va); 2882 sz = round_page(sz); 2883 2884 rw_wlock(&pvh_global_lock); 2885 pmap = PCPU_GET(curpmap); 2886 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2887 while (sz > 0) { 2888 PMAP_LOCK(pm); 2889 pte = pte_find(mmu, pm, va); 2890 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2891 if (valid) 2892 pa = PTE_PA(pte); 2893 PMAP_UNLOCK(pm); 2894 if (valid) { 2895 if (!active) { 2896 /* Create a mapping in the active pmap. */ 2897 addr = 0; 2898 m = PHYS_TO_VM_PAGE(pa); 2899 PMAP_LOCK(pmap); 2900 pte_enter(mmu, pmap, m, addr, 2901 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2902 __syncicache((void *)addr, PAGE_SIZE); 2903 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2904 PMAP_UNLOCK(pmap); 2905 } else 2906 __syncicache((void *)va, PAGE_SIZE); 2907 } 2908 va += PAGE_SIZE; 2909 sz -= PAGE_SIZE; 2910 } 2911 rw_wunlock(&pvh_global_lock); 2912 } 2913 2914 /* 2915 * Atomically extract and hold the physical page with the given 2916 * pmap and virtual address pair if that mapping permits the given 2917 * protection. 2918 */ 2919 static vm_page_t 2920 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2921 vm_prot_t prot) 2922 { 2923 pte_t *pte; 2924 vm_page_t m; 2925 uint32_t pte_wbit; 2926 vm_paddr_t pa; 2927 2928 m = NULL; 2929 pa = 0; 2930 PMAP_LOCK(pmap); 2931 retry: 2932 pte = pte_find(mmu, pmap, va); 2933 if ((pte != NULL) && PTE_ISVALID(pte)) { 2934 if (pmap == kernel_pmap) 2935 pte_wbit = PTE_SW; 2936 else 2937 pte_wbit = PTE_UW; 2938 2939 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2940 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2941 goto retry; 2942 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2943 vm_page_hold(m); 2944 } 2945 } 2946 2947 PA_UNLOCK_COND(pa); 2948 PMAP_UNLOCK(pmap); 2949 return (m); 2950 } 2951 2952 /* 2953 * Initialize a vm_page's machine-dependent fields. 2954 */ 2955 static void 2956 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2957 { 2958 2959 m->md.pv_tracked = 0; 2960 TAILQ_INIT(&m->md.pv_list); 2961 } 2962 2963 /* 2964 * mmu_booke_zero_page_area zeros the specified hardware page by 2965 * mapping it into virtual memory and using bzero to clear 2966 * its contents. 2967 * 2968 * off and size must reside within a single page. 2969 */ 2970 static void 2971 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2972 { 2973 vm_offset_t va; 2974 2975 /* XXX KASSERT off and size are within a single page? */ 2976 2977 #ifdef __powerpc64__ 2978 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 2979 bzero((caddr_t)va + off, size); 2980 #else 2981 mtx_lock(&zero_page_mutex); 2982 va = zero_page_va; 2983 2984 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2985 bzero((caddr_t)va + off, size); 2986 mmu_booke_kremove(mmu, va); 2987 2988 mtx_unlock(&zero_page_mutex); 2989 #endif 2990 } 2991 2992 /* 2993 * mmu_booke_zero_page zeros the specified hardware page. 2994 */ 2995 static void 2996 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2997 { 2998 vm_offset_t off, va; 2999 3000 #ifdef __powerpc64__ 3001 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3002 3003 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 3004 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 3005 #else 3006 va = zero_page_va; 3007 mtx_lock(&zero_page_mutex); 3008 3009 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 3010 3011 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 3012 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 3013 3014 mmu_booke_kremove(mmu, va); 3015 3016 mtx_unlock(&zero_page_mutex); 3017 #endif 3018 } 3019 3020 /* 3021 * mmu_booke_copy_page copies the specified (machine independent) page by 3022 * mapping the page into virtual memory and using memcopy to copy the page, 3023 * one machine dependent page at a time. 3024 */ 3025 static void 3026 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 3027 { 3028 vm_offset_t sva, dva; 3029 3030 #ifdef __powerpc64__ 3031 sva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(sm)); 3032 dva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dm)); 3033 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 3034 #else 3035 mtx_lock(©_page_mutex); 3036 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 3037 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 3038 sva = copy_page_src_va; 3039 dva = copy_page_dst_va; 3040 3041 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 3042 3043 mmu_booke_kremove(mmu, dva); 3044 mmu_booke_kremove(mmu, sva); 3045 mtx_unlock(©_page_mutex); 3046 #endif 3047 } 3048 3049 static inline void 3050 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 3051 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 3052 { 3053 void *a_cp, *b_cp; 3054 vm_offset_t a_pg_offset, b_pg_offset; 3055 int cnt; 3056 3057 #ifdef __powerpc64__ 3058 vm_page_t pa, pb; 3059 3060 while (xfersize > 0) { 3061 a_pg_offset = a_offset & PAGE_MASK; 3062 pa = ma[a_offset >> PAGE_SHIFT]; 3063 b_pg_offset = b_offset & PAGE_MASK; 3064 pb = mb[b_offset >> PAGE_SHIFT]; 3065 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3066 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3067 a_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pa)) + 3068 a_pg_offset); 3069 b_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pb)) + 3070 b_pg_offset); 3071 bcopy(a_cp, b_cp, cnt); 3072 a_offset += cnt; 3073 b_offset += cnt; 3074 xfersize -= cnt; 3075 } 3076 #else 3077 mtx_lock(©_page_mutex); 3078 while (xfersize > 0) { 3079 a_pg_offset = a_offset & PAGE_MASK; 3080 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3081 mmu_booke_kenter(mmu, copy_page_src_va, 3082 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 3083 a_cp = (char *)copy_page_src_va + a_pg_offset; 3084 b_pg_offset = b_offset & PAGE_MASK; 3085 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3086 mmu_booke_kenter(mmu, copy_page_dst_va, 3087 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 3088 b_cp = (char *)copy_page_dst_va + b_pg_offset; 3089 bcopy(a_cp, b_cp, cnt); 3090 mmu_booke_kremove(mmu, copy_page_dst_va); 3091 mmu_booke_kremove(mmu, copy_page_src_va); 3092 a_offset += cnt; 3093 b_offset += cnt; 3094 xfersize -= cnt; 3095 } 3096 mtx_unlock(©_page_mutex); 3097 #endif 3098 } 3099 3100 static vm_offset_t 3101 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 3102 { 3103 #ifdef __powerpc64__ 3104 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 3105 #else 3106 vm_paddr_t paddr; 3107 vm_offset_t qaddr; 3108 uint32_t flags; 3109 pte_t *pte; 3110 3111 paddr = VM_PAGE_TO_PHYS(m); 3112 3113 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 3114 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 3115 flags |= PTE_PS_4KB; 3116 3117 critical_enter(); 3118 qaddr = PCPU_GET(qmap_addr); 3119 3120 pte = pte_find(mmu, kernel_pmap, qaddr); 3121 3122 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 3123 3124 /* 3125 * XXX: tlbivax is broadcast to other cores, but qaddr should 3126 * not be present in other TLBs. Is there a better instruction 3127 * sequence to use? Or just forget it & use mmu_booke_kenter()... 3128 */ 3129 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 3130 __asm __volatile("isync; msync"); 3131 3132 *pte = PTE_RPN_FROM_PA(paddr) | flags; 3133 3134 /* Flush the real memory from the instruction cache. */ 3135 if ((flags & (PTE_I | PTE_G)) == 0) 3136 __syncicache((void *)qaddr, PAGE_SIZE); 3137 3138 return (qaddr); 3139 #endif 3140 } 3141 3142 static void 3143 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 3144 { 3145 #ifndef __powerpc64__ 3146 pte_t *pte; 3147 3148 pte = pte_find(mmu, kernel_pmap, addr); 3149 3150 KASSERT(PCPU_GET(qmap_addr) == addr, 3151 ("mmu_booke_quick_remove_page: invalid address")); 3152 KASSERT(*pte != 0, 3153 ("mmu_booke_quick_remove_page: PTE not in use")); 3154 3155 *pte = 0; 3156 critical_exit(); 3157 #endif 3158 } 3159 3160 /* 3161 * Return whether or not the specified physical page was modified 3162 * in any of physical maps. 3163 */ 3164 static boolean_t 3165 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 3166 { 3167 pte_t *pte; 3168 pv_entry_t pv; 3169 boolean_t rv; 3170 3171 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3172 ("mmu_booke_is_modified: page %p is not managed", m)); 3173 rv = FALSE; 3174 3175 /* 3176 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3177 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3178 * is clear, no PTEs can be modified. 3179 */ 3180 VM_OBJECT_ASSERT_WLOCKED(m->object); 3181 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3182 return (rv); 3183 rw_wlock(&pvh_global_lock); 3184 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3185 PMAP_LOCK(pv->pv_pmap); 3186 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3187 PTE_ISVALID(pte)) { 3188 if (PTE_ISMODIFIED(pte)) 3189 rv = TRUE; 3190 } 3191 PMAP_UNLOCK(pv->pv_pmap); 3192 if (rv) 3193 break; 3194 } 3195 rw_wunlock(&pvh_global_lock); 3196 return (rv); 3197 } 3198 3199 /* 3200 * Return whether or not the specified virtual address is eligible 3201 * for prefault. 3202 */ 3203 static boolean_t 3204 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 3205 { 3206 3207 return (FALSE); 3208 } 3209 3210 /* 3211 * Return whether or not the specified physical page was referenced 3212 * in any physical maps. 3213 */ 3214 static boolean_t 3215 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 3216 { 3217 pte_t *pte; 3218 pv_entry_t pv; 3219 boolean_t rv; 3220 3221 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3222 ("mmu_booke_is_referenced: page %p is not managed", m)); 3223 rv = FALSE; 3224 rw_wlock(&pvh_global_lock); 3225 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3226 PMAP_LOCK(pv->pv_pmap); 3227 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3228 PTE_ISVALID(pte)) { 3229 if (PTE_ISREFERENCED(pte)) 3230 rv = TRUE; 3231 } 3232 PMAP_UNLOCK(pv->pv_pmap); 3233 if (rv) 3234 break; 3235 } 3236 rw_wunlock(&pvh_global_lock); 3237 return (rv); 3238 } 3239 3240 /* 3241 * Clear the modify bits on the specified physical page. 3242 */ 3243 static void 3244 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 3245 { 3246 pte_t *pte; 3247 pv_entry_t pv; 3248 3249 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3250 ("mmu_booke_clear_modify: page %p is not managed", m)); 3251 VM_OBJECT_ASSERT_WLOCKED(m->object); 3252 KASSERT(!vm_page_xbusied(m), 3253 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 3254 3255 /* 3256 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 3257 * If the object containing the page is locked and the page is not 3258 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 3259 */ 3260 if ((m->aflags & PGA_WRITEABLE) == 0) 3261 return; 3262 rw_wlock(&pvh_global_lock); 3263 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3264 PMAP_LOCK(pv->pv_pmap); 3265 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3266 PTE_ISVALID(pte)) { 3267 mtx_lock_spin(&tlbivax_mutex); 3268 tlb_miss_lock(); 3269 3270 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 3271 tlb0_flush_entry(pv->pv_va); 3272 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 3273 PTE_REFERENCED); 3274 } 3275 3276 tlb_miss_unlock(); 3277 mtx_unlock_spin(&tlbivax_mutex); 3278 } 3279 PMAP_UNLOCK(pv->pv_pmap); 3280 } 3281 rw_wunlock(&pvh_global_lock); 3282 } 3283 3284 /* 3285 * Return a count of reference bits for a page, clearing those bits. 3286 * It is not necessary for every reference bit to be cleared, but it 3287 * is necessary that 0 only be returned when there are truly no 3288 * reference bits set. 3289 * 3290 * As an optimization, update the page's dirty field if a modified bit is 3291 * found while counting reference bits. This opportunistic update can be 3292 * performed at low cost and can eliminate the need for some future calls 3293 * to pmap_is_modified(). However, since this function stops after 3294 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 3295 * dirty pages. Those dirty pages will only be detected by a future call 3296 * to pmap_is_modified(). 3297 */ 3298 static int 3299 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 3300 { 3301 pte_t *pte; 3302 pv_entry_t pv; 3303 int count; 3304 3305 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3306 ("mmu_booke_ts_referenced: page %p is not managed", m)); 3307 count = 0; 3308 rw_wlock(&pvh_global_lock); 3309 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3310 PMAP_LOCK(pv->pv_pmap); 3311 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3312 PTE_ISVALID(pte)) { 3313 if (PTE_ISMODIFIED(pte)) 3314 vm_page_dirty(m); 3315 if (PTE_ISREFERENCED(pte)) { 3316 mtx_lock_spin(&tlbivax_mutex); 3317 tlb_miss_lock(); 3318 3319 tlb0_flush_entry(pv->pv_va); 3320 *pte &= ~PTE_REFERENCED; 3321 3322 tlb_miss_unlock(); 3323 mtx_unlock_spin(&tlbivax_mutex); 3324 3325 if (++count >= PMAP_TS_REFERENCED_MAX) { 3326 PMAP_UNLOCK(pv->pv_pmap); 3327 break; 3328 } 3329 } 3330 } 3331 PMAP_UNLOCK(pv->pv_pmap); 3332 } 3333 rw_wunlock(&pvh_global_lock); 3334 return (count); 3335 } 3336 3337 /* 3338 * Clear the wired attribute from the mappings for the specified range of 3339 * addresses in the given pmap. Every valid mapping within that range must 3340 * have the wired attribute set. In contrast, invalid mappings cannot have 3341 * the wired attribute set, so they are ignored. 3342 * 3343 * The wired attribute of the page table entry is not a hardware feature, so 3344 * there is no need to invalidate any TLB entries. 3345 */ 3346 static void 3347 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3348 { 3349 vm_offset_t va; 3350 pte_t *pte; 3351 3352 PMAP_LOCK(pmap); 3353 for (va = sva; va < eva; va += PAGE_SIZE) { 3354 if ((pte = pte_find(mmu, pmap, va)) != NULL && 3355 PTE_ISVALID(pte)) { 3356 if (!PTE_ISWIRED(pte)) 3357 panic("mmu_booke_unwire: pte %p isn't wired", 3358 pte); 3359 *pte &= ~PTE_WIRED; 3360 pmap->pm_stats.wired_count--; 3361 } 3362 } 3363 PMAP_UNLOCK(pmap); 3364 3365 } 3366 3367 /* 3368 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 3369 * page. This count may be changed upwards or downwards in the future; it is 3370 * only necessary that true be returned for a small subset of pmaps for proper 3371 * page aging. 3372 */ 3373 static boolean_t 3374 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 3375 { 3376 pv_entry_t pv; 3377 int loops; 3378 boolean_t rv; 3379 3380 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3381 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 3382 loops = 0; 3383 rv = FALSE; 3384 rw_wlock(&pvh_global_lock); 3385 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3386 if (pv->pv_pmap == pmap) { 3387 rv = TRUE; 3388 break; 3389 } 3390 if (++loops >= 16) 3391 break; 3392 } 3393 rw_wunlock(&pvh_global_lock); 3394 return (rv); 3395 } 3396 3397 /* 3398 * Return the number of managed mappings to the given physical page that are 3399 * wired. 3400 */ 3401 static int 3402 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 3403 { 3404 pv_entry_t pv; 3405 pte_t *pte; 3406 int count = 0; 3407 3408 if ((m->oflags & VPO_UNMANAGED) != 0) 3409 return (count); 3410 rw_wlock(&pvh_global_lock); 3411 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3412 PMAP_LOCK(pv->pv_pmap); 3413 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 3414 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 3415 count++; 3416 PMAP_UNLOCK(pv->pv_pmap); 3417 } 3418 rw_wunlock(&pvh_global_lock); 3419 return (count); 3420 } 3421 3422 static int 3423 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 3424 { 3425 int i; 3426 vm_offset_t va; 3427 3428 /* 3429 * This currently does not work for entries that 3430 * overlap TLB1 entries. 3431 */ 3432 for (i = 0; i < TLB1_ENTRIES; i ++) { 3433 if (tlb1_iomapped(i, pa, size, &va) == 0) 3434 return (0); 3435 } 3436 3437 return (EFAULT); 3438 } 3439 3440 void 3441 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 3442 { 3443 vm_paddr_t ppa; 3444 vm_offset_t ofs; 3445 vm_size_t gran; 3446 3447 /* Minidumps are based on virtual memory addresses. */ 3448 if (do_minidump) { 3449 *va = (void *)(vm_offset_t)pa; 3450 return; 3451 } 3452 3453 /* Raw physical memory dumps don't have a virtual address. */ 3454 /* We always map a 256MB page at 256M. */ 3455 gran = 256 * 1024 * 1024; 3456 ppa = rounddown2(pa, gran); 3457 ofs = pa - ppa; 3458 *va = (void *)gran; 3459 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 3460 3461 if (sz > (gran - ofs)) 3462 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 3463 _TLB_ENTRY_IO); 3464 } 3465 3466 void 3467 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 3468 { 3469 vm_paddr_t ppa; 3470 vm_offset_t ofs; 3471 vm_size_t gran; 3472 tlb_entry_t e; 3473 int i; 3474 3475 /* Minidumps are based on virtual memory addresses. */ 3476 /* Nothing to do... */ 3477 if (do_minidump) 3478 return; 3479 3480 for (i = 0; i < TLB1_ENTRIES; i++) { 3481 tlb1_read_entry(&e, i); 3482 if (!(e.mas1 & MAS1_VALID)) 3483 break; 3484 } 3485 3486 /* Raw physical memory dumps don't have a virtual address. */ 3487 i--; 3488 e.mas1 = 0; 3489 e.mas2 = 0; 3490 e.mas3 = 0; 3491 tlb1_write_entry(&e, i); 3492 3493 gran = 256 * 1024 * 1024; 3494 ppa = rounddown2(pa, gran); 3495 ofs = pa - ppa; 3496 if (sz > (gran - ofs)) { 3497 i--; 3498 e.mas1 = 0; 3499 e.mas2 = 0; 3500 e.mas3 = 0; 3501 tlb1_write_entry(&e, i); 3502 } 3503 } 3504 3505 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 3506 3507 void 3508 mmu_booke_scan_init(mmu_t mmu) 3509 { 3510 vm_offset_t va; 3511 pte_t *pte; 3512 int i; 3513 3514 if (!do_minidump) { 3515 /* Initialize phys. segments for dumpsys(). */ 3516 memset(&dump_map, 0, sizeof(dump_map)); 3517 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 3518 &availmem_regions_sz); 3519 for (i = 0; i < physmem_regions_sz; i++) { 3520 dump_map[i].pa_start = physmem_regions[i].mr_start; 3521 dump_map[i].pa_size = physmem_regions[i].mr_size; 3522 } 3523 return; 3524 } 3525 3526 /* Virtual segments for minidumps: */ 3527 memset(&dump_map, 0, sizeof(dump_map)); 3528 3529 /* 1st: kernel .data and .bss. */ 3530 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 3531 dump_map[0].pa_size = 3532 round_page((uintptr_t)_end) - dump_map[0].pa_start; 3533 3534 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 3535 dump_map[1].pa_start = data_start; 3536 dump_map[1].pa_size = data_end - data_start; 3537 3538 /* 3rd: kernel VM. */ 3539 va = dump_map[1].pa_start + dump_map[1].pa_size; 3540 /* Find start of next chunk (from va). */ 3541 while (va < virtual_end) { 3542 /* Don't dump the buffer cache. */ 3543 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 3544 va = kmi.buffer_eva; 3545 continue; 3546 } 3547 pte = pte_find(mmu, kernel_pmap, va); 3548 if (pte != NULL && PTE_ISVALID(pte)) 3549 break; 3550 va += PAGE_SIZE; 3551 } 3552 if (va < virtual_end) { 3553 dump_map[2].pa_start = va; 3554 va += PAGE_SIZE; 3555 /* Find last page in chunk. */ 3556 while (va < virtual_end) { 3557 /* Don't run into the buffer cache. */ 3558 if (va == kmi.buffer_sva) 3559 break; 3560 pte = pte_find(mmu, kernel_pmap, va); 3561 if (pte == NULL || !PTE_ISVALID(pte)) 3562 break; 3563 va += PAGE_SIZE; 3564 } 3565 dump_map[2].pa_size = va - dump_map[2].pa_start; 3566 } 3567 } 3568 3569 /* 3570 * Map a set of physical memory pages into the kernel virtual address space. 3571 * Return a pointer to where it is mapped. This routine is intended to be used 3572 * for mapping device memory, NOT real memory. 3573 */ 3574 static void * 3575 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 3576 { 3577 3578 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 3579 } 3580 3581 static void * 3582 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 3583 { 3584 tlb_entry_t e; 3585 void *res; 3586 uintptr_t va, tmpva; 3587 vm_size_t sz; 3588 int i; 3589 3590 /* 3591 * Check if this is premapped in TLB1. Note: this should probably also 3592 * check whether a sequence of TLB1 entries exist that match the 3593 * requirement, but now only checks the easy case. 3594 */ 3595 for (i = 0; i < TLB1_ENTRIES; i++) { 3596 tlb1_read_entry(&e, i); 3597 if (!(e.mas1 & MAS1_VALID)) 3598 continue; 3599 if (pa >= e.phys && 3600 (pa + size) <= (e.phys + e.size) && 3601 (ma == VM_MEMATTR_DEFAULT || 3602 tlb_calc_wimg(pa, ma) == 3603 (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))) 3604 return (void *)(e.virt + 3605 (vm_offset_t)(pa - e.phys)); 3606 } 3607 3608 size = roundup(size, PAGE_SIZE); 3609 3610 /* 3611 * The device mapping area is between VM_MAXUSER_ADDRESS and 3612 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 3613 */ 3614 #ifdef SPARSE_MAPDEV 3615 /* 3616 * With a sparse mapdev, align to the largest starting region. This 3617 * could feasibly be optimized for a 'best-fit' alignment, but that 3618 * calculation could be very costly. 3619 * Align to the smaller of: 3620 * - first set bit in overlap of (pa & size mask) 3621 * - largest size envelope 3622 * 3623 * It's possible the device mapping may start at a PA that's not larger 3624 * than the size mask, so we need to offset in to maximize the TLB entry 3625 * range and minimize the number of used TLB entries. 3626 */ 3627 do { 3628 tmpva = tlb1_map_base; 3629 sz = ffsl(((1 << flsl(size-1)) - 1) & pa); 3630 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1; 3631 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa); 3632 #ifdef __powerpc64__ 3633 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size)); 3634 #else 3635 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 3636 #endif 3637 #else 3638 #ifdef __powerpc64__ 3639 va = atomic_fetchadd_long(&tlb1_map_base, size); 3640 #else 3641 va = atomic_fetchadd_int(&tlb1_map_base, size); 3642 #endif 3643 #endif 3644 res = (void *)va; 3645 3646 do { 3647 sz = 1 << (ilog2(size) & ~1); 3648 /* Align size to PA */ 3649 if (pa % sz != 0) { 3650 do { 3651 sz >>= 2; 3652 } while (pa % sz != 0); 3653 } 3654 /* Now align from there to VA */ 3655 if (va % sz != 0) { 3656 do { 3657 sz >>= 2; 3658 } while (va % sz != 0); 3659 } 3660 if (bootverbose) 3661 printf("Wiring VA=%lx to PA=%jx (size=%lx)\n", 3662 va, (uintmax_t)pa, sz); 3663 if (tlb1_set_entry(va, pa, sz, 3664 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)) < 0) 3665 return (NULL); 3666 size -= sz; 3667 pa += sz; 3668 va += sz; 3669 } while (size > 0); 3670 3671 return (res); 3672 } 3673 3674 /* 3675 * 'Unmap' a range mapped by mmu_booke_mapdev(). 3676 */ 3677 static void 3678 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 3679 { 3680 #ifdef SUPPORTS_SHRINKING_TLB1 3681 vm_offset_t base, offset; 3682 3683 /* 3684 * Unmap only if this is inside kernel virtual space. 3685 */ 3686 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 3687 base = trunc_page(va); 3688 offset = va & PAGE_MASK; 3689 size = roundup(offset + size, PAGE_SIZE); 3690 kva_free(base, size); 3691 } 3692 #endif 3693 } 3694 3695 /* 3696 * mmu_booke_object_init_pt preloads the ptes for a given object into the 3697 * specified pmap. This eliminates the blast of soft faults on process startup 3698 * and immediately after an mmap. 3699 */ 3700 static void 3701 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 3702 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 3703 { 3704 3705 VM_OBJECT_ASSERT_WLOCKED(object); 3706 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3707 ("mmu_booke_object_init_pt: non-device object")); 3708 } 3709 3710 /* 3711 * Perform the pmap work for mincore. 3712 */ 3713 static int 3714 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 3715 vm_paddr_t *locked_pa) 3716 { 3717 3718 /* XXX: this should be implemented at some point */ 3719 return (0); 3720 } 3721 3722 static int 3723 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 3724 vm_memattr_t mode) 3725 { 3726 vm_offset_t va; 3727 pte_t *pte; 3728 int i, j; 3729 tlb_entry_t e; 3730 3731 /* Check TLB1 mappings */ 3732 for (i = 0; i < TLB1_ENTRIES; i++) { 3733 tlb1_read_entry(&e, i); 3734 if (!(e.mas1 & MAS1_VALID)) 3735 continue; 3736 if (addr >= e.virt && addr < e.virt + e.size) 3737 break; 3738 } 3739 if (i < TLB1_ENTRIES) { 3740 /* Only allow full mappings to be modified for now. */ 3741 /* Validate the range. */ 3742 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 3743 tlb1_read_entry(&e, j); 3744 if (va != e.virt || (sz - (va - addr) < e.size)) 3745 return (EINVAL); 3746 } 3747 for (va = addr; va < addr + sz; va += e.size, i++) { 3748 tlb1_read_entry(&e, i); 3749 e.mas2 &= ~MAS2_WIMGE_MASK; 3750 e.mas2 |= tlb_calc_wimg(e.phys, mode); 3751 3752 /* 3753 * Write it out to the TLB. Should really re-sync with other 3754 * cores. 3755 */ 3756 tlb1_write_entry(&e, i); 3757 } 3758 return (0); 3759 } 3760 3761 /* Not in TLB1, try through pmap */ 3762 /* First validate the range. */ 3763 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 3764 pte = pte_find(mmu, kernel_pmap, va); 3765 if (pte == NULL || !PTE_ISVALID(pte)) 3766 return (EINVAL); 3767 } 3768 3769 mtx_lock_spin(&tlbivax_mutex); 3770 tlb_miss_lock(); 3771 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 3772 pte = pte_find(mmu, kernel_pmap, va); 3773 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 3774 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 3775 tlb0_flush_entry(va); 3776 } 3777 tlb_miss_unlock(); 3778 mtx_unlock_spin(&tlbivax_mutex); 3779 3780 return (0); 3781 } 3782 3783 /**************************************************************************/ 3784 /* TID handling */ 3785 /**************************************************************************/ 3786 3787 /* 3788 * Allocate a TID. If necessary, steal one from someone else. 3789 * The new TID is flushed from the TLB before returning. 3790 */ 3791 static tlbtid_t 3792 tid_alloc(pmap_t pmap) 3793 { 3794 tlbtid_t tid; 3795 int thiscpu; 3796 3797 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 3798 3799 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 3800 3801 thiscpu = PCPU_GET(cpuid); 3802 3803 tid = PCPU_GET(booke.tid_next); 3804 if (tid > TID_MAX) 3805 tid = TID_MIN; 3806 PCPU_SET(booke.tid_next, tid + 1); 3807 3808 /* If we are stealing TID then clear the relevant pmap's field */ 3809 if (tidbusy[thiscpu][tid] != NULL) { 3810 3811 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 3812 3813 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 3814 3815 /* Flush all entries from TLB0 matching this TID. */ 3816 tid_flush(tid); 3817 } 3818 3819 tidbusy[thiscpu][tid] = pmap; 3820 pmap->pm_tid[thiscpu] = tid; 3821 __asm __volatile("msync; isync"); 3822 3823 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3824 PCPU_GET(booke.tid_next)); 3825 3826 return (tid); 3827 } 3828 3829 /**************************************************************************/ 3830 /* TLB0 handling */ 3831 /**************************************************************************/ 3832 3833 /* Convert TLB0 va and way number to tlb0[] table index. */ 3834 static inline unsigned int 3835 tlb0_tableidx(vm_offset_t va, unsigned int way) 3836 { 3837 unsigned int idx; 3838 3839 idx = (way * TLB0_ENTRIES_PER_WAY); 3840 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3841 return (idx); 3842 } 3843 3844 /* 3845 * Invalidate TLB0 entry. 3846 */ 3847 static inline void 3848 tlb0_flush_entry(vm_offset_t va) 3849 { 3850 3851 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3852 3853 mtx_assert(&tlbivax_mutex, MA_OWNED); 3854 3855 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3856 __asm __volatile("isync; msync"); 3857 __asm __volatile("tlbsync; msync"); 3858 3859 CTR1(KTR_PMAP, "%s: e", __func__); 3860 } 3861 3862 3863 /**************************************************************************/ 3864 /* TLB1 handling */ 3865 /**************************************************************************/ 3866 3867 /* 3868 * TLB1 mapping notes: 3869 * 3870 * TLB1[0] Kernel text and data. 3871 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3872 * windows, other devices mappings. 3873 */ 3874 3875 /* 3876 * Read an entry from given TLB1 slot. 3877 */ 3878 void 3879 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 3880 { 3881 register_t msr; 3882 uint32_t mas0; 3883 3884 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 3885 3886 msr = mfmsr(); 3887 __asm __volatile("wrteei 0"); 3888 3889 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 3890 mtspr(SPR_MAS0, mas0); 3891 __asm __volatile("isync; tlbre"); 3892 3893 entry->mas1 = mfspr(SPR_MAS1); 3894 entry->mas2 = mfspr(SPR_MAS2); 3895 entry->mas3 = mfspr(SPR_MAS3); 3896 3897 switch ((mfpvr() >> 16) & 0xFFFF) { 3898 case FSL_E500v2: 3899 case FSL_E500mc: 3900 case FSL_E5500: 3901 case FSL_E6500: 3902 entry->mas7 = mfspr(SPR_MAS7); 3903 break; 3904 default: 3905 entry->mas7 = 0; 3906 break; 3907 } 3908 mtmsr(msr); 3909 3910 entry->virt = entry->mas2 & MAS2_EPN_MASK; 3911 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 3912 (entry->mas3 & MAS3_RPN); 3913 entry->size = 3914 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 3915 } 3916 3917 struct tlbwrite_args { 3918 tlb_entry_t *e; 3919 unsigned int idx; 3920 }; 3921 3922 static void 3923 tlb1_write_entry_int(void *arg) 3924 { 3925 struct tlbwrite_args *args = arg; 3926 uint32_t mas0; 3927 3928 /* Select entry */ 3929 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx); 3930 3931 mtspr(SPR_MAS0, mas0); 3932 mtspr(SPR_MAS1, args->e->mas1); 3933 mtspr(SPR_MAS2, args->e->mas2); 3934 mtspr(SPR_MAS3, args->e->mas3); 3935 switch ((mfpvr() >> 16) & 0xFFFF) { 3936 case FSL_E500mc: 3937 case FSL_E5500: 3938 case FSL_E6500: 3939 mtspr(SPR_MAS8, 0); 3940 /* FALLTHROUGH */ 3941 case FSL_E500v2: 3942 mtspr(SPR_MAS7, args->e->mas7); 3943 break; 3944 default: 3945 break; 3946 } 3947 3948 __asm __volatile("isync; tlbwe; isync; msync"); 3949 3950 } 3951 3952 static void 3953 tlb1_write_entry_sync(void *arg) 3954 { 3955 /* Empty synchronization point for smp_rendezvous(). */ 3956 } 3957 3958 /* 3959 * Write given entry to TLB1 hardware. 3960 */ 3961 static void 3962 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 3963 { 3964 struct tlbwrite_args args; 3965 3966 args.e = e; 3967 args.idx = idx; 3968 3969 #ifdef SMP 3970 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) { 3971 mb(); 3972 smp_rendezvous(tlb1_write_entry_sync, 3973 tlb1_write_entry_int, 3974 tlb1_write_entry_sync, &args); 3975 } else 3976 #endif 3977 { 3978 register_t msr; 3979 3980 msr = mfmsr(); 3981 __asm __volatile("wrteei 0"); 3982 tlb1_write_entry_int(&args); 3983 mtmsr(msr); 3984 } 3985 } 3986 3987 /* 3988 * Return the largest uint value log such that 2^log <= num. 3989 */ 3990 static unsigned int 3991 ilog2(unsigned long num) 3992 { 3993 long lz; 3994 3995 #ifdef __powerpc64__ 3996 __asm ("cntlzd %0, %1" : "=r" (lz) : "r" (num)); 3997 return (63 - lz); 3998 #else 3999 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 4000 return (31 - lz); 4001 #endif 4002 } 4003 4004 /* 4005 * Convert TLB TSIZE value to mapped region size. 4006 */ 4007 static vm_size_t 4008 tsize2size(unsigned int tsize) 4009 { 4010 4011 /* 4012 * size = 4^tsize KB 4013 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 4014 */ 4015 4016 return ((1 << (2 * tsize)) * 1024); 4017 } 4018 4019 /* 4020 * Convert region size (must be power of 4) to TLB TSIZE value. 4021 */ 4022 static unsigned int 4023 size2tsize(vm_size_t size) 4024 { 4025 4026 return (ilog2(size) / 2 - 5); 4027 } 4028 4029 /* 4030 * Register permanent kernel mapping in TLB1. 4031 * 4032 * Entries are created starting from index 0 (current free entry is 4033 * kept in tlb1_idx) and are not supposed to be invalidated. 4034 */ 4035 int 4036 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 4037 uint32_t flags) 4038 { 4039 tlb_entry_t e; 4040 uint32_t ts, tid; 4041 int tsize, index; 4042 4043 for (index = 0; index < TLB1_ENTRIES; index++) { 4044 tlb1_read_entry(&e, index); 4045 if ((e.mas1 & MAS1_VALID) == 0) 4046 break; 4047 /* Check if we're just updating the flags, and update them. */ 4048 if (e.phys == pa && e.virt == va && e.size == size) { 4049 e.mas2 = (va & MAS2_EPN_MASK) | flags; 4050 tlb1_write_entry(&e, index); 4051 return (0); 4052 } 4053 } 4054 if (index >= TLB1_ENTRIES) { 4055 printf("tlb1_set_entry: TLB1 full!\n"); 4056 return (-1); 4057 } 4058 4059 /* Convert size to TSIZE */ 4060 tsize = size2tsize(size); 4061 4062 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 4063 /* XXX TS is hard coded to 0 for now as we only use single address space */ 4064 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 4065 4066 e.phys = pa; 4067 e.virt = va; 4068 e.size = size; 4069 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 4070 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 4071 e.mas2 = (va & MAS2_EPN_MASK) | flags; 4072 4073 /* Set supervisor RWX permission bits */ 4074 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 4075 e.mas7 = (pa >> 32) & MAS7_RPN; 4076 4077 tlb1_write_entry(&e, index); 4078 4079 /* 4080 * XXX in general TLB1 updates should be propagated between CPUs, 4081 * since current design assumes to have the same TLB1 set-up on all 4082 * cores. 4083 */ 4084 return (0); 4085 } 4086 4087 /* 4088 * Map in contiguous RAM region into the TLB1 using maximum of 4089 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 4090 * 4091 * If necessary round up last entry size and return total size 4092 * used by all allocated entries. 4093 */ 4094 vm_size_t 4095 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 4096 { 4097 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 4098 vm_size_t mapped, pgsz, base, mask; 4099 int idx, nents; 4100 4101 /* Round up to the next 1M */ 4102 size = roundup2(size, 1 << 20); 4103 4104 mapped = 0; 4105 idx = 0; 4106 base = va; 4107 pgsz = 64*1024*1024; 4108 while (mapped < size) { 4109 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 4110 while (pgsz > (size - mapped)) 4111 pgsz >>= 2; 4112 pgs[idx++] = pgsz; 4113 mapped += pgsz; 4114 } 4115 4116 /* We under-map. Correct for this. */ 4117 if (mapped < size) { 4118 while (pgs[idx - 1] == pgsz) { 4119 idx--; 4120 mapped -= pgsz; 4121 } 4122 /* XXX We may increase beyond out starting point. */ 4123 pgsz <<= 2; 4124 pgs[idx++] = pgsz; 4125 mapped += pgsz; 4126 } 4127 } 4128 4129 nents = idx; 4130 mask = pgs[0] - 1; 4131 /* Align address to the boundary */ 4132 if (va & mask) { 4133 va = (va + mask) & ~mask; 4134 pa = (pa + mask) & ~mask; 4135 } 4136 4137 for (idx = 0; idx < nents; idx++) { 4138 pgsz = pgs[idx]; 4139 debugf("%u: %llx -> %jx, size=%jx\n", idx, pa, 4140 (uintmax_t)va, (uintmax_t)pgsz); 4141 tlb1_set_entry(va, pa, pgsz, 4142 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM); 4143 pa += pgsz; 4144 va += pgsz; 4145 } 4146 4147 mapped = (va - base); 4148 if (bootverbose) 4149 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n", 4150 mapped, mapped - size); 4151 return (mapped); 4152 } 4153 4154 /* 4155 * TLB1 initialization routine, to be called after the very first 4156 * assembler level setup done in locore.S. 4157 */ 4158 void 4159 tlb1_init() 4160 { 4161 uint32_t mas0, mas1, mas2, mas3, mas7; 4162 uint32_t tsz; 4163 4164 tlb1_get_tlbconf(); 4165 4166 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 4167 mtspr(SPR_MAS0, mas0); 4168 __asm __volatile("isync; tlbre"); 4169 4170 mas1 = mfspr(SPR_MAS1); 4171 mas2 = mfspr(SPR_MAS2); 4172 mas3 = mfspr(SPR_MAS3); 4173 mas7 = mfspr(SPR_MAS7); 4174 4175 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 4176 (mas3 & MAS3_RPN); 4177 4178 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4179 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 4180 4181 /* Setup TLB miss defaults */ 4182 set_mas4_defaults(); 4183 } 4184 4185 /* 4186 * pmap_early_io_unmap() should be used in short conjunction with 4187 * pmap_early_io_map(), as in the following snippet: 4188 * 4189 * x = pmap_early_io_map(...); 4190 * <do something with x> 4191 * pmap_early_io_unmap(x, size); 4192 * 4193 * And avoiding more allocations between. 4194 */ 4195 void 4196 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 4197 { 4198 int i; 4199 tlb_entry_t e; 4200 vm_size_t isize; 4201 4202 size = roundup(size, PAGE_SIZE); 4203 isize = size; 4204 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 4205 tlb1_read_entry(&e, i); 4206 if (!(e.mas1 & MAS1_VALID)) 4207 continue; 4208 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 4209 size -= e.size; 4210 e.mas1 &= ~MAS1_VALID; 4211 tlb1_write_entry(&e, i); 4212 } 4213 } 4214 if (tlb1_map_base == va + isize) 4215 tlb1_map_base -= isize; 4216 } 4217 4218 vm_offset_t 4219 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 4220 { 4221 vm_paddr_t pa_base; 4222 vm_offset_t va, sz; 4223 int i; 4224 tlb_entry_t e; 4225 4226 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 4227 4228 for (i = 0; i < TLB1_ENTRIES; i++) { 4229 tlb1_read_entry(&e, i); 4230 if (!(e.mas1 & MAS1_VALID)) 4231 continue; 4232 if (pa >= e.phys && (pa + size) <= 4233 (e.phys + e.size)) 4234 return (e.virt + (pa - e.phys)); 4235 } 4236 4237 pa_base = rounddown(pa, PAGE_SIZE); 4238 size = roundup(size + (pa - pa_base), PAGE_SIZE); 4239 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 4240 va = tlb1_map_base + (pa - pa_base); 4241 4242 do { 4243 sz = 1 << (ilog2(size) & ~1); 4244 tlb1_set_entry(tlb1_map_base, pa_base, sz, 4245 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 4246 size -= sz; 4247 pa_base += sz; 4248 tlb1_map_base += sz; 4249 } while (size > 0); 4250 4251 return (va); 4252 } 4253 4254 void 4255 pmap_track_page(pmap_t pmap, vm_offset_t va) 4256 { 4257 vm_paddr_t pa; 4258 vm_page_t page; 4259 struct pv_entry *pve; 4260 4261 va = trunc_page(va); 4262 pa = pmap_kextract(va); 4263 page = PHYS_TO_VM_PAGE(pa); 4264 4265 rw_wlock(&pvh_global_lock); 4266 PMAP_LOCK(pmap); 4267 4268 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 4269 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 4270 goto out; 4271 } 4272 } 4273 page->md.pv_tracked = true; 4274 pv_insert(pmap, va, page); 4275 out: 4276 PMAP_UNLOCK(pmap); 4277 rw_wunlock(&pvh_global_lock); 4278 } 4279 4280 4281 /* 4282 * Setup MAS4 defaults. 4283 * These values are loaded to MAS0-2 on a TLB miss. 4284 */ 4285 static void 4286 set_mas4_defaults(void) 4287 { 4288 uint32_t mas4; 4289 4290 /* Defaults: TLB0, PID0, TSIZED=4K */ 4291 mas4 = MAS4_TLBSELD0; 4292 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 4293 #ifdef SMP 4294 mas4 |= MAS4_MD; 4295 #endif 4296 mtspr(SPR_MAS4, mas4); 4297 __asm __volatile("isync"); 4298 } 4299 4300 4301 /* 4302 * Return 0 if the physical IO range is encompassed by one of the 4303 * the TLB1 entries, otherwise return related error code. 4304 */ 4305 static int 4306 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 4307 { 4308 uint32_t prot; 4309 vm_paddr_t pa_start; 4310 vm_paddr_t pa_end; 4311 unsigned int entry_tsize; 4312 vm_size_t entry_size; 4313 tlb_entry_t e; 4314 4315 *va = (vm_offset_t)NULL; 4316 4317 tlb1_read_entry(&e, i); 4318 /* Skip invalid entries */ 4319 if (!(e.mas1 & MAS1_VALID)) 4320 return (EINVAL); 4321 4322 /* 4323 * The entry must be cache-inhibited, guarded, and r/w 4324 * so it can function as an i/o page 4325 */ 4326 prot = e.mas2 & (MAS2_I | MAS2_G); 4327 if (prot != (MAS2_I | MAS2_G)) 4328 return (EPERM); 4329 4330 prot = e.mas3 & (MAS3_SR | MAS3_SW); 4331 if (prot != (MAS3_SR | MAS3_SW)) 4332 return (EPERM); 4333 4334 /* The address should be within the entry range. */ 4335 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4336 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 4337 4338 entry_size = tsize2size(entry_tsize); 4339 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 4340 (e.mas3 & MAS3_RPN); 4341 pa_end = pa_start + entry_size; 4342 4343 if ((pa < pa_start) || ((pa + size) > pa_end)) 4344 return (ERANGE); 4345 4346 /* Return virtual address of this mapping. */ 4347 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 4348 return (0); 4349 } 4350 4351 /* 4352 * Invalidate all TLB0 entries which match the given TID. Note this is 4353 * dedicated for cases when invalidations should NOT be propagated to other 4354 * CPUs. 4355 */ 4356 static void 4357 tid_flush(tlbtid_t tid) 4358 { 4359 register_t msr; 4360 uint32_t mas0, mas1, mas2; 4361 int entry, way; 4362 4363 4364 /* Don't evict kernel translations */ 4365 if (tid == TID_KERNEL) 4366 return; 4367 4368 msr = mfmsr(); 4369 __asm __volatile("wrteei 0"); 4370 4371 /* 4372 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use 4373 * it for PID invalidation. 4374 */ 4375 switch ((mfpvr() >> 16) & 0xffff) { 4376 case FSL_E500mc: 4377 case FSL_E5500: 4378 case FSL_E6500: 4379 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT); 4380 /* tlbilxpid */ 4381 __asm __volatile("isync; .long 0x7c000024; isync; msync"); 4382 mtmsr(msr); 4383 return; 4384 } 4385 4386 for (way = 0; way < TLB0_WAYS; way++) 4387 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 4388 4389 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 4390 mtspr(SPR_MAS0, mas0); 4391 4392 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 4393 mtspr(SPR_MAS2, mas2); 4394 4395 __asm __volatile("isync; tlbre"); 4396 4397 mas1 = mfspr(SPR_MAS1); 4398 4399 if (!(mas1 & MAS1_VALID)) 4400 continue; 4401 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 4402 continue; 4403 mas1 &= ~MAS1_VALID; 4404 mtspr(SPR_MAS1, mas1); 4405 __asm __volatile("isync; tlbwe; isync; msync"); 4406 } 4407 mtmsr(msr); 4408 } 4409 4410 #ifdef DDB 4411 /* Print out contents of the MAS registers for each TLB0 entry */ 4412 static void 4413 #ifdef __powerpc64__ 4414 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3, 4415 #else 4416 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 4417 #endif 4418 uint32_t mas7) 4419 { 4420 int as; 4421 char desc[3]; 4422 tlbtid_t tid; 4423 vm_size_t size; 4424 unsigned int tsize; 4425 4426 desc[2] = '\0'; 4427 if (mas1 & MAS1_VALID) 4428 desc[0] = 'V'; 4429 else 4430 desc[0] = ' '; 4431 4432 if (mas1 & MAS1_IPROT) 4433 desc[1] = 'P'; 4434 else 4435 desc[1] = ' '; 4436 4437 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 4438 tid = MAS1_GETTID(mas1); 4439 4440 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4441 size = 0; 4442 if (tsize) 4443 size = tsize2size(tsize); 4444 4445 printf("%3d: (%s) [AS=%d] " 4446 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 4447 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n", 4448 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 4449 } 4450 4451 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries) 4452 { 4453 uint32_t mas0, mas1, mas3, mas7; 4454 #ifdef __powerpc64__ 4455 uint64_t mas2; 4456 #else 4457 uint32_t mas2; 4458 #endif 4459 int entryidx, way, idx; 4460 4461 printf("TLB0 entries:\n"); 4462 for (way = 0; way < TLB0_WAYS; way ++) 4463 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 4464 4465 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 4466 mtspr(SPR_MAS0, mas0); 4467 4468 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 4469 mtspr(SPR_MAS2, mas2); 4470 4471 __asm __volatile("isync; tlbre"); 4472 4473 mas1 = mfspr(SPR_MAS1); 4474 mas2 = mfspr(SPR_MAS2); 4475 mas3 = mfspr(SPR_MAS3); 4476 mas7 = mfspr(SPR_MAS7); 4477 4478 idx = tlb0_tableidx(mas2, way); 4479 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 4480 } 4481 } 4482 4483 /* 4484 * Print out contents of the MAS registers for each TLB1 entry 4485 */ 4486 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries) 4487 { 4488 uint32_t mas0, mas1, mas3, mas7; 4489 #ifdef __powerpc64__ 4490 uint64_t mas2; 4491 #else 4492 uint32_t mas2; 4493 #endif 4494 int i; 4495 4496 printf("TLB1 entries:\n"); 4497 for (i = 0; i < TLB1_ENTRIES; i++) { 4498 4499 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 4500 mtspr(SPR_MAS0, mas0); 4501 4502 __asm __volatile("isync; tlbre"); 4503 4504 mas1 = mfspr(SPR_MAS1); 4505 mas2 = mfspr(SPR_MAS2); 4506 mas3 = mfspr(SPR_MAS3); 4507 mas7 = mfspr(SPR_MAS7); 4508 4509 tlb_print_entry(i, mas1, mas2, mas3, mas7); 4510 } 4511 } 4512 #endif 4513