1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include <sys/param.h> 55 #include <sys/malloc.h> 56 #include <sys/ktr.h> 57 #include <sys/proc.h> 58 #include <sys/user.h> 59 #include <sys/queue.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/linker.h> 63 #include <sys/msgbuf.h> 64 #include <sys/lock.h> 65 #include <sys/mutex.h> 66 #include <sys/rwlock.h> 67 #include <sys/sched.h> 68 #include <sys/smp.h> 69 #include <sys/vmmeter.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_page.h> 73 #include <vm/vm_kern.h> 74 #include <vm/vm_pageout.h> 75 #include <vm/vm_extern.h> 76 #include <vm/vm_object.h> 77 #include <vm/vm_param.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_pager.h> 80 #include <vm/uma.h> 81 82 #include <machine/cpu.h> 83 #include <machine/pcb.h> 84 #include <machine/platform.h> 85 86 #include <machine/tlb.h> 87 #include <machine/spr.h> 88 #include <machine/md_var.h> 89 #include <machine/mmuvar.h> 90 #include <machine/pmap.h> 91 #include <machine/pte.h> 92 93 #include "mmu_if.h" 94 95 #ifdef DEBUG 96 #define debugf(fmt, args...) printf(fmt, ##args) 97 #else 98 #define debugf(fmt, args...) 99 #endif 100 101 #define TODO panic("%s: not implemented", __func__); 102 103 extern struct mtx sched_lock; 104 105 extern int dumpsys_minidump; 106 107 extern unsigned char _etext[]; 108 extern unsigned char _end[]; 109 110 extern uint32_t *bootinfo; 111 112 #ifdef SMP 113 extern uint32_t bp_ntlb1s; 114 #endif 115 116 vm_paddr_t ccsrbar_pa; 117 vm_paddr_t kernload; 118 vm_offset_t kernstart; 119 vm_size_t kernsize; 120 121 /* Message buffer and tables. */ 122 static vm_offset_t data_start; 123 static vm_size_t data_end; 124 125 /* Phys/avail memory regions. */ 126 static struct mem_region *availmem_regions; 127 static int availmem_regions_sz; 128 static struct mem_region *physmem_regions; 129 static int physmem_regions_sz; 130 131 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 132 static vm_offset_t zero_page_va; 133 static struct mtx zero_page_mutex; 134 135 static struct mtx tlbivax_mutex; 136 137 /* 138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 139 * by idle thred only, no lock required. 140 */ 141 static vm_offset_t zero_page_idle_va; 142 143 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 144 static vm_offset_t copy_page_src_va; 145 static vm_offset_t copy_page_dst_va; 146 static struct mtx copy_page_mutex; 147 148 /**************************************************************************/ 149 /* PMAP */ 150 /**************************************************************************/ 151 152 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 153 vm_prot_t, boolean_t); 154 155 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 156 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 157 158 /* 159 * If user pmap is processed with mmu_booke_remove and the resident count 160 * drops to 0, there are no more pages to remove, so we need not continue. 161 */ 162 #define PMAP_REMOVE_DONE(pmap) \ 163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 164 165 extern void tid_flush(tlbtid_t); 166 167 /**************************************************************************/ 168 /* TLB and TID handling */ 169 /**************************************************************************/ 170 171 /* Translation ID busy table */ 172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 173 174 /* 175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 176 * core revisions and should be read from h/w registers during early config. 177 */ 178 uint32_t tlb0_entries; 179 uint32_t tlb0_ways; 180 uint32_t tlb0_entries_per_way; 181 182 #define TLB0_ENTRIES (tlb0_entries) 183 #define TLB0_WAYS (tlb0_ways) 184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186 #define TLB1_ENTRIES 16 187 188 /* In-ram copy of the TLB1 */ 189 static tlb_entry_t tlb1[TLB1_ENTRIES]; 190 191 /* Next free entry in the TLB1 */ 192 static unsigned int tlb1_idx; 193 194 static tlbtid_t tid_alloc(struct pmap *); 195 196 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 197 198 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 199 static void tlb1_write_entry(unsigned int); 200 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 201 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 202 203 static vm_size_t tsize2size(unsigned int); 204 static unsigned int size2tsize(vm_size_t); 205 static unsigned int ilog2(unsigned int); 206 207 static void set_mas4_defaults(void); 208 209 static inline void tlb0_flush_entry(vm_offset_t); 210 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 211 212 /**************************************************************************/ 213 /* Page table management */ 214 /**************************************************************************/ 215 216 static struct rwlock_padalign pvh_global_lock; 217 218 /* Data for the pv entry allocation mechanism */ 219 static uma_zone_t pvzone; 220 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 221 222 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 223 224 #ifndef PMAP_SHPGPERPROC 225 #define PMAP_SHPGPERPROC 200 226 #endif 227 228 static void ptbl_init(void); 229 static struct ptbl_buf *ptbl_buf_alloc(void); 230 static void ptbl_buf_free(struct ptbl_buf *); 231 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 232 233 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 234 static void ptbl_free(mmu_t, pmap_t, unsigned int); 235 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 236 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 237 238 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 239 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 240 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 241 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 242 243 static pv_entry_t pv_alloc(void); 244 static void pv_free(pv_entry_t); 245 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 246 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 247 248 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 249 #define PTBL_BUFS (128 * 16) 250 251 struct ptbl_buf { 252 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 253 vm_offset_t kva; /* va of mapping */ 254 }; 255 256 /* ptbl free list and a lock used for access synchronization. */ 257 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 258 static struct mtx ptbl_buf_freelist_lock; 259 260 /* Base address of kva space allocated fot ptbl bufs. */ 261 static vm_offset_t ptbl_buf_pool_vabase; 262 263 /* Pointer to ptbl_buf structures. */ 264 static struct ptbl_buf *ptbl_bufs; 265 266 void pmap_bootstrap_ap(volatile uint32_t *); 267 268 /* 269 * Kernel MMU interface 270 */ 271 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 272 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 273 static void mmu_booke_clear_reference(mmu_t, vm_page_t); 274 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 275 vm_size_t, vm_offset_t); 276 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 277 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 278 vm_prot_t, boolean_t); 279 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 280 vm_page_t, vm_prot_t); 281 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 282 vm_prot_t); 283 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 284 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 285 vm_prot_t); 286 static void mmu_booke_init(mmu_t); 287 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 288 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 289 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 290 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 291 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 292 int); 293 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 294 vm_paddr_t *); 295 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 296 vm_object_t, vm_pindex_t, vm_size_t); 297 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 298 static void mmu_booke_page_init(mmu_t, vm_page_t); 299 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 300 static void mmu_booke_pinit(mmu_t, pmap_t); 301 static void mmu_booke_pinit0(mmu_t, pmap_t); 302 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 303 vm_prot_t); 304 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 305 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 306 static void mmu_booke_release(mmu_t, pmap_t); 307 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 308 static void mmu_booke_remove_all(mmu_t, vm_page_t); 309 static void mmu_booke_remove_write(mmu_t, vm_page_t); 310 static void mmu_booke_zero_page(mmu_t, vm_page_t); 311 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 312 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 313 static void mmu_booke_activate(mmu_t, struct thread *); 314 static void mmu_booke_deactivate(mmu_t, struct thread *); 315 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 316 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 317 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 318 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 319 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 320 static void mmu_booke_kremove(mmu_t, vm_offset_t); 321 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 322 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 323 vm_size_t); 324 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 325 vm_size_t, vm_size_t *); 326 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 327 vm_size_t, vm_offset_t); 328 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 329 330 static mmu_method_t mmu_booke_methods[] = { 331 /* pmap dispatcher interface */ 332 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 333 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 334 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 335 MMUMETHOD(mmu_copy, mmu_booke_copy), 336 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 337 MMUMETHOD(mmu_enter, mmu_booke_enter), 338 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 339 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 340 MMUMETHOD(mmu_extract, mmu_booke_extract), 341 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 342 MMUMETHOD(mmu_init, mmu_booke_init), 343 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 344 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 345 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 346 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 347 MMUMETHOD(mmu_map, mmu_booke_map), 348 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 349 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 350 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 351 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 352 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 353 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 354 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 355 MMUMETHOD(mmu_protect, mmu_booke_protect), 356 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 357 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 358 MMUMETHOD(mmu_release, mmu_booke_release), 359 MMUMETHOD(mmu_remove, mmu_booke_remove), 360 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 361 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 362 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 363 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 364 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 365 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 366 MMUMETHOD(mmu_activate, mmu_booke_activate), 367 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 368 369 /* Internal interfaces */ 370 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 371 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 372 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 373 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 374 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 375 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 376 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 377 378 /* dumpsys() support */ 379 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 380 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 381 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 382 383 { 0, 0 } 384 }; 385 386 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 387 388 static inline void 389 tlb_miss_lock(void) 390 { 391 #ifdef SMP 392 struct pcpu *pc; 393 394 if (!smp_started) 395 return; 396 397 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 398 if (pc != pcpup) { 399 400 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 401 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 402 403 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 404 ("tlb_miss_lock: tried to lock self")); 405 406 tlb_lock(pc->pc_booke_tlb_lock); 407 408 CTR1(KTR_PMAP, "%s: locked", __func__); 409 } 410 } 411 #endif 412 } 413 414 static inline void 415 tlb_miss_unlock(void) 416 { 417 #ifdef SMP 418 struct pcpu *pc; 419 420 if (!smp_started) 421 return; 422 423 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 424 if (pc != pcpup) { 425 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 426 __func__, pc->pc_cpuid); 427 428 tlb_unlock(pc->pc_booke_tlb_lock); 429 430 CTR1(KTR_PMAP, "%s: unlocked", __func__); 431 } 432 } 433 #endif 434 } 435 436 /* Return number of entries in TLB0. */ 437 static __inline void 438 tlb0_get_tlbconf(void) 439 { 440 uint32_t tlb0_cfg; 441 442 tlb0_cfg = mfspr(SPR_TLB0CFG); 443 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 444 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 445 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 446 } 447 448 /* Initialize pool of kva ptbl buffers. */ 449 static void 450 ptbl_init(void) 451 { 452 int i; 453 454 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 455 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 456 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 457 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 458 459 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 460 TAILQ_INIT(&ptbl_buf_freelist); 461 462 for (i = 0; i < PTBL_BUFS; i++) { 463 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 464 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 465 } 466 } 467 468 /* Get a ptbl_buf from the freelist. */ 469 static struct ptbl_buf * 470 ptbl_buf_alloc(void) 471 { 472 struct ptbl_buf *buf; 473 474 mtx_lock(&ptbl_buf_freelist_lock); 475 buf = TAILQ_FIRST(&ptbl_buf_freelist); 476 if (buf != NULL) 477 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 478 mtx_unlock(&ptbl_buf_freelist_lock); 479 480 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 481 482 return (buf); 483 } 484 485 /* Return ptbl buff to free pool. */ 486 static void 487 ptbl_buf_free(struct ptbl_buf *buf) 488 { 489 490 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 491 492 mtx_lock(&ptbl_buf_freelist_lock); 493 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 494 mtx_unlock(&ptbl_buf_freelist_lock); 495 } 496 497 /* 498 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 499 */ 500 static void 501 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 502 { 503 struct ptbl_buf *pbuf; 504 505 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 506 507 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 508 509 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 510 if (pbuf->kva == (vm_offset_t)ptbl) { 511 /* Remove from pmap ptbl buf list. */ 512 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 513 514 /* Free corresponding ptbl buf. */ 515 ptbl_buf_free(pbuf); 516 break; 517 } 518 } 519 520 /* Allocate page table. */ 521 static pte_t * 522 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 523 { 524 vm_page_t mtbl[PTBL_PAGES]; 525 vm_page_t m; 526 struct ptbl_buf *pbuf; 527 unsigned int pidx; 528 pte_t *ptbl; 529 int i; 530 531 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 532 (pmap == kernel_pmap), pdir_idx); 533 534 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 535 ("ptbl_alloc: invalid pdir_idx")); 536 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 537 ("pte_alloc: valid ptbl entry exists!")); 538 539 pbuf = ptbl_buf_alloc(); 540 if (pbuf == NULL) 541 panic("pte_alloc: couldn't alloc kernel virtual memory"); 542 543 ptbl = (pte_t *)pbuf->kva; 544 545 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 546 547 /* Allocate ptbl pages, this will sleep! */ 548 for (i = 0; i < PTBL_PAGES; i++) { 549 pidx = (PTBL_PAGES * pdir_idx) + i; 550 while ((m = vm_page_alloc(NULL, pidx, 551 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 552 553 PMAP_UNLOCK(pmap); 554 rw_wunlock(&pvh_global_lock); 555 VM_WAIT; 556 rw_wlock(&pvh_global_lock); 557 PMAP_LOCK(pmap); 558 } 559 mtbl[i] = m; 560 } 561 562 /* Map allocated pages into kernel_pmap. */ 563 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 564 565 /* Zero whole ptbl. */ 566 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 567 568 /* Add pbuf to the pmap ptbl bufs list. */ 569 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 570 571 return (ptbl); 572 } 573 574 /* Free ptbl pages and invalidate pdir entry. */ 575 static void 576 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 577 { 578 pte_t *ptbl; 579 vm_paddr_t pa; 580 vm_offset_t va; 581 vm_page_t m; 582 int i; 583 584 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 585 (pmap == kernel_pmap), pdir_idx); 586 587 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 588 ("ptbl_free: invalid pdir_idx")); 589 590 ptbl = pmap->pm_pdir[pdir_idx]; 591 592 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 593 594 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 595 596 /* 597 * Invalidate the pdir entry as soon as possible, so that other CPUs 598 * don't attempt to look up the page tables we are releasing. 599 */ 600 mtx_lock_spin(&tlbivax_mutex); 601 tlb_miss_lock(); 602 603 pmap->pm_pdir[pdir_idx] = NULL; 604 605 tlb_miss_unlock(); 606 mtx_unlock_spin(&tlbivax_mutex); 607 608 for (i = 0; i < PTBL_PAGES; i++) { 609 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 610 pa = pte_vatopa(mmu, kernel_pmap, va); 611 m = PHYS_TO_VM_PAGE(pa); 612 vm_page_free_zero(m); 613 atomic_subtract_int(&cnt.v_wire_count, 1); 614 mmu_booke_kremove(mmu, va); 615 } 616 617 ptbl_free_pmap_ptbl(pmap, ptbl); 618 } 619 620 /* 621 * Decrement ptbl pages hold count and attempt to free ptbl pages. 622 * Called when removing pte entry from ptbl. 623 * 624 * Return 1 if ptbl pages were freed. 625 */ 626 static int 627 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 628 { 629 pte_t *ptbl; 630 vm_paddr_t pa; 631 vm_page_t m; 632 int i; 633 634 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 635 (pmap == kernel_pmap), pdir_idx); 636 637 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 638 ("ptbl_unhold: invalid pdir_idx")); 639 KASSERT((pmap != kernel_pmap), 640 ("ptbl_unhold: unholding kernel ptbl!")); 641 642 ptbl = pmap->pm_pdir[pdir_idx]; 643 644 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 645 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 646 ("ptbl_unhold: non kva ptbl")); 647 648 /* decrement hold count */ 649 for (i = 0; i < PTBL_PAGES; i++) { 650 pa = pte_vatopa(mmu, kernel_pmap, 651 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 652 m = PHYS_TO_VM_PAGE(pa); 653 m->wire_count--; 654 } 655 656 /* 657 * Free ptbl pages if there are no pte etries in this ptbl. 658 * wire_count has the same value for all ptbl pages, so check the last 659 * page. 660 */ 661 if (m->wire_count == 0) { 662 ptbl_free(mmu, pmap, pdir_idx); 663 664 //debugf("ptbl_unhold: e (freed ptbl)\n"); 665 return (1); 666 } 667 668 return (0); 669 } 670 671 /* 672 * Increment hold count for ptbl pages. This routine is used when a new pte 673 * entry is being inserted into the ptbl. 674 */ 675 static void 676 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 677 { 678 vm_paddr_t pa; 679 pte_t *ptbl; 680 vm_page_t m; 681 int i; 682 683 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 684 pdir_idx); 685 686 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 687 ("ptbl_hold: invalid pdir_idx")); 688 KASSERT((pmap != kernel_pmap), 689 ("ptbl_hold: holding kernel ptbl!")); 690 691 ptbl = pmap->pm_pdir[pdir_idx]; 692 693 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 694 695 for (i = 0; i < PTBL_PAGES; i++) { 696 pa = pte_vatopa(mmu, kernel_pmap, 697 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 698 m = PHYS_TO_VM_PAGE(pa); 699 m->wire_count++; 700 } 701 } 702 703 /* Allocate pv_entry structure. */ 704 pv_entry_t 705 pv_alloc(void) 706 { 707 pv_entry_t pv; 708 709 pv_entry_count++; 710 if (pv_entry_count > pv_entry_high_water) 711 pagedaemon_wakeup(); 712 pv = uma_zalloc(pvzone, M_NOWAIT); 713 714 return (pv); 715 } 716 717 /* Free pv_entry structure. */ 718 static __inline void 719 pv_free(pv_entry_t pve) 720 { 721 722 pv_entry_count--; 723 uma_zfree(pvzone, pve); 724 } 725 726 727 /* Allocate and initialize pv_entry structure. */ 728 static void 729 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 730 { 731 pv_entry_t pve; 732 733 //int su = (pmap == kernel_pmap); 734 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 735 // (u_int32_t)pmap, va, (u_int32_t)m); 736 737 pve = pv_alloc(); 738 if (pve == NULL) 739 panic("pv_insert: no pv entries!"); 740 741 pve->pv_pmap = pmap; 742 pve->pv_va = va; 743 744 /* add to pv_list */ 745 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 746 rw_assert(&pvh_global_lock, RA_WLOCKED); 747 748 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 749 750 //debugf("pv_insert: e\n"); 751 } 752 753 /* Destroy pv entry. */ 754 static void 755 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 756 { 757 pv_entry_t pve; 758 759 //int su = (pmap == kernel_pmap); 760 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 761 762 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 763 rw_assert(&pvh_global_lock, RA_WLOCKED); 764 765 /* find pv entry */ 766 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 767 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 768 /* remove from pv_list */ 769 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 770 if (TAILQ_EMPTY(&m->md.pv_list)) 771 vm_page_aflag_clear(m, PGA_WRITEABLE); 772 773 /* free pv entry struct */ 774 pv_free(pve); 775 break; 776 } 777 } 778 779 //debugf("pv_remove: e\n"); 780 } 781 782 /* 783 * Clean pte entry, try to free page table page if requested. 784 * 785 * Return 1 if ptbl pages were freed, otherwise return 0. 786 */ 787 static int 788 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 789 { 790 unsigned int pdir_idx = PDIR_IDX(va); 791 unsigned int ptbl_idx = PTBL_IDX(va); 792 vm_page_t m; 793 pte_t *ptbl; 794 pte_t *pte; 795 796 //int su = (pmap == kernel_pmap); 797 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 798 // su, (u_int32_t)pmap, va, flags); 799 800 ptbl = pmap->pm_pdir[pdir_idx]; 801 KASSERT(ptbl, ("pte_remove: null ptbl")); 802 803 pte = &ptbl[ptbl_idx]; 804 805 if (pte == NULL || !PTE_ISVALID(pte)) 806 return (0); 807 808 if (PTE_ISWIRED(pte)) 809 pmap->pm_stats.wired_count--; 810 811 /* Handle managed entry. */ 812 if (PTE_ISMANAGED(pte)) { 813 /* Get vm_page_t for mapped pte. */ 814 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 815 816 if (PTE_ISMODIFIED(pte)) 817 vm_page_dirty(m); 818 819 if (PTE_ISREFERENCED(pte)) 820 vm_page_aflag_set(m, PGA_REFERENCED); 821 822 pv_remove(pmap, va, m); 823 } 824 825 mtx_lock_spin(&tlbivax_mutex); 826 tlb_miss_lock(); 827 828 tlb0_flush_entry(va); 829 pte->flags = 0; 830 pte->rpn = 0; 831 832 tlb_miss_unlock(); 833 mtx_unlock_spin(&tlbivax_mutex); 834 835 pmap->pm_stats.resident_count--; 836 837 if (flags & PTBL_UNHOLD) { 838 //debugf("pte_remove: e (unhold)\n"); 839 return (ptbl_unhold(mmu, pmap, pdir_idx)); 840 } 841 842 //debugf("pte_remove: e\n"); 843 return (0); 844 } 845 846 /* 847 * Insert PTE for a given page and virtual address. 848 */ 849 static void 850 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 851 { 852 unsigned int pdir_idx = PDIR_IDX(va); 853 unsigned int ptbl_idx = PTBL_IDX(va); 854 pte_t *ptbl, *pte; 855 856 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 857 pmap == kernel_pmap, pmap, va); 858 859 /* Get the page table pointer. */ 860 ptbl = pmap->pm_pdir[pdir_idx]; 861 862 if (ptbl == NULL) { 863 /* Allocate page table pages. */ 864 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 865 } else { 866 /* 867 * Check if there is valid mapping for requested 868 * va, if there is, remove it. 869 */ 870 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 871 if (PTE_ISVALID(pte)) { 872 pte_remove(mmu, pmap, va, PTBL_HOLD); 873 } else { 874 /* 875 * pte is not used, increment hold count 876 * for ptbl pages. 877 */ 878 if (pmap != kernel_pmap) 879 ptbl_hold(mmu, pmap, pdir_idx); 880 } 881 } 882 883 /* 884 * Insert pv_entry into pv_list for mapped page if part of managed 885 * memory. 886 */ 887 if ((m->oflags & VPO_UNMANAGED) == 0) { 888 flags |= PTE_MANAGED; 889 890 /* Create and insert pv entry. */ 891 pv_insert(pmap, va, m); 892 } 893 894 pmap->pm_stats.resident_count++; 895 896 mtx_lock_spin(&tlbivax_mutex); 897 tlb_miss_lock(); 898 899 tlb0_flush_entry(va); 900 if (pmap->pm_pdir[pdir_idx] == NULL) { 901 /* 902 * If we just allocated a new page table, hook it in 903 * the pdir. 904 */ 905 pmap->pm_pdir[pdir_idx] = ptbl; 906 } 907 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 908 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 909 pte->flags |= (PTE_VALID | flags); 910 911 tlb_miss_unlock(); 912 mtx_unlock_spin(&tlbivax_mutex); 913 } 914 915 /* Return the pa for the given pmap/va. */ 916 static vm_paddr_t 917 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 918 { 919 vm_paddr_t pa = 0; 920 pte_t *pte; 921 922 pte = pte_find(mmu, pmap, va); 923 if ((pte != NULL) && PTE_ISVALID(pte)) 924 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 925 return (pa); 926 } 927 928 /* Get a pointer to a PTE in a page table. */ 929 static pte_t * 930 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 931 { 932 unsigned int pdir_idx = PDIR_IDX(va); 933 unsigned int ptbl_idx = PTBL_IDX(va); 934 935 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 936 937 if (pmap->pm_pdir[pdir_idx]) 938 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 939 940 return (NULL); 941 } 942 943 /**************************************************************************/ 944 /* PMAP related */ 945 /**************************************************************************/ 946 947 /* 948 * This is called during booke_init, before the system is really initialized. 949 */ 950 static void 951 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 952 { 953 vm_offset_t phys_kernelend; 954 struct mem_region *mp, *mp1; 955 int cnt, i, j; 956 u_int s, e, sz; 957 u_int phys_avail_count; 958 vm_size_t physsz, hwphyssz, kstack0_sz; 959 vm_offset_t kernel_pdir, kstack0, va; 960 vm_paddr_t kstack0_phys; 961 void *dpcpu; 962 pte_t *pte; 963 964 debugf("mmu_booke_bootstrap: entered\n"); 965 966 /* Initialize invalidation mutex */ 967 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 968 969 /* Read TLB0 size and associativity. */ 970 tlb0_get_tlbconf(); 971 972 /* 973 * Align kernel start and end address (kernel image). 974 * Note that kernel end does not necessarily relate to kernsize. 975 * kernsize is the size of the kernel that is actually mapped. 976 * Also note that "start - 1" is deliberate. With SMP, the 977 * entry point is exactly a page from the actual load address. 978 * As such, trunc_page() has no effect and we're off by a page. 979 * Since we always have the ELF header between the load address 980 * and the entry point, we can safely subtract 1 to compensate. 981 */ 982 kernstart = trunc_page(start - 1); 983 data_start = round_page(kernelend); 984 data_end = data_start; 985 986 /* 987 * Addresses of preloaded modules (like file systems) use 988 * physical addresses. Make sure we relocate those into 989 * virtual addresses. 990 */ 991 preload_addr_relocate = kernstart - kernload; 992 993 /* Allocate the dynamic per-cpu area. */ 994 dpcpu = (void *)data_end; 995 data_end += DPCPU_SIZE; 996 997 /* Allocate space for the message buffer. */ 998 msgbufp = (struct msgbuf *)data_end; 999 data_end += msgbufsize; 1000 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1001 data_end); 1002 1003 data_end = round_page(data_end); 1004 1005 /* Allocate space for ptbl_bufs. */ 1006 ptbl_bufs = (struct ptbl_buf *)data_end; 1007 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1008 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1009 data_end); 1010 1011 data_end = round_page(data_end); 1012 1013 /* Allocate PTE tables for kernel KVA. */ 1014 kernel_pdir = data_end; 1015 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1016 PDIR_SIZE - 1) / PDIR_SIZE; 1017 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1018 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1019 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1020 1021 debugf(" data_end: 0x%08x\n", data_end); 1022 if (data_end - kernstart > kernsize) { 1023 kernsize += tlb1_mapin_region(kernstart + kernsize, 1024 kernload + kernsize, (data_end - kernstart) - kernsize); 1025 } 1026 data_end = kernstart + kernsize; 1027 debugf(" updated data_end: 0x%08x\n", data_end); 1028 1029 /* 1030 * Clear the structures - note we can only do it safely after the 1031 * possible additional TLB1 translations are in place (above) so that 1032 * all range up to the currently calculated 'data_end' is covered. 1033 */ 1034 dpcpu_init(dpcpu, 0); 1035 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1036 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1037 1038 /*******************************************************/ 1039 /* Set the start and end of kva. */ 1040 /*******************************************************/ 1041 virtual_avail = round_page(data_end); 1042 virtual_end = VM_MAX_KERNEL_ADDRESS; 1043 1044 /* Allocate KVA space for page zero/copy operations. */ 1045 zero_page_va = virtual_avail; 1046 virtual_avail += PAGE_SIZE; 1047 zero_page_idle_va = virtual_avail; 1048 virtual_avail += PAGE_SIZE; 1049 copy_page_src_va = virtual_avail; 1050 virtual_avail += PAGE_SIZE; 1051 copy_page_dst_va = virtual_avail; 1052 virtual_avail += PAGE_SIZE; 1053 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1054 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1055 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1056 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1057 1058 /* Initialize page zero/copy mutexes. */ 1059 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1060 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1061 1062 /* Allocate KVA space for ptbl bufs. */ 1063 ptbl_buf_pool_vabase = virtual_avail; 1064 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1065 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1066 ptbl_buf_pool_vabase, virtual_avail); 1067 1068 /* Calculate corresponding physical addresses for the kernel region. */ 1069 phys_kernelend = kernload + kernsize; 1070 debugf("kernel image and allocated data:\n"); 1071 debugf(" kernload = 0x%08x\n", kernload); 1072 debugf(" kernstart = 0x%08x\n", kernstart); 1073 debugf(" kernsize = 0x%08x\n", kernsize); 1074 1075 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1076 panic("mmu_booke_bootstrap: phys_avail too small"); 1077 1078 /* 1079 * Remove kernel physical address range from avail regions list. Page 1080 * align all regions. Non-page aligned memory isn't very interesting 1081 * to us. Also, sort the entries for ascending addresses. 1082 */ 1083 1084 /* Retrieve phys/avail mem regions */ 1085 mem_regions(&physmem_regions, &physmem_regions_sz, 1086 &availmem_regions, &availmem_regions_sz); 1087 sz = 0; 1088 cnt = availmem_regions_sz; 1089 debugf("processing avail regions:\n"); 1090 for (mp = availmem_regions; mp->mr_size; mp++) { 1091 s = mp->mr_start; 1092 e = mp->mr_start + mp->mr_size; 1093 debugf(" %08x-%08x -> ", s, e); 1094 /* Check whether this region holds all of the kernel. */ 1095 if (s < kernload && e > phys_kernelend) { 1096 availmem_regions[cnt].mr_start = phys_kernelend; 1097 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1098 e = kernload; 1099 } 1100 /* Look whether this regions starts within the kernel. */ 1101 if (s >= kernload && s < phys_kernelend) { 1102 if (e <= phys_kernelend) 1103 goto empty; 1104 s = phys_kernelend; 1105 } 1106 /* Now look whether this region ends within the kernel. */ 1107 if (e > kernload && e <= phys_kernelend) { 1108 if (s >= kernload) 1109 goto empty; 1110 e = kernload; 1111 } 1112 /* Now page align the start and size of the region. */ 1113 s = round_page(s); 1114 e = trunc_page(e); 1115 if (e < s) 1116 e = s; 1117 sz = e - s; 1118 debugf("%08x-%08x = %x\n", s, e, sz); 1119 1120 /* Check whether some memory is left here. */ 1121 if (sz == 0) { 1122 empty: 1123 memmove(mp, mp + 1, 1124 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1125 cnt--; 1126 mp--; 1127 continue; 1128 } 1129 1130 /* Do an insertion sort. */ 1131 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1132 if (s < mp1->mr_start) 1133 break; 1134 if (mp1 < mp) { 1135 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1136 mp1->mr_start = s; 1137 mp1->mr_size = sz; 1138 } else { 1139 mp->mr_start = s; 1140 mp->mr_size = sz; 1141 } 1142 } 1143 availmem_regions_sz = cnt; 1144 1145 /*******************************************************/ 1146 /* Steal physical memory for kernel stack from the end */ 1147 /* of the first avail region */ 1148 /*******************************************************/ 1149 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1150 kstack0_phys = availmem_regions[0].mr_start + 1151 availmem_regions[0].mr_size; 1152 kstack0_phys -= kstack0_sz; 1153 availmem_regions[0].mr_size -= kstack0_sz; 1154 1155 /*******************************************************/ 1156 /* Fill in phys_avail table, based on availmem_regions */ 1157 /*******************************************************/ 1158 phys_avail_count = 0; 1159 physsz = 0; 1160 hwphyssz = 0; 1161 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1162 1163 debugf("fill in phys_avail:\n"); 1164 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1165 1166 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1167 availmem_regions[i].mr_start, 1168 availmem_regions[i].mr_start + 1169 availmem_regions[i].mr_size, 1170 availmem_regions[i].mr_size); 1171 1172 if (hwphyssz != 0 && 1173 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1174 debugf(" hw.physmem adjust\n"); 1175 if (physsz < hwphyssz) { 1176 phys_avail[j] = availmem_regions[i].mr_start; 1177 phys_avail[j + 1] = 1178 availmem_regions[i].mr_start + 1179 hwphyssz - physsz; 1180 physsz = hwphyssz; 1181 phys_avail_count++; 1182 } 1183 break; 1184 } 1185 1186 phys_avail[j] = availmem_regions[i].mr_start; 1187 phys_avail[j + 1] = availmem_regions[i].mr_start + 1188 availmem_regions[i].mr_size; 1189 phys_avail_count++; 1190 physsz += availmem_regions[i].mr_size; 1191 } 1192 physmem = btoc(physsz); 1193 1194 /* Calculate the last available physical address. */ 1195 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1196 ; 1197 Maxmem = powerpc_btop(phys_avail[i + 1]); 1198 1199 debugf("Maxmem = 0x%08lx\n", Maxmem); 1200 debugf("phys_avail_count = %d\n", phys_avail_count); 1201 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1202 physmem); 1203 1204 /*******************************************************/ 1205 /* Initialize (statically allocated) kernel pmap. */ 1206 /*******************************************************/ 1207 PMAP_LOCK_INIT(kernel_pmap); 1208 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1209 1210 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1211 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1212 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1213 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1214 1215 /* Initialize kernel pdir */ 1216 for (i = 0; i < kernel_ptbls; i++) 1217 kernel_pmap->pm_pdir[kptbl_min + i] = 1218 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1219 1220 for (i = 0; i < MAXCPU; i++) { 1221 kernel_pmap->pm_tid[i] = TID_KERNEL; 1222 1223 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1224 tidbusy[i][0] = kernel_pmap; 1225 } 1226 1227 /* 1228 * Fill in PTEs covering kernel code and data. They are not required 1229 * for address translation, as this area is covered by static TLB1 1230 * entries, but for pte_vatopa() to work correctly with kernel area 1231 * addresses. 1232 */ 1233 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1234 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1235 pte->rpn = kernload + (va - kernstart); 1236 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1237 PTE_VALID; 1238 } 1239 /* Mark kernel_pmap active on all CPUs */ 1240 CPU_FILL(&kernel_pmap->pm_active); 1241 1242 /* 1243 * Initialize the global pv list lock. 1244 */ 1245 rw_init(&pvh_global_lock, "pmap pv global"); 1246 1247 /*******************************************************/ 1248 /* Final setup */ 1249 /*******************************************************/ 1250 1251 /* Enter kstack0 into kernel map, provide guard page */ 1252 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1253 thread0.td_kstack = kstack0; 1254 thread0.td_kstack_pages = KSTACK_PAGES; 1255 1256 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1257 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1258 kstack0_phys, kstack0_phys + kstack0_sz); 1259 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1260 1261 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1262 for (i = 0; i < KSTACK_PAGES; i++) { 1263 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1264 kstack0 += PAGE_SIZE; 1265 kstack0_phys += PAGE_SIZE; 1266 } 1267 1268 debugf("virtual_avail = %08x\n", virtual_avail); 1269 debugf("virtual_end = %08x\n", virtual_end); 1270 1271 debugf("mmu_booke_bootstrap: exit\n"); 1272 } 1273 1274 void 1275 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1276 { 1277 int i; 1278 1279 /* 1280 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1281 * have the snapshot of its contents in the s/w tlb1[] table, so use 1282 * these values directly to (re)program AP's TLB1 hardware. 1283 */ 1284 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1285 /* Skip invalid entries */ 1286 if (!(tlb1[i].mas1 & MAS1_VALID)) 1287 continue; 1288 1289 tlb1_write_entry(i); 1290 } 1291 1292 set_mas4_defaults(); 1293 } 1294 1295 /* 1296 * Get the physical page address for the given pmap/virtual address. 1297 */ 1298 static vm_paddr_t 1299 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1300 { 1301 vm_paddr_t pa; 1302 1303 PMAP_LOCK(pmap); 1304 pa = pte_vatopa(mmu, pmap, va); 1305 PMAP_UNLOCK(pmap); 1306 1307 return (pa); 1308 } 1309 1310 /* 1311 * Extract the physical page address associated with the given 1312 * kernel virtual address. 1313 */ 1314 static vm_paddr_t 1315 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1316 { 1317 1318 return (pte_vatopa(mmu, kernel_pmap, va)); 1319 } 1320 1321 /* 1322 * Initialize the pmap module. 1323 * Called by vm_init, to initialize any structures that the pmap 1324 * system needs to map virtual memory. 1325 */ 1326 static void 1327 mmu_booke_init(mmu_t mmu) 1328 { 1329 int shpgperproc = PMAP_SHPGPERPROC; 1330 1331 /* 1332 * Initialize the address space (zone) for the pv entries. Set a 1333 * high water mark so that the system can recover from excessive 1334 * numbers of pv entries. 1335 */ 1336 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1337 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1338 1339 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1340 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1341 1342 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1343 pv_entry_high_water = 9 * (pv_entry_max / 10); 1344 1345 uma_zone_reserve_kva(pvzone, pv_entry_max); 1346 1347 /* Pre-fill pvzone with initial number of pv entries. */ 1348 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1349 1350 /* Initialize ptbl allocation. */ 1351 ptbl_init(); 1352 } 1353 1354 /* 1355 * Map a list of wired pages into kernel virtual address space. This is 1356 * intended for temporary mappings which do not need page modification or 1357 * references recorded. Existing mappings in the region are overwritten. 1358 */ 1359 static void 1360 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1361 { 1362 vm_offset_t va; 1363 1364 va = sva; 1365 while (count-- > 0) { 1366 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1367 va += PAGE_SIZE; 1368 m++; 1369 } 1370 } 1371 1372 /* 1373 * Remove page mappings from kernel virtual address space. Intended for 1374 * temporary mappings entered by mmu_booke_qenter. 1375 */ 1376 static void 1377 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1378 { 1379 vm_offset_t va; 1380 1381 va = sva; 1382 while (count-- > 0) { 1383 mmu_booke_kremove(mmu, va); 1384 va += PAGE_SIZE; 1385 } 1386 } 1387 1388 /* 1389 * Map a wired page into kernel virtual address space. 1390 */ 1391 static void 1392 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1393 { 1394 unsigned int pdir_idx = PDIR_IDX(va); 1395 unsigned int ptbl_idx = PTBL_IDX(va); 1396 uint32_t flags; 1397 pte_t *pte; 1398 1399 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1400 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1401 1402 flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1403 1404 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1405 1406 mtx_lock_spin(&tlbivax_mutex); 1407 tlb_miss_lock(); 1408 1409 if (PTE_ISVALID(pte)) { 1410 1411 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1412 1413 /* Flush entry from TLB0 */ 1414 tlb0_flush_entry(va); 1415 } 1416 1417 pte->rpn = pa & ~PTE_PA_MASK; 1418 pte->flags = flags; 1419 1420 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1421 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1422 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1423 1424 /* Flush the real memory from the instruction cache. */ 1425 if ((flags & (PTE_I | PTE_G)) == 0) { 1426 __syncicache((void *)va, PAGE_SIZE); 1427 } 1428 1429 tlb_miss_unlock(); 1430 mtx_unlock_spin(&tlbivax_mutex); 1431 } 1432 1433 /* 1434 * Remove a page from kernel page table. 1435 */ 1436 static void 1437 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1438 { 1439 unsigned int pdir_idx = PDIR_IDX(va); 1440 unsigned int ptbl_idx = PTBL_IDX(va); 1441 pte_t *pte; 1442 1443 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1444 1445 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1446 (va <= VM_MAX_KERNEL_ADDRESS)), 1447 ("mmu_booke_kremove: invalid va")); 1448 1449 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1450 1451 if (!PTE_ISVALID(pte)) { 1452 1453 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1454 1455 return; 1456 } 1457 1458 mtx_lock_spin(&tlbivax_mutex); 1459 tlb_miss_lock(); 1460 1461 /* Invalidate entry in TLB0, update PTE. */ 1462 tlb0_flush_entry(va); 1463 pte->flags = 0; 1464 pte->rpn = 0; 1465 1466 tlb_miss_unlock(); 1467 mtx_unlock_spin(&tlbivax_mutex); 1468 } 1469 1470 /* 1471 * Initialize pmap associated with process 0. 1472 */ 1473 static void 1474 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1475 { 1476 1477 mmu_booke_pinit(mmu, pmap); 1478 PCPU_SET(curpmap, pmap); 1479 } 1480 1481 /* 1482 * Initialize a preallocated and zeroed pmap structure, 1483 * such as one in a vmspace structure. 1484 */ 1485 static void 1486 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1487 { 1488 int i; 1489 1490 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1491 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1492 1493 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1494 1495 PMAP_LOCK_INIT(pmap); 1496 for (i = 0; i < MAXCPU; i++) 1497 pmap->pm_tid[i] = TID_NONE; 1498 CPU_ZERO(&kernel_pmap->pm_active); 1499 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1500 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1501 TAILQ_INIT(&pmap->pm_ptbl_list); 1502 } 1503 1504 /* 1505 * Release any resources held by the given physical map. 1506 * Called when a pmap initialized by mmu_booke_pinit is being released. 1507 * Should only be called if the map contains no valid mappings. 1508 */ 1509 static void 1510 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1511 { 1512 1513 KASSERT(pmap->pm_stats.resident_count == 0, 1514 ("pmap_release: pmap resident count %ld != 0", 1515 pmap->pm_stats.resident_count)); 1516 1517 PMAP_LOCK_DESTROY(pmap); 1518 } 1519 1520 /* 1521 * Insert the given physical page at the specified virtual address in the 1522 * target physical map with the protection requested. If specified the page 1523 * will be wired down. 1524 */ 1525 static void 1526 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1527 vm_prot_t prot, boolean_t wired) 1528 { 1529 1530 rw_wlock(&pvh_global_lock); 1531 PMAP_LOCK(pmap); 1532 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1533 rw_wunlock(&pvh_global_lock); 1534 PMAP_UNLOCK(pmap); 1535 } 1536 1537 static void 1538 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1539 vm_prot_t prot, boolean_t wired) 1540 { 1541 pte_t *pte; 1542 vm_paddr_t pa; 1543 uint32_t flags; 1544 int su, sync; 1545 1546 pa = VM_PAGE_TO_PHYS(m); 1547 su = (pmap == kernel_pmap); 1548 sync = 0; 1549 1550 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1551 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1552 // (u_int32_t)pmap, su, pmap->pm_tid, 1553 // (u_int32_t)m, va, pa, prot, wired); 1554 1555 if (su) { 1556 KASSERT(((va >= virtual_avail) && 1557 (va <= VM_MAX_KERNEL_ADDRESS)), 1558 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1559 } else { 1560 KASSERT((va <= VM_MAXUSER_ADDRESS), 1561 ("mmu_booke_enter_locked: user pmap, non user va")); 1562 } 1563 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0) 1564 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1565 1566 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1567 1568 /* 1569 * If there is an existing mapping, and the physical address has not 1570 * changed, must be protection or wiring change. 1571 */ 1572 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1573 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1574 1575 /* 1576 * Before actually updating pte->flags we calculate and 1577 * prepare its new value in a helper var. 1578 */ 1579 flags = pte->flags; 1580 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1581 1582 /* Wiring change, just update stats. */ 1583 if (wired) { 1584 if (!PTE_ISWIRED(pte)) { 1585 flags |= PTE_WIRED; 1586 pmap->pm_stats.wired_count++; 1587 } 1588 } else { 1589 if (PTE_ISWIRED(pte)) { 1590 flags &= ~PTE_WIRED; 1591 pmap->pm_stats.wired_count--; 1592 } 1593 } 1594 1595 if (prot & VM_PROT_WRITE) { 1596 /* Add write permissions. */ 1597 flags |= PTE_SW; 1598 if (!su) 1599 flags |= PTE_UW; 1600 1601 if ((flags & PTE_MANAGED) != 0) 1602 vm_page_aflag_set(m, PGA_WRITEABLE); 1603 } else { 1604 /* Handle modified pages, sense modify status. */ 1605 1606 /* 1607 * The PTE_MODIFIED flag could be set by underlying 1608 * TLB misses since we last read it (above), possibly 1609 * other CPUs could update it so we check in the PTE 1610 * directly rather than rely on that saved local flags 1611 * copy. 1612 */ 1613 if (PTE_ISMODIFIED(pte)) 1614 vm_page_dirty(m); 1615 } 1616 1617 if (prot & VM_PROT_EXECUTE) { 1618 flags |= PTE_SX; 1619 if (!su) 1620 flags |= PTE_UX; 1621 1622 /* 1623 * Check existing flags for execute permissions: if we 1624 * are turning execute permissions on, icache should 1625 * be flushed. 1626 */ 1627 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1628 sync++; 1629 } 1630 1631 flags &= ~PTE_REFERENCED; 1632 1633 /* 1634 * The new flags value is all calculated -- only now actually 1635 * update the PTE. 1636 */ 1637 mtx_lock_spin(&tlbivax_mutex); 1638 tlb_miss_lock(); 1639 1640 tlb0_flush_entry(va); 1641 pte->flags = flags; 1642 1643 tlb_miss_unlock(); 1644 mtx_unlock_spin(&tlbivax_mutex); 1645 1646 } else { 1647 /* 1648 * If there is an existing mapping, but it's for a different 1649 * physical address, pte_enter() will delete the old mapping. 1650 */ 1651 //if ((pte != NULL) && PTE_ISVALID(pte)) 1652 // debugf("mmu_booke_enter_locked: replace\n"); 1653 //else 1654 // debugf("mmu_booke_enter_locked: new\n"); 1655 1656 /* Now set up the flags and install the new mapping. */ 1657 flags = (PTE_SR | PTE_VALID); 1658 flags |= PTE_M; 1659 1660 if (!su) 1661 flags |= PTE_UR; 1662 1663 if (prot & VM_PROT_WRITE) { 1664 flags |= PTE_SW; 1665 if (!su) 1666 flags |= PTE_UW; 1667 1668 if ((m->oflags & VPO_UNMANAGED) == 0) 1669 vm_page_aflag_set(m, PGA_WRITEABLE); 1670 } 1671 1672 if (prot & VM_PROT_EXECUTE) { 1673 flags |= PTE_SX; 1674 if (!su) 1675 flags |= PTE_UX; 1676 } 1677 1678 /* If its wired update stats. */ 1679 if (wired) { 1680 pmap->pm_stats.wired_count++; 1681 flags |= PTE_WIRED; 1682 } 1683 1684 pte_enter(mmu, pmap, m, va, flags); 1685 1686 /* Flush the real memory from the instruction cache. */ 1687 if (prot & VM_PROT_EXECUTE) 1688 sync++; 1689 } 1690 1691 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1692 __syncicache((void *)va, PAGE_SIZE); 1693 sync = 0; 1694 } 1695 } 1696 1697 /* 1698 * Maps a sequence of resident pages belonging to the same object. 1699 * The sequence begins with the given page m_start. This page is 1700 * mapped at the given virtual address start. Each subsequent page is 1701 * mapped at a virtual address that is offset from start by the same 1702 * amount as the page is offset from m_start within the object. The 1703 * last page in the sequence is the page with the largest offset from 1704 * m_start that can be mapped at a virtual address less than the given 1705 * virtual address end. Not every virtual page between start and end 1706 * is mapped; only those for which a resident page exists with the 1707 * corresponding offset from m_start are mapped. 1708 */ 1709 static void 1710 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1711 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1712 { 1713 vm_page_t m; 1714 vm_pindex_t diff, psize; 1715 1716 psize = atop(end - start); 1717 m = m_start; 1718 rw_wlock(&pvh_global_lock); 1719 PMAP_LOCK(pmap); 1720 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1721 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1722 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1723 m = TAILQ_NEXT(m, listq); 1724 } 1725 rw_wunlock(&pvh_global_lock); 1726 PMAP_UNLOCK(pmap); 1727 } 1728 1729 static void 1730 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1731 vm_prot_t prot) 1732 { 1733 1734 rw_wlock(&pvh_global_lock); 1735 PMAP_LOCK(pmap); 1736 mmu_booke_enter_locked(mmu, pmap, va, m, 1737 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1738 rw_wunlock(&pvh_global_lock); 1739 PMAP_UNLOCK(pmap); 1740 } 1741 1742 /* 1743 * Remove the given range of addresses from the specified map. 1744 * 1745 * It is assumed that the start and end are properly rounded to the page size. 1746 */ 1747 static void 1748 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1749 { 1750 pte_t *pte; 1751 uint8_t hold_flag; 1752 1753 int su = (pmap == kernel_pmap); 1754 1755 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1756 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1757 1758 if (su) { 1759 KASSERT(((va >= virtual_avail) && 1760 (va <= VM_MAX_KERNEL_ADDRESS)), 1761 ("mmu_booke_remove: kernel pmap, non kernel va")); 1762 } else { 1763 KASSERT((va <= VM_MAXUSER_ADDRESS), 1764 ("mmu_booke_remove: user pmap, non user va")); 1765 } 1766 1767 if (PMAP_REMOVE_DONE(pmap)) { 1768 //debugf("mmu_booke_remove: e (empty)\n"); 1769 return; 1770 } 1771 1772 hold_flag = PTBL_HOLD_FLAG(pmap); 1773 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1774 1775 rw_wlock(&pvh_global_lock); 1776 PMAP_LOCK(pmap); 1777 for (; va < endva; va += PAGE_SIZE) { 1778 pte = pte_find(mmu, pmap, va); 1779 if ((pte != NULL) && PTE_ISVALID(pte)) 1780 pte_remove(mmu, pmap, va, hold_flag); 1781 } 1782 PMAP_UNLOCK(pmap); 1783 rw_wunlock(&pvh_global_lock); 1784 1785 //debugf("mmu_booke_remove: e\n"); 1786 } 1787 1788 /* 1789 * Remove physical page from all pmaps in which it resides. 1790 */ 1791 static void 1792 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1793 { 1794 pv_entry_t pv, pvn; 1795 uint8_t hold_flag; 1796 1797 rw_wlock(&pvh_global_lock); 1798 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1799 pvn = TAILQ_NEXT(pv, pv_link); 1800 1801 PMAP_LOCK(pv->pv_pmap); 1802 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1803 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1804 PMAP_UNLOCK(pv->pv_pmap); 1805 } 1806 vm_page_aflag_clear(m, PGA_WRITEABLE); 1807 rw_wunlock(&pvh_global_lock); 1808 } 1809 1810 /* 1811 * Map a range of physical addresses into kernel virtual address space. 1812 */ 1813 static vm_offset_t 1814 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1815 vm_paddr_t pa_end, int prot) 1816 { 1817 vm_offset_t sva = *virt; 1818 vm_offset_t va = sva; 1819 1820 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1821 // sva, pa_start, pa_end); 1822 1823 while (pa_start < pa_end) { 1824 mmu_booke_kenter(mmu, va, pa_start); 1825 va += PAGE_SIZE; 1826 pa_start += PAGE_SIZE; 1827 } 1828 *virt = va; 1829 1830 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1831 return (sva); 1832 } 1833 1834 /* 1835 * The pmap must be activated before it's address space can be accessed in any 1836 * way. 1837 */ 1838 static void 1839 mmu_booke_activate(mmu_t mmu, struct thread *td) 1840 { 1841 pmap_t pmap; 1842 u_int cpuid; 1843 1844 pmap = &td->td_proc->p_vmspace->vm_pmap; 1845 1846 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1847 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1848 1849 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1850 1851 mtx_lock_spin(&sched_lock); 1852 1853 cpuid = PCPU_GET(cpuid); 1854 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1855 PCPU_SET(curpmap, pmap); 1856 1857 if (pmap->pm_tid[cpuid] == TID_NONE) 1858 tid_alloc(pmap); 1859 1860 /* Load PID0 register with pmap tid value. */ 1861 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1862 __asm __volatile("isync"); 1863 1864 mtx_unlock_spin(&sched_lock); 1865 1866 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1867 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1868 } 1869 1870 /* 1871 * Deactivate the specified process's address space. 1872 */ 1873 static void 1874 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1875 { 1876 pmap_t pmap; 1877 1878 pmap = &td->td_proc->p_vmspace->vm_pmap; 1879 1880 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1881 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1882 1883 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1884 PCPU_SET(curpmap, NULL); 1885 } 1886 1887 /* 1888 * Copy the range specified by src_addr/len 1889 * from the source map to the range dst_addr/len 1890 * in the destination map. 1891 * 1892 * This routine is only advisory and need not do anything. 1893 */ 1894 static void 1895 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1896 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1897 { 1898 1899 } 1900 1901 /* 1902 * Set the physical protection on the specified range of this map as requested. 1903 */ 1904 static void 1905 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1906 vm_prot_t prot) 1907 { 1908 vm_offset_t va; 1909 vm_page_t m; 1910 pte_t *pte; 1911 1912 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1913 mmu_booke_remove(mmu, pmap, sva, eva); 1914 return; 1915 } 1916 1917 if (prot & VM_PROT_WRITE) 1918 return; 1919 1920 PMAP_LOCK(pmap); 1921 for (va = sva; va < eva; va += PAGE_SIZE) { 1922 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1923 if (PTE_ISVALID(pte)) { 1924 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1925 1926 mtx_lock_spin(&tlbivax_mutex); 1927 tlb_miss_lock(); 1928 1929 /* Handle modified pages. */ 1930 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1931 vm_page_dirty(m); 1932 1933 tlb0_flush_entry(va); 1934 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1935 1936 tlb_miss_unlock(); 1937 mtx_unlock_spin(&tlbivax_mutex); 1938 } 1939 } 1940 } 1941 PMAP_UNLOCK(pmap); 1942 } 1943 1944 /* 1945 * Clear the write and modified bits in each of the given page's mappings. 1946 */ 1947 static void 1948 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1949 { 1950 pv_entry_t pv; 1951 pte_t *pte; 1952 1953 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1954 ("mmu_booke_remove_write: page %p is not managed", m)); 1955 1956 /* 1957 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1958 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1959 * is clear, no page table entries need updating. 1960 */ 1961 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1962 if ((m->oflags & VPO_BUSY) == 0 && 1963 (m->aflags & PGA_WRITEABLE) == 0) 1964 return; 1965 rw_wlock(&pvh_global_lock); 1966 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1967 PMAP_LOCK(pv->pv_pmap); 1968 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1969 if (PTE_ISVALID(pte)) { 1970 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1971 1972 mtx_lock_spin(&tlbivax_mutex); 1973 tlb_miss_lock(); 1974 1975 /* Handle modified pages. */ 1976 if (PTE_ISMODIFIED(pte)) 1977 vm_page_dirty(m); 1978 1979 /* Flush mapping from TLB0. */ 1980 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1981 1982 tlb_miss_unlock(); 1983 mtx_unlock_spin(&tlbivax_mutex); 1984 } 1985 } 1986 PMAP_UNLOCK(pv->pv_pmap); 1987 } 1988 vm_page_aflag_clear(m, PGA_WRITEABLE); 1989 rw_wunlock(&pvh_global_lock); 1990 } 1991 1992 static void 1993 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1994 { 1995 pte_t *pte; 1996 pmap_t pmap; 1997 vm_page_t m; 1998 vm_offset_t addr; 1999 vm_paddr_t pa; 2000 int active, valid; 2001 2002 va = trunc_page(va); 2003 sz = round_page(sz); 2004 2005 rw_wlock(&pvh_global_lock); 2006 pmap = PCPU_GET(curpmap); 2007 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2008 while (sz > 0) { 2009 PMAP_LOCK(pm); 2010 pte = pte_find(mmu, pm, va); 2011 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2012 if (valid) 2013 pa = PTE_PA(pte); 2014 PMAP_UNLOCK(pm); 2015 if (valid) { 2016 if (!active) { 2017 /* Create a mapping in the active pmap. */ 2018 addr = 0; 2019 m = PHYS_TO_VM_PAGE(pa); 2020 PMAP_LOCK(pmap); 2021 pte_enter(mmu, pmap, m, addr, 2022 PTE_SR | PTE_VALID | PTE_UR); 2023 __syncicache((void *)addr, PAGE_SIZE); 2024 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2025 PMAP_UNLOCK(pmap); 2026 } else 2027 __syncicache((void *)va, PAGE_SIZE); 2028 } 2029 va += PAGE_SIZE; 2030 sz -= PAGE_SIZE; 2031 } 2032 rw_wunlock(&pvh_global_lock); 2033 } 2034 2035 /* 2036 * Atomically extract and hold the physical page with the given 2037 * pmap and virtual address pair if that mapping permits the given 2038 * protection. 2039 */ 2040 static vm_page_t 2041 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2042 vm_prot_t prot) 2043 { 2044 pte_t *pte; 2045 vm_page_t m; 2046 uint32_t pte_wbit; 2047 vm_paddr_t pa; 2048 2049 m = NULL; 2050 pa = 0; 2051 PMAP_LOCK(pmap); 2052 retry: 2053 pte = pte_find(mmu, pmap, va); 2054 if ((pte != NULL) && PTE_ISVALID(pte)) { 2055 if (pmap == kernel_pmap) 2056 pte_wbit = PTE_SW; 2057 else 2058 pte_wbit = PTE_UW; 2059 2060 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2061 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2062 goto retry; 2063 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2064 vm_page_hold(m); 2065 } 2066 } 2067 2068 PA_UNLOCK_COND(pa); 2069 PMAP_UNLOCK(pmap); 2070 return (m); 2071 } 2072 2073 /* 2074 * Initialize a vm_page's machine-dependent fields. 2075 */ 2076 static void 2077 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2078 { 2079 2080 TAILQ_INIT(&m->md.pv_list); 2081 } 2082 2083 /* 2084 * mmu_booke_zero_page_area zeros the specified hardware page by 2085 * mapping it into virtual memory and using bzero to clear 2086 * its contents. 2087 * 2088 * off and size must reside within a single page. 2089 */ 2090 static void 2091 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2092 { 2093 vm_offset_t va; 2094 2095 /* XXX KASSERT off and size are within a single page? */ 2096 2097 mtx_lock(&zero_page_mutex); 2098 va = zero_page_va; 2099 2100 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2101 bzero((caddr_t)va + off, size); 2102 mmu_booke_kremove(mmu, va); 2103 2104 mtx_unlock(&zero_page_mutex); 2105 } 2106 2107 /* 2108 * mmu_booke_zero_page zeros the specified hardware page. 2109 */ 2110 static void 2111 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2112 { 2113 2114 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2115 } 2116 2117 /* 2118 * mmu_booke_copy_page copies the specified (machine independent) page by 2119 * mapping the page into virtual memory and using memcopy to copy the page, 2120 * one machine dependent page at a time. 2121 */ 2122 static void 2123 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2124 { 2125 vm_offset_t sva, dva; 2126 2127 sva = copy_page_src_va; 2128 dva = copy_page_dst_va; 2129 2130 mtx_lock(©_page_mutex); 2131 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2132 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2133 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2134 mmu_booke_kremove(mmu, dva); 2135 mmu_booke_kremove(mmu, sva); 2136 mtx_unlock(©_page_mutex); 2137 } 2138 2139 /* 2140 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2141 * into virtual memory and using bzero to clear its contents. This is intended 2142 * to be called from the vm_pagezero process only and outside of Giant. No 2143 * lock is required. 2144 */ 2145 static void 2146 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2147 { 2148 vm_offset_t va; 2149 2150 va = zero_page_idle_va; 2151 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2152 bzero((caddr_t)va, PAGE_SIZE); 2153 mmu_booke_kremove(mmu, va); 2154 } 2155 2156 /* 2157 * Return whether or not the specified physical page was modified 2158 * in any of physical maps. 2159 */ 2160 static boolean_t 2161 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2162 { 2163 pte_t *pte; 2164 pv_entry_t pv; 2165 boolean_t rv; 2166 2167 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2168 ("mmu_booke_is_modified: page %p is not managed", m)); 2169 rv = FALSE; 2170 2171 /* 2172 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 2173 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2174 * is clear, no PTEs can be modified. 2175 */ 2176 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2177 if ((m->oflags & VPO_BUSY) == 0 && 2178 (m->aflags & PGA_WRITEABLE) == 0) 2179 return (rv); 2180 rw_wlock(&pvh_global_lock); 2181 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2182 PMAP_LOCK(pv->pv_pmap); 2183 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2184 PTE_ISVALID(pte)) { 2185 if (PTE_ISMODIFIED(pte)) 2186 rv = TRUE; 2187 } 2188 PMAP_UNLOCK(pv->pv_pmap); 2189 if (rv) 2190 break; 2191 } 2192 rw_wunlock(&pvh_global_lock); 2193 return (rv); 2194 } 2195 2196 /* 2197 * Return whether or not the specified virtual address is eligible 2198 * for prefault. 2199 */ 2200 static boolean_t 2201 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2202 { 2203 2204 return (FALSE); 2205 } 2206 2207 /* 2208 * Return whether or not the specified physical page was referenced 2209 * in any physical maps. 2210 */ 2211 static boolean_t 2212 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2213 { 2214 pte_t *pte; 2215 pv_entry_t pv; 2216 boolean_t rv; 2217 2218 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2219 ("mmu_booke_is_referenced: page %p is not managed", m)); 2220 rv = FALSE; 2221 rw_wlock(&pvh_global_lock); 2222 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2223 PMAP_LOCK(pv->pv_pmap); 2224 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2225 PTE_ISVALID(pte)) { 2226 if (PTE_ISREFERENCED(pte)) 2227 rv = TRUE; 2228 } 2229 PMAP_UNLOCK(pv->pv_pmap); 2230 if (rv) 2231 break; 2232 } 2233 rw_wunlock(&pvh_global_lock); 2234 return (rv); 2235 } 2236 2237 /* 2238 * Clear the modify bits on the specified physical page. 2239 */ 2240 static void 2241 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2242 { 2243 pte_t *pte; 2244 pv_entry_t pv; 2245 2246 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2247 ("mmu_booke_clear_modify: page %p is not managed", m)); 2248 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2249 KASSERT((m->oflags & VPO_BUSY) == 0, 2250 ("mmu_booke_clear_modify: page %p is busy", m)); 2251 2252 /* 2253 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2254 * If the object containing the page is locked and the page is not 2255 * VPO_BUSY, then PG_AWRITEABLE cannot be concurrently set. 2256 */ 2257 if ((m->aflags & PGA_WRITEABLE) == 0) 2258 return; 2259 rw_wlock(&pvh_global_lock); 2260 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2261 PMAP_LOCK(pv->pv_pmap); 2262 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2263 PTE_ISVALID(pte)) { 2264 mtx_lock_spin(&tlbivax_mutex); 2265 tlb_miss_lock(); 2266 2267 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2268 tlb0_flush_entry(pv->pv_va); 2269 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2270 PTE_REFERENCED); 2271 } 2272 2273 tlb_miss_unlock(); 2274 mtx_unlock_spin(&tlbivax_mutex); 2275 } 2276 PMAP_UNLOCK(pv->pv_pmap); 2277 } 2278 rw_wunlock(&pvh_global_lock); 2279 } 2280 2281 /* 2282 * Return a count of reference bits for a page, clearing those bits. 2283 * It is not necessary for every reference bit to be cleared, but it 2284 * is necessary that 0 only be returned when there are truly no 2285 * reference bits set. 2286 * 2287 * XXX: The exact number of bits to check and clear is a matter that 2288 * should be tested and standardized at some point in the future for 2289 * optimal aging of shared pages. 2290 */ 2291 static int 2292 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2293 { 2294 pte_t *pte; 2295 pv_entry_t pv; 2296 int count; 2297 2298 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2299 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2300 count = 0; 2301 rw_wlock(&pvh_global_lock); 2302 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2303 PMAP_LOCK(pv->pv_pmap); 2304 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2305 PTE_ISVALID(pte)) { 2306 if (PTE_ISREFERENCED(pte)) { 2307 mtx_lock_spin(&tlbivax_mutex); 2308 tlb_miss_lock(); 2309 2310 tlb0_flush_entry(pv->pv_va); 2311 pte->flags &= ~PTE_REFERENCED; 2312 2313 tlb_miss_unlock(); 2314 mtx_unlock_spin(&tlbivax_mutex); 2315 2316 if (++count > 4) { 2317 PMAP_UNLOCK(pv->pv_pmap); 2318 break; 2319 } 2320 } 2321 } 2322 PMAP_UNLOCK(pv->pv_pmap); 2323 } 2324 rw_wunlock(&pvh_global_lock); 2325 return (count); 2326 } 2327 2328 /* 2329 * Clear the reference bit on the specified physical page. 2330 */ 2331 static void 2332 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2333 { 2334 pte_t *pte; 2335 pv_entry_t pv; 2336 2337 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2338 ("mmu_booke_clear_reference: page %p is not managed", m)); 2339 rw_wlock(&pvh_global_lock); 2340 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2341 PMAP_LOCK(pv->pv_pmap); 2342 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2343 PTE_ISVALID(pte)) { 2344 if (PTE_ISREFERENCED(pte)) { 2345 mtx_lock_spin(&tlbivax_mutex); 2346 tlb_miss_lock(); 2347 2348 tlb0_flush_entry(pv->pv_va); 2349 pte->flags &= ~PTE_REFERENCED; 2350 2351 tlb_miss_unlock(); 2352 mtx_unlock_spin(&tlbivax_mutex); 2353 } 2354 } 2355 PMAP_UNLOCK(pv->pv_pmap); 2356 } 2357 rw_wunlock(&pvh_global_lock); 2358 } 2359 2360 /* 2361 * Change wiring attribute for a map/virtual-address pair. 2362 */ 2363 static void 2364 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2365 { 2366 pte_t *pte; 2367 2368 PMAP_LOCK(pmap); 2369 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2370 if (wired) { 2371 if (!PTE_ISWIRED(pte)) { 2372 pte->flags |= PTE_WIRED; 2373 pmap->pm_stats.wired_count++; 2374 } 2375 } else { 2376 if (PTE_ISWIRED(pte)) { 2377 pte->flags &= ~PTE_WIRED; 2378 pmap->pm_stats.wired_count--; 2379 } 2380 } 2381 } 2382 PMAP_UNLOCK(pmap); 2383 } 2384 2385 /* 2386 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2387 * page. This count may be changed upwards or downwards in the future; it is 2388 * only necessary that true be returned for a small subset of pmaps for proper 2389 * page aging. 2390 */ 2391 static boolean_t 2392 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2393 { 2394 pv_entry_t pv; 2395 int loops; 2396 boolean_t rv; 2397 2398 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2399 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2400 loops = 0; 2401 rv = FALSE; 2402 rw_wlock(&pvh_global_lock); 2403 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2404 if (pv->pv_pmap == pmap) { 2405 rv = TRUE; 2406 break; 2407 } 2408 if (++loops >= 16) 2409 break; 2410 } 2411 rw_wunlock(&pvh_global_lock); 2412 return (rv); 2413 } 2414 2415 /* 2416 * Return the number of managed mappings to the given physical page that are 2417 * wired. 2418 */ 2419 static int 2420 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2421 { 2422 pv_entry_t pv; 2423 pte_t *pte; 2424 int count = 0; 2425 2426 if ((m->oflags & VPO_UNMANAGED) != 0) 2427 return (count); 2428 rw_wlock(&pvh_global_lock); 2429 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2430 PMAP_LOCK(pv->pv_pmap); 2431 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2432 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2433 count++; 2434 PMAP_UNLOCK(pv->pv_pmap); 2435 } 2436 rw_wunlock(&pvh_global_lock); 2437 return (count); 2438 } 2439 2440 static int 2441 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2442 { 2443 int i; 2444 vm_offset_t va; 2445 2446 /* 2447 * This currently does not work for entries that 2448 * overlap TLB1 entries. 2449 */ 2450 for (i = 0; i < tlb1_idx; i ++) { 2451 if (tlb1_iomapped(i, pa, size, &va) == 0) 2452 return (0); 2453 } 2454 2455 return (EFAULT); 2456 } 2457 2458 vm_offset_t 2459 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2460 vm_size_t *sz) 2461 { 2462 vm_paddr_t pa, ppa; 2463 vm_offset_t va; 2464 vm_size_t gran; 2465 2466 /* Raw physical memory dumps don't have a virtual address. */ 2467 if (md->md_vaddr == ~0UL) { 2468 /* We always map a 256MB page at 256M. */ 2469 gran = 256 * 1024 * 1024; 2470 pa = md->md_paddr + ofs; 2471 ppa = pa & ~(gran - 1); 2472 ofs = pa - ppa; 2473 va = gran; 2474 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2475 if (*sz > (gran - ofs)) 2476 *sz = gran - ofs; 2477 return (va + ofs); 2478 } 2479 2480 /* Minidumps are based on virtual memory addresses. */ 2481 va = md->md_vaddr + ofs; 2482 if (va >= kernstart + kernsize) { 2483 gran = PAGE_SIZE - (va & PAGE_MASK); 2484 if (*sz > gran) 2485 *sz = gran; 2486 } 2487 return (va); 2488 } 2489 2490 void 2491 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2492 vm_offset_t va) 2493 { 2494 2495 /* Raw physical memory dumps don't have a virtual address. */ 2496 if (md->md_vaddr == ~0UL) { 2497 tlb1_idx--; 2498 tlb1[tlb1_idx].mas1 = 0; 2499 tlb1[tlb1_idx].mas2 = 0; 2500 tlb1[tlb1_idx].mas3 = 0; 2501 tlb1_write_entry(tlb1_idx); 2502 return; 2503 } 2504 2505 /* Minidumps are based on virtual memory addresses. */ 2506 /* Nothing to do... */ 2507 } 2508 2509 struct pmap_md * 2510 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2511 { 2512 static struct pmap_md md; 2513 pte_t *pte; 2514 vm_offset_t va; 2515 2516 if (dumpsys_minidump) { 2517 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2518 if (prev == NULL) { 2519 /* 1st: kernel .data and .bss. */ 2520 md.md_index = 1; 2521 md.md_vaddr = trunc_page((uintptr_t)_etext); 2522 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2523 return (&md); 2524 } 2525 switch (prev->md_index) { 2526 case 1: 2527 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2528 md.md_index = 2; 2529 md.md_vaddr = data_start; 2530 md.md_size = data_end - data_start; 2531 break; 2532 case 2: 2533 /* 3rd: kernel VM. */ 2534 va = prev->md_vaddr + prev->md_size; 2535 /* Find start of next chunk (from va). */ 2536 while (va < virtual_end) { 2537 /* Don't dump the buffer cache. */ 2538 if (va >= kmi.buffer_sva && 2539 va < kmi.buffer_eva) { 2540 va = kmi.buffer_eva; 2541 continue; 2542 } 2543 pte = pte_find(mmu, kernel_pmap, va); 2544 if (pte != NULL && PTE_ISVALID(pte)) 2545 break; 2546 va += PAGE_SIZE; 2547 } 2548 if (va < virtual_end) { 2549 md.md_vaddr = va; 2550 va += PAGE_SIZE; 2551 /* Find last page in chunk. */ 2552 while (va < virtual_end) { 2553 /* Don't run into the buffer cache. */ 2554 if (va == kmi.buffer_sva) 2555 break; 2556 pte = pte_find(mmu, kernel_pmap, va); 2557 if (pte == NULL || !PTE_ISVALID(pte)) 2558 break; 2559 va += PAGE_SIZE; 2560 } 2561 md.md_size = va - md.md_vaddr; 2562 break; 2563 } 2564 md.md_index = 3; 2565 /* FALLTHROUGH */ 2566 default: 2567 return (NULL); 2568 } 2569 } else { /* minidumps */ 2570 mem_regions(&physmem_regions, &physmem_regions_sz, 2571 &availmem_regions, &availmem_regions_sz); 2572 2573 if (prev == NULL) { 2574 /* first physical chunk. */ 2575 md.md_paddr = physmem_regions[0].mr_start; 2576 md.md_size = physmem_regions[0].mr_size; 2577 md.md_vaddr = ~0UL; 2578 md.md_index = 1; 2579 } else if (md.md_index < physmem_regions_sz) { 2580 md.md_paddr = physmem_regions[md.md_index].mr_start; 2581 md.md_size = physmem_regions[md.md_index].mr_size; 2582 md.md_vaddr = ~0UL; 2583 md.md_index++; 2584 } else { 2585 /* There's no next physical chunk. */ 2586 return (NULL); 2587 } 2588 } 2589 2590 return (&md); 2591 } 2592 2593 /* 2594 * Map a set of physical memory pages into the kernel virtual address space. 2595 * Return a pointer to where it is mapped. This routine is intended to be used 2596 * for mapping device memory, NOT real memory. 2597 */ 2598 static void * 2599 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2600 { 2601 void *res; 2602 uintptr_t va; 2603 vm_size_t sz; 2604 2605 /* 2606 * CCSR is premapped. Note that (pa + size - 1) is there to make sure 2607 * we don't wrap around. Devices on the local bus typically extend all 2608 * the way up to and including 0xffffffff. In that case (pa + size) 2609 * would be 0. This creates a false positive (i.e. we think it's 2610 * within the CCSR) and not create a mapping. 2611 */ 2612 if (pa >= ccsrbar_pa && (pa + size - 1) < (ccsrbar_pa + CCSRBAR_SIZE)) { 2613 va = CCSRBAR_VA + (pa - ccsrbar_pa); 2614 return ((void *)va); 2615 } 2616 2617 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2618 res = (void *)va; 2619 2620 do { 2621 sz = 1 << (ilog2(size) & ~1); 2622 if (bootverbose) 2623 printf("Wiring VA=%x to PA=%x (size=%x), " 2624 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2625 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2626 size -= sz; 2627 pa += sz; 2628 va += sz; 2629 } while (size > 0); 2630 2631 return (res); 2632 } 2633 2634 /* 2635 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2636 */ 2637 static void 2638 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2639 { 2640 vm_offset_t base, offset; 2641 2642 /* 2643 * Unmap only if this is inside kernel virtual space. 2644 */ 2645 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2646 base = trunc_page(va); 2647 offset = va & PAGE_MASK; 2648 size = roundup(offset + size, PAGE_SIZE); 2649 kmem_free(kernel_map, base, size); 2650 } 2651 } 2652 2653 /* 2654 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2655 * specified pmap. This eliminates the blast of soft faults on process startup 2656 * and immediately after an mmap. 2657 */ 2658 static void 2659 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2660 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2661 { 2662 2663 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2664 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2665 ("mmu_booke_object_init_pt: non-device object")); 2666 } 2667 2668 /* 2669 * Perform the pmap work for mincore. 2670 */ 2671 static int 2672 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2673 vm_paddr_t *locked_pa) 2674 { 2675 2676 TODO; 2677 return (0); 2678 } 2679 2680 /**************************************************************************/ 2681 /* TID handling */ 2682 /**************************************************************************/ 2683 2684 /* 2685 * Allocate a TID. If necessary, steal one from someone else. 2686 * The new TID is flushed from the TLB before returning. 2687 */ 2688 static tlbtid_t 2689 tid_alloc(pmap_t pmap) 2690 { 2691 tlbtid_t tid; 2692 int thiscpu; 2693 2694 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2695 2696 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2697 2698 thiscpu = PCPU_GET(cpuid); 2699 2700 tid = PCPU_GET(tid_next); 2701 if (tid > TID_MAX) 2702 tid = TID_MIN; 2703 PCPU_SET(tid_next, tid + 1); 2704 2705 /* If we are stealing TID then clear the relevant pmap's field */ 2706 if (tidbusy[thiscpu][tid] != NULL) { 2707 2708 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2709 2710 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2711 2712 /* Flush all entries from TLB0 matching this TID. */ 2713 tid_flush(tid); 2714 } 2715 2716 tidbusy[thiscpu][tid] = pmap; 2717 pmap->pm_tid[thiscpu] = tid; 2718 __asm __volatile("msync; isync"); 2719 2720 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2721 PCPU_GET(tid_next)); 2722 2723 return (tid); 2724 } 2725 2726 /**************************************************************************/ 2727 /* TLB0 handling */ 2728 /**************************************************************************/ 2729 2730 static void 2731 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2732 uint32_t mas7) 2733 { 2734 int as; 2735 char desc[3]; 2736 tlbtid_t tid; 2737 vm_size_t size; 2738 unsigned int tsize; 2739 2740 desc[2] = '\0'; 2741 if (mas1 & MAS1_VALID) 2742 desc[0] = 'V'; 2743 else 2744 desc[0] = ' '; 2745 2746 if (mas1 & MAS1_IPROT) 2747 desc[1] = 'P'; 2748 else 2749 desc[1] = ' '; 2750 2751 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2752 tid = MAS1_GETTID(mas1); 2753 2754 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2755 size = 0; 2756 if (tsize) 2757 size = tsize2size(tsize); 2758 2759 debugf("%3d: (%s) [AS=%d] " 2760 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2761 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2762 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2763 } 2764 2765 /* Convert TLB0 va and way number to tlb0[] table index. */ 2766 static inline unsigned int 2767 tlb0_tableidx(vm_offset_t va, unsigned int way) 2768 { 2769 unsigned int idx; 2770 2771 idx = (way * TLB0_ENTRIES_PER_WAY); 2772 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2773 return (idx); 2774 } 2775 2776 /* 2777 * Invalidate TLB0 entry. 2778 */ 2779 static inline void 2780 tlb0_flush_entry(vm_offset_t va) 2781 { 2782 2783 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2784 2785 mtx_assert(&tlbivax_mutex, MA_OWNED); 2786 2787 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2788 __asm __volatile("isync; msync"); 2789 __asm __volatile("tlbsync; msync"); 2790 2791 CTR1(KTR_PMAP, "%s: e", __func__); 2792 } 2793 2794 /* Print out contents of the MAS registers for each TLB0 entry */ 2795 void 2796 tlb0_print_tlbentries(void) 2797 { 2798 uint32_t mas0, mas1, mas2, mas3, mas7; 2799 int entryidx, way, idx; 2800 2801 debugf("TLB0 entries:\n"); 2802 for (way = 0; way < TLB0_WAYS; way ++) 2803 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2804 2805 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2806 mtspr(SPR_MAS0, mas0); 2807 __asm __volatile("isync"); 2808 2809 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2810 mtspr(SPR_MAS2, mas2); 2811 2812 __asm __volatile("isync; tlbre"); 2813 2814 mas1 = mfspr(SPR_MAS1); 2815 mas2 = mfspr(SPR_MAS2); 2816 mas3 = mfspr(SPR_MAS3); 2817 mas7 = mfspr(SPR_MAS7); 2818 2819 idx = tlb0_tableidx(mas2, way); 2820 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2821 } 2822 } 2823 2824 /**************************************************************************/ 2825 /* TLB1 handling */ 2826 /**************************************************************************/ 2827 2828 /* 2829 * TLB1 mapping notes: 2830 * 2831 * TLB1[0] CCSRBAR 2832 * TLB1[1] Kernel text and data. 2833 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2834 * windows, other devices mappings. 2835 */ 2836 2837 /* 2838 * Write given entry to TLB1 hardware. 2839 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2840 */ 2841 static void 2842 tlb1_write_entry(unsigned int idx) 2843 { 2844 uint32_t mas0, mas7; 2845 2846 //debugf("tlb1_write_entry: s\n"); 2847 2848 /* Clear high order RPN bits */ 2849 mas7 = 0; 2850 2851 /* Select entry */ 2852 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2853 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2854 2855 mtspr(SPR_MAS0, mas0); 2856 __asm __volatile("isync"); 2857 mtspr(SPR_MAS1, tlb1[idx].mas1); 2858 __asm __volatile("isync"); 2859 mtspr(SPR_MAS2, tlb1[idx].mas2); 2860 __asm __volatile("isync"); 2861 mtspr(SPR_MAS3, tlb1[idx].mas3); 2862 __asm __volatile("isync"); 2863 mtspr(SPR_MAS7, mas7); 2864 __asm __volatile("isync; tlbwe; isync; msync"); 2865 2866 //debugf("tlb1_write_entry: e\n"); 2867 } 2868 2869 /* 2870 * Return the largest uint value log such that 2^log <= num. 2871 */ 2872 static unsigned int 2873 ilog2(unsigned int num) 2874 { 2875 int lz; 2876 2877 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2878 return (31 - lz); 2879 } 2880 2881 /* 2882 * Convert TLB TSIZE value to mapped region size. 2883 */ 2884 static vm_size_t 2885 tsize2size(unsigned int tsize) 2886 { 2887 2888 /* 2889 * size = 4^tsize KB 2890 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2891 */ 2892 2893 return ((1 << (2 * tsize)) * 1024); 2894 } 2895 2896 /* 2897 * Convert region size (must be power of 4) to TLB TSIZE value. 2898 */ 2899 static unsigned int 2900 size2tsize(vm_size_t size) 2901 { 2902 2903 return (ilog2(size) / 2 - 5); 2904 } 2905 2906 /* 2907 * Register permanent kernel mapping in TLB1. 2908 * 2909 * Entries are created starting from index 0 (current free entry is 2910 * kept in tlb1_idx) and are not supposed to be invalidated. 2911 */ 2912 static int 2913 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2914 uint32_t flags) 2915 { 2916 uint32_t ts, tid; 2917 int tsize; 2918 2919 if (tlb1_idx >= TLB1_ENTRIES) { 2920 printf("tlb1_set_entry: TLB1 full!\n"); 2921 return (-1); 2922 } 2923 2924 /* Convert size to TSIZE */ 2925 tsize = size2tsize(size); 2926 2927 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2928 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2929 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2930 2931 /* XXX LOCK tlb1[] */ 2932 2933 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2934 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2935 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2936 2937 /* Set supervisor RWX permission bits */ 2938 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2939 2940 tlb1_write_entry(tlb1_idx++); 2941 2942 /* XXX UNLOCK tlb1[] */ 2943 2944 /* 2945 * XXX in general TLB1 updates should be propagated between CPUs, 2946 * since current design assumes to have the same TLB1 set-up on all 2947 * cores. 2948 */ 2949 return (0); 2950 } 2951 2952 /* 2953 * Map in contiguous RAM region into the TLB1 using maximum of 2954 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2955 * 2956 * If necessary round up last entry size and return total size 2957 * used by all allocated entries. 2958 */ 2959 vm_size_t 2960 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 2961 { 2962 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 2963 vm_size_t mapped, pgsz, base, mask; 2964 int idx, nents; 2965 2966 /* Round up to the next 1M */ 2967 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 2968 2969 mapped = 0; 2970 idx = 0; 2971 base = va; 2972 pgsz = 64*1024*1024; 2973 while (mapped < size) { 2974 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 2975 while (pgsz > (size - mapped)) 2976 pgsz >>= 2; 2977 pgs[idx++] = pgsz; 2978 mapped += pgsz; 2979 } 2980 2981 /* We under-map. Correct for this. */ 2982 if (mapped < size) { 2983 while (pgs[idx - 1] == pgsz) { 2984 idx--; 2985 mapped -= pgsz; 2986 } 2987 /* XXX We may increase beyond out starting point. */ 2988 pgsz <<= 2; 2989 pgs[idx++] = pgsz; 2990 mapped += pgsz; 2991 } 2992 } 2993 2994 nents = idx; 2995 mask = pgs[0] - 1; 2996 /* Align address to the boundary */ 2997 if (va & mask) { 2998 va = (va + mask) & ~mask; 2999 pa = (pa + mask) & ~mask; 3000 } 3001 3002 for (idx = 0; idx < nents; idx++) { 3003 pgsz = pgs[idx]; 3004 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3005 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3006 pa += pgsz; 3007 va += pgsz; 3008 } 3009 3010 mapped = (va - base); 3011 debugf("mapped size 0x%08x (wasted space 0x%08x)\n", 3012 mapped, mapped - size); 3013 return (mapped); 3014 } 3015 3016 /* 3017 * TLB1 initialization routine, to be called after the very first 3018 * assembler level setup done in locore.S. 3019 */ 3020 void 3021 tlb1_init(vm_offset_t ccsrbar) 3022 { 3023 uint32_t mas0, mas1, mas3; 3024 uint32_t tsz; 3025 u_int i; 3026 3027 ccsrbar_pa = ccsrbar; 3028 3029 if (bootinfo != NULL && bootinfo[0] != 1) { 3030 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3031 } else 3032 tlb1_idx = 1; 3033 3034 /* The first entry/entries are used to map the kernel. */ 3035 for (i = 0; i < tlb1_idx; i++) { 3036 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3037 mtspr(SPR_MAS0, mas0); 3038 __asm __volatile("isync; tlbre"); 3039 3040 mas1 = mfspr(SPR_MAS1); 3041 if ((mas1 & MAS1_VALID) == 0) 3042 continue; 3043 3044 mas3 = mfspr(SPR_MAS3); 3045 3046 tlb1[i].mas1 = mas1; 3047 tlb1[i].mas2 = mfspr(SPR_MAS2); 3048 tlb1[i].mas3 = mas3; 3049 3050 if (i == 0) 3051 kernload = mas3 & MAS3_RPN; 3052 3053 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3054 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3055 } 3056 3057 /* Map in CCSRBAR. */ 3058 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3059 3060 #ifdef SMP 3061 bp_ntlb1s = tlb1_idx; 3062 #endif 3063 3064 /* Purge the remaining entries */ 3065 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3066 tlb1_write_entry(i); 3067 3068 /* Setup TLB miss defaults */ 3069 set_mas4_defaults(); 3070 } 3071 3072 /* 3073 * Setup MAS4 defaults. 3074 * These values are loaded to MAS0-2 on a TLB miss. 3075 */ 3076 static void 3077 set_mas4_defaults(void) 3078 { 3079 uint32_t mas4; 3080 3081 /* Defaults: TLB0, PID0, TSIZED=4K */ 3082 mas4 = MAS4_TLBSELD0; 3083 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3084 #ifdef SMP 3085 mas4 |= MAS4_MD; 3086 #endif 3087 mtspr(SPR_MAS4, mas4); 3088 __asm __volatile("isync"); 3089 } 3090 3091 /* 3092 * Print out contents of the MAS registers for each TLB1 entry 3093 */ 3094 void 3095 tlb1_print_tlbentries(void) 3096 { 3097 uint32_t mas0, mas1, mas2, mas3, mas7; 3098 int i; 3099 3100 debugf("TLB1 entries:\n"); 3101 for (i = 0; i < TLB1_ENTRIES; i++) { 3102 3103 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3104 mtspr(SPR_MAS0, mas0); 3105 3106 __asm __volatile("isync; tlbre"); 3107 3108 mas1 = mfspr(SPR_MAS1); 3109 mas2 = mfspr(SPR_MAS2); 3110 mas3 = mfspr(SPR_MAS3); 3111 mas7 = mfspr(SPR_MAS7); 3112 3113 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3114 } 3115 } 3116 3117 /* 3118 * Print out contents of the in-ram tlb1 table. 3119 */ 3120 void 3121 tlb1_print_entries(void) 3122 { 3123 int i; 3124 3125 debugf("tlb1[] table entries:\n"); 3126 for (i = 0; i < TLB1_ENTRIES; i++) 3127 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3128 } 3129 3130 /* 3131 * Return 0 if the physical IO range is encompassed by one of the 3132 * the TLB1 entries, otherwise return related error code. 3133 */ 3134 static int 3135 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3136 { 3137 uint32_t prot; 3138 vm_paddr_t pa_start; 3139 vm_paddr_t pa_end; 3140 unsigned int entry_tsize; 3141 vm_size_t entry_size; 3142 3143 *va = (vm_offset_t)NULL; 3144 3145 /* Skip invalid entries */ 3146 if (!(tlb1[i].mas1 & MAS1_VALID)) 3147 return (EINVAL); 3148 3149 /* 3150 * The entry must be cache-inhibited, guarded, and r/w 3151 * so it can function as an i/o page 3152 */ 3153 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3154 if (prot != (MAS2_I | MAS2_G)) 3155 return (EPERM); 3156 3157 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3158 if (prot != (MAS3_SR | MAS3_SW)) 3159 return (EPERM); 3160 3161 /* The address should be within the entry range. */ 3162 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3163 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3164 3165 entry_size = tsize2size(entry_tsize); 3166 pa_start = tlb1[i].mas3 & MAS3_RPN; 3167 pa_end = pa_start + entry_size - 1; 3168 3169 if ((pa < pa_start) || ((pa + size) > pa_end)) 3170 return (ERANGE); 3171 3172 /* Return virtual address of this mapping. */ 3173 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3174 return (0); 3175 } 3176