1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #define SPARSE_MAPDEV 100 #ifdef DEBUG 101 #define debugf(fmt, args...) printf(fmt, ##args) 102 #else 103 #define debugf(fmt, args...) 104 #endif 105 106 #define TODO panic("%s: not implemented", __func__); 107 108 extern unsigned char _etext[]; 109 extern unsigned char _end[]; 110 111 extern uint32_t *bootinfo; 112 113 #ifdef SMP 114 extern uint32_t bp_ntlb1s; 115 #endif 116 117 vm_paddr_t kernload; 118 vm_offset_t kernstart; 119 vm_size_t kernsize; 120 121 /* Message buffer and tables. */ 122 static vm_offset_t data_start; 123 static vm_size_t data_end; 124 125 /* Phys/avail memory regions. */ 126 static struct mem_region *availmem_regions; 127 static int availmem_regions_sz; 128 static struct mem_region *physmem_regions; 129 static int physmem_regions_sz; 130 131 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 132 static vm_offset_t zero_page_va; 133 static struct mtx zero_page_mutex; 134 135 static struct mtx tlbivax_mutex; 136 137 /* 138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 139 * by idle thred only, no lock required. 140 */ 141 static vm_offset_t zero_page_idle_va; 142 143 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 144 static vm_offset_t copy_page_src_va; 145 static vm_offset_t copy_page_dst_va; 146 static struct mtx copy_page_mutex; 147 148 /**************************************************************************/ 149 /* PMAP */ 150 /**************************************************************************/ 151 152 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 153 vm_prot_t, u_int flags, int8_t psind); 154 155 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 156 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 157 158 /* 159 * If user pmap is processed with mmu_booke_remove and the resident count 160 * drops to 0, there are no more pages to remove, so we need not continue. 161 */ 162 #define PMAP_REMOVE_DONE(pmap) \ 163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 164 165 extern int elf32_nxstack; 166 167 /**************************************************************************/ 168 /* TLB and TID handling */ 169 /**************************************************************************/ 170 171 /* Translation ID busy table */ 172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 173 174 /* 175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 176 * core revisions and should be read from h/w registers during early config. 177 */ 178 uint32_t tlb0_entries; 179 uint32_t tlb0_ways; 180 uint32_t tlb0_entries_per_way; 181 uint32_t tlb1_entries; 182 183 #define TLB0_ENTRIES (tlb0_entries) 184 #define TLB0_WAYS (tlb0_ways) 185 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 186 187 #define TLB1_ENTRIES (tlb1_entries) 188 #define TLB1_MAXENTRIES 64 189 190 /* In-ram copy of the TLB1 */ 191 static tlb_entry_t tlb1[TLB1_MAXENTRIES]; 192 193 /* Next free entry in the TLB1 */ 194 static unsigned int tlb1_idx; 195 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE; 196 197 static tlbtid_t tid_alloc(struct pmap *); 198 static void tid_flush(tlbtid_t tid); 199 200 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 201 202 static void tlb1_write_entry(unsigned int); 203 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 204 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 205 206 static vm_size_t tsize2size(unsigned int); 207 static unsigned int size2tsize(vm_size_t); 208 static unsigned int ilog2(unsigned int); 209 210 static void set_mas4_defaults(void); 211 212 static inline void tlb0_flush_entry(vm_offset_t); 213 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 214 215 /**************************************************************************/ 216 /* Page table management */ 217 /**************************************************************************/ 218 219 static struct rwlock_padalign pvh_global_lock; 220 221 /* Data for the pv entry allocation mechanism */ 222 static uma_zone_t pvzone; 223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227 #ifndef PMAP_SHPGPERPROC 228 #define PMAP_SHPGPERPROC 200 229 #endif 230 231 static void ptbl_init(void); 232 static struct ptbl_buf *ptbl_buf_alloc(void); 233 static void ptbl_buf_free(struct ptbl_buf *); 234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 237 static void ptbl_free(mmu_t, pmap_t, unsigned int); 238 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 245 static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, 246 vm_offset_t pdir); 247 248 static pv_entry_t pv_alloc(void); 249 static void pv_free(pv_entry_t); 250 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 251 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 252 253 static void booke_pmap_init_qpages(void); 254 255 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 256 #define PTBL_BUFS (128 * 16) 257 258 struct ptbl_buf { 259 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 260 vm_offset_t kva; /* va of mapping */ 261 }; 262 263 /* ptbl free list and a lock used for access synchronization. */ 264 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 265 static struct mtx ptbl_buf_freelist_lock; 266 267 /* Base address of kva space allocated fot ptbl bufs. */ 268 static vm_offset_t ptbl_buf_pool_vabase; 269 270 /* Pointer to ptbl_buf structures. */ 271 static struct ptbl_buf *ptbl_bufs; 272 273 #ifdef SMP 274 void pmap_bootstrap_ap(volatile uint32_t *); 275 #endif 276 277 /* 278 * Kernel MMU interface 279 */ 280 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 281 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 282 vm_size_t, vm_offset_t); 283 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 284 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 285 vm_offset_t, vm_page_t *, vm_offset_t, int); 286 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 287 vm_prot_t, u_int flags, int8_t psind); 288 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 289 vm_page_t, vm_prot_t); 290 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 291 vm_prot_t); 292 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 293 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 294 vm_prot_t); 295 static void mmu_booke_init(mmu_t); 296 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 297 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 298 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 299 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 300 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 301 int); 302 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 303 vm_paddr_t *); 304 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 305 vm_object_t, vm_pindex_t, vm_size_t); 306 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 307 static void mmu_booke_page_init(mmu_t, vm_page_t); 308 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 309 static void mmu_booke_pinit(mmu_t, pmap_t); 310 static void mmu_booke_pinit0(mmu_t, pmap_t); 311 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 312 vm_prot_t); 313 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 314 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 315 static void mmu_booke_release(mmu_t, pmap_t); 316 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 317 static void mmu_booke_remove_all(mmu_t, vm_page_t); 318 static void mmu_booke_remove_write(mmu_t, vm_page_t); 319 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 320 static void mmu_booke_zero_page(mmu_t, vm_page_t); 321 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 322 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 323 static void mmu_booke_activate(mmu_t, struct thread *); 324 static void mmu_booke_deactivate(mmu_t, struct thread *); 325 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 326 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 327 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 328 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 329 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 330 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 331 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 332 static void mmu_booke_kremove(mmu_t, vm_offset_t); 333 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 334 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 335 vm_size_t); 336 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 337 void **); 338 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 339 void *); 340 static void mmu_booke_scan_init(mmu_t); 341 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 342 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 343 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 344 vm_size_t sz, vm_memattr_t mode); 345 346 static mmu_method_t mmu_booke_methods[] = { 347 /* pmap dispatcher interface */ 348 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 349 MMUMETHOD(mmu_copy, mmu_booke_copy), 350 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 351 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 352 MMUMETHOD(mmu_enter, mmu_booke_enter), 353 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 354 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 355 MMUMETHOD(mmu_extract, mmu_booke_extract), 356 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 357 MMUMETHOD(mmu_init, mmu_booke_init), 358 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 359 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 360 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 361 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 362 MMUMETHOD(mmu_map, mmu_booke_map), 363 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 364 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 365 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 366 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 367 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 368 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 369 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 370 MMUMETHOD(mmu_protect, mmu_booke_protect), 371 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 372 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 373 MMUMETHOD(mmu_release, mmu_booke_release), 374 MMUMETHOD(mmu_remove, mmu_booke_remove), 375 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 376 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 377 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 378 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 379 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 380 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 381 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 382 MMUMETHOD(mmu_activate, mmu_booke_activate), 383 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 384 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 385 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 386 387 /* Internal interfaces */ 388 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 389 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 390 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 391 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 392 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 393 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 394 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 395 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 396 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 397 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 398 399 /* dumpsys() support */ 400 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 401 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 402 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 403 404 { 0, 0 } 405 }; 406 407 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 408 409 static __inline uint32_t 410 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 411 { 412 uint32_t attrib; 413 int i; 414 415 if (ma != VM_MEMATTR_DEFAULT) { 416 switch (ma) { 417 case VM_MEMATTR_UNCACHEABLE: 418 return (MAS2_I | MAS2_G); 419 case VM_MEMATTR_WRITE_COMBINING: 420 case VM_MEMATTR_WRITE_BACK: 421 case VM_MEMATTR_PREFETCHABLE: 422 return (MAS2_I); 423 case VM_MEMATTR_WRITE_THROUGH: 424 return (MAS2_W | MAS2_M); 425 case VM_MEMATTR_CACHEABLE: 426 return (MAS2_M); 427 } 428 } 429 430 /* 431 * Assume the page is cache inhibited and access is guarded unless 432 * it's in our available memory array. 433 */ 434 attrib = _TLB_ENTRY_IO; 435 for (i = 0; i < physmem_regions_sz; i++) { 436 if ((pa >= physmem_regions[i].mr_start) && 437 (pa < (physmem_regions[i].mr_start + 438 physmem_regions[i].mr_size))) { 439 attrib = _TLB_ENTRY_MEM; 440 break; 441 } 442 } 443 444 return (attrib); 445 } 446 447 static inline void 448 tlb_miss_lock(void) 449 { 450 #ifdef SMP 451 struct pcpu *pc; 452 453 if (!smp_started) 454 return; 455 456 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 457 if (pc != pcpup) { 458 459 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 460 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 461 462 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 463 ("tlb_miss_lock: tried to lock self")); 464 465 tlb_lock(pc->pc_booke_tlb_lock); 466 467 CTR1(KTR_PMAP, "%s: locked", __func__); 468 } 469 } 470 #endif 471 } 472 473 static inline void 474 tlb_miss_unlock(void) 475 { 476 #ifdef SMP 477 struct pcpu *pc; 478 479 if (!smp_started) 480 return; 481 482 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 483 if (pc != pcpup) { 484 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 485 __func__, pc->pc_cpuid); 486 487 tlb_unlock(pc->pc_booke_tlb_lock); 488 489 CTR1(KTR_PMAP, "%s: unlocked", __func__); 490 } 491 } 492 #endif 493 } 494 495 /* Return number of entries in TLB0. */ 496 static __inline void 497 tlb0_get_tlbconf(void) 498 { 499 uint32_t tlb0_cfg; 500 501 tlb0_cfg = mfspr(SPR_TLB0CFG); 502 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 503 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 504 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 505 } 506 507 /* Return number of entries in TLB1. */ 508 static __inline void 509 tlb1_get_tlbconf(void) 510 { 511 uint32_t tlb1_cfg; 512 513 tlb1_cfg = mfspr(SPR_TLB1CFG); 514 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 515 } 516 517 /**************************************************************************/ 518 /* Page table related */ 519 /**************************************************************************/ 520 521 /* Initialize pool of kva ptbl buffers. */ 522 static void 523 ptbl_init(void) 524 { 525 int i; 526 527 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 528 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 529 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 530 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 531 532 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 533 TAILQ_INIT(&ptbl_buf_freelist); 534 535 for (i = 0; i < PTBL_BUFS; i++) { 536 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 537 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 538 } 539 } 540 541 /* Get a ptbl_buf from the freelist. */ 542 static struct ptbl_buf * 543 ptbl_buf_alloc(void) 544 { 545 struct ptbl_buf *buf; 546 547 mtx_lock(&ptbl_buf_freelist_lock); 548 buf = TAILQ_FIRST(&ptbl_buf_freelist); 549 if (buf != NULL) 550 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 551 mtx_unlock(&ptbl_buf_freelist_lock); 552 553 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 554 555 return (buf); 556 } 557 558 /* Return ptbl buff to free pool. */ 559 static void 560 ptbl_buf_free(struct ptbl_buf *buf) 561 { 562 563 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 564 565 mtx_lock(&ptbl_buf_freelist_lock); 566 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 567 mtx_unlock(&ptbl_buf_freelist_lock); 568 } 569 570 /* 571 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 572 */ 573 static void 574 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 575 { 576 struct ptbl_buf *pbuf; 577 578 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 579 580 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 581 582 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 583 if (pbuf->kva == (vm_offset_t)ptbl) { 584 /* Remove from pmap ptbl buf list. */ 585 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 586 587 /* Free corresponding ptbl buf. */ 588 ptbl_buf_free(pbuf); 589 break; 590 } 591 } 592 593 /* Allocate page table. */ 594 static pte_t * 595 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 596 { 597 vm_page_t mtbl[PTBL_PAGES]; 598 vm_page_t m; 599 struct ptbl_buf *pbuf; 600 unsigned int pidx; 601 pte_t *ptbl; 602 int i, j; 603 604 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 605 (pmap == kernel_pmap), pdir_idx); 606 607 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 608 ("ptbl_alloc: invalid pdir_idx")); 609 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 610 ("pte_alloc: valid ptbl entry exists!")); 611 612 pbuf = ptbl_buf_alloc(); 613 if (pbuf == NULL) 614 panic("pte_alloc: couldn't alloc kernel virtual memory"); 615 616 ptbl = (pte_t *)pbuf->kva; 617 618 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 619 620 /* Allocate ptbl pages, this will sleep! */ 621 for (i = 0; i < PTBL_PAGES; i++) { 622 pidx = (PTBL_PAGES * pdir_idx) + i; 623 while ((m = vm_page_alloc(NULL, pidx, 624 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 625 PMAP_UNLOCK(pmap); 626 rw_wunlock(&pvh_global_lock); 627 if (nosleep) { 628 ptbl_free_pmap_ptbl(pmap, ptbl); 629 for (j = 0; j < i; j++) 630 vm_page_free(mtbl[j]); 631 atomic_subtract_int(&vm_cnt.v_wire_count, i); 632 return (NULL); 633 } 634 VM_WAIT; 635 rw_wlock(&pvh_global_lock); 636 PMAP_LOCK(pmap); 637 } 638 mtbl[i] = m; 639 } 640 641 /* Map allocated pages into kernel_pmap. */ 642 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 643 644 /* Zero whole ptbl. */ 645 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 646 647 /* Add pbuf to the pmap ptbl bufs list. */ 648 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 649 650 return (ptbl); 651 } 652 653 /* Free ptbl pages and invalidate pdir entry. */ 654 static void 655 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 656 { 657 pte_t *ptbl; 658 vm_paddr_t pa; 659 vm_offset_t va; 660 vm_page_t m; 661 int i; 662 663 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 664 (pmap == kernel_pmap), pdir_idx); 665 666 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 667 ("ptbl_free: invalid pdir_idx")); 668 669 ptbl = pmap->pm_pdir[pdir_idx]; 670 671 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 672 673 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 674 675 /* 676 * Invalidate the pdir entry as soon as possible, so that other CPUs 677 * don't attempt to look up the page tables we are releasing. 678 */ 679 mtx_lock_spin(&tlbivax_mutex); 680 tlb_miss_lock(); 681 682 pmap->pm_pdir[pdir_idx] = NULL; 683 684 tlb_miss_unlock(); 685 mtx_unlock_spin(&tlbivax_mutex); 686 687 for (i = 0; i < PTBL_PAGES; i++) { 688 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 689 pa = pte_vatopa(mmu, kernel_pmap, va); 690 m = PHYS_TO_VM_PAGE(pa); 691 vm_page_free_zero(m); 692 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 693 mmu_booke_kremove(mmu, va); 694 } 695 696 ptbl_free_pmap_ptbl(pmap, ptbl); 697 } 698 699 /* 700 * Decrement ptbl pages hold count and attempt to free ptbl pages. 701 * Called when removing pte entry from ptbl. 702 * 703 * Return 1 if ptbl pages were freed. 704 */ 705 static int 706 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 707 { 708 pte_t *ptbl; 709 vm_paddr_t pa; 710 vm_page_t m; 711 int i; 712 713 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 714 (pmap == kernel_pmap), pdir_idx); 715 716 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 717 ("ptbl_unhold: invalid pdir_idx")); 718 KASSERT((pmap != kernel_pmap), 719 ("ptbl_unhold: unholding kernel ptbl!")); 720 721 ptbl = pmap->pm_pdir[pdir_idx]; 722 723 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 724 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 725 ("ptbl_unhold: non kva ptbl")); 726 727 /* decrement hold count */ 728 for (i = 0; i < PTBL_PAGES; i++) { 729 pa = pte_vatopa(mmu, kernel_pmap, 730 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 731 m = PHYS_TO_VM_PAGE(pa); 732 m->wire_count--; 733 } 734 735 /* 736 * Free ptbl pages if there are no pte etries in this ptbl. 737 * wire_count has the same value for all ptbl pages, so check the last 738 * page. 739 */ 740 if (m->wire_count == 0) { 741 ptbl_free(mmu, pmap, pdir_idx); 742 743 //debugf("ptbl_unhold: e (freed ptbl)\n"); 744 return (1); 745 } 746 747 return (0); 748 } 749 750 /* 751 * Increment hold count for ptbl pages. This routine is used when a new pte 752 * entry is being inserted into the ptbl. 753 */ 754 static void 755 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 756 { 757 vm_paddr_t pa; 758 pte_t *ptbl; 759 vm_page_t m; 760 int i; 761 762 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 763 pdir_idx); 764 765 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 766 ("ptbl_hold: invalid pdir_idx")); 767 KASSERT((pmap != kernel_pmap), 768 ("ptbl_hold: holding kernel ptbl!")); 769 770 ptbl = pmap->pm_pdir[pdir_idx]; 771 772 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 773 774 for (i = 0; i < PTBL_PAGES; i++) { 775 pa = pte_vatopa(mmu, kernel_pmap, 776 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 777 m = PHYS_TO_VM_PAGE(pa); 778 m->wire_count++; 779 } 780 } 781 782 /* Allocate pv_entry structure. */ 783 pv_entry_t 784 pv_alloc(void) 785 { 786 pv_entry_t pv; 787 788 pv_entry_count++; 789 if (pv_entry_count > pv_entry_high_water) 790 pagedaemon_wakeup(); 791 pv = uma_zalloc(pvzone, M_NOWAIT); 792 793 return (pv); 794 } 795 796 /* Free pv_entry structure. */ 797 static __inline void 798 pv_free(pv_entry_t pve) 799 { 800 801 pv_entry_count--; 802 uma_zfree(pvzone, pve); 803 } 804 805 806 /* Allocate and initialize pv_entry structure. */ 807 static void 808 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 809 { 810 pv_entry_t pve; 811 812 //int su = (pmap == kernel_pmap); 813 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 814 // (u_int32_t)pmap, va, (u_int32_t)m); 815 816 pve = pv_alloc(); 817 if (pve == NULL) 818 panic("pv_insert: no pv entries!"); 819 820 pve->pv_pmap = pmap; 821 pve->pv_va = va; 822 823 /* add to pv_list */ 824 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 825 rw_assert(&pvh_global_lock, RA_WLOCKED); 826 827 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 828 829 //debugf("pv_insert: e\n"); 830 } 831 832 /* Destroy pv entry. */ 833 static void 834 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 835 { 836 pv_entry_t pve; 837 838 //int su = (pmap == kernel_pmap); 839 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 840 841 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 842 rw_assert(&pvh_global_lock, RA_WLOCKED); 843 844 /* find pv entry */ 845 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 846 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 847 /* remove from pv_list */ 848 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 849 if (TAILQ_EMPTY(&m->md.pv_list)) 850 vm_page_aflag_clear(m, PGA_WRITEABLE); 851 852 /* free pv entry struct */ 853 pv_free(pve); 854 break; 855 } 856 } 857 858 //debugf("pv_remove: e\n"); 859 } 860 861 /* 862 * Clean pte entry, try to free page table page if requested. 863 * 864 * Return 1 if ptbl pages were freed, otherwise return 0. 865 */ 866 static int 867 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 868 { 869 unsigned int pdir_idx = PDIR_IDX(va); 870 unsigned int ptbl_idx = PTBL_IDX(va); 871 vm_page_t m; 872 pte_t *ptbl; 873 pte_t *pte; 874 875 //int su = (pmap == kernel_pmap); 876 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 877 // su, (u_int32_t)pmap, va, flags); 878 879 ptbl = pmap->pm_pdir[pdir_idx]; 880 KASSERT(ptbl, ("pte_remove: null ptbl")); 881 882 pte = &ptbl[ptbl_idx]; 883 884 if (pte == NULL || !PTE_ISVALID(pte)) 885 return (0); 886 887 if (PTE_ISWIRED(pte)) 888 pmap->pm_stats.wired_count--; 889 890 /* Handle managed entry. */ 891 if (PTE_ISMANAGED(pte)) { 892 /* Get vm_page_t for mapped pte. */ 893 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 894 895 if (PTE_ISMODIFIED(pte)) 896 vm_page_dirty(m); 897 898 if (PTE_ISREFERENCED(pte)) 899 vm_page_aflag_set(m, PGA_REFERENCED); 900 901 pv_remove(pmap, va, m); 902 } 903 904 mtx_lock_spin(&tlbivax_mutex); 905 tlb_miss_lock(); 906 907 tlb0_flush_entry(va); 908 *pte = 0; 909 910 tlb_miss_unlock(); 911 mtx_unlock_spin(&tlbivax_mutex); 912 913 pmap->pm_stats.resident_count--; 914 915 if (flags & PTBL_UNHOLD) { 916 //debugf("pte_remove: e (unhold)\n"); 917 return (ptbl_unhold(mmu, pmap, pdir_idx)); 918 } 919 920 //debugf("pte_remove: e\n"); 921 return (0); 922 } 923 924 /* 925 * Insert PTE for a given page and virtual address. 926 */ 927 static int 928 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 929 boolean_t nosleep) 930 { 931 unsigned int pdir_idx = PDIR_IDX(va); 932 unsigned int ptbl_idx = PTBL_IDX(va); 933 pte_t *ptbl, *pte; 934 935 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 936 pmap == kernel_pmap, pmap, va); 937 938 /* Get the page table pointer. */ 939 ptbl = pmap->pm_pdir[pdir_idx]; 940 941 if (ptbl == NULL) { 942 /* Allocate page table pages. */ 943 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 944 if (ptbl == NULL) { 945 KASSERT(nosleep, ("nosleep and NULL ptbl")); 946 return (ENOMEM); 947 } 948 } else { 949 /* 950 * Check if there is valid mapping for requested 951 * va, if there is, remove it. 952 */ 953 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 954 if (PTE_ISVALID(pte)) { 955 pte_remove(mmu, pmap, va, PTBL_HOLD); 956 } else { 957 /* 958 * pte is not used, increment hold count 959 * for ptbl pages. 960 */ 961 if (pmap != kernel_pmap) 962 ptbl_hold(mmu, pmap, pdir_idx); 963 } 964 } 965 966 /* 967 * Insert pv_entry into pv_list for mapped page if part of managed 968 * memory. 969 */ 970 if ((m->oflags & VPO_UNMANAGED) == 0) { 971 flags |= PTE_MANAGED; 972 973 /* Create and insert pv entry. */ 974 pv_insert(pmap, va, m); 975 } 976 977 pmap->pm_stats.resident_count++; 978 979 mtx_lock_spin(&tlbivax_mutex); 980 tlb_miss_lock(); 981 982 tlb0_flush_entry(va); 983 if (pmap->pm_pdir[pdir_idx] == NULL) { 984 /* 985 * If we just allocated a new page table, hook it in 986 * the pdir. 987 */ 988 pmap->pm_pdir[pdir_idx] = ptbl; 989 } 990 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 991 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 992 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 993 994 tlb_miss_unlock(); 995 mtx_unlock_spin(&tlbivax_mutex); 996 return (0); 997 } 998 999 /* Return the pa for the given pmap/va. */ 1000 static vm_paddr_t 1001 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1002 { 1003 vm_paddr_t pa = 0; 1004 pte_t *pte; 1005 1006 pte = pte_find(mmu, pmap, va); 1007 if ((pte != NULL) && PTE_ISVALID(pte)) 1008 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1009 return (pa); 1010 } 1011 1012 /* Get a pointer to a PTE in a page table. */ 1013 static pte_t * 1014 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1015 { 1016 unsigned int pdir_idx = PDIR_IDX(va); 1017 unsigned int ptbl_idx = PTBL_IDX(va); 1018 1019 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1020 1021 if (pmap->pm_pdir[pdir_idx]) 1022 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1023 1024 return (NULL); 1025 } 1026 1027 /* Set up kernel page tables. */ 1028 static void 1029 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1030 { 1031 int i; 1032 vm_offset_t va; 1033 pte_t *pte; 1034 1035 /* Initialize kernel pdir */ 1036 for (i = 0; i < kernel_ptbls; i++) 1037 kernel_pmap->pm_pdir[kptbl_min + i] = 1038 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1039 1040 /* 1041 * Fill in PTEs covering kernel code and data. They are not required 1042 * for address translation, as this area is covered by static TLB1 1043 * entries, but for pte_vatopa() to work correctly with kernel area 1044 * addresses. 1045 */ 1046 for (va = addr; va < data_end; va += PAGE_SIZE) { 1047 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1048 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1049 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1050 PTE_VALID | PTE_PS_4KB; 1051 } 1052 } 1053 1054 /**************************************************************************/ 1055 /* PMAP related */ 1056 /**************************************************************************/ 1057 1058 /* 1059 * This is called during booke_init, before the system is really initialized. 1060 */ 1061 static void 1062 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1063 { 1064 vm_paddr_t phys_kernelend; 1065 struct mem_region *mp, *mp1; 1066 int cnt, i, j; 1067 vm_paddr_t s, e, sz; 1068 vm_paddr_t physsz, hwphyssz; 1069 u_int phys_avail_count; 1070 vm_size_t kstack0_sz; 1071 vm_offset_t kernel_pdir, kstack0; 1072 vm_paddr_t kstack0_phys; 1073 void *dpcpu; 1074 1075 debugf("mmu_booke_bootstrap: entered\n"); 1076 1077 /* Set interesting system properties */ 1078 hw_direct_map = 0; 1079 elf32_nxstack = 1; 1080 1081 /* Initialize invalidation mutex */ 1082 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1083 1084 /* Read TLB0 size and associativity. */ 1085 tlb0_get_tlbconf(); 1086 1087 /* 1088 * Align kernel start and end address (kernel image). 1089 * Note that kernel end does not necessarily relate to kernsize. 1090 * kernsize is the size of the kernel that is actually mapped. 1091 */ 1092 kernstart = trunc_page(start); 1093 data_start = round_page(kernelend); 1094 data_end = data_start; 1095 1096 /* 1097 * Addresses of preloaded modules (like file systems) use 1098 * physical addresses. Make sure we relocate those into 1099 * virtual addresses. 1100 */ 1101 preload_addr_relocate = kernstart - kernload; 1102 1103 /* Allocate the dynamic per-cpu area. */ 1104 dpcpu = (void *)data_end; 1105 data_end += DPCPU_SIZE; 1106 1107 /* Allocate space for the message buffer. */ 1108 msgbufp = (struct msgbuf *)data_end; 1109 data_end += msgbufsize; 1110 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1111 data_end); 1112 1113 data_end = round_page(data_end); 1114 1115 /* Allocate space for ptbl_bufs. */ 1116 ptbl_bufs = (struct ptbl_buf *)data_end; 1117 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1118 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1119 data_end); 1120 1121 data_end = round_page(data_end); 1122 1123 /* Allocate PTE tables for kernel KVA. */ 1124 kernel_pdir = data_end; 1125 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1126 PDIR_SIZE - 1) / PDIR_SIZE; 1127 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1128 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1129 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1130 1131 debugf(" data_end: 0x%08x\n", data_end); 1132 if (data_end - kernstart > kernsize) { 1133 kernsize += tlb1_mapin_region(kernstart + kernsize, 1134 kernload + kernsize, (data_end - kernstart) - kernsize); 1135 } 1136 data_end = kernstart + kernsize; 1137 debugf(" updated data_end: 0x%08x\n", data_end); 1138 1139 /* 1140 * Clear the structures - note we can only do it safely after the 1141 * possible additional TLB1 translations are in place (above) so that 1142 * all range up to the currently calculated 'data_end' is covered. 1143 */ 1144 dpcpu_init(dpcpu, 0); 1145 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1146 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1147 1148 /*******************************************************/ 1149 /* Set the start and end of kva. */ 1150 /*******************************************************/ 1151 virtual_avail = round_page(data_end); 1152 virtual_end = VM_MAX_KERNEL_ADDRESS; 1153 1154 /* Allocate KVA space for page zero/copy operations. */ 1155 zero_page_va = virtual_avail; 1156 virtual_avail += PAGE_SIZE; 1157 zero_page_idle_va = virtual_avail; 1158 virtual_avail += PAGE_SIZE; 1159 copy_page_src_va = virtual_avail; 1160 virtual_avail += PAGE_SIZE; 1161 copy_page_dst_va = virtual_avail; 1162 virtual_avail += PAGE_SIZE; 1163 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1164 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1165 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1166 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1167 1168 /* Initialize page zero/copy mutexes. */ 1169 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1170 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1171 1172 /* Allocate KVA space for ptbl bufs. */ 1173 ptbl_buf_pool_vabase = virtual_avail; 1174 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1175 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1176 ptbl_buf_pool_vabase, virtual_avail); 1177 1178 /* Calculate corresponding physical addresses for the kernel region. */ 1179 phys_kernelend = kernload + kernsize; 1180 debugf("kernel image and allocated data:\n"); 1181 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1182 debugf(" kernstart = 0x%08x\n", kernstart); 1183 debugf(" kernsize = 0x%08x\n", kernsize); 1184 1185 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1186 panic("mmu_booke_bootstrap: phys_avail too small"); 1187 1188 /* 1189 * Remove kernel physical address range from avail regions list. Page 1190 * align all regions. Non-page aligned memory isn't very interesting 1191 * to us. Also, sort the entries for ascending addresses. 1192 */ 1193 1194 /* Retrieve phys/avail mem regions */ 1195 mem_regions(&physmem_regions, &physmem_regions_sz, 1196 &availmem_regions, &availmem_regions_sz); 1197 sz = 0; 1198 cnt = availmem_regions_sz; 1199 debugf("processing avail regions:\n"); 1200 for (mp = availmem_regions; mp->mr_size; mp++) { 1201 s = mp->mr_start; 1202 e = mp->mr_start + mp->mr_size; 1203 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1204 /* Check whether this region holds all of the kernel. */ 1205 if (s < kernload && e > phys_kernelend) { 1206 availmem_regions[cnt].mr_start = phys_kernelend; 1207 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1208 e = kernload; 1209 } 1210 /* Look whether this regions starts within the kernel. */ 1211 if (s >= kernload && s < phys_kernelend) { 1212 if (e <= phys_kernelend) 1213 goto empty; 1214 s = phys_kernelend; 1215 } 1216 /* Now look whether this region ends within the kernel. */ 1217 if (e > kernload && e <= phys_kernelend) { 1218 if (s >= kernload) 1219 goto empty; 1220 e = kernload; 1221 } 1222 /* Now page align the start and size of the region. */ 1223 s = round_page(s); 1224 e = trunc_page(e); 1225 if (e < s) 1226 e = s; 1227 sz = e - s; 1228 debugf("%09jx-%09jx = %jx\n", 1229 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1230 1231 /* Check whether some memory is left here. */ 1232 if (sz == 0) { 1233 empty: 1234 memmove(mp, mp + 1, 1235 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1236 cnt--; 1237 mp--; 1238 continue; 1239 } 1240 1241 /* Do an insertion sort. */ 1242 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1243 if (s < mp1->mr_start) 1244 break; 1245 if (mp1 < mp) { 1246 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1247 mp1->mr_start = s; 1248 mp1->mr_size = sz; 1249 } else { 1250 mp->mr_start = s; 1251 mp->mr_size = sz; 1252 } 1253 } 1254 availmem_regions_sz = cnt; 1255 1256 /*******************************************************/ 1257 /* Steal physical memory for kernel stack from the end */ 1258 /* of the first avail region */ 1259 /*******************************************************/ 1260 kstack0_sz = kstack_pages * PAGE_SIZE; 1261 kstack0_phys = availmem_regions[0].mr_start + 1262 availmem_regions[0].mr_size; 1263 kstack0_phys -= kstack0_sz; 1264 availmem_regions[0].mr_size -= kstack0_sz; 1265 1266 /*******************************************************/ 1267 /* Fill in phys_avail table, based on availmem_regions */ 1268 /*******************************************************/ 1269 phys_avail_count = 0; 1270 physsz = 0; 1271 hwphyssz = 0; 1272 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1273 1274 debugf("fill in phys_avail:\n"); 1275 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1276 1277 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1278 (uintmax_t)availmem_regions[i].mr_start, 1279 (uintmax_t)availmem_regions[i].mr_start + 1280 availmem_regions[i].mr_size, 1281 (uintmax_t)availmem_regions[i].mr_size); 1282 1283 if (hwphyssz != 0 && 1284 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1285 debugf(" hw.physmem adjust\n"); 1286 if (physsz < hwphyssz) { 1287 phys_avail[j] = availmem_regions[i].mr_start; 1288 phys_avail[j + 1] = 1289 availmem_regions[i].mr_start + 1290 hwphyssz - physsz; 1291 physsz = hwphyssz; 1292 phys_avail_count++; 1293 } 1294 break; 1295 } 1296 1297 phys_avail[j] = availmem_regions[i].mr_start; 1298 phys_avail[j + 1] = availmem_regions[i].mr_start + 1299 availmem_regions[i].mr_size; 1300 phys_avail_count++; 1301 physsz += availmem_regions[i].mr_size; 1302 } 1303 physmem = btoc(physsz); 1304 1305 /* Calculate the last available physical address. */ 1306 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1307 ; 1308 Maxmem = powerpc_btop(phys_avail[i + 1]); 1309 1310 debugf("Maxmem = 0x%08lx\n", Maxmem); 1311 debugf("phys_avail_count = %d\n", phys_avail_count); 1312 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1313 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1314 1315 /*******************************************************/ 1316 /* Initialize (statically allocated) kernel pmap. */ 1317 /*******************************************************/ 1318 PMAP_LOCK_INIT(kernel_pmap); 1319 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1320 1321 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1322 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1323 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1324 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1325 1326 kernel_pte_alloc(data_end, kernstart, kernel_pdir); 1327 for (i = 0; i < MAXCPU; i++) { 1328 kernel_pmap->pm_tid[i] = TID_KERNEL; 1329 1330 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1331 tidbusy[i][TID_KERNEL] = kernel_pmap; 1332 } 1333 1334 /* Mark kernel_pmap active on all CPUs */ 1335 CPU_FILL(&kernel_pmap->pm_active); 1336 1337 /* 1338 * Initialize the global pv list lock. 1339 */ 1340 rw_init(&pvh_global_lock, "pmap pv global"); 1341 1342 /*******************************************************/ 1343 /* Final setup */ 1344 /*******************************************************/ 1345 1346 /* Enter kstack0 into kernel map, provide guard page */ 1347 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1348 thread0.td_kstack = kstack0; 1349 thread0.td_kstack_pages = kstack_pages; 1350 1351 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1352 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1353 kstack0_phys, kstack0_phys + kstack0_sz); 1354 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1355 1356 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1357 for (i = 0; i < kstack_pages; i++) { 1358 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1359 kstack0 += PAGE_SIZE; 1360 kstack0_phys += PAGE_SIZE; 1361 } 1362 1363 pmap_bootstrapped = 1; 1364 1365 debugf("virtual_avail = %08x\n", virtual_avail); 1366 debugf("virtual_end = %08x\n", virtual_end); 1367 1368 debugf("mmu_booke_bootstrap: exit\n"); 1369 } 1370 1371 #ifdef SMP 1372 void 1373 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1374 { 1375 int i; 1376 1377 /* 1378 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1379 * have the snapshot of its contents in the s/w tlb1[] table, so use 1380 * these values directly to (re)program AP's TLB1 hardware. 1381 */ 1382 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1383 /* Skip invalid entries */ 1384 if (!(tlb1[i].mas1 & MAS1_VALID)) 1385 continue; 1386 1387 tlb1_write_entry(i); 1388 } 1389 1390 set_mas4_defaults(); 1391 } 1392 #endif 1393 1394 static void 1395 booke_pmap_init_qpages(void) 1396 { 1397 struct pcpu *pc; 1398 int i; 1399 1400 CPU_FOREACH(i) { 1401 pc = pcpu_find(i); 1402 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1403 if (pc->pc_qmap_addr == 0) 1404 panic("pmap_init_qpages: unable to allocate KVA"); 1405 } 1406 } 1407 1408 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1409 1410 /* 1411 * Get the physical page address for the given pmap/virtual address. 1412 */ 1413 static vm_paddr_t 1414 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1415 { 1416 vm_paddr_t pa; 1417 1418 PMAP_LOCK(pmap); 1419 pa = pte_vatopa(mmu, pmap, va); 1420 PMAP_UNLOCK(pmap); 1421 1422 return (pa); 1423 } 1424 1425 /* 1426 * Extract the physical page address associated with the given 1427 * kernel virtual address. 1428 */ 1429 static vm_paddr_t 1430 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1431 { 1432 int i; 1433 1434 /* Check TLB1 mappings */ 1435 for (i = 0; i < tlb1_idx; i++) { 1436 if (!(tlb1[i].mas1 & MAS1_VALID)) 1437 continue; 1438 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1439 return (tlb1[i].phys + (va - tlb1[i].virt)); 1440 } 1441 1442 return (pte_vatopa(mmu, kernel_pmap, va)); 1443 } 1444 1445 /* 1446 * Initialize the pmap module. 1447 * Called by vm_init, to initialize any structures that the pmap 1448 * system needs to map virtual memory. 1449 */ 1450 static void 1451 mmu_booke_init(mmu_t mmu) 1452 { 1453 int shpgperproc = PMAP_SHPGPERPROC; 1454 1455 /* 1456 * Initialize the address space (zone) for the pv entries. Set a 1457 * high water mark so that the system can recover from excessive 1458 * numbers of pv entries. 1459 */ 1460 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1461 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1462 1463 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1464 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1465 1466 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1467 pv_entry_high_water = 9 * (pv_entry_max / 10); 1468 1469 uma_zone_reserve_kva(pvzone, pv_entry_max); 1470 1471 /* Pre-fill pvzone with initial number of pv entries. */ 1472 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1473 1474 /* Initialize ptbl allocation. */ 1475 ptbl_init(); 1476 } 1477 1478 /* 1479 * Map a list of wired pages into kernel virtual address space. This is 1480 * intended for temporary mappings which do not need page modification or 1481 * references recorded. Existing mappings in the region are overwritten. 1482 */ 1483 static void 1484 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1485 { 1486 vm_offset_t va; 1487 1488 va = sva; 1489 while (count-- > 0) { 1490 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1491 va += PAGE_SIZE; 1492 m++; 1493 } 1494 } 1495 1496 /* 1497 * Remove page mappings from kernel virtual address space. Intended for 1498 * temporary mappings entered by mmu_booke_qenter. 1499 */ 1500 static void 1501 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1502 { 1503 vm_offset_t va; 1504 1505 va = sva; 1506 while (count-- > 0) { 1507 mmu_booke_kremove(mmu, va); 1508 va += PAGE_SIZE; 1509 } 1510 } 1511 1512 /* 1513 * Map a wired page into kernel virtual address space. 1514 */ 1515 static void 1516 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1517 { 1518 1519 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1520 } 1521 1522 static void 1523 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1524 { 1525 uint32_t flags; 1526 pte_t *pte; 1527 1528 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1529 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1530 1531 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1532 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1533 flags |= PTE_PS_4KB; 1534 1535 pte = pte_find(mmu, kernel_pmap, va); 1536 1537 mtx_lock_spin(&tlbivax_mutex); 1538 tlb_miss_lock(); 1539 1540 if (PTE_ISVALID(pte)) { 1541 1542 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1543 1544 /* Flush entry from TLB0 */ 1545 tlb0_flush_entry(va); 1546 } 1547 1548 *pte = PTE_RPN_FROM_PA(pa) | flags; 1549 1550 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1551 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1552 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1553 1554 /* Flush the real memory from the instruction cache. */ 1555 if ((flags & (PTE_I | PTE_G)) == 0) 1556 __syncicache((void *)va, PAGE_SIZE); 1557 1558 tlb_miss_unlock(); 1559 mtx_unlock_spin(&tlbivax_mutex); 1560 } 1561 1562 /* 1563 * Remove a page from kernel page table. 1564 */ 1565 static void 1566 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1567 { 1568 pte_t *pte; 1569 1570 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 1571 1572 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1573 (va <= VM_MAX_KERNEL_ADDRESS)), 1574 ("mmu_booke_kremove: invalid va")); 1575 1576 pte = pte_find(mmu, kernel_pmap, va); 1577 1578 if (!PTE_ISVALID(pte)) { 1579 1580 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1581 1582 return; 1583 } 1584 1585 mtx_lock_spin(&tlbivax_mutex); 1586 tlb_miss_lock(); 1587 1588 /* Invalidate entry in TLB0, update PTE. */ 1589 tlb0_flush_entry(va); 1590 *pte = 0; 1591 1592 tlb_miss_unlock(); 1593 mtx_unlock_spin(&tlbivax_mutex); 1594 } 1595 1596 /* 1597 * Initialize pmap associated with process 0. 1598 */ 1599 static void 1600 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1601 { 1602 1603 PMAP_LOCK_INIT(pmap); 1604 mmu_booke_pinit(mmu, pmap); 1605 PCPU_SET(curpmap, pmap); 1606 } 1607 1608 /* 1609 * Initialize a preallocated and zeroed pmap structure, 1610 * such as one in a vmspace structure. 1611 */ 1612 static void 1613 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1614 { 1615 int i; 1616 1617 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1618 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1619 1620 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1621 1622 for (i = 0; i < MAXCPU; i++) 1623 pmap->pm_tid[i] = TID_NONE; 1624 CPU_ZERO(&kernel_pmap->pm_active); 1625 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1626 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1627 TAILQ_INIT(&pmap->pm_ptbl_list); 1628 } 1629 1630 /* 1631 * Release any resources held by the given physical map. 1632 * Called when a pmap initialized by mmu_booke_pinit is being released. 1633 * Should only be called if the map contains no valid mappings. 1634 */ 1635 static void 1636 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1637 { 1638 1639 KASSERT(pmap->pm_stats.resident_count == 0, 1640 ("pmap_release: pmap resident count %ld != 0", 1641 pmap->pm_stats.resident_count)); 1642 } 1643 1644 /* 1645 * Insert the given physical page at the specified virtual address in the 1646 * target physical map with the protection requested. If specified the page 1647 * will be wired down. 1648 */ 1649 static int 1650 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1651 vm_prot_t prot, u_int flags, int8_t psind) 1652 { 1653 int error; 1654 1655 rw_wlock(&pvh_global_lock); 1656 PMAP_LOCK(pmap); 1657 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1658 rw_wunlock(&pvh_global_lock); 1659 PMAP_UNLOCK(pmap); 1660 return (error); 1661 } 1662 1663 static int 1664 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1665 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1666 { 1667 pte_t *pte; 1668 vm_paddr_t pa; 1669 uint32_t flags; 1670 int error, su, sync; 1671 1672 pa = VM_PAGE_TO_PHYS(m); 1673 su = (pmap == kernel_pmap); 1674 sync = 0; 1675 1676 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1677 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1678 // (u_int32_t)pmap, su, pmap->pm_tid, 1679 // (u_int32_t)m, va, pa, prot, flags); 1680 1681 if (su) { 1682 KASSERT(((va >= virtual_avail) && 1683 (va <= VM_MAX_KERNEL_ADDRESS)), 1684 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1685 } else { 1686 KASSERT((va <= VM_MAXUSER_ADDRESS), 1687 ("mmu_booke_enter_locked: user pmap, non user va")); 1688 } 1689 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1690 VM_OBJECT_ASSERT_LOCKED(m->object); 1691 1692 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1693 1694 /* 1695 * If there is an existing mapping, and the physical address has not 1696 * changed, must be protection or wiring change. 1697 */ 1698 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1699 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1700 1701 /* 1702 * Before actually updating pte->flags we calculate and 1703 * prepare its new value in a helper var. 1704 */ 1705 flags = *pte; 1706 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1707 1708 /* Wiring change, just update stats. */ 1709 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1710 if (!PTE_ISWIRED(pte)) { 1711 flags |= PTE_WIRED; 1712 pmap->pm_stats.wired_count++; 1713 } 1714 } else { 1715 if (PTE_ISWIRED(pte)) { 1716 flags &= ~PTE_WIRED; 1717 pmap->pm_stats.wired_count--; 1718 } 1719 } 1720 1721 if (prot & VM_PROT_WRITE) { 1722 /* Add write permissions. */ 1723 flags |= PTE_SW; 1724 if (!su) 1725 flags |= PTE_UW; 1726 1727 if ((flags & PTE_MANAGED) != 0) 1728 vm_page_aflag_set(m, PGA_WRITEABLE); 1729 } else { 1730 /* Handle modified pages, sense modify status. */ 1731 1732 /* 1733 * The PTE_MODIFIED flag could be set by underlying 1734 * TLB misses since we last read it (above), possibly 1735 * other CPUs could update it so we check in the PTE 1736 * directly rather than rely on that saved local flags 1737 * copy. 1738 */ 1739 if (PTE_ISMODIFIED(pte)) 1740 vm_page_dirty(m); 1741 } 1742 1743 if (prot & VM_PROT_EXECUTE) { 1744 flags |= PTE_SX; 1745 if (!su) 1746 flags |= PTE_UX; 1747 1748 /* 1749 * Check existing flags for execute permissions: if we 1750 * are turning execute permissions on, icache should 1751 * be flushed. 1752 */ 1753 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1754 sync++; 1755 } 1756 1757 flags &= ~PTE_REFERENCED; 1758 1759 /* 1760 * The new flags value is all calculated -- only now actually 1761 * update the PTE. 1762 */ 1763 mtx_lock_spin(&tlbivax_mutex); 1764 tlb_miss_lock(); 1765 1766 tlb0_flush_entry(va); 1767 *pte &= ~PTE_FLAGS_MASK; 1768 *pte |= flags; 1769 1770 tlb_miss_unlock(); 1771 mtx_unlock_spin(&tlbivax_mutex); 1772 1773 } else { 1774 /* 1775 * If there is an existing mapping, but it's for a different 1776 * physical address, pte_enter() will delete the old mapping. 1777 */ 1778 //if ((pte != NULL) && PTE_ISVALID(pte)) 1779 // debugf("mmu_booke_enter_locked: replace\n"); 1780 //else 1781 // debugf("mmu_booke_enter_locked: new\n"); 1782 1783 /* Now set up the flags and install the new mapping. */ 1784 flags = (PTE_SR | PTE_VALID); 1785 flags |= PTE_M; 1786 1787 if (!su) 1788 flags |= PTE_UR; 1789 1790 if (prot & VM_PROT_WRITE) { 1791 flags |= PTE_SW; 1792 if (!su) 1793 flags |= PTE_UW; 1794 1795 if ((m->oflags & VPO_UNMANAGED) == 0) 1796 vm_page_aflag_set(m, PGA_WRITEABLE); 1797 } 1798 1799 if (prot & VM_PROT_EXECUTE) { 1800 flags |= PTE_SX; 1801 if (!su) 1802 flags |= PTE_UX; 1803 } 1804 1805 /* If its wired update stats. */ 1806 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1807 flags |= PTE_WIRED; 1808 1809 error = pte_enter(mmu, pmap, m, va, flags, 1810 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1811 if (error != 0) 1812 return (KERN_RESOURCE_SHORTAGE); 1813 1814 if ((flags & PMAP_ENTER_WIRED) != 0) 1815 pmap->pm_stats.wired_count++; 1816 1817 /* Flush the real memory from the instruction cache. */ 1818 if (prot & VM_PROT_EXECUTE) 1819 sync++; 1820 } 1821 1822 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1823 __syncicache((void *)va, PAGE_SIZE); 1824 sync = 0; 1825 } 1826 1827 return (KERN_SUCCESS); 1828 } 1829 1830 /* 1831 * Maps a sequence of resident pages belonging to the same object. 1832 * The sequence begins with the given page m_start. This page is 1833 * mapped at the given virtual address start. Each subsequent page is 1834 * mapped at a virtual address that is offset from start by the same 1835 * amount as the page is offset from m_start within the object. The 1836 * last page in the sequence is the page with the largest offset from 1837 * m_start that can be mapped at a virtual address less than the given 1838 * virtual address end. Not every virtual page between start and end 1839 * is mapped; only those for which a resident page exists with the 1840 * corresponding offset from m_start are mapped. 1841 */ 1842 static void 1843 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1844 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1845 { 1846 vm_page_t m; 1847 vm_pindex_t diff, psize; 1848 1849 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1850 1851 psize = atop(end - start); 1852 m = m_start; 1853 rw_wlock(&pvh_global_lock); 1854 PMAP_LOCK(pmap); 1855 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1856 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1857 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1858 PMAP_ENTER_NOSLEEP, 0); 1859 m = TAILQ_NEXT(m, listq); 1860 } 1861 rw_wunlock(&pvh_global_lock); 1862 PMAP_UNLOCK(pmap); 1863 } 1864 1865 static void 1866 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1867 vm_prot_t prot) 1868 { 1869 1870 rw_wlock(&pvh_global_lock); 1871 PMAP_LOCK(pmap); 1872 mmu_booke_enter_locked(mmu, pmap, va, m, 1873 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1874 0); 1875 rw_wunlock(&pvh_global_lock); 1876 PMAP_UNLOCK(pmap); 1877 } 1878 1879 /* 1880 * Remove the given range of addresses from the specified map. 1881 * 1882 * It is assumed that the start and end are properly rounded to the page size. 1883 */ 1884 static void 1885 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1886 { 1887 pte_t *pte; 1888 uint8_t hold_flag; 1889 1890 int su = (pmap == kernel_pmap); 1891 1892 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1893 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1894 1895 if (su) { 1896 KASSERT(((va >= virtual_avail) && 1897 (va <= VM_MAX_KERNEL_ADDRESS)), 1898 ("mmu_booke_remove: kernel pmap, non kernel va")); 1899 } else { 1900 KASSERT((va <= VM_MAXUSER_ADDRESS), 1901 ("mmu_booke_remove: user pmap, non user va")); 1902 } 1903 1904 if (PMAP_REMOVE_DONE(pmap)) { 1905 //debugf("mmu_booke_remove: e (empty)\n"); 1906 return; 1907 } 1908 1909 hold_flag = PTBL_HOLD_FLAG(pmap); 1910 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1911 1912 rw_wlock(&pvh_global_lock); 1913 PMAP_LOCK(pmap); 1914 for (; va < endva; va += PAGE_SIZE) { 1915 pte = pte_find(mmu, pmap, va); 1916 if ((pte != NULL) && PTE_ISVALID(pte)) 1917 pte_remove(mmu, pmap, va, hold_flag); 1918 } 1919 PMAP_UNLOCK(pmap); 1920 rw_wunlock(&pvh_global_lock); 1921 1922 //debugf("mmu_booke_remove: e\n"); 1923 } 1924 1925 /* 1926 * Remove physical page from all pmaps in which it resides. 1927 */ 1928 static void 1929 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1930 { 1931 pv_entry_t pv, pvn; 1932 uint8_t hold_flag; 1933 1934 rw_wlock(&pvh_global_lock); 1935 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1936 pvn = TAILQ_NEXT(pv, pv_link); 1937 1938 PMAP_LOCK(pv->pv_pmap); 1939 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1940 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1941 PMAP_UNLOCK(pv->pv_pmap); 1942 } 1943 vm_page_aflag_clear(m, PGA_WRITEABLE); 1944 rw_wunlock(&pvh_global_lock); 1945 } 1946 1947 /* 1948 * Map a range of physical addresses into kernel virtual address space. 1949 */ 1950 static vm_offset_t 1951 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1952 vm_paddr_t pa_end, int prot) 1953 { 1954 vm_offset_t sva = *virt; 1955 vm_offset_t va = sva; 1956 1957 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1958 // sva, pa_start, pa_end); 1959 1960 while (pa_start < pa_end) { 1961 mmu_booke_kenter(mmu, va, pa_start); 1962 va += PAGE_SIZE; 1963 pa_start += PAGE_SIZE; 1964 } 1965 *virt = va; 1966 1967 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1968 return (sva); 1969 } 1970 1971 /* 1972 * The pmap must be activated before it's address space can be accessed in any 1973 * way. 1974 */ 1975 static void 1976 mmu_booke_activate(mmu_t mmu, struct thread *td) 1977 { 1978 pmap_t pmap; 1979 u_int cpuid; 1980 1981 pmap = &td->td_proc->p_vmspace->vm_pmap; 1982 1983 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1984 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1985 1986 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1987 1988 sched_pin(); 1989 1990 cpuid = PCPU_GET(cpuid); 1991 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1992 PCPU_SET(curpmap, pmap); 1993 1994 if (pmap->pm_tid[cpuid] == TID_NONE) 1995 tid_alloc(pmap); 1996 1997 /* Load PID0 register with pmap tid value. */ 1998 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1999 __asm __volatile("isync"); 2000 2001 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2002 2003 sched_unpin(); 2004 2005 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2006 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2007 } 2008 2009 /* 2010 * Deactivate the specified process's address space. 2011 */ 2012 static void 2013 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2014 { 2015 pmap_t pmap; 2016 2017 pmap = &td->td_proc->p_vmspace->vm_pmap; 2018 2019 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2020 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2021 2022 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2023 2024 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2025 PCPU_SET(curpmap, NULL); 2026 } 2027 2028 /* 2029 * Copy the range specified by src_addr/len 2030 * from the source map to the range dst_addr/len 2031 * in the destination map. 2032 * 2033 * This routine is only advisory and need not do anything. 2034 */ 2035 static void 2036 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2037 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2038 { 2039 2040 } 2041 2042 /* 2043 * Set the physical protection on the specified range of this map as requested. 2044 */ 2045 static void 2046 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2047 vm_prot_t prot) 2048 { 2049 vm_offset_t va; 2050 vm_page_t m; 2051 pte_t *pte; 2052 2053 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2054 mmu_booke_remove(mmu, pmap, sva, eva); 2055 return; 2056 } 2057 2058 if (prot & VM_PROT_WRITE) 2059 return; 2060 2061 PMAP_LOCK(pmap); 2062 for (va = sva; va < eva; va += PAGE_SIZE) { 2063 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2064 if (PTE_ISVALID(pte)) { 2065 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2066 2067 mtx_lock_spin(&tlbivax_mutex); 2068 tlb_miss_lock(); 2069 2070 /* Handle modified pages. */ 2071 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2072 vm_page_dirty(m); 2073 2074 tlb0_flush_entry(va); 2075 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2076 2077 tlb_miss_unlock(); 2078 mtx_unlock_spin(&tlbivax_mutex); 2079 } 2080 } 2081 } 2082 PMAP_UNLOCK(pmap); 2083 } 2084 2085 /* 2086 * Clear the write and modified bits in each of the given page's mappings. 2087 */ 2088 static void 2089 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2090 { 2091 pv_entry_t pv; 2092 pte_t *pte; 2093 2094 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2095 ("mmu_booke_remove_write: page %p is not managed", m)); 2096 2097 /* 2098 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2099 * set by another thread while the object is locked. Thus, 2100 * if PGA_WRITEABLE is clear, no page table entries need updating. 2101 */ 2102 VM_OBJECT_ASSERT_WLOCKED(m->object); 2103 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2104 return; 2105 rw_wlock(&pvh_global_lock); 2106 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2107 PMAP_LOCK(pv->pv_pmap); 2108 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2109 if (PTE_ISVALID(pte)) { 2110 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2111 2112 mtx_lock_spin(&tlbivax_mutex); 2113 tlb_miss_lock(); 2114 2115 /* Handle modified pages. */ 2116 if (PTE_ISMODIFIED(pte)) 2117 vm_page_dirty(m); 2118 2119 /* Flush mapping from TLB0. */ 2120 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2121 2122 tlb_miss_unlock(); 2123 mtx_unlock_spin(&tlbivax_mutex); 2124 } 2125 } 2126 PMAP_UNLOCK(pv->pv_pmap); 2127 } 2128 vm_page_aflag_clear(m, PGA_WRITEABLE); 2129 rw_wunlock(&pvh_global_lock); 2130 } 2131 2132 static void 2133 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2134 { 2135 pte_t *pte; 2136 pmap_t pmap; 2137 vm_page_t m; 2138 vm_offset_t addr; 2139 vm_paddr_t pa = 0; 2140 int active, valid; 2141 2142 va = trunc_page(va); 2143 sz = round_page(sz); 2144 2145 rw_wlock(&pvh_global_lock); 2146 pmap = PCPU_GET(curpmap); 2147 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2148 while (sz > 0) { 2149 PMAP_LOCK(pm); 2150 pte = pte_find(mmu, pm, va); 2151 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2152 if (valid) 2153 pa = PTE_PA(pte); 2154 PMAP_UNLOCK(pm); 2155 if (valid) { 2156 if (!active) { 2157 /* Create a mapping in the active pmap. */ 2158 addr = 0; 2159 m = PHYS_TO_VM_PAGE(pa); 2160 PMAP_LOCK(pmap); 2161 pte_enter(mmu, pmap, m, addr, 2162 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2163 __syncicache((void *)addr, PAGE_SIZE); 2164 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2165 PMAP_UNLOCK(pmap); 2166 } else 2167 __syncicache((void *)va, PAGE_SIZE); 2168 } 2169 va += PAGE_SIZE; 2170 sz -= PAGE_SIZE; 2171 } 2172 rw_wunlock(&pvh_global_lock); 2173 } 2174 2175 /* 2176 * Atomically extract and hold the physical page with the given 2177 * pmap and virtual address pair if that mapping permits the given 2178 * protection. 2179 */ 2180 static vm_page_t 2181 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2182 vm_prot_t prot) 2183 { 2184 pte_t *pte; 2185 vm_page_t m; 2186 uint32_t pte_wbit; 2187 vm_paddr_t pa; 2188 2189 m = NULL; 2190 pa = 0; 2191 PMAP_LOCK(pmap); 2192 retry: 2193 pte = pte_find(mmu, pmap, va); 2194 if ((pte != NULL) && PTE_ISVALID(pte)) { 2195 if (pmap == kernel_pmap) 2196 pte_wbit = PTE_SW; 2197 else 2198 pte_wbit = PTE_UW; 2199 2200 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2201 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2202 goto retry; 2203 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2204 vm_page_hold(m); 2205 } 2206 } 2207 2208 PA_UNLOCK_COND(pa); 2209 PMAP_UNLOCK(pmap); 2210 return (m); 2211 } 2212 2213 /* 2214 * Initialize a vm_page's machine-dependent fields. 2215 */ 2216 static void 2217 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2218 { 2219 2220 TAILQ_INIT(&m->md.pv_list); 2221 } 2222 2223 /* 2224 * mmu_booke_zero_page_area zeros the specified hardware page by 2225 * mapping it into virtual memory and using bzero to clear 2226 * its contents. 2227 * 2228 * off and size must reside within a single page. 2229 */ 2230 static void 2231 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2232 { 2233 vm_offset_t va; 2234 2235 /* XXX KASSERT off and size are within a single page? */ 2236 2237 mtx_lock(&zero_page_mutex); 2238 va = zero_page_va; 2239 2240 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2241 bzero((caddr_t)va + off, size); 2242 mmu_booke_kremove(mmu, va); 2243 2244 mtx_unlock(&zero_page_mutex); 2245 } 2246 2247 /* 2248 * mmu_booke_zero_page zeros the specified hardware page. 2249 */ 2250 static void 2251 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2252 { 2253 vm_offset_t off, va; 2254 2255 mtx_lock(&zero_page_mutex); 2256 va = zero_page_va; 2257 2258 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2259 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2260 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 2261 mmu_booke_kremove(mmu, va); 2262 2263 mtx_unlock(&zero_page_mutex); 2264 } 2265 2266 /* 2267 * mmu_booke_copy_page copies the specified (machine independent) page by 2268 * mapping the page into virtual memory and using memcopy to copy the page, 2269 * one machine dependent page at a time. 2270 */ 2271 static void 2272 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2273 { 2274 vm_offset_t sva, dva; 2275 2276 sva = copy_page_src_va; 2277 dva = copy_page_dst_va; 2278 2279 mtx_lock(©_page_mutex); 2280 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2281 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2282 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2283 mmu_booke_kremove(mmu, dva); 2284 mmu_booke_kremove(mmu, sva); 2285 mtx_unlock(©_page_mutex); 2286 } 2287 2288 static inline void 2289 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2290 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2291 { 2292 void *a_cp, *b_cp; 2293 vm_offset_t a_pg_offset, b_pg_offset; 2294 int cnt; 2295 2296 mtx_lock(©_page_mutex); 2297 while (xfersize > 0) { 2298 a_pg_offset = a_offset & PAGE_MASK; 2299 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2300 mmu_booke_kenter(mmu, copy_page_src_va, 2301 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2302 a_cp = (char *)copy_page_src_va + a_pg_offset; 2303 b_pg_offset = b_offset & PAGE_MASK; 2304 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2305 mmu_booke_kenter(mmu, copy_page_dst_va, 2306 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2307 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2308 bcopy(a_cp, b_cp, cnt); 2309 mmu_booke_kremove(mmu, copy_page_dst_va); 2310 mmu_booke_kremove(mmu, copy_page_src_va); 2311 a_offset += cnt; 2312 b_offset += cnt; 2313 xfersize -= cnt; 2314 } 2315 mtx_unlock(©_page_mutex); 2316 } 2317 2318 /* 2319 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2320 * into virtual memory and using bzero to clear its contents. This is intended 2321 * to be called from the vm_pagezero process only and outside of Giant. No 2322 * lock is required. 2323 */ 2324 static void 2325 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2326 { 2327 vm_offset_t va; 2328 2329 va = zero_page_idle_va; 2330 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2331 bzero((caddr_t)va, PAGE_SIZE); 2332 mmu_booke_kremove(mmu, va); 2333 } 2334 2335 static vm_offset_t 2336 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2337 { 2338 vm_paddr_t paddr; 2339 vm_offset_t qaddr; 2340 uint32_t flags; 2341 pte_t *pte; 2342 2343 paddr = VM_PAGE_TO_PHYS(m); 2344 2345 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2346 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 2347 flags |= PTE_PS_4KB; 2348 2349 critical_enter(); 2350 qaddr = PCPU_GET(qmap_addr); 2351 2352 pte = pte_find(mmu, kernel_pmap, qaddr); 2353 2354 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2355 2356 /* 2357 * XXX: tlbivax is broadcast to other cores, but qaddr should 2358 * not be present in other TLBs. Is there a better instruction 2359 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2360 */ 2361 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2362 __asm __volatile("isync; msync"); 2363 2364 *pte = PTE_RPN_FROM_PA(paddr) | flags; 2365 2366 /* Flush the real memory from the instruction cache. */ 2367 if ((flags & (PTE_I | PTE_G)) == 0) 2368 __syncicache((void *)qaddr, PAGE_SIZE); 2369 2370 return (qaddr); 2371 } 2372 2373 static void 2374 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2375 { 2376 pte_t *pte; 2377 2378 pte = pte_find(mmu, kernel_pmap, addr); 2379 2380 KASSERT(PCPU_GET(qmap_addr) == addr, 2381 ("mmu_booke_quick_remove_page: invalid address")); 2382 KASSERT(*pte != 0, 2383 ("mmu_booke_quick_remove_page: PTE not in use")); 2384 2385 *pte = 0; 2386 critical_exit(); 2387 } 2388 2389 /* 2390 * Return whether or not the specified physical page was modified 2391 * in any of physical maps. 2392 */ 2393 static boolean_t 2394 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2395 { 2396 pte_t *pte; 2397 pv_entry_t pv; 2398 boolean_t rv; 2399 2400 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2401 ("mmu_booke_is_modified: page %p is not managed", m)); 2402 rv = FALSE; 2403 2404 /* 2405 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2406 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2407 * is clear, no PTEs can be modified. 2408 */ 2409 VM_OBJECT_ASSERT_WLOCKED(m->object); 2410 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2411 return (rv); 2412 rw_wlock(&pvh_global_lock); 2413 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2414 PMAP_LOCK(pv->pv_pmap); 2415 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2416 PTE_ISVALID(pte)) { 2417 if (PTE_ISMODIFIED(pte)) 2418 rv = TRUE; 2419 } 2420 PMAP_UNLOCK(pv->pv_pmap); 2421 if (rv) 2422 break; 2423 } 2424 rw_wunlock(&pvh_global_lock); 2425 return (rv); 2426 } 2427 2428 /* 2429 * Return whether or not the specified virtual address is eligible 2430 * for prefault. 2431 */ 2432 static boolean_t 2433 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2434 { 2435 2436 return (FALSE); 2437 } 2438 2439 /* 2440 * Return whether or not the specified physical page was referenced 2441 * in any physical maps. 2442 */ 2443 static boolean_t 2444 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2445 { 2446 pte_t *pte; 2447 pv_entry_t pv; 2448 boolean_t rv; 2449 2450 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2451 ("mmu_booke_is_referenced: page %p is not managed", m)); 2452 rv = FALSE; 2453 rw_wlock(&pvh_global_lock); 2454 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2455 PMAP_LOCK(pv->pv_pmap); 2456 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2457 PTE_ISVALID(pte)) { 2458 if (PTE_ISREFERENCED(pte)) 2459 rv = TRUE; 2460 } 2461 PMAP_UNLOCK(pv->pv_pmap); 2462 if (rv) 2463 break; 2464 } 2465 rw_wunlock(&pvh_global_lock); 2466 return (rv); 2467 } 2468 2469 /* 2470 * Clear the modify bits on the specified physical page. 2471 */ 2472 static void 2473 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2474 { 2475 pte_t *pte; 2476 pv_entry_t pv; 2477 2478 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2479 ("mmu_booke_clear_modify: page %p is not managed", m)); 2480 VM_OBJECT_ASSERT_WLOCKED(m->object); 2481 KASSERT(!vm_page_xbusied(m), 2482 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2483 2484 /* 2485 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2486 * If the object containing the page is locked and the page is not 2487 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2488 */ 2489 if ((m->aflags & PGA_WRITEABLE) == 0) 2490 return; 2491 rw_wlock(&pvh_global_lock); 2492 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2493 PMAP_LOCK(pv->pv_pmap); 2494 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2495 PTE_ISVALID(pte)) { 2496 mtx_lock_spin(&tlbivax_mutex); 2497 tlb_miss_lock(); 2498 2499 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2500 tlb0_flush_entry(pv->pv_va); 2501 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2502 PTE_REFERENCED); 2503 } 2504 2505 tlb_miss_unlock(); 2506 mtx_unlock_spin(&tlbivax_mutex); 2507 } 2508 PMAP_UNLOCK(pv->pv_pmap); 2509 } 2510 rw_wunlock(&pvh_global_lock); 2511 } 2512 2513 /* 2514 * Return a count of reference bits for a page, clearing those bits. 2515 * It is not necessary for every reference bit to be cleared, but it 2516 * is necessary that 0 only be returned when there are truly no 2517 * reference bits set. 2518 * 2519 * XXX: The exact number of bits to check and clear is a matter that 2520 * should be tested and standardized at some point in the future for 2521 * optimal aging of shared pages. 2522 */ 2523 static int 2524 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2525 { 2526 pte_t *pte; 2527 pv_entry_t pv; 2528 int count; 2529 2530 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2531 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2532 count = 0; 2533 rw_wlock(&pvh_global_lock); 2534 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2535 PMAP_LOCK(pv->pv_pmap); 2536 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2537 PTE_ISVALID(pte)) { 2538 if (PTE_ISREFERENCED(pte)) { 2539 mtx_lock_spin(&tlbivax_mutex); 2540 tlb_miss_lock(); 2541 2542 tlb0_flush_entry(pv->pv_va); 2543 *pte &= ~PTE_REFERENCED; 2544 2545 tlb_miss_unlock(); 2546 mtx_unlock_spin(&tlbivax_mutex); 2547 2548 if (++count > 4) { 2549 PMAP_UNLOCK(pv->pv_pmap); 2550 break; 2551 } 2552 } 2553 } 2554 PMAP_UNLOCK(pv->pv_pmap); 2555 } 2556 rw_wunlock(&pvh_global_lock); 2557 return (count); 2558 } 2559 2560 /* 2561 * Clear the wired attribute from the mappings for the specified range of 2562 * addresses in the given pmap. Every valid mapping within that range must 2563 * have the wired attribute set. In contrast, invalid mappings cannot have 2564 * the wired attribute set, so they are ignored. 2565 * 2566 * The wired attribute of the page table entry is not a hardware feature, so 2567 * there is no need to invalidate any TLB entries. 2568 */ 2569 static void 2570 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2571 { 2572 vm_offset_t va; 2573 pte_t *pte; 2574 2575 PMAP_LOCK(pmap); 2576 for (va = sva; va < eva; va += PAGE_SIZE) { 2577 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2578 PTE_ISVALID(pte)) { 2579 if (!PTE_ISWIRED(pte)) 2580 panic("mmu_booke_unwire: pte %p isn't wired", 2581 pte); 2582 *pte &= ~PTE_WIRED; 2583 pmap->pm_stats.wired_count--; 2584 } 2585 } 2586 PMAP_UNLOCK(pmap); 2587 2588 } 2589 2590 /* 2591 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2592 * page. This count may be changed upwards or downwards in the future; it is 2593 * only necessary that true be returned for a small subset of pmaps for proper 2594 * page aging. 2595 */ 2596 static boolean_t 2597 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2598 { 2599 pv_entry_t pv; 2600 int loops; 2601 boolean_t rv; 2602 2603 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2604 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2605 loops = 0; 2606 rv = FALSE; 2607 rw_wlock(&pvh_global_lock); 2608 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2609 if (pv->pv_pmap == pmap) { 2610 rv = TRUE; 2611 break; 2612 } 2613 if (++loops >= 16) 2614 break; 2615 } 2616 rw_wunlock(&pvh_global_lock); 2617 return (rv); 2618 } 2619 2620 /* 2621 * Return the number of managed mappings to the given physical page that are 2622 * wired. 2623 */ 2624 static int 2625 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2626 { 2627 pv_entry_t pv; 2628 pte_t *pte; 2629 int count = 0; 2630 2631 if ((m->oflags & VPO_UNMANAGED) != 0) 2632 return (count); 2633 rw_wlock(&pvh_global_lock); 2634 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2635 PMAP_LOCK(pv->pv_pmap); 2636 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2637 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2638 count++; 2639 PMAP_UNLOCK(pv->pv_pmap); 2640 } 2641 rw_wunlock(&pvh_global_lock); 2642 return (count); 2643 } 2644 2645 static int 2646 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2647 { 2648 int i; 2649 vm_offset_t va; 2650 2651 /* 2652 * This currently does not work for entries that 2653 * overlap TLB1 entries. 2654 */ 2655 for (i = 0; i < tlb1_idx; i ++) { 2656 if (tlb1_iomapped(i, pa, size, &va) == 0) 2657 return (0); 2658 } 2659 2660 return (EFAULT); 2661 } 2662 2663 void 2664 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2665 { 2666 vm_paddr_t ppa; 2667 vm_offset_t ofs; 2668 vm_size_t gran; 2669 2670 /* Minidumps are based on virtual memory addresses. */ 2671 if (do_minidump) { 2672 *va = (void *)(vm_offset_t)pa; 2673 return; 2674 } 2675 2676 /* Raw physical memory dumps don't have a virtual address. */ 2677 /* We always map a 256MB page at 256M. */ 2678 gran = 256 * 1024 * 1024; 2679 ppa = pa & ~(gran - 1); 2680 ofs = pa - ppa; 2681 *va = (void *)gran; 2682 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2683 2684 if (sz > (gran - ofs)) 2685 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2686 _TLB_ENTRY_IO); 2687 } 2688 2689 void 2690 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2691 { 2692 vm_paddr_t ppa; 2693 vm_offset_t ofs; 2694 vm_size_t gran; 2695 2696 /* Minidumps are based on virtual memory addresses. */ 2697 /* Nothing to do... */ 2698 if (do_minidump) 2699 return; 2700 2701 /* Raw physical memory dumps don't have a virtual address. */ 2702 tlb1_idx--; 2703 tlb1[tlb1_idx].mas1 = 0; 2704 tlb1[tlb1_idx].mas2 = 0; 2705 tlb1[tlb1_idx].mas3 = 0; 2706 tlb1_write_entry(tlb1_idx); 2707 2708 gran = 256 * 1024 * 1024; 2709 ppa = pa & ~(gran - 1); 2710 ofs = pa - ppa; 2711 if (sz > (gran - ofs)) { 2712 tlb1_idx--; 2713 tlb1[tlb1_idx].mas1 = 0; 2714 tlb1[tlb1_idx].mas2 = 0; 2715 tlb1[tlb1_idx].mas3 = 0; 2716 tlb1_write_entry(tlb1_idx); 2717 } 2718 } 2719 2720 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2721 2722 void 2723 mmu_booke_scan_init(mmu_t mmu) 2724 { 2725 vm_offset_t va; 2726 pte_t *pte; 2727 int i; 2728 2729 if (!do_minidump) { 2730 /* Initialize phys. segments for dumpsys(). */ 2731 memset(&dump_map, 0, sizeof(dump_map)); 2732 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2733 &availmem_regions_sz); 2734 for (i = 0; i < physmem_regions_sz; i++) { 2735 dump_map[i].pa_start = physmem_regions[i].mr_start; 2736 dump_map[i].pa_size = physmem_regions[i].mr_size; 2737 } 2738 return; 2739 } 2740 2741 /* Virtual segments for minidumps: */ 2742 memset(&dump_map, 0, sizeof(dump_map)); 2743 2744 /* 1st: kernel .data and .bss. */ 2745 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2746 dump_map[0].pa_size = 2747 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2748 2749 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2750 dump_map[1].pa_start = data_start; 2751 dump_map[1].pa_size = data_end - data_start; 2752 2753 /* 3rd: kernel VM. */ 2754 va = dump_map[1].pa_start + dump_map[1].pa_size; 2755 /* Find start of next chunk (from va). */ 2756 while (va < virtual_end) { 2757 /* Don't dump the buffer cache. */ 2758 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2759 va = kmi.buffer_eva; 2760 continue; 2761 } 2762 pte = pte_find(mmu, kernel_pmap, va); 2763 if (pte != NULL && PTE_ISVALID(pte)) 2764 break; 2765 va += PAGE_SIZE; 2766 } 2767 if (va < virtual_end) { 2768 dump_map[2].pa_start = va; 2769 va += PAGE_SIZE; 2770 /* Find last page in chunk. */ 2771 while (va < virtual_end) { 2772 /* Don't run into the buffer cache. */ 2773 if (va == kmi.buffer_sva) 2774 break; 2775 pte = pte_find(mmu, kernel_pmap, va); 2776 if (pte == NULL || !PTE_ISVALID(pte)) 2777 break; 2778 va += PAGE_SIZE; 2779 } 2780 dump_map[2].pa_size = va - dump_map[2].pa_start; 2781 } 2782 } 2783 2784 /* 2785 * Map a set of physical memory pages into the kernel virtual address space. 2786 * Return a pointer to where it is mapped. This routine is intended to be used 2787 * for mapping device memory, NOT real memory. 2788 */ 2789 static void * 2790 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2791 { 2792 2793 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2794 } 2795 2796 static void * 2797 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2798 { 2799 void *res; 2800 uintptr_t va, tmpva; 2801 vm_size_t sz; 2802 int i; 2803 2804 /* 2805 * Check if this is premapped in TLB1. Note: this should probably also 2806 * check whether a sequence of TLB1 entries exist that match the 2807 * requirement, but now only checks the easy case. 2808 */ 2809 if (ma == VM_MEMATTR_DEFAULT) { 2810 for (i = 0; i < tlb1_idx; i++) { 2811 if (!(tlb1[i].mas1 & MAS1_VALID)) 2812 continue; 2813 if (pa >= tlb1[i].phys && 2814 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2815 return (void *)(tlb1[i].virt + 2816 (vm_offset_t)(pa - tlb1[i].phys)); 2817 } 2818 } 2819 2820 size = roundup(size, PAGE_SIZE); 2821 2822 /* 2823 * The device mapping area is between VM_MAXUSER_ADDRESS and 2824 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 2825 */ 2826 #ifdef SPARSE_MAPDEV 2827 /* 2828 * With a sparse mapdev, align to the largest starting region. This 2829 * could feasibly be optimized for a 'best-fit' alignment, but that 2830 * calculation could be very costly. 2831 */ 2832 do { 2833 tmpva = tlb1_map_base; 2834 va = roundup(tlb1_map_base, 1 << flsl(size)); 2835 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 2836 #else 2837 va = atomic_fetchadd_int(&tlb1_map_base, size); 2838 #endif 2839 res = (void *)va; 2840 2841 do { 2842 sz = 1 << (ilog2(size) & ~1); 2843 if (va % sz != 0) { 2844 do { 2845 sz >>= 2; 2846 } while (va % sz != 0); 2847 } 2848 if (bootverbose) 2849 printf("Wiring VA=%x to PA=%jx (size=%x), " 2850 "using TLB1[%d]\n", va, (uintmax_t)pa, sz, tlb1_idx); 2851 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2852 size -= sz; 2853 pa += sz; 2854 va += sz; 2855 } while (size > 0); 2856 2857 return (res); 2858 } 2859 2860 /* 2861 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2862 */ 2863 static void 2864 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2865 { 2866 #ifdef SUPPORTS_SHRINKING_TLB1 2867 vm_offset_t base, offset; 2868 2869 /* 2870 * Unmap only if this is inside kernel virtual space. 2871 */ 2872 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2873 base = trunc_page(va); 2874 offset = va & PAGE_MASK; 2875 size = roundup(offset + size, PAGE_SIZE); 2876 kva_free(base, size); 2877 } 2878 #endif 2879 } 2880 2881 /* 2882 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2883 * specified pmap. This eliminates the blast of soft faults on process startup 2884 * and immediately after an mmap. 2885 */ 2886 static void 2887 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2888 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2889 { 2890 2891 VM_OBJECT_ASSERT_WLOCKED(object); 2892 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2893 ("mmu_booke_object_init_pt: non-device object")); 2894 } 2895 2896 /* 2897 * Perform the pmap work for mincore. 2898 */ 2899 static int 2900 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2901 vm_paddr_t *locked_pa) 2902 { 2903 2904 /* XXX: this should be implemented at some point */ 2905 return (0); 2906 } 2907 2908 static int 2909 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 2910 vm_memattr_t mode) 2911 { 2912 vm_offset_t va; 2913 pte_t *pte; 2914 int i, j; 2915 2916 /* Check TLB1 mappings */ 2917 for (i = 0; i < tlb1_idx; i++) { 2918 if (!(tlb1[i].mas1 & MAS1_VALID)) 2919 continue; 2920 if (addr >= tlb1[i].virt && addr < tlb1[i].virt + tlb1[i].size) 2921 break; 2922 } 2923 if (i < tlb1_idx) { 2924 /* Only allow full mappings to be modified for now. */ 2925 /* Validate the range. */ 2926 for (j = i, va = addr; va < addr + sz; va += tlb1[j].size, j++) { 2927 if (va != tlb1[j].virt || (sz - (va - addr) < tlb1[j].size)) 2928 return (EINVAL); 2929 } 2930 for (va = addr; va < addr + sz; va += tlb1[i].size, i++) { 2931 tlb1[i].mas2 &= ~MAS2_WIMGE_MASK; 2932 tlb1[i].mas2 |= tlb_calc_wimg(tlb1[i].phys, mode); 2933 2934 /* 2935 * Write it out to the TLB. Should really re-sync with other 2936 * cores. 2937 */ 2938 tlb1_write_entry(i); 2939 } 2940 return (0); 2941 } 2942 2943 /* Not in TLB1, try through pmap */ 2944 /* First validate the range. */ 2945 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2946 pte = pte_find(mmu, kernel_pmap, va); 2947 if (pte == NULL || !PTE_ISVALID(pte)) 2948 return (EINVAL); 2949 } 2950 2951 mtx_lock_spin(&tlbivax_mutex); 2952 tlb_miss_lock(); 2953 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2954 pte = pte_find(mmu, kernel_pmap, va); 2955 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2956 *pte |= tlb_calc_wimg(PTE_PA(pte), mode << PTE_MAS2_SHIFT); 2957 tlb0_flush_entry(va); 2958 } 2959 tlb_miss_unlock(); 2960 mtx_unlock_spin(&tlbivax_mutex); 2961 2962 return (pte_vatopa(mmu, kernel_pmap, va)); 2963 } 2964 2965 /**************************************************************************/ 2966 /* TID handling */ 2967 /**************************************************************************/ 2968 2969 /* 2970 * Allocate a TID. If necessary, steal one from someone else. 2971 * The new TID is flushed from the TLB before returning. 2972 */ 2973 static tlbtid_t 2974 tid_alloc(pmap_t pmap) 2975 { 2976 tlbtid_t tid; 2977 int thiscpu; 2978 2979 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2980 2981 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2982 2983 thiscpu = PCPU_GET(cpuid); 2984 2985 tid = PCPU_GET(tid_next); 2986 if (tid > TID_MAX) 2987 tid = TID_MIN; 2988 PCPU_SET(tid_next, tid + 1); 2989 2990 /* If we are stealing TID then clear the relevant pmap's field */ 2991 if (tidbusy[thiscpu][tid] != NULL) { 2992 2993 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2994 2995 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2996 2997 /* Flush all entries from TLB0 matching this TID. */ 2998 tid_flush(tid); 2999 } 3000 3001 tidbusy[thiscpu][tid] = pmap; 3002 pmap->pm_tid[thiscpu] = tid; 3003 __asm __volatile("msync; isync"); 3004 3005 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3006 PCPU_GET(tid_next)); 3007 3008 return (tid); 3009 } 3010 3011 /**************************************************************************/ 3012 /* TLB0 handling */ 3013 /**************************************************************************/ 3014 3015 static void 3016 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3017 uint32_t mas7) 3018 { 3019 int as; 3020 char desc[3]; 3021 tlbtid_t tid; 3022 vm_size_t size; 3023 unsigned int tsize; 3024 3025 desc[2] = '\0'; 3026 if (mas1 & MAS1_VALID) 3027 desc[0] = 'V'; 3028 else 3029 desc[0] = ' '; 3030 3031 if (mas1 & MAS1_IPROT) 3032 desc[1] = 'P'; 3033 else 3034 desc[1] = ' '; 3035 3036 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3037 tid = MAS1_GETTID(mas1); 3038 3039 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3040 size = 0; 3041 if (tsize) 3042 size = tsize2size(tsize); 3043 3044 debugf("%3d: (%s) [AS=%d] " 3045 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 3046 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3047 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 3048 } 3049 3050 /* Convert TLB0 va and way number to tlb0[] table index. */ 3051 static inline unsigned int 3052 tlb0_tableidx(vm_offset_t va, unsigned int way) 3053 { 3054 unsigned int idx; 3055 3056 idx = (way * TLB0_ENTRIES_PER_WAY); 3057 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3058 return (idx); 3059 } 3060 3061 /* 3062 * Invalidate TLB0 entry. 3063 */ 3064 static inline void 3065 tlb0_flush_entry(vm_offset_t va) 3066 { 3067 3068 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3069 3070 mtx_assert(&tlbivax_mutex, MA_OWNED); 3071 3072 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3073 __asm __volatile("isync; msync"); 3074 __asm __volatile("tlbsync; msync"); 3075 3076 CTR1(KTR_PMAP, "%s: e", __func__); 3077 } 3078 3079 /* Print out contents of the MAS registers for each TLB0 entry */ 3080 void 3081 tlb0_print_tlbentries(void) 3082 { 3083 uint32_t mas0, mas1, mas2, mas3, mas7; 3084 int entryidx, way, idx; 3085 3086 debugf("TLB0 entries:\n"); 3087 for (way = 0; way < TLB0_WAYS; way ++) 3088 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3089 3090 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3091 mtspr(SPR_MAS0, mas0); 3092 __asm __volatile("isync"); 3093 3094 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3095 mtspr(SPR_MAS2, mas2); 3096 3097 __asm __volatile("isync; tlbre"); 3098 3099 mas1 = mfspr(SPR_MAS1); 3100 mas2 = mfspr(SPR_MAS2); 3101 mas3 = mfspr(SPR_MAS3); 3102 mas7 = mfspr(SPR_MAS7); 3103 3104 idx = tlb0_tableidx(mas2, way); 3105 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3106 } 3107 } 3108 3109 /**************************************************************************/ 3110 /* TLB1 handling */ 3111 /**************************************************************************/ 3112 3113 /* 3114 * TLB1 mapping notes: 3115 * 3116 * TLB1[0] Kernel text and data. 3117 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3118 * windows, other devices mappings. 3119 */ 3120 3121 /* 3122 * Write given entry to TLB1 hardware. 3123 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3124 */ 3125 static void 3126 tlb1_write_entry(unsigned int idx) 3127 { 3128 uint32_t mas0; 3129 3130 //debugf("tlb1_write_entry: s\n"); 3131 3132 /* Select entry */ 3133 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3134 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3135 3136 mtspr(SPR_MAS0, mas0); 3137 __asm __volatile("isync"); 3138 mtspr(SPR_MAS1, tlb1[idx].mas1); 3139 __asm __volatile("isync"); 3140 mtspr(SPR_MAS2, tlb1[idx].mas2); 3141 __asm __volatile("isync"); 3142 mtspr(SPR_MAS3, tlb1[idx].mas3); 3143 __asm __volatile("isync"); 3144 switch ((mfpvr() >> 16) & 0xFFFF) { 3145 case FSL_E500mc: 3146 case FSL_E5500: 3147 mtspr(SPR_MAS8, 0); 3148 __asm __volatile("isync"); 3149 /* FALLTHROUGH */ 3150 case FSL_E500v2: 3151 mtspr(SPR_MAS7, tlb1[idx].mas7); 3152 __asm __volatile("isync"); 3153 break; 3154 default: 3155 break; 3156 } 3157 3158 __asm __volatile("tlbwe; isync; msync"); 3159 3160 //debugf("tlb1_write_entry: e\n"); 3161 } 3162 3163 /* 3164 * Return the largest uint value log such that 2^log <= num. 3165 */ 3166 static unsigned int 3167 ilog2(unsigned int num) 3168 { 3169 int lz; 3170 3171 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3172 return (31 - lz); 3173 } 3174 3175 /* 3176 * Convert TLB TSIZE value to mapped region size. 3177 */ 3178 static vm_size_t 3179 tsize2size(unsigned int tsize) 3180 { 3181 3182 /* 3183 * size = 4^tsize KB 3184 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3185 */ 3186 3187 return ((1 << (2 * tsize)) * 1024); 3188 } 3189 3190 /* 3191 * Convert region size (must be power of 4) to TLB TSIZE value. 3192 */ 3193 static unsigned int 3194 size2tsize(vm_size_t size) 3195 { 3196 3197 return (ilog2(size) / 2 - 5); 3198 } 3199 3200 /* 3201 * Register permanent kernel mapping in TLB1. 3202 * 3203 * Entries are created starting from index 0 (current free entry is 3204 * kept in tlb1_idx) and are not supposed to be invalidated. 3205 */ 3206 int 3207 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3208 uint32_t flags) 3209 { 3210 uint32_t ts, tid; 3211 int tsize, index; 3212 3213 index = atomic_fetchadd_int(&tlb1_idx, 1); 3214 if (index >= TLB1_ENTRIES) { 3215 printf("tlb1_set_entry: TLB1 full!\n"); 3216 return (-1); 3217 } 3218 3219 /* Convert size to TSIZE */ 3220 tsize = size2tsize(size); 3221 3222 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3223 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3224 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3225 3226 /* 3227 * Atomicity is preserved by the atomic increment above since nothing 3228 * is ever removed from tlb1. 3229 */ 3230 3231 tlb1[index].phys = pa; 3232 tlb1[index].virt = va; 3233 tlb1[index].size = size; 3234 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3235 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3236 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3237 3238 /* Set supervisor RWX permission bits */ 3239 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3240 tlb1[index].mas7 = (pa >> 32) & MAS7_RPN; 3241 3242 tlb1_write_entry(index); 3243 3244 /* 3245 * XXX in general TLB1 updates should be propagated between CPUs, 3246 * since current design assumes to have the same TLB1 set-up on all 3247 * cores. 3248 */ 3249 return (0); 3250 } 3251 3252 /* 3253 * Map in contiguous RAM region into the TLB1 using maximum of 3254 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3255 * 3256 * If necessary round up last entry size and return total size 3257 * used by all allocated entries. 3258 */ 3259 vm_size_t 3260 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3261 { 3262 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3263 vm_size_t mapped, pgsz, base, mask; 3264 int idx, nents; 3265 3266 /* Round up to the next 1M */ 3267 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3268 3269 mapped = 0; 3270 idx = 0; 3271 base = va; 3272 pgsz = 64*1024*1024; 3273 while (mapped < size) { 3274 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3275 while (pgsz > (size - mapped)) 3276 pgsz >>= 2; 3277 pgs[idx++] = pgsz; 3278 mapped += pgsz; 3279 } 3280 3281 /* We under-map. Correct for this. */ 3282 if (mapped < size) { 3283 while (pgs[idx - 1] == pgsz) { 3284 idx--; 3285 mapped -= pgsz; 3286 } 3287 /* XXX We may increase beyond out starting point. */ 3288 pgsz <<= 2; 3289 pgs[idx++] = pgsz; 3290 mapped += pgsz; 3291 } 3292 } 3293 3294 nents = idx; 3295 mask = pgs[0] - 1; 3296 /* Align address to the boundary */ 3297 if (va & mask) { 3298 va = (va + mask) & ~mask; 3299 pa = (pa + mask) & ~mask; 3300 } 3301 3302 for (idx = 0; idx < nents; idx++) { 3303 pgsz = pgs[idx]; 3304 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3305 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3306 pa += pgsz; 3307 va += pgsz; 3308 } 3309 3310 mapped = (va - base); 3311 #ifdef __powerpc64__ 3312 printf("mapped size 0x%016lx (wasted space 0x%16lx)\n", 3313 #else 3314 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3315 #endif 3316 mapped, mapped - size); 3317 return (mapped); 3318 } 3319 3320 /* 3321 * TLB1 initialization routine, to be called after the very first 3322 * assembler level setup done in locore.S. 3323 */ 3324 void 3325 tlb1_init() 3326 { 3327 uint32_t mas0, mas1, mas2, mas3, mas7; 3328 uint32_t tsz; 3329 int i; 3330 3331 tlb1_idx = 1; 3332 3333 tlb1_get_tlbconf(); 3334 3335 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3336 mtspr(SPR_MAS0, mas0); 3337 __asm __volatile("isync; tlbre"); 3338 3339 mas1 = mfspr(SPR_MAS1); 3340 mas2 = mfspr(SPR_MAS2); 3341 mas3 = mfspr(SPR_MAS3); 3342 mas7 = mfspr(SPR_MAS7); 3343 3344 tlb1[0].mas1 = mas1; 3345 tlb1[0].mas2 = mfspr(SPR_MAS2); 3346 tlb1[0].mas3 = mas3; 3347 tlb1[0].mas7 = mas7; 3348 tlb1[0].virt = mas2 & MAS2_EPN_MASK; 3349 tlb1[0].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3350 (mas3 & MAS3_RPN); 3351 3352 kernload = tlb1[0].phys; 3353 3354 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3355 tlb1[0].size = (tsz > 0) ? tsize2size(tsz) : 0; 3356 kernsize += tlb1[0].size; 3357 3358 #ifdef SMP 3359 bp_ntlb1s = tlb1_idx; 3360 #endif 3361 3362 /* Purge the remaining entries */ 3363 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3364 tlb1_write_entry(i); 3365 3366 /* Setup TLB miss defaults */ 3367 set_mas4_defaults(); 3368 } 3369 3370 vm_offset_t 3371 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3372 { 3373 vm_paddr_t pa_base; 3374 vm_offset_t va, sz; 3375 int i; 3376 3377 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3378 3379 for (i = 0; i < tlb1_idx; i++) { 3380 if (!(tlb1[i].mas1 & MAS1_VALID)) 3381 continue; 3382 if (pa >= tlb1[i].phys && (pa + size) <= 3383 (tlb1[i].phys + tlb1[i].size)) 3384 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3385 } 3386 3387 pa_base = rounddown(pa, PAGE_SIZE); 3388 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3389 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3390 va = tlb1_map_base + (pa - pa_base); 3391 3392 do { 3393 sz = 1 << (ilog2(size) & ~1); 3394 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3395 size -= sz; 3396 pa_base += sz; 3397 tlb1_map_base += sz; 3398 } while (size > 0); 3399 3400 #ifdef SMP 3401 bp_ntlb1s = tlb1_idx; 3402 #endif 3403 3404 return (va); 3405 } 3406 3407 /* 3408 * Setup MAS4 defaults. 3409 * These values are loaded to MAS0-2 on a TLB miss. 3410 */ 3411 static void 3412 set_mas4_defaults(void) 3413 { 3414 uint32_t mas4; 3415 3416 /* Defaults: TLB0, PID0, TSIZED=4K */ 3417 mas4 = MAS4_TLBSELD0; 3418 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3419 #ifdef SMP 3420 mas4 |= MAS4_MD; 3421 #endif 3422 mtspr(SPR_MAS4, mas4); 3423 __asm __volatile("isync"); 3424 } 3425 3426 /* 3427 * Print out contents of the MAS registers for each TLB1 entry 3428 */ 3429 void 3430 tlb1_print_tlbentries(void) 3431 { 3432 uint32_t mas0, mas1, mas2, mas3, mas7; 3433 int i; 3434 3435 debugf("TLB1 entries:\n"); 3436 for (i = 0; i < TLB1_ENTRIES; i++) { 3437 3438 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3439 mtspr(SPR_MAS0, mas0); 3440 3441 __asm __volatile("isync; tlbre"); 3442 3443 mas1 = mfspr(SPR_MAS1); 3444 mas2 = mfspr(SPR_MAS2); 3445 mas3 = mfspr(SPR_MAS3); 3446 mas7 = mfspr(SPR_MAS7); 3447 3448 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3449 } 3450 } 3451 3452 /* 3453 * Print out contents of the in-ram tlb1 table. 3454 */ 3455 void 3456 tlb1_print_entries(void) 3457 { 3458 int i; 3459 3460 debugf("tlb1[] table entries:\n"); 3461 for (i = 0; i < TLB1_ENTRIES; i++) 3462 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 3463 tlb1[i].mas7); 3464 } 3465 3466 /* 3467 * Return 0 if the physical IO range is encompassed by one of the 3468 * the TLB1 entries, otherwise return related error code. 3469 */ 3470 static int 3471 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3472 { 3473 uint32_t prot; 3474 vm_paddr_t pa_start; 3475 vm_paddr_t pa_end; 3476 unsigned int entry_tsize; 3477 vm_size_t entry_size; 3478 3479 *va = (vm_offset_t)NULL; 3480 3481 /* Skip invalid entries */ 3482 if (!(tlb1[i].mas1 & MAS1_VALID)) 3483 return (EINVAL); 3484 3485 /* 3486 * The entry must be cache-inhibited, guarded, and r/w 3487 * so it can function as an i/o page 3488 */ 3489 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3490 if (prot != (MAS2_I | MAS2_G)) 3491 return (EPERM); 3492 3493 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3494 if (prot != (MAS3_SR | MAS3_SW)) 3495 return (EPERM); 3496 3497 /* The address should be within the entry range. */ 3498 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3499 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3500 3501 entry_size = tsize2size(entry_tsize); 3502 pa_start = (((vm_paddr_t)tlb1[i].mas7 & MAS7_RPN) << 32) | 3503 (tlb1[i].mas3 & MAS3_RPN); 3504 pa_end = pa_start + entry_size; 3505 3506 if ((pa < pa_start) || ((pa + size) > pa_end)) 3507 return (ERANGE); 3508 3509 /* Return virtual address of this mapping. */ 3510 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3511 return (0); 3512 } 3513 3514 /* 3515 * Invalidate all TLB0 entries which match the given TID. Note this is 3516 * dedicated for cases when invalidations should NOT be propagated to other 3517 * CPUs. 3518 */ 3519 static void 3520 tid_flush(tlbtid_t tid) 3521 { 3522 register_t msr; 3523 uint32_t mas0, mas1, mas2; 3524 int entry, way; 3525 3526 3527 /* Don't evict kernel translations */ 3528 if (tid == TID_KERNEL) 3529 return; 3530 3531 msr = mfmsr(); 3532 __asm __volatile("wrteei 0"); 3533 3534 for (way = 0; way < TLB0_WAYS; way++) 3535 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3536 3537 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3538 mtspr(SPR_MAS0, mas0); 3539 __asm __volatile("isync"); 3540 3541 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3542 mtspr(SPR_MAS2, mas2); 3543 3544 __asm __volatile("isync; tlbre"); 3545 3546 mas1 = mfspr(SPR_MAS1); 3547 3548 if (!(mas1 & MAS1_VALID)) 3549 continue; 3550 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3551 continue; 3552 mas1 &= ~MAS1_VALID; 3553 mtspr(SPR_MAS1, mas1); 3554 __asm __volatile("isync; tlbwe; isync; msync"); 3555 } 3556 mtmsr(msr); 3557 } 3558