1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * 32-bit pmap: 40 * Virtual address space layout: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA 47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 51 * 52 * 64-bit pmap: 53 * Virtual address space layout: 54 * ----------------------------- 55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process 56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries 57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region 58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack 59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved 60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data 61 * endkernel - msgbufp-1 : flat device tree 62 * msgbufp - kernel_pdir-1 : message buffer 63 * kernel_pdir - kernel_pp2d-1 : kernel page directory 64 * kernel_pp2d - . : kernel pointers to page directory 65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy 66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs 67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables 68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space 69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region 70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region 71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map 72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map 73 * - 0xffff_ffff_ffff_ffff : device direct map 74 */ 75 76 #include <sys/cdefs.h> 77 __FBSDID("$FreeBSD$"); 78 79 #include "opt_ddb.h" 80 #include "opt_kstack_pages.h" 81 82 #include <sys/param.h> 83 #include <sys/conf.h> 84 #include <sys/malloc.h> 85 #include <sys/ktr.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 #include <sys/queue.h> 89 #include <sys/systm.h> 90 #include <sys/kernel.h> 91 #include <sys/kerneldump.h> 92 #include <sys/linker.h> 93 #include <sys/msgbuf.h> 94 #include <sys/lock.h> 95 #include <sys/mutex.h> 96 #include <sys/rwlock.h> 97 #include <sys/sched.h> 98 #include <sys/smp.h> 99 #include <sys/vmmeter.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_page.h> 104 #include <vm/vm_kern.h> 105 #include <vm/vm_pageout.h> 106 #include <vm/vm_extern.h> 107 #include <vm/vm_object.h> 108 #include <vm/vm_map.h> 109 #include <vm/vm_pager.h> 110 #include <vm/vm_phys.h> 111 #include <vm/vm_pagequeue.h> 112 #include <vm/vm_dumpset.h> 113 #include <vm/uma.h> 114 115 #include <machine/_inttypes.h> 116 #include <machine/cpu.h> 117 #include <machine/pcb.h> 118 #include <machine/platform.h> 119 120 #include <machine/tlb.h> 121 #include <machine/spr.h> 122 #include <machine/md_var.h> 123 #include <machine/mmuvar.h> 124 #include <machine/pmap.h> 125 #include <machine/pte.h> 126 127 #include <ddb/ddb.h> 128 129 #define SPARSE_MAPDEV 130 131 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */ 132 #define POW2_MAPPINGS 133 134 #ifdef DEBUG 135 #define debugf(fmt, args...) printf(fmt, ##args) 136 #else 137 #define debugf(fmt, args...) 138 #endif 139 140 #ifdef __powerpc64__ 141 #define PRI0ptrX "016lx" 142 #else 143 #define PRI0ptrX "08x" 144 #endif 145 146 #define TODO panic("%s: not implemented", __func__); 147 148 extern unsigned char _etext[]; 149 extern unsigned char _end[]; 150 151 extern uint32_t *bootinfo; 152 153 vm_paddr_t kernload; 154 vm_offset_t kernstart; 155 vm_size_t kernsize; 156 157 /* Message buffer and tables. */ 158 static vm_offset_t data_start; 159 static vm_size_t data_end; 160 161 /* Phys/avail memory regions. */ 162 static struct mem_region *availmem_regions; 163 static int availmem_regions_sz; 164 static struct mem_region *physmem_regions; 165 static int physmem_regions_sz; 166 167 #ifndef __powerpc64__ 168 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 169 static vm_offset_t zero_page_va; 170 static struct mtx zero_page_mutex; 171 172 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 173 static vm_offset_t copy_page_src_va; 174 static vm_offset_t copy_page_dst_va; 175 static struct mtx copy_page_mutex; 176 #endif 177 178 static struct mtx tlbivax_mutex; 179 180 /**************************************************************************/ 181 /* PMAP */ 182 /**************************************************************************/ 183 184 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t, 185 vm_prot_t, u_int flags, int8_t psind); 186 187 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 188 static uma_zone_t ptbl_root_zone; 189 190 /* 191 * If user pmap is processed with mmu_booke_remove and the resident count 192 * drops to 0, there are no more pages to remove, so we need not continue. 193 */ 194 #define PMAP_REMOVE_DONE(pmap) \ 195 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 196 197 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 198 extern int elf32_nxstack; 199 #endif 200 201 /**************************************************************************/ 202 /* TLB and TID handling */ 203 /**************************************************************************/ 204 205 /* Translation ID busy table */ 206 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 207 208 /* 209 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 210 * core revisions and should be read from h/w registers during early config. 211 */ 212 uint32_t tlb0_entries; 213 uint32_t tlb0_ways; 214 uint32_t tlb0_entries_per_way; 215 uint32_t tlb1_entries; 216 217 #define TLB0_ENTRIES (tlb0_entries) 218 #define TLB0_WAYS (tlb0_ways) 219 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 220 221 #define TLB1_ENTRIES (tlb1_entries) 222 223 static tlbtid_t tid_alloc(struct pmap *); 224 225 #ifdef DDB 226 #ifdef __powerpc64__ 227 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t); 228 #else 229 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 230 #endif 231 #endif 232 233 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 234 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 235 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 236 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int); 237 238 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma); 239 240 static vm_size_t tsize2size(unsigned int); 241 static unsigned int size2tsize(vm_size_t); 242 static unsigned long ilog2(unsigned long); 243 244 static void set_mas4_defaults(void); 245 246 static inline void tlb0_flush_entry(vm_offset_t); 247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 248 249 /**************************************************************************/ 250 /* Page table management */ 251 /**************************************************************************/ 252 253 static struct rwlock_padalign pvh_global_lock; 254 255 /* Data for the pv entry allocation mechanism */ 256 static uma_zone_t pvzone; 257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 258 259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 260 261 #ifndef PMAP_SHPGPERPROC 262 #define PMAP_SHPGPERPROC 200 263 #endif 264 265 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t); 266 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 267 static int pte_remove(pmap_t, vm_offset_t, uint8_t); 268 static pte_t *pte_find(pmap_t, vm_offset_t); 269 static void kernel_pte_alloc(vm_offset_t, vm_offset_t); 270 271 static pv_entry_t pv_alloc(void); 272 static void pv_free(pv_entry_t); 273 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 274 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 275 276 static void booke_pmap_init_qpages(void); 277 278 static inline void tlb_miss_lock(void); 279 static inline void tlb_miss_unlock(void); 280 281 #ifdef SMP 282 extern tlb_entry_t __boot_tlb1[]; 283 void pmap_bootstrap_ap(volatile uint32_t *); 284 #endif 285 286 /* 287 * Kernel MMU interface 288 */ 289 static void mmu_booke_clear_modify(vm_page_t); 290 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, 291 vm_size_t, vm_offset_t); 292 static void mmu_booke_copy_page(vm_page_t, vm_page_t); 293 static void mmu_booke_copy_pages(vm_page_t *, 294 vm_offset_t, vm_page_t *, vm_offset_t, int); 295 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t, 296 vm_prot_t, u_int flags, int8_t psind); 297 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t, 298 vm_page_t, vm_prot_t); 299 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t, 300 vm_prot_t); 301 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t); 302 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t, 303 vm_prot_t); 304 static void mmu_booke_init(void); 305 static boolean_t mmu_booke_is_modified(vm_page_t); 306 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t); 307 static boolean_t mmu_booke_is_referenced(vm_page_t); 308 static int mmu_booke_ts_referenced(vm_page_t); 309 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, 310 int); 311 static int mmu_booke_mincore(pmap_t, vm_offset_t, 312 vm_paddr_t *); 313 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t, 314 vm_object_t, vm_pindex_t, vm_size_t); 315 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t); 316 static void mmu_booke_page_init(vm_page_t); 317 static int mmu_booke_page_wired_mappings(vm_page_t); 318 static int mmu_booke_pinit(pmap_t); 319 static void mmu_booke_pinit0(pmap_t); 320 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t, 321 vm_prot_t); 322 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int); 323 static void mmu_booke_qremove(vm_offset_t, int); 324 static void mmu_booke_release(pmap_t); 325 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t); 326 static void mmu_booke_remove_all(vm_page_t); 327 static void mmu_booke_remove_write(vm_page_t); 328 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t); 329 static void mmu_booke_zero_page(vm_page_t); 330 static void mmu_booke_zero_page_area(vm_page_t, int, int); 331 static void mmu_booke_activate(struct thread *); 332 static void mmu_booke_deactivate(struct thread *); 333 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t); 334 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t); 335 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 336 static void mmu_booke_unmapdev(vm_offset_t, vm_size_t); 337 static vm_paddr_t mmu_booke_kextract(vm_offset_t); 338 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t); 339 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 340 static void mmu_booke_kremove(vm_offset_t); 341 static boolean_t mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t); 342 static void mmu_booke_sync_icache(pmap_t, vm_offset_t, 343 vm_size_t); 344 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t, 345 void **); 346 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t, 347 void *); 348 static void mmu_booke_scan_init(void); 349 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m); 350 static void mmu_booke_quick_remove_page(vm_offset_t addr); 351 static int mmu_booke_change_attr(vm_offset_t addr, 352 vm_size_t sz, vm_memattr_t mode); 353 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr, 354 int *is_user, vm_offset_t *decoded_addr); 355 static void mmu_booke_page_array_startup(long); 356 static boolean_t mmu_booke_page_is_mapped(vm_page_t m); 357 358 static struct pmap_funcs mmu_booke_methods = { 359 /* pmap dispatcher interface */ 360 .clear_modify = mmu_booke_clear_modify, 361 .copy = mmu_booke_copy, 362 .copy_page = mmu_booke_copy_page, 363 .copy_pages = mmu_booke_copy_pages, 364 .enter = mmu_booke_enter, 365 .enter_object = mmu_booke_enter_object, 366 .enter_quick = mmu_booke_enter_quick, 367 .extract = mmu_booke_extract, 368 .extract_and_hold = mmu_booke_extract_and_hold, 369 .init = mmu_booke_init, 370 .is_modified = mmu_booke_is_modified, 371 .is_prefaultable = mmu_booke_is_prefaultable, 372 .is_referenced = mmu_booke_is_referenced, 373 .ts_referenced = mmu_booke_ts_referenced, 374 .map = mmu_booke_map, 375 .mincore = mmu_booke_mincore, 376 .object_init_pt = mmu_booke_object_init_pt, 377 .page_exists_quick = mmu_booke_page_exists_quick, 378 .page_init = mmu_booke_page_init, 379 .page_wired_mappings = mmu_booke_page_wired_mappings, 380 .pinit = mmu_booke_pinit, 381 .pinit0 = mmu_booke_pinit0, 382 .protect = mmu_booke_protect, 383 .qenter = mmu_booke_qenter, 384 .qremove = mmu_booke_qremove, 385 .release = mmu_booke_release, 386 .remove = mmu_booke_remove, 387 .remove_all = mmu_booke_remove_all, 388 .remove_write = mmu_booke_remove_write, 389 .sync_icache = mmu_booke_sync_icache, 390 .unwire = mmu_booke_unwire, 391 .zero_page = mmu_booke_zero_page, 392 .zero_page_area = mmu_booke_zero_page_area, 393 .activate = mmu_booke_activate, 394 .deactivate = mmu_booke_deactivate, 395 .quick_enter_page = mmu_booke_quick_enter_page, 396 .quick_remove_page = mmu_booke_quick_remove_page, 397 .page_array_startup = mmu_booke_page_array_startup, 398 .page_is_mapped = mmu_booke_page_is_mapped, 399 400 /* Internal interfaces */ 401 .bootstrap = mmu_booke_bootstrap, 402 .dev_direct_mapped = mmu_booke_dev_direct_mapped, 403 .mapdev = mmu_booke_mapdev, 404 .mapdev_attr = mmu_booke_mapdev_attr, 405 .kenter = mmu_booke_kenter, 406 .kenter_attr = mmu_booke_kenter_attr, 407 .kextract = mmu_booke_kextract, 408 .kremove = mmu_booke_kremove, 409 .unmapdev = mmu_booke_unmapdev, 410 .change_attr = mmu_booke_change_attr, 411 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr, 412 413 /* dumpsys() support */ 414 .dumpsys_map_chunk = mmu_booke_dumpsys_map, 415 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap, 416 .dumpsys_pa_init = mmu_booke_scan_init, 417 }; 418 419 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods); 420 421 #ifdef __powerpc64__ 422 #include "pmap_64.c" 423 #else 424 #include "pmap_32.c" 425 #endif 426 427 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE; 428 429 static __inline uint32_t 430 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 431 { 432 uint32_t attrib; 433 int i; 434 435 if (ma != VM_MEMATTR_DEFAULT) { 436 switch (ma) { 437 case VM_MEMATTR_UNCACHEABLE: 438 return (MAS2_I | MAS2_G); 439 case VM_MEMATTR_WRITE_COMBINING: 440 case VM_MEMATTR_WRITE_BACK: 441 case VM_MEMATTR_PREFETCHABLE: 442 return (MAS2_I); 443 case VM_MEMATTR_WRITE_THROUGH: 444 return (MAS2_W | MAS2_M); 445 case VM_MEMATTR_CACHEABLE: 446 return (MAS2_M); 447 } 448 } 449 450 /* 451 * Assume the page is cache inhibited and access is guarded unless 452 * it's in our available memory array. 453 */ 454 attrib = _TLB_ENTRY_IO; 455 for (i = 0; i < physmem_regions_sz; i++) { 456 if ((pa >= physmem_regions[i].mr_start) && 457 (pa < (physmem_regions[i].mr_start + 458 physmem_regions[i].mr_size))) { 459 attrib = _TLB_ENTRY_MEM; 460 break; 461 } 462 } 463 464 return (attrib); 465 } 466 467 static inline void 468 tlb_miss_lock(void) 469 { 470 #ifdef SMP 471 struct pcpu *pc; 472 473 if (!smp_started) 474 return; 475 476 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 477 if (pc != pcpup) { 478 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 479 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock); 480 481 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 482 ("tlb_miss_lock: tried to lock self")); 483 484 tlb_lock(pc->pc_booke.tlb_lock); 485 486 CTR1(KTR_PMAP, "%s: locked", __func__); 487 } 488 } 489 #endif 490 } 491 492 static inline void 493 tlb_miss_unlock(void) 494 { 495 #ifdef SMP 496 struct pcpu *pc; 497 498 if (!smp_started) 499 return; 500 501 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 502 if (pc != pcpup) { 503 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 504 __func__, pc->pc_cpuid); 505 506 tlb_unlock(pc->pc_booke.tlb_lock); 507 508 CTR1(KTR_PMAP, "%s: unlocked", __func__); 509 } 510 } 511 #endif 512 } 513 514 /* Return number of entries in TLB0. */ 515 static __inline void 516 tlb0_get_tlbconf(void) 517 { 518 uint32_t tlb0_cfg; 519 520 tlb0_cfg = mfspr(SPR_TLB0CFG); 521 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 522 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 523 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 524 } 525 526 /* Return number of entries in TLB1. */ 527 static __inline void 528 tlb1_get_tlbconf(void) 529 { 530 uint32_t tlb1_cfg; 531 532 tlb1_cfg = mfspr(SPR_TLB1CFG); 533 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 534 } 535 536 /**************************************************************************/ 537 /* Page table related */ 538 /**************************************************************************/ 539 540 /* Allocate pv_entry structure. */ 541 pv_entry_t 542 pv_alloc(void) 543 { 544 pv_entry_t pv; 545 546 pv_entry_count++; 547 if (pv_entry_count > pv_entry_high_water) 548 pagedaemon_wakeup(0); /* XXX powerpc NUMA */ 549 pv = uma_zalloc(pvzone, M_NOWAIT); 550 551 return (pv); 552 } 553 554 /* Free pv_entry structure. */ 555 static __inline void 556 pv_free(pv_entry_t pve) 557 { 558 559 pv_entry_count--; 560 uma_zfree(pvzone, pve); 561 } 562 563 /* Allocate and initialize pv_entry structure. */ 564 static void 565 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 566 { 567 pv_entry_t pve; 568 569 //int su = (pmap == kernel_pmap); 570 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 571 // (u_int32_t)pmap, va, (u_int32_t)m); 572 573 pve = pv_alloc(); 574 if (pve == NULL) 575 panic("pv_insert: no pv entries!"); 576 577 pve->pv_pmap = pmap; 578 pve->pv_va = va; 579 580 /* add to pv_list */ 581 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 582 rw_assert(&pvh_global_lock, RA_WLOCKED); 583 584 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 585 586 //debugf("pv_insert: e\n"); 587 } 588 589 /* Destroy pv entry. */ 590 static void 591 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 592 { 593 pv_entry_t pve; 594 595 //int su = (pmap == kernel_pmap); 596 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 597 598 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 599 rw_assert(&pvh_global_lock, RA_WLOCKED); 600 601 /* find pv entry */ 602 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 603 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 604 /* remove from pv_list */ 605 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 606 if (TAILQ_EMPTY(&m->md.pv_list)) 607 vm_page_aflag_clear(m, PGA_WRITEABLE); 608 609 /* free pv entry struct */ 610 pv_free(pve); 611 break; 612 } 613 } 614 615 //debugf("pv_remove: e\n"); 616 } 617 618 /**************************************************************************/ 619 /* PMAP related */ 620 /**************************************************************************/ 621 622 /* 623 * This is called during booke_init, before the system is really initialized. 624 */ 625 static void 626 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend) 627 { 628 vm_paddr_t phys_kernelend; 629 struct mem_region *mp, *mp1; 630 int cnt, i, j; 631 vm_paddr_t s, e, sz; 632 vm_paddr_t physsz, hwphyssz; 633 u_int phys_avail_count; 634 vm_size_t kstack0_sz; 635 vm_paddr_t kstack0_phys; 636 vm_offset_t kstack0; 637 void *dpcpu; 638 639 debugf("mmu_booke_bootstrap: entered\n"); 640 641 /* Set interesting system properties */ 642 #ifdef __powerpc64__ 643 hw_direct_map = 1; 644 #else 645 hw_direct_map = 0; 646 #endif 647 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 648 elf32_nxstack = 1; 649 #endif 650 651 /* Initialize invalidation mutex */ 652 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 653 654 /* Read TLB0 size and associativity. */ 655 tlb0_get_tlbconf(); 656 657 /* 658 * Align kernel start and end address (kernel image). 659 * Note that kernel end does not necessarily relate to kernsize. 660 * kernsize is the size of the kernel that is actually mapped. 661 */ 662 data_start = round_page(kernelend); 663 data_end = data_start; 664 665 /* Allocate the dynamic per-cpu area. */ 666 dpcpu = (void *)data_end; 667 data_end += DPCPU_SIZE; 668 669 /* Allocate space for the message buffer. */ 670 msgbufp = (struct msgbuf *)data_end; 671 data_end += msgbufsize; 672 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 673 (uintptr_t)msgbufp, data_end); 674 675 data_end = round_page(data_end); 676 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end)); 677 678 /* Retrieve phys/avail mem regions */ 679 mem_regions(&physmem_regions, &physmem_regions_sz, 680 &availmem_regions, &availmem_regions_sz); 681 682 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz) 683 panic("mmu_booke_bootstrap: phys_avail too small"); 684 685 data_end = round_page(data_end); 686 vm_page_array = (vm_page_t)data_end; 687 /* 688 * Get a rough idea (upper bound) on the size of the page array. The 689 * vm_page_array will not handle any more pages than we have in the 690 * avail_regions array, and most likely much less. 691 */ 692 sz = 0; 693 for (mp = availmem_regions; mp->mr_size; mp++) { 694 sz += mp->mr_size; 695 } 696 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page))); 697 data_end += round_page(sz * sizeof(struct vm_page)); 698 699 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */ 700 data_end = roundup2(data_end, 1 << 20); 701 702 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end); 703 debugf(" kernstart: %#zx\n", kernstart); 704 debugf(" kernsize: %#zx\n", kernsize); 705 706 if (data_end - kernstart > kernsize) { 707 kernsize += tlb1_mapin_region(kernstart + kernsize, 708 kernload + kernsize, (data_end - kernstart) - kernsize, 709 _TLB_ENTRY_MEM); 710 } 711 data_end = kernstart + kernsize; 712 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end); 713 714 /* 715 * Clear the structures - note we can only do it safely after the 716 * possible additional TLB1 translations are in place (above) so that 717 * all range up to the currently calculated 'data_end' is covered. 718 */ 719 bzero((void *)data_start, data_end - data_start); 720 dpcpu_init(dpcpu, 0); 721 722 /*******************************************************/ 723 /* Set the start and end of kva. */ 724 /*******************************************************/ 725 virtual_avail = round_page(data_end); 726 virtual_end = VM_MAX_KERNEL_ADDRESS; 727 728 #ifndef __powerpc64__ 729 /* Allocate KVA space for page zero/copy operations. */ 730 zero_page_va = virtual_avail; 731 virtual_avail += PAGE_SIZE; 732 copy_page_src_va = virtual_avail; 733 virtual_avail += PAGE_SIZE; 734 copy_page_dst_va = virtual_avail; 735 virtual_avail += PAGE_SIZE; 736 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va); 737 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va); 738 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va); 739 740 /* Initialize page zero/copy mutexes. */ 741 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 742 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 743 744 /* Allocate KVA space for ptbl bufs. */ 745 ptbl_buf_pool_vabase = virtual_avail; 746 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 747 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 748 ptbl_buf_pool_vabase, virtual_avail); 749 #endif 750 751 /* Calculate corresponding physical addresses for the kernel region. */ 752 phys_kernelend = kernload + kernsize; 753 debugf("kernel image and allocated data:\n"); 754 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload); 755 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart); 756 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize); 757 758 /* 759 * Remove kernel physical address range from avail regions list. Page 760 * align all regions. Non-page aligned memory isn't very interesting 761 * to us. Also, sort the entries for ascending addresses. 762 */ 763 764 sz = 0; 765 cnt = availmem_regions_sz; 766 debugf("processing avail regions:\n"); 767 for (mp = availmem_regions; mp->mr_size; mp++) { 768 s = mp->mr_start; 769 e = mp->mr_start + mp->mr_size; 770 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 771 /* Check whether this region holds all of the kernel. */ 772 if (s < kernload && e > phys_kernelend) { 773 availmem_regions[cnt].mr_start = phys_kernelend; 774 availmem_regions[cnt++].mr_size = e - phys_kernelend; 775 e = kernload; 776 } 777 /* Look whether this regions starts within the kernel. */ 778 if (s >= kernload && s < phys_kernelend) { 779 if (e <= phys_kernelend) 780 goto empty; 781 s = phys_kernelend; 782 } 783 /* Now look whether this region ends within the kernel. */ 784 if (e > kernload && e <= phys_kernelend) { 785 if (s >= kernload) 786 goto empty; 787 e = kernload; 788 } 789 /* Now page align the start and size of the region. */ 790 s = round_page(s); 791 e = trunc_page(e); 792 if (e < s) 793 e = s; 794 sz = e - s; 795 debugf("%09jx-%09jx = %jx\n", 796 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 797 798 /* Check whether some memory is left here. */ 799 if (sz == 0) { 800 empty: 801 memmove(mp, mp + 1, 802 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 803 cnt--; 804 mp--; 805 continue; 806 } 807 808 /* Do an insertion sort. */ 809 for (mp1 = availmem_regions; mp1 < mp; mp1++) 810 if (s < mp1->mr_start) 811 break; 812 if (mp1 < mp) { 813 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 814 mp1->mr_start = s; 815 mp1->mr_size = sz; 816 } else { 817 mp->mr_start = s; 818 mp->mr_size = sz; 819 } 820 } 821 availmem_regions_sz = cnt; 822 823 /*******************************************************/ 824 /* Steal physical memory for kernel stack from the end */ 825 /* of the first avail region */ 826 /*******************************************************/ 827 kstack0_sz = kstack_pages * PAGE_SIZE; 828 kstack0_phys = availmem_regions[0].mr_start + 829 availmem_regions[0].mr_size; 830 kstack0_phys -= kstack0_sz; 831 availmem_regions[0].mr_size -= kstack0_sz; 832 833 /*******************************************************/ 834 /* Fill in phys_avail table, based on availmem_regions */ 835 /*******************************************************/ 836 phys_avail_count = 0; 837 physsz = 0; 838 hwphyssz = 0; 839 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 840 841 debugf("fill in phys_avail:\n"); 842 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 843 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 844 (uintmax_t)availmem_regions[i].mr_start, 845 (uintmax_t)availmem_regions[i].mr_start + 846 availmem_regions[i].mr_size, 847 (uintmax_t)availmem_regions[i].mr_size); 848 849 if (hwphyssz != 0 && 850 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 851 debugf(" hw.physmem adjust\n"); 852 if (physsz < hwphyssz) { 853 phys_avail[j] = availmem_regions[i].mr_start; 854 phys_avail[j + 1] = 855 availmem_regions[i].mr_start + 856 hwphyssz - physsz; 857 physsz = hwphyssz; 858 phys_avail_count++; 859 dump_avail[j] = phys_avail[j]; 860 dump_avail[j + 1] = phys_avail[j + 1]; 861 } 862 break; 863 } 864 865 phys_avail[j] = availmem_regions[i].mr_start; 866 phys_avail[j + 1] = availmem_regions[i].mr_start + 867 availmem_regions[i].mr_size; 868 phys_avail_count++; 869 physsz += availmem_regions[i].mr_size; 870 dump_avail[j] = phys_avail[j]; 871 dump_avail[j + 1] = phys_avail[j + 1]; 872 } 873 physmem = btoc(physsz); 874 875 /* Calculate the last available physical address. */ 876 for (i = 0; phys_avail[i + 2] != 0; i += 2) 877 ; 878 Maxmem = powerpc_btop(phys_avail[i + 1]); 879 880 debugf("Maxmem = 0x%08lx\n", Maxmem); 881 debugf("phys_avail_count = %d\n", phys_avail_count); 882 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 883 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 884 885 #ifdef __powerpc64__ 886 /* 887 * Map the physical memory contiguously in TLB1. 888 * Round so it fits into a single mapping. 889 */ 890 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0, 891 phys_avail[i + 1], _TLB_ENTRY_MEM); 892 #endif 893 894 /*******************************************************/ 895 /* Initialize (statically allocated) kernel pmap. */ 896 /*******************************************************/ 897 PMAP_LOCK_INIT(kernel_pmap); 898 899 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap); 900 kernel_pte_alloc(virtual_avail, kernstart); 901 for (i = 0; i < MAXCPU; i++) { 902 kernel_pmap->pm_tid[i] = TID_KERNEL; 903 904 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 905 tidbusy[i][TID_KERNEL] = kernel_pmap; 906 } 907 908 /* Mark kernel_pmap active on all CPUs */ 909 CPU_FILL(&kernel_pmap->pm_active); 910 911 /* 912 * Initialize the global pv list lock. 913 */ 914 rw_init(&pvh_global_lock, "pmap pv global"); 915 916 /*******************************************************/ 917 /* Final setup */ 918 /*******************************************************/ 919 920 /* Enter kstack0 into kernel map, provide guard page */ 921 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 922 thread0.td_kstack = kstack0; 923 thread0.td_kstack_pages = kstack_pages; 924 925 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz); 926 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n", 927 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz); 928 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n", 929 kstack0, kstack0 + kstack0_sz); 930 931 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 932 for (i = 0; i < kstack_pages; i++) { 933 mmu_booke_kenter(kstack0, kstack0_phys); 934 kstack0 += PAGE_SIZE; 935 kstack0_phys += PAGE_SIZE; 936 } 937 938 pmap_bootstrapped = 1; 939 940 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail); 941 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end); 942 943 debugf("mmu_booke_bootstrap: exit\n"); 944 } 945 946 #ifdef SMP 947 void 948 tlb1_ap_prep(void) 949 { 950 tlb_entry_t *e, tmp; 951 unsigned int i; 952 953 /* Prepare TLB1 image for AP processors */ 954 e = __boot_tlb1; 955 for (i = 0; i < TLB1_ENTRIES; i++) { 956 tlb1_read_entry(&tmp, i); 957 958 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 959 memcpy(e++, &tmp, sizeof(tmp)); 960 } 961 } 962 963 void 964 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 965 { 966 int i; 967 968 /* 969 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 970 * have the snapshot of its contents in the s/w __boot_tlb1[] table 971 * created by tlb1_ap_prep(), so use these values directly to 972 * (re)program AP's TLB1 hardware. 973 * 974 * Start at index 1 because index 0 has the kernel map. 975 */ 976 for (i = 1; i < TLB1_ENTRIES; i++) { 977 if (__boot_tlb1[i].mas1 & MAS1_VALID) 978 tlb1_write_entry(&__boot_tlb1[i], i); 979 } 980 981 set_mas4_defaults(); 982 } 983 #endif 984 985 static void 986 booke_pmap_init_qpages(void) 987 { 988 struct pcpu *pc; 989 int i; 990 991 CPU_FOREACH(i) { 992 pc = pcpu_find(i); 993 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 994 if (pc->pc_qmap_addr == 0) 995 panic("pmap_init_qpages: unable to allocate KVA"); 996 } 997 } 998 999 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1000 1001 /* 1002 * Get the physical page address for the given pmap/virtual address. 1003 */ 1004 static vm_paddr_t 1005 mmu_booke_extract(pmap_t pmap, vm_offset_t va) 1006 { 1007 vm_paddr_t pa; 1008 1009 PMAP_LOCK(pmap); 1010 pa = pte_vatopa(pmap, va); 1011 PMAP_UNLOCK(pmap); 1012 1013 return (pa); 1014 } 1015 1016 /* 1017 * Extract the physical page address associated with the given 1018 * kernel virtual address. 1019 */ 1020 static vm_paddr_t 1021 mmu_booke_kextract(vm_offset_t va) 1022 { 1023 tlb_entry_t e; 1024 vm_paddr_t p = 0; 1025 int i; 1026 1027 #ifdef __powerpc64__ 1028 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) 1029 return (DMAP_TO_PHYS(va)); 1030 #endif 1031 1032 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS) 1033 p = pte_vatopa(kernel_pmap, va); 1034 1035 if (p == 0) { 1036 /* Check TLB1 mappings */ 1037 for (i = 0; i < TLB1_ENTRIES; i++) { 1038 tlb1_read_entry(&e, i); 1039 if (!(e.mas1 & MAS1_VALID)) 1040 continue; 1041 if (va >= e.virt && va < e.virt + e.size) 1042 return (e.phys + (va - e.virt)); 1043 } 1044 } 1045 1046 return (p); 1047 } 1048 1049 /* 1050 * Initialize the pmap module. 1051 * Called by vm_init, to initialize any structures that the pmap 1052 * system needs to map virtual memory. 1053 */ 1054 static void 1055 mmu_booke_init() 1056 { 1057 int shpgperproc = PMAP_SHPGPERPROC; 1058 1059 /* 1060 * Initialize the address space (zone) for the pv entries. Set a 1061 * high water mark so that the system can recover from excessive 1062 * numbers of pv entries. 1063 */ 1064 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1065 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1066 1067 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1068 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1069 1070 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1071 pv_entry_high_water = 9 * (pv_entry_max / 10); 1072 1073 uma_zone_reserve_kva(pvzone, pv_entry_max); 1074 1075 /* Pre-fill pvzone with initial number of pv entries. */ 1076 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1077 1078 /* Create a UMA zone for page table roots. */ 1079 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE, 1080 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM); 1081 1082 /* Initialize ptbl allocation. */ 1083 ptbl_init(); 1084 } 1085 1086 /* 1087 * Map a list of wired pages into kernel virtual address space. This is 1088 * intended for temporary mappings which do not need page modification or 1089 * references recorded. Existing mappings in the region are overwritten. 1090 */ 1091 static void 1092 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count) 1093 { 1094 vm_offset_t va; 1095 1096 va = sva; 1097 while (count-- > 0) { 1098 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m)); 1099 va += PAGE_SIZE; 1100 m++; 1101 } 1102 } 1103 1104 /* 1105 * Remove page mappings from kernel virtual address space. Intended for 1106 * temporary mappings entered by mmu_booke_qenter. 1107 */ 1108 static void 1109 mmu_booke_qremove(vm_offset_t sva, int count) 1110 { 1111 vm_offset_t va; 1112 1113 va = sva; 1114 while (count-- > 0) { 1115 mmu_booke_kremove(va); 1116 va += PAGE_SIZE; 1117 } 1118 } 1119 1120 /* 1121 * Map a wired page into kernel virtual address space. 1122 */ 1123 static void 1124 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa) 1125 { 1126 1127 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1128 } 1129 1130 static void 1131 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1132 { 1133 uint32_t flags; 1134 pte_t *pte; 1135 1136 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1137 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1138 1139 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1140 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1141 flags |= PTE_PS_4KB; 1142 1143 pte = pte_find(kernel_pmap, va); 1144 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE")); 1145 1146 mtx_lock_spin(&tlbivax_mutex); 1147 tlb_miss_lock(); 1148 1149 if (PTE_ISVALID(pte)) { 1150 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1151 1152 /* Flush entry from TLB0 */ 1153 tlb0_flush_entry(va); 1154 } 1155 1156 *pte = PTE_RPN_FROM_PA(pa) | flags; 1157 1158 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1159 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1160 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1161 1162 /* Flush the real memory from the instruction cache. */ 1163 if ((flags & (PTE_I | PTE_G)) == 0) 1164 __syncicache((void *)va, PAGE_SIZE); 1165 1166 tlb_miss_unlock(); 1167 mtx_unlock_spin(&tlbivax_mutex); 1168 } 1169 1170 /* 1171 * Remove a page from kernel page table. 1172 */ 1173 static void 1174 mmu_booke_kremove(vm_offset_t va) 1175 { 1176 pte_t *pte; 1177 1178 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va); 1179 1180 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1181 (va <= VM_MAX_KERNEL_ADDRESS)), 1182 ("mmu_booke_kremove: invalid va")); 1183 1184 pte = pte_find(kernel_pmap, va); 1185 1186 if (!PTE_ISVALID(pte)) { 1187 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1188 1189 return; 1190 } 1191 1192 mtx_lock_spin(&tlbivax_mutex); 1193 tlb_miss_lock(); 1194 1195 /* Invalidate entry in TLB0, update PTE. */ 1196 tlb0_flush_entry(va); 1197 *pte = 0; 1198 1199 tlb_miss_unlock(); 1200 mtx_unlock_spin(&tlbivax_mutex); 1201 } 1202 1203 /* 1204 * Figure out where a given kernel pointer (usually in a fault) points 1205 * to from the VM's perspective, potentially remapping into userland's 1206 * address space. 1207 */ 1208 static int 1209 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1210 vm_offset_t *decoded_addr) 1211 { 1212 1213 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS) 1214 *is_user = 1; 1215 else 1216 *is_user = 0; 1217 1218 *decoded_addr = addr; 1219 return (0); 1220 } 1221 1222 static boolean_t 1223 mmu_booke_page_is_mapped(vm_page_t m) 1224 { 1225 1226 return (!TAILQ_EMPTY(&(m)->md.pv_list)); 1227 } 1228 1229 /* 1230 * Initialize pmap associated with process 0. 1231 */ 1232 static void 1233 mmu_booke_pinit0(pmap_t pmap) 1234 { 1235 1236 PMAP_LOCK_INIT(pmap); 1237 mmu_booke_pinit(pmap); 1238 PCPU_SET(curpmap, pmap); 1239 } 1240 1241 /* 1242 * Insert the given physical page at the specified virtual address in the 1243 * target physical map with the protection requested. If specified the page 1244 * will be wired down. 1245 */ 1246 static int 1247 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1248 vm_prot_t prot, u_int flags, int8_t psind) 1249 { 1250 int error; 1251 1252 rw_wlock(&pvh_global_lock); 1253 PMAP_LOCK(pmap); 1254 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind); 1255 PMAP_UNLOCK(pmap); 1256 rw_wunlock(&pvh_global_lock); 1257 return (error); 1258 } 1259 1260 static int 1261 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1262 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1263 { 1264 pte_t *pte; 1265 vm_paddr_t pa; 1266 pte_t flags; 1267 int error, su, sync; 1268 1269 pa = VM_PAGE_TO_PHYS(m); 1270 su = (pmap == kernel_pmap); 1271 sync = 0; 1272 1273 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1274 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1275 // (u_int32_t)pmap, su, pmap->pm_tid, 1276 // (u_int32_t)m, va, pa, prot, flags); 1277 1278 if (su) { 1279 KASSERT(((va >= virtual_avail) && 1280 (va <= VM_MAX_KERNEL_ADDRESS)), 1281 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1282 } else { 1283 KASSERT((va <= VM_MAXUSER_ADDRESS), 1284 ("mmu_booke_enter_locked: user pmap, non user va")); 1285 } 1286 if ((m->oflags & VPO_UNMANAGED) == 0) { 1287 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1288 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1289 else 1290 VM_OBJECT_ASSERT_LOCKED(m->object); 1291 } 1292 1293 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1294 1295 /* 1296 * If there is an existing mapping, and the physical address has not 1297 * changed, must be protection or wiring change. 1298 */ 1299 if (((pte = pte_find(pmap, va)) != NULL) && 1300 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1301 1302 /* 1303 * Before actually updating pte->flags we calculate and 1304 * prepare its new value in a helper var. 1305 */ 1306 flags = *pte; 1307 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1308 1309 /* Wiring change, just update stats. */ 1310 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1311 if (!PTE_ISWIRED(pte)) { 1312 flags |= PTE_WIRED; 1313 pmap->pm_stats.wired_count++; 1314 } 1315 } else { 1316 if (PTE_ISWIRED(pte)) { 1317 flags &= ~PTE_WIRED; 1318 pmap->pm_stats.wired_count--; 1319 } 1320 } 1321 1322 if (prot & VM_PROT_WRITE) { 1323 /* Add write permissions. */ 1324 flags |= PTE_SW; 1325 if (!su) 1326 flags |= PTE_UW; 1327 1328 if ((flags & PTE_MANAGED) != 0) 1329 vm_page_aflag_set(m, PGA_WRITEABLE); 1330 } else { 1331 /* Handle modified pages, sense modify status. */ 1332 1333 /* 1334 * The PTE_MODIFIED flag could be set by underlying 1335 * TLB misses since we last read it (above), possibly 1336 * other CPUs could update it so we check in the PTE 1337 * directly rather than rely on that saved local flags 1338 * copy. 1339 */ 1340 if (PTE_ISMODIFIED(pte)) 1341 vm_page_dirty(m); 1342 } 1343 1344 if (prot & VM_PROT_EXECUTE) { 1345 flags |= PTE_SX; 1346 if (!su) 1347 flags |= PTE_UX; 1348 1349 /* 1350 * Check existing flags for execute permissions: if we 1351 * are turning execute permissions on, icache should 1352 * be flushed. 1353 */ 1354 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1355 sync++; 1356 } 1357 1358 flags &= ~PTE_REFERENCED; 1359 1360 /* 1361 * The new flags value is all calculated -- only now actually 1362 * update the PTE. 1363 */ 1364 mtx_lock_spin(&tlbivax_mutex); 1365 tlb_miss_lock(); 1366 1367 tlb0_flush_entry(va); 1368 *pte &= ~PTE_FLAGS_MASK; 1369 *pte |= flags; 1370 1371 tlb_miss_unlock(); 1372 mtx_unlock_spin(&tlbivax_mutex); 1373 1374 } else { 1375 /* 1376 * If there is an existing mapping, but it's for a different 1377 * physical address, pte_enter() will delete the old mapping. 1378 */ 1379 //if ((pte != NULL) && PTE_ISVALID(pte)) 1380 // debugf("mmu_booke_enter_locked: replace\n"); 1381 //else 1382 // debugf("mmu_booke_enter_locked: new\n"); 1383 1384 /* Now set up the flags and install the new mapping. */ 1385 flags = (PTE_SR | PTE_VALID); 1386 flags |= PTE_M; 1387 1388 if (!su) 1389 flags |= PTE_UR; 1390 1391 if (prot & VM_PROT_WRITE) { 1392 flags |= PTE_SW; 1393 if (!su) 1394 flags |= PTE_UW; 1395 1396 if ((m->oflags & VPO_UNMANAGED) == 0) 1397 vm_page_aflag_set(m, PGA_WRITEABLE); 1398 } 1399 1400 if (prot & VM_PROT_EXECUTE) { 1401 flags |= PTE_SX; 1402 if (!su) 1403 flags |= PTE_UX; 1404 } 1405 1406 /* If its wired update stats. */ 1407 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1408 flags |= PTE_WIRED; 1409 1410 error = pte_enter(pmap, m, va, flags, 1411 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1412 if (error != 0) 1413 return (KERN_RESOURCE_SHORTAGE); 1414 1415 if ((flags & PMAP_ENTER_WIRED) != 0) 1416 pmap->pm_stats.wired_count++; 1417 1418 /* Flush the real memory from the instruction cache. */ 1419 if (prot & VM_PROT_EXECUTE) 1420 sync++; 1421 } 1422 1423 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1424 __syncicache((void *)va, PAGE_SIZE); 1425 sync = 0; 1426 } 1427 1428 return (KERN_SUCCESS); 1429 } 1430 1431 /* 1432 * Maps a sequence of resident pages belonging to the same object. 1433 * The sequence begins with the given page m_start. This page is 1434 * mapped at the given virtual address start. Each subsequent page is 1435 * mapped at a virtual address that is offset from start by the same 1436 * amount as the page is offset from m_start within the object. The 1437 * last page in the sequence is the page with the largest offset from 1438 * m_start that can be mapped at a virtual address less than the given 1439 * virtual address end. Not every virtual page between start and end 1440 * is mapped; only those for which a resident page exists with the 1441 * corresponding offset from m_start are mapped. 1442 */ 1443 static void 1444 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start, 1445 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1446 { 1447 vm_page_t m; 1448 vm_pindex_t diff, psize; 1449 1450 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1451 1452 psize = atop(end - start); 1453 m = m_start; 1454 rw_wlock(&pvh_global_lock); 1455 PMAP_LOCK(pmap); 1456 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1457 mmu_booke_enter_locked(pmap, start + ptoa(diff), m, 1458 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1459 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1460 m = TAILQ_NEXT(m, listq); 1461 } 1462 PMAP_UNLOCK(pmap); 1463 rw_wunlock(&pvh_global_lock); 1464 } 1465 1466 static void 1467 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, 1468 vm_prot_t prot) 1469 { 1470 1471 rw_wlock(&pvh_global_lock); 1472 PMAP_LOCK(pmap); 1473 mmu_booke_enter_locked(pmap, va, m, 1474 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1475 PMAP_ENTER_QUICK_LOCKED, 0); 1476 PMAP_UNLOCK(pmap); 1477 rw_wunlock(&pvh_global_lock); 1478 } 1479 1480 /* 1481 * Remove the given range of addresses from the specified map. 1482 * 1483 * It is assumed that the start and end are properly rounded to the page size. 1484 */ 1485 static void 1486 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1487 { 1488 pte_t *pte; 1489 uint8_t hold_flag; 1490 1491 int su = (pmap == kernel_pmap); 1492 1493 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1494 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1495 1496 if (su) { 1497 KASSERT(((va >= virtual_avail) && 1498 (va <= VM_MAX_KERNEL_ADDRESS)), 1499 ("mmu_booke_remove: kernel pmap, non kernel va")); 1500 } else { 1501 KASSERT((va <= VM_MAXUSER_ADDRESS), 1502 ("mmu_booke_remove: user pmap, non user va")); 1503 } 1504 1505 if (PMAP_REMOVE_DONE(pmap)) { 1506 //debugf("mmu_booke_remove: e (empty)\n"); 1507 return; 1508 } 1509 1510 hold_flag = PTBL_HOLD_FLAG(pmap); 1511 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1512 1513 rw_wlock(&pvh_global_lock); 1514 PMAP_LOCK(pmap); 1515 for (; va < endva; va += PAGE_SIZE) { 1516 pte = pte_find_next(pmap, &va); 1517 if ((pte == NULL) || !PTE_ISVALID(pte)) 1518 break; 1519 if (va >= endva) 1520 break; 1521 pte_remove(pmap, va, hold_flag); 1522 } 1523 PMAP_UNLOCK(pmap); 1524 rw_wunlock(&pvh_global_lock); 1525 1526 //debugf("mmu_booke_remove: e\n"); 1527 } 1528 1529 /* 1530 * Remove physical page from all pmaps in which it resides. 1531 */ 1532 static void 1533 mmu_booke_remove_all(vm_page_t m) 1534 { 1535 pv_entry_t pv, pvn; 1536 uint8_t hold_flag; 1537 1538 rw_wlock(&pvh_global_lock); 1539 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) { 1540 PMAP_LOCK(pv->pv_pmap); 1541 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1542 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag); 1543 PMAP_UNLOCK(pv->pv_pmap); 1544 } 1545 vm_page_aflag_clear(m, PGA_WRITEABLE); 1546 rw_wunlock(&pvh_global_lock); 1547 } 1548 1549 /* 1550 * Map a range of physical addresses into kernel virtual address space. 1551 */ 1552 static vm_offset_t 1553 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start, 1554 vm_paddr_t pa_end, int prot) 1555 { 1556 vm_offset_t sva = *virt; 1557 vm_offset_t va = sva; 1558 1559 #ifdef __powerpc64__ 1560 /* XXX: Handle memory not starting at 0x0. */ 1561 if (pa_end < ctob(Maxmem)) 1562 return (PHYS_TO_DMAP(pa_start)); 1563 #endif 1564 1565 while (pa_start < pa_end) { 1566 mmu_booke_kenter(va, pa_start); 1567 va += PAGE_SIZE; 1568 pa_start += PAGE_SIZE; 1569 } 1570 *virt = va; 1571 1572 return (sva); 1573 } 1574 1575 /* 1576 * The pmap must be activated before it's address space can be accessed in any 1577 * way. 1578 */ 1579 static void 1580 mmu_booke_activate(struct thread *td) 1581 { 1582 pmap_t pmap; 1583 u_int cpuid; 1584 1585 pmap = &td->td_proc->p_vmspace->vm_pmap; 1586 1587 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")", 1588 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1589 1590 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1591 1592 sched_pin(); 1593 1594 cpuid = PCPU_GET(cpuid); 1595 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1596 PCPU_SET(curpmap, pmap); 1597 1598 if (pmap->pm_tid[cpuid] == TID_NONE) 1599 tid_alloc(pmap); 1600 1601 /* Load PID0 register with pmap tid value. */ 1602 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1603 __asm __volatile("isync"); 1604 1605 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1606 1607 sched_unpin(); 1608 1609 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1610 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1611 } 1612 1613 /* 1614 * Deactivate the specified process's address space. 1615 */ 1616 static void 1617 mmu_booke_deactivate(struct thread *td) 1618 { 1619 pmap_t pmap; 1620 1621 pmap = &td->td_proc->p_vmspace->vm_pmap; 1622 1623 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX, 1624 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1625 1626 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 1627 1628 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1629 PCPU_SET(curpmap, NULL); 1630 } 1631 1632 /* 1633 * Copy the range specified by src_addr/len 1634 * from the source map to the range dst_addr/len 1635 * in the destination map. 1636 * 1637 * This routine is only advisory and need not do anything. 1638 */ 1639 static void 1640 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, 1641 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1642 { 1643 1644 } 1645 1646 /* 1647 * Set the physical protection on the specified range of this map as requested. 1648 */ 1649 static void 1650 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1651 vm_prot_t prot) 1652 { 1653 vm_offset_t va; 1654 vm_page_t m; 1655 pte_t *pte; 1656 1657 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1658 mmu_booke_remove(pmap, sva, eva); 1659 return; 1660 } 1661 1662 if (prot & VM_PROT_WRITE) 1663 return; 1664 1665 PMAP_LOCK(pmap); 1666 for (va = sva; va < eva; va += PAGE_SIZE) { 1667 if ((pte = pte_find(pmap, va)) != NULL) { 1668 if (PTE_ISVALID(pte)) { 1669 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1670 1671 mtx_lock_spin(&tlbivax_mutex); 1672 tlb_miss_lock(); 1673 1674 /* Handle modified pages. */ 1675 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1676 vm_page_dirty(m); 1677 1678 tlb0_flush_entry(va); 1679 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1680 1681 tlb_miss_unlock(); 1682 mtx_unlock_spin(&tlbivax_mutex); 1683 } 1684 } 1685 } 1686 PMAP_UNLOCK(pmap); 1687 } 1688 1689 /* 1690 * Clear the write and modified bits in each of the given page's mappings. 1691 */ 1692 static void 1693 mmu_booke_remove_write(vm_page_t m) 1694 { 1695 pv_entry_t pv; 1696 pte_t *pte; 1697 1698 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1699 ("mmu_booke_remove_write: page %p is not managed", m)); 1700 vm_page_assert_busied(m); 1701 1702 if (!pmap_page_is_write_mapped(m)) 1703 return; 1704 rw_wlock(&pvh_global_lock); 1705 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1706 PMAP_LOCK(pv->pv_pmap); 1707 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) { 1708 if (PTE_ISVALID(pte)) { 1709 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1710 1711 mtx_lock_spin(&tlbivax_mutex); 1712 tlb_miss_lock(); 1713 1714 /* Handle modified pages. */ 1715 if (PTE_ISMODIFIED(pte)) 1716 vm_page_dirty(m); 1717 1718 /* Flush mapping from TLB0. */ 1719 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1720 1721 tlb_miss_unlock(); 1722 mtx_unlock_spin(&tlbivax_mutex); 1723 } 1724 } 1725 PMAP_UNLOCK(pv->pv_pmap); 1726 } 1727 vm_page_aflag_clear(m, PGA_WRITEABLE); 1728 rw_wunlock(&pvh_global_lock); 1729 } 1730 1731 /* 1732 * Atomically extract and hold the physical page with the given 1733 * pmap and virtual address pair if that mapping permits the given 1734 * protection. 1735 */ 1736 static vm_page_t 1737 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va, 1738 vm_prot_t prot) 1739 { 1740 pte_t *pte; 1741 vm_page_t m; 1742 uint32_t pte_wbit; 1743 1744 m = NULL; 1745 PMAP_LOCK(pmap); 1746 pte = pte_find(pmap, va); 1747 if ((pte != NULL) && PTE_ISVALID(pte)) { 1748 if (pmap == kernel_pmap) 1749 pte_wbit = PTE_SW; 1750 else 1751 pte_wbit = PTE_UW; 1752 1753 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) { 1754 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1755 if (!vm_page_wire_mapped(m)) 1756 m = NULL; 1757 } 1758 } 1759 PMAP_UNLOCK(pmap); 1760 return (m); 1761 } 1762 1763 /* 1764 * Initialize a vm_page's machine-dependent fields. 1765 */ 1766 static void 1767 mmu_booke_page_init(vm_page_t m) 1768 { 1769 1770 m->md.pv_tracked = 0; 1771 TAILQ_INIT(&m->md.pv_list); 1772 } 1773 1774 /* 1775 * Return whether or not the specified physical page was modified 1776 * in any of physical maps. 1777 */ 1778 static boolean_t 1779 mmu_booke_is_modified(vm_page_t m) 1780 { 1781 pte_t *pte; 1782 pv_entry_t pv; 1783 boolean_t rv; 1784 1785 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1786 ("mmu_booke_is_modified: page %p is not managed", m)); 1787 rv = FALSE; 1788 1789 /* 1790 * If the page is not busied then this check is racy. 1791 */ 1792 if (!pmap_page_is_write_mapped(m)) 1793 return (FALSE); 1794 1795 rw_wlock(&pvh_global_lock); 1796 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1797 PMAP_LOCK(pv->pv_pmap); 1798 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1799 PTE_ISVALID(pte)) { 1800 if (PTE_ISMODIFIED(pte)) 1801 rv = TRUE; 1802 } 1803 PMAP_UNLOCK(pv->pv_pmap); 1804 if (rv) 1805 break; 1806 } 1807 rw_wunlock(&pvh_global_lock); 1808 return (rv); 1809 } 1810 1811 /* 1812 * Return whether or not the specified virtual address is eligible 1813 * for prefault. 1814 */ 1815 static boolean_t 1816 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1817 { 1818 1819 return (FALSE); 1820 } 1821 1822 /* 1823 * Return whether or not the specified physical page was referenced 1824 * in any physical maps. 1825 */ 1826 static boolean_t 1827 mmu_booke_is_referenced(vm_page_t m) 1828 { 1829 pte_t *pte; 1830 pv_entry_t pv; 1831 boolean_t rv; 1832 1833 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1834 ("mmu_booke_is_referenced: page %p is not managed", m)); 1835 rv = FALSE; 1836 rw_wlock(&pvh_global_lock); 1837 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1838 PMAP_LOCK(pv->pv_pmap); 1839 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1840 PTE_ISVALID(pte)) { 1841 if (PTE_ISREFERENCED(pte)) 1842 rv = TRUE; 1843 } 1844 PMAP_UNLOCK(pv->pv_pmap); 1845 if (rv) 1846 break; 1847 } 1848 rw_wunlock(&pvh_global_lock); 1849 return (rv); 1850 } 1851 1852 /* 1853 * Clear the modify bits on the specified physical page. 1854 */ 1855 static void 1856 mmu_booke_clear_modify(vm_page_t m) 1857 { 1858 pte_t *pte; 1859 pv_entry_t pv; 1860 1861 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1862 ("mmu_booke_clear_modify: page %p is not managed", m)); 1863 vm_page_assert_busied(m); 1864 1865 if (!pmap_page_is_write_mapped(m)) 1866 return; 1867 1868 rw_wlock(&pvh_global_lock); 1869 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1870 PMAP_LOCK(pv->pv_pmap); 1871 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1872 PTE_ISVALID(pte)) { 1873 mtx_lock_spin(&tlbivax_mutex); 1874 tlb_miss_lock(); 1875 1876 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 1877 tlb0_flush_entry(pv->pv_va); 1878 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 1879 PTE_REFERENCED); 1880 } 1881 1882 tlb_miss_unlock(); 1883 mtx_unlock_spin(&tlbivax_mutex); 1884 } 1885 PMAP_UNLOCK(pv->pv_pmap); 1886 } 1887 rw_wunlock(&pvh_global_lock); 1888 } 1889 1890 /* 1891 * Return a count of reference bits for a page, clearing those bits. 1892 * It is not necessary for every reference bit to be cleared, but it 1893 * is necessary that 0 only be returned when there are truly no 1894 * reference bits set. 1895 * 1896 * As an optimization, update the page's dirty field if a modified bit is 1897 * found while counting reference bits. This opportunistic update can be 1898 * performed at low cost and can eliminate the need for some future calls 1899 * to pmap_is_modified(). However, since this function stops after 1900 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 1901 * dirty pages. Those dirty pages will only be detected by a future call 1902 * to pmap_is_modified(). 1903 */ 1904 static int 1905 mmu_booke_ts_referenced(vm_page_t m) 1906 { 1907 pte_t *pte; 1908 pv_entry_t pv; 1909 int count; 1910 1911 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1912 ("mmu_booke_ts_referenced: page %p is not managed", m)); 1913 count = 0; 1914 rw_wlock(&pvh_global_lock); 1915 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1916 PMAP_LOCK(pv->pv_pmap); 1917 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1918 PTE_ISVALID(pte)) { 1919 if (PTE_ISMODIFIED(pte)) 1920 vm_page_dirty(m); 1921 if (PTE_ISREFERENCED(pte)) { 1922 mtx_lock_spin(&tlbivax_mutex); 1923 tlb_miss_lock(); 1924 1925 tlb0_flush_entry(pv->pv_va); 1926 *pte &= ~PTE_REFERENCED; 1927 1928 tlb_miss_unlock(); 1929 mtx_unlock_spin(&tlbivax_mutex); 1930 1931 if (++count >= PMAP_TS_REFERENCED_MAX) { 1932 PMAP_UNLOCK(pv->pv_pmap); 1933 break; 1934 } 1935 } 1936 } 1937 PMAP_UNLOCK(pv->pv_pmap); 1938 } 1939 rw_wunlock(&pvh_global_lock); 1940 return (count); 1941 } 1942 1943 /* 1944 * Clear the wired attribute from the mappings for the specified range of 1945 * addresses in the given pmap. Every valid mapping within that range must 1946 * have the wired attribute set. In contrast, invalid mappings cannot have 1947 * the wired attribute set, so they are ignored. 1948 * 1949 * The wired attribute of the page table entry is not a hardware feature, so 1950 * there is no need to invalidate any TLB entries. 1951 */ 1952 static void 1953 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1954 { 1955 vm_offset_t va; 1956 pte_t *pte; 1957 1958 PMAP_LOCK(pmap); 1959 for (va = sva; va < eva; va += PAGE_SIZE) { 1960 if ((pte = pte_find(pmap, va)) != NULL && 1961 PTE_ISVALID(pte)) { 1962 if (!PTE_ISWIRED(pte)) 1963 panic("mmu_booke_unwire: pte %p isn't wired", 1964 pte); 1965 *pte &= ~PTE_WIRED; 1966 pmap->pm_stats.wired_count--; 1967 } 1968 } 1969 PMAP_UNLOCK(pmap); 1970 1971 } 1972 1973 /* 1974 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 1975 * page. This count may be changed upwards or downwards in the future; it is 1976 * only necessary that true be returned for a small subset of pmaps for proper 1977 * page aging. 1978 */ 1979 static boolean_t 1980 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m) 1981 { 1982 pv_entry_t pv; 1983 int loops; 1984 boolean_t rv; 1985 1986 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1987 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 1988 loops = 0; 1989 rv = FALSE; 1990 rw_wlock(&pvh_global_lock); 1991 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1992 if (pv->pv_pmap == pmap) { 1993 rv = TRUE; 1994 break; 1995 } 1996 if (++loops >= 16) 1997 break; 1998 } 1999 rw_wunlock(&pvh_global_lock); 2000 return (rv); 2001 } 2002 2003 /* 2004 * Return the number of managed mappings to the given physical page that are 2005 * wired. 2006 */ 2007 static int 2008 mmu_booke_page_wired_mappings(vm_page_t m) 2009 { 2010 pv_entry_t pv; 2011 pte_t *pte; 2012 int count = 0; 2013 2014 if ((m->oflags & VPO_UNMANAGED) != 0) 2015 return (count); 2016 rw_wlock(&pvh_global_lock); 2017 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2018 PMAP_LOCK(pv->pv_pmap); 2019 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) 2020 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2021 count++; 2022 PMAP_UNLOCK(pv->pv_pmap); 2023 } 2024 rw_wunlock(&pvh_global_lock); 2025 return (count); 2026 } 2027 2028 static int 2029 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2030 { 2031 int i; 2032 vm_offset_t va; 2033 2034 /* 2035 * This currently does not work for entries that 2036 * overlap TLB1 entries. 2037 */ 2038 for (i = 0; i < TLB1_ENTRIES; i ++) { 2039 if (tlb1_iomapped(i, pa, size, &va) == 0) 2040 return (0); 2041 } 2042 2043 return (EFAULT); 2044 } 2045 2046 void 2047 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2048 { 2049 vm_paddr_t ppa; 2050 vm_offset_t ofs; 2051 vm_size_t gran; 2052 2053 /* Minidumps are based on virtual memory addresses. */ 2054 if (do_minidump) { 2055 *va = (void *)(vm_offset_t)pa; 2056 return; 2057 } 2058 2059 /* Raw physical memory dumps don't have a virtual address. */ 2060 /* We always map a 256MB page at 256M. */ 2061 gran = 256 * 1024 * 1024; 2062 ppa = rounddown2(pa, gran); 2063 ofs = pa - ppa; 2064 *va = (void *)gran; 2065 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2066 2067 if (sz > (gran - ofs)) 2068 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2069 _TLB_ENTRY_IO); 2070 } 2071 2072 void 2073 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va) 2074 { 2075 vm_paddr_t ppa; 2076 vm_offset_t ofs; 2077 vm_size_t gran; 2078 tlb_entry_t e; 2079 int i; 2080 2081 /* Minidumps are based on virtual memory addresses. */ 2082 /* Nothing to do... */ 2083 if (do_minidump) 2084 return; 2085 2086 for (i = 0; i < TLB1_ENTRIES; i++) { 2087 tlb1_read_entry(&e, i); 2088 if (!(e.mas1 & MAS1_VALID)) 2089 break; 2090 } 2091 2092 /* Raw physical memory dumps don't have a virtual address. */ 2093 i--; 2094 e.mas1 = 0; 2095 e.mas2 = 0; 2096 e.mas3 = 0; 2097 tlb1_write_entry(&e, i); 2098 2099 gran = 256 * 1024 * 1024; 2100 ppa = rounddown2(pa, gran); 2101 ofs = pa - ppa; 2102 if (sz > (gran - ofs)) { 2103 i--; 2104 e.mas1 = 0; 2105 e.mas2 = 0; 2106 e.mas3 = 0; 2107 tlb1_write_entry(&e, i); 2108 } 2109 } 2110 2111 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2112 2113 void 2114 mmu_booke_scan_init() 2115 { 2116 vm_offset_t va; 2117 pte_t *pte; 2118 int i; 2119 2120 if (!do_minidump) { 2121 /* Initialize phys. segments for dumpsys(). */ 2122 memset(&dump_map, 0, sizeof(dump_map)); 2123 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2124 &availmem_regions_sz); 2125 for (i = 0; i < physmem_regions_sz; i++) { 2126 dump_map[i].pa_start = physmem_regions[i].mr_start; 2127 dump_map[i].pa_size = physmem_regions[i].mr_size; 2128 } 2129 return; 2130 } 2131 2132 /* Virtual segments for minidumps: */ 2133 memset(&dump_map, 0, sizeof(dump_map)); 2134 2135 /* 1st: kernel .data and .bss. */ 2136 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2137 dump_map[0].pa_size = 2138 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2139 2140 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2141 dump_map[1].pa_start = data_start; 2142 dump_map[1].pa_size = data_end - data_start; 2143 2144 /* 3rd: kernel VM. */ 2145 va = dump_map[1].pa_start + dump_map[1].pa_size; 2146 /* Find start of next chunk (from va). */ 2147 while (va < virtual_end) { 2148 /* Don't dump the buffer cache. */ 2149 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2150 va = kmi.buffer_eva; 2151 continue; 2152 } 2153 pte = pte_find(kernel_pmap, va); 2154 if (pte != NULL && PTE_ISVALID(pte)) 2155 break; 2156 va += PAGE_SIZE; 2157 } 2158 if (va < virtual_end) { 2159 dump_map[2].pa_start = va; 2160 va += PAGE_SIZE; 2161 /* Find last page in chunk. */ 2162 while (va < virtual_end) { 2163 /* Don't run into the buffer cache. */ 2164 if (va == kmi.buffer_sva) 2165 break; 2166 pte = pte_find(kernel_pmap, va); 2167 if (pte == NULL || !PTE_ISVALID(pte)) 2168 break; 2169 va += PAGE_SIZE; 2170 } 2171 dump_map[2].pa_size = va - dump_map[2].pa_start; 2172 } 2173 } 2174 2175 /* 2176 * Map a set of physical memory pages into the kernel virtual address space. 2177 * Return a pointer to where it is mapped. This routine is intended to be used 2178 * for mapping device memory, NOT real memory. 2179 */ 2180 static void * 2181 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size) 2182 { 2183 2184 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2185 } 2186 2187 static int 2188 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e) 2189 { 2190 int i; 2191 2192 for (i = 0; i < TLB1_ENTRIES; i++) { 2193 tlb1_read_entry(e, i); 2194 if ((e->mas1 & MAS1_VALID) == 0) 2195 continue; 2196 if (e->phys == pa) 2197 return (i); 2198 } 2199 return (-1); 2200 } 2201 2202 static void * 2203 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2204 { 2205 tlb_entry_t e; 2206 vm_paddr_t tmppa; 2207 #ifndef __powerpc64__ 2208 uintptr_t tmpva; 2209 #endif 2210 uintptr_t va, retva; 2211 vm_size_t sz; 2212 int i; 2213 int wimge; 2214 2215 /* 2216 * Check if this is premapped in TLB1. 2217 */ 2218 sz = size; 2219 tmppa = pa; 2220 va = ~0; 2221 wimge = tlb_calc_wimg(pa, ma); 2222 for (i = 0; i < TLB1_ENTRIES; i++) { 2223 tlb1_read_entry(&e, i); 2224 if (!(e.mas1 & MAS1_VALID)) 2225 continue; 2226 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))) 2227 continue; 2228 if (tmppa >= e.phys && tmppa < e.phys + e.size) { 2229 va = e.virt + (pa - e.phys); 2230 tmppa = e.phys + e.size; 2231 sz -= MIN(sz, e.size - (pa - e.phys)); 2232 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) { 2233 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))) 2234 break; 2235 sz -= MIN(sz, e.size); 2236 tmppa = e.phys + e.size; 2237 } 2238 if (sz != 0) 2239 break; 2240 return ((void *)va); 2241 } 2242 } 2243 2244 size = roundup(size, PAGE_SIZE); 2245 2246 #ifdef __powerpc64__ 2247 KASSERT(pa < VM_MAPDEV_PA_MAX, 2248 ("Unsupported physical address! %lx", pa)); 2249 va = VM_MAPDEV_BASE + pa; 2250 retva = va; 2251 #ifdef POW2_MAPPINGS 2252 /* 2253 * Align the mapping to a power of 2 size, taking into account that we 2254 * may need to increase the size multiple times to satisfy the size and 2255 * alignment requirements. 2256 * 2257 * This works in the general case because it's very rare (near never?) 2258 * to have different access properties (WIMG) within a single 2259 * power-of-two region. If a design does call for that, POW2_MAPPINGS 2260 * can be undefined, and exact mappings will be used instead. 2261 */ 2262 sz = size; 2263 size = roundup2(size, 1 << ilog2(size)); 2264 while (rounddown2(va, size) + size < va + sz) 2265 size <<= 1; 2266 va = rounddown2(va, size); 2267 pa = rounddown2(pa, size); 2268 #endif 2269 #else 2270 /* 2271 * The device mapping area is between VM_MAXUSER_ADDRESS and 2272 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 2273 */ 2274 #ifdef SPARSE_MAPDEV 2275 /* 2276 * With a sparse mapdev, align to the largest starting region. This 2277 * could feasibly be optimized for a 'best-fit' alignment, but that 2278 * calculation could be very costly. 2279 * Align to the smaller of: 2280 * - first set bit in overlap of (pa & size mask) 2281 * - largest size envelope 2282 * 2283 * It's possible the device mapping may start at a PA that's not larger 2284 * than the size mask, so we need to offset in to maximize the TLB entry 2285 * range and minimize the number of used TLB entries. 2286 */ 2287 do { 2288 tmpva = tlb1_map_base; 2289 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa); 2290 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1; 2291 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa); 2292 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 2293 #endif 2294 va = atomic_fetchadd_int(&tlb1_map_base, size); 2295 retva = va; 2296 #endif 2297 2298 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size) 2299 return (NULL); 2300 2301 return ((void *)retva); 2302 } 2303 2304 /* 2305 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2306 */ 2307 static void 2308 mmu_booke_unmapdev(vm_offset_t va, vm_size_t size) 2309 { 2310 #ifdef SUPPORTS_SHRINKING_TLB1 2311 vm_offset_t base, offset; 2312 2313 /* 2314 * Unmap only if this is inside kernel virtual space. 2315 */ 2316 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2317 base = trunc_page(va); 2318 offset = va & PAGE_MASK; 2319 size = roundup(offset + size, PAGE_SIZE); 2320 mmu_booke_qremove(base, atop(size)); 2321 kva_free(base, size); 2322 } 2323 #endif 2324 } 2325 2326 /* 2327 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2328 * specified pmap. This eliminates the blast of soft faults on process startup 2329 * and immediately after an mmap. 2330 */ 2331 static void 2332 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr, 2333 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2334 { 2335 2336 VM_OBJECT_ASSERT_WLOCKED(object); 2337 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2338 ("mmu_booke_object_init_pt: non-device object")); 2339 } 2340 2341 /* 2342 * Perform the pmap work for mincore. 2343 */ 2344 static int 2345 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 2346 { 2347 2348 /* XXX: this should be implemented at some point */ 2349 return (0); 2350 } 2351 2352 static int 2353 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode) 2354 { 2355 vm_offset_t va; 2356 pte_t *pte; 2357 int i, j; 2358 tlb_entry_t e; 2359 2360 addr = trunc_page(addr); 2361 2362 /* Only allow changes to mapped kernel addresses. This includes: 2363 * - KVA 2364 * - DMAP (powerpc64) 2365 * - Device mappings 2366 */ 2367 if (addr <= VM_MAXUSER_ADDRESS || 2368 #ifdef __powerpc64__ 2369 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) || 2370 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) || 2371 #else 2372 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) || 2373 #endif 2374 (addr > VM_MAX_KERNEL_ADDRESS)) 2375 return (EINVAL); 2376 2377 /* Check TLB1 mappings */ 2378 for (i = 0; i < TLB1_ENTRIES; i++) { 2379 tlb1_read_entry(&e, i); 2380 if (!(e.mas1 & MAS1_VALID)) 2381 continue; 2382 if (addr >= e.virt && addr < e.virt + e.size) 2383 break; 2384 } 2385 if (i < TLB1_ENTRIES) { 2386 /* Only allow full mappings to be modified for now. */ 2387 /* Validate the range. */ 2388 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 2389 tlb1_read_entry(&e, j); 2390 if (va != e.virt || (sz - (va - addr) < e.size)) 2391 return (EINVAL); 2392 } 2393 for (va = addr; va < addr + sz; va += e.size, i++) { 2394 tlb1_read_entry(&e, i); 2395 e.mas2 &= ~MAS2_WIMGE_MASK; 2396 e.mas2 |= tlb_calc_wimg(e.phys, mode); 2397 2398 /* 2399 * Write it out to the TLB. Should really re-sync with other 2400 * cores. 2401 */ 2402 tlb1_write_entry(&e, i); 2403 } 2404 return (0); 2405 } 2406 2407 /* Not in TLB1, try through pmap */ 2408 /* First validate the range. */ 2409 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2410 pte = pte_find(kernel_pmap, va); 2411 if (pte == NULL || !PTE_ISVALID(pte)) 2412 return (EINVAL); 2413 } 2414 2415 mtx_lock_spin(&tlbivax_mutex); 2416 tlb_miss_lock(); 2417 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2418 pte = pte_find(kernel_pmap, va); 2419 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2420 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 2421 tlb0_flush_entry(va); 2422 } 2423 tlb_miss_unlock(); 2424 mtx_unlock_spin(&tlbivax_mutex); 2425 2426 return (0); 2427 } 2428 2429 static void 2430 mmu_booke_page_array_startup(long pages) 2431 { 2432 vm_page_array_size = pages; 2433 } 2434 2435 /**************************************************************************/ 2436 /* TID handling */ 2437 /**************************************************************************/ 2438 2439 /* 2440 * Allocate a TID. If necessary, steal one from someone else. 2441 * The new TID is flushed from the TLB before returning. 2442 */ 2443 static tlbtid_t 2444 tid_alloc(pmap_t pmap) 2445 { 2446 tlbtid_t tid; 2447 int thiscpu; 2448 2449 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2450 2451 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2452 2453 thiscpu = PCPU_GET(cpuid); 2454 2455 tid = PCPU_GET(booke.tid_next); 2456 if (tid > TID_MAX) 2457 tid = TID_MIN; 2458 PCPU_SET(booke.tid_next, tid + 1); 2459 2460 /* If we are stealing TID then clear the relevant pmap's field */ 2461 if (tidbusy[thiscpu][tid] != NULL) { 2462 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2463 2464 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2465 2466 /* Flush all entries from TLB0 matching this TID. */ 2467 tid_flush(tid); 2468 } 2469 2470 tidbusy[thiscpu][tid] = pmap; 2471 pmap->pm_tid[thiscpu] = tid; 2472 __asm __volatile("msync; isync"); 2473 2474 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2475 PCPU_GET(booke.tid_next)); 2476 2477 return (tid); 2478 } 2479 2480 /**************************************************************************/ 2481 /* TLB0 handling */ 2482 /**************************************************************************/ 2483 2484 /* Convert TLB0 va and way number to tlb0[] table index. */ 2485 static inline unsigned int 2486 tlb0_tableidx(vm_offset_t va, unsigned int way) 2487 { 2488 unsigned int idx; 2489 2490 idx = (way * TLB0_ENTRIES_PER_WAY); 2491 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2492 return (idx); 2493 } 2494 2495 /* 2496 * Invalidate TLB0 entry. 2497 */ 2498 static inline void 2499 tlb0_flush_entry(vm_offset_t va) 2500 { 2501 2502 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2503 2504 mtx_assert(&tlbivax_mutex, MA_OWNED); 2505 2506 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2507 __asm __volatile("isync; msync"); 2508 __asm __volatile("tlbsync; msync"); 2509 2510 CTR1(KTR_PMAP, "%s: e", __func__); 2511 } 2512 2513 /**************************************************************************/ 2514 /* TLB1 handling */ 2515 /**************************************************************************/ 2516 2517 /* 2518 * TLB1 mapping notes: 2519 * 2520 * TLB1[0] Kernel text and data. 2521 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2522 * windows, other devices mappings. 2523 */ 2524 2525 /* 2526 * Read an entry from given TLB1 slot. 2527 */ 2528 void 2529 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 2530 { 2531 register_t msr; 2532 uint32_t mas0; 2533 2534 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 2535 2536 msr = mfmsr(); 2537 __asm __volatile("wrteei 0"); 2538 2539 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 2540 mtspr(SPR_MAS0, mas0); 2541 __asm __volatile("isync; tlbre"); 2542 2543 entry->mas1 = mfspr(SPR_MAS1); 2544 entry->mas2 = mfspr(SPR_MAS2); 2545 entry->mas3 = mfspr(SPR_MAS3); 2546 2547 switch ((mfpvr() >> 16) & 0xFFFF) { 2548 case FSL_E500v2: 2549 case FSL_E500mc: 2550 case FSL_E5500: 2551 case FSL_E6500: 2552 entry->mas7 = mfspr(SPR_MAS7); 2553 break; 2554 default: 2555 entry->mas7 = 0; 2556 break; 2557 } 2558 __asm __volatile("wrtee %0" :: "r"(msr)); 2559 2560 entry->virt = entry->mas2 & MAS2_EPN_MASK; 2561 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 2562 (entry->mas3 & MAS3_RPN); 2563 entry->size = 2564 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 2565 } 2566 2567 struct tlbwrite_args { 2568 tlb_entry_t *e; 2569 unsigned int idx; 2570 }; 2571 2572 static uint32_t 2573 tlb1_find_free(void) 2574 { 2575 tlb_entry_t e; 2576 int i; 2577 2578 for (i = 0; i < TLB1_ENTRIES; i++) { 2579 tlb1_read_entry(&e, i); 2580 if ((e.mas1 & MAS1_VALID) == 0) 2581 return (i); 2582 } 2583 return (-1); 2584 } 2585 2586 static void 2587 tlb1_purge_va_range(vm_offset_t va, vm_size_t size) 2588 { 2589 tlb_entry_t e; 2590 int i; 2591 2592 for (i = 0; i < TLB1_ENTRIES; i++) { 2593 tlb1_read_entry(&e, i); 2594 if ((e.mas1 & MAS1_VALID) == 0) 2595 continue; 2596 if ((e.mas2 & MAS2_EPN_MASK) >= va && 2597 (e.mas2 & MAS2_EPN_MASK) < va + size) { 2598 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID); 2599 __asm __volatile("isync; tlbwe; isync; msync"); 2600 } 2601 } 2602 } 2603 2604 static void 2605 tlb1_write_entry_int(void *arg) 2606 { 2607 struct tlbwrite_args *args = arg; 2608 uint32_t idx, mas0; 2609 2610 idx = args->idx; 2611 if (idx == -1) { 2612 tlb1_purge_va_range(args->e->virt, args->e->size); 2613 idx = tlb1_find_free(); 2614 if (idx == -1) 2615 panic("No free TLB1 entries!\n"); 2616 } 2617 /* Select entry */ 2618 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2619 2620 mtspr(SPR_MAS0, mas0); 2621 mtspr(SPR_MAS1, args->e->mas1); 2622 mtspr(SPR_MAS2, args->e->mas2); 2623 mtspr(SPR_MAS3, args->e->mas3); 2624 switch ((mfpvr() >> 16) & 0xFFFF) { 2625 case FSL_E500mc: 2626 case FSL_E5500: 2627 case FSL_E6500: 2628 mtspr(SPR_MAS8, 0); 2629 /* FALLTHROUGH */ 2630 case FSL_E500v2: 2631 mtspr(SPR_MAS7, args->e->mas7); 2632 break; 2633 default: 2634 break; 2635 } 2636 2637 __asm __volatile("isync; tlbwe; isync; msync"); 2638 2639 } 2640 2641 static void 2642 tlb1_write_entry_sync(void *arg) 2643 { 2644 /* Empty synchronization point for smp_rendezvous(). */ 2645 } 2646 2647 /* 2648 * Write given entry to TLB1 hardware. 2649 */ 2650 static void 2651 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 2652 { 2653 struct tlbwrite_args args; 2654 2655 args.e = e; 2656 args.idx = idx; 2657 2658 #ifdef SMP 2659 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) { 2660 mb(); 2661 smp_rendezvous(tlb1_write_entry_sync, 2662 tlb1_write_entry_int, 2663 tlb1_write_entry_sync, &args); 2664 } else 2665 #endif 2666 { 2667 register_t msr; 2668 2669 msr = mfmsr(); 2670 __asm __volatile("wrteei 0"); 2671 tlb1_write_entry_int(&args); 2672 __asm __volatile("wrtee %0" :: "r"(msr)); 2673 } 2674 } 2675 2676 /* 2677 * Convert TLB TSIZE value to mapped region size. 2678 */ 2679 static vm_size_t 2680 tsize2size(unsigned int tsize) 2681 { 2682 2683 /* 2684 * size = 4^tsize KB 2685 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2686 */ 2687 2688 return ((1 << (2 * tsize)) * 1024); 2689 } 2690 2691 /* 2692 * Convert region size (must be power of 4) to TLB TSIZE value. 2693 */ 2694 static unsigned int 2695 size2tsize(vm_size_t size) 2696 { 2697 2698 return (ilog2(size) / 2 - 5); 2699 } 2700 2701 /* 2702 * Register permanent kernel mapping in TLB1. 2703 * 2704 * Entries are created starting from index 0 (current free entry is 2705 * kept in tlb1_idx) and are not supposed to be invalidated. 2706 */ 2707 int 2708 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 2709 uint32_t flags) 2710 { 2711 tlb_entry_t e; 2712 uint32_t ts, tid; 2713 int tsize, index; 2714 2715 /* First try to update an existing entry. */ 2716 for (index = 0; index < TLB1_ENTRIES; index++) { 2717 tlb1_read_entry(&e, index); 2718 /* Check if we're just updating the flags, and update them. */ 2719 if (e.phys == pa && e.virt == va && e.size == size) { 2720 e.mas2 = (va & MAS2_EPN_MASK) | flags; 2721 tlb1_write_entry(&e, index); 2722 return (0); 2723 } 2724 } 2725 2726 /* Convert size to TSIZE */ 2727 tsize = size2tsize(size); 2728 2729 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2730 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2731 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2732 2733 e.phys = pa; 2734 e.virt = va; 2735 e.size = size; 2736 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2737 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2738 e.mas2 = (va & MAS2_EPN_MASK) | flags; 2739 2740 /* Set supervisor RWX permission bits */ 2741 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2742 e.mas7 = (pa >> 32) & MAS7_RPN; 2743 2744 tlb1_write_entry(&e, -1); 2745 2746 return (0); 2747 } 2748 2749 /* 2750 * Map in contiguous RAM region into the TLB1. 2751 */ 2752 static vm_size_t 2753 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge) 2754 { 2755 vm_offset_t base; 2756 vm_size_t mapped, sz, ssize; 2757 2758 mapped = 0; 2759 base = va; 2760 ssize = size; 2761 2762 while (size > 0) { 2763 sz = 1UL << (ilog2(size) & ~1); 2764 /* Align size to PA */ 2765 if (pa % sz != 0) { 2766 do { 2767 sz >>= 2; 2768 } while (pa % sz != 0); 2769 } 2770 /* Now align from there to VA */ 2771 if (va % sz != 0) { 2772 do { 2773 sz >>= 2; 2774 } while (va % sz != 0); 2775 } 2776 #ifdef __powerpc64__ 2777 /* 2778 * Clamp TLB1 entries to 4G. 2779 * 2780 * While the e6500 supports up to 1TB mappings, the e5500 2781 * only supports up to 4G mappings. (0b1011) 2782 * 2783 * If any e6500 machines capable of supporting a very 2784 * large amount of memory appear in the future, we can 2785 * revisit this. 2786 * 2787 * For now, though, since we have plenty of space in TLB1, 2788 * always avoid creating entries larger than 4GB. 2789 */ 2790 sz = MIN(sz, 1UL << 32); 2791 #endif 2792 if (bootverbose) 2793 printf("Wiring VA=%p to PA=%jx (size=%lx)\n", 2794 (void *)va, (uintmax_t)pa, (long)sz); 2795 if (tlb1_set_entry(va, pa, sz, 2796 _TLB_ENTRY_SHARED | wimge) < 0) 2797 return (mapped); 2798 size -= sz; 2799 pa += sz; 2800 va += sz; 2801 } 2802 2803 mapped = (va - base); 2804 if (bootverbose) 2805 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n", 2806 mapped, mapped - ssize); 2807 2808 return (mapped); 2809 } 2810 2811 /* 2812 * TLB1 initialization routine, to be called after the very first 2813 * assembler level setup done in locore.S. 2814 */ 2815 void 2816 tlb1_init() 2817 { 2818 vm_offset_t mas2; 2819 uint32_t mas0, mas1, mas3, mas7; 2820 uint32_t tsz; 2821 2822 tlb1_get_tlbconf(); 2823 2824 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 2825 mtspr(SPR_MAS0, mas0); 2826 __asm __volatile("isync; tlbre"); 2827 2828 mas1 = mfspr(SPR_MAS1); 2829 mas2 = mfspr(SPR_MAS2); 2830 mas3 = mfspr(SPR_MAS3); 2831 mas7 = mfspr(SPR_MAS7); 2832 2833 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 2834 (mas3 & MAS3_RPN); 2835 2836 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2837 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 2838 kernstart = trunc_page(mas2); 2839 2840 /* Setup TLB miss defaults */ 2841 set_mas4_defaults(); 2842 } 2843 2844 /* 2845 * pmap_early_io_unmap() should be used in short conjunction with 2846 * pmap_early_io_map(), as in the following snippet: 2847 * 2848 * x = pmap_early_io_map(...); 2849 * <do something with x> 2850 * pmap_early_io_unmap(x, size); 2851 * 2852 * And avoiding more allocations between. 2853 */ 2854 void 2855 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 2856 { 2857 int i; 2858 tlb_entry_t e; 2859 vm_size_t isize; 2860 2861 size = roundup(size, PAGE_SIZE); 2862 isize = size; 2863 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 2864 tlb1_read_entry(&e, i); 2865 if (!(e.mas1 & MAS1_VALID)) 2866 continue; 2867 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 2868 size -= e.size; 2869 e.mas1 &= ~MAS1_VALID; 2870 tlb1_write_entry(&e, i); 2871 } 2872 } 2873 if (tlb1_map_base == va + isize) 2874 tlb1_map_base -= isize; 2875 } 2876 2877 vm_offset_t 2878 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 2879 { 2880 vm_paddr_t pa_base; 2881 vm_offset_t va, sz; 2882 int i; 2883 tlb_entry_t e; 2884 2885 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 2886 2887 for (i = 0; i < TLB1_ENTRIES; i++) { 2888 tlb1_read_entry(&e, i); 2889 if (!(e.mas1 & MAS1_VALID)) 2890 continue; 2891 if (pa >= e.phys && (pa + size) <= 2892 (e.phys + e.size)) 2893 return (e.virt + (pa - e.phys)); 2894 } 2895 2896 pa_base = rounddown(pa, PAGE_SIZE); 2897 size = roundup(size + (pa - pa_base), PAGE_SIZE); 2898 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 2899 va = tlb1_map_base + (pa - pa_base); 2900 2901 do { 2902 sz = 1 << (ilog2(size) & ~1); 2903 tlb1_set_entry(tlb1_map_base, pa_base, sz, 2904 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 2905 size -= sz; 2906 pa_base += sz; 2907 tlb1_map_base += sz; 2908 } while (size > 0); 2909 2910 return (va); 2911 } 2912 2913 void 2914 pmap_track_page(pmap_t pmap, vm_offset_t va) 2915 { 2916 vm_paddr_t pa; 2917 vm_page_t page; 2918 struct pv_entry *pve; 2919 2920 va = trunc_page(va); 2921 pa = pmap_kextract(va); 2922 page = PHYS_TO_VM_PAGE(pa); 2923 2924 rw_wlock(&pvh_global_lock); 2925 PMAP_LOCK(pmap); 2926 2927 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 2928 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 2929 goto out; 2930 } 2931 } 2932 page->md.pv_tracked = true; 2933 pv_insert(pmap, va, page); 2934 out: 2935 PMAP_UNLOCK(pmap); 2936 rw_wunlock(&pvh_global_lock); 2937 } 2938 2939 /* 2940 * Setup MAS4 defaults. 2941 * These values are loaded to MAS0-2 on a TLB miss. 2942 */ 2943 static void 2944 set_mas4_defaults(void) 2945 { 2946 uint32_t mas4; 2947 2948 /* Defaults: TLB0, PID0, TSIZED=4K */ 2949 mas4 = MAS4_TLBSELD0; 2950 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 2951 #ifdef SMP 2952 mas4 |= MAS4_MD; 2953 #endif 2954 mtspr(SPR_MAS4, mas4); 2955 __asm __volatile("isync"); 2956 } 2957 2958 /* 2959 * Return 0 if the physical IO range is encompassed by one of the 2960 * the TLB1 entries, otherwise return related error code. 2961 */ 2962 static int 2963 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 2964 { 2965 uint32_t prot; 2966 vm_paddr_t pa_start; 2967 vm_paddr_t pa_end; 2968 unsigned int entry_tsize; 2969 vm_size_t entry_size; 2970 tlb_entry_t e; 2971 2972 *va = (vm_offset_t)NULL; 2973 2974 tlb1_read_entry(&e, i); 2975 /* Skip invalid entries */ 2976 if (!(e.mas1 & MAS1_VALID)) 2977 return (EINVAL); 2978 2979 /* 2980 * The entry must be cache-inhibited, guarded, and r/w 2981 * so it can function as an i/o page 2982 */ 2983 prot = e.mas2 & (MAS2_I | MAS2_G); 2984 if (prot != (MAS2_I | MAS2_G)) 2985 return (EPERM); 2986 2987 prot = e.mas3 & (MAS3_SR | MAS3_SW); 2988 if (prot != (MAS3_SR | MAS3_SW)) 2989 return (EPERM); 2990 2991 /* The address should be within the entry range. */ 2992 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2993 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 2994 2995 entry_size = tsize2size(entry_tsize); 2996 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 2997 (e.mas3 & MAS3_RPN); 2998 pa_end = pa_start + entry_size; 2999 3000 if ((pa < pa_start) || ((pa + size) > pa_end)) 3001 return (ERANGE); 3002 3003 /* Return virtual address of this mapping. */ 3004 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3005 return (0); 3006 } 3007 3008 #ifdef DDB 3009 /* Print out contents of the MAS registers for each TLB0 entry */ 3010 static void 3011 #ifdef __powerpc64__ 3012 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3, 3013 #else 3014 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3015 #endif 3016 uint32_t mas7) 3017 { 3018 int as; 3019 char desc[3]; 3020 tlbtid_t tid; 3021 vm_size_t size; 3022 unsigned int tsize; 3023 3024 desc[2] = '\0'; 3025 if (mas1 & MAS1_VALID) 3026 desc[0] = 'V'; 3027 else 3028 desc[0] = ' '; 3029 3030 if (mas1 & MAS1_IPROT) 3031 desc[1] = 'P'; 3032 else 3033 desc[1] = ' '; 3034 3035 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3036 tid = MAS1_GETTID(mas1); 3037 3038 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3039 size = 0; 3040 if (tsize) 3041 size = tsize2size(tsize); 3042 3043 printf("%3d: (%s) [AS=%d] " 3044 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x " 3045 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3046 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7); 3047 } 3048 3049 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries) 3050 { 3051 uint32_t mas0, mas1, mas3, mas7; 3052 #ifdef __powerpc64__ 3053 uint64_t mas2; 3054 #else 3055 uint32_t mas2; 3056 #endif 3057 int entryidx, way, idx; 3058 3059 printf("TLB0 entries:\n"); 3060 for (way = 0; way < TLB0_WAYS; way ++) 3061 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3062 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3063 mtspr(SPR_MAS0, mas0); 3064 3065 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3066 mtspr(SPR_MAS2, mas2); 3067 3068 __asm __volatile("isync; tlbre"); 3069 3070 mas1 = mfspr(SPR_MAS1); 3071 mas2 = mfspr(SPR_MAS2); 3072 mas3 = mfspr(SPR_MAS3); 3073 mas7 = mfspr(SPR_MAS7); 3074 3075 idx = tlb0_tableidx(mas2, way); 3076 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3077 } 3078 } 3079 3080 /* 3081 * Print out contents of the MAS registers for each TLB1 entry 3082 */ 3083 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries) 3084 { 3085 uint32_t mas0, mas1, mas3, mas7; 3086 #ifdef __powerpc64__ 3087 uint64_t mas2; 3088 #else 3089 uint32_t mas2; 3090 #endif 3091 int i; 3092 3093 printf("TLB1 entries:\n"); 3094 for (i = 0; i < TLB1_ENTRIES; i++) { 3095 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3096 mtspr(SPR_MAS0, mas0); 3097 3098 __asm __volatile("isync; tlbre"); 3099 3100 mas1 = mfspr(SPR_MAS1); 3101 mas2 = mfspr(SPR_MAS2); 3102 mas3 = mfspr(SPR_MAS3); 3103 mas7 = mfspr(SPR_MAS7); 3104 3105 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3106 } 3107 } 3108 #endif 3109