1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include <sys/param.h> 55 #include <sys/malloc.h> 56 #include <sys/ktr.h> 57 #include <sys/proc.h> 58 #include <sys/user.h> 59 #include <sys/queue.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/linker.h> 63 #include <sys/msgbuf.h> 64 #include <sys/lock.h> 65 #include <sys/mutex.h> 66 #include <sys/rwlock.h> 67 #include <sys/sched.h> 68 #include <sys/smp.h> 69 #include <sys/vmmeter.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_page.h> 73 #include <vm/vm_kern.h> 74 #include <vm/vm_pageout.h> 75 #include <vm/vm_extern.h> 76 #include <vm/vm_object.h> 77 #include <vm/vm_param.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_pager.h> 80 #include <vm/uma.h> 81 82 #include <machine/cpu.h> 83 #include <machine/pcb.h> 84 #include <machine/platform.h> 85 86 #include <machine/tlb.h> 87 #include <machine/spr.h> 88 #include <machine/md_var.h> 89 #include <machine/mmuvar.h> 90 #include <machine/pmap.h> 91 #include <machine/pte.h> 92 93 #include "mmu_if.h" 94 95 #ifdef DEBUG 96 #define debugf(fmt, args...) printf(fmt, ##args) 97 #else 98 #define debugf(fmt, args...) 99 #endif 100 101 #define TODO panic("%s: not implemented", __func__); 102 103 extern int dumpsys_minidump; 104 105 extern unsigned char _etext[]; 106 extern unsigned char _end[]; 107 108 extern uint32_t *bootinfo; 109 110 #ifdef SMP 111 extern uint32_t bp_ntlb1s; 112 #endif 113 114 vm_paddr_t kernload; 115 vm_offset_t kernstart; 116 vm_size_t kernsize; 117 118 /* Message buffer and tables. */ 119 static vm_offset_t data_start; 120 static vm_size_t data_end; 121 122 /* Phys/avail memory regions. */ 123 static struct mem_region *availmem_regions; 124 static int availmem_regions_sz; 125 static struct mem_region *physmem_regions; 126 static int physmem_regions_sz; 127 128 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 129 static vm_offset_t zero_page_va; 130 static struct mtx zero_page_mutex; 131 132 static struct mtx tlbivax_mutex; 133 134 /* 135 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 136 * by idle thred only, no lock required. 137 */ 138 static vm_offset_t zero_page_idle_va; 139 140 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 141 static vm_offset_t copy_page_src_va; 142 static vm_offset_t copy_page_dst_va; 143 static struct mtx copy_page_mutex; 144 145 /**************************************************************************/ 146 /* PMAP */ 147 /**************************************************************************/ 148 149 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 150 vm_prot_t, boolean_t); 151 152 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 153 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 154 155 /* 156 * If user pmap is processed with mmu_booke_remove and the resident count 157 * drops to 0, there are no more pages to remove, so we need not continue. 158 */ 159 #define PMAP_REMOVE_DONE(pmap) \ 160 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 161 162 extern void tid_flush(tlbtid_t); 163 164 /**************************************************************************/ 165 /* TLB and TID handling */ 166 /**************************************************************************/ 167 168 /* Translation ID busy table */ 169 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 170 171 /* 172 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 173 * core revisions and should be read from h/w registers during early config. 174 */ 175 uint32_t tlb0_entries; 176 uint32_t tlb0_ways; 177 uint32_t tlb0_entries_per_way; 178 179 #define TLB0_ENTRIES (tlb0_entries) 180 #define TLB0_WAYS (tlb0_ways) 181 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 182 183 #define TLB1_ENTRIES 16 184 185 /* In-ram copy of the TLB1 */ 186 static tlb_entry_t tlb1[TLB1_ENTRIES]; 187 188 /* Next free entry in the TLB1 */ 189 static unsigned int tlb1_idx; 190 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 191 192 static tlbtid_t tid_alloc(struct pmap *); 193 194 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 195 196 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 197 static void tlb1_write_entry(unsigned int); 198 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 199 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 200 201 static vm_size_t tsize2size(unsigned int); 202 static unsigned int size2tsize(vm_size_t); 203 static unsigned int ilog2(unsigned int); 204 205 static void set_mas4_defaults(void); 206 207 static inline void tlb0_flush_entry(vm_offset_t); 208 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 209 210 /**************************************************************************/ 211 /* Page table management */ 212 /**************************************************************************/ 213 214 static struct rwlock_padalign pvh_global_lock; 215 216 /* Data for the pv entry allocation mechanism */ 217 static uma_zone_t pvzone; 218 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 219 220 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 221 222 #ifndef PMAP_SHPGPERPROC 223 #define PMAP_SHPGPERPROC 200 224 #endif 225 226 static void ptbl_init(void); 227 static struct ptbl_buf *ptbl_buf_alloc(void); 228 static void ptbl_buf_free(struct ptbl_buf *); 229 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 230 231 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 232 static void ptbl_free(mmu_t, pmap_t, unsigned int); 233 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 234 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 235 236 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 237 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 238 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 239 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 240 241 static pv_entry_t pv_alloc(void); 242 static void pv_free(pv_entry_t); 243 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 244 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 245 246 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 247 #define PTBL_BUFS (128 * 16) 248 249 struct ptbl_buf { 250 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 251 vm_offset_t kva; /* va of mapping */ 252 }; 253 254 /* ptbl free list and a lock used for access synchronization. */ 255 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 256 static struct mtx ptbl_buf_freelist_lock; 257 258 /* Base address of kva space allocated fot ptbl bufs. */ 259 static vm_offset_t ptbl_buf_pool_vabase; 260 261 /* Pointer to ptbl_buf structures. */ 262 static struct ptbl_buf *ptbl_bufs; 263 264 void pmap_bootstrap_ap(volatile uint32_t *); 265 266 /* 267 * Kernel MMU interface 268 */ 269 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 270 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 271 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 272 vm_size_t, vm_offset_t); 273 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 274 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 275 vm_offset_t, vm_page_t *, vm_offset_t, int); 276 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 277 vm_prot_t, boolean_t); 278 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 279 vm_page_t, vm_prot_t); 280 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 283 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 284 vm_prot_t); 285 static void mmu_booke_init(mmu_t); 286 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 287 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 289 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 290 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 291 int); 292 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 293 vm_paddr_t *); 294 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 295 vm_object_t, vm_pindex_t, vm_size_t); 296 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297 static void mmu_booke_page_init(mmu_t, vm_page_t); 298 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 299 static void mmu_booke_pinit(mmu_t, pmap_t); 300 static void mmu_booke_pinit0(mmu_t, pmap_t); 301 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 302 vm_prot_t); 303 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 305 static void mmu_booke_release(mmu_t, pmap_t); 306 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307 static void mmu_booke_remove_all(mmu_t, vm_page_t); 308 static void mmu_booke_remove_write(mmu_t, vm_page_t); 309 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 310 static void mmu_booke_zero_page(mmu_t, vm_page_t); 311 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 312 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 313 static void mmu_booke_activate(mmu_t, struct thread *); 314 static void mmu_booke_deactivate(mmu_t, struct thread *); 315 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 316 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 317 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 318 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 319 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 320 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 321 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 322 static void mmu_booke_kremove(mmu_t, vm_offset_t); 323 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 324 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 325 vm_size_t); 326 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 327 vm_size_t, vm_size_t *); 328 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 329 vm_size_t, vm_offset_t); 330 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 331 332 static mmu_method_t mmu_booke_methods[] = { 333 /* pmap dispatcher interface */ 334 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 335 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 336 MMUMETHOD(mmu_copy, mmu_booke_copy), 337 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 338 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 339 MMUMETHOD(mmu_enter, mmu_booke_enter), 340 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 341 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 342 MMUMETHOD(mmu_extract, mmu_booke_extract), 343 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 344 MMUMETHOD(mmu_init, mmu_booke_init), 345 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 346 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 347 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 348 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 349 MMUMETHOD(mmu_map, mmu_booke_map), 350 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 351 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 352 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 353 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 354 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 355 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 356 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 357 MMUMETHOD(mmu_protect, mmu_booke_protect), 358 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 359 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 360 MMUMETHOD(mmu_release, mmu_booke_release), 361 MMUMETHOD(mmu_remove, mmu_booke_remove), 362 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 363 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 364 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 365 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 369 MMUMETHOD(mmu_activate, mmu_booke_activate), 370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 377 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 378 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 379 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 380 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 381 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 382 383 /* dumpsys() support */ 384 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 385 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 386 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 387 388 { 0, 0 } 389 }; 390 391 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 392 393 static __inline uint32_t 394 tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 395 { 396 uint32_t attrib; 397 int i; 398 399 if (ma != VM_MEMATTR_DEFAULT) { 400 switch (ma) { 401 case VM_MEMATTR_UNCACHEABLE: 402 return (PTE_I | PTE_G); 403 case VM_MEMATTR_WRITE_COMBINING: 404 case VM_MEMATTR_WRITE_BACK: 405 case VM_MEMATTR_PREFETCHABLE: 406 return (PTE_I); 407 case VM_MEMATTR_WRITE_THROUGH: 408 return (PTE_W | PTE_M); 409 } 410 } 411 412 /* 413 * Assume the page is cache inhibited and access is guarded unless 414 * it's in our available memory array. 415 */ 416 attrib = _TLB_ENTRY_IO; 417 for (i = 0; i < physmem_regions_sz; i++) { 418 if ((pa >= physmem_regions[i].mr_start) && 419 (pa < (physmem_regions[i].mr_start + 420 physmem_regions[i].mr_size))) { 421 attrib = _TLB_ENTRY_MEM; 422 break; 423 } 424 } 425 426 return (attrib); 427 } 428 429 static inline void 430 tlb_miss_lock(void) 431 { 432 #ifdef SMP 433 struct pcpu *pc; 434 435 if (!smp_started) 436 return; 437 438 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 439 if (pc != pcpup) { 440 441 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 442 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 443 444 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 445 ("tlb_miss_lock: tried to lock self")); 446 447 tlb_lock(pc->pc_booke_tlb_lock); 448 449 CTR1(KTR_PMAP, "%s: locked", __func__); 450 } 451 } 452 #endif 453 } 454 455 static inline void 456 tlb_miss_unlock(void) 457 { 458 #ifdef SMP 459 struct pcpu *pc; 460 461 if (!smp_started) 462 return; 463 464 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 465 if (pc != pcpup) { 466 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 467 __func__, pc->pc_cpuid); 468 469 tlb_unlock(pc->pc_booke_tlb_lock); 470 471 CTR1(KTR_PMAP, "%s: unlocked", __func__); 472 } 473 } 474 #endif 475 } 476 477 /* Return number of entries in TLB0. */ 478 static __inline void 479 tlb0_get_tlbconf(void) 480 { 481 uint32_t tlb0_cfg; 482 483 tlb0_cfg = mfspr(SPR_TLB0CFG); 484 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 485 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 486 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 487 } 488 489 /* Initialize pool of kva ptbl buffers. */ 490 static void 491 ptbl_init(void) 492 { 493 int i; 494 495 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 496 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 497 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 498 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 499 500 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 501 TAILQ_INIT(&ptbl_buf_freelist); 502 503 for (i = 0; i < PTBL_BUFS; i++) { 504 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 505 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 506 } 507 } 508 509 /* Get a ptbl_buf from the freelist. */ 510 static struct ptbl_buf * 511 ptbl_buf_alloc(void) 512 { 513 struct ptbl_buf *buf; 514 515 mtx_lock(&ptbl_buf_freelist_lock); 516 buf = TAILQ_FIRST(&ptbl_buf_freelist); 517 if (buf != NULL) 518 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 519 mtx_unlock(&ptbl_buf_freelist_lock); 520 521 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 522 523 return (buf); 524 } 525 526 /* Return ptbl buff to free pool. */ 527 static void 528 ptbl_buf_free(struct ptbl_buf *buf) 529 { 530 531 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 532 533 mtx_lock(&ptbl_buf_freelist_lock); 534 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 535 mtx_unlock(&ptbl_buf_freelist_lock); 536 } 537 538 /* 539 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 540 */ 541 static void 542 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 543 { 544 struct ptbl_buf *pbuf; 545 546 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 547 548 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 549 550 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 551 if (pbuf->kva == (vm_offset_t)ptbl) { 552 /* Remove from pmap ptbl buf list. */ 553 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 554 555 /* Free corresponding ptbl buf. */ 556 ptbl_buf_free(pbuf); 557 break; 558 } 559 } 560 561 /* Allocate page table. */ 562 static pte_t * 563 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 564 { 565 vm_page_t mtbl[PTBL_PAGES]; 566 vm_page_t m; 567 struct ptbl_buf *pbuf; 568 unsigned int pidx; 569 pte_t *ptbl; 570 int i; 571 572 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 573 (pmap == kernel_pmap), pdir_idx); 574 575 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 576 ("ptbl_alloc: invalid pdir_idx")); 577 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 578 ("pte_alloc: valid ptbl entry exists!")); 579 580 pbuf = ptbl_buf_alloc(); 581 if (pbuf == NULL) 582 panic("pte_alloc: couldn't alloc kernel virtual memory"); 583 584 ptbl = (pte_t *)pbuf->kva; 585 586 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 587 588 /* Allocate ptbl pages, this will sleep! */ 589 for (i = 0; i < PTBL_PAGES; i++) { 590 pidx = (PTBL_PAGES * pdir_idx) + i; 591 while ((m = vm_page_alloc(NULL, pidx, 592 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 593 594 PMAP_UNLOCK(pmap); 595 rw_wunlock(&pvh_global_lock); 596 VM_WAIT; 597 rw_wlock(&pvh_global_lock); 598 PMAP_LOCK(pmap); 599 } 600 mtbl[i] = m; 601 } 602 603 /* Map allocated pages into kernel_pmap. */ 604 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 605 606 /* Zero whole ptbl. */ 607 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 608 609 /* Add pbuf to the pmap ptbl bufs list. */ 610 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 611 612 return (ptbl); 613 } 614 615 /* Free ptbl pages and invalidate pdir entry. */ 616 static void 617 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 618 { 619 pte_t *ptbl; 620 vm_paddr_t pa; 621 vm_offset_t va; 622 vm_page_t m; 623 int i; 624 625 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 626 (pmap == kernel_pmap), pdir_idx); 627 628 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 629 ("ptbl_free: invalid pdir_idx")); 630 631 ptbl = pmap->pm_pdir[pdir_idx]; 632 633 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 634 635 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 636 637 /* 638 * Invalidate the pdir entry as soon as possible, so that other CPUs 639 * don't attempt to look up the page tables we are releasing. 640 */ 641 mtx_lock_spin(&tlbivax_mutex); 642 tlb_miss_lock(); 643 644 pmap->pm_pdir[pdir_idx] = NULL; 645 646 tlb_miss_unlock(); 647 mtx_unlock_spin(&tlbivax_mutex); 648 649 for (i = 0; i < PTBL_PAGES; i++) { 650 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 651 pa = pte_vatopa(mmu, kernel_pmap, va); 652 m = PHYS_TO_VM_PAGE(pa); 653 vm_page_free_zero(m); 654 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 655 mmu_booke_kremove(mmu, va); 656 } 657 658 ptbl_free_pmap_ptbl(pmap, ptbl); 659 } 660 661 /* 662 * Decrement ptbl pages hold count and attempt to free ptbl pages. 663 * Called when removing pte entry from ptbl. 664 * 665 * Return 1 if ptbl pages were freed. 666 */ 667 static int 668 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 669 { 670 pte_t *ptbl; 671 vm_paddr_t pa; 672 vm_page_t m; 673 int i; 674 675 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 676 (pmap == kernel_pmap), pdir_idx); 677 678 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 679 ("ptbl_unhold: invalid pdir_idx")); 680 KASSERT((pmap != kernel_pmap), 681 ("ptbl_unhold: unholding kernel ptbl!")); 682 683 ptbl = pmap->pm_pdir[pdir_idx]; 684 685 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 686 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 687 ("ptbl_unhold: non kva ptbl")); 688 689 /* decrement hold count */ 690 for (i = 0; i < PTBL_PAGES; i++) { 691 pa = pte_vatopa(mmu, kernel_pmap, 692 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 693 m = PHYS_TO_VM_PAGE(pa); 694 m->wire_count--; 695 } 696 697 /* 698 * Free ptbl pages if there are no pte etries in this ptbl. 699 * wire_count has the same value for all ptbl pages, so check the last 700 * page. 701 */ 702 if (m->wire_count == 0) { 703 ptbl_free(mmu, pmap, pdir_idx); 704 705 //debugf("ptbl_unhold: e (freed ptbl)\n"); 706 return (1); 707 } 708 709 return (0); 710 } 711 712 /* 713 * Increment hold count for ptbl pages. This routine is used when a new pte 714 * entry is being inserted into the ptbl. 715 */ 716 static void 717 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 718 { 719 vm_paddr_t pa; 720 pte_t *ptbl; 721 vm_page_t m; 722 int i; 723 724 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 725 pdir_idx); 726 727 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 728 ("ptbl_hold: invalid pdir_idx")); 729 KASSERT((pmap != kernel_pmap), 730 ("ptbl_hold: holding kernel ptbl!")); 731 732 ptbl = pmap->pm_pdir[pdir_idx]; 733 734 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 735 736 for (i = 0; i < PTBL_PAGES; i++) { 737 pa = pte_vatopa(mmu, kernel_pmap, 738 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 739 m = PHYS_TO_VM_PAGE(pa); 740 m->wire_count++; 741 } 742 } 743 744 /* Allocate pv_entry structure. */ 745 pv_entry_t 746 pv_alloc(void) 747 { 748 pv_entry_t pv; 749 750 pv_entry_count++; 751 if (pv_entry_count > pv_entry_high_water) 752 pagedaemon_wakeup(); 753 pv = uma_zalloc(pvzone, M_NOWAIT); 754 755 return (pv); 756 } 757 758 /* Free pv_entry structure. */ 759 static __inline void 760 pv_free(pv_entry_t pve) 761 { 762 763 pv_entry_count--; 764 uma_zfree(pvzone, pve); 765 } 766 767 768 /* Allocate and initialize pv_entry structure. */ 769 static void 770 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 771 { 772 pv_entry_t pve; 773 774 //int su = (pmap == kernel_pmap); 775 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 776 // (u_int32_t)pmap, va, (u_int32_t)m); 777 778 pve = pv_alloc(); 779 if (pve == NULL) 780 panic("pv_insert: no pv entries!"); 781 782 pve->pv_pmap = pmap; 783 pve->pv_va = va; 784 785 /* add to pv_list */ 786 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 787 rw_assert(&pvh_global_lock, RA_WLOCKED); 788 789 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 790 791 //debugf("pv_insert: e\n"); 792 } 793 794 /* Destroy pv entry. */ 795 static void 796 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 797 { 798 pv_entry_t pve; 799 800 //int su = (pmap == kernel_pmap); 801 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 802 803 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 804 rw_assert(&pvh_global_lock, RA_WLOCKED); 805 806 /* find pv entry */ 807 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 808 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 809 /* remove from pv_list */ 810 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 811 if (TAILQ_EMPTY(&m->md.pv_list)) 812 vm_page_aflag_clear(m, PGA_WRITEABLE); 813 814 /* free pv entry struct */ 815 pv_free(pve); 816 break; 817 } 818 } 819 820 //debugf("pv_remove: e\n"); 821 } 822 823 /* 824 * Clean pte entry, try to free page table page if requested. 825 * 826 * Return 1 if ptbl pages were freed, otherwise return 0. 827 */ 828 static int 829 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 830 { 831 unsigned int pdir_idx = PDIR_IDX(va); 832 unsigned int ptbl_idx = PTBL_IDX(va); 833 vm_page_t m; 834 pte_t *ptbl; 835 pte_t *pte; 836 837 //int su = (pmap == kernel_pmap); 838 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 839 // su, (u_int32_t)pmap, va, flags); 840 841 ptbl = pmap->pm_pdir[pdir_idx]; 842 KASSERT(ptbl, ("pte_remove: null ptbl")); 843 844 pte = &ptbl[ptbl_idx]; 845 846 if (pte == NULL || !PTE_ISVALID(pte)) 847 return (0); 848 849 if (PTE_ISWIRED(pte)) 850 pmap->pm_stats.wired_count--; 851 852 /* Handle managed entry. */ 853 if (PTE_ISMANAGED(pte)) { 854 /* Get vm_page_t for mapped pte. */ 855 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 856 857 if (PTE_ISMODIFIED(pte)) 858 vm_page_dirty(m); 859 860 if (PTE_ISREFERENCED(pte)) 861 vm_page_aflag_set(m, PGA_REFERENCED); 862 863 pv_remove(pmap, va, m); 864 } 865 866 mtx_lock_spin(&tlbivax_mutex); 867 tlb_miss_lock(); 868 869 tlb0_flush_entry(va); 870 pte->flags = 0; 871 pte->rpn = 0; 872 873 tlb_miss_unlock(); 874 mtx_unlock_spin(&tlbivax_mutex); 875 876 pmap->pm_stats.resident_count--; 877 878 if (flags & PTBL_UNHOLD) { 879 //debugf("pte_remove: e (unhold)\n"); 880 return (ptbl_unhold(mmu, pmap, pdir_idx)); 881 } 882 883 //debugf("pte_remove: e\n"); 884 return (0); 885 } 886 887 /* 888 * Insert PTE for a given page and virtual address. 889 */ 890 static void 891 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 892 { 893 unsigned int pdir_idx = PDIR_IDX(va); 894 unsigned int ptbl_idx = PTBL_IDX(va); 895 pte_t *ptbl, *pte; 896 897 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 898 pmap == kernel_pmap, pmap, va); 899 900 /* Get the page table pointer. */ 901 ptbl = pmap->pm_pdir[pdir_idx]; 902 903 if (ptbl == NULL) { 904 /* Allocate page table pages. */ 905 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 906 } else { 907 /* 908 * Check if there is valid mapping for requested 909 * va, if there is, remove it. 910 */ 911 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 912 if (PTE_ISVALID(pte)) { 913 pte_remove(mmu, pmap, va, PTBL_HOLD); 914 } else { 915 /* 916 * pte is not used, increment hold count 917 * for ptbl pages. 918 */ 919 if (pmap != kernel_pmap) 920 ptbl_hold(mmu, pmap, pdir_idx); 921 } 922 } 923 924 /* 925 * Insert pv_entry into pv_list for mapped page if part of managed 926 * memory. 927 */ 928 if ((m->oflags & VPO_UNMANAGED) == 0) { 929 flags |= PTE_MANAGED; 930 931 /* Create and insert pv entry. */ 932 pv_insert(pmap, va, m); 933 } 934 935 pmap->pm_stats.resident_count++; 936 937 mtx_lock_spin(&tlbivax_mutex); 938 tlb_miss_lock(); 939 940 tlb0_flush_entry(va); 941 if (pmap->pm_pdir[pdir_idx] == NULL) { 942 /* 943 * If we just allocated a new page table, hook it in 944 * the pdir. 945 */ 946 pmap->pm_pdir[pdir_idx] = ptbl; 947 } 948 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 949 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 950 pte->flags |= (PTE_VALID | flags); 951 952 tlb_miss_unlock(); 953 mtx_unlock_spin(&tlbivax_mutex); 954 } 955 956 /* Return the pa for the given pmap/va. */ 957 static vm_paddr_t 958 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 959 { 960 vm_paddr_t pa = 0; 961 pte_t *pte; 962 963 pte = pte_find(mmu, pmap, va); 964 if ((pte != NULL) && PTE_ISVALID(pte)) 965 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 966 return (pa); 967 } 968 969 /* Get a pointer to a PTE in a page table. */ 970 static pte_t * 971 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 972 { 973 unsigned int pdir_idx = PDIR_IDX(va); 974 unsigned int ptbl_idx = PTBL_IDX(va); 975 976 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 977 978 if (pmap->pm_pdir[pdir_idx]) 979 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 980 981 return (NULL); 982 } 983 984 /**************************************************************************/ 985 /* PMAP related */ 986 /**************************************************************************/ 987 988 /* 989 * This is called during booke_init, before the system is really initialized. 990 */ 991 static void 992 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 993 { 994 vm_offset_t phys_kernelend; 995 struct mem_region *mp, *mp1; 996 int cnt, i, j; 997 u_int s, e, sz; 998 u_int phys_avail_count; 999 vm_size_t physsz, hwphyssz, kstack0_sz; 1000 vm_offset_t kernel_pdir, kstack0, va; 1001 vm_paddr_t kstack0_phys; 1002 void *dpcpu; 1003 pte_t *pte; 1004 1005 debugf("mmu_booke_bootstrap: entered\n"); 1006 1007 /* Initialize invalidation mutex */ 1008 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1009 1010 /* Read TLB0 size and associativity. */ 1011 tlb0_get_tlbconf(); 1012 1013 /* 1014 * Align kernel start and end address (kernel image). 1015 * Note that kernel end does not necessarily relate to kernsize. 1016 * kernsize is the size of the kernel that is actually mapped. 1017 * Also note that "start - 1" is deliberate. With SMP, the 1018 * entry point is exactly a page from the actual load address. 1019 * As such, trunc_page() has no effect and we're off by a page. 1020 * Since we always have the ELF header between the load address 1021 * and the entry point, we can safely subtract 1 to compensate. 1022 */ 1023 kernstart = trunc_page(start - 1); 1024 data_start = round_page(kernelend); 1025 data_end = data_start; 1026 1027 /* 1028 * Addresses of preloaded modules (like file systems) use 1029 * physical addresses. Make sure we relocate those into 1030 * virtual addresses. 1031 */ 1032 preload_addr_relocate = kernstart - kernload; 1033 1034 /* Allocate the dynamic per-cpu area. */ 1035 dpcpu = (void *)data_end; 1036 data_end += DPCPU_SIZE; 1037 1038 /* Allocate space for the message buffer. */ 1039 msgbufp = (struct msgbuf *)data_end; 1040 data_end += msgbufsize; 1041 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1042 data_end); 1043 1044 data_end = round_page(data_end); 1045 1046 /* Allocate space for ptbl_bufs. */ 1047 ptbl_bufs = (struct ptbl_buf *)data_end; 1048 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1049 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1050 data_end); 1051 1052 data_end = round_page(data_end); 1053 1054 /* Allocate PTE tables for kernel KVA. */ 1055 kernel_pdir = data_end; 1056 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1057 PDIR_SIZE - 1) / PDIR_SIZE; 1058 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1059 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1060 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1061 1062 debugf(" data_end: 0x%08x\n", data_end); 1063 if (data_end - kernstart > kernsize) { 1064 kernsize += tlb1_mapin_region(kernstart + kernsize, 1065 kernload + kernsize, (data_end - kernstart) - kernsize); 1066 } 1067 data_end = kernstart + kernsize; 1068 debugf(" updated data_end: 0x%08x\n", data_end); 1069 1070 /* 1071 * Clear the structures - note we can only do it safely after the 1072 * possible additional TLB1 translations are in place (above) so that 1073 * all range up to the currently calculated 'data_end' is covered. 1074 */ 1075 dpcpu_init(dpcpu, 0); 1076 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1077 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1078 1079 /*******************************************************/ 1080 /* Set the start and end of kva. */ 1081 /*******************************************************/ 1082 virtual_avail = round_page(data_end); 1083 virtual_end = VM_MAX_KERNEL_ADDRESS; 1084 1085 /* Allocate KVA space for page zero/copy operations. */ 1086 zero_page_va = virtual_avail; 1087 virtual_avail += PAGE_SIZE; 1088 zero_page_idle_va = virtual_avail; 1089 virtual_avail += PAGE_SIZE; 1090 copy_page_src_va = virtual_avail; 1091 virtual_avail += PAGE_SIZE; 1092 copy_page_dst_va = virtual_avail; 1093 virtual_avail += PAGE_SIZE; 1094 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1095 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1096 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1097 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1098 1099 /* Initialize page zero/copy mutexes. */ 1100 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1101 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1102 1103 /* Allocate KVA space for ptbl bufs. */ 1104 ptbl_buf_pool_vabase = virtual_avail; 1105 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1106 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1107 ptbl_buf_pool_vabase, virtual_avail); 1108 1109 /* Calculate corresponding physical addresses for the kernel region. */ 1110 phys_kernelend = kernload + kernsize; 1111 debugf("kernel image and allocated data:\n"); 1112 debugf(" kernload = 0x%08x\n", kernload); 1113 debugf(" kernstart = 0x%08x\n", kernstart); 1114 debugf(" kernsize = 0x%08x\n", kernsize); 1115 1116 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1117 panic("mmu_booke_bootstrap: phys_avail too small"); 1118 1119 /* 1120 * Remove kernel physical address range from avail regions list. Page 1121 * align all regions. Non-page aligned memory isn't very interesting 1122 * to us. Also, sort the entries for ascending addresses. 1123 */ 1124 1125 /* Retrieve phys/avail mem regions */ 1126 mem_regions(&physmem_regions, &physmem_regions_sz, 1127 &availmem_regions, &availmem_regions_sz); 1128 sz = 0; 1129 cnt = availmem_regions_sz; 1130 debugf("processing avail regions:\n"); 1131 for (mp = availmem_regions; mp->mr_size; mp++) { 1132 s = mp->mr_start; 1133 e = mp->mr_start + mp->mr_size; 1134 debugf(" %08x-%08x -> ", s, e); 1135 /* Check whether this region holds all of the kernel. */ 1136 if (s < kernload && e > phys_kernelend) { 1137 availmem_regions[cnt].mr_start = phys_kernelend; 1138 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1139 e = kernload; 1140 } 1141 /* Look whether this regions starts within the kernel. */ 1142 if (s >= kernload && s < phys_kernelend) { 1143 if (e <= phys_kernelend) 1144 goto empty; 1145 s = phys_kernelend; 1146 } 1147 /* Now look whether this region ends within the kernel. */ 1148 if (e > kernload && e <= phys_kernelend) { 1149 if (s >= kernload) 1150 goto empty; 1151 e = kernload; 1152 } 1153 /* Now page align the start and size of the region. */ 1154 s = round_page(s); 1155 e = trunc_page(e); 1156 if (e < s) 1157 e = s; 1158 sz = e - s; 1159 debugf("%08x-%08x = %x\n", s, e, sz); 1160 1161 /* Check whether some memory is left here. */ 1162 if (sz == 0) { 1163 empty: 1164 memmove(mp, mp + 1, 1165 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1166 cnt--; 1167 mp--; 1168 continue; 1169 } 1170 1171 /* Do an insertion sort. */ 1172 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1173 if (s < mp1->mr_start) 1174 break; 1175 if (mp1 < mp) { 1176 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1177 mp1->mr_start = s; 1178 mp1->mr_size = sz; 1179 } else { 1180 mp->mr_start = s; 1181 mp->mr_size = sz; 1182 } 1183 } 1184 availmem_regions_sz = cnt; 1185 1186 /*******************************************************/ 1187 /* Steal physical memory for kernel stack from the end */ 1188 /* of the first avail region */ 1189 /*******************************************************/ 1190 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1191 kstack0_phys = availmem_regions[0].mr_start + 1192 availmem_regions[0].mr_size; 1193 kstack0_phys -= kstack0_sz; 1194 availmem_regions[0].mr_size -= kstack0_sz; 1195 1196 /*******************************************************/ 1197 /* Fill in phys_avail table, based on availmem_regions */ 1198 /*******************************************************/ 1199 phys_avail_count = 0; 1200 physsz = 0; 1201 hwphyssz = 0; 1202 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1203 1204 debugf("fill in phys_avail:\n"); 1205 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1206 1207 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1208 availmem_regions[i].mr_start, 1209 availmem_regions[i].mr_start + 1210 availmem_regions[i].mr_size, 1211 availmem_regions[i].mr_size); 1212 1213 if (hwphyssz != 0 && 1214 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1215 debugf(" hw.physmem adjust\n"); 1216 if (physsz < hwphyssz) { 1217 phys_avail[j] = availmem_regions[i].mr_start; 1218 phys_avail[j + 1] = 1219 availmem_regions[i].mr_start + 1220 hwphyssz - physsz; 1221 physsz = hwphyssz; 1222 phys_avail_count++; 1223 } 1224 break; 1225 } 1226 1227 phys_avail[j] = availmem_regions[i].mr_start; 1228 phys_avail[j + 1] = availmem_regions[i].mr_start + 1229 availmem_regions[i].mr_size; 1230 phys_avail_count++; 1231 physsz += availmem_regions[i].mr_size; 1232 } 1233 physmem = btoc(physsz); 1234 1235 /* Calculate the last available physical address. */ 1236 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1237 ; 1238 Maxmem = powerpc_btop(phys_avail[i + 1]); 1239 1240 debugf("Maxmem = 0x%08lx\n", Maxmem); 1241 debugf("phys_avail_count = %d\n", phys_avail_count); 1242 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1243 physmem); 1244 1245 /*******************************************************/ 1246 /* Initialize (statically allocated) kernel pmap. */ 1247 /*******************************************************/ 1248 PMAP_LOCK_INIT(kernel_pmap); 1249 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1250 1251 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1252 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1253 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1254 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1255 1256 /* Initialize kernel pdir */ 1257 for (i = 0; i < kernel_ptbls; i++) 1258 kernel_pmap->pm_pdir[kptbl_min + i] = 1259 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1260 1261 for (i = 0; i < MAXCPU; i++) { 1262 kernel_pmap->pm_tid[i] = TID_KERNEL; 1263 1264 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1265 tidbusy[i][0] = kernel_pmap; 1266 } 1267 1268 /* 1269 * Fill in PTEs covering kernel code and data. They are not required 1270 * for address translation, as this area is covered by static TLB1 1271 * entries, but for pte_vatopa() to work correctly with kernel area 1272 * addresses. 1273 */ 1274 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1275 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1276 pte->rpn = kernload + (va - kernstart); 1277 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1278 PTE_VALID; 1279 } 1280 /* Mark kernel_pmap active on all CPUs */ 1281 CPU_FILL(&kernel_pmap->pm_active); 1282 1283 /* 1284 * Initialize the global pv list lock. 1285 */ 1286 rw_init(&pvh_global_lock, "pmap pv global"); 1287 1288 /*******************************************************/ 1289 /* Final setup */ 1290 /*******************************************************/ 1291 1292 /* Enter kstack0 into kernel map, provide guard page */ 1293 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1294 thread0.td_kstack = kstack0; 1295 thread0.td_kstack_pages = KSTACK_PAGES; 1296 1297 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1298 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1299 kstack0_phys, kstack0_phys + kstack0_sz); 1300 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1301 1302 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1303 for (i = 0; i < KSTACK_PAGES; i++) { 1304 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1305 kstack0 += PAGE_SIZE; 1306 kstack0_phys += PAGE_SIZE; 1307 } 1308 1309 debugf("virtual_avail = %08x\n", virtual_avail); 1310 debugf("virtual_end = %08x\n", virtual_end); 1311 1312 debugf("mmu_booke_bootstrap: exit\n"); 1313 } 1314 1315 void 1316 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1317 { 1318 int i; 1319 1320 /* 1321 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1322 * have the snapshot of its contents in the s/w tlb1[] table, so use 1323 * these values directly to (re)program AP's TLB1 hardware. 1324 */ 1325 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1326 /* Skip invalid entries */ 1327 if (!(tlb1[i].mas1 & MAS1_VALID)) 1328 continue; 1329 1330 tlb1_write_entry(i); 1331 } 1332 1333 set_mas4_defaults(); 1334 } 1335 1336 /* 1337 * Get the physical page address for the given pmap/virtual address. 1338 */ 1339 static vm_paddr_t 1340 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1341 { 1342 vm_paddr_t pa; 1343 1344 PMAP_LOCK(pmap); 1345 pa = pte_vatopa(mmu, pmap, va); 1346 PMAP_UNLOCK(pmap); 1347 1348 return (pa); 1349 } 1350 1351 /* 1352 * Extract the physical page address associated with the given 1353 * kernel virtual address. 1354 */ 1355 static vm_paddr_t 1356 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1357 { 1358 int i; 1359 1360 /* Check TLB1 mappings */ 1361 for (i = 0; i < tlb1_idx; i++) { 1362 if (!(tlb1[i].mas1 & MAS1_VALID)) 1363 continue; 1364 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1365 return (tlb1[i].phys + (va - tlb1[i].virt)); 1366 } 1367 1368 return (pte_vatopa(mmu, kernel_pmap, va)); 1369 } 1370 1371 /* 1372 * Initialize the pmap module. 1373 * Called by vm_init, to initialize any structures that the pmap 1374 * system needs to map virtual memory. 1375 */ 1376 static void 1377 mmu_booke_init(mmu_t mmu) 1378 { 1379 int shpgperproc = PMAP_SHPGPERPROC; 1380 1381 /* 1382 * Initialize the address space (zone) for the pv entries. Set a 1383 * high water mark so that the system can recover from excessive 1384 * numbers of pv entries. 1385 */ 1386 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1387 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1388 1389 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1390 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1391 1392 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1393 pv_entry_high_water = 9 * (pv_entry_max / 10); 1394 1395 uma_zone_reserve_kva(pvzone, pv_entry_max); 1396 1397 /* Pre-fill pvzone with initial number of pv entries. */ 1398 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1399 1400 /* Initialize ptbl allocation. */ 1401 ptbl_init(); 1402 } 1403 1404 /* 1405 * Map a list of wired pages into kernel virtual address space. This is 1406 * intended for temporary mappings which do not need page modification or 1407 * references recorded. Existing mappings in the region are overwritten. 1408 */ 1409 static void 1410 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1411 { 1412 vm_offset_t va; 1413 1414 va = sva; 1415 while (count-- > 0) { 1416 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1417 va += PAGE_SIZE; 1418 m++; 1419 } 1420 } 1421 1422 /* 1423 * Remove page mappings from kernel virtual address space. Intended for 1424 * temporary mappings entered by mmu_booke_qenter. 1425 */ 1426 static void 1427 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1428 { 1429 vm_offset_t va; 1430 1431 va = sva; 1432 while (count-- > 0) { 1433 mmu_booke_kremove(mmu, va); 1434 va += PAGE_SIZE; 1435 } 1436 } 1437 1438 /* 1439 * Map a wired page into kernel virtual address space. 1440 */ 1441 static void 1442 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1443 { 1444 1445 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1446 } 1447 1448 static void 1449 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1450 { 1451 unsigned int pdir_idx = PDIR_IDX(va); 1452 unsigned int ptbl_idx = PTBL_IDX(va); 1453 uint32_t flags; 1454 pte_t *pte; 1455 1456 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1457 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1458 1459 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1460 flags |= tlb_calc_wimg(pa, ma); 1461 1462 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1463 1464 mtx_lock_spin(&tlbivax_mutex); 1465 tlb_miss_lock(); 1466 1467 if (PTE_ISVALID(pte)) { 1468 1469 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1470 1471 /* Flush entry from TLB0 */ 1472 tlb0_flush_entry(va); 1473 } 1474 1475 pte->rpn = pa & ~PTE_PA_MASK; 1476 pte->flags = flags; 1477 1478 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1479 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1480 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1481 1482 /* Flush the real memory from the instruction cache. */ 1483 if ((flags & (PTE_I | PTE_G)) == 0) { 1484 __syncicache((void *)va, PAGE_SIZE); 1485 } 1486 1487 tlb_miss_unlock(); 1488 mtx_unlock_spin(&tlbivax_mutex); 1489 } 1490 1491 /* 1492 * Remove a page from kernel page table. 1493 */ 1494 static void 1495 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1496 { 1497 unsigned int pdir_idx = PDIR_IDX(va); 1498 unsigned int ptbl_idx = PTBL_IDX(va); 1499 pte_t *pte; 1500 1501 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1502 1503 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1504 (va <= VM_MAX_KERNEL_ADDRESS)), 1505 ("mmu_booke_kremove: invalid va")); 1506 1507 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1508 1509 if (!PTE_ISVALID(pte)) { 1510 1511 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1512 1513 return; 1514 } 1515 1516 mtx_lock_spin(&tlbivax_mutex); 1517 tlb_miss_lock(); 1518 1519 /* Invalidate entry in TLB0, update PTE. */ 1520 tlb0_flush_entry(va); 1521 pte->flags = 0; 1522 pte->rpn = 0; 1523 1524 tlb_miss_unlock(); 1525 mtx_unlock_spin(&tlbivax_mutex); 1526 } 1527 1528 /* 1529 * Initialize pmap associated with process 0. 1530 */ 1531 static void 1532 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1533 { 1534 1535 PMAP_LOCK_INIT(pmap); 1536 mmu_booke_pinit(mmu, pmap); 1537 PCPU_SET(curpmap, pmap); 1538 } 1539 1540 /* 1541 * Initialize a preallocated and zeroed pmap structure, 1542 * such as one in a vmspace structure. 1543 */ 1544 static void 1545 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1546 { 1547 int i; 1548 1549 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1550 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1551 1552 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1553 1554 for (i = 0; i < MAXCPU; i++) 1555 pmap->pm_tid[i] = TID_NONE; 1556 CPU_ZERO(&kernel_pmap->pm_active); 1557 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1558 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1559 TAILQ_INIT(&pmap->pm_ptbl_list); 1560 } 1561 1562 /* 1563 * Release any resources held by the given physical map. 1564 * Called when a pmap initialized by mmu_booke_pinit is being released. 1565 * Should only be called if the map contains no valid mappings. 1566 */ 1567 static void 1568 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1569 { 1570 1571 KASSERT(pmap->pm_stats.resident_count == 0, 1572 ("pmap_release: pmap resident count %ld != 0", 1573 pmap->pm_stats.resident_count)); 1574 } 1575 1576 /* 1577 * Insert the given physical page at the specified virtual address in the 1578 * target physical map with the protection requested. If specified the page 1579 * will be wired down. 1580 */ 1581 static void 1582 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1583 vm_prot_t prot, boolean_t wired) 1584 { 1585 1586 rw_wlock(&pvh_global_lock); 1587 PMAP_LOCK(pmap); 1588 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1589 rw_wunlock(&pvh_global_lock); 1590 PMAP_UNLOCK(pmap); 1591 } 1592 1593 static void 1594 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1595 vm_prot_t prot, boolean_t wired) 1596 { 1597 pte_t *pte; 1598 vm_paddr_t pa; 1599 uint32_t flags; 1600 int su, sync; 1601 1602 pa = VM_PAGE_TO_PHYS(m); 1603 su = (pmap == kernel_pmap); 1604 sync = 0; 1605 1606 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1607 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1608 // (u_int32_t)pmap, su, pmap->pm_tid, 1609 // (u_int32_t)m, va, pa, prot, wired); 1610 1611 if (su) { 1612 KASSERT(((va >= virtual_avail) && 1613 (va <= VM_MAX_KERNEL_ADDRESS)), 1614 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1615 } else { 1616 KASSERT((va <= VM_MAXUSER_ADDRESS), 1617 ("mmu_booke_enter_locked: user pmap, non user va")); 1618 } 1619 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1620 VM_OBJECT_ASSERT_LOCKED(m->object); 1621 1622 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1623 1624 /* 1625 * If there is an existing mapping, and the physical address has not 1626 * changed, must be protection or wiring change. 1627 */ 1628 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1629 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1630 1631 /* 1632 * Before actually updating pte->flags we calculate and 1633 * prepare its new value in a helper var. 1634 */ 1635 flags = pte->flags; 1636 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1637 1638 /* Wiring change, just update stats. */ 1639 if (wired) { 1640 if (!PTE_ISWIRED(pte)) { 1641 flags |= PTE_WIRED; 1642 pmap->pm_stats.wired_count++; 1643 } 1644 } else { 1645 if (PTE_ISWIRED(pte)) { 1646 flags &= ~PTE_WIRED; 1647 pmap->pm_stats.wired_count--; 1648 } 1649 } 1650 1651 if (prot & VM_PROT_WRITE) { 1652 /* Add write permissions. */ 1653 flags |= PTE_SW; 1654 if (!su) 1655 flags |= PTE_UW; 1656 1657 if ((flags & PTE_MANAGED) != 0) 1658 vm_page_aflag_set(m, PGA_WRITEABLE); 1659 } else { 1660 /* Handle modified pages, sense modify status. */ 1661 1662 /* 1663 * The PTE_MODIFIED flag could be set by underlying 1664 * TLB misses since we last read it (above), possibly 1665 * other CPUs could update it so we check in the PTE 1666 * directly rather than rely on that saved local flags 1667 * copy. 1668 */ 1669 if (PTE_ISMODIFIED(pte)) 1670 vm_page_dirty(m); 1671 } 1672 1673 if (prot & VM_PROT_EXECUTE) { 1674 flags |= PTE_SX; 1675 if (!su) 1676 flags |= PTE_UX; 1677 1678 /* 1679 * Check existing flags for execute permissions: if we 1680 * are turning execute permissions on, icache should 1681 * be flushed. 1682 */ 1683 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1684 sync++; 1685 } 1686 1687 flags &= ~PTE_REFERENCED; 1688 1689 /* 1690 * The new flags value is all calculated -- only now actually 1691 * update the PTE. 1692 */ 1693 mtx_lock_spin(&tlbivax_mutex); 1694 tlb_miss_lock(); 1695 1696 tlb0_flush_entry(va); 1697 pte->flags = flags; 1698 1699 tlb_miss_unlock(); 1700 mtx_unlock_spin(&tlbivax_mutex); 1701 1702 } else { 1703 /* 1704 * If there is an existing mapping, but it's for a different 1705 * physical address, pte_enter() will delete the old mapping. 1706 */ 1707 //if ((pte != NULL) && PTE_ISVALID(pte)) 1708 // debugf("mmu_booke_enter_locked: replace\n"); 1709 //else 1710 // debugf("mmu_booke_enter_locked: new\n"); 1711 1712 /* Now set up the flags and install the new mapping. */ 1713 flags = (PTE_SR | PTE_VALID); 1714 flags |= PTE_M; 1715 1716 if (!su) 1717 flags |= PTE_UR; 1718 1719 if (prot & VM_PROT_WRITE) { 1720 flags |= PTE_SW; 1721 if (!su) 1722 flags |= PTE_UW; 1723 1724 if ((m->oflags & VPO_UNMANAGED) == 0) 1725 vm_page_aflag_set(m, PGA_WRITEABLE); 1726 } 1727 1728 if (prot & VM_PROT_EXECUTE) { 1729 flags |= PTE_SX; 1730 if (!su) 1731 flags |= PTE_UX; 1732 } 1733 1734 /* If its wired update stats. */ 1735 if (wired) { 1736 pmap->pm_stats.wired_count++; 1737 flags |= PTE_WIRED; 1738 } 1739 1740 pte_enter(mmu, pmap, m, va, flags); 1741 1742 /* Flush the real memory from the instruction cache. */ 1743 if (prot & VM_PROT_EXECUTE) 1744 sync++; 1745 } 1746 1747 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1748 __syncicache((void *)va, PAGE_SIZE); 1749 sync = 0; 1750 } 1751 } 1752 1753 /* 1754 * Maps a sequence of resident pages belonging to the same object. 1755 * The sequence begins with the given page m_start. This page is 1756 * mapped at the given virtual address start. Each subsequent page is 1757 * mapped at a virtual address that is offset from start by the same 1758 * amount as the page is offset from m_start within the object. The 1759 * last page in the sequence is the page with the largest offset from 1760 * m_start that can be mapped at a virtual address less than the given 1761 * virtual address end. Not every virtual page between start and end 1762 * is mapped; only those for which a resident page exists with the 1763 * corresponding offset from m_start are mapped. 1764 */ 1765 static void 1766 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1767 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1768 { 1769 vm_page_t m; 1770 vm_pindex_t diff, psize; 1771 1772 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1773 1774 psize = atop(end - start); 1775 m = m_start; 1776 rw_wlock(&pvh_global_lock); 1777 PMAP_LOCK(pmap); 1778 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1779 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1780 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1781 m = TAILQ_NEXT(m, listq); 1782 } 1783 rw_wunlock(&pvh_global_lock); 1784 PMAP_UNLOCK(pmap); 1785 } 1786 1787 static void 1788 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1789 vm_prot_t prot) 1790 { 1791 1792 rw_wlock(&pvh_global_lock); 1793 PMAP_LOCK(pmap); 1794 mmu_booke_enter_locked(mmu, pmap, va, m, 1795 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1796 rw_wunlock(&pvh_global_lock); 1797 PMAP_UNLOCK(pmap); 1798 } 1799 1800 /* 1801 * Remove the given range of addresses from the specified map. 1802 * 1803 * It is assumed that the start and end are properly rounded to the page size. 1804 */ 1805 static void 1806 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1807 { 1808 pte_t *pte; 1809 uint8_t hold_flag; 1810 1811 int su = (pmap == kernel_pmap); 1812 1813 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1814 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1815 1816 if (su) { 1817 KASSERT(((va >= virtual_avail) && 1818 (va <= VM_MAX_KERNEL_ADDRESS)), 1819 ("mmu_booke_remove: kernel pmap, non kernel va")); 1820 } else { 1821 KASSERT((va <= VM_MAXUSER_ADDRESS), 1822 ("mmu_booke_remove: user pmap, non user va")); 1823 } 1824 1825 if (PMAP_REMOVE_DONE(pmap)) { 1826 //debugf("mmu_booke_remove: e (empty)\n"); 1827 return; 1828 } 1829 1830 hold_flag = PTBL_HOLD_FLAG(pmap); 1831 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1832 1833 rw_wlock(&pvh_global_lock); 1834 PMAP_LOCK(pmap); 1835 for (; va < endva; va += PAGE_SIZE) { 1836 pte = pte_find(mmu, pmap, va); 1837 if ((pte != NULL) && PTE_ISVALID(pte)) 1838 pte_remove(mmu, pmap, va, hold_flag); 1839 } 1840 PMAP_UNLOCK(pmap); 1841 rw_wunlock(&pvh_global_lock); 1842 1843 //debugf("mmu_booke_remove: e\n"); 1844 } 1845 1846 /* 1847 * Remove physical page from all pmaps in which it resides. 1848 */ 1849 static void 1850 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1851 { 1852 pv_entry_t pv, pvn; 1853 uint8_t hold_flag; 1854 1855 rw_wlock(&pvh_global_lock); 1856 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1857 pvn = TAILQ_NEXT(pv, pv_link); 1858 1859 PMAP_LOCK(pv->pv_pmap); 1860 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1861 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1862 PMAP_UNLOCK(pv->pv_pmap); 1863 } 1864 vm_page_aflag_clear(m, PGA_WRITEABLE); 1865 rw_wunlock(&pvh_global_lock); 1866 } 1867 1868 /* 1869 * Map a range of physical addresses into kernel virtual address space. 1870 */ 1871 static vm_offset_t 1872 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1873 vm_paddr_t pa_end, int prot) 1874 { 1875 vm_offset_t sva = *virt; 1876 vm_offset_t va = sva; 1877 1878 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1879 // sva, pa_start, pa_end); 1880 1881 while (pa_start < pa_end) { 1882 mmu_booke_kenter(mmu, va, pa_start); 1883 va += PAGE_SIZE; 1884 pa_start += PAGE_SIZE; 1885 } 1886 *virt = va; 1887 1888 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1889 return (sva); 1890 } 1891 1892 /* 1893 * The pmap must be activated before it's address space can be accessed in any 1894 * way. 1895 */ 1896 static void 1897 mmu_booke_activate(mmu_t mmu, struct thread *td) 1898 { 1899 pmap_t pmap; 1900 u_int cpuid; 1901 1902 pmap = &td->td_proc->p_vmspace->vm_pmap; 1903 1904 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1905 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1906 1907 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1908 1909 sched_pin(); 1910 1911 cpuid = PCPU_GET(cpuid); 1912 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1913 PCPU_SET(curpmap, pmap); 1914 1915 if (pmap->pm_tid[cpuid] == TID_NONE) 1916 tid_alloc(pmap); 1917 1918 /* Load PID0 register with pmap tid value. */ 1919 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1920 __asm __volatile("isync"); 1921 1922 sched_unpin(); 1923 1924 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1925 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1926 } 1927 1928 /* 1929 * Deactivate the specified process's address space. 1930 */ 1931 static void 1932 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1933 { 1934 pmap_t pmap; 1935 1936 pmap = &td->td_proc->p_vmspace->vm_pmap; 1937 1938 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1939 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1940 1941 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1942 PCPU_SET(curpmap, NULL); 1943 } 1944 1945 /* 1946 * Copy the range specified by src_addr/len 1947 * from the source map to the range dst_addr/len 1948 * in the destination map. 1949 * 1950 * This routine is only advisory and need not do anything. 1951 */ 1952 static void 1953 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1954 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1955 { 1956 1957 } 1958 1959 /* 1960 * Set the physical protection on the specified range of this map as requested. 1961 */ 1962 static void 1963 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1964 vm_prot_t prot) 1965 { 1966 vm_offset_t va; 1967 vm_page_t m; 1968 pte_t *pte; 1969 1970 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1971 mmu_booke_remove(mmu, pmap, sva, eva); 1972 return; 1973 } 1974 1975 if (prot & VM_PROT_WRITE) 1976 return; 1977 1978 PMAP_LOCK(pmap); 1979 for (va = sva; va < eva; va += PAGE_SIZE) { 1980 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1981 if (PTE_ISVALID(pte)) { 1982 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1983 1984 mtx_lock_spin(&tlbivax_mutex); 1985 tlb_miss_lock(); 1986 1987 /* Handle modified pages. */ 1988 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1989 vm_page_dirty(m); 1990 1991 tlb0_flush_entry(va); 1992 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1993 1994 tlb_miss_unlock(); 1995 mtx_unlock_spin(&tlbivax_mutex); 1996 } 1997 } 1998 } 1999 PMAP_UNLOCK(pmap); 2000 } 2001 2002 /* 2003 * Clear the write and modified bits in each of the given page's mappings. 2004 */ 2005 static void 2006 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2007 { 2008 pv_entry_t pv; 2009 pte_t *pte; 2010 2011 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2012 ("mmu_booke_remove_write: page %p is not managed", m)); 2013 2014 /* 2015 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2016 * set by another thread while the object is locked. Thus, 2017 * if PGA_WRITEABLE is clear, no page table entries need updating. 2018 */ 2019 VM_OBJECT_ASSERT_WLOCKED(m->object); 2020 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2021 return; 2022 rw_wlock(&pvh_global_lock); 2023 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2024 PMAP_LOCK(pv->pv_pmap); 2025 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2026 if (PTE_ISVALID(pte)) { 2027 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2028 2029 mtx_lock_spin(&tlbivax_mutex); 2030 tlb_miss_lock(); 2031 2032 /* Handle modified pages. */ 2033 if (PTE_ISMODIFIED(pte)) 2034 vm_page_dirty(m); 2035 2036 /* Flush mapping from TLB0. */ 2037 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2038 2039 tlb_miss_unlock(); 2040 mtx_unlock_spin(&tlbivax_mutex); 2041 } 2042 } 2043 PMAP_UNLOCK(pv->pv_pmap); 2044 } 2045 vm_page_aflag_clear(m, PGA_WRITEABLE); 2046 rw_wunlock(&pvh_global_lock); 2047 } 2048 2049 static void 2050 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2051 { 2052 pte_t *pte; 2053 pmap_t pmap; 2054 vm_page_t m; 2055 vm_offset_t addr; 2056 vm_paddr_t pa = 0; 2057 int active, valid; 2058 2059 va = trunc_page(va); 2060 sz = round_page(sz); 2061 2062 rw_wlock(&pvh_global_lock); 2063 pmap = PCPU_GET(curpmap); 2064 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2065 while (sz > 0) { 2066 PMAP_LOCK(pm); 2067 pte = pte_find(mmu, pm, va); 2068 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2069 if (valid) 2070 pa = PTE_PA(pte); 2071 PMAP_UNLOCK(pm); 2072 if (valid) { 2073 if (!active) { 2074 /* Create a mapping in the active pmap. */ 2075 addr = 0; 2076 m = PHYS_TO_VM_PAGE(pa); 2077 PMAP_LOCK(pmap); 2078 pte_enter(mmu, pmap, m, addr, 2079 PTE_SR | PTE_VALID | PTE_UR); 2080 __syncicache((void *)addr, PAGE_SIZE); 2081 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2082 PMAP_UNLOCK(pmap); 2083 } else 2084 __syncicache((void *)va, PAGE_SIZE); 2085 } 2086 va += PAGE_SIZE; 2087 sz -= PAGE_SIZE; 2088 } 2089 rw_wunlock(&pvh_global_lock); 2090 } 2091 2092 /* 2093 * Atomically extract and hold the physical page with the given 2094 * pmap and virtual address pair if that mapping permits the given 2095 * protection. 2096 */ 2097 static vm_page_t 2098 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2099 vm_prot_t prot) 2100 { 2101 pte_t *pte; 2102 vm_page_t m; 2103 uint32_t pte_wbit; 2104 vm_paddr_t pa; 2105 2106 m = NULL; 2107 pa = 0; 2108 PMAP_LOCK(pmap); 2109 retry: 2110 pte = pte_find(mmu, pmap, va); 2111 if ((pte != NULL) && PTE_ISVALID(pte)) { 2112 if (pmap == kernel_pmap) 2113 pte_wbit = PTE_SW; 2114 else 2115 pte_wbit = PTE_UW; 2116 2117 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2118 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2119 goto retry; 2120 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2121 vm_page_hold(m); 2122 } 2123 } 2124 2125 PA_UNLOCK_COND(pa); 2126 PMAP_UNLOCK(pmap); 2127 return (m); 2128 } 2129 2130 /* 2131 * Initialize a vm_page's machine-dependent fields. 2132 */ 2133 static void 2134 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2135 { 2136 2137 TAILQ_INIT(&m->md.pv_list); 2138 } 2139 2140 /* 2141 * mmu_booke_zero_page_area zeros the specified hardware page by 2142 * mapping it into virtual memory and using bzero to clear 2143 * its contents. 2144 * 2145 * off and size must reside within a single page. 2146 */ 2147 static void 2148 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2149 { 2150 vm_offset_t va; 2151 2152 /* XXX KASSERT off and size are within a single page? */ 2153 2154 mtx_lock(&zero_page_mutex); 2155 va = zero_page_va; 2156 2157 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2158 bzero((caddr_t)va + off, size); 2159 mmu_booke_kremove(mmu, va); 2160 2161 mtx_unlock(&zero_page_mutex); 2162 } 2163 2164 /* 2165 * mmu_booke_zero_page zeros the specified hardware page. 2166 */ 2167 static void 2168 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2169 { 2170 2171 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2172 } 2173 2174 /* 2175 * mmu_booke_copy_page copies the specified (machine independent) page by 2176 * mapping the page into virtual memory and using memcopy to copy the page, 2177 * one machine dependent page at a time. 2178 */ 2179 static void 2180 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2181 { 2182 vm_offset_t sva, dva; 2183 2184 sva = copy_page_src_va; 2185 dva = copy_page_dst_va; 2186 2187 mtx_lock(©_page_mutex); 2188 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2189 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2190 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2191 mmu_booke_kremove(mmu, dva); 2192 mmu_booke_kremove(mmu, sva); 2193 mtx_unlock(©_page_mutex); 2194 } 2195 2196 static inline void 2197 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2198 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2199 { 2200 void *a_cp, *b_cp; 2201 vm_offset_t a_pg_offset, b_pg_offset; 2202 int cnt; 2203 2204 mtx_lock(©_page_mutex); 2205 while (xfersize > 0) { 2206 a_pg_offset = a_offset & PAGE_MASK; 2207 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2208 mmu_booke_kenter(mmu, copy_page_src_va, 2209 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2210 a_cp = (char *)copy_page_src_va + a_pg_offset; 2211 b_pg_offset = b_offset & PAGE_MASK; 2212 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2213 mmu_booke_kenter(mmu, copy_page_dst_va, 2214 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2215 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2216 bcopy(a_cp, b_cp, cnt); 2217 mmu_booke_kremove(mmu, copy_page_dst_va); 2218 mmu_booke_kremove(mmu, copy_page_src_va); 2219 a_offset += cnt; 2220 b_offset += cnt; 2221 xfersize -= cnt; 2222 } 2223 mtx_unlock(©_page_mutex); 2224 } 2225 2226 /* 2227 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2228 * into virtual memory and using bzero to clear its contents. This is intended 2229 * to be called from the vm_pagezero process only and outside of Giant. No 2230 * lock is required. 2231 */ 2232 static void 2233 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2234 { 2235 vm_offset_t va; 2236 2237 va = zero_page_idle_va; 2238 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2239 bzero((caddr_t)va, PAGE_SIZE); 2240 mmu_booke_kremove(mmu, va); 2241 } 2242 2243 /* 2244 * Return whether or not the specified physical page was modified 2245 * in any of physical maps. 2246 */ 2247 static boolean_t 2248 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2249 { 2250 pte_t *pte; 2251 pv_entry_t pv; 2252 boolean_t rv; 2253 2254 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2255 ("mmu_booke_is_modified: page %p is not managed", m)); 2256 rv = FALSE; 2257 2258 /* 2259 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2260 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2261 * is clear, no PTEs can be modified. 2262 */ 2263 VM_OBJECT_ASSERT_WLOCKED(m->object); 2264 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2265 return (rv); 2266 rw_wlock(&pvh_global_lock); 2267 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2268 PMAP_LOCK(pv->pv_pmap); 2269 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2270 PTE_ISVALID(pte)) { 2271 if (PTE_ISMODIFIED(pte)) 2272 rv = TRUE; 2273 } 2274 PMAP_UNLOCK(pv->pv_pmap); 2275 if (rv) 2276 break; 2277 } 2278 rw_wunlock(&pvh_global_lock); 2279 return (rv); 2280 } 2281 2282 /* 2283 * Return whether or not the specified virtual address is eligible 2284 * for prefault. 2285 */ 2286 static boolean_t 2287 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2288 { 2289 2290 return (FALSE); 2291 } 2292 2293 /* 2294 * Return whether or not the specified physical page was referenced 2295 * in any physical maps. 2296 */ 2297 static boolean_t 2298 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2299 { 2300 pte_t *pte; 2301 pv_entry_t pv; 2302 boolean_t rv; 2303 2304 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2305 ("mmu_booke_is_referenced: page %p is not managed", m)); 2306 rv = FALSE; 2307 rw_wlock(&pvh_global_lock); 2308 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2309 PMAP_LOCK(pv->pv_pmap); 2310 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2311 PTE_ISVALID(pte)) { 2312 if (PTE_ISREFERENCED(pte)) 2313 rv = TRUE; 2314 } 2315 PMAP_UNLOCK(pv->pv_pmap); 2316 if (rv) 2317 break; 2318 } 2319 rw_wunlock(&pvh_global_lock); 2320 return (rv); 2321 } 2322 2323 /* 2324 * Clear the modify bits on the specified physical page. 2325 */ 2326 static void 2327 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2328 { 2329 pte_t *pte; 2330 pv_entry_t pv; 2331 2332 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2333 ("mmu_booke_clear_modify: page %p is not managed", m)); 2334 VM_OBJECT_ASSERT_WLOCKED(m->object); 2335 KASSERT(!vm_page_xbusied(m), 2336 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2337 2338 /* 2339 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2340 * If the object containing the page is locked and the page is not 2341 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2342 */ 2343 if ((m->aflags & PGA_WRITEABLE) == 0) 2344 return; 2345 rw_wlock(&pvh_global_lock); 2346 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2347 PMAP_LOCK(pv->pv_pmap); 2348 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2349 PTE_ISVALID(pte)) { 2350 mtx_lock_spin(&tlbivax_mutex); 2351 tlb_miss_lock(); 2352 2353 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2354 tlb0_flush_entry(pv->pv_va); 2355 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2356 PTE_REFERENCED); 2357 } 2358 2359 tlb_miss_unlock(); 2360 mtx_unlock_spin(&tlbivax_mutex); 2361 } 2362 PMAP_UNLOCK(pv->pv_pmap); 2363 } 2364 rw_wunlock(&pvh_global_lock); 2365 } 2366 2367 /* 2368 * Return a count of reference bits for a page, clearing those bits. 2369 * It is not necessary for every reference bit to be cleared, but it 2370 * is necessary that 0 only be returned when there are truly no 2371 * reference bits set. 2372 * 2373 * XXX: The exact number of bits to check and clear is a matter that 2374 * should be tested and standardized at some point in the future for 2375 * optimal aging of shared pages. 2376 */ 2377 static int 2378 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2379 { 2380 pte_t *pte; 2381 pv_entry_t pv; 2382 int count; 2383 2384 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2385 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2386 count = 0; 2387 rw_wlock(&pvh_global_lock); 2388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2389 PMAP_LOCK(pv->pv_pmap); 2390 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2391 PTE_ISVALID(pte)) { 2392 if (PTE_ISREFERENCED(pte)) { 2393 mtx_lock_spin(&tlbivax_mutex); 2394 tlb_miss_lock(); 2395 2396 tlb0_flush_entry(pv->pv_va); 2397 pte->flags &= ~PTE_REFERENCED; 2398 2399 tlb_miss_unlock(); 2400 mtx_unlock_spin(&tlbivax_mutex); 2401 2402 if (++count > 4) { 2403 PMAP_UNLOCK(pv->pv_pmap); 2404 break; 2405 } 2406 } 2407 } 2408 PMAP_UNLOCK(pv->pv_pmap); 2409 } 2410 rw_wunlock(&pvh_global_lock); 2411 return (count); 2412 } 2413 2414 /* 2415 * Change wiring attribute for a map/virtual-address pair. 2416 */ 2417 static void 2418 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2419 { 2420 pte_t *pte; 2421 2422 PMAP_LOCK(pmap); 2423 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2424 if (wired) { 2425 if (!PTE_ISWIRED(pte)) { 2426 pte->flags |= PTE_WIRED; 2427 pmap->pm_stats.wired_count++; 2428 } 2429 } else { 2430 if (PTE_ISWIRED(pte)) { 2431 pte->flags &= ~PTE_WIRED; 2432 pmap->pm_stats.wired_count--; 2433 } 2434 } 2435 } 2436 PMAP_UNLOCK(pmap); 2437 } 2438 2439 /* 2440 * Clear the wired attribute from the mappings for the specified range of 2441 * addresses in the given pmap. Every valid mapping within that range must 2442 * have the wired attribute set. In contrast, invalid mappings cannot have 2443 * the wired attribute set, so they are ignored. 2444 * 2445 * The wired attribute of the page table entry is not a hardware feature, so 2446 * there is no need to invalidate any TLB entries. 2447 */ 2448 static void 2449 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2450 { 2451 vm_offset_t va; 2452 pte_t *pte; 2453 2454 PMAP_LOCK(pmap); 2455 for (va = sva; va < eva; va += PAGE_SIZE) { 2456 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2457 PTE_ISVALID(pte)) { 2458 if (!PTE_ISWIRED(pte)) 2459 panic("mmu_booke_unwire: pte %p isn't wired", 2460 pte); 2461 pte->flags &= ~PTE_WIRED; 2462 pmap->pm_stats.wired_count--; 2463 } 2464 } 2465 PMAP_UNLOCK(pmap); 2466 2467 } 2468 2469 /* 2470 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2471 * page. This count may be changed upwards or downwards in the future; it is 2472 * only necessary that true be returned for a small subset of pmaps for proper 2473 * page aging. 2474 */ 2475 static boolean_t 2476 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2477 { 2478 pv_entry_t pv; 2479 int loops; 2480 boolean_t rv; 2481 2482 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2483 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2484 loops = 0; 2485 rv = FALSE; 2486 rw_wlock(&pvh_global_lock); 2487 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2488 if (pv->pv_pmap == pmap) { 2489 rv = TRUE; 2490 break; 2491 } 2492 if (++loops >= 16) 2493 break; 2494 } 2495 rw_wunlock(&pvh_global_lock); 2496 return (rv); 2497 } 2498 2499 /* 2500 * Return the number of managed mappings to the given physical page that are 2501 * wired. 2502 */ 2503 static int 2504 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2505 { 2506 pv_entry_t pv; 2507 pte_t *pte; 2508 int count = 0; 2509 2510 if ((m->oflags & VPO_UNMANAGED) != 0) 2511 return (count); 2512 rw_wlock(&pvh_global_lock); 2513 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2514 PMAP_LOCK(pv->pv_pmap); 2515 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2516 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2517 count++; 2518 PMAP_UNLOCK(pv->pv_pmap); 2519 } 2520 rw_wunlock(&pvh_global_lock); 2521 return (count); 2522 } 2523 2524 static int 2525 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2526 { 2527 int i; 2528 vm_offset_t va; 2529 2530 /* 2531 * This currently does not work for entries that 2532 * overlap TLB1 entries. 2533 */ 2534 for (i = 0; i < tlb1_idx; i ++) { 2535 if (tlb1_iomapped(i, pa, size, &va) == 0) 2536 return (0); 2537 } 2538 2539 return (EFAULT); 2540 } 2541 2542 vm_offset_t 2543 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2544 vm_size_t *sz) 2545 { 2546 vm_paddr_t pa, ppa; 2547 vm_offset_t va; 2548 vm_size_t gran; 2549 2550 /* Raw physical memory dumps don't have a virtual address. */ 2551 if (md->md_vaddr == ~0UL) { 2552 /* We always map a 256MB page at 256M. */ 2553 gran = 256 * 1024 * 1024; 2554 pa = md->md_paddr + ofs; 2555 ppa = pa & ~(gran - 1); 2556 ofs = pa - ppa; 2557 va = gran; 2558 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2559 if (*sz > (gran - ofs)) 2560 *sz = gran - ofs; 2561 return (va + ofs); 2562 } 2563 2564 /* Minidumps are based on virtual memory addresses. */ 2565 va = md->md_vaddr + ofs; 2566 if (va >= kernstart + kernsize) { 2567 gran = PAGE_SIZE - (va & PAGE_MASK); 2568 if (*sz > gran) 2569 *sz = gran; 2570 } 2571 return (va); 2572 } 2573 2574 void 2575 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2576 vm_offset_t va) 2577 { 2578 2579 /* Raw physical memory dumps don't have a virtual address. */ 2580 if (md->md_vaddr == ~0UL) { 2581 tlb1_idx--; 2582 tlb1[tlb1_idx].mas1 = 0; 2583 tlb1[tlb1_idx].mas2 = 0; 2584 tlb1[tlb1_idx].mas3 = 0; 2585 tlb1_write_entry(tlb1_idx); 2586 return; 2587 } 2588 2589 /* Minidumps are based on virtual memory addresses. */ 2590 /* Nothing to do... */ 2591 } 2592 2593 struct pmap_md * 2594 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2595 { 2596 static struct pmap_md md; 2597 pte_t *pte; 2598 vm_offset_t va; 2599 2600 if (dumpsys_minidump) { 2601 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2602 if (prev == NULL) { 2603 /* 1st: kernel .data and .bss. */ 2604 md.md_index = 1; 2605 md.md_vaddr = trunc_page((uintptr_t)_etext); 2606 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2607 return (&md); 2608 } 2609 switch (prev->md_index) { 2610 case 1: 2611 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2612 md.md_index = 2; 2613 md.md_vaddr = data_start; 2614 md.md_size = data_end - data_start; 2615 break; 2616 case 2: 2617 /* 3rd: kernel VM. */ 2618 va = prev->md_vaddr + prev->md_size; 2619 /* Find start of next chunk (from va). */ 2620 while (va < virtual_end) { 2621 /* Don't dump the buffer cache. */ 2622 if (va >= kmi.buffer_sva && 2623 va < kmi.buffer_eva) { 2624 va = kmi.buffer_eva; 2625 continue; 2626 } 2627 pte = pte_find(mmu, kernel_pmap, va); 2628 if (pte != NULL && PTE_ISVALID(pte)) 2629 break; 2630 va += PAGE_SIZE; 2631 } 2632 if (va < virtual_end) { 2633 md.md_vaddr = va; 2634 va += PAGE_SIZE; 2635 /* Find last page in chunk. */ 2636 while (va < virtual_end) { 2637 /* Don't run into the buffer cache. */ 2638 if (va == kmi.buffer_sva) 2639 break; 2640 pte = pte_find(mmu, kernel_pmap, va); 2641 if (pte == NULL || !PTE_ISVALID(pte)) 2642 break; 2643 va += PAGE_SIZE; 2644 } 2645 md.md_size = va - md.md_vaddr; 2646 break; 2647 } 2648 md.md_index = 3; 2649 /* FALLTHROUGH */ 2650 default: 2651 return (NULL); 2652 } 2653 } else { /* minidumps */ 2654 mem_regions(&physmem_regions, &physmem_regions_sz, 2655 &availmem_regions, &availmem_regions_sz); 2656 2657 if (prev == NULL) { 2658 /* first physical chunk. */ 2659 md.md_paddr = physmem_regions[0].mr_start; 2660 md.md_size = physmem_regions[0].mr_size; 2661 md.md_vaddr = ~0UL; 2662 md.md_index = 1; 2663 } else if (md.md_index < physmem_regions_sz) { 2664 md.md_paddr = physmem_regions[md.md_index].mr_start; 2665 md.md_size = physmem_regions[md.md_index].mr_size; 2666 md.md_vaddr = ~0UL; 2667 md.md_index++; 2668 } else { 2669 /* There's no next physical chunk. */ 2670 return (NULL); 2671 } 2672 } 2673 2674 return (&md); 2675 } 2676 2677 /* 2678 * Map a set of physical memory pages into the kernel virtual address space. 2679 * Return a pointer to where it is mapped. This routine is intended to be used 2680 * for mapping device memory, NOT real memory. 2681 */ 2682 static void * 2683 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2684 { 2685 2686 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2687 } 2688 2689 static void * 2690 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2691 { 2692 void *res; 2693 uintptr_t va; 2694 vm_size_t sz; 2695 int i; 2696 2697 /* 2698 * Check if this is premapped in TLB1. Note: this should probably also 2699 * check whether a sequence of TLB1 entries exist that match the 2700 * requirement, but now only checks the easy case. 2701 */ 2702 if (ma == VM_MEMATTR_DEFAULT) { 2703 for (i = 0; i < tlb1_idx; i++) { 2704 if (!(tlb1[i].mas1 & MAS1_VALID)) 2705 continue; 2706 if (pa >= tlb1[i].phys && 2707 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2708 return (void *)(tlb1[i].virt + 2709 (pa - tlb1[i].phys)); 2710 } 2711 } 2712 2713 size = roundup(size, PAGE_SIZE); 2714 2715 /* 2716 * We leave a hole for device direct mapping between the maximum user 2717 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2718 * devices are in there, just map them 1:1. If not, map them to the 2719 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2720 * addresses should be pulled from an allocator, but since we do not 2721 * ever free TLB1 entries, it is safe just to increment a counter. 2722 * Note that there isn't a lot of address space here (128 MB) and it 2723 * is not at all difficult to imagine running out, since that is a 4:1 2724 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2725 * mapped there. 2726 */ 2727 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2728 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2729 va = pa; 2730 else 2731 va = atomic_fetchadd_int(&tlb1_map_base, size); 2732 res = (void *)va; 2733 2734 do { 2735 sz = 1 << (ilog2(size) & ~1); 2736 if (bootverbose) 2737 printf("Wiring VA=%x to PA=%x (size=%x), " 2738 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2739 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2740 size -= sz; 2741 pa += sz; 2742 va += sz; 2743 } while (size > 0); 2744 2745 return (res); 2746 } 2747 2748 /* 2749 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2750 */ 2751 static void 2752 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2753 { 2754 #ifdef SUPPORTS_SHRINKING_TLB1 2755 vm_offset_t base, offset; 2756 2757 /* 2758 * Unmap only if this is inside kernel virtual space. 2759 */ 2760 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2761 base = trunc_page(va); 2762 offset = va & PAGE_MASK; 2763 size = roundup(offset + size, PAGE_SIZE); 2764 kva_free(base, size); 2765 } 2766 #endif 2767 } 2768 2769 /* 2770 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2771 * specified pmap. This eliminates the blast of soft faults on process startup 2772 * and immediately after an mmap. 2773 */ 2774 static void 2775 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2776 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2777 { 2778 2779 VM_OBJECT_ASSERT_WLOCKED(object); 2780 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2781 ("mmu_booke_object_init_pt: non-device object")); 2782 } 2783 2784 /* 2785 * Perform the pmap work for mincore. 2786 */ 2787 static int 2788 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2789 vm_paddr_t *locked_pa) 2790 { 2791 2792 /* XXX: this should be implemented at some point */ 2793 return (0); 2794 } 2795 2796 /**************************************************************************/ 2797 /* TID handling */ 2798 /**************************************************************************/ 2799 2800 /* 2801 * Allocate a TID. If necessary, steal one from someone else. 2802 * The new TID is flushed from the TLB before returning. 2803 */ 2804 static tlbtid_t 2805 tid_alloc(pmap_t pmap) 2806 { 2807 tlbtid_t tid; 2808 int thiscpu; 2809 2810 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2811 2812 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2813 2814 thiscpu = PCPU_GET(cpuid); 2815 2816 tid = PCPU_GET(tid_next); 2817 if (tid > TID_MAX) 2818 tid = TID_MIN; 2819 PCPU_SET(tid_next, tid + 1); 2820 2821 /* If we are stealing TID then clear the relevant pmap's field */ 2822 if (tidbusy[thiscpu][tid] != NULL) { 2823 2824 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2825 2826 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2827 2828 /* Flush all entries from TLB0 matching this TID. */ 2829 tid_flush(tid); 2830 } 2831 2832 tidbusy[thiscpu][tid] = pmap; 2833 pmap->pm_tid[thiscpu] = tid; 2834 __asm __volatile("msync; isync"); 2835 2836 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2837 PCPU_GET(tid_next)); 2838 2839 return (tid); 2840 } 2841 2842 /**************************************************************************/ 2843 /* TLB0 handling */ 2844 /**************************************************************************/ 2845 2846 static void 2847 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2848 uint32_t mas7) 2849 { 2850 int as; 2851 char desc[3]; 2852 tlbtid_t tid; 2853 vm_size_t size; 2854 unsigned int tsize; 2855 2856 desc[2] = '\0'; 2857 if (mas1 & MAS1_VALID) 2858 desc[0] = 'V'; 2859 else 2860 desc[0] = ' '; 2861 2862 if (mas1 & MAS1_IPROT) 2863 desc[1] = 'P'; 2864 else 2865 desc[1] = ' '; 2866 2867 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2868 tid = MAS1_GETTID(mas1); 2869 2870 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2871 size = 0; 2872 if (tsize) 2873 size = tsize2size(tsize); 2874 2875 debugf("%3d: (%s) [AS=%d] " 2876 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2877 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2878 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2879 } 2880 2881 /* Convert TLB0 va and way number to tlb0[] table index. */ 2882 static inline unsigned int 2883 tlb0_tableidx(vm_offset_t va, unsigned int way) 2884 { 2885 unsigned int idx; 2886 2887 idx = (way * TLB0_ENTRIES_PER_WAY); 2888 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2889 return (idx); 2890 } 2891 2892 /* 2893 * Invalidate TLB0 entry. 2894 */ 2895 static inline void 2896 tlb0_flush_entry(vm_offset_t va) 2897 { 2898 2899 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2900 2901 mtx_assert(&tlbivax_mutex, MA_OWNED); 2902 2903 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2904 __asm __volatile("isync; msync"); 2905 __asm __volatile("tlbsync; msync"); 2906 2907 CTR1(KTR_PMAP, "%s: e", __func__); 2908 } 2909 2910 /* Print out contents of the MAS registers for each TLB0 entry */ 2911 void 2912 tlb0_print_tlbentries(void) 2913 { 2914 uint32_t mas0, mas1, mas2, mas3, mas7; 2915 int entryidx, way, idx; 2916 2917 debugf("TLB0 entries:\n"); 2918 for (way = 0; way < TLB0_WAYS; way ++) 2919 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2920 2921 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2922 mtspr(SPR_MAS0, mas0); 2923 __asm __volatile("isync"); 2924 2925 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2926 mtspr(SPR_MAS2, mas2); 2927 2928 __asm __volatile("isync; tlbre"); 2929 2930 mas1 = mfspr(SPR_MAS1); 2931 mas2 = mfspr(SPR_MAS2); 2932 mas3 = mfspr(SPR_MAS3); 2933 mas7 = mfspr(SPR_MAS7); 2934 2935 idx = tlb0_tableidx(mas2, way); 2936 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2937 } 2938 } 2939 2940 /**************************************************************************/ 2941 /* TLB1 handling */ 2942 /**************************************************************************/ 2943 2944 /* 2945 * TLB1 mapping notes: 2946 * 2947 * TLB1[0] Kernel text and data. 2948 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2949 * windows, other devices mappings. 2950 */ 2951 2952 /* 2953 * Write given entry to TLB1 hardware. 2954 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2955 */ 2956 static void 2957 tlb1_write_entry(unsigned int idx) 2958 { 2959 uint32_t mas0, mas7; 2960 2961 //debugf("tlb1_write_entry: s\n"); 2962 2963 /* Clear high order RPN bits */ 2964 mas7 = 0; 2965 2966 /* Select entry */ 2967 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2968 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2969 2970 mtspr(SPR_MAS0, mas0); 2971 __asm __volatile("isync"); 2972 mtspr(SPR_MAS1, tlb1[idx].mas1); 2973 __asm __volatile("isync"); 2974 mtspr(SPR_MAS2, tlb1[idx].mas2); 2975 __asm __volatile("isync"); 2976 mtspr(SPR_MAS3, tlb1[idx].mas3); 2977 __asm __volatile("isync"); 2978 mtspr(SPR_MAS7, mas7); 2979 __asm __volatile("isync; tlbwe; isync; msync"); 2980 2981 //debugf("tlb1_write_entry: e\n"); 2982 } 2983 2984 /* 2985 * Return the largest uint value log such that 2^log <= num. 2986 */ 2987 static unsigned int 2988 ilog2(unsigned int num) 2989 { 2990 int lz; 2991 2992 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2993 return (31 - lz); 2994 } 2995 2996 /* 2997 * Convert TLB TSIZE value to mapped region size. 2998 */ 2999 static vm_size_t 3000 tsize2size(unsigned int tsize) 3001 { 3002 3003 /* 3004 * size = 4^tsize KB 3005 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3006 */ 3007 3008 return ((1 << (2 * tsize)) * 1024); 3009 } 3010 3011 /* 3012 * Convert region size (must be power of 4) to TLB TSIZE value. 3013 */ 3014 static unsigned int 3015 size2tsize(vm_size_t size) 3016 { 3017 3018 return (ilog2(size) / 2 - 5); 3019 } 3020 3021 /* 3022 * Register permanent kernel mapping in TLB1. 3023 * 3024 * Entries are created starting from index 0 (current free entry is 3025 * kept in tlb1_idx) and are not supposed to be invalidated. 3026 */ 3027 static int 3028 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 3029 uint32_t flags) 3030 { 3031 uint32_t ts, tid; 3032 int tsize, index; 3033 3034 index = atomic_fetchadd_int(&tlb1_idx, 1); 3035 if (index >= TLB1_ENTRIES) { 3036 printf("tlb1_set_entry: TLB1 full!\n"); 3037 return (-1); 3038 } 3039 3040 /* Convert size to TSIZE */ 3041 tsize = size2tsize(size); 3042 3043 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3044 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3045 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3046 3047 /* 3048 * Atomicity is preserved by the atomic increment above since nothing 3049 * is ever removed from tlb1. 3050 */ 3051 3052 tlb1[index].phys = pa; 3053 tlb1[index].virt = va; 3054 tlb1[index].size = size; 3055 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3056 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3057 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3058 3059 /* Set supervisor RWX permission bits */ 3060 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3061 3062 tlb1_write_entry(index); 3063 3064 /* 3065 * XXX in general TLB1 updates should be propagated between CPUs, 3066 * since current design assumes to have the same TLB1 set-up on all 3067 * cores. 3068 */ 3069 return (0); 3070 } 3071 3072 /* 3073 * Map in contiguous RAM region into the TLB1 using maximum of 3074 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3075 * 3076 * If necessary round up last entry size and return total size 3077 * used by all allocated entries. 3078 */ 3079 vm_size_t 3080 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3081 { 3082 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3083 vm_size_t mapped, pgsz, base, mask; 3084 int idx, nents; 3085 3086 /* Round up to the next 1M */ 3087 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3088 3089 mapped = 0; 3090 idx = 0; 3091 base = va; 3092 pgsz = 64*1024*1024; 3093 while (mapped < size) { 3094 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3095 while (pgsz > (size - mapped)) 3096 pgsz >>= 2; 3097 pgs[idx++] = pgsz; 3098 mapped += pgsz; 3099 } 3100 3101 /* We under-map. Correct for this. */ 3102 if (mapped < size) { 3103 while (pgs[idx - 1] == pgsz) { 3104 idx--; 3105 mapped -= pgsz; 3106 } 3107 /* XXX We may increase beyond out starting point. */ 3108 pgsz <<= 2; 3109 pgs[idx++] = pgsz; 3110 mapped += pgsz; 3111 } 3112 } 3113 3114 nents = idx; 3115 mask = pgs[0] - 1; 3116 /* Align address to the boundary */ 3117 if (va & mask) { 3118 va = (va + mask) & ~mask; 3119 pa = (pa + mask) & ~mask; 3120 } 3121 3122 for (idx = 0; idx < nents; idx++) { 3123 pgsz = pgs[idx]; 3124 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3125 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3126 pa += pgsz; 3127 va += pgsz; 3128 } 3129 3130 mapped = (va - base); 3131 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3132 mapped, mapped - size); 3133 return (mapped); 3134 } 3135 3136 /* 3137 * TLB1 initialization routine, to be called after the very first 3138 * assembler level setup done in locore.S. 3139 */ 3140 void 3141 tlb1_init() 3142 { 3143 uint32_t mas0, mas1, mas2, mas3; 3144 uint32_t tsz; 3145 u_int i; 3146 3147 if (bootinfo != NULL && bootinfo[0] != 1) { 3148 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3149 } else 3150 tlb1_idx = 1; 3151 3152 /* The first entry/entries are used to map the kernel. */ 3153 for (i = 0; i < tlb1_idx; i++) { 3154 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3155 mtspr(SPR_MAS0, mas0); 3156 __asm __volatile("isync; tlbre"); 3157 3158 mas1 = mfspr(SPR_MAS1); 3159 if ((mas1 & MAS1_VALID) == 0) 3160 continue; 3161 3162 mas2 = mfspr(SPR_MAS2); 3163 mas3 = mfspr(SPR_MAS3); 3164 3165 tlb1[i].mas1 = mas1; 3166 tlb1[i].mas2 = mfspr(SPR_MAS2); 3167 tlb1[i].mas3 = mas3; 3168 tlb1[i].virt = mas2 & MAS2_EPN_MASK; 3169 tlb1[i].phys = mas3 & MAS3_RPN; 3170 3171 if (i == 0) 3172 kernload = mas3 & MAS3_RPN; 3173 3174 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3175 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0; 3176 kernsize += tlb1[i].size; 3177 } 3178 3179 #ifdef SMP 3180 bp_ntlb1s = tlb1_idx; 3181 #endif 3182 3183 /* Purge the remaining entries */ 3184 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3185 tlb1_write_entry(i); 3186 3187 /* Setup TLB miss defaults */ 3188 set_mas4_defaults(); 3189 } 3190 3191 vm_offset_t 3192 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3193 { 3194 vm_paddr_t pa_base; 3195 vm_offset_t va, sz; 3196 int i; 3197 3198 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3199 3200 for (i = 0; i < tlb1_idx; i++) { 3201 if (!(tlb1[i].mas1 & MAS1_VALID)) 3202 continue; 3203 if (pa >= tlb1[i].phys && (pa + size) <= 3204 (tlb1[i].phys + tlb1[i].size)) 3205 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3206 } 3207 3208 pa_base = trunc_page(pa); 3209 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3210 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3211 va = tlb1_map_base + (pa - pa_base); 3212 3213 do { 3214 sz = 1 << (ilog2(size) & ~1); 3215 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3216 size -= sz; 3217 pa_base += sz; 3218 tlb1_map_base += sz; 3219 } while (size > 0); 3220 3221 #ifdef SMP 3222 bp_ntlb1s = tlb1_idx; 3223 #endif 3224 3225 return (va); 3226 } 3227 3228 /* 3229 * Setup MAS4 defaults. 3230 * These values are loaded to MAS0-2 on a TLB miss. 3231 */ 3232 static void 3233 set_mas4_defaults(void) 3234 { 3235 uint32_t mas4; 3236 3237 /* Defaults: TLB0, PID0, TSIZED=4K */ 3238 mas4 = MAS4_TLBSELD0; 3239 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3240 #ifdef SMP 3241 mas4 |= MAS4_MD; 3242 #endif 3243 mtspr(SPR_MAS4, mas4); 3244 __asm __volatile("isync"); 3245 } 3246 3247 /* 3248 * Print out contents of the MAS registers for each TLB1 entry 3249 */ 3250 void 3251 tlb1_print_tlbentries(void) 3252 { 3253 uint32_t mas0, mas1, mas2, mas3, mas7; 3254 int i; 3255 3256 debugf("TLB1 entries:\n"); 3257 for (i = 0; i < TLB1_ENTRIES; i++) { 3258 3259 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3260 mtspr(SPR_MAS0, mas0); 3261 3262 __asm __volatile("isync; tlbre"); 3263 3264 mas1 = mfspr(SPR_MAS1); 3265 mas2 = mfspr(SPR_MAS2); 3266 mas3 = mfspr(SPR_MAS3); 3267 mas7 = mfspr(SPR_MAS7); 3268 3269 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3270 } 3271 } 3272 3273 /* 3274 * Print out contents of the in-ram tlb1 table. 3275 */ 3276 void 3277 tlb1_print_entries(void) 3278 { 3279 int i; 3280 3281 debugf("tlb1[] table entries:\n"); 3282 for (i = 0; i < TLB1_ENTRIES; i++) 3283 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3284 } 3285 3286 /* 3287 * Return 0 if the physical IO range is encompassed by one of the 3288 * the TLB1 entries, otherwise return related error code. 3289 */ 3290 static int 3291 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3292 { 3293 uint32_t prot; 3294 vm_paddr_t pa_start; 3295 vm_paddr_t pa_end; 3296 unsigned int entry_tsize; 3297 vm_size_t entry_size; 3298 3299 *va = (vm_offset_t)NULL; 3300 3301 /* Skip invalid entries */ 3302 if (!(tlb1[i].mas1 & MAS1_VALID)) 3303 return (EINVAL); 3304 3305 /* 3306 * The entry must be cache-inhibited, guarded, and r/w 3307 * so it can function as an i/o page 3308 */ 3309 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3310 if (prot != (MAS2_I | MAS2_G)) 3311 return (EPERM); 3312 3313 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3314 if (prot != (MAS3_SR | MAS3_SW)) 3315 return (EPERM); 3316 3317 /* The address should be within the entry range. */ 3318 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3319 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3320 3321 entry_size = tsize2size(entry_tsize); 3322 pa_start = tlb1[i].mas3 & MAS3_RPN; 3323 pa_end = pa_start + entry_size - 1; 3324 3325 if ((pa < pa_start) || ((pa + size) > pa_end)) 3326 return (ERANGE); 3327 3328 /* Return virtual address of this mapping. */ 3329 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3330 return (0); 3331 } 3332