1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #ifdef DEBUG 100 #define debugf(fmt, args...) printf(fmt, ##args) 101 #else 102 #define debugf(fmt, args...) 103 #endif 104 105 #define TODO panic("%s: not implemented", __func__); 106 107 extern unsigned char _etext[]; 108 extern unsigned char _end[]; 109 110 extern uint32_t *bootinfo; 111 112 #ifdef SMP 113 extern uint32_t bp_ntlb1s; 114 #endif 115 116 vm_paddr_t kernload; 117 vm_offset_t kernstart; 118 vm_size_t kernsize; 119 120 /* Message buffer and tables. */ 121 static vm_offset_t data_start; 122 static vm_size_t data_end; 123 124 /* Phys/avail memory regions. */ 125 static struct mem_region *availmem_regions; 126 static int availmem_regions_sz; 127 static struct mem_region *physmem_regions; 128 static int physmem_regions_sz; 129 130 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 131 static vm_offset_t zero_page_va; 132 static struct mtx zero_page_mutex; 133 134 static struct mtx tlbivax_mutex; 135 136 /* 137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 138 * by idle thred only, no lock required. 139 */ 140 static vm_offset_t zero_page_idle_va; 141 142 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 143 static vm_offset_t copy_page_src_va; 144 static vm_offset_t copy_page_dst_va; 145 static struct mtx copy_page_mutex; 146 147 /**************************************************************************/ 148 /* PMAP */ 149 /**************************************************************************/ 150 151 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 152 vm_prot_t, u_int flags, int8_t psind); 153 154 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 155 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 156 157 /* 158 * If user pmap is processed with mmu_booke_remove and the resident count 159 * drops to 0, there are no more pages to remove, so we need not continue. 160 */ 161 #define PMAP_REMOVE_DONE(pmap) \ 162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 163 164 extern int elf32_nxstack; 165 166 /**************************************************************************/ 167 /* TLB and TID handling */ 168 /**************************************************************************/ 169 170 /* Translation ID busy table */ 171 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 172 173 /* 174 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 175 * core revisions and should be read from h/w registers during early config. 176 */ 177 uint32_t tlb0_entries; 178 uint32_t tlb0_ways; 179 uint32_t tlb0_entries_per_way; 180 uint32_t tlb1_entries; 181 182 #define TLB0_ENTRIES (tlb0_entries) 183 #define TLB0_WAYS (tlb0_ways) 184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186 #define TLB1_ENTRIES (tlb1_entries) 187 #define TLB1_MAXENTRIES 64 188 189 /* In-ram copy of the TLB1 */ 190 static tlb_entry_t tlb1[TLB1_MAXENTRIES]; 191 192 /* Next free entry in the TLB1 */ 193 static unsigned int tlb1_idx; 194 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 195 196 static tlbtid_t tid_alloc(struct pmap *); 197 static void tid_flush(tlbtid_t tid); 198 199 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 200 201 static int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t); 202 static void tlb1_write_entry(unsigned int); 203 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 204 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 205 206 static vm_size_t tsize2size(unsigned int); 207 static unsigned int size2tsize(vm_size_t); 208 static unsigned int ilog2(unsigned int); 209 210 static void set_mas4_defaults(void); 211 212 static inline void tlb0_flush_entry(vm_offset_t); 213 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 214 215 /**************************************************************************/ 216 /* Page table management */ 217 /**************************************************************************/ 218 219 static struct rwlock_padalign pvh_global_lock; 220 221 /* Data for the pv entry allocation mechanism */ 222 static uma_zone_t pvzone; 223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227 #ifndef PMAP_SHPGPERPROC 228 #define PMAP_SHPGPERPROC 200 229 #endif 230 231 static void ptbl_init(void); 232 static struct ptbl_buf *ptbl_buf_alloc(void); 233 static void ptbl_buf_free(struct ptbl_buf *); 234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 237 static void ptbl_free(mmu_t, pmap_t, unsigned int); 238 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 245 246 static pv_entry_t pv_alloc(void); 247 static void pv_free(pv_entry_t); 248 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 249 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 250 251 static void booke_pmap_init_qpages(void); 252 253 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 254 #define PTBL_BUFS (128 * 16) 255 256 struct ptbl_buf { 257 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 258 vm_offset_t kva; /* va of mapping */ 259 }; 260 261 /* ptbl free list and a lock used for access synchronization. */ 262 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 263 static struct mtx ptbl_buf_freelist_lock; 264 265 /* Base address of kva space allocated fot ptbl bufs. */ 266 static vm_offset_t ptbl_buf_pool_vabase; 267 268 /* Pointer to ptbl_buf structures. */ 269 static struct ptbl_buf *ptbl_bufs; 270 271 #ifdef SMP 272 void pmap_bootstrap_ap(volatile uint32_t *); 273 #endif 274 275 /* 276 * Kernel MMU interface 277 */ 278 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 279 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 280 vm_size_t, vm_offset_t); 281 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 282 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 283 vm_offset_t, vm_page_t *, vm_offset_t, int); 284 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 285 vm_prot_t, u_int flags, int8_t psind); 286 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 287 vm_page_t, vm_prot_t); 288 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 289 vm_prot_t); 290 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 291 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 292 vm_prot_t); 293 static void mmu_booke_init(mmu_t); 294 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 295 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 296 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 297 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 298 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 299 int); 300 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 301 vm_paddr_t *); 302 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 303 vm_object_t, vm_pindex_t, vm_size_t); 304 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 305 static void mmu_booke_page_init(mmu_t, vm_page_t); 306 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 307 static void mmu_booke_pinit(mmu_t, pmap_t); 308 static void mmu_booke_pinit0(mmu_t, pmap_t); 309 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 310 vm_prot_t); 311 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 312 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 313 static void mmu_booke_release(mmu_t, pmap_t); 314 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 315 static void mmu_booke_remove_all(mmu_t, vm_page_t); 316 static void mmu_booke_remove_write(mmu_t, vm_page_t); 317 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 318 static void mmu_booke_zero_page(mmu_t, vm_page_t); 319 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 320 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 321 static void mmu_booke_activate(mmu_t, struct thread *); 322 static void mmu_booke_deactivate(mmu_t, struct thread *); 323 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 324 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 325 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 326 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 327 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 328 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 329 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 330 static void mmu_booke_kremove(mmu_t, vm_offset_t); 331 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 332 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 333 vm_size_t); 334 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 335 void **); 336 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 337 void *); 338 static void mmu_booke_scan_init(mmu_t); 339 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 340 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 341 342 static mmu_method_t mmu_booke_methods[] = { 343 /* pmap dispatcher interface */ 344 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 345 MMUMETHOD(mmu_copy, mmu_booke_copy), 346 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 347 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 348 MMUMETHOD(mmu_enter, mmu_booke_enter), 349 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 350 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 351 MMUMETHOD(mmu_extract, mmu_booke_extract), 352 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 353 MMUMETHOD(mmu_init, mmu_booke_init), 354 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 355 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 356 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 357 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 358 MMUMETHOD(mmu_map, mmu_booke_map), 359 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 360 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 361 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 362 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 363 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 364 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 365 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 366 MMUMETHOD(mmu_protect, mmu_booke_protect), 367 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 368 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 369 MMUMETHOD(mmu_release, mmu_booke_release), 370 MMUMETHOD(mmu_remove, mmu_booke_remove), 371 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 372 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 373 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 374 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 375 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 376 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 377 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 378 MMUMETHOD(mmu_activate, mmu_booke_activate), 379 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 380 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 381 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 382 383 /* Internal interfaces */ 384 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 385 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 386 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 387 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 388 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 389 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 390 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 391 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 392 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 393 394 /* dumpsys() support */ 395 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 396 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 397 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 398 399 { 0, 0 } 400 }; 401 402 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 403 404 static __inline uint32_t 405 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 406 { 407 uint32_t attrib; 408 int i; 409 410 if (ma != VM_MEMATTR_DEFAULT) { 411 switch (ma) { 412 case VM_MEMATTR_UNCACHEABLE: 413 return (PTE_I | PTE_G); 414 case VM_MEMATTR_WRITE_COMBINING: 415 case VM_MEMATTR_WRITE_BACK: 416 case VM_MEMATTR_PREFETCHABLE: 417 return (PTE_I); 418 case VM_MEMATTR_WRITE_THROUGH: 419 return (PTE_W | PTE_M); 420 } 421 } 422 423 /* 424 * Assume the page is cache inhibited and access is guarded unless 425 * it's in our available memory array. 426 */ 427 attrib = _TLB_ENTRY_IO; 428 for (i = 0; i < physmem_regions_sz; i++) { 429 if ((pa >= physmem_regions[i].mr_start) && 430 (pa < (physmem_regions[i].mr_start + 431 physmem_regions[i].mr_size))) { 432 attrib = _TLB_ENTRY_MEM; 433 break; 434 } 435 } 436 437 return (attrib); 438 } 439 440 static inline void 441 tlb_miss_lock(void) 442 { 443 #ifdef SMP 444 struct pcpu *pc; 445 446 if (!smp_started) 447 return; 448 449 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 450 if (pc != pcpup) { 451 452 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 453 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 454 455 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 456 ("tlb_miss_lock: tried to lock self")); 457 458 tlb_lock(pc->pc_booke_tlb_lock); 459 460 CTR1(KTR_PMAP, "%s: locked", __func__); 461 } 462 } 463 #endif 464 } 465 466 static inline void 467 tlb_miss_unlock(void) 468 { 469 #ifdef SMP 470 struct pcpu *pc; 471 472 if (!smp_started) 473 return; 474 475 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 476 if (pc != pcpup) { 477 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 478 __func__, pc->pc_cpuid); 479 480 tlb_unlock(pc->pc_booke_tlb_lock); 481 482 CTR1(KTR_PMAP, "%s: unlocked", __func__); 483 } 484 } 485 #endif 486 } 487 488 /* Return number of entries in TLB0. */ 489 static __inline void 490 tlb0_get_tlbconf(void) 491 { 492 uint32_t tlb0_cfg; 493 494 tlb0_cfg = mfspr(SPR_TLB0CFG); 495 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 496 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 497 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 498 } 499 500 /* Return number of entries in TLB1. */ 501 static __inline void 502 tlb1_get_tlbconf(void) 503 { 504 uint32_t tlb1_cfg; 505 506 tlb1_cfg = mfspr(SPR_TLB1CFG); 507 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 508 } 509 510 /* Initialize pool of kva ptbl buffers. */ 511 static void 512 ptbl_init(void) 513 { 514 int i; 515 516 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 517 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 518 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 519 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 520 521 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 522 TAILQ_INIT(&ptbl_buf_freelist); 523 524 for (i = 0; i < PTBL_BUFS; i++) { 525 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 526 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 527 } 528 } 529 530 /* Get a ptbl_buf from the freelist. */ 531 static struct ptbl_buf * 532 ptbl_buf_alloc(void) 533 { 534 struct ptbl_buf *buf; 535 536 mtx_lock(&ptbl_buf_freelist_lock); 537 buf = TAILQ_FIRST(&ptbl_buf_freelist); 538 if (buf != NULL) 539 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 540 mtx_unlock(&ptbl_buf_freelist_lock); 541 542 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 543 544 return (buf); 545 } 546 547 /* Return ptbl buff to free pool. */ 548 static void 549 ptbl_buf_free(struct ptbl_buf *buf) 550 { 551 552 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 553 554 mtx_lock(&ptbl_buf_freelist_lock); 555 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 556 mtx_unlock(&ptbl_buf_freelist_lock); 557 } 558 559 /* 560 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 561 */ 562 static void 563 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 564 { 565 struct ptbl_buf *pbuf; 566 567 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 568 569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 570 571 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 572 if (pbuf->kva == (vm_offset_t)ptbl) { 573 /* Remove from pmap ptbl buf list. */ 574 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 575 576 /* Free corresponding ptbl buf. */ 577 ptbl_buf_free(pbuf); 578 break; 579 } 580 } 581 582 /* Allocate page table. */ 583 static pte_t * 584 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 585 { 586 vm_page_t mtbl[PTBL_PAGES]; 587 vm_page_t m; 588 struct ptbl_buf *pbuf; 589 unsigned int pidx; 590 pte_t *ptbl; 591 int i, j; 592 593 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 594 (pmap == kernel_pmap), pdir_idx); 595 596 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 597 ("ptbl_alloc: invalid pdir_idx")); 598 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 599 ("pte_alloc: valid ptbl entry exists!")); 600 601 pbuf = ptbl_buf_alloc(); 602 if (pbuf == NULL) 603 panic("pte_alloc: couldn't alloc kernel virtual memory"); 604 605 ptbl = (pte_t *)pbuf->kva; 606 607 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 608 609 /* Allocate ptbl pages, this will sleep! */ 610 for (i = 0; i < PTBL_PAGES; i++) { 611 pidx = (PTBL_PAGES * pdir_idx) + i; 612 while ((m = vm_page_alloc(NULL, pidx, 613 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 614 PMAP_UNLOCK(pmap); 615 rw_wunlock(&pvh_global_lock); 616 if (nosleep) { 617 ptbl_free_pmap_ptbl(pmap, ptbl); 618 for (j = 0; j < i; j++) 619 vm_page_free(mtbl[j]); 620 atomic_subtract_int(&vm_cnt.v_wire_count, i); 621 return (NULL); 622 } 623 VM_WAIT; 624 rw_wlock(&pvh_global_lock); 625 PMAP_LOCK(pmap); 626 } 627 mtbl[i] = m; 628 } 629 630 /* Map allocated pages into kernel_pmap. */ 631 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 632 633 /* Zero whole ptbl. */ 634 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 635 636 /* Add pbuf to the pmap ptbl bufs list. */ 637 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 638 639 return (ptbl); 640 } 641 642 /* Free ptbl pages and invalidate pdir entry. */ 643 static void 644 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 645 { 646 pte_t *ptbl; 647 vm_paddr_t pa; 648 vm_offset_t va; 649 vm_page_t m; 650 int i; 651 652 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 653 (pmap == kernel_pmap), pdir_idx); 654 655 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 656 ("ptbl_free: invalid pdir_idx")); 657 658 ptbl = pmap->pm_pdir[pdir_idx]; 659 660 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 661 662 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 663 664 /* 665 * Invalidate the pdir entry as soon as possible, so that other CPUs 666 * don't attempt to look up the page tables we are releasing. 667 */ 668 mtx_lock_spin(&tlbivax_mutex); 669 tlb_miss_lock(); 670 671 pmap->pm_pdir[pdir_idx] = NULL; 672 673 tlb_miss_unlock(); 674 mtx_unlock_spin(&tlbivax_mutex); 675 676 for (i = 0; i < PTBL_PAGES; i++) { 677 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 678 pa = pte_vatopa(mmu, kernel_pmap, va); 679 m = PHYS_TO_VM_PAGE(pa); 680 vm_page_free_zero(m); 681 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 682 mmu_booke_kremove(mmu, va); 683 } 684 685 ptbl_free_pmap_ptbl(pmap, ptbl); 686 } 687 688 /* 689 * Decrement ptbl pages hold count and attempt to free ptbl pages. 690 * Called when removing pte entry from ptbl. 691 * 692 * Return 1 if ptbl pages were freed. 693 */ 694 static int 695 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 696 { 697 pte_t *ptbl; 698 vm_paddr_t pa; 699 vm_page_t m; 700 int i; 701 702 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 703 (pmap == kernel_pmap), pdir_idx); 704 705 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 706 ("ptbl_unhold: invalid pdir_idx")); 707 KASSERT((pmap != kernel_pmap), 708 ("ptbl_unhold: unholding kernel ptbl!")); 709 710 ptbl = pmap->pm_pdir[pdir_idx]; 711 712 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 713 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 714 ("ptbl_unhold: non kva ptbl")); 715 716 /* decrement hold count */ 717 for (i = 0; i < PTBL_PAGES; i++) { 718 pa = pte_vatopa(mmu, kernel_pmap, 719 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 720 m = PHYS_TO_VM_PAGE(pa); 721 m->wire_count--; 722 } 723 724 /* 725 * Free ptbl pages if there are no pte etries in this ptbl. 726 * wire_count has the same value for all ptbl pages, so check the last 727 * page. 728 */ 729 if (m->wire_count == 0) { 730 ptbl_free(mmu, pmap, pdir_idx); 731 732 //debugf("ptbl_unhold: e (freed ptbl)\n"); 733 return (1); 734 } 735 736 return (0); 737 } 738 739 /* 740 * Increment hold count for ptbl pages. This routine is used when a new pte 741 * entry is being inserted into the ptbl. 742 */ 743 static void 744 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 745 { 746 vm_paddr_t pa; 747 pte_t *ptbl; 748 vm_page_t m; 749 int i; 750 751 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 752 pdir_idx); 753 754 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 755 ("ptbl_hold: invalid pdir_idx")); 756 KASSERT((pmap != kernel_pmap), 757 ("ptbl_hold: holding kernel ptbl!")); 758 759 ptbl = pmap->pm_pdir[pdir_idx]; 760 761 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 762 763 for (i = 0; i < PTBL_PAGES; i++) { 764 pa = pte_vatopa(mmu, kernel_pmap, 765 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 766 m = PHYS_TO_VM_PAGE(pa); 767 m->wire_count++; 768 } 769 } 770 771 /* Allocate pv_entry structure. */ 772 pv_entry_t 773 pv_alloc(void) 774 { 775 pv_entry_t pv; 776 777 pv_entry_count++; 778 if (pv_entry_count > pv_entry_high_water) 779 pagedaemon_wakeup(); 780 pv = uma_zalloc(pvzone, M_NOWAIT); 781 782 return (pv); 783 } 784 785 /* Free pv_entry structure. */ 786 static __inline void 787 pv_free(pv_entry_t pve) 788 { 789 790 pv_entry_count--; 791 uma_zfree(pvzone, pve); 792 } 793 794 795 /* Allocate and initialize pv_entry structure. */ 796 static void 797 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 798 { 799 pv_entry_t pve; 800 801 //int su = (pmap == kernel_pmap); 802 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 803 // (u_int32_t)pmap, va, (u_int32_t)m); 804 805 pve = pv_alloc(); 806 if (pve == NULL) 807 panic("pv_insert: no pv entries!"); 808 809 pve->pv_pmap = pmap; 810 pve->pv_va = va; 811 812 /* add to pv_list */ 813 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 814 rw_assert(&pvh_global_lock, RA_WLOCKED); 815 816 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 817 818 //debugf("pv_insert: e\n"); 819 } 820 821 /* Destroy pv entry. */ 822 static void 823 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 824 { 825 pv_entry_t pve; 826 827 //int su = (pmap == kernel_pmap); 828 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 829 830 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 831 rw_assert(&pvh_global_lock, RA_WLOCKED); 832 833 /* find pv entry */ 834 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 835 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 836 /* remove from pv_list */ 837 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 838 if (TAILQ_EMPTY(&m->md.pv_list)) 839 vm_page_aflag_clear(m, PGA_WRITEABLE); 840 841 /* free pv entry struct */ 842 pv_free(pve); 843 break; 844 } 845 } 846 847 //debugf("pv_remove: e\n"); 848 } 849 850 /* 851 * Clean pte entry, try to free page table page if requested. 852 * 853 * Return 1 if ptbl pages were freed, otherwise return 0. 854 */ 855 static int 856 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 857 { 858 unsigned int pdir_idx = PDIR_IDX(va); 859 unsigned int ptbl_idx = PTBL_IDX(va); 860 vm_page_t m; 861 pte_t *ptbl; 862 pte_t *pte; 863 864 //int su = (pmap == kernel_pmap); 865 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 866 // su, (u_int32_t)pmap, va, flags); 867 868 ptbl = pmap->pm_pdir[pdir_idx]; 869 KASSERT(ptbl, ("pte_remove: null ptbl")); 870 871 pte = &ptbl[ptbl_idx]; 872 873 if (pte == NULL || !PTE_ISVALID(pte)) 874 return (0); 875 876 if (PTE_ISWIRED(pte)) 877 pmap->pm_stats.wired_count--; 878 879 /* Handle managed entry. */ 880 if (PTE_ISMANAGED(pte)) { 881 /* Get vm_page_t for mapped pte. */ 882 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 883 884 if (PTE_ISMODIFIED(pte)) 885 vm_page_dirty(m); 886 887 if (PTE_ISREFERENCED(pte)) 888 vm_page_aflag_set(m, PGA_REFERENCED); 889 890 pv_remove(pmap, va, m); 891 } 892 893 mtx_lock_spin(&tlbivax_mutex); 894 tlb_miss_lock(); 895 896 tlb0_flush_entry(va); 897 pte->flags = 0; 898 pte->rpn = 0; 899 900 tlb_miss_unlock(); 901 mtx_unlock_spin(&tlbivax_mutex); 902 903 pmap->pm_stats.resident_count--; 904 905 if (flags & PTBL_UNHOLD) { 906 //debugf("pte_remove: e (unhold)\n"); 907 return (ptbl_unhold(mmu, pmap, pdir_idx)); 908 } 909 910 //debugf("pte_remove: e\n"); 911 return (0); 912 } 913 914 /* 915 * Insert PTE for a given page and virtual address. 916 */ 917 static int 918 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 919 boolean_t nosleep) 920 { 921 unsigned int pdir_idx = PDIR_IDX(va); 922 unsigned int ptbl_idx = PTBL_IDX(va); 923 pte_t *ptbl, *pte; 924 925 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 926 pmap == kernel_pmap, pmap, va); 927 928 /* Get the page table pointer. */ 929 ptbl = pmap->pm_pdir[pdir_idx]; 930 931 if (ptbl == NULL) { 932 /* Allocate page table pages. */ 933 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 934 if (ptbl == NULL) { 935 KASSERT(nosleep, ("nosleep and NULL ptbl")); 936 return (ENOMEM); 937 } 938 } else { 939 /* 940 * Check if there is valid mapping for requested 941 * va, if there is, remove it. 942 */ 943 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 944 if (PTE_ISVALID(pte)) { 945 pte_remove(mmu, pmap, va, PTBL_HOLD); 946 } else { 947 /* 948 * pte is not used, increment hold count 949 * for ptbl pages. 950 */ 951 if (pmap != kernel_pmap) 952 ptbl_hold(mmu, pmap, pdir_idx); 953 } 954 } 955 956 /* 957 * Insert pv_entry into pv_list for mapped page if part of managed 958 * memory. 959 */ 960 if ((m->oflags & VPO_UNMANAGED) == 0) { 961 flags |= PTE_MANAGED; 962 963 /* Create and insert pv entry. */ 964 pv_insert(pmap, va, m); 965 } 966 967 pmap->pm_stats.resident_count++; 968 969 mtx_lock_spin(&tlbivax_mutex); 970 tlb_miss_lock(); 971 972 tlb0_flush_entry(va); 973 if (pmap->pm_pdir[pdir_idx] == NULL) { 974 /* 975 * If we just allocated a new page table, hook it in 976 * the pdir. 977 */ 978 pmap->pm_pdir[pdir_idx] = ptbl; 979 } 980 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 981 pte->rpn = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 982 pte->flags |= (PTE_VALID | flags); 983 984 tlb_miss_unlock(); 985 mtx_unlock_spin(&tlbivax_mutex); 986 return (0); 987 } 988 989 /* Return the pa for the given pmap/va. */ 990 static vm_paddr_t 991 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 992 { 993 vm_paddr_t pa = 0; 994 pte_t *pte; 995 996 pte = pte_find(mmu, pmap, va); 997 if ((pte != NULL) && PTE_ISVALID(pte)) 998 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 999 return (pa); 1000 } 1001 1002 /* Get a pointer to a PTE in a page table. */ 1003 static pte_t * 1004 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1005 { 1006 unsigned int pdir_idx = PDIR_IDX(va); 1007 unsigned int ptbl_idx = PTBL_IDX(va); 1008 1009 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1010 1011 if (pmap->pm_pdir[pdir_idx]) 1012 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1013 1014 return (NULL); 1015 } 1016 1017 /**************************************************************************/ 1018 /* PMAP related */ 1019 /**************************************************************************/ 1020 1021 /* 1022 * This is called during booke_init, before the system is really initialized. 1023 */ 1024 static void 1025 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1026 { 1027 vm_paddr_t phys_kernelend; 1028 struct mem_region *mp, *mp1; 1029 int cnt, i, j; 1030 vm_paddr_t s, e, sz; 1031 vm_paddr_t physsz, hwphyssz; 1032 u_int phys_avail_count; 1033 vm_size_t kstack0_sz; 1034 vm_offset_t kernel_pdir, kstack0, va; 1035 vm_paddr_t kstack0_phys; 1036 void *dpcpu; 1037 pte_t *pte; 1038 1039 debugf("mmu_booke_bootstrap: entered\n"); 1040 1041 /* Set interesting system properties */ 1042 hw_direct_map = 0; 1043 elf32_nxstack = 1; 1044 1045 /* Initialize invalidation mutex */ 1046 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1047 1048 /* Read TLB0 size and associativity. */ 1049 tlb0_get_tlbconf(); 1050 1051 /* 1052 * Align kernel start and end address (kernel image). 1053 * Note that kernel end does not necessarily relate to kernsize. 1054 * kernsize is the size of the kernel that is actually mapped. 1055 */ 1056 kernstart = trunc_page(start); 1057 data_start = round_page(kernelend); 1058 data_end = data_start; 1059 1060 /* 1061 * Addresses of preloaded modules (like file systems) use 1062 * physical addresses. Make sure we relocate those into 1063 * virtual addresses. 1064 */ 1065 preload_addr_relocate = kernstart - kernload; 1066 1067 /* Allocate the dynamic per-cpu area. */ 1068 dpcpu = (void *)data_end; 1069 data_end += DPCPU_SIZE; 1070 1071 /* Allocate space for the message buffer. */ 1072 msgbufp = (struct msgbuf *)data_end; 1073 data_end += msgbufsize; 1074 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1075 data_end); 1076 1077 data_end = round_page(data_end); 1078 1079 /* Allocate space for ptbl_bufs. */ 1080 ptbl_bufs = (struct ptbl_buf *)data_end; 1081 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1082 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1083 data_end); 1084 1085 data_end = round_page(data_end); 1086 1087 /* Allocate PTE tables for kernel KVA. */ 1088 kernel_pdir = data_end; 1089 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1090 PDIR_SIZE - 1) / PDIR_SIZE; 1091 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1092 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1093 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1094 1095 debugf(" data_end: 0x%08x\n", data_end); 1096 if (data_end - kernstart > kernsize) { 1097 kernsize += tlb1_mapin_region(kernstart + kernsize, 1098 kernload + kernsize, (data_end - kernstart) - kernsize); 1099 } 1100 data_end = kernstart + kernsize; 1101 debugf(" updated data_end: 0x%08x\n", data_end); 1102 1103 /* 1104 * Clear the structures - note we can only do it safely after the 1105 * possible additional TLB1 translations are in place (above) so that 1106 * all range up to the currently calculated 'data_end' is covered. 1107 */ 1108 dpcpu_init(dpcpu, 0); 1109 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1110 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1111 1112 /*******************************************************/ 1113 /* Set the start and end of kva. */ 1114 /*******************************************************/ 1115 virtual_avail = round_page(data_end); 1116 virtual_end = VM_MAX_KERNEL_ADDRESS; 1117 1118 /* Allocate KVA space for page zero/copy operations. */ 1119 zero_page_va = virtual_avail; 1120 virtual_avail += PAGE_SIZE; 1121 zero_page_idle_va = virtual_avail; 1122 virtual_avail += PAGE_SIZE; 1123 copy_page_src_va = virtual_avail; 1124 virtual_avail += PAGE_SIZE; 1125 copy_page_dst_va = virtual_avail; 1126 virtual_avail += PAGE_SIZE; 1127 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1128 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1129 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1130 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1131 1132 /* Initialize page zero/copy mutexes. */ 1133 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1134 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1135 1136 /* Allocate KVA space for ptbl bufs. */ 1137 ptbl_buf_pool_vabase = virtual_avail; 1138 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1139 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1140 ptbl_buf_pool_vabase, virtual_avail); 1141 1142 /* Calculate corresponding physical addresses for the kernel region. */ 1143 phys_kernelend = kernload + kernsize; 1144 debugf("kernel image and allocated data:\n"); 1145 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1146 debugf(" kernstart = 0x%08x\n", kernstart); 1147 debugf(" kernsize = 0x%08x\n", kernsize); 1148 1149 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1150 panic("mmu_booke_bootstrap: phys_avail too small"); 1151 1152 /* 1153 * Remove kernel physical address range from avail regions list. Page 1154 * align all regions. Non-page aligned memory isn't very interesting 1155 * to us. Also, sort the entries for ascending addresses. 1156 */ 1157 1158 /* Retrieve phys/avail mem regions */ 1159 mem_regions(&physmem_regions, &physmem_regions_sz, 1160 &availmem_regions, &availmem_regions_sz); 1161 sz = 0; 1162 cnt = availmem_regions_sz; 1163 debugf("processing avail regions:\n"); 1164 for (mp = availmem_regions; mp->mr_size; mp++) { 1165 s = mp->mr_start; 1166 e = mp->mr_start + mp->mr_size; 1167 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1168 /* Check whether this region holds all of the kernel. */ 1169 if (s < kernload && e > phys_kernelend) { 1170 availmem_regions[cnt].mr_start = phys_kernelend; 1171 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1172 e = kernload; 1173 } 1174 /* Look whether this regions starts within the kernel. */ 1175 if (s >= kernload && s < phys_kernelend) { 1176 if (e <= phys_kernelend) 1177 goto empty; 1178 s = phys_kernelend; 1179 } 1180 /* Now look whether this region ends within the kernel. */ 1181 if (e > kernload && e <= phys_kernelend) { 1182 if (s >= kernload) 1183 goto empty; 1184 e = kernload; 1185 } 1186 /* Now page align the start and size of the region. */ 1187 s = round_page(s); 1188 e = trunc_page(e); 1189 if (e < s) 1190 e = s; 1191 sz = e - s; 1192 debugf("%09jx-%09jx = %jx\n", 1193 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1194 1195 /* Check whether some memory is left here. */ 1196 if (sz == 0) { 1197 empty: 1198 memmove(mp, mp + 1, 1199 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1200 cnt--; 1201 mp--; 1202 continue; 1203 } 1204 1205 /* Do an insertion sort. */ 1206 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1207 if (s < mp1->mr_start) 1208 break; 1209 if (mp1 < mp) { 1210 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1211 mp1->mr_start = s; 1212 mp1->mr_size = sz; 1213 } else { 1214 mp->mr_start = s; 1215 mp->mr_size = sz; 1216 } 1217 } 1218 availmem_regions_sz = cnt; 1219 1220 /*******************************************************/ 1221 /* Steal physical memory for kernel stack from the end */ 1222 /* of the first avail region */ 1223 /*******************************************************/ 1224 kstack0_sz = kstack_pages * PAGE_SIZE; 1225 kstack0_phys = availmem_regions[0].mr_start + 1226 availmem_regions[0].mr_size; 1227 kstack0_phys -= kstack0_sz; 1228 availmem_regions[0].mr_size -= kstack0_sz; 1229 1230 /*******************************************************/ 1231 /* Fill in phys_avail table, based on availmem_regions */ 1232 /*******************************************************/ 1233 phys_avail_count = 0; 1234 physsz = 0; 1235 hwphyssz = 0; 1236 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1237 1238 debugf("fill in phys_avail:\n"); 1239 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1240 1241 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1242 (uintmax_t)availmem_regions[i].mr_start, 1243 (uintmax_t)availmem_regions[i].mr_start + 1244 availmem_regions[i].mr_size, 1245 (uintmax_t)availmem_regions[i].mr_size); 1246 1247 if (hwphyssz != 0 && 1248 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1249 debugf(" hw.physmem adjust\n"); 1250 if (physsz < hwphyssz) { 1251 phys_avail[j] = availmem_regions[i].mr_start; 1252 phys_avail[j + 1] = 1253 availmem_regions[i].mr_start + 1254 hwphyssz - physsz; 1255 physsz = hwphyssz; 1256 phys_avail_count++; 1257 } 1258 break; 1259 } 1260 1261 phys_avail[j] = availmem_regions[i].mr_start; 1262 phys_avail[j + 1] = availmem_regions[i].mr_start + 1263 availmem_regions[i].mr_size; 1264 phys_avail_count++; 1265 physsz += availmem_regions[i].mr_size; 1266 } 1267 physmem = btoc(physsz); 1268 1269 /* Calculate the last available physical address. */ 1270 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1271 ; 1272 Maxmem = powerpc_btop(phys_avail[i + 1]); 1273 1274 debugf("Maxmem = 0x%08lx\n", Maxmem); 1275 debugf("phys_avail_count = %d\n", phys_avail_count); 1276 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1277 physmem); 1278 1279 /*******************************************************/ 1280 /* Initialize (statically allocated) kernel pmap. */ 1281 /*******************************************************/ 1282 PMAP_LOCK_INIT(kernel_pmap); 1283 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1284 1285 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1286 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1287 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1288 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1289 1290 /* Initialize kernel pdir */ 1291 for (i = 0; i < kernel_ptbls; i++) 1292 kernel_pmap->pm_pdir[kptbl_min + i] = 1293 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1294 1295 for (i = 0; i < MAXCPU; i++) { 1296 kernel_pmap->pm_tid[i] = TID_KERNEL; 1297 1298 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1299 tidbusy[i][TID_KERNEL] = kernel_pmap; 1300 } 1301 1302 /* 1303 * Fill in PTEs covering kernel code and data. They are not required 1304 * for address translation, as this area is covered by static TLB1 1305 * entries, but for pte_vatopa() to work correctly with kernel area 1306 * addresses. 1307 */ 1308 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1309 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1310 pte->rpn = kernload + (va - kernstart); 1311 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1312 PTE_VALID; 1313 } 1314 /* Mark kernel_pmap active on all CPUs */ 1315 CPU_FILL(&kernel_pmap->pm_active); 1316 1317 /* 1318 * Initialize the global pv list lock. 1319 */ 1320 rw_init(&pvh_global_lock, "pmap pv global"); 1321 1322 /*******************************************************/ 1323 /* Final setup */ 1324 /*******************************************************/ 1325 1326 /* Enter kstack0 into kernel map, provide guard page */ 1327 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1328 thread0.td_kstack = kstack0; 1329 thread0.td_kstack_pages = kstack_pages; 1330 1331 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1332 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1333 kstack0_phys, kstack0_phys + kstack0_sz); 1334 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1335 1336 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1337 for (i = 0; i < kstack_pages; i++) { 1338 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1339 kstack0 += PAGE_SIZE; 1340 kstack0_phys += PAGE_SIZE; 1341 } 1342 1343 pmap_bootstrapped = 1; 1344 1345 debugf("virtual_avail = %08x\n", virtual_avail); 1346 debugf("virtual_end = %08x\n", virtual_end); 1347 1348 debugf("mmu_booke_bootstrap: exit\n"); 1349 } 1350 1351 #ifdef SMP 1352 void 1353 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1354 { 1355 int i; 1356 1357 /* 1358 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1359 * have the snapshot of its contents in the s/w tlb1[] table, so use 1360 * these values directly to (re)program AP's TLB1 hardware. 1361 */ 1362 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1363 /* Skip invalid entries */ 1364 if (!(tlb1[i].mas1 & MAS1_VALID)) 1365 continue; 1366 1367 tlb1_write_entry(i); 1368 } 1369 1370 set_mas4_defaults(); 1371 } 1372 #endif 1373 1374 static void 1375 booke_pmap_init_qpages(void) 1376 { 1377 struct pcpu *pc; 1378 int i; 1379 1380 CPU_FOREACH(i) { 1381 pc = pcpu_find(i); 1382 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1383 if (pc->pc_qmap_addr == 0) 1384 panic("pmap_init_qpages: unable to allocate KVA"); 1385 } 1386 } 1387 1388 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1389 1390 /* 1391 * Get the physical page address for the given pmap/virtual address. 1392 */ 1393 static vm_paddr_t 1394 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1395 { 1396 vm_paddr_t pa; 1397 1398 PMAP_LOCK(pmap); 1399 pa = pte_vatopa(mmu, pmap, va); 1400 PMAP_UNLOCK(pmap); 1401 1402 return (pa); 1403 } 1404 1405 /* 1406 * Extract the physical page address associated with the given 1407 * kernel virtual address. 1408 */ 1409 static vm_paddr_t 1410 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1411 { 1412 int i; 1413 1414 /* Check TLB1 mappings */ 1415 for (i = 0; i < tlb1_idx; i++) { 1416 if (!(tlb1[i].mas1 & MAS1_VALID)) 1417 continue; 1418 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1419 return (tlb1[i].phys + (va - tlb1[i].virt)); 1420 } 1421 1422 return (pte_vatopa(mmu, kernel_pmap, va)); 1423 } 1424 1425 /* 1426 * Initialize the pmap module. 1427 * Called by vm_init, to initialize any structures that the pmap 1428 * system needs to map virtual memory. 1429 */ 1430 static void 1431 mmu_booke_init(mmu_t mmu) 1432 { 1433 int shpgperproc = PMAP_SHPGPERPROC; 1434 1435 /* 1436 * Initialize the address space (zone) for the pv entries. Set a 1437 * high water mark so that the system can recover from excessive 1438 * numbers of pv entries. 1439 */ 1440 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1441 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1442 1443 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1444 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1445 1446 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1447 pv_entry_high_water = 9 * (pv_entry_max / 10); 1448 1449 uma_zone_reserve_kva(pvzone, pv_entry_max); 1450 1451 /* Pre-fill pvzone with initial number of pv entries. */ 1452 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1453 1454 /* Initialize ptbl allocation. */ 1455 ptbl_init(); 1456 } 1457 1458 /* 1459 * Map a list of wired pages into kernel virtual address space. This is 1460 * intended for temporary mappings which do not need page modification or 1461 * references recorded. Existing mappings in the region are overwritten. 1462 */ 1463 static void 1464 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1465 { 1466 vm_offset_t va; 1467 1468 va = sva; 1469 while (count-- > 0) { 1470 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1471 va += PAGE_SIZE; 1472 m++; 1473 } 1474 } 1475 1476 /* 1477 * Remove page mappings from kernel virtual address space. Intended for 1478 * temporary mappings entered by mmu_booke_qenter. 1479 */ 1480 static void 1481 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1482 { 1483 vm_offset_t va; 1484 1485 va = sva; 1486 while (count-- > 0) { 1487 mmu_booke_kremove(mmu, va); 1488 va += PAGE_SIZE; 1489 } 1490 } 1491 1492 /* 1493 * Map a wired page into kernel virtual address space. 1494 */ 1495 static void 1496 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1497 { 1498 1499 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1500 } 1501 1502 static void 1503 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1504 { 1505 unsigned int pdir_idx = PDIR_IDX(va); 1506 unsigned int ptbl_idx = PTBL_IDX(va); 1507 uint32_t flags; 1508 pte_t *pte; 1509 1510 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1511 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1512 1513 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1514 flags |= tlb_calc_wimg(pa, ma); 1515 1516 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1517 1518 mtx_lock_spin(&tlbivax_mutex); 1519 tlb_miss_lock(); 1520 1521 if (PTE_ISVALID(pte)) { 1522 1523 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1524 1525 /* Flush entry from TLB0 */ 1526 tlb0_flush_entry(va); 1527 } 1528 1529 pte->rpn = PTE_RPN_FROM_PA(pa); 1530 pte->flags = flags; 1531 1532 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1533 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1534 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1535 1536 /* Flush the real memory from the instruction cache. */ 1537 if ((flags & (PTE_I | PTE_G)) == 0) { 1538 __syncicache((void *)va, PAGE_SIZE); 1539 } 1540 1541 tlb_miss_unlock(); 1542 mtx_unlock_spin(&tlbivax_mutex); 1543 } 1544 1545 /* 1546 * Remove a page from kernel page table. 1547 */ 1548 static void 1549 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1550 { 1551 unsigned int pdir_idx = PDIR_IDX(va); 1552 unsigned int ptbl_idx = PTBL_IDX(va); 1553 pte_t *pte; 1554 1555 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1556 1557 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1558 (va <= VM_MAX_KERNEL_ADDRESS)), 1559 ("mmu_booke_kremove: invalid va")); 1560 1561 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1562 1563 if (!PTE_ISVALID(pte)) { 1564 1565 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1566 1567 return; 1568 } 1569 1570 mtx_lock_spin(&tlbivax_mutex); 1571 tlb_miss_lock(); 1572 1573 /* Invalidate entry in TLB0, update PTE. */ 1574 tlb0_flush_entry(va); 1575 pte->flags = 0; 1576 pte->rpn = 0; 1577 1578 tlb_miss_unlock(); 1579 mtx_unlock_spin(&tlbivax_mutex); 1580 } 1581 1582 /* 1583 * Initialize pmap associated with process 0. 1584 */ 1585 static void 1586 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1587 { 1588 1589 PMAP_LOCK_INIT(pmap); 1590 mmu_booke_pinit(mmu, pmap); 1591 PCPU_SET(curpmap, pmap); 1592 } 1593 1594 /* 1595 * Initialize a preallocated and zeroed pmap structure, 1596 * such as one in a vmspace structure. 1597 */ 1598 static void 1599 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1600 { 1601 int i; 1602 1603 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1604 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1605 1606 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1607 1608 for (i = 0; i < MAXCPU; i++) 1609 pmap->pm_tid[i] = TID_NONE; 1610 CPU_ZERO(&kernel_pmap->pm_active); 1611 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1612 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1613 TAILQ_INIT(&pmap->pm_ptbl_list); 1614 } 1615 1616 /* 1617 * Release any resources held by the given physical map. 1618 * Called when a pmap initialized by mmu_booke_pinit is being released. 1619 * Should only be called if the map contains no valid mappings. 1620 */ 1621 static void 1622 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1623 { 1624 1625 KASSERT(pmap->pm_stats.resident_count == 0, 1626 ("pmap_release: pmap resident count %ld != 0", 1627 pmap->pm_stats.resident_count)); 1628 } 1629 1630 /* 1631 * Insert the given physical page at the specified virtual address in the 1632 * target physical map with the protection requested. If specified the page 1633 * will be wired down. 1634 */ 1635 static int 1636 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1637 vm_prot_t prot, u_int flags, int8_t psind) 1638 { 1639 int error; 1640 1641 rw_wlock(&pvh_global_lock); 1642 PMAP_LOCK(pmap); 1643 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1644 rw_wunlock(&pvh_global_lock); 1645 PMAP_UNLOCK(pmap); 1646 return (error); 1647 } 1648 1649 static int 1650 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1651 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1652 { 1653 pte_t *pte; 1654 vm_paddr_t pa; 1655 uint32_t flags; 1656 int error, su, sync; 1657 1658 pa = VM_PAGE_TO_PHYS(m); 1659 su = (pmap == kernel_pmap); 1660 sync = 0; 1661 1662 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1663 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1664 // (u_int32_t)pmap, su, pmap->pm_tid, 1665 // (u_int32_t)m, va, pa, prot, flags); 1666 1667 if (su) { 1668 KASSERT(((va >= virtual_avail) && 1669 (va <= VM_MAX_KERNEL_ADDRESS)), 1670 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1671 } else { 1672 KASSERT((va <= VM_MAXUSER_ADDRESS), 1673 ("mmu_booke_enter_locked: user pmap, non user va")); 1674 } 1675 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1676 VM_OBJECT_ASSERT_LOCKED(m->object); 1677 1678 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1679 1680 /* 1681 * If there is an existing mapping, and the physical address has not 1682 * changed, must be protection or wiring change. 1683 */ 1684 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1685 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1686 1687 /* 1688 * Before actually updating pte->flags we calculate and 1689 * prepare its new value in a helper var. 1690 */ 1691 flags = pte->flags; 1692 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1693 1694 /* Wiring change, just update stats. */ 1695 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1696 if (!PTE_ISWIRED(pte)) { 1697 flags |= PTE_WIRED; 1698 pmap->pm_stats.wired_count++; 1699 } 1700 } else { 1701 if (PTE_ISWIRED(pte)) { 1702 flags &= ~PTE_WIRED; 1703 pmap->pm_stats.wired_count--; 1704 } 1705 } 1706 1707 if (prot & VM_PROT_WRITE) { 1708 /* Add write permissions. */ 1709 flags |= PTE_SW; 1710 if (!su) 1711 flags |= PTE_UW; 1712 1713 if ((flags & PTE_MANAGED) != 0) 1714 vm_page_aflag_set(m, PGA_WRITEABLE); 1715 } else { 1716 /* Handle modified pages, sense modify status. */ 1717 1718 /* 1719 * The PTE_MODIFIED flag could be set by underlying 1720 * TLB misses since we last read it (above), possibly 1721 * other CPUs could update it so we check in the PTE 1722 * directly rather than rely on that saved local flags 1723 * copy. 1724 */ 1725 if (PTE_ISMODIFIED(pte)) 1726 vm_page_dirty(m); 1727 } 1728 1729 if (prot & VM_PROT_EXECUTE) { 1730 flags |= PTE_SX; 1731 if (!su) 1732 flags |= PTE_UX; 1733 1734 /* 1735 * Check existing flags for execute permissions: if we 1736 * are turning execute permissions on, icache should 1737 * be flushed. 1738 */ 1739 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1740 sync++; 1741 } 1742 1743 flags &= ~PTE_REFERENCED; 1744 1745 /* 1746 * The new flags value is all calculated -- only now actually 1747 * update the PTE. 1748 */ 1749 mtx_lock_spin(&tlbivax_mutex); 1750 tlb_miss_lock(); 1751 1752 tlb0_flush_entry(va); 1753 pte->flags = flags; 1754 1755 tlb_miss_unlock(); 1756 mtx_unlock_spin(&tlbivax_mutex); 1757 1758 } else { 1759 /* 1760 * If there is an existing mapping, but it's for a different 1761 * physical address, pte_enter() will delete the old mapping. 1762 */ 1763 //if ((pte != NULL) && PTE_ISVALID(pte)) 1764 // debugf("mmu_booke_enter_locked: replace\n"); 1765 //else 1766 // debugf("mmu_booke_enter_locked: new\n"); 1767 1768 /* Now set up the flags and install the new mapping. */ 1769 flags = (PTE_SR | PTE_VALID); 1770 flags |= PTE_M; 1771 1772 if (!su) 1773 flags |= PTE_UR; 1774 1775 if (prot & VM_PROT_WRITE) { 1776 flags |= PTE_SW; 1777 if (!su) 1778 flags |= PTE_UW; 1779 1780 if ((m->oflags & VPO_UNMANAGED) == 0) 1781 vm_page_aflag_set(m, PGA_WRITEABLE); 1782 } 1783 1784 if (prot & VM_PROT_EXECUTE) { 1785 flags |= PTE_SX; 1786 if (!su) 1787 flags |= PTE_UX; 1788 } 1789 1790 /* If its wired update stats. */ 1791 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1792 flags |= PTE_WIRED; 1793 1794 error = pte_enter(mmu, pmap, m, va, flags, 1795 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1796 if (error != 0) 1797 return (KERN_RESOURCE_SHORTAGE); 1798 1799 if ((flags & PMAP_ENTER_WIRED) != 0) 1800 pmap->pm_stats.wired_count++; 1801 1802 /* Flush the real memory from the instruction cache. */ 1803 if (prot & VM_PROT_EXECUTE) 1804 sync++; 1805 } 1806 1807 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1808 __syncicache((void *)va, PAGE_SIZE); 1809 sync = 0; 1810 } 1811 1812 return (KERN_SUCCESS); 1813 } 1814 1815 /* 1816 * Maps a sequence of resident pages belonging to the same object. 1817 * The sequence begins with the given page m_start. This page is 1818 * mapped at the given virtual address start. Each subsequent page is 1819 * mapped at a virtual address that is offset from start by the same 1820 * amount as the page is offset from m_start within the object. The 1821 * last page in the sequence is the page with the largest offset from 1822 * m_start that can be mapped at a virtual address less than the given 1823 * virtual address end. Not every virtual page between start and end 1824 * is mapped; only those for which a resident page exists with the 1825 * corresponding offset from m_start are mapped. 1826 */ 1827 static void 1828 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1829 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1830 { 1831 vm_page_t m; 1832 vm_pindex_t diff, psize; 1833 1834 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1835 1836 psize = atop(end - start); 1837 m = m_start; 1838 rw_wlock(&pvh_global_lock); 1839 PMAP_LOCK(pmap); 1840 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1841 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1842 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1843 PMAP_ENTER_NOSLEEP, 0); 1844 m = TAILQ_NEXT(m, listq); 1845 } 1846 rw_wunlock(&pvh_global_lock); 1847 PMAP_UNLOCK(pmap); 1848 } 1849 1850 static void 1851 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1852 vm_prot_t prot) 1853 { 1854 1855 rw_wlock(&pvh_global_lock); 1856 PMAP_LOCK(pmap); 1857 mmu_booke_enter_locked(mmu, pmap, va, m, 1858 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1859 0); 1860 rw_wunlock(&pvh_global_lock); 1861 PMAP_UNLOCK(pmap); 1862 } 1863 1864 /* 1865 * Remove the given range of addresses from the specified map. 1866 * 1867 * It is assumed that the start and end are properly rounded to the page size. 1868 */ 1869 static void 1870 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1871 { 1872 pte_t *pte; 1873 uint8_t hold_flag; 1874 1875 int su = (pmap == kernel_pmap); 1876 1877 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1878 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1879 1880 if (su) { 1881 KASSERT(((va >= virtual_avail) && 1882 (va <= VM_MAX_KERNEL_ADDRESS)), 1883 ("mmu_booke_remove: kernel pmap, non kernel va")); 1884 } else { 1885 KASSERT((va <= VM_MAXUSER_ADDRESS), 1886 ("mmu_booke_remove: user pmap, non user va")); 1887 } 1888 1889 if (PMAP_REMOVE_DONE(pmap)) { 1890 //debugf("mmu_booke_remove: e (empty)\n"); 1891 return; 1892 } 1893 1894 hold_flag = PTBL_HOLD_FLAG(pmap); 1895 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1896 1897 rw_wlock(&pvh_global_lock); 1898 PMAP_LOCK(pmap); 1899 for (; va < endva; va += PAGE_SIZE) { 1900 pte = pte_find(mmu, pmap, va); 1901 if ((pte != NULL) && PTE_ISVALID(pte)) 1902 pte_remove(mmu, pmap, va, hold_flag); 1903 } 1904 PMAP_UNLOCK(pmap); 1905 rw_wunlock(&pvh_global_lock); 1906 1907 //debugf("mmu_booke_remove: e\n"); 1908 } 1909 1910 /* 1911 * Remove physical page from all pmaps in which it resides. 1912 */ 1913 static void 1914 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1915 { 1916 pv_entry_t pv, pvn; 1917 uint8_t hold_flag; 1918 1919 rw_wlock(&pvh_global_lock); 1920 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1921 pvn = TAILQ_NEXT(pv, pv_link); 1922 1923 PMAP_LOCK(pv->pv_pmap); 1924 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1925 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1926 PMAP_UNLOCK(pv->pv_pmap); 1927 } 1928 vm_page_aflag_clear(m, PGA_WRITEABLE); 1929 rw_wunlock(&pvh_global_lock); 1930 } 1931 1932 /* 1933 * Map a range of physical addresses into kernel virtual address space. 1934 */ 1935 static vm_offset_t 1936 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1937 vm_paddr_t pa_end, int prot) 1938 { 1939 vm_offset_t sva = *virt; 1940 vm_offset_t va = sva; 1941 1942 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1943 // sva, pa_start, pa_end); 1944 1945 while (pa_start < pa_end) { 1946 mmu_booke_kenter(mmu, va, pa_start); 1947 va += PAGE_SIZE; 1948 pa_start += PAGE_SIZE; 1949 } 1950 *virt = va; 1951 1952 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1953 return (sva); 1954 } 1955 1956 /* 1957 * The pmap must be activated before it's address space can be accessed in any 1958 * way. 1959 */ 1960 static void 1961 mmu_booke_activate(mmu_t mmu, struct thread *td) 1962 { 1963 pmap_t pmap; 1964 u_int cpuid; 1965 1966 pmap = &td->td_proc->p_vmspace->vm_pmap; 1967 1968 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1969 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1970 1971 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1972 1973 sched_pin(); 1974 1975 cpuid = PCPU_GET(cpuid); 1976 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1977 PCPU_SET(curpmap, pmap); 1978 1979 if (pmap->pm_tid[cpuid] == TID_NONE) 1980 tid_alloc(pmap); 1981 1982 /* Load PID0 register with pmap tid value. */ 1983 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1984 __asm __volatile("isync"); 1985 1986 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1987 1988 sched_unpin(); 1989 1990 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1991 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1992 } 1993 1994 /* 1995 * Deactivate the specified process's address space. 1996 */ 1997 static void 1998 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1999 { 2000 pmap_t pmap; 2001 2002 pmap = &td->td_proc->p_vmspace->vm_pmap; 2003 2004 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2005 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2006 2007 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2008 2009 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2010 PCPU_SET(curpmap, NULL); 2011 } 2012 2013 /* 2014 * Copy the range specified by src_addr/len 2015 * from the source map to the range dst_addr/len 2016 * in the destination map. 2017 * 2018 * This routine is only advisory and need not do anything. 2019 */ 2020 static void 2021 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2022 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2023 { 2024 2025 } 2026 2027 /* 2028 * Set the physical protection on the specified range of this map as requested. 2029 */ 2030 static void 2031 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2032 vm_prot_t prot) 2033 { 2034 vm_offset_t va; 2035 vm_page_t m; 2036 pte_t *pte; 2037 2038 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2039 mmu_booke_remove(mmu, pmap, sva, eva); 2040 return; 2041 } 2042 2043 if (prot & VM_PROT_WRITE) 2044 return; 2045 2046 PMAP_LOCK(pmap); 2047 for (va = sva; va < eva; va += PAGE_SIZE) { 2048 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2049 if (PTE_ISVALID(pte)) { 2050 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2051 2052 mtx_lock_spin(&tlbivax_mutex); 2053 tlb_miss_lock(); 2054 2055 /* Handle modified pages. */ 2056 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2057 vm_page_dirty(m); 2058 2059 tlb0_flush_entry(va); 2060 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2061 2062 tlb_miss_unlock(); 2063 mtx_unlock_spin(&tlbivax_mutex); 2064 } 2065 } 2066 } 2067 PMAP_UNLOCK(pmap); 2068 } 2069 2070 /* 2071 * Clear the write and modified bits in each of the given page's mappings. 2072 */ 2073 static void 2074 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2075 { 2076 pv_entry_t pv; 2077 pte_t *pte; 2078 2079 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2080 ("mmu_booke_remove_write: page %p is not managed", m)); 2081 2082 /* 2083 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2084 * set by another thread while the object is locked. Thus, 2085 * if PGA_WRITEABLE is clear, no page table entries need updating. 2086 */ 2087 VM_OBJECT_ASSERT_WLOCKED(m->object); 2088 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2089 return; 2090 rw_wlock(&pvh_global_lock); 2091 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2092 PMAP_LOCK(pv->pv_pmap); 2093 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2094 if (PTE_ISVALID(pte)) { 2095 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2096 2097 mtx_lock_spin(&tlbivax_mutex); 2098 tlb_miss_lock(); 2099 2100 /* Handle modified pages. */ 2101 if (PTE_ISMODIFIED(pte)) 2102 vm_page_dirty(m); 2103 2104 /* Flush mapping from TLB0. */ 2105 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2106 2107 tlb_miss_unlock(); 2108 mtx_unlock_spin(&tlbivax_mutex); 2109 } 2110 } 2111 PMAP_UNLOCK(pv->pv_pmap); 2112 } 2113 vm_page_aflag_clear(m, PGA_WRITEABLE); 2114 rw_wunlock(&pvh_global_lock); 2115 } 2116 2117 static void 2118 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2119 { 2120 pte_t *pte; 2121 pmap_t pmap; 2122 vm_page_t m; 2123 vm_offset_t addr; 2124 vm_paddr_t pa = 0; 2125 int active, valid; 2126 2127 va = trunc_page(va); 2128 sz = round_page(sz); 2129 2130 rw_wlock(&pvh_global_lock); 2131 pmap = PCPU_GET(curpmap); 2132 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2133 while (sz > 0) { 2134 PMAP_LOCK(pm); 2135 pte = pte_find(mmu, pm, va); 2136 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2137 if (valid) 2138 pa = PTE_PA(pte); 2139 PMAP_UNLOCK(pm); 2140 if (valid) { 2141 if (!active) { 2142 /* Create a mapping in the active pmap. */ 2143 addr = 0; 2144 m = PHYS_TO_VM_PAGE(pa); 2145 PMAP_LOCK(pmap); 2146 pte_enter(mmu, pmap, m, addr, 2147 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2148 __syncicache((void *)addr, PAGE_SIZE); 2149 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2150 PMAP_UNLOCK(pmap); 2151 } else 2152 __syncicache((void *)va, PAGE_SIZE); 2153 } 2154 va += PAGE_SIZE; 2155 sz -= PAGE_SIZE; 2156 } 2157 rw_wunlock(&pvh_global_lock); 2158 } 2159 2160 /* 2161 * Atomically extract and hold the physical page with the given 2162 * pmap and virtual address pair if that mapping permits the given 2163 * protection. 2164 */ 2165 static vm_page_t 2166 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2167 vm_prot_t prot) 2168 { 2169 pte_t *pte; 2170 vm_page_t m; 2171 uint32_t pte_wbit; 2172 vm_paddr_t pa; 2173 2174 m = NULL; 2175 pa = 0; 2176 PMAP_LOCK(pmap); 2177 retry: 2178 pte = pte_find(mmu, pmap, va); 2179 if ((pte != NULL) && PTE_ISVALID(pte)) { 2180 if (pmap == kernel_pmap) 2181 pte_wbit = PTE_SW; 2182 else 2183 pte_wbit = PTE_UW; 2184 2185 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2186 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2187 goto retry; 2188 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2189 vm_page_hold(m); 2190 } 2191 } 2192 2193 PA_UNLOCK_COND(pa); 2194 PMAP_UNLOCK(pmap); 2195 return (m); 2196 } 2197 2198 /* 2199 * Initialize a vm_page's machine-dependent fields. 2200 */ 2201 static void 2202 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2203 { 2204 2205 TAILQ_INIT(&m->md.pv_list); 2206 } 2207 2208 /* 2209 * mmu_booke_zero_page_area zeros the specified hardware page by 2210 * mapping it into virtual memory and using bzero to clear 2211 * its contents. 2212 * 2213 * off and size must reside within a single page. 2214 */ 2215 static void 2216 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2217 { 2218 vm_offset_t va; 2219 2220 /* XXX KASSERT off and size are within a single page? */ 2221 2222 mtx_lock(&zero_page_mutex); 2223 va = zero_page_va; 2224 2225 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2226 bzero((caddr_t)va + off, size); 2227 mmu_booke_kremove(mmu, va); 2228 2229 mtx_unlock(&zero_page_mutex); 2230 } 2231 2232 /* 2233 * mmu_booke_zero_page zeros the specified hardware page. 2234 */ 2235 static void 2236 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2237 { 2238 vm_offset_t off, va; 2239 2240 mtx_lock(&zero_page_mutex); 2241 va = zero_page_va; 2242 2243 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2244 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2245 __asm __volatile("dcbzl 0,%0" :: "r"(va + off)); 2246 mmu_booke_kremove(mmu, va); 2247 2248 mtx_unlock(&zero_page_mutex); 2249 } 2250 2251 /* 2252 * mmu_booke_copy_page copies the specified (machine independent) page by 2253 * mapping the page into virtual memory and using memcopy to copy the page, 2254 * one machine dependent page at a time. 2255 */ 2256 static void 2257 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2258 { 2259 vm_offset_t sva, dva; 2260 2261 sva = copy_page_src_va; 2262 dva = copy_page_dst_va; 2263 2264 mtx_lock(©_page_mutex); 2265 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2266 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2267 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2268 mmu_booke_kremove(mmu, dva); 2269 mmu_booke_kremove(mmu, sva); 2270 mtx_unlock(©_page_mutex); 2271 } 2272 2273 static inline void 2274 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2275 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2276 { 2277 void *a_cp, *b_cp; 2278 vm_offset_t a_pg_offset, b_pg_offset; 2279 int cnt; 2280 2281 mtx_lock(©_page_mutex); 2282 while (xfersize > 0) { 2283 a_pg_offset = a_offset & PAGE_MASK; 2284 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2285 mmu_booke_kenter(mmu, copy_page_src_va, 2286 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2287 a_cp = (char *)copy_page_src_va + a_pg_offset; 2288 b_pg_offset = b_offset & PAGE_MASK; 2289 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2290 mmu_booke_kenter(mmu, copy_page_dst_va, 2291 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2292 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2293 bcopy(a_cp, b_cp, cnt); 2294 mmu_booke_kremove(mmu, copy_page_dst_va); 2295 mmu_booke_kremove(mmu, copy_page_src_va); 2296 a_offset += cnt; 2297 b_offset += cnt; 2298 xfersize -= cnt; 2299 } 2300 mtx_unlock(©_page_mutex); 2301 } 2302 2303 /* 2304 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2305 * into virtual memory and using bzero to clear its contents. This is intended 2306 * to be called from the vm_pagezero process only and outside of Giant. No 2307 * lock is required. 2308 */ 2309 static void 2310 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2311 { 2312 vm_offset_t va; 2313 2314 va = zero_page_idle_va; 2315 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2316 bzero((caddr_t)va, PAGE_SIZE); 2317 mmu_booke_kremove(mmu, va); 2318 } 2319 2320 static vm_offset_t 2321 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2322 { 2323 vm_paddr_t paddr; 2324 vm_offset_t qaddr; 2325 uint32_t flags; 2326 pte_t *pte; 2327 2328 paddr = VM_PAGE_TO_PHYS(m); 2329 2330 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2331 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)); 2332 2333 critical_enter(); 2334 qaddr = PCPU_GET(qmap_addr); 2335 2336 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(qaddr)][PTBL_IDX(qaddr)]); 2337 2338 KASSERT(pte->flags == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2339 2340 /* 2341 * XXX: tlbivax is broadcast to other cores, but qaddr should 2342 * not be present in other TLBs. Is there a better instruction 2343 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2344 */ 2345 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2346 __asm __volatile("isync; msync"); 2347 2348 pte->rpn = paddr & ~PTE_PA_MASK; 2349 pte->flags = flags; 2350 2351 /* Flush the real memory from the instruction cache. */ 2352 if ((flags & (PTE_I | PTE_G)) == 0) 2353 __syncicache((void *)qaddr, PAGE_SIZE); 2354 2355 return (qaddr); 2356 } 2357 2358 static void 2359 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2360 { 2361 pte_t *pte; 2362 2363 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(addr)][PTBL_IDX(addr)]); 2364 2365 KASSERT(PCPU_GET(qmap_addr) == addr, 2366 ("mmu_booke_quick_remove_page: invalid address")); 2367 KASSERT(pte->flags != 0, 2368 ("mmu_booke_quick_remove_page: PTE not in use")); 2369 2370 pte->flags = 0; 2371 pte->rpn = 0; 2372 critical_exit(); 2373 } 2374 2375 /* 2376 * Return whether or not the specified physical page was modified 2377 * in any of physical maps. 2378 */ 2379 static boolean_t 2380 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2381 { 2382 pte_t *pte; 2383 pv_entry_t pv; 2384 boolean_t rv; 2385 2386 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2387 ("mmu_booke_is_modified: page %p is not managed", m)); 2388 rv = FALSE; 2389 2390 /* 2391 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2392 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2393 * is clear, no PTEs can be modified. 2394 */ 2395 VM_OBJECT_ASSERT_WLOCKED(m->object); 2396 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2397 return (rv); 2398 rw_wlock(&pvh_global_lock); 2399 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2400 PMAP_LOCK(pv->pv_pmap); 2401 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2402 PTE_ISVALID(pte)) { 2403 if (PTE_ISMODIFIED(pte)) 2404 rv = TRUE; 2405 } 2406 PMAP_UNLOCK(pv->pv_pmap); 2407 if (rv) 2408 break; 2409 } 2410 rw_wunlock(&pvh_global_lock); 2411 return (rv); 2412 } 2413 2414 /* 2415 * Return whether or not the specified virtual address is eligible 2416 * for prefault. 2417 */ 2418 static boolean_t 2419 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2420 { 2421 2422 return (FALSE); 2423 } 2424 2425 /* 2426 * Return whether or not the specified physical page was referenced 2427 * in any physical maps. 2428 */ 2429 static boolean_t 2430 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2431 { 2432 pte_t *pte; 2433 pv_entry_t pv; 2434 boolean_t rv; 2435 2436 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2437 ("mmu_booke_is_referenced: page %p is not managed", m)); 2438 rv = FALSE; 2439 rw_wlock(&pvh_global_lock); 2440 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2441 PMAP_LOCK(pv->pv_pmap); 2442 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2443 PTE_ISVALID(pte)) { 2444 if (PTE_ISREFERENCED(pte)) 2445 rv = TRUE; 2446 } 2447 PMAP_UNLOCK(pv->pv_pmap); 2448 if (rv) 2449 break; 2450 } 2451 rw_wunlock(&pvh_global_lock); 2452 return (rv); 2453 } 2454 2455 /* 2456 * Clear the modify bits on the specified physical page. 2457 */ 2458 static void 2459 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2460 { 2461 pte_t *pte; 2462 pv_entry_t pv; 2463 2464 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2465 ("mmu_booke_clear_modify: page %p is not managed", m)); 2466 VM_OBJECT_ASSERT_WLOCKED(m->object); 2467 KASSERT(!vm_page_xbusied(m), 2468 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2469 2470 /* 2471 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2472 * If the object containing the page is locked and the page is not 2473 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2474 */ 2475 if ((m->aflags & PGA_WRITEABLE) == 0) 2476 return; 2477 rw_wlock(&pvh_global_lock); 2478 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2479 PMAP_LOCK(pv->pv_pmap); 2480 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2481 PTE_ISVALID(pte)) { 2482 mtx_lock_spin(&tlbivax_mutex); 2483 tlb_miss_lock(); 2484 2485 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2486 tlb0_flush_entry(pv->pv_va); 2487 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2488 PTE_REFERENCED); 2489 } 2490 2491 tlb_miss_unlock(); 2492 mtx_unlock_spin(&tlbivax_mutex); 2493 } 2494 PMAP_UNLOCK(pv->pv_pmap); 2495 } 2496 rw_wunlock(&pvh_global_lock); 2497 } 2498 2499 /* 2500 * Return a count of reference bits for a page, clearing those bits. 2501 * It is not necessary for every reference bit to be cleared, but it 2502 * is necessary that 0 only be returned when there are truly no 2503 * reference bits set. 2504 * 2505 * XXX: The exact number of bits to check and clear is a matter that 2506 * should be tested and standardized at some point in the future for 2507 * optimal aging of shared pages. 2508 */ 2509 static int 2510 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2511 { 2512 pte_t *pte; 2513 pv_entry_t pv; 2514 int count; 2515 2516 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2517 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2518 count = 0; 2519 rw_wlock(&pvh_global_lock); 2520 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2521 PMAP_LOCK(pv->pv_pmap); 2522 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2523 PTE_ISVALID(pte)) { 2524 if (PTE_ISREFERENCED(pte)) { 2525 mtx_lock_spin(&tlbivax_mutex); 2526 tlb_miss_lock(); 2527 2528 tlb0_flush_entry(pv->pv_va); 2529 pte->flags &= ~PTE_REFERENCED; 2530 2531 tlb_miss_unlock(); 2532 mtx_unlock_spin(&tlbivax_mutex); 2533 2534 if (++count > 4) { 2535 PMAP_UNLOCK(pv->pv_pmap); 2536 break; 2537 } 2538 } 2539 } 2540 PMAP_UNLOCK(pv->pv_pmap); 2541 } 2542 rw_wunlock(&pvh_global_lock); 2543 return (count); 2544 } 2545 2546 /* 2547 * Clear the wired attribute from the mappings for the specified range of 2548 * addresses in the given pmap. Every valid mapping within that range must 2549 * have the wired attribute set. In contrast, invalid mappings cannot have 2550 * the wired attribute set, so they are ignored. 2551 * 2552 * The wired attribute of the page table entry is not a hardware feature, so 2553 * there is no need to invalidate any TLB entries. 2554 */ 2555 static void 2556 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2557 { 2558 vm_offset_t va; 2559 pte_t *pte; 2560 2561 PMAP_LOCK(pmap); 2562 for (va = sva; va < eva; va += PAGE_SIZE) { 2563 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2564 PTE_ISVALID(pte)) { 2565 if (!PTE_ISWIRED(pte)) 2566 panic("mmu_booke_unwire: pte %p isn't wired", 2567 pte); 2568 pte->flags &= ~PTE_WIRED; 2569 pmap->pm_stats.wired_count--; 2570 } 2571 } 2572 PMAP_UNLOCK(pmap); 2573 2574 } 2575 2576 /* 2577 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2578 * page. This count may be changed upwards or downwards in the future; it is 2579 * only necessary that true be returned for a small subset of pmaps for proper 2580 * page aging. 2581 */ 2582 static boolean_t 2583 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2584 { 2585 pv_entry_t pv; 2586 int loops; 2587 boolean_t rv; 2588 2589 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2590 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2591 loops = 0; 2592 rv = FALSE; 2593 rw_wlock(&pvh_global_lock); 2594 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2595 if (pv->pv_pmap == pmap) { 2596 rv = TRUE; 2597 break; 2598 } 2599 if (++loops >= 16) 2600 break; 2601 } 2602 rw_wunlock(&pvh_global_lock); 2603 return (rv); 2604 } 2605 2606 /* 2607 * Return the number of managed mappings to the given physical page that are 2608 * wired. 2609 */ 2610 static int 2611 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2612 { 2613 pv_entry_t pv; 2614 pte_t *pte; 2615 int count = 0; 2616 2617 if ((m->oflags & VPO_UNMANAGED) != 0) 2618 return (count); 2619 rw_wlock(&pvh_global_lock); 2620 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2621 PMAP_LOCK(pv->pv_pmap); 2622 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2623 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2624 count++; 2625 PMAP_UNLOCK(pv->pv_pmap); 2626 } 2627 rw_wunlock(&pvh_global_lock); 2628 return (count); 2629 } 2630 2631 static int 2632 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2633 { 2634 int i; 2635 vm_offset_t va; 2636 2637 /* 2638 * This currently does not work for entries that 2639 * overlap TLB1 entries. 2640 */ 2641 for (i = 0; i < tlb1_idx; i ++) { 2642 if (tlb1_iomapped(i, pa, size, &va) == 0) 2643 return (0); 2644 } 2645 2646 return (EFAULT); 2647 } 2648 2649 void 2650 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2651 { 2652 vm_paddr_t ppa; 2653 vm_offset_t ofs; 2654 vm_size_t gran; 2655 2656 /* Minidumps are based on virtual memory addresses. */ 2657 if (do_minidump) { 2658 *va = (void *)(vm_offset_t)pa; 2659 return; 2660 } 2661 2662 /* Raw physical memory dumps don't have a virtual address. */ 2663 /* We always map a 256MB page at 256M. */ 2664 gran = 256 * 1024 * 1024; 2665 ppa = pa & ~(gran - 1); 2666 ofs = pa - ppa; 2667 *va = (void *)gran; 2668 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2669 2670 if (sz > (gran - ofs)) 2671 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2672 _TLB_ENTRY_IO); 2673 } 2674 2675 void 2676 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2677 { 2678 vm_paddr_t ppa; 2679 vm_offset_t ofs; 2680 vm_size_t gran; 2681 2682 /* Minidumps are based on virtual memory addresses. */ 2683 /* Nothing to do... */ 2684 if (do_minidump) 2685 return; 2686 2687 /* Raw physical memory dumps don't have a virtual address. */ 2688 tlb1_idx--; 2689 tlb1[tlb1_idx].mas1 = 0; 2690 tlb1[tlb1_idx].mas2 = 0; 2691 tlb1[tlb1_idx].mas3 = 0; 2692 tlb1_write_entry(tlb1_idx); 2693 2694 gran = 256 * 1024 * 1024; 2695 ppa = pa & ~(gran - 1); 2696 ofs = pa - ppa; 2697 if (sz > (gran - ofs)) { 2698 tlb1_idx--; 2699 tlb1[tlb1_idx].mas1 = 0; 2700 tlb1[tlb1_idx].mas2 = 0; 2701 tlb1[tlb1_idx].mas3 = 0; 2702 tlb1_write_entry(tlb1_idx); 2703 } 2704 } 2705 2706 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2707 2708 void 2709 mmu_booke_scan_init(mmu_t mmu) 2710 { 2711 vm_offset_t va; 2712 pte_t *pte; 2713 int i; 2714 2715 if (!do_minidump) { 2716 /* Initialize phys. segments for dumpsys(). */ 2717 memset(&dump_map, 0, sizeof(dump_map)); 2718 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2719 &availmem_regions_sz); 2720 for (i = 0; i < physmem_regions_sz; i++) { 2721 dump_map[i].pa_start = physmem_regions[i].mr_start; 2722 dump_map[i].pa_size = physmem_regions[i].mr_size; 2723 } 2724 return; 2725 } 2726 2727 /* Virtual segments for minidumps: */ 2728 memset(&dump_map, 0, sizeof(dump_map)); 2729 2730 /* 1st: kernel .data and .bss. */ 2731 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2732 dump_map[0].pa_size = 2733 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2734 2735 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2736 dump_map[1].pa_start = data_start; 2737 dump_map[1].pa_size = data_end - data_start; 2738 2739 /* 3rd: kernel VM. */ 2740 va = dump_map[1].pa_start + dump_map[1].pa_size; 2741 /* Find start of next chunk (from va). */ 2742 while (va < virtual_end) { 2743 /* Don't dump the buffer cache. */ 2744 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2745 va = kmi.buffer_eva; 2746 continue; 2747 } 2748 pte = pte_find(mmu, kernel_pmap, va); 2749 if (pte != NULL && PTE_ISVALID(pte)) 2750 break; 2751 va += PAGE_SIZE; 2752 } 2753 if (va < virtual_end) { 2754 dump_map[2].pa_start = va; 2755 va += PAGE_SIZE; 2756 /* Find last page in chunk. */ 2757 while (va < virtual_end) { 2758 /* Don't run into the buffer cache. */ 2759 if (va == kmi.buffer_sva) 2760 break; 2761 pte = pte_find(mmu, kernel_pmap, va); 2762 if (pte == NULL || !PTE_ISVALID(pte)) 2763 break; 2764 va += PAGE_SIZE; 2765 } 2766 dump_map[2].pa_size = va - dump_map[2].pa_start; 2767 } 2768 } 2769 2770 /* 2771 * Map a set of physical memory pages into the kernel virtual address space. 2772 * Return a pointer to where it is mapped. This routine is intended to be used 2773 * for mapping device memory, NOT real memory. 2774 */ 2775 static void * 2776 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2777 { 2778 2779 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2780 } 2781 2782 static void * 2783 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2784 { 2785 void *res; 2786 uintptr_t va; 2787 vm_size_t sz; 2788 int i; 2789 2790 /* 2791 * Check if this is premapped in TLB1. Note: this should probably also 2792 * check whether a sequence of TLB1 entries exist that match the 2793 * requirement, but now only checks the easy case. 2794 */ 2795 if (ma == VM_MEMATTR_DEFAULT) { 2796 for (i = 0; i < tlb1_idx; i++) { 2797 if (!(tlb1[i].mas1 & MAS1_VALID)) 2798 continue; 2799 if (pa >= tlb1[i].phys && 2800 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2801 return (void *)(tlb1[i].virt + 2802 (vm_offset_t)(pa - tlb1[i].phys)); 2803 } 2804 } 2805 2806 size = roundup(size, PAGE_SIZE); 2807 2808 /* 2809 * We leave a hole for device direct mapping between the maximum user 2810 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2811 * devices are in there, just map them 1:1. If not, map them to the 2812 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2813 * addresses should be pulled from an allocator, but since we do not 2814 * ever free TLB1 entries, it is safe just to increment a counter. 2815 * Note that there isn't a lot of address space here (128 MB) and it 2816 * is not at all difficult to imagine running out, since that is a 4:1 2817 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2818 * mapped there. 2819 */ 2820 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2821 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2822 va = pa; 2823 else 2824 va = atomic_fetchadd_int(&tlb1_map_base, size); 2825 res = (void *)va; 2826 2827 do { 2828 sz = 1 << (ilog2(size) & ~1); 2829 if (va % sz != 0) { 2830 do { 2831 sz >>= 2; 2832 } while (va % sz != 0); 2833 } 2834 if (bootverbose) 2835 printf("Wiring VA=%x to PA=%llx (size=%x), " 2836 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2837 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2838 size -= sz; 2839 pa += sz; 2840 va += sz; 2841 } while (size > 0); 2842 2843 return (res); 2844 } 2845 2846 /* 2847 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2848 */ 2849 static void 2850 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2851 { 2852 #ifdef SUPPORTS_SHRINKING_TLB1 2853 vm_offset_t base, offset; 2854 2855 /* 2856 * Unmap only if this is inside kernel virtual space. 2857 */ 2858 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2859 base = trunc_page(va); 2860 offset = va & PAGE_MASK; 2861 size = roundup(offset + size, PAGE_SIZE); 2862 kva_free(base, size); 2863 } 2864 #endif 2865 } 2866 2867 /* 2868 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2869 * specified pmap. This eliminates the blast of soft faults on process startup 2870 * and immediately after an mmap. 2871 */ 2872 static void 2873 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2874 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2875 { 2876 2877 VM_OBJECT_ASSERT_WLOCKED(object); 2878 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2879 ("mmu_booke_object_init_pt: non-device object")); 2880 } 2881 2882 /* 2883 * Perform the pmap work for mincore. 2884 */ 2885 static int 2886 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2887 vm_paddr_t *locked_pa) 2888 { 2889 2890 /* XXX: this should be implemented at some point */ 2891 return (0); 2892 } 2893 2894 /**************************************************************************/ 2895 /* TID handling */ 2896 /**************************************************************************/ 2897 2898 /* 2899 * Allocate a TID. If necessary, steal one from someone else. 2900 * The new TID is flushed from the TLB before returning. 2901 */ 2902 static tlbtid_t 2903 tid_alloc(pmap_t pmap) 2904 { 2905 tlbtid_t tid; 2906 int thiscpu; 2907 2908 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2909 2910 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2911 2912 thiscpu = PCPU_GET(cpuid); 2913 2914 tid = PCPU_GET(tid_next); 2915 if (tid > TID_MAX) 2916 tid = TID_MIN; 2917 PCPU_SET(tid_next, tid + 1); 2918 2919 /* If we are stealing TID then clear the relevant pmap's field */ 2920 if (tidbusy[thiscpu][tid] != NULL) { 2921 2922 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2923 2924 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2925 2926 /* Flush all entries from TLB0 matching this TID. */ 2927 tid_flush(tid); 2928 } 2929 2930 tidbusy[thiscpu][tid] = pmap; 2931 pmap->pm_tid[thiscpu] = tid; 2932 __asm __volatile("msync; isync"); 2933 2934 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2935 PCPU_GET(tid_next)); 2936 2937 return (tid); 2938 } 2939 2940 /**************************************************************************/ 2941 /* TLB0 handling */ 2942 /**************************************************************************/ 2943 2944 static void 2945 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2946 uint32_t mas7) 2947 { 2948 int as; 2949 char desc[3]; 2950 tlbtid_t tid; 2951 vm_size_t size; 2952 unsigned int tsize; 2953 2954 desc[2] = '\0'; 2955 if (mas1 & MAS1_VALID) 2956 desc[0] = 'V'; 2957 else 2958 desc[0] = ' '; 2959 2960 if (mas1 & MAS1_IPROT) 2961 desc[1] = 'P'; 2962 else 2963 desc[1] = ' '; 2964 2965 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2966 tid = MAS1_GETTID(mas1); 2967 2968 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2969 size = 0; 2970 if (tsize) 2971 size = tsize2size(tsize); 2972 2973 debugf("%3d: (%s) [AS=%d] " 2974 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2975 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2976 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2977 } 2978 2979 /* Convert TLB0 va and way number to tlb0[] table index. */ 2980 static inline unsigned int 2981 tlb0_tableidx(vm_offset_t va, unsigned int way) 2982 { 2983 unsigned int idx; 2984 2985 idx = (way * TLB0_ENTRIES_PER_WAY); 2986 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2987 return (idx); 2988 } 2989 2990 /* 2991 * Invalidate TLB0 entry. 2992 */ 2993 static inline void 2994 tlb0_flush_entry(vm_offset_t va) 2995 { 2996 2997 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2998 2999 mtx_assert(&tlbivax_mutex, MA_OWNED); 3000 3001 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3002 __asm __volatile("isync; msync"); 3003 __asm __volatile("tlbsync; msync"); 3004 3005 CTR1(KTR_PMAP, "%s: e", __func__); 3006 } 3007 3008 /* Print out contents of the MAS registers for each TLB0 entry */ 3009 void 3010 tlb0_print_tlbentries(void) 3011 { 3012 uint32_t mas0, mas1, mas2, mas3, mas7; 3013 int entryidx, way, idx; 3014 3015 debugf("TLB0 entries:\n"); 3016 for (way = 0; way < TLB0_WAYS; way ++) 3017 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3018 3019 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3020 mtspr(SPR_MAS0, mas0); 3021 __asm __volatile("isync"); 3022 3023 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3024 mtspr(SPR_MAS2, mas2); 3025 3026 __asm __volatile("isync; tlbre"); 3027 3028 mas1 = mfspr(SPR_MAS1); 3029 mas2 = mfspr(SPR_MAS2); 3030 mas3 = mfspr(SPR_MAS3); 3031 mas7 = mfspr(SPR_MAS7); 3032 3033 idx = tlb0_tableidx(mas2, way); 3034 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3035 } 3036 } 3037 3038 /**************************************************************************/ 3039 /* TLB1 handling */ 3040 /**************************************************************************/ 3041 3042 /* 3043 * TLB1 mapping notes: 3044 * 3045 * TLB1[0] Kernel text and data. 3046 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3047 * windows, other devices mappings. 3048 */ 3049 3050 /* 3051 * Write given entry to TLB1 hardware. 3052 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3053 */ 3054 static void 3055 tlb1_write_entry(unsigned int idx) 3056 { 3057 uint32_t mas0; 3058 3059 //debugf("tlb1_write_entry: s\n"); 3060 3061 /* Select entry */ 3062 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3063 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3064 3065 mtspr(SPR_MAS0, mas0); 3066 __asm __volatile("isync"); 3067 mtspr(SPR_MAS1, tlb1[idx].mas1); 3068 __asm __volatile("isync"); 3069 mtspr(SPR_MAS2, tlb1[idx].mas2); 3070 __asm __volatile("isync"); 3071 mtspr(SPR_MAS3, tlb1[idx].mas3); 3072 __asm __volatile("isync"); 3073 switch ((mfpvr() >> 16) & 0xFFFF) { 3074 case FSL_E500mc: 3075 case FSL_E5500: 3076 mtspr(SPR_MAS8, 0); 3077 __asm __volatile("isync"); 3078 /* FALLTHROUGH */ 3079 case FSL_E500v2: 3080 mtspr(SPR_MAS7, tlb1[idx].mas7); 3081 __asm __volatile("isync"); 3082 break; 3083 default: 3084 break; 3085 } 3086 3087 __asm __volatile("tlbwe; isync; msync"); 3088 3089 //debugf("tlb1_write_entry: e\n"); 3090 } 3091 3092 /* 3093 * Return the largest uint value log such that 2^log <= num. 3094 */ 3095 static unsigned int 3096 ilog2(unsigned int num) 3097 { 3098 int lz; 3099 3100 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3101 return (31 - lz); 3102 } 3103 3104 /* 3105 * Convert TLB TSIZE value to mapped region size. 3106 */ 3107 static vm_size_t 3108 tsize2size(unsigned int tsize) 3109 { 3110 3111 /* 3112 * size = 4^tsize KB 3113 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3114 */ 3115 3116 return ((1 << (2 * tsize)) * 1024); 3117 } 3118 3119 /* 3120 * Convert region size (must be power of 4) to TLB TSIZE value. 3121 */ 3122 static unsigned int 3123 size2tsize(vm_size_t size) 3124 { 3125 3126 return (ilog2(size) / 2 - 5); 3127 } 3128 3129 /* 3130 * Register permanent kernel mapping in TLB1. 3131 * 3132 * Entries are created starting from index 0 (current free entry is 3133 * kept in tlb1_idx) and are not supposed to be invalidated. 3134 */ 3135 static int 3136 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3137 uint32_t flags) 3138 { 3139 uint32_t ts, tid; 3140 int tsize, index; 3141 3142 index = atomic_fetchadd_int(&tlb1_idx, 1); 3143 if (index >= TLB1_ENTRIES) { 3144 printf("tlb1_set_entry: TLB1 full!\n"); 3145 return (-1); 3146 } 3147 3148 /* Convert size to TSIZE */ 3149 tsize = size2tsize(size); 3150 3151 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3152 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3153 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3154 3155 /* 3156 * Atomicity is preserved by the atomic increment above since nothing 3157 * is ever removed from tlb1. 3158 */ 3159 3160 tlb1[index].phys = pa; 3161 tlb1[index].virt = va; 3162 tlb1[index].size = size; 3163 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3164 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3165 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3166 3167 /* Set supervisor RWX permission bits */ 3168 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3169 tlb1[index].mas7 = (pa >> 32) & MAS7_RPN; 3170 3171 tlb1_write_entry(index); 3172 3173 /* 3174 * XXX in general TLB1 updates should be propagated between CPUs, 3175 * since current design assumes to have the same TLB1 set-up on all 3176 * cores. 3177 */ 3178 return (0); 3179 } 3180 3181 /* 3182 * Map in contiguous RAM region into the TLB1 using maximum of 3183 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3184 * 3185 * If necessary round up last entry size and return total size 3186 * used by all allocated entries. 3187 */ 3188 vm_size_t 3189 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3190 { 3191 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3192 vm_size_t mapped, pgsz, base, mask; 3193 int idx, nents; 3194 3195 /* Round up to the next 1M */ 3196 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3197 3198 mapped = 0; 3199 idx = 0; 3200 base = va; 3201 pgsz = 64*1024*1024; 3202 while (mapped < size) { 3203 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3204 while (pgsz > (size - mapped)) 3205 pgsz >>= 2; 3206 pgs[idx++] = pgsz; 3207 mapped += pgsz; 3208 } 3209 3210 /* We under-map. Correct for this. */ 3211 if (mapped < size) { 3212 while (pgs[idx - 1] == pgsz) { 3213 idx--; 3214 mapped -= pgsz; 3215 } 3216 /* XXX We may increase beyond out starting point. */ 3217 pgsz <<= 2; 3218 pgs[idx++] = pgsz; 3219 mapped += pgsz; 3220 } 3221 } 3222 3223 nents = idx; 3224 mask = pgs[0] - 1; 3225 /* Align address to the boundary */ 3226 if (va & mask) { 3227 va = (va + mask) & ~mask; 3228 pa = (pa + mask) & ~mask; 3229 } 3230 3231 for (idx = 0; idx < nents; idx++) { 3232 pgsz = pgs[idx]; 3233 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3234 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3235 pa += pgsz; 3236 va += pgsz; 3237 } 3238 3239 mapped = (va - base); 3240 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3241 mapped, mapped - size); 3242 return (mapped); 3243 } 3244 3245 /* 3246 * TLB1 initialization routine, to be called after the very first 3247 * assembler level setup done in locore.S. 3248 */ 3249 void 3250 tlb1_init() 3251 { 3252 uint32_t mas0, mas1, mas2, mas3, mas7; 3253 uint32_t tsz; 3254 int i; 3255 3256 tlb1_idx = 1; 3257 3258 tlb1_get_tlbconf(); 3259 3260 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3261 mtspr(SPR_MAS0, mas0); 3262 __asm __volatile("isync; tlbre"); 3263 3264 mas1 = mfspr(SPR_MAS1); 3265 mas2 = mfspr(SPR_MAS2); 3266 mas3 = mfspr(SPR_MAS3); 3267 mas7 = mfspr(SPR_MAS7); 3268 3269 tlb1[0].mas1 = mas1; 3270 tlb1[0].mas2 = mfspr(SPR_MAS2); 3271 tlb1[0].mas3 = mas3; 3272 tlb1[0].mas7 = mas7; 3273 tlb1[0].virt = mas2 & MAS2_EPN_MASK; 3274 tlb1[0].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3275 (mas3 & MAS3_RPN); 3276 3277 kernload = tlb1[0].phys; 3278 3279 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3280 tlb1[0].size = (tsz > 0) ? tsize2size(tsz) : 0; 3281 kernsize += tlb1[0].size; 3282 3283 #ifdef SMP 3284 bp_ntlb1s = tlb1_idx; 3285 #endif 3286 3287 /* Purge the remaining entries */ 3288 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3289 tlb1_write_entry(i); 3290 3291 /* Setup TLB miss defaults */ 3292 set_mas4_defaults(); 3293 } 3294 3295 vm_offset_t 3296 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3297 { 3298 vm_paddr_t pa_base; 3299 vm_offset_t va, sz; 3300 int i; 3301 3302 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3303 3304 for (i = 0; i < tlb1_idx; i++) { 3305 if (!(tlb1[i].mas1 & MAS1_VALID)) 3306 continue; 3307 if (pa >= tlb1[i].phys && (pa + size) <= 3308 (tlb1[i].phys + tlb1[i].size)) 3309 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3310 } 3311 3312 pa_base = rounddown(pa, PAGE_SIZE); 3313 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3314 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3315 va = tlb1_map_base + (pa - pa_base); 3316 3317 do { 3318 sz = 1 << (ilog2(size) & ~1); 3319 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3320 size -= sz; 3321 pa_base += sz; 3322 tlb1_map_base += sz; 3323 } while (size > 0); 3324 3325 #ifdef SMP 3326 bp_ntlb1s = tlb1_idx; 3327 #endif 3328 3329 return (va); 3330 } 3331 3332 /* 3333 * Setup MAS4 defaults. 3334 * These values are loaded to MAS0-2 on a TLB miss. 3335 */ 3336 static void 3337 set_mas4_defaults(void) 3338 { 3339 uint32_t mas4; 3340 3341 /* Defaults: TLB0, PID0, TSIZED=4K */ 3342 mas4 = MAS4_TLBSELD0; 3343 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3344 #ifdef SMP 3345 mas4 |= MAS4_MD; 3346 #endif 3347 mtspr(SPR_MAS4, mas4); 3348 __asm __volatile("isync"); 3349 } 3350 3351 /* 3352 * Print out contents of the MAS registers for each TLB1 entry 3353 */ 3354 void 3355 tlb1_print_tlbentries(void) 3356 { 3357 uint32_t mas0, mas1, mas2, mas3, mas7; 3358 int i; 3359 3360 debugf("TLB1 entries:\n"); 3361 for (i = 0; i < TLB1_ENTRIES; i++) { 3362 3363 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3364 mtspr(SPR_MAS0, mas0); 3365 3366 __asm __volatile("isync; tlbre"); 3367 3368 mas1 = mfspr(SPR_MAS1); 3369 mas2 = mfspr(SPR_MAS2); 3370 mas3 = mfspr(SPR_MAS3); 3371 mas7 = mfspr(SPR_MAS7); 3372 3373 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3374 } 3375 } 3376 3377 /* 3378 * Print out contents of the in-ram tlb1 table. 3379 */ 3380 void 3381 tlb1_print_entries(void) 3382 { 3383 int i; 3384 3385 debugf("tlb1[] table entries:\n"); 3386 for (i = 0; i < TLB1_ENTRIES; i++) 3387 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 3388 tlb1[i].mas7); 3389 } 3390 3391 /* 3392 * Return 0 if the physical IO range is encompassed by one of the 3393 * the TLB1 entries, otherwise return related error code. 3394 */ 3395 static int 3396 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3397 { 3398 uint32_t prot; 3399 vm_paddr_t pa_start; 3400 vm_paddr_t pa_end; 3401 unsigned int entry_tsize; 3402 vm_size_t entry_size; 3403 3404 *va = (vm_offset_t)NULL; 3405 3406 /* Skip invalid entries */ 3407 if (!(tlb1[i].mas1 & MAS1_VALID)) 3408 return (EINVAL); 3409 3410 /* 3411 * The entry must be cache-inhibited, guarded, and r/w 3412 * so it can function as an i/o page 3413 */ 3414 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3415 if (prot != (MAS2_I | MAS2_G)) 3416 return (EPERM); 3417 3418 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3419 if (prot != (MAS3_SR | MAS3_SW)) 3420 return (EPERM); 3421 3422 /* The address should be within the entry range. */ 3423 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3424 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3425 3426 entry_size = tsize2size(entry_tsize); 3427 pa_start = (((vm_paddr_t)tlb1[i].mas7 & MAS7_RPN) << 32) | 3428 (tlb1[i].mas3 & MAS3_RPN); 3429 pa_end = pa_start + entry_size; 3430 3431 if ((pa < pa_start) || ((pa + size) > pa_end)) 3432 return (ERANGE); 3433 3434 /* Return virtual address of this mapping. */ 3435 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3436 return (0); 3437 } 3438 3439 /* 3440 * Invalidate all TLB0 entries which match the given TID. Note this is 3441 * dedicated for cases when invalidations should NOT be propagated to other 3442 * CPUs. 3443 */ 3444 static void 3445 tid_flush(tlbtid_t tid) 3446 { 3447 register_t msr; 3448 uint32_t mas0, mas1, mas2; 3449 int entry, way; 3450 3451 3452 /* Don't evict kernel translations */ 3453 if (tid == TID_KERNEL) 3454 return; 3455 3456 msr = mfmsr(); 3457 __asm __volatile("wrteei 0"); 3458 3459 for (way = 0; way < TLB0_WAYS; way++) 3460 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3461 3462 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3463 mtspr(SPR_MAS0, mas0); 3464 __asm __volatile("isync"); 3465 3466 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3467 mtspr(SPR_MAS2, mas2); 3468 3469 __asm __volatile("isync; tlbre"); 3470 3471 mas1 = mfspr(SPR_MAS1); 3472 3473 if (!(mas1 & MAS1_VALID)) 3474 continue; 3475 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3476 continue; 3477 mas1 &= ~MAS1_VALID; 3478 mtspr(SPR_MAS1, mas1); 3479 __asm __volatile("isync; tlbwe; isync; msync"); 3480 } 3481 mtmsr(msr); 3482 } 3483