1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #ifdef DEBUG 100 #define debugf(fmt, args...) printf(fmt, ##args) 101 #else 102 #define debugf(fmt, args...) 103 #endif 104 105 #define TODO panic("%s: not implemented", __func__); 106 107 extern unsigned char _etext[]; 108 extern unsigned char _end[]; 109 110 extern uint32_t *bootinfo; 111 112 #ifdef SMP 113 extern uint32_t bp_ntlb1s; 114 #endif 115 116 vm_paddr_t kernload; 117 vm_offset_t kernstart; 118 vm_size_t kernsize; 119 120 /* Message buffer and tables. */ 121 static vm_offset_t data_start; 122 static vm_size_t data_end; 123 124 /* Phys/avail memory regions. */ 125 static struct mem_region *availmem_regions; 126 static int availmem_regions_sz; 127 static struct mem_region *physmem_regions; 128 static int physmem_regions_sz; 129 130 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 131 static vm_offset_t zero_page_va; 132 static struct mtx zero_page_mutex; 133 134 static struct mtx tlbivax_mutex; 135 136 /* 137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 138 * by idle thred only, no lock required. 139 */ 140 static vm_offset_t zero_page_idle_va; 141 142 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 143 static vm_offset_t copy_page_src_va; 144 static vm_offset_t copy_page_dst_va; 145 static struct mtx copy_page_mutex; 146 147 /**************************************************************************/ 148 /* PMAP */ 149 /**************************************************************************/ 150 151 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 152 vm_prot_t, u_int flags, int8_t psind); 153 154 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 155 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 156 157 /* 158 * If user pmap is processed with mmu_booke_remove and the resident count 159 * drops to 0, there are no more pages to remove, so we need not continue. 160 */ 161 #define PMAP_REMOVE_DONE(pmap) \ 162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 163 164 extern int elf32_nxstack; 165 166 /**************************************************************************/ 167 /* TLB and TID handling */ 168 /**************************************************************************/ 169 170 /* Translation ID busy table */ 171 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 172 173 /* 174 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 175 * core revisions and should be read from h/w registers during early config. 176 */ 177 uint32_t tlb0_entries; 178 uint32_t tlb0_ways; 179 uint32_t tlb0_entries_per_way; 180 uint32_t tlb1_entries; 181 182 #define TLB0_ENTRIES (tlb0_entries) 183 #define TLB0_WAYS (tlb0_ways) 184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186 #define TLB1_ENTRIES (tlb1_entries) 187 #define TLB1_MAXENTRIES 64 188 189 /* In-ram copy of the TLB1 */ 190 static tlb_entry_t tlb1[TLB1_MAXENTRIES]; 191 192 /* Next free entry in the TLB1 */ 193 static unsigned int tlb1_idx; 194 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 195 196 static tlbtid_t tid_alloc(struct pmap *); 197 static void tid_flush(tlbtid_t tid); 198 199 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 200 201 static void tlb1_write_entry(unsigned int); 202 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 203 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 204 205 static vm_size_t tsize2size(unsigned int); 206 static unsigned int size2tsize(vm_size_t); 207 static unsigned int ilog2(unsigned int); 208 209 static void set_mas4_defaults(void); 210 211 static inline void tlb0_flush_entry(vm_offset_t); 212 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 213 214 /**************************************************************************/ 215 /* Page table management */ 216 /**************************************************************************/ 217 218 static struct rwlock_padalign pvh_global_lock; 219 220 /* Data for the pv entry allocation mechanism */ 221 static uma_zone_t pvzone; 222 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 223 224 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 225 226 #ifndef PMAP_SHPGPERPROC 227 #define PMAP_SHPGPERPROC 200 228 #endif 229 230 static void ptbl_init(void); 231 static struct ptbl_buf *ptbl_buf_alloc(void); 232 static void ptbl_buf_free(struct ptbl_buf *); 233 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 234 235 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 236 static void ptbl_free(mmu_t, pmap_t, unsigned int); 237 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 238 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 239 240 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 241 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 242 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 243 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 244 static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, 245 vm_offset_t pdir); 246 247 static pv_entry_t pv_alloc(void); 248 static void pv_free(pv_entry_t); 249 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 250 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 251 252 static void booke_pmap_init_qpages(void); 253 254 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 255 #define PTBL_BUFS (128 * 16) 256 257 struct ptbl_buf { 258 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 259 vm_offset_t kva; /* va of mapping */ 260 }; 261 262 /* ptbl free list and a lock used for access synchronization. */ 263 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 264 static struct mtx ptbl_buf_freelist_lock; 265 266 /* Base address of kva space allocated fot ptbl bufs. */ 267 static vm_offset_t ptbl_buf_pool_vabase; 268 269 /* Pointer to ptbl_buf structures. */ 270 static struct ptbl_buf *ptbl_bufs; 271 272 #ifdef SMP 273 void pmap_bootstrap_ap(volatile uint32_t *); 274 #endif 275 276 /* 277 * Kernel MMU interface 278 */ 279 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 280 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 281 vm_size_t, vm_offset_t); 282 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 283 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 284 vm_offset_t, vm_page_t *, vm_offset_t, int); 285 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 286 vm_prot_t, u_int flags, int8_t psind); 287 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 288 vm_page_t, vm_prot_t); 289 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 290 vm_prot_t); 291 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 292 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 293 vm_prot_t); 294 static void mmu_booke_init(mmu_t); 295 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 296 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 297 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 298 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 299 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 300 int); 301 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 302 vm_paddr_t *); 303 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 304 vm_object_t, vm_pindex_t, vm_size_t); 305 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 306 static void mmu_booke_page_init(mmu_t, vm_page_t); 307 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 308 static void mmu_booke_pinit(mmu_t, pmap_t); 309 static void mmu_booke_pinit0(mmu_t, pmap_t); 310 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 311 vm_prot_t); 312 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 313 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 314 static void mmu_booke_release(mmu_t, pmap_t); 315 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 316 static void mmu_booke_remove_all(mmu_t, vm_page_t); 317 static void mmu_booke_remove_write(mmu_t, vm_page_t); 318 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 319 static void mmu_booke_zero_page(mmu_t, vm_page_t); 320 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 321 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 322 static void mmu_booke_activate(mmu_t, struct thread *); 323 static void mmu_booke_deactivate(mmu_t, struct thread *); 324 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 325 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 326 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 327 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 328 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 329 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 330 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 331 static void mmu_booke_kremove(mmu_t, vm_offset_t); 332 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 333 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 334 vm_size_t); 335 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 336 void **); 337 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 338 void *); 339 static void mmu_booke_scan_init(mmu_t); 340 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 341 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 342 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 343 vm_size_t sz, vm_memattr_t mode); 344 345 static mmu_method_t mmu_booke_methods[] = { 346 /* pmap dispatcher interface */ 347 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 348 MMUMETHOD(mmu_copy, mmu_booke_copy), 349 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 350 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 351 MMUMETHOD(mmu_enter, mmu_booke_enter), 352 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 353 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 354 MMUMETHOD(mmu_extract, mmu_booke_extract), 355 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 356 MMUMETHOD(mmu_init, mmu_booke_init), 357 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 358 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 359 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 360 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 361 MMUMETHOD(mmu_map, mmu_booke_map), 362 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 363 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 364 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 365 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 366 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 367 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 368 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 369 MMUMETHOD(mmu_protect, mmu_booke_protect), 370 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 371 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 372 MMUMETHOD(mmu_release, mmu_booke_release), 373 MMUMETHOD(mmu_remove, mmu_booke_remove), 374 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 375 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 376 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 377 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 378 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 379 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 380 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 381 MMUMETHOD(mmu_activate, mmu_booke_activate), 382 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 383 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 384 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 385 386 /* Internal interfaces */ 387 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 388 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 389 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 390 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 391 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 392 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 393 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 394 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 395 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 396 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 397 398 /* dumpsys() support */ 399 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 400 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 401 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 402 403 { 0, 0 } 404 }; 405 406 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 407 408 static __inline uint32_t 409 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 410 { 411 uint32_t attrib; 412 int i; 413 414 if (ma != VM_MEMATTR_DEFAULT) { 415 switch (ma) { 416 case VM_MEMATTR_UNCACHEABLE: 417 return (MAS2_I | MAS2_G); 418 case VM_MEMATTR_WRITE_COMBINING: 419 case VM_MEMATTR_WRITE_BACK: 420 case VM_MEMATTR_PREFETCHABLE: 421 return (MAS2_I); 422 case VM_MEMATTR_WRITE_THROUGH: 423 return (MAS2_W | MAS2_M); 424 case VM_MEMATTR_CACHEABLE: 425 return (MAS2_M); 426 } 427 } 428 429 /* 430 * Assume the page is cache inhibited and access is guarded unless 431 * it's in our available memory array. 432 */ 433 attrib = _TLB_ENTRY_IO; 434 for (i = 0; i < physmem_regions_sz; i++) { 435 if ((pa >= physmem_regions[i].mr_start) && 436 (pa < (physmem_regions[i].mr_start + 437 physmem_regions[i].mr_size))) { 438 attrib = _TLB_ENTRY_MEM; 439 break; 440 } 441 } 442 443 return (attrib); 444 } 445 446 static inline void 447 tlb_miss_lock(void) 448 { 449 #ifdef SMP 450 struct pcpu *pc; 451 452 if (!smp_started) 453 return; 454 455 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 456 if (pc != pcpup) { 457 458 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 459 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 460 461 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 462 ("tlb_miss_lock: tried to lock self")); 463 464 tlb_lock(pc->pc_booke_tlb_lock); 465 466 CTR1(KTR_PMAP, "%s: locked", __func__); 467 } 468 } 469 #endif 470 } 471 472 static inline void 473 tlb_miss_unlock(void) 474 { 475 #ifdef SMP 476 struct pcpu *pc; 477 478 if (!smp_started) 479 return; 480 481 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 482 if (pc != pcpup) { 483 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 484 __func__, pc->pc_cpuid); 485 486 tlb_unlock(pc->pc_booke_tlb_lock); 487 488 CTR1(KTR_PMAP, "%s: unlocked", __func__); 489 } 490 } 491 #endif 492 } 493 494 /* Return number of entries in TLB0. */ 495 static __inline void 496 tlb0_get_tlbconf(void) 497 { 498 uint32_t tlb0_cfg; 499 500 tlb0_cfg = mfspr(SPR_TLB0CFG); 501 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 502 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 503 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 504 } 505 506 /* Return number of entries in TLB1. */ 507 static __inline void 508 tlb1_get_tlbconf(void) 509 { 510 uint32_t tlb1_cfg; 511 512 tlb1_cfg = mfspr(SPR_TLB1CFG); 513 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 514 } 515 516 /**************************************************************************/ 517 /* Page table related */ 518 /**************************************************************************/ 519 520 /* Initialize pool of kva ptbl buffers. */ 521 static void 522 ptbl_init(void) 523 { 524 int i; 525 526 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 527 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 528 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 529 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 530 531 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 532 TAILQ_INIT(&ptbl_buf_freelist); 533 534 for (i = 0; i < PTBL_BUFS; i++) { 535 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 536 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 537 } 538 } 539 540 /* Get a ptbl_buf from the freelist. */ 541 static struct ptbl_buf * 542 ptbl_buf_alloc(void) 543 { 544 struct ptbl_buf *buf; 545 546 mtx_lock(&ptbl_buf_freelist_lock); 547 buf = TAILQ_FIRST(&ptbl_buf_freelist); 548 if (buf != NULL) 549 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 550 mtx_unlock(&ptbl_buf_freelist_lock); 551 552 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 553 554 return (buf); 555 } 556 557 /* Return ptbl buff to free pool. */ 558 static void 559 ptbl_buf_free(struct ptbl_buf *buf) 560 { 561 562 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 563 564 mtx_lock(&ptbl_buf_freelist_lock); 565 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 566 mtx_unlock(&ptbl_buf_freelist_lock); 567 } 568 569 /* 570 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 571 */ 572 static void 573 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 574 { 575 struct ptbl_buf *pbuf; 576 577 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 578 579 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 580 581 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 582 if (pbuf->kva == (vm_offset_t)ptbl) { 583 /* Remove from pmap ptbl buf list. */ 584 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 585 586 /* Free corresponding ptbl buf. */ 587 ptbl_buf_free(pbuf); 588 break; 589 } 590 } 591 592 /* Allocate page table. */ 593 static pte_t * 594 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 595 { 596 vm_page_t mtbl[PTBL_PAGES]; 597 vm_page_t m; 598 struct ptbl_buf *pbuf; 599 unsigned int pidx; 600 pte_t *ptbl; 601 int i, j; 602 603 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 604 (pmap == kernel_pmap), pdir_idx); 605 606 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 607 ("ptbl_alloc: invalid pdir_idx")); 608 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 609 ("pte_alloc: valid ptbl entry exists!")); 610 611 pbuf = ptbl_buf_alloc(); 612 if (pbuf == NULL) 613 panic("pte_alloc: couldn't alloc kernel virtual memory"); 614 615 ptbl = (pte_t *)pbuf->kva; 616 617 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 618 619 /* Allocate ptbl pages, this will sleep! */ 620 for (i = 0; i < PTBL_PAGES; i++) { 621 pidx = (PTBL_PAGES * pdir_idx) + i; 622 while ((m = vm_page_alloc(NULL, pidx, 623 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 624 PMAP_UNLOCK(pmap); 625 rw_wunlock(&pvh_global_lock); 626 if (nosleep) { 627 ptbl_free_pmap_ptbl(pmap, ptbl); 628 for (j = 0; j < i; j++) 629 vm_page_free(mtbl[j]); 630 atomic_subtract_int(&vm_cnt.v_wire_count, i); 631 return (NULL); 632 } 633 VM_WAIT; 634 rw_wlock(&pvh_global_lock); 635 PMAP_LOCK(pmap); 636 } 637 mtbl[i] = m; 638 } 639 640 /* Map allocated pages into kernel_pmap. */ 641 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 642 643 /* Zero whole ptbl. */ 644 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 645 646 /* Add pbuf to the pmap ptbl bufs list. */ 647 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 648 649 return (ptbl); 650 } 651 652 /* Free ptbl pages and invalidate pdir entry. */ 653 static void 654 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 655 { 656 pte_t *ptbl; 657 vm_paddr_t pa; 658 vm_offset_t va; 659 vm_page_t m; 660 int i; 661 662 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 663 (pmap == kernel_pmap), pdir_idx); 664 665 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 666 ("ptbl_free: invalid pdir_idx")); 667 668 ptbl = pmap->pm_pdir[pdir_idx]; 669 670 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 671 672 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 673 674 /* 675 * Invalidate the pdir entry as soon as possible, so that other CPUs 676 * don't attempt to look up the page tables we are releasing. 677 */ 678 mtx_lock_spin(&tlbivax_mutex); 679 tlb_miss_lock(); 680 681 pmap->pm_pdir[pdir_idx] = NULL; 682 683 tlb_miss_unlock(); 684 mtx_unlock_spin(&tlbivax_mutex); 685 686 for (i = 0; i < PTBL_PAGES; i++) { 687 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 688 pa = pte_vatopa(mmu, kernel_pmap, va); 689 m = PHYS_TO_VM_PAGE(pa); 690 vm_page_free_zero(m); 691 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 692 mmu_booke_kremove(mmu, va); 693 } 694 695 ptbl_free_pmap_ptbl(pmap, ptbl); 696 } 697 698 /* 699 * Decrement ptbl pages hold count and attempt to free ptbl pages. 700 * Called when removing pte entry from ptbl. 701 * 702 * Return 1 if ptbl pages were freed. 703 */ 704 static int 705 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 706 { 707 pte_t *ptbl; 708 vm_paddr_t pa; 709 vm_page_t m; 710 int i; 711 712 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 713 (pmap == kernel_pmap), pdir_idx); 714 715 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 716 ("ptbl_unhold: invalid pdir_idx")); 717 KASSERT((pmap != kernel_pmap), 718 ("ptbl_unhold: unholding kernel ptbl!")); 719 720 ptbl = pmap->pm_pdir[pdir_idx]; 721 722 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 723 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 724 ("ptbl_unhold: non kva ptbl")); 725 726 /* decrement hold count */ 727 for (i = 0; i < PTBL_PAGES; i++) { 728 pa = pte_vatopa(mmu, kernel_pmap, 729 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 730 m = PHYS_TO_VM_PAGE(pa); 731 m->wire_count--; 732 } 733 734 /* 735 * Free ptbl pages if there are no pte etries in this ptbl. 736 * wire_count has the same value for all ptbl pages, so check the last 737 * page. 738 */ 739 if (m->wire_count == 0) { 740 ptbl_free(mmu, pmap, pdir_idx); 741 742 //debugf("ptbl_unhold: e (freed ptbl)\n"); 743 return (1); 744 } 745 746 return (0); 747 } 748 749 /* 750 * Increment hold count for ptbl pages. This routine is used when a new pte 751 * entry is being inserted into the ptbl. 752 */ 753 static void 754 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 755 { 756 vm_paddr_t pa; 757 pte_t *ptbl; 758 vm_page_t m; 759 int i; 760 761 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 762 pdir_idx); 763 764 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 765 ("ptbl_hold: invalid pdir_idx")); 766 KASSERT((pmap != kernel_pmap), 767 ("ptbl_hold: holding kernel ptbl!")); 768 769 ptbl = pmap->pm_pdir[pdir_idx]; 770 771 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 772 773 for (i = 0; i < PTBL_PAGES; i++) { 774 pa = pte_vatopa(mmu, kernel_pmap, 775 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 776 m = PHYS_TO_VM_PAGE(pa); 777 m->wire_count++; 778 } 779 } 780 781 /* Allocate pv_entry structure. */ 782 pv_entry_t 783 pv_alloc(void) 784 { 785 pv_entry_t pv; 786 787 pv_entry_count++; 788 if (pv_entry_count > pv_entry_high_water) 789 pagedaemon_wakeup(); 790 pv = uma_zalloc(pvzone, M_NOWAIT); 791 792 return (pv); 793 } 794 795 /* Free pv_entry structure. */ 796 static __inline void 797 pv_free(pv_entry_t pve) 798 { 799 800 pv_entry_count--; 801 uma_zfree(pvzone, pve); 802 } 803 804 805 /* Allocate and initialize pv_entry structure. */ 806 static void 807 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 808 { 809 pv_entry_t pve; 810 811 //int su = (pmap == kernel_pmap); 812 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 813 // (u_int32_t)pmap, va, (u_int32_t)m); 814 815 pve = pv_alloc(); 816 if (pve == NULL) 817 panic("pv_insert: no pv entries!"); 818 819 pve->pv_pmap = pmap; 820 pve->pv_va = va; 821 822 /* add to pv_list */ 823 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 824 rw_assert(&pvh_global_lock, RA_WLOCKED); 825 826 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 827 828 //debugf("pv_insert: e\n"); 829 } 830 831 /* Destroy pv entry. */ 832 static void 833 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 834 { 835 pv_entry_t pve; 836 837 //int su = (pmap == kernel_pmap); 838 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 839 840 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 841 rw_assert(&pvh_global_lock, RA_WLOCKED); 842 843 /* find pv entry */ 844 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 845 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 846 /* remove from pv_list */ 847 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 848 if (TAILQ_EMPTY(&m->md.pv_list)) 849 vm_page_aflag_clear(m, PGA_WRITEABLE); 850 851 /* free pv entry struct */ 852 pv_free(pve); 853 break; 854 } 855 } 856 857 //debugf("pv_remove: e\n"); 858 } 859 860 /* 861 * Clean pte entry, try to free page table page if requested. 862 * 863 * Return 1 if ptbl pages were freed, otherwise return 0. 864 */ 865 static int 866 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 867 { 868 unsigned int pdir_idx = PDIR_IDX(va); 869 unsigned int ptbl_idx = PTBL_IDX(va); 870 vm_page_t m; 871 pte_t *ptbl; 872 pte_t *pte; 873 874 //int su = (pmap == kernel_pmap); 875 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 876 // su, (u_int32_t)pmap, va, flags); 877 878 ptbl = pmap->pm_pdir[pdir_idx]; 879 KASSERT(ptbl, ("pte_remove: null ptbl")); 880 881 pte = &ptbl[ptbl_idx]; 882 883 if (pte == NULL || !PTE_ISVALID(pte)) 884 return (0); 885 886 if (PTE_ISWIRED(pte)) 887 pmap->pm_stats.wired_count--; 888 889 /* Handle managed entry. */ 890 if (PTE_ISMANAGED(pte)) { 891 /* Get vm_page_t for mapped pte. */ 892 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 893 894 if (PTE_ISMODIFIED(pte)) 895 vm_page_dirty(m); 896 897 if (PTE_ISREFERENCED(pte)) 898 vm_page_aflag_set(m, PGA_REFERENCED); 899 900 pv_remove(pmap, va, m); 901 } 902 903 mtx_lock_spin(&tlbivax_mutex); 904 tlb_miss_lock(); 905 906 tlb0_flush_entry(va); 907 *pte = 0; 908 909 tlb_miss_unlock(); 910 mtx_unlock_spin(&tlbivax_mutex); 911 912 pmap->pm_stats.resident_count--; 913 914 if (flags & PTBL_UNHOLD) { 915 //debugf("pte_remove: e (unhold)\n"); 916 return (ptbl_unhold(mmu, pmap, pdir_idx)); 917 } 918 919 //debugf("pte_remove: e\n"); 920 return (0); 921 } 922 923 /* 924 * Insert PTE for a given page and virtual address. 925 */ 926 static int 927 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 928 boolean_t nosleep) 929 { 930 unsigned int pdir_idx = PDIR_IDX(va); 931 unsigned int ptbl_idx = PTBL_IDX(va); 932 pte_t *ptbl, *pte; 933 934 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 935 pmap == kernel_pmap, pmap, va); 936 937 /* Get the page table pointer. */ 938 ptbl = pmap->pm_pdir[pdir_idx]; 939 940 if (ptbl == NULL) { 941 /* Allocate page table pages. */ 942 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 943 if (ptbl == NULL) { 944 KASSERT(nosleep, ("nosleep and NULL ptbl")); 945 return (ENOMEM); 946 } 947 } else { 948 /* 949 * Check if there is valid mapping for requested 950 * va, if there is, remove it. 951 */ 952 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 953 if (PTE_ISVALID(pte)) { 954 pte_remove(mmu, pmap, va, PTBL_HOLD); 955 } else { 956 /* 957 * pte is not used, increment hold count 958 * for ptbl pages. 959 */ 960 if (pmap != kernel_pmap) 961 ptbl_hold(mmu, pmap, pdir_idx); 962 } 963 } 964 965 /* 966 * Insert pv_entry into pv_list for mapped page if part of managed 967 * memory. 968 */ 969 if ((m->oflags & VPO_UNMANAGED) == 0) { 970 flags |= PTE_MANAGED; 971 972 /* Create and insert pv entry. */ 973 pv_insert(pmap, va, m); 974 } 975 976 pmap->pm_stats.resident_count++; 977 978 mtx_lock_spin(&tlbivax_mutex); 979 tlb_miss_lock(); 980 981 tlb0_flush_entry(va); 982 if (pmap->pm_pdir[pdir_idx] == NULL) { 983 /* 984 * If we just allocated a new page table, hook it in 985 * the pdir. 986 */ 987 pmap->pm_pdir[pdir_idx] = ptbl; 988 } 989 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 990 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 991 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 992 993 tlb_miss_unlock(); 994 mtx_unlock_spin(&tlbivax_mutex); 995 return (0); 996 } 997 998 /* Return the pa for the given pmap/va. */ 999 static vm_paddr_t 1000 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1001 { 1002 vm_paddr_t pa = 0; 1003 pte_t *pte; 1004 1005 pte = pte_find(mmu, pmap, va); 1006 if ((pte != NULL) && PTE_ISVALID(pte)) 1007 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1008 return (pa); 1009 } 1010 1011 /* Get a pointer to a PTE in a page table. */ 1012 static pte_t * 1013 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1014 { 1015 unsigned int pdir_idx = PDIR_IDX(va); 1016 unsigned int ptbl_idx = PTBL_IDX(va); 1017 1018 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1019 1020 if (pmap->pm_pdir[pdir_idx]) 1021 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1022 1023 return (NULL); 1024 } 1025 1026 /* Set up kernel page tables. */ 1027 static void 1028 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1029 { 1030 int i; 1031 vm_offset_t va; 1032 pte_t *pte; 1033 1034 /* Initialize kernel pdir */ 1035 for (i = 0; i < kernel_ptbls; i++) 1036 kernel_pmap->pm_pdir[kptbl_min + i] = 1037 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1038 1039 /* 1040 * Fill in PTEs covering kernel code and data. They are not required 1041 * for address translation, as this area is covered by static TLB1 1042 * entries, but for pte_vatopa() to work correctly with kernel area 1043 * addresses. 1044 */ 1045 for (va = addr; va < data_end; va += PAGE_SIZE) { 1046 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1047 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1048 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1049 PTE_VALID | PTE_PS_4KB; 1050 } 1051 } 1052 1053 /**************************************************************************/ 1054 /* PMAP related */ 1055 /**************************************************************************/ 1056 1057 /* 1058 * This is called during booke_init, before the system is really initialized. 1059 */ 1060 static void 1061 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1062 { 1063 vm_paddr_t phys_kernelend; 1064 struct mem_region *mp, *mp1; 1065 int cnt, i, j; 1066 vm_paddr_t s, e, sz; 1067 vm_paddr_t physsz, hwphyssz; 1068 u_int phys_avail_count; 1069 vm_size_t kstack0_sz; 1070 vm_offset_t kernel_pdir, kstack0; 1071 vm_paddr_t kstack0_phys; 1072 void *dpcpu; 1073 1074 debugf("mmu_booke_bootstrap: entered\n"); 1075 1076 /* Set interesting system properties */ 1077 hw_direct_map = 0; 1078 elf32_nxstack = 1; 1079 1080 /* Initialize invalidation mutex */ 1081 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1082 1083 /* Read TLB0 size and associativity. */ 1084 tlb0_get_tlbconf(); 1085 1086 /* 1087 * Align kernel start and end address (kernel image). 1088 * Note that kernel end does not necessarily relate to kernsize. 1089 * kernsize is the size of the kernel that is actually mapped. 1090 */ 1091 kernstart = trunc_page(start); 1092 data_start = round_page(kernelend); 1093 data_end = data_start; 1094 1095 /* 1096 * Addresses of preloaded modules (like file systems) use 1097 * physical addresses. Make sure we relocate those into 1098 * virtual addresses. 1099 */ 1100 preload_addr_relocate = kernstart - kernload; 1101 1102 /* Allocate the dynamic per-cpu area. */ 1103 dpcpu = (void *)data_end; 1104 data_end += DPCPU_SIZE; 1105 1106 /* Allocate space for the message buffer. */ 1107 msgbufp = (struct msgbuf *)data_end; 1108 data_end += msgbufsize; 1109 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1110 data_end); 1111 1112 data_end = round_page(data_end); 1113 1114 /* Allocate space for ptbl_bufs. */ 1115 ptbl_bufs = (struct ptbl_buf *)data_end; 1116 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1117 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1118 data_end); 1119 1120 data_end = round_page(data_end); 1121 1122 /* Allocate PTE tables for kernel KVA. */ 1123 kernel_pdir = data_end; 1124 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1125 PDIR_SIZE - 1) / PDIR_SIZE; 1126 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1127 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1128 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1129 1130 debugf(" data_end: 0x%08x\n", data_end); 1131 if (data_end - kernstart > kernsize) { 1132 kernsize += tlb1_mapin_region(kernstart + kernsize, 1133 kernload + kernsize, (data_end - kernstart) - kernsize); 1134 } 1135 data_end = kernstart + kernsize; 1136 debugf(" updated data_end: 0x%08x\n", data_end); 1137 1138 /* 1139 * Clear the structures - note we can only do it safely after the 1140 * possible additional TLB1 translations are in place (above) so that 1141 * all range up to the currently calculated 'data_end' is covered. 1142 */ 1143 dpcpu_init(dpcpu, 0); 1144 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1145 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1146 1147 /*******************************************************/ 1148 /* Set the start and end of kva. */ 1149 /*******************************************************/ 1150 virtual_avail = round_page(data_end); 1151 virtual_end = VM_MAX_KERNEL_ADDRESS; 1152 1153 /* Allocate KVA space for page zero/copy operations. */ 1154 zero_page_va = virtual_avail; 1155 virtual_avail += PAGE_SIZE; 1156 zero_page_idle_va = virtual_avail; 1157 virtual_avail += PAGE_SIZE; 1158 copy_page_src_va = virtual_avail; 1159 virtual_avail += PAGE_SIZE; 1160 copy_page_dst_va = virtual_avail; 1161 virtual_avail += PAGE_SIZE; 1162 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1163 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1164 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1165 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1166 1167 /* Initialize page zero/copy mutexes. */ 1168 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1169 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1170 1171 /* Allocate KVA space for ptbl bufs. */ 1172 ptbl_buf_pool_vabase = virtual_avail; 1173 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1174 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1175 ptbl_buf_pool_vabase, virtual_avail); 1176 1177 /* Calculate corresponding physical addresses for the kernel region. */ 1178 phys_kernelend = kernload + kernsize; 1179 debugf("kernel image and allocated data:\n"); 1180 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1181 debugf(" kernstart = 0x%08x\n", kernstart); 1182 debugf(" kernsize = 0x%08x\n", kernsize); 1183 1184 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1185 panic("mmu_booke_bootstrap: phys_avail too small"); 1186 1187 /* 1188 * Remove kernel physical address range from avail regions list. Page 1189 * align all regions. Non-page aligned memory isn't very interesting 1190 * to us. Also, sort the entries for ascending addresses. 1191 */ 1192 1193 /* Retrieve phys/avail mem regions */ 1194 mem_regions(&physmem_regions, &physmem_regions_sz, 1195 &availmem_regions, &availmem_regions_sz); 1196 sz = 0; 1197 cnt = availmem_regions_sz; 1198 debugf("processing avail regions:\n"); 1199 for (mp = availmem_regions; mp->mr_size; mp++) { 1200 s = mp->mr_start; 1201 e = mp->mr_start + mp->mr_size; 1202 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1203 /* Check whether this region holds all of the kernel. */ 1204 if (s < kernload && e > phys_kernelend) { 1205 availmem_regions[cnt].mr_start = phys_kernelend; 1206 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1207 e = kernload; 1208 } 1209 /* Look whether this regions starts within the kernel. */ 1210 if (s >= kernload && s < phys_kernelend) { 1211 if (e <= phys_kernelend) 1212 goto empty; 1213 s = phys_kernelend; 1214 } 1215 /* Now look whether this region ends within the kernel. */ 1216 if (e > kernload && e <= phys_kernelend) { 1217 if (s >= kernload) 1218 goto empty; 1219 e = kernload; 1220 } 1221 /* Now page align the start and size of the region. */ 1222 s = round_page(s); 1223 e = trunc_page(e); 1224 if (e < s) 1225 e = s; 1226 sz = e - s; 1227 debugf("%09jx-%09jx = %jx\n", 1228 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1229 1230 /* Check whether some memory is left here. */ 1231 if (sz == 0) { 1232 empty: 1233 memmove(mp, mp + 1, 1234 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1235 cnt--; 1236 mp--; 1237 continue; 1238 } 1239 1240 /* Do an insertion sort. */ 1241 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1242 if (s < mp1->mr_start) 1243 break; 1244 if (mp1 < mp) { 1245 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1246 mp1->mr_start = s; 1247 mp1->mr_size = sz; 1248 } else { 1249 mp->mr_start = s; 1250 mp->mr_size = sz; 1251 } 1252 } 1253 availmem_regions_sz = cnt; 1254 1255 /*******************************************************/ 1256 /* Steal physical memory for kernel stack from the end */ 1257 /* of the first avail region */ 1258 /*******************************************************/ 1259 kstack0_sz = kstack_pages * PAGE_SIZE; 1260 kstack0_phys = availmem_regions[0].mr_start + 1261 availmem_regions[0].mr_size; 1262 kstack0_phys -= kstack0_sz; 1263 availmem_regions[0].mr_size -= kstack0_sz; 1264 1265 /*******************************************************/ 1266 /* Fill in phys_avail table, based on availmem_regions */ 1267 /*******************************************************/ 1268 phys_avail_count = 0; 1269 physsz = 0; 1270 hwphyssz = 0; 1271 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1272 1273 debugf("fill in phys_avail:\n"); 1274 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1275 1276 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1277 (uintmax_t)availmem_regions[i].mr_start, 1278 (uintmax_t)availmem_regions[i].mr_start + 1279 availmem_regions[i].mr_size, 1280 (uintmax_t)availmem_regions[i].mr_size); 1281 1282 if (hwphyssz != 0 && 1283 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1284 debugf(" hw.physmem adjust\n"); 1285 if (physsz < hwphyssz) { 1286 phys_avail[j] = availmem_regions[i].mr_start; 1287 phys_avail[j + 1] = 1288 availmem_regions[i].mr_start + 1289 hwphyssz - physsz; 1290 physsz = hwphyssz; 1291 phys_avail_count++; 1292 } 1293 break; 1294 } 1295 1296 phys_avail[j] = availmem_regions[i].mr_start; 1297 phys_avail[j + 1] = availmem_regions[i].mr_start + 1298 availmem_regions[i].mr_size; 1299 phys_avail_count++; 1300 physsz += availmem_regions[i].mr_size; 1301 } 1302 physmem = btoc(physsz); 1303 1304 /* Calculate the last available physical address. */ 1305 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1306 ; 1307 Maxmem = powerpc_btop(phys_avail[i + 1]); 1308 1309 debugf("Maxmem = 0x%08lx\n", Maxmem); 1310 debugf("phys_avail_count = %d\n", phys_avail_count); 1311 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1312 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1313 1314 /*******************************************************/ 1315 /* Initialize (statically allocated) kernel pmap. */ 1316 /*******************************************************/ 1317 PMAP_LOCK_INIT(kernel_pmap); 1318 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1319 1320 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1321 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1322 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1323 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1324 1325 kernel_pte_alloc(data_end, kernstart, kernel_pdir); 1326 for (i = 0; i < MAXCPU; i++) { 1327 kernel_pmap->pm_tid[i] = TID_KERNEL; 1328 1329 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1330 tidbusy[i][TID_KERNEL] = kernel_pmap; 1331 } 1332 1333 /* Mark kernel_pmap active on all CPUs */ 1334 CPU_FILL(&kernel_pmap->pm_active); 1335 1336 /* 1337 * Initialize the global pv list lock. 1338 */ 1339 rw_init(&pvh_global_lock, "pmap pv global"); 1340 1341 /*******************************************************/ 1342 /* Final setup */ 1343 /*******************************************************/ 1344 1345 /* Enter kstack0 into kernel map, provide guard page */ 1346 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1347 thread0.td_kstack = kstack0; 1348 thread0.td_kstack_pages = kstack_pages; 1349 1350 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1351 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1352 kstack0_phys, kstack0_phys + kstack0_sz); 1353 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1354 1355 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1356 for (i = 0; i < kstack_pages; i++) { 1357 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1358 kstack0 += PAGE_SIZE; 1359 kstack0_phys += PAGE_SIZE; 1360 } 1361 1362 pmap_bootstrapped = 1; 1363 1364 debugf("virtual_avail = %08x\n", virtual_avail); 1365 debugf("virtual_end = %08x\n", virtual_end); 1366 1367 debugf("mmu_booke_bootstrap: exit\n"); 1368 } 1369 1370 #ifdef SMP 1371 void 1372 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1373 { 1374 int i; 1375 1376 /* 1377 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1378 * have the snapshot of its contents in the s/w tlb1[] table, so use 1379 * these values directly to (re)program AP's TLB1 hardware. 1380 */ 1381 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1382 /* Skip invalid entries */ 1383 if (!(tlb1[i].mas1 & MAS1_VALID)) 1384 continue; 1385 1386 tlb1_write_entry(i); 1387 } 1388 1389 set_mas4_defaults(); 1390 } 1391 #endif 1392 1393 static void 1394 booke_pmap_init_qpages(void) 1395 { 1396 struct pcpu *pc; 1397 int i; 1398 1399 CPU_FOREACH(i) { 1400 pc = pcpu_find(i); 1401 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1402 if (pc->pc_qmap_addr == 0) 1403 panic("pmap_init_qpages: unable to allocate KVA"); 1404 } 1405 } 1406 1407 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1408 1409 /* 1410 * Get the physical page address for the given pmap/virtual address. 1411 */ 1412 static vm_paddr_t 1413 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1414 { 1415 vm_paddr_t pa; 1416 1417 PMAP_LOCK(pmap); 1418 pa = pte_vatopa(mmu, pmap, va); 1419 PMAP_UNLOCK(pmap); 1420 1421 return (pa); 1422 } 1423 1424 /* 1425 * Extract the physical page address associated with the given 1426 * kernel virtual address. 1427 */ 1428 static vm_paddr_t 1429 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1430 { 1431 int i; 1432 1433 /* Check TLB1 mappings */ 1434 for (i = 0; i < tlb1_idx; i++) { 1435 if (!(tlb1[i].mas1 & MAS1_VALID)) 1436 continue; 1437 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1438 return (tlb1[i].phys + (va - tlb1[i].virt)); 1439 } 1440 1441 return (pte_vatopa(mmu, kernel_pmap, va)); 1442 } 1443 1444 /* 1445 * Initialize the pmap module. 1446 * Called by vm_init, to initialize any structures that the pmap 1447 * system needs to map virtual memory. 1448 */ 1449 static void 1450 mmu_booke_init(mmu_t mmu) 1451 { 1452 int shpgperproc = PMAP_SHPGPERPROC; 1453 1454 /* 1455 * Initialize the address space (zone) for the pv entries. Set a 1456 * high water mark so that the system can recover from excessive 1457 * numbers of pv entries. 1458 */ 1459 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1460 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1461 1462 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1463 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1464 1465 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1466 pv_entry_high_water = 9 * (pv_entry_max / 10); 1467 1468 uma_zone_reserve_kva(pvzone, pv_entry_max); 1469 1470 /* Pre-fill pvzone with initial number of pv entries. */ 1471 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1472 1473 /* Initialize ptbl allocation. */ 1474 ptbl_init(); 1475 } 1476 1477 /* 1478 * Map a list of wired pages into kernel virtual address space. This is 1479 * intended for temporary mappings which do not need page modification or 1480 * references recorded. Existing mappings in the region are overwritten. 1481 */ 1482 static void 1483 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1484 { 1485 vm_offset_t va; 1486 1487 va = sva; 1488 while (count-- > 0) { 1489 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1490 va += PAGE_SIZE; 1491 m++; 1492 } 1493 } 1494 1495 /* 1496 * Remove page mappings from kernel virtual address space. Intended for 1497 * temporary mappings entered by mmu_booke_qenter. 1498 */ 1499 static void 1500 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1501 { 1502 vm_offset_t va; 1503 1504 va = sva; 1505 while (count-- > 0) { 1506 mmu_booke_kremove(mmu, va); 1507 va += PAGE_SIZE; 1508 } 1509 } 1510 1511 /* 1512 * Map a wired page into kernel virtual address space. 1513 */ 1514 static void 1515 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1516 { 1517 1518 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1519 } 1520 1521 static void 1522 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1523 { 1524 uint32_t flags; 1525 pte_t *pte; 1526 1527 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1528 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1529 1530 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1531 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1532 flags |= PTE_PS_4KB; 1533 1534 pte = pte_find(mmu, kernel_pmap, va); 1535 1536 mtx_lock_spin(&tlbivax_mutex); 1537 tlb_miss_lock(); 1538 1539 if (PTE_ISVALID(pte)) { 1540 1541 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1542 1543 /* Flush entry from TLB0 */ 1544 tlb0_flush_entry(va); 1545 } 1546 1547 *pte = PTE_RPN_FROM_PA(pa) | flags; 1548 1549 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1550 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1551 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1552 1553 /* Flush the real memory from the instruction cache. */ 1554 if ((flags & (PTE_I | PTE_G)) == 0) 1555 __syncicache((void *)va, PAGE_SIZE); 1556 1557 tlb_miss_unlock(); 1558 mtx_unlock_spin(&tlbivax_mutex); 1559 } 1560 1561 /* 1562 * Remove a page from kernel page table. 1563 */ 1564 static void 1565 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1566 { 1567 pte_t *pte; 1568 1569 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 1570 1571 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1572 (va <= VM_MAX_KERNEL_ADDRESS)), 1573 ("mmu_booke_kremove: invalid va")); 1574 1575 pte = pte_find(mmu, kernel_pmap, va); 1576 1577 if (!PTE_ISVALID(pte)) { 1578 1579 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1580 1581 return; 1582 } 1583 1584 mtx_lock_spin(&tlbivax_mutex); 1585 tlb_miss_lock(); 1586 1587 /* Invalidate entry in TLB0, update PTE. */ 1588 tlb0_flush_entry(va); 1589 *pte = 0; 1590 1591 tlb_miss_unlock(); 1592 mtx_unlock_spin(&tlbivax_mutex); 1593 } 1594 1595 /* 1596 * Initialize pmap associated with process 0. 1597 */ 1598 static void 1599 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1600 { 1601 1602 PMAP_LOCK_INIT(pmap); 1603 mmu_booke_pinit(mmu, pmap); 1604 PCPU_SET(curpmap, pmap); 1605 } 1606 1607 /* 1608 * Initialize a preallocated and zeroed pmap structure, 1609 * such as one in a vmspace structure. 1610 */ 1611 static void 1612 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1613 { 1614 int i; 1615 1616 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1617 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1618 1619 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1620 1621 for (i = 0; i < MAXCPU; i++) 1622 pmap->pm_tid[i] = TID_NONE; 1623 CPU_ZERO(&kernel_pmap->pm_active); 1624 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1625 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1626 TAILQ_INIT(&pmap->pm_ptbl_list); 1627 } 1628 1629 /* 1630 * Release any resources held by the given physical map. 1631 * Called when a pmap initialized by mmu_booke_pinit is being released. 1632 * Should only be called if the map contains no valid mappings. 1633 */ 1634 static void 1635 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1636 { 1637 1638 KASSERT(pmap->pm_stats.resident_count == 0, 1639 ("pmap_release: pmap resident count %ld != 0", 1640 pmap->pm_stats.resident_count)); 1641 } 1642 1643 /* 1644 * Insert the given physical page at the specified virtual address in the 1645 * target physical map with the protection requested. If specified the page 1646 * will be wired down. 1647 */ 1648 static int 1649 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1650 vm_prot_t prot, u_int flags, int8_t psind) 1651 { 1652 int error; 1653 1654 rw_wlock(&pvh_global_lock); 1655 PMAP_LOCK(pmap); 1656 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1657 rw_wunlock(&pvh_global_lock); 1658 PMAP_UNLOCK(pmap); 1659 return (error); 1660 } 1661 1662 static int 1663 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1664 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1665 { 1666 pte_t *pte; 1667 vm_paddr_t pa; 1668 uint32_t flags; 1669 int error, su, sync; 1670 1671 pa = VM_PAGE_TO_PHYS(m); 1672 su = (pmap == kernel_pmap); 1673 sync = 0; 1674 1675 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1676 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1677 // (u_int32_t)pmap, su, pmap->pm_tid, 1678 // (u_int32_t)m, va, pa, prot, flags); 1679 1680 if (su) { 1681 KASSERT(((va >= virtual_avail) && 1682 (va <= VM_MAX_KERNEL_ADDRESS)), 1683 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1684 } else { 1685 KASSERT((va <= VM_MAXUSER_ADDRESS), 1686 ("mmu_booke_enter_locked: user pmap, non user va")); 1687 } 1688 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1689 VM_OBJECT_ASSERT_LOCKED(m->object); 1690 1691 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1692 1693 /* 1694 * If there is an existing mapping, and the physical address has not 1695 * changed, must be protection or wiring change. 1696 */ 1697 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1698 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1699 1700 /* 1701 * Before actually updating pte->flags we calculate and 1702 * prepare its new value in a helper var. 1703 */ 1704 flags = *pte; 1705 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1706 1707 /* Wiring change, just update stats. */ 1708 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1709 if (!PTE_ISWIRED(pte)) { 1710 flags |= PTE_WIRED; 1711 pmap->pm_stats.wired_count++; 1712 } 1713 } else { 1714 if (PTE_ISWIRED(pte)) { 1715 flags &= ~PTE_WIRED; 1716 pmap->pm_stats.wired_count--; 1717 } 1718 } 1719 1720 if (prot & VM_PROT_WRITE) { 1721 /* Add write permissions. */ 1722 flags |= PTE_SW; 1723 if (!su) 1724 flags |= PTE_UW; 1725 1726 if ((flags & PTE_MANAGED) != 0) 1727 vm_page_aflag_set(m, PGA_WRITEABLE); 1728 } else { 1729 /* Handle modified pages, sense modify status. */ 1730 1731 /* 1732 * The PTE_MODIFIED flag could be set by underlying 1733 * TLB misses since we last read it (above), possibly 1734 * other CPUs could update it so we check in the PTE 1735 * directly rather than rely on that saved local flags 1736 * copy. 1737 */ 1738 if (PTE_ISMODIFIED(pte)) 1739 vm_page_dirty(m); 1740 } 1741 1742 if (prot & VM_PROT_EXECUTE) { 1743 flags |= PTE_SX; 1744 if (!su) 1745 flags |= PTE_UX; 1746 1747 /* 1748 * Check existing flags for execute permissions: if we 1749 * are turning execute permissions on, icache should 1750 * be flushed. 1751 */ 1752 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1753 sync++; 1754 } 1755 1756 flags &= ~PTE_REFERENCED; 1757 1758 /* 1759 * The new flags value is all calculated -- only now actually 1760 * update the PTE. 1761 */ 1762 mtx_lock_spin(&tlbivax_mutex); 1763 tlb_miss_lock(); 1764 1765 tlb0_flush_entry(va); 1766 *pte &= ~PTE_FLAGS_MASK; 1767 *pte |= flags; 1768 1769 tlb_miss_unlock(); 1770 mtx_unlock_spin(&tlbivax_mutex); 1771 1772 } else { 1773 /* 1774 * If there is an existing mapping, but it's for a different 1775 * physical address, pte_enter() will delete the old mapping. 1776 */ 1777 //if ((pte != NULL) && PTE_ISVALID(pte)) 1778 // debugf("mmu_booke_enter_locked: replace\n"); 1779 //else 1780 // debugf("mmu_booke_enter_locked: new\n"); 1781 1782 /* Now set up the flags and install the new mapping. */ 1783 flags = (PTE_SR | PTE_VALID); 1784 flags |= PTE_M; 1785 1786 if (!su) 1787 flags |= PTE_UR; 1788 1789 if (prot & VM_PROT_WRITE) { 1790 flags |= PTE_SW; 1791 if (!su) 1792 flags |= PTE_UW; 1793 1794 if ((m->oflags & VPO_UNMANAGED) == 0) 1795 vm_page_aflag_set(m, PGA_WRITEABLE); 1796 } 1797 1798 if (prot & VM_PROT_EXECUTE) { 1799 flags |= PTE_SX; 1800 if (!su) 1801 flags |= PTE_UX; 1802 } 1803 1804 /* If its wired update stats. */ 1805 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1806 flags |= PTE_WIRED; 1807 1808 error = pte_enter(mmu, pmap, m, va, flags, 1809 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1810 if (error != 0) 1811 return (KERN_RESOURCE_SHORTAGE); 1812 1813 if ((flags & PMAP_ENTER_WIRED) != 0) 1814 pmap->pm_stats.wired_count++; 1815 1816 /* Flush the real memory from the instruction cache. */ 1817 if (prot & VM_PROT_EXECUTE) 1818 sync++; 1819 } 1820 1821 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1822 __syncicache((void *)va, PAGE_SIZE); 1823 sync = 0; 1824 } 1825 1826 return (KERN_SUCCESS); 1827 } 1828 1829 /* 1830 * Maps a sequence of resident pages belonging to the same object. 1831 * The sequence begins with the given page m_start. This page is 1832 * mapped at the given virtual address start. Each subsequent page is 1833 * mapped at a virtual address that is offset from start by the same 1834 * amount as the page is offset from m_start within the object. The 1835 * last page in the sequence is the page with the largest offset from 1836 * m_start that can be mapped at a virtual address less than the given 1837 * virtual address end. Not every virtual page between start and end 1838 * is mapped; only those for which a resident page exists with the 1839 * corresponding offset from m_start are mapped. 1840 */ 1841 static void 1842 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1843 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1844 { 1845 vm_page_t m; 1846 vm_pindex_t diff, psize; 1847 1848 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1849 1850 psize = atop(end - start); 1851 m = m_start; 1852 rw_wlock(&pvh_global_lock); 1853 PMAP_LOCK(pmap); 1854 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1855 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1856 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1857 PMAP_ENTER_NOSLEEP, 0); 1858 m = TAILQ_NEXT(m, listq); 1859 } 1860 rw_wunlock(&pvh_global_lock); 1861 PMAP_UNLOCK(pmap); 1862 } 1863 1864 static void 1865 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1866 vm_prot_t prot) 1867 { 1868 1869 rw_wlock(&pvh_global_lock); 1870 PMAP_LOCK(pmap); 1871 mmu_booke_enter_locked(mmu, pmap, va, m, 1872 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1873 0); 1874 rw_wunlock(&pvh_global_lock); 1875 PMAP_UNLOCK(pmap); 1876 } 1877 1878 /* 1879 * Remove the given range of addresses from the specified map. 1880 * 1881 * It is assumed that the start and end are properly rounded to the page size. 1882 */ 1883 static void 1884 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1885 { 1886 pte_t *pte; 1887 uint8_t hold_flag; 1888 1889 int su = (pmap == kernel_pmap); 1890 1891 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1892 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1893 1894 if (su) { 1895 KASSERT(((va >= virtual_avail) && 1896 (va <= VM_MAX_KERNEL_ADDRESS)), 1897 ("mmu_booke_remove: kernel pmap, non kernel va")); 1898 } else { 1899 KASSERT((va <= VM_MAXUSER_ADDRESS), 1900 ("mmu_booke_remove: user pmap, non user va")); 1901 } 1902 1903 if (PMAP_REMOVE_DONE(pmap)) { 1904 //debugf("mmu_booke_remove: e (empty)\n"); 1905 return; 1906 } 1907 1908 hold_flag = PTBL_HOLD_FLAG(pmap); 1909 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1910 1911 rw_wlock(&pvh_global_lock); 1912 PMAP_LOCK(pmap); 1913 for (; va < endva; va += PAGE_SIZE) { 1914 pte = pte_find(mmu, pmap, va); 1915 if ((pte != NULL) && PTE_ISVALID(pte)) 1916 pte_remove(mmu, pmap, va, hold_flag); 1917 } 1918 PMAP_UNLOCK(pmap); 1919 rw_wunlock(&pvh_global_lock); 1920 1921 //debugf("mmu_booke_remove: e\n"); 1922 } 1923 1924 /* 1925 * Remove physical page from all pmaps in which it resides. 1926 */ 1927 static void 1928 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1929 { 1930 pv_entry_t pv, pvn; 1931 uint8_t hold_flag; 1932 1933 rw_wlock(&pvh_global_lock); 1934 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1935 pvn = TAILQ_NEXT(pv, pv_link); 1936 1937 PMAP_LOCK(pv->pv_pmap); 1938 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1939 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1940 PMAP_UNLOCK(pv->pv_pmap); 1941 } 1942 vm_page_aflag_clear(m, PGA_WRITEABLE); 1943 rw_wunlock(&pvh_global_lock); 1944 } 1945 1946 /* 1947 * Map a range of physical addresses into kernel virtual address space. 1948 */ 1949 static vm_offset_t 1950 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1951 vm_paddr_t pa_end, int prot) 1952 { 1953 vm_offset_t sva = *virt; 1954 vm_offset_t va = sva; 1955 1956 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1957 // sva, pa_start, pa_end); 1958 1959 while (pa_start < pa_end) { 1960 mmu_booke_kenter(mmu, va, pa_start); 1961 va += PAGE_SIZE; 1962 pa_start += PAGE_SIZE; 1963 } 1964 *virt = va; 1965 1966 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1967 return (sva); 1968 } 1969 1970 /* 1971 * The pmap must be activated before it's address space can be accessed in any 1972 * way. 1973 */ 1974 static void 1975 mmu_booke_activate(mmu_t mmu, struct thread *td) 1976 { 1977 pmap_t pmap; 1978 u_int cpuid; 1979 1980 pmap = &td->td_proc->p_vmspace->vm_pmap; 1981 1982 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1983 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1984 1985 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1986 1987 sched_pin(); 1988 1989 cpuid = PCPU_GET(cpuid); 1990 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1991 PCPU_SET(curpmap, pmap); 1992 1993 if (pmap->pm_tid[cpuid] == TID_NONE) 1994 tid_alloc(pmap); 1995 1996 /* Load PID0 register with pmap tid value. */ 1997 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1998 __asm __volatile("isync"); 1999 2000 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2001 2002 sched_unpin(); 2003 2004 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2005 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2006 } 2007 2008 /* 2009 * Deactivate the specified process's address space. 2010 */ 2011 static void 2012 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2013 { 2014 pmap_t pmap; 2015 2016 pmap = &td->td_proc->p_vmspace->vm_pmap; 2017 2018 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2019 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2020 2021 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2022 2023 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2024 PCPU_SET(curpmap, NULL); 2025 } 2026 2027 /* 2028 * Copy the range specified by src_addr/len 2029 * from the source map to the range dst_addr/len 2030 * in the destination map. 2031 * 2032 * This routine is only advisory and need not do anything. 2033 */ 2034 static void 2035 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2036 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2037 { 2038 2039 } 2040 2041 /* 2042 * Set the physical protection on the specified range of this map as requested. 2043 */ 2044 static void 2045 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2046 vm_prot_t prot) 2047 { 2048 vm_offset_t va; 2049 vm_page_t m; 2050 pte_t *pte; 2051 2052 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2053 mmu_booke_remove(mmu, pmap, sva, eva); 2054 return; 2055 } 2056 2057 if (prot & VM_PROT_WRITE) 2058 return; 2059 2060 PMAP_LOCK(pmap); 2061 for (va = sva; va < eva; va += PAGE_SIZE) { 2062 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2063 if (PTE_ISVALID(pte)) { 2064 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2065 2066 mtx_lock_spin(&tlbivax_mutex); 2067 tlb_miss_lock(); 2068 2069 /* Handle modified pages. */ 2070 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2071 vm_page_dirty(m); 2072 2073 tlb0_flush_entry(va); 2074 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2075 2076 tlb_miss_unlock(); 2077 mtx_unlock_spin(&tlbivax_mutex); 2078 } 2079 } 2080 } 2081 PMAP_UNLOCK(pmap); 2082 } 2083 2084 /* 2085 * Clear the write and modified bits in each of the given page's mappings. 2086 */ 2087 static void 2088 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2089 { 2090 pv_entry_t pv; 2091 pte_t *pte; 2092 2093 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2094 ("mmu_booke_remove_write: page %p is not managed", m)); 2095 2096 /* 2097 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2098 * set by another thread while the object is locked. Thus, 2099 * if PGA_WRITEABLE is clear, no page table entries need updating. 2100 */ 2101 VM_OBJECT_ASSERT_WLOCKED(m->object); 2102 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2103 return; 2104 rw_wlock(&pvh_global_lock); 2105 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2106 PMAP_LOCK(pv->pv_pmap); 2107 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2108 if (PTE_ISVALID(pte)) { 2109 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2110 2111 mtx_lock_spin(&tlbivax_mutex); 2112 tlb_miss_lock(); 2113 2114 /* Handle modified pages. */ 2115 if (PTE_ISMODIFIED(pte)) 2116 vm_page_dirty(m); 2117 2118 /* Flush mapping from TLB0. */ 2119 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2120 2121 tlb_miss_unlock(); 2122 mtx_unlock_spin(&tlbivax_mutex); 2123 } 2124 } 2125 PMAP_UNLOCK(pv->pv_pmap); 2126 } 2127 vm_page_aflag_clear(m, PGA_WRITEABLE); 2128 rw_wunlock(&pvh_global_lock); 2129 } 2130 2131 static void 2132 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2133 { 2134 pte_t *pte; 2135 pmap_t pmap; 2136 vm_page_t m; 2137 vm_offset_t addr; 2138 vm_paddr_t pa = 0; 2139 int active, valid; 2140 2141 va = trunc_page(va); 2142 sz = round_page(sz); 2143 2144 rw_wlock(&pvh_global_lock); 2145 pmap = PCPU_GET(curpmap); 2146 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2147 while (sz > 0) { 2148 PMAP_LOCK(pm); 2149 pte = pte_find(mmu, pm, va); 2150 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2151 if (valid) 2152 pa = PTE_PA(pte); 2153 PMAP_UNLOCK(pm); 2154 if (valid) { 2155 if (!active) { 2156 /* Create a mapping in the active pmap. */ 2157 addr = 0; 2158 m = PHYS_TO_VM_PAGE(pa); 2159 PMAP_LOCK(pmap); 2160 pte_enter(mmu, pmap, m, addr, 2161 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2162 __syncicache((void *)addr, PAGE_SIZE); 2163 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2164 PMAP_UNLOCK(pmap); 2165 } else 2166 __syncicache((void *)va, PAGE_SIZE); 2167 } 2168 va += PAGE_SIZE; 2169 sz -= PAGE_SIZE; 2170 } 2171 rw_wunlock(&pvh_global_lock); 2172 } 2173 2174 /* 2175 * Atomically extract and hold the physical page with the given 2176 * pmap and virtual address pair if that mapping permits the given 2177 * protection. 2178 */ 2179 static vm_page_t 2180 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2181 vm_prot_t prot) 2182 { 2183 pte_t *pte; 2184 vm_page_t m; 2185 uint32_t pte_wbit; 2186 vm_paddr_t pa; 2187 2188 m = NULL; 2189 pa = 0; 2190 PMAP_LOCK(pmap); 2191 retry: 2192 pte = pte_find(mmu, pmap, va); 2193 if ((pte != NULL) && PTE_ISVALID(pte)) { 2194 if (pmap == kernel_pmap) 2195 pte_wbit = PTE_SW; 2196 else 2197 pte_wbit = PTE_UW; 2198 2199 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2200 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2201 goto retry; 2202 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2203 vm_page_hold(m); 2204 } 2205 } 2206 2207 PA_UNLOCK_COND(pa); 2208 PMAP_UNLOCK(pmap); 2209 return (m); 2210 } 2211 2212 /* 2213 * Initialize a vm_page's machine-dependent fields. 2214 */ 2215 static void 2216 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2217 { 2218 2219 TAILQ_INIT(&m->md.pv_list); 2220 } 2221 2222 /* 2223 * mmu_booke_zero_page_area zeros the specified hardware page by 2224 * mapping it into virtual memory and using bzero to clear 2225 * its contents. 2226 * 2227 * off and size must reside within a single page. 2228 */ 2229 static void 2230 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2231 { 2232 vm_offset_t va; 2233 2234 /* XXX KASSERT off and size are within a single page? */ 2235 2236 mtx_lock(&zero_page_mutex); 2237 va = zero_page_va; 2238 2239 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2240 bzero((caddr_t)va + off, size); 2241 mmu_booke_kremove(mmu, va); 2242 2243 mtx_unlock(&zero_page_mutex); 2244 } 2245 2246 /* 2247 * mmu_booke_zero_page zeros the specified hardware page. 2248 */ 2249 static void 2250 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2251 { 2252 vm_offset_t off, va; 2253 2254 mtx_lock(&zero_page_mutex); 2255 va = zero_page_va; 2256 2257 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2258 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2259 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 2260 mmu_booke_kremove(mmu, va); 2261 2262 mtx_unlock(&zero_page_mutex); 2263 } 2264 2265 /* 2266 * mmu_booke_copy_page copies the specified (machine independent) page by 2267 * mapping the page into virtual memory and using memcopy to copy the page, 2268 * one machine dependent page at a time. 2269 */ 2270 static void 2271 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2272 { 2273 vm_offset_t sva, dva; 2274 2275 sva = copy_page_src_va; 2276 dva = copy_page_dst_va; 2277 2278 mtx_lock(©_page_mutex); 2279 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2280 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2281 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2282 mmu_booke_kremove(mmu, dva); 2283 mmu_booke_kremove(mmu, sva); 2284 mtx_unlock(©_page_mutex); 2285 } 2286 2287 static inline void 2288 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2289 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2290 { 2291 void *a_cp, *b_cp; 2292 vm_offset_t a_pg_offset, b_pg_offset; 2293 int cnt; 2294 2295 mtx_lock(©_page_mutex); 2296 while (xfersize > 0) { 2297 a_pg_offset = a_offset & PAGE_MASK; 2298 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2299 mmu_booke_kenter(mmu, copy_page_src_va, 2300 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2301 a_cp = (char *)copy_page_src_va + a_pg_offset; 2302 b_pg_offset = b_offset & PAGE_MASK; 2303 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2304 mmu_booke_kenter(mmu, copy_page_dst_va, 2305 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2306 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2307 bcopy(a_cp, b_cp, cnt); 2308 mmu_booke_kremove(mmu, copy_page_dst_va); 2309 mmu_booke_kremove(mmu, copy_page_src_va); 2310 a_offset += cnt; 2311 b_offset += cnt; 2312 xfersize -= cnt; 2313 } 2314 mtx_unlock(©_page_mutex); 2315 } 2316 2317 /* 2318 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2319 * into virtual memory and using bzero to clear its contents. This is intended 2320 * to be called from the vm_pagezero process only and outside of Giant. No 2321 * lock is required. 2322 */ 2323 static void 2324 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2325 { 2326 vm_offset_t va; 2327 2328 va = zero_page_idle_va; 2329 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2330 bzero((caddr_t)va, PAGE_SIZE); 2331 mmu_booke_kremove(mmu, va); 2332 } 2333 2334 static vm_offset_t 2335 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2336 { 2337 vm_paddr_t paddr; 2338 vm_offset_t qaddr; 2339 uint32_t flags; 2340 pte_t *pte; 2341 2342 paddr = VM_PAGE_TO_PHYS(m); 2343 2344 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2345 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 2346 flags |= PTE_PS_4KB; 2347 2348 critical_enter(); 2349 qaddr = PCPU_GET(qmap_addr); 2350 2351 pte = pte_find(mmu, kernel_pmap, qaddr); 2352 2353 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2354 2355 /* 2356 * XXX: tlbivax is broadcast to other cores, but qaddr should 2357 * not be present in other TLBs. Is there a better instruction 2358 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2359 */ 2360 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2361 __asm __volatile("isync; msync"); 2362 2363 *pte = PTE_RPN_FROM_PA(paddr) | flags; 2364 2365 /* Flush the real memory from the instruction cache. */ 2366 if ((flags & (PTE_I | PTE_G)) == 0) 2367 __syncicache((void *)qaddr, PAGE_SIZE); 2368 2369 return (qaddr); 2370 } 2371 2372 static void 2373 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2374 { 2375 pte_t *pte; 2376 2377 pte = pte_find(mmu, kernel_pmap, addr); 2378 2379 KASSERT(PCPU_GET(qmap_addr) == addr, 2380 ("mmu_booke_quick_remove_page: invalid address")); 2381 KASSERT(*pte != 0, 2382 ("mmu_booke_quick_remove_page: PTE not in use")); 2383 2384 *pte = 0; 2385 critical_exit(); 2386 } 2387 2388 /* 2389 * Return whether or not the specified physical page was modified 2390 * in any of physical maps. 2391 */ 2392 static boolean_t 2393 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2394 { 2395 pte_t *pte; 2396 pv_entry_t pv; 2397 boolean_t rv; 2398 2399 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2400 ("mmu_booke_is_modified: page %p is not managed", m)); 2401 rv = FALSE; 2402 2403 /* 2404 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2405 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2406 * is clear, no PTEs can be modified. 2407 */ 2408 VM_OBJECT_ASSERT_WLOCKED(m->object); 2409 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2410 return (rv); 2411 rw_wlock(&pvh_global_lock); 2412 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2413 PMAP_LOCK(pv->pv_pmap); 2414 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2415 PTE_ISVALID(pte)) { 2416 if (PTE_ISMODIFIED(pte)) 2417 rv = TRUE; 2418 } 2419 PMAP_UNLOCK(pv->pv_pmap); 2420 if (rv) 2421 break; 2422 } 2423 rw_wunlock(&pvh_global_lock); 2424 return (rv); 2425 } 2426 2427 /* 2428 * Return whether or not the specified virtual address is eligible 2429 * for prefault. 2430 */ 2431 static boolean_t 2432 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2433 { 2434 2435 return (FALSE); 2436 } 2437 2438 /* 2439 * Return whether or not the specified physical page was referenced 2440 * in any physical maps. 2441 */ 2442 static boolean_t 2443 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2444 { 2445 pte_t *pte; 2446 pv_entry_t pv; 2447 boolean_t rv; 2448 2449 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2450 ("mmu_booke_is_referenced: page %p is not managed", m)); 2451 rv = FALSE; 2452 rw_wlock(&pvh_global_lock); 2453 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2454 PMAP_LOCK(pv->pv_pmap); 2455 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2456 PTE_ISVALID(pte)) { 2457 if (PTE_ISREFERENCED(pte)) 2458 rv = TRUE; 2459 } 2460 PMAP_UNLOCK(pv->pv_pmap); 2461 if (rv) 2462 break; 2463 } 2464 rw_wunlock(&pvh_global_lock); 2465 return (rv); 2466 } 2467 2468 /* 2469 * Clear the modify bits on the specified physical page. 2470 */ 2471 static void 2472 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2473 { 2474 pte_t *pte; 2475 pv_entry_t pv; 2476 2477 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2478 ("mmu_booke_clear_modify: page %p is not managed", m)); 2479 VM_OBJECT_ASSERT_WLOCKED(m->object); 2480 KASSERT(!vm_page_xbusied(m), 2481 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2482 2483 /* 2484 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2485 * If the object containing the page is locked and the page is not 2486 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2487 */ 2488 if ((m->aflags & PGA_WRITEABLE) == 0) 2489 return; 2490 rw_wlock(&pvh_global_lock); 2491 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2492 PMAP_LOCK(pv->pv_pmap); 2493 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2494 PTE_ISVALID(pte)) { 2495 mtx_lock_spin(&tlbivax_mutex); 2496 tlb_miss_lock(); 2497 2498 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2499 tlb0_flush_entry(pv->pv_va); 2500 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2501 PTE_REFERENCED); 2502 } 2503 2504 tlb_miss_unlock(); 2505 mtx_unlock_spin(&tlbivax_mutex); 2506 } 2507 PMAP_UNLOCK(pv->pv_pmap); 2508 } 2509 rw_wunlock(&pvh_global_lock); 2510 } 2511 2512 /* 2513 * Return a count of reference bits for a page, clearing those bits. 2514 * It is not necessary for every reference bit to be cleared, but it 2515 * is necessary that 0 only be returned when there are truly no 2516 * reference bits set. 2517 * 2518 * XXX: The exact number of bits to check and clear is a matter that 2519 * should be tested and standardized at some point in the future for 2520 * optimal aging of shared pages. 2521 */ 2522 static int 2523 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2524 { 2525 pte_t *pte; 2526 pv_entry_t pv; 2527 int count; 2528 2529 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2530 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2531 count = 0; 2532 rw_wlock(&pvh_global_lock); 2533 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2534 PMAP_LOCK(pv->pv_pmap); 2535 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2536 PTE_ISVALID(pte)) { 2537 if (PTE_ISREFERENCED(pte)) { 2538 mtx_lock_spin(&tlbivax_mutex); 2539 tlb_miss_lock(); 2540 2541 tlb0_flush_entry(pv->pv_va); 2542 *pte &= ~PTE_REFERENCED; 2543 2544 tlb_miss_unlock(); 2545 mtx_unlock_spin(&tlbivax_mutex); 2546 2547 if (++count > 4) { 2548 PMAP_UNLOCK(pv->pv_pmap); 2549 break; 2550 } 2551 } 2552 } 2553 PMAP_UNLOCK(pv->pv_pmap); 2554 } 2555 rw_wunlock(&pvh_global_lock); 2556 return (count); 2557 } 2558 2559 /* 2560 * Clear the wired attribute from the mappings for the specified range of 2561 * addresses in the given pmap. Every valid mapping within that range must 2562 * have the wired attribute set. In contrast, invalid mappings cannot have 2563 * the wired attribute set, so they are ignored. 2564 * 2565 * The wired attribute of the page table entry is not a hardware feature, so 2566 * there is no need to invalidate any TLB entries. 2567 */ 2568 static void 2569 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2570 { 2571 vm_offset_t va; 2572 pte_t *pte; 2573 2574 PMAP_LOCK(pmap); 2575 for (va = sva; va < eva; va += PAGE_SIZE) { 2576 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2577 PTE_ISVALID(pte)) { 2578 if (!PTE_ISWIRED(pte)) 2579 panic("mmu_booke_unwire: pte %p isn't wired", 2580 pte); 2581 *pte &= ~PTE_WIRED; 2582 pmap->pm_stats.wired_count--; 2583 } 2584 } 2585 PMAP_UNLOCK(pmap); 2586 2587 } 2588 2589 /* 2590 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2591 * page. This count may be changed upwards or downwards in the future; it is 2592 * only necessary that true be returned for a small subset of pmaps for proper 2593 * page aging. 2594 */ 2595 static boolean_t 2596 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2597 { 2598 pv_entry_t pv; 2599 int loops; 2600 boolean_t rv; 2601 2602 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2603 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2604 loops = 0; 2605 rv = FALSE; 2606 rw_wlock(&pvh_global_lock); 2607 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2608 if (pv->pv_pmap == pmap) { 2609 rv = TRUE; 2610 break; 2611 } 2612 if (++loops >= 16) 2613 break; 2614 } 2615 rw_wunlock(&pvh_global_lock); 2616 return (rv); 2617 } 2618 2619 /* 2620 * Return the number of managed mappings to the given physical page that are 2621 * wired. 2622 */ 2623 static int 2624 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2625 { 2626 pv_entry_t pv; 2627 pte_t *pte; 2628 int count = 0; 2629 2630 if ((m->oflags & VPO_UNMANAGED) != 0) 2631 return (count); 2632 rw_wlock(&pvh_global_lock); 2633 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2634 PMAP_LOCK(pv->pv_pmap); 2635 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2636 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2637 count++; 2638 PMAP_UNLOCK(pv->pv_pmap); 2639 } 2640 rw_wunlock(&pvh_global_lock); 2641 return (count); 2642 } 2643 2644 static int 2645 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2646 { 2647 int i; 2648 vm_offset_t va; 2649 2650 /* 2651 * This currently does not work for entries that 2652 * overlap TLB1 entries. 2653 */ 2654 for (i = 0; i < tlb1_idx; i ++) { 2655 if (tlb1_iomapped(i, pa, size, &va) == 0) 2656 return (0); 2657 } 2658 2659 return (EFAULT); 2660 } 2661 2662 void 2663 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2664 { 2665 vm_paddr_t ppa; 2666 vm_offset_t ofs; 2667 vm_size_t gran; 2668 2669 /* Minidumps are based on virtual memory addresses. */ 2670 if (do_minidump) { 2671 *va = (void *)(vm_offset_t)pa; 2672 return; 2673 } 2674 2675 /* Raw physical memory dumps don't have a virtual address. */ 2676 /* We always map a 256MB page at 256M. */ 2677 gran = 256 * 1024 * 1024; 2678 ppa = pa & ~(gran - 1); 2679 ofs = pa - ppa; 2680 *va = (void *)gran; 2681 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2682 2683 if (sz > (gran - ofs)) 2684 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2685 _TLB_ENTRY_IO); 2686 } 2687 2688 void 2689 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2690 { 2691 vm_paddr_t ppa; 2692 vm_offset_t ofs; 2693 vm_size_t gran; 2694 2695 /* Minidumps are based on virtual memory addresses. */ 2696 /* Nothing to do... */ 2697 if (do_minidump) 2698 return; 2699 2700 /* Raw physical memory dumps don't have a virtual address. */ 2701 tlb1_idx--; 2702 tlb1[tlb1_idx].mas1 = 0; 2703 tlb1[tlb1_idx].mas2 = 0; 2704 tlb1[tlb1_idx].mas3 = 0; 2705 tlb1_write_entry(tlb1_idx); 2706 2707 gran = 256 * 1024 * 1024; 2708 ppa = pa & ~(gran - 1); 2709 ofs = pa - ppa; 2710 if (sz > (gran - ofs)) { 2711 tlb1_idx--; 2712 tlb1[tlb1_idx].mas1 = 0; 2713 tlb1[tlb1_idx].mas2 = 0; 2714 tlb1[tlb1_idx].mas3 = 0; 2715 tlb1_write_entry(tlb1_idx); 2716 } 2717 } 2718 2719 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2720 2721 void 2722 mmu_booke_scan_init(mmu_t mmu) 2723 { 2724 vm_offset_t va; 2725 pte_t *pte; 2726 int i; 2727 2728 if (!do_minidump) { 2729 /* Initialize phys. segments for dumpsys(). */ 2730 memset(&dump_map, 0, sizeof(dump_map)); 2731 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2732 &availmem_regions_sz); 2733 for (i = 0; i < physmem_regions_sz; i++) { 2734 dump_map[i].pa_start = physmem_regions[i].mr_start; 2735 dump_map[i].pa_size = physmem_regions[i].mr_size; 2736 } 2737 return; 2738 } 2739 2740 /* Virtual segments for minidumps: */ 2741 memset(&dump_map, 0, sizeof(dump_map)); 2742 2743 /* 1st: kernel .data and .bss. */ 2744 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2745 dump_map[0].pa_size = 2746 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2747 2748 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2749 dump_map[1].pa_start = data_start; 2750 dump_map[1].pa_size = data_end - data_start; 2751 2752 /* 3rd: kernel VM. */ 2753 va = dump_map[1].pa_start + dump_map[1].pa_size; 2754 /* Find start of next chunk (from va). */ 2755 while (va < virtual_end) { 2756 /* Don't dump the buffer cache. */ 2757 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2758 va = kmi.buffer_eva; 2759 continue; 2760 } 2761 pte = pte_find(mmu, kernel_pmap, va); 2762 if (pte != NULL && PTE_ISVALID(pte)) 2763 break; 2764 va += PAGE_SIZE; 2765 } 2766 if (va < virtual_end) { 2767 dump_map[2].pa_start = va; 2768 va += PAGE_SIZE; 2769 /* Find last page in chunk. */ 2770 while (va < virtual_end) { 2771 /* Don't run into the buffer cache. */ 2772 if (va == kmi.buffer_sva) 2773 break; 2774 pte = pte_find(mmu, kernel_pmap, va); 2775 if (pte == NULL || !PTE_ISVALID(pte)) 2776 break; 2777 va += PAGE_SIZE; 2778 } 2779 dump_map[2].pa_size = va - dump_map[2].pa_start; 2780 } 2781 } 2782 2783 /* 2784 * Map a set of physical memory pages into the kernel virtual address space. 2785 * Return a pointer to where it is mapped. This routine is intended to be used 2786 * for mapping device memory, NOT real memory. 2787 */ 2788 static void * 2789 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2790 { 2791 2792 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2793 } 2794 2795 static void * 2796 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2797 { 2798 void *res; 2799 uintptr_t va; 2800 vm_size_t sz; 2801 int i; 2802 2803 /* 2804 * Check if this is premapped in TLB1. Note: this should probably also 2805 * check whether a sequence of TLB1 entries exist that match the 2806 * requirement, but now only checks the easy case. 2807 */ 2808 if (ma == VM_MEMATTR_DEFAULT) { 2809 for (i = 0; i < tlb1_idx; i++) { 2810 if (!(tlb1[i].mas1 & MAS1_VALID)) 2811 continue; 2812 if (pa >= tlb1[i].phys && 2813 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2814 return (void *)(tlb1[i].virt + 2815 (vm_offset_t)(pa - tlb1[i].phys)); 2816 } 2817 } 2818 2819 size = roundup(size, PAGE_SIZE); 2820 2821 /* 2822 * We leave a hole for device direct mapping between the maximum user 2823 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2824 * devices are in there, just map them 1:1. If not, map them to the 2825 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2826 * addresses should be pulled from an allocator, but since we do not 2827 * ever free TLB1 entries, it is safe just to increment a counter. 2828 * Note that there isn't a lot of address space here (128 MB) and it 2829 * is not at all difficult to imagine running out, since that is a 4:1 2830 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2831 * mapped there. 2832 */ 2833 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2834 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2835 va = pa; 2836 else 2837 va = atomic_fetchadd_int(&tlb1_map_base, size); 2838 res = (void *)va; 2839 2840 do { 2841 sz = 1 << (ilog2(size) & ~1); 2842 if (va % sz != 0) { 2843 do { 2844 sz >>= 2; 2845 } while (va % sz != 0); 2846 } 2847 if (bootverbose) 2848 printf("Wiring VA=%x to PA=%jx (size=%x), " 2849 "using TLB1[%d]\n", va, (uintmax_t)pa, sz, tlb1_idx); 2850 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2851 size -= sz; 2852 pa += sz; 2853 va += sz; 2854 } while (size > 0); 2855 2856 return (res); 2857 } 2858 2859 /* 2860 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2861 */ 2862 static void 2863 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2864 { 2865 #ifdef SUPPORTS_SHRINKING_TLB1 2866 vm_offset_t base, offset; 2867 2868 /* 2869 * Unmap only if this is inside kernel virtual space. 2870 */ 2871 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2872 base = trunc_page(va); 2873 offset = va & PAGE_MASK; 2874 size = roundup(offset + size, PAGE_SIZE); 2875 kva_free(base, size); 2876 } 2877 #endif 2878 } 2879 2880 /* 2881 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2882 * specified pmap. This eliminates the blast of soft faults on process startup 2883 * and immediately after an mmap. 2884 */ 2885 static void 2886 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2887 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2888 { 2889 2890 VM_OBJECT_ASSERT_WLOCKED(object); 2891 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2892 ("mmu_booke_object_init_pt: non-device object")); 2893 } 2894 2895 /* 2896 * Perform the pmap work for mincore. 2897 */ 2898 static int 2899 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2900 vm_paddr_t *locked_pa) 2901 { 2902 2903 /* XXX: this should be implemented at some point */ 2904 return (0); 2905 } 2906 2907 static int 2908 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 2909 vm_memattr_t mode) 2910 { 2911 vm_offset_t va; 2912 pte_t *pte; 2913 int i, j; 2914 2915 /* Check TLB1 mappings */ 2916 for (i = 0; i < tlb1_idx; i++) { 2917 if (!(tlb1[i].mas1 & MAS1_VALID)) 2918 continue; 2919 if (addr >= tlb1[i].virt && addr < tlb1[i].virt + tlb1[i].size) 2920 break; 2921 } 2922 if (i < tlb1_idx) { 2923 /* Only allow full mappings to be modified for now. */ 2924 /* Validate the range. */ 2925 for (j = i, va = addr; va < addr + sz; va += tlb1[j].size, j++) { 2926 if (va != tlb1[j].virt || (sz - (va - addr) < tlb1[j].size)) 2927 return (EINVAL); 2928 } 2929 for (va = addr; va < addr + sz; va += tlb1[i].size, i++) { 2930 tlb1[i].mas2 &= ~MAS2_WIMGE_MASK; 2931 tlb1[i].mas2 |= tlb_calc_wimg(tlb1[i].phys, mode); 2932 2933 /* 2934 * Write it out to the TLB. Should really re-sync with other 2935 * cores. 2936 */ 2937 tlb1_write_entry(i); 2938 } 2939 return (0); 2940 } 2941 2942 /* Not in TLB1, try through pmap */ 2943 /* First validate the range. */ 2944 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2945 pte = pte_find(mmu, kernel_pmap, va); 2946 if (pte == NULL || !PTE_ISVALID(pte)) 2947 return (EINVAL); 2948 } 2949 2950 mtx_lock_spin(&tlbivax_mutex); 2951 tlb_miss_lock(); 2952 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2953 pte = pte_find(mmu, kernel_pmap, va); 2954 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2955 *pte |= tlb_calc_wimg(PTE_PA(pte), mode << PTE_MAS2_SHIFT); 2956 tlb0_flush_entry(va); 2957 } 2958 tlb_miss_unlock(); 2959 mtx_unlock_spin(&tlbivax_mutex); 2960 2961 return (pte_vatopa(mmu, kernel_pmap, va)); 2962 } 2963 2964 /**************************************************************************/ 2965 /* TID handling */ 2966 /**************************************************************************/ 2967 2968 /* 2969 * Allocate a TID. If necessary, steal one from someone else. 2970 * The new TID is flushed from the TLB before returning. 2971 */ 2972 static tlbtid_t 2973 tid_alloc(pmap_t pmap) 2974 { 2975 tlbtid_t tid; 2976 int thiscpu; 2977 2978 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2979 2980 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2981 2982 thiscpu = PCPU_GET(cpuid); 2983 2984 tid = PCPU_GET(tid_next); 2985 if (tid > TID_MAX) 2986 tid = TID_MIN; 2987 PCPU_SET(tid_next, tid + 1); 2988 2989 /* If we are stealing TID then clear the relevant pmap's field */ 2990 if (tidbusy[thiscpu][tid] != NULL) { 2991 2992 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2993 2994 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2995 2996 /* Flush all entries from TLB0 matching this TID. */ 2997 tid_flush(tid); 2998 } 2999 3000 tidbusy[thiscpu][tid] = pmap; 3001 pmap->pm_tid[thiscpu] = tid; 3002 __asm __volatile("msync; isync"); 3003 3004 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3005 PCPU_GET(tid_next)); 3006 3007 return (tid); 3008 } 3009 3010 /**************************************************************************/ 3011 /* TLB0 handling */ 3012 /**************************************************************************/ 3013 3014 static void 3015 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3016 uint32_t mas7) 3017 { 3018 int as; 3019 char desc[3]; 3020 tlbtid_t tid; 3021 vm_size_t size; 3022 unsigned int tsize; 3023 3024 desc[2] = '\0'; 3025 if (mas1 & MAS1_VALID) 3026 desc[0] = 'V'; 3027 else 3028 desc[0] = ' '; 3029 3030 if (mas1 & MAS1_IPROT) 3031 desc[1] = 'P'; 3032 else 3033 desc[1] = ' '; 3034 3035 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3036 tid = MAS1_GETTID(mas1); 3037 3038 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3039 size = 0; 3040 if (tsize) 3041 size = tsize2size(tsize); 3042 3043 debugf("%3d: (%s) [AS=%d] " 3044 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 3045 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3046 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 3047 } 3048 3049 /* Convert TLB0 va and way number to tlb0[] table index. */ 3050 static inline unsigned int 3051 tlb0_tableidx(vm_offset_t va, unsigned int way) 3052 { 3053 unsigned int idx; 3054 3055 idx = (way * TLB0_ENTRIES_PER_WAY); 3056 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3057 return (idx); 3058 } 3059 3060 /* 3061 * Invalidate TLB0 entry. 3062 */ 3063 static inline void 3064 tlb0_flush_entry(vm_offset_t va) 3065 { 3066 3067 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3068 3069 mtx_assert(&tlbivax_mutex, MA_OWNED); 3070 3071 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3072 __asm __volatile("isync; msync"); 3073 __asm __volatile("tlbsync; msync"); 3074 3075 CTR1(KTR_PMAP, "%s: e", __func__); 3076 } 3077 3078 /* Print out contents of the MAS registers for each TLB0 entry */ 3079 void 3080 tlb0_print_tlbentries(void) 3081 { 3082 uint32_t mas0, mas1, mas2, mas3, mas7; 3083 int entryidx, way, idx; 3084 3085 debugf("TLB0 entries:\n"); 3086 for (way = 0; way < TLB0_WAYS; way ++) 3087 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3088 3089 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3090 mtspr(SPR_MAS0, mas0); 3091 __asm __volatile("isync"); 3092 3093 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3094 mtspr(SPR_MAS2, mas2); 3095 3096 __asm __volatile("isync; tlbre"); 3097 3098 mas1 = mfspr(SPR_MAS1); 3099 mas2 = mfspr(SPR_MAS2); 3100 mas3 = mfspr(SPR_MAS3); 3101 mas7 = mfspr(SPR_MAS7); 3102 3103 idx = tlb0_tableidx(mas2, way); 3104 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3105 } 3106 } 3107 3108 /**************************************************************************/ 3109 /* TLB1 handling */ 3110 /**************************************************************************/ 3111 3112 /* 3113 * TLB1 mapping notes: 3114 * 3115 * TLB1[0] Kernel text and data. 3116 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3117 * windows, other devices mappings. 3118 */ 3119 3120 /* 3121 * Write given entry to TLB1 hardware. 3122 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3123 */ 3124 static void 3125 tlb1_write_entry(unsigned int idx) 3126 { 3127 uint32_t mas0; 3128 3129 //debugf("tlb1_write_entry: s\n"); 3130 3131 /* Select entry */ 3132 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3133 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3134 3135 mtspr(SPR_MAS0, mas0); 3136 __asm __volatile("isync"); 3137 mtspr(SPR_MAS1, tlb1[idx].mas1); 3138 __asm __volatile("isync"); 3139 mtspr(SPR_MAS2, tlb1[idx].mas2); 3140 __asm __volatile("isync"); 3141 mtspr(SPR_MAS3, tlb1[idx].mas3); 3142 __asm __volatile("isync"); 3143 switch ((mfpvr() >> 16) & 0xFFFF) { 3144 case FSL_E500mc: 3145 case FSL_E5500: 3146 mtspr(SPR_MAS8, 0); 3147 __asm __volatile("isync"); 3148 /* FALLTHROUGH */ 3149 case FSL_E500v2: 3150 mtspr(SPR_MAS7, tlb1[idx].mas7); 3151 __asm __volatile("isync"); 3152 break; 3153 default: 3154 break; 3155 } 3156 3157 __asm __volatile("tlbwe; isync; msync"); 3158 3159 //debugf("tlb1_write_entry: e\n"); 3160 } 3161 3162 /* 3163 * Return the largest uint value log such that 2^log <= num. 3164 */ 3165 static unsigned int 3166 ilog2(unsigned int num) 3167 { 3168 int lz; 3169 3170 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3171 return (31 - lz); 3172 } 3173 3174 /* 3175 * Convert TLB TSIZE value to mapped region size. 3176 */ 3177 static vm_size_t 3178 tsize2size(unsigned int tsize) 3179 { 3180 3181 /* 3182 * size = 4^tsize KB 3183 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3184 */ 3185 3186 return ((1 << (2 * tsize)) * 1024); 3187 } 3188 3189 /* 3190 * Convert region size (must be power of 4) to TLB TSIZE value. 3191 */ 3192 static unsigned int 3193 size2tsize(vm_size_t size) 3194 { 3195 3196 return (ilog2(size) / 2 - 5); 3197 } 3198 3199 /* 3200 * Register permanent kernel mapping in TLB1. 3201 * 3202 * Entries are created starting from index 0 (current free entry is 3203 * kept in tlb1_idx) and are not supposed to be invalidated. 3204 */ 3205 int 3206 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3207 uint32_t flags) 3208 { 3209 uint32_t ts, tid; 3210 int tsize, index; 3211 3212 index = atomic_fetchadd_int(&tlb1_idx, 1); 3213 if (index >= TLB1_ENTRIES) { 3214 printf("tlb1_set_entry: TLB1 full!\n"); 3215 return (-1); 3216 } 3217 3218 /* Convert size to TSIZE */ 3219 tsize = size2tsize(size); 3220 3221 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3222 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3223 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3224 3225 /* 3226 * Atomicity is preserved by the atomic increment above since nothing 3227 * is ever removed from tlb1. 3228 */ 3229 3230 tlb1[index].phys = pa; 3231 tlb1[index].virt = va; 3232 tlb1[index].size = size; 3233 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3234 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3235 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3236 3237 /* Set supervisor RWX permission bits */ 3238 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3239 tlb1[index].mas7 = (pa >> 32) & MAS7_RPN; 3240 3241 tlb1_write_entry(index); 3242 3243 /* 3244 * XXX in general TLB1 updates should be propagated between CPUs, 3245 * since current design assumes to have the same TLB1 set-up on all 3246 * cores. 3247 */ 3248 return (0); 3249 } 3250 3251 /* 3252 * Map in contiguous RAM region into the TLB1 using maximum of 3253 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3254 * 3255 * If necessary round up last entry size and return total size 3256 * used by all allocated entries. 3257 */ 3258 vm_size_t 3259 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3260 { 3261 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3262 vm_size_t mapped, pgsz, base, mask; 3263 int idx, nents; 3264 3265 /* Round up to the next 1M */ 3266 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3267 3268 mapped = 0; 3269 idx = 0; 3270 base = va; 3271 pgsz = 64*1024*1024; 3272 while (mapped < size) { 3273 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3274 while (pgsz > (size - mapped)) 3275 pgsz >>= 2; 3276 pgs[idx++] = pgsz; 3277 mapped += pgsz; 3278 } 3279 3280 /* We under-map. Correct for this. */ 3281 if (mapped < size) { 3282 while (pgs[idx - 1] == pgsz) { 3283 idx--; 3284 mapped -= pgsz; 3285 } 3286 /* XXX We may increase beyond out starting point. */ 3287 pgsz <<= 2; 3288 pgs[idx++] = pgsz; 3289 mapped += pgsz; 3290 } 3291 } 3292 3293 nents = idx; 3294 mask = pgs[0] - 1; 3295 /* Align address to the boundary */ 3296 if (va & mask) { 3297 va = (va + mask) & ~mask; 3298 pa = (pa + mask) & ~mask; 3299 } 3300 3301 for (idx = 0; idx < nents; idx++) { 3302 pgsz = pgs[idx]; 3303 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3304 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3305 pa += pgsz; 3306 va += pgsz; 3307 } 3308 3309 mapped = (va - base); 3310 #ifdef __powerpc64__ 3311 printf("mapped size 0x%016lx (wasted space 0x%16lx)\n", 3312 #else 3313 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3314 #endif 3315 mapped, mapped - size); 3316 return (mapped); 3317 } 3318 3319 /* 3320 * TLB1 initialization routine, to be called after the very first 3321 * assembler level setup done in locore.S. 3322 */ 3323 void 3324 tlb1_init() 3325 { 3326 uint32_t mas0, mas1, mas2, mas3, mas7; 3327 uint32_t tsz; 3328 int i; 3329 3330 tlb1_idx = 1; 3331 3332 tlb1_get_tlbconf(); 3333 3334 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3335 mtspr(SPR_MAS0, mas0); 3336 __asm __volatile("isync; tlbre"); 3337 3338 mas1 = mfspr(SPR_MAS1); 3339 mas2 = mfspr(SPR_MAS2); 3340 mas3 = mfspr(SPR_MAS3); 3341 mas7 = mfspr(SPR_MAS7); 3342 3343 tlb1[0].mas1 = mas1; 3344 tlb1[0].mas2 = mfspr(SPR_MAS2); 3345 tlb1[0].mas3 = mas3; 3346 tlb1[0].mas7 = mas7; 3347 tlb1[0].virt = mas2 & MAS2_EPN_MASK; 3348 tlb1[0].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3349 (mas3 & MAS3_RPN); 3350 3351 kernload = tlb1[0].phys; 3352 3353 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3354 tlb1[0].size = (tsz > 0) ? tsize2size(tsz) : 0; 3355 kernsize += tlb1[0].size; 3356 3357 #ifdef SMP 3358 bp_ntlb1s = tlb1_idx; 3359 #endif 3360 3361 /* Purge the remaining entries */ 3362 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3363 tlb1_write_entry(i); 3364 3365 /* Setup TLB miss defaults */ 3366 set_mas4_defaults(); 3367 } 3368 3369 vm_offset_t 3370 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3371 { 3372 vm_paddr_t pa_base; 3373 vm_offset_t va, sz; 3374 int i; 3375 3376 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3377 3378 for (i = 0; i < tlb1_idx; i++) { 3379 if (!(tlb1[i].mas1 & MAS1_VALID)) 3380 continue; 3381 if (pa >= tlb1[i].phys && (pa + size) <= 3382 (tlb1[i].phys + tlb1[i].size)) 3383 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3384 } 3385 3386 pa_base = rounddown(pa, PAGE_SIZE); 3387 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3388 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3389 va = tlb1_map_base + (pa - pa_base); 3390 3391 do { 3392 sz = 1 << (ilog2(size) & ~1); 3393 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3394 size -= sz; 3395 pa_base += sz; 3396 tlb1_map_base += sz; 3397 } while (size > 0); 3398 3399 #ifdef SMP 3400 bp_ntlb1s = tlb1_idx; 3401 #endif 3402 3403 return (va); 3404 } 3405 3406 /* 3407 * Setup MAS4 defaults. 3408 * These values are loaded to MAS0-2 on a TLB miss. 3409 */ 3410 static void 3411 set_mas4_defaults(void) 3412 { 3413 uint32_t mas4; 3414 3415 /* Defaults: TLB0, PID0, TSIZED=4K */ 3416 mas4 = MAS4_TLBSELD0; 3417 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3418 #ifdef SMP 3419 mas4 |= MAS4_MD; 3420 #endif 3421 mtspr(SPR_MAS4, mas4); 3422 __asm __volatile("isync"); 3423 } 3424 3425 /* 3426 * Print out contents of the MAS registers for each TLB1 entry 3427 */ 3428 void 3429 tlb1_print_tlbentries(void) 3430 { 3431 uint32_t mas0, mas1, mas2, mas3, mas7; 3432 int i; 3433 3434 debugf("TLB1 entries:\n"); 3435 for (i = 0; i < TLB1_ENTRIES; i++) { 3436 3437 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3438 mtspr(SPR_MAS0, mas0); 3439 3440 __asm __volatile("isync; tlbre"); 3441 3442 mas1 = mfspr(SPR_MAS1); 3443 mas2 = mfspr(SPR_MAS2); 3444 mas3 = mfspr(SPR_MAS3); 3445 mas7 = mfspr(SPR_MAS7); 3446 3447 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3448 } 3449 } 3450 3451 /* 3452 * Print out contents of the in-ram tlb1 table. 3453 */ 3454 void 3455 tlb1_print_entries(void) 3456 { 3457 int i; 3458 3459 debugf("tlb1[] table entries:\n"); 3460 for (i = 0; i < TLB1_ENTRIES; i++) 3461 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 3462 tlb1[i].mas7); 3463 } 3464 3465 /* 3466 * Return 0 if the physical IO range is encompassed by one of the 3467 * the TLB1 entries, otherwise return related error code. 3468 */ 3469 static int 3470 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3471 { 3472 uint32_t prot; 3473 vm_paddr_t pa_start; 3474 vm_paddr_t pa_end; 3475 unsigned int entry_tsize; 3476 vm_size_t entry_size; 3477 3478 *va = (vm_offset_t)NULL; 3479 3480 /* Skip invalid entries */ 3481 if (!(tlb1[i].mas1 & MAS1_VALID)) 3482 return (EINVAL); 3483 3484 /* 3485 * The entry must be cache-inhibited, guarded, and r/w 3486 * so it can function as an i/o page 3487 */ 3488 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3489 if (prot != (MAS2_I | MAS2_G)) 3490 return (EPERM); 3491 3492 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3493 if (prot != (MAS3_SR | MAS3_SW)) 3494 return (EPERM); 3495 3496 /* The address should be within the entry range. */ 3497 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3498 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3499 3500 entry_size = tsize2size(entry_tsize); 3501 pa_start = (((vm_paddr_t)tlb1[i].mas7 & MAS7_RPN) << 32) | 3502 (tlb1[i].mas3 & MAS3_RPN); 3503 pa_end = pa_start + entry_size; 3504 3505 if ((pa < pa_start) || ((pa + size) > pa_end)) 3506 return (ERANGE); 3507 3508 /* Return virtual address of this mapping. */ 3509 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3510 return (0); 3511 } 3512 3513 /* 3514 * Invalidate all TLB0 entries which match the given TID. Note this is 3515 * dedicated for cases when invalidations should NOT be propagated to other 3516 * CPUs. 3517 */ 3518 static void 3519 tid_flush(tlbtid_t tid) 3520 { 3521 register_t msr; 3522 uint32_t mas0, mas1, mas2; 3523 int entry, way; 3524 3525 3526 /* Don't evict kernel translations */ 3527 if (tid == TID_KERNEL) 3528 return; 3529 3530 msr = mfmsr(); 3531 __asm __volatile("wrteei 0"); 3532 3533 for (way = 0; way < TLB0_WAYS; way++) 3534 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3535 3536 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3537 mtspr(SPR_MAS0, mas0); 3538 __asm __volatile("isync"); 3539 3540 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3541 mtspr(SPR_MAS2, mas2); 3542 3543 __asm __volatile("isync; tlbre"); 3544 3545 mas1 = mfspr(SPR_MAS1); 3546 3547 if (!(mas1 & MAS1_VALID)) 3548 continue; 3549 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3550 continue; 3551 mas1 &= ~MAS1_VALID; 3552 mtspr(SPR_MAS1, mas1); 3553 __asm __volatile("isync; tlbwe; isync; msync"); 3554 } 3555 mtmsr(msr); 3556 } 3557