1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/malloc.h> 57 #include <sys/ktr.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/linker.h> 64 #include <sys/msgbuf.h> 65 #include <sys/lock.h> 66 #include <sys/mutex.h> 67 #include <sys/sched.h> 68 #include <sys/smp.h> 69 #include <sys/vmmeter.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_page.h> 73 #include <vm/vm_kern.h> 74 #include <vm/vm_pageout.h> 75 #include <vm/vm_extern.h> 76 #include <vm/vm_object.h> 77 #include <vm/vm_param.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_pager.h> 80 #include <vm/uma.h> 81 82 #include <machine/cpu.h> 83 #include <machine/pcb.h> 84 #include <machine/platform.h> 85 86 #include <machine/tlb.h> 87 #include <machine/spr.h> 88 #include <machine/vmparam.h> 89 #include <machine/md_var.h> 90 #include <machine/mmuvar.h> 91 #include <machine/pmap.h> 92 #include <machine/pte.h> 93 94 #include "mmu_if.h" 95 96 #ifdef DEBUG 97 #define debugf(fmt, args...) printf(fmt, ##args) 98 #else 99 #define debugf(fmt, args...) 100 #endif 101 102 #define TODO panic("%s: not implemented", __func__); 103 104 #include "opt_sched.h" 105 #ifndef SCHED_4BSD 106 #error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 107 #endif 108 extern struct mtx sched_lock; 109 110 extern int dumpsys_minidump; 111 112 extern unsigned char _etext[]; 113 extern unsigned char _end[]; 114 115 extern uint32_t *bootinfo; 116 117 #ifdef SMP 118 extern uint32_t kernload_ap; 119 #endif 120 121 vm_paddr_t kernload; 122 vm_offset_t kernstart; 123 vm_size_t kernsize; 124 125 /* Message buffer and tables. */ 126 static vm_offset_t data_start; 127 static vm_size_t data_end; 128 129 /* Phys/avail memory regions. */ 130 static struct mem_region *availmem_regions; 131 static int availmem_regions_sz; 132 static struct mem_region *physmem_regions; 133 static int physmem_regions_sz; 134 135 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 136 static vm_offset_t zero_page_va; 137 static struct mtx zero_page_mutex; 138 139 static struct mtx tlbivax_mutex; 140 141 /* 142 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 143 * by idle thred only, no lock required. 144 */ 145 static vm_offset_t zero_page_idle_va; 146 147 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 148 static vm_offset_t copy_page_src_va; 149 static vm_offset_t copy_page_dst_va; 150 static struct mtx copy_page_mutex; 151 152 /**************************************************************************/ 153 /* PMAP */ 154 /**************************************************************************/ 155 156 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 157 vm_prot_t, boolean_t); 158 159 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 160 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 161 162 /* 163 * If user pmap is processed with mmu_booke_remove and the resident count 164 * drops to 0, there are no more pages to remove, so we need not continue. 165 */ 166 #define PMAP_REMOVE_DONE(pmap) \ 167 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 168 169 extern void tid_flush(tlbtid_t); 170 171 /**************************************************************************/ 172 /* TLB and TID handling */ 173 /**************************************************************************/ 174 175 /* Translation ID busy table */ 176 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 177 178 /* 179 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 180 * core revisions and should be read from h/w registers during early config. 181 */ 182 uint32_t tlb0_entries; 183 uint32_t tlb0_ways; 184 uint32_t tlb0_entries_per_way; 185 186 #define TLB0_ENTRIES (tlb0_entries) 187 #define TLB0_WAYS (tlb0_ways) 188 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 189 190 #define TLB1_ENTRIES 16 191 192 /* In-ram copy of the TLB1 */ 193 static tlb_entry_t tlb1[TLB1_ENTRIES]; 194 195 /* Next free entry in the TLB1 */ 196 static unsigned int tlb1_idx; 197 198 static tlbtid_t tid_alloc(struct pmap *); 199 200 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 201 202 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 203 static void tlb1_write_entry(unsigned int); 204 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 205 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 206 207 static vm_size_t tsize2size(unsigned int); 208 static unsigned int size2tsize(vm_size_t); 209 static unsigned int ilog2(unsigned int); 210 211 static void set_mas4_defaults(void); 212 213 static inline void tlb0_flush_entry(vm_offset_t); 214 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 215 216 /**************************************************************************/ 217 /* Page table management */ 218 /**************************************************************************/ 219 220 /* Data for the pv entry allocation mechanism */ 221 static uma_zone_t pvzone; 222 static struct vm_object pvzone_obj; 223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227 #ifndef PMAP_SHPGPERPROC 228 #define PMAP_SHPGPERPROC 200 229 #endif 230 231 static void ptbl_init(void); 232 static struct ptbl_buf *ptbl_buf_alloc(void); 233 static void ptbl_buf_free(struct ptbl_buf *); 234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 237 static void ptbl_free(mmu_t, pmap_t, unsigned int); 238 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 245 246 static pv_entry_t pv_alloc(void); 247 static void pv_free(pv_entry_t); 248 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 249 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 250 251 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 252 #define PTBL_BUFS (128 * 16) 253 254 struct ptbl_buf { 255 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 256 vm_offset_t kva; /* va of mapping */ 257 }; 258 259 /* ptbl free list and a lock used for access synchronization. */ 260 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 261 static struct mtx ptbl_buf_freelist_lock; 262 263 /* Base address of kva space allocated fot ptbl bufs. */ 264 static vm_offset_t ptbl_buf_pool_vabase; 265 266 /* Pointer to ptbl_buf structures. */ 267 static struct ptbl_buf *ptbl_bufs; 268 269 void pmap_bootstrap_ap(volatile uint32_t *); 270 271 /* 272 * Kernel MMU interface 273 */ 274 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 275 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 276 static void mmu_booke_clear_reference(mmu_t, vm_page_t); 277 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 278 vm_size_t, vm_offset_t); 279 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 280 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 281 vm_prot_t, boolean_t); 282 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 283 vm_page_t, vm_prot_t); 284 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 285 vm_prot_t); 286 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 287 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 288 vm_prot_t); 289 static void mmu_booke_init(mmu_t); 290 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 291 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 292 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 293 static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 294 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 295 int); 296 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 297 vm_paddr_t *); 298 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 299 vm_object_t, vm_pindex_t, vm_size_t); 300 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 301 static void mmu_booke_page_init(mmu_t, vm_page_t); 302 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 303 static void mmu_booke_pinit(mmu_t, pmap_t); 304 static void mmu_booke_pinit0(mmu_t, pmap_t); 305 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 306 vm_prot_t); 307 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 308 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 309 static void mmu_booke_release(mmu_t, pmap_t); 310 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 311 static void mmu_booke_remove_all(mmu_t, vm_page_t); 312 static void mmu_booke_remove_write(mmu_t, vm_page_t); 313 static void mmu_booke_zero_page(mmu_t, vm_page_t); 314 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 315 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 316 static void mmu_booke_activate(mmu_t, struct thread *); 317 static void mmu_booke_deactivate(mmu_t, struct thread *); 318 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 319 static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 320 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 321 static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 322 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 323 static void mmu_booke_kremove(mmu_t, vm_offset_t); 324 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 325 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 326 vm_size_t); 327 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 328 vm_size_t, vm_size_t *); 329 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 330 vm_size_t, vm_offset_t); 331 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 332 333 static mmu_method_t mmu_booke_methods[] = { 334 /* pmap dispatcher interface */ 335 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 337 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 338 MMUMETHOD(mmu_copy, mmu_booke_copy), 339 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 340 MMUMETHOD(mmu_enter, mmu_booke_enter), 341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 343 MMUMETHOD(mmu_extract, mmu_booke_extract), 344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 345 MMUMETHOD(mmu_init, mmu_booke_init), 346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 350 MMUMETHOD(mmu_map, mmu_booke_map), 351 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 354 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 356 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 358 MMUMETHOD(mmu_protect, mmu_booke_protect), 359 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 360 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 361 MMUMETHOD(mmu_release, mmu_booke_release), 362 MMUMETHOD(mmu_remove, mmu_booke_remove), 363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 369 MMUMETHOD(mmu_activate, mmu_booke_activate), 370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 377 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 378 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 380 381 /* dumpsys() support */ 382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 385 386 { 0, 0 } 387 }; 388 389 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 390 391 static inline void 392 tlb_miss_lock(void) 393 { 394 #ifdef SMP 395 struct pcpu *pc; 396 397 if (!smp_started) 398 return; 399 400 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 401 if (pc != pcpup) { 402 403 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 404 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 405 406 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 407 ("tlb_miss_lock: tried to lock self")); 408 409 tlb_lock(pc->pc_booke_tlb_lock); 410 411 CTR1(KTR_PMAP, "%s: locked", __func__); 412 } 413 } 414 #endif 415 } 416 417 static inline void 418 tlb_miss_unlock(void) 419 { 420 #ifdef SMP 421 struct pcpu *pc; 422 423 if (!smp_started) 424 return; 425 426 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 427 if (pc != pcpup) { 428 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 429 __func__, pc->pc_cpuid); 430 431 tlb_unlock(pc->pc_booke_tlb_lock); 432 433 CTR1(KTR_PMAP, "%s: unlocked", __func__); 434 } 435 } 436 #endif 437 } 438 439 /* Return number of entries in TLB0. */ 440 static __inline void 441 tlb0_get_tlbconf(void) 442 { 443 uint32_t tlb0_cfg; 444 445 tlb0_cfg = mfspr(SPR_TLB0CFG); 446 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 447 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 448 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 449 } 450 451 /* Initialize pool of kva ptbl buffers. */ 452 static void 453 ptbl_init(void) 454 { 455 int i; 456 457 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 458 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 459 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 460 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 461 462 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 463 TAILQ_INIT(&ptbl_buf_freelist); 464 465 for (i = 0; i < PTBL_BUFS; i++) { 466 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 467 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 468 } 469 } 470 471 /* Get a ptbl_buf from the freelist. */ 472 static struct ptbl_buf * 473 ptbl_buf_alloc(void) 474 { 475 struct ptbl_buf *buf; 476 477 mtx_lock(&ptbl_buf_freelist_lock); 478 buf = TAILQ_FIRST(&ptbl_buf_freelist); 479 if (buf != NULL) 480 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 481 mtx_unlock(&ptbl_buf_freelist_lock); 482 483 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 484 485 return (buf); 486 } 487 488 /* Return ptbl buff to free pool. */ 489 static void 490 ptbl_buf_free(struct ptbl_buf *buf) 491 { 492 493 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 494 495 mtx_lock(&ptbl_buf_freelist_lock); 496 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 497 mtx_unlock(&ptbl_buf_freelist_lock); 498 } 499 500 /* 501 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 502 */ 503 static void 504 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 505 { 506 struct ptbl_buf *pbuf; 507 508 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 509 510 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 511 512 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 513 if (pbuf->kva == (vm_offset_t)ptbl) { 514 /* Remove from pmap ptbl buf list. */ 515 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 516 517 /* Free corresponding ptbl buf. */ 518 ptbl_buf_free(pbuf); 519 break; 520 } 521 } 522 523 /* Allocate page table. */ 524 static pte_t * 525 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 526 { 527 vm_page_t mtbl[PTBL_PAGES]; 528 vm_page_t m; 529 struct ptbl_buf *pbuf; 530 unsigned int pidx; 531 pte_t *ptbl; 532 int i; 533 534 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 535 (pmap == kernel_pmap), pdir_idx); 536 537 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 538 ("ptbl_alloc: invalid pdir_idx")); 539 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 540 ("pte_alloc: valid ptbl entry exists!")); 541 542 pbuf = ptbl_buf_alloc(); 543 if (pbuf == NULL) 544 panic("pte_alloc: couldn't alloc kernel virtual memory"); 545 546 ptbl = (pte_t *)pbuf->kva; 547 548 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 549 550 /* Allocate ptbl pages, this will sleep! */ 551 for (i = 0; i < PTBL_PAGES; i++) { 552 pidx = (PTBL_PAGES * pdir_idx) + i; 553 while ((m = vm_page_alloc(NULL, pidx, 554 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 555 556 PMAP_UNLOCK(pmap); 557 vm_page_unlock_queues(); 558 VM_WAIT; 559 vm_page_lock_queues(); 560 PMAP_LOCK(pmap); 561 } 562 mtbl[i] = m; 563 } 564 565 /* Map allocated pages into kernel_pmap. */ 566 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 567 568 /* Zero whole ptbl. */ 569 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 570 571 /* Add pbuf to the pmap ptbl bufs list. */ 572 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 573 574 return (ptbl); 575 } 576 577 /* Free ptbl pages and invalidate pdir entry. */ 578 static void 579 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 580 { 581 pte_t *ptbl; 582 vm_paddr_t pa; 583 vm_offset_t va; 584 vm_page_t m; 585 int i; 586 587 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 588 (pmap == kernel_pmap), pdir_idx); 589 590 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 591 ("ptbl_free: invalid pdir_idx")); 592 593 ptbl = pmap->pm_pdir[pdir_idx]; 594 595 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 596 597 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 598 599 /* 600 * Invalidate the pdir entry as soon as possible, so that other CPUs 601 * don't attempt to look up the page tables we are releasing. 602 */ 603 mtx_lock_spin(&tlbivax_mutex); 604 tlb_miss_lock(); 605 606 pmap->pm_pdir[pdir_idx] = NULL; 607 608 tlb_miss_unlock(); 609 mtx_unlock_spin(&tlbivax_mutex); 610 611 for (i = 0; i < PTBL_PAGES; i++) { 612 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 613 pa = pte_vatopa(mmu, kernel_pmap, va); 614 m = PHYS_TO_VM_PAGE(pa); 615 vm_page_free_zero(m); 616 atomic_subtract_int(&cnt.v_wire_count, 1); 617 mmu_booke_kremove(mmu, va); 618 } 619 620 ptbl_free_pmap_ptbl(pmap, ptbl); 621 } 622 623 /* 624 * Decrement ptbl pages hold count and attempt to free ptbl pages. 625 * Called when removing pte entry from ptbl. 626 * 627 * Return 1 if ptbl pages were freed. 628 */ 629 static int 630 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 631 { 632 pte_t *ptbl; 633 vm_paddr_t pa; 634 vm_page_t m; 635 int i; 636 637 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 638 (pmap == kernel_pmap), pdir_idx); 639 640 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 641 ("ptbl_unhold: invalid pdir_idx")); 642 KASSERT((pmap != kernel_pmap), 643 ("ptbl_unhold: unholding kernel ptbl!")); 644 645 ptbl = pmap->pm_pdir[pdir_idx]; 646 647 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 648 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 649 ("ptbl_unhold: non kva ptbl")); 650 651 /* decrement hold count */ 652 for (i = 0; i < PTBL_PAGES; i++) { 653 pa = pte_vatopa(mmu, kernel_pmap, 654 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 655 m = PHYS_TO_VM_PAGE(pa); 656 m->wire_count--; 657 } 658 659 /* 660 * Free ptbl pages if there are no pte etries in this ptbl. 661 * wire_count has the same value for all ptbl pages, so check the last 662 * page. 663 */ 664 if (m->wire_count == 0) { 665 ptbl_free(mmu, pmap, pdir_idx); 666 667 //debugf("ptbl_unhold: e (freed ptbl)\n"); 668 return (1); 669 } 670 671 return (0); 672 } 673 674 /* 675 * Increment hold count for ptbl pages. This routine is used when a new pte 676 * entry is being inserted into the ptbl. 677 */ 678 static void 679 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 680 { 681 vm_paddr_t pa; 682 pte_t *ptbl; 683 vm_page_t m; 684 int i; 685 686 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 687 pdir_idx); 688 689 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 690 ("ptbl_hold: invalid pdir_idx")); 691 KASSERT((pmap != kernel_pmap), 692 ("ptbl_hold: holding kernel ptbl!")); 693 694 ptbl = pmap->pm_pdir[pdir_idx]; 695 696 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 697 698 for (i = 0; i < PTBL_PAGES; i++) { 699 pa = pte_vatopa(mmu, kernel_pmap, 700 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 701 m = PHYS_TO_VM_PAGE(pa); 702 m->wire_count++; 703 } 704 } 705 706 /* Allocate pv_entry structure. */ 707 pv_entry_t 708 pv_alloc(void) 709 { 710 pv_entry_t pv; 711 712 pv_entry_count++; 713 if (pv_entry_count > pv_entry_high_water) 714 pagedaemon_wakeup(); 715 pv = uma_zalloc(pvzone, M_NOWAIT); 716 717 return (pv); 718 } 719 720 /* Free pv_entry structure. */ 721 static __inline void 722 pv_free(pv_entry_t pve) 723 { 724 725 pv_entry_count--; 726 uma_zfree(pvzone, pve); 727 } 728 729 730 /* Allocate and initialize pv_entry structure. */ 731 static void 732 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 733 { 734 pv_entry_t pve; 735 736 //int su = (pmap == kernel_pmap); 737 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 738 // (u_int32_t)pmap, va, (u_int32_t)m); 739 740 pve = pv_alloc(); 741 if (pve == NULL) 742 panic("pv_insert: no pv entries!"); 743 744 pve->pv_pmap = pmap; 745 pve->pv_va = va; 746 747 /* add to pv_list */ 748 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 749 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 750 751 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 752 753 //debugf("pv_insert: e\n"); 754 } 755 756 /* Destroy pv entry. */ 757 static void 758 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 759 { 760 pv_entry_t pve; 761 762 //int su = (pmap == kernel_pmap); 763 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 764 765 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 766 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 767 768 /* find pv entry */ 769 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 770 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 771 /* remove from pv_list */ 772 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 773 if (TAILQ_EMPTY(&m->md.pv_list)) 774 vm_page_aflag_clear(m, PGA_WRITEABLE); 775 776 /* free pv entry struct */ 777 pv_free(pve); 778 break; 779 } 780 } 781 782 //debugf("pv_remove: e\n"); 783 } 784 785 /* 786 * Clean pte entry, try to free page table page if requested. 787 * 788 * Return 1 if ptbl pages were freed, otherwise return 0. 789 */ 790 static int 791 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 792 { 793 unsigned int pdir_idx = PDIR_IDX(va); 794 unsigned int ptbl_idx = PTBL_IDX(va); 795 vm_page_t m; 796 pte_t *ptbl; 797 pte_t *pte; 798 799 //int su = (pmap == kernel_pmap); 800 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 801 // su, (u_int32_t)pmap, va, flags); 802 803 ptbl = pmap->pm_pdir[pdir_idx]; 804 KASSERT(ptbl, ("pte_remove: null ptbl")); 805 806 pte = &ptbl[ptbl_idx]; 807 808 if (pte == NULL || !PTE_ISVALID(pte)) 809 return (0); 810 811 if (PTE_ISWIRED(pte)) 812 pmap->pm_stats.wired_count--; 813 814 /* Handle managed entry. */ 815 if (PTE_ISMANAGED(pte)) { 816 /* Get vm_page_t for mapped pte. */ 817 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 818 819 if (PTE_ISMODIFIED(pte)) 820 vm_page_dirty(m); 821 822 if (PTE_ISREFERENCED(pte)) 823 vm_page_aflag_set(m, PGA_REFERENCED); 824 825 pv_remove(pmap, va, m); 826 } 827 828 mtx_lock_spin(&tlbivax_mutex); 829 tlb_miss_lock(); 830 831 tlb0_flush_entry(va); 832 pte->flags = 0; 833 pte->rpn = 0; 834 835 tlb_miss_unlock(); 836 mtx_unlock_spin(&tlbivax_mutex); 837 838 pmap->pm_stats.resident_count--; 839 840 if (flags & PTBL_UNHOLD) { 841 //debugf("pte_remove: e (unhold)\n"); 842 return (ptbl_unhold(mmu, pmap, pdir_idx)); 843 } 844 845 //debugf("pte_remove: e\n"); 846 return (0); 847 } 848 849 /* 850 * Insert PTE for a given page and virtual address. 851 */ 852 static void 853 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 854 { 855 unsigned int pdir_idx = PDIR_IDX(va); 856 unsigned int ptbl_idx = PTBL_IDX(va); 857 pte_t *ptbl, *pte; 858 859 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 860 pmap == kernel_pmap, pmap, va); 861 862 /* Get the page table pointer. */ 863 ptbl = pmap->pm_pdir[pdir_idx]; 864 865 if (ptbl == NULL) { 866 /* Allocate page table pages. */ 867 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 868 } else { 869 /* 870 * Check if there is valid mapping for requested 871 * va, if there is, remove it. 872 */ 873 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 874 if (PTE_ISVALID(pte)) { 875 pte_remove(mmu, pmap, va, PTBL_HOLD); 876 } else { 877 /* 878 * pte is not used, increment hold count 879 * for ptbl pages. 880 */ 881 if (pmap != kernel_pmap) 882 ptbl_hold(mmu, pmap, pdir_idx); 883 } 884 } 885 886 /* 887 * Insert pv_entry into pv_list for mapped page if part of managed 888 * memory. 889 */ 890 if ((m->oflags & VPO_UNMANAGED) == 0) { 891 flags |= PTE_MANAGED; 892 893 /* Create and insert pv entry. */ 894 pv_insert(pmap, va, m); 895 } 896 897 pmap->pm_stats.resident_count++; 898 899 mtx_lock_spin(&tlbivax_mutex); 900 tlb_miss_lock(); 901 902 tlb0_flush_entry(va); 903 if (pmap->pm_pdir[pdir_idx] == NULL) { 904 /* 905 * If we just allocated a new page table, hook it in 906 * the pdir. 907 */ 908 pmap->pm_pdir[pdir_idx] = ptbl; 909 } 910 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 911 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 912 pte->flags |= (PTE_VALID | flags); 913 914 tlb_miss_unlock(); 915 mtx_unlock_spin(&tlbivax_mutex); 916 } 917 918 /* Return the pa for the given pmap/va. */ 919 static vm_paddr_t 920 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 921 { 922 vm_paddr_t pa = 0; 923 pte_t *pte; 924 925 pte = pte_find(mmu, pmap, va); 926 if ((pte != NULL) && PTE_ISVALID(pte)) 927 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 928 return (pa); 929 } 930 931 /* Get a pointer to a PTE in a page table. */ 932 static pte_t * 933 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 934 { 935 unsigned int pdir_idx = PDIR_IDX(va); 936 unsigned int ptbl_idx = PTBL_IDX(va); 937 938 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 939 940 if (pmap->pm_pdir[pdir_idx]) 941 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 942 943 return (NULL); 944 } 945 946 /**************************************************************************/ 947 /* PMAP related */ 948 /**************************************************************************/ 949 950 /* 951 * This is called during booke_init, before the system is really initialized. 952 */ 953 static void 954 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 955 { 956 vm_offset_t phys_kernelend; 957 struct mem_region *mp, *mp1; 958 int cnt, i, j; 959 u_int s, e, sz; 960 u_int phys_avail_count; 961 vm_size_t physsz, hwphyssz, kstack0_sz; 962 vm_offset_t kernel_pdir, kstack0, va; 963 vm_paddr_t kstack0_phys; 964 void *dpcpu; 965 pte_t *pte; 966 967 debugf("mmu_booke_bootstrap: entered\n"); 968 969 #ifdef SMP 970 kernload_ap = kernload; 971 #endif 972 973 974 /* Initialize invalidation mutex */ 975 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 976 977 /* Read TLB0 size and associativity. */ 978 tlb0_get_tlbconf(); 979 980 /* 981 * Align kernel start and end address (kernel image). 982 * Note that kernel end does not necessarily relate to kernsize. 983 * kernsize is the size of the kernel that is actually mapped. 984 */ 985 kernstart = trunc_page(start); 986 data_start = round_page(kernelend); 987 data_end = data_start; 988 989 /* 990 * Addresses of preloaded modules (like file systems) use 991 * physical addresses. Make sure we relocate those into 992 * virtual addresses. 993 */ 994 preload_addr_relocate = kernstart - kernload; 995 996 /* Allocate the dynamic per-cpu area. */ 997 dpcpu = (void *)data_end; 998 data_end += DPCPU_SIZE; 999 1000 /* Allocate space for the message buffer. */ 1001 msgbufp = (struct msgbuf *)data_end; 1002 data_end += msgbufsize; 1003 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1004 data_end); 1005 1006 data_end = round_page(data_end); 1007 1008 /* Allocate space for ptbl_bufs. */ 1009 ptbl_bufs = (struct ptbl_buf *)data_end; 1010 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1011 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1012 data_end); 1013 1014 data_end = round_page(data_end); 1015 1016 /* Allocate PTE tables for kernel KVA. */ 1017 kernel_pdir = data_end; 1018 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1019 PDIR_SIZE - 1) / PDIR_SIZE; 1020 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1021 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1022 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1023 1024 debugf(" data_end: 0x%08x\n", data_end); 1025 if (data_end - kernstart > kernsize) { 1026 kernsize += tlb1_mapin_region(kernstart + kernsize, 1027 kernload + kernsize, (data_end - kernstart) - kernsize); 1028 } 1029 data_end = kernstart + kernsize; 1030 debugf(" updated data_end: 0x%08x\n", data_end); 1031 1032 /* 1033 * Clear the structures - note we can only do it safely after the 1034 * possible additional TLB1 translations are in place (above) so that 1035 * all range up to the currently calculated 'data_end' is covered. 1036 */ 1037 dpcpu_init(dpcpu, 0); 1038 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1039 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1040 1041 /*******************************************************/ 1042 /* Set the start and end of kva. */ 1043 /*******************************************************/ 1044 virtual_avail = round_page(data_end); 1045 virtual_end = VM_MAX_KERNEL_ADDRESS; 1046 1047 /* Allocate KVA space for page zero/copy operations. */ 1048 zero_page_va = virtual_avail; 1049 virtual_avail += PAGE_SIZE; 1050 zero_page_idle_va = virtual_avail; 1051 virtual_avail += PAGE_SIZE; 1052 copy_page_src_va = virtual_avail; 1053 virtual_avail += PAGE_SIZE; 1054 copy_page_dst_va = virtual_avail; 1055 virtual_avail += PAGE_SIZE; 1056 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1057 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1058 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1059 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1060 1061 /* Initialize page zero/copy mutexes. */ 1062 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1063 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1064 1065 /* Allocate KVA space for ptbl bufs. */ 1066 ptbl_buf_pool_vabase = virtual_avail; 1067 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1068 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1069 ptbl_buf_pool_vabase, virtual_avail); 1070 1071 /* Calculate corresponding physical addresses for the kernel region. */ 1072 phys_kernelend = kernload + kernsize; 1073 debugf("kernel image and allocated data:\n"); 1074 debugf(" kernload = 0x%08x\n", kernload); 1075 debugf(" kernstart = 0x%08x\n", kernstart); 1076 debugf(" kernsize = 0x%08x\n", kernsize); 1077 1078 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1079 panic("mmu_booke_bootstrap: phys_avail too small"); 1080 1081 /* 1082 * Remove kernel physical address range from avail regions list. Page 1083 * align all regions. Non-page aligned memory isn't very interesting 1084 * to us. Also, sort the entries for ascending addresses. 1085 */ 1086 1087 /* Retrieve phys/avail mem regions */ 1088 mem_regions(&physmem_regions, &physmem_regions_sz, 1089 &availmem_regions, &availmem_regions_sz); 1090 sz = 0; 1091 cnt = availmem_regions_sz; 1092 debugf("processing avail regions:\n"); 1093 for (mp = availmem_regions; mp->mr_size; mp++) { 1094 s = mp->mr_start; 1095 e = mp->mr_start + mp->mr_size; 1096 debugf(" %08x-%08x -> ", s, e); 1097 /* Check whether this region holds all of the kernel. */ 1098 if (s < kernload && e > phys_kernelend) { 1099 availmem_regions[cnt].mr_start = phys_kernelend; 1100 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1101 e = kernload; 1102 } 1103 /* Look whether this regions starts within the kernel. */ 1104 if (s >= kernload && s < phys_kernelend) { 1105 if (e <= phys_kernelend) 1106 goto empty; 1107 s = phys_kernelend; 1108 } 1109 /* Now look whether this region ends within the kernel. */ 1110 if (e > kernload && e <= phys_kernelend) { 1111 if (s >= kernload) 1112 goto empty; 1113 e = kernload; 1114 } 1115 /* Now page align the start and size of the region. */ 1116 s = round_page(s); 1117 e = trunc_page(e); 1118 if (e < s) 1119 e = s; 1120 sz = e - s; 1121 debugf("%08x-%08x = %x\n", s, e, sz); 1122 1123 /* Check whether some memory is left here. */ 1124 if (sz == 0) { 1125 empty: 1126 memmove(mp, mp + 1, 1127 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1128 cnt--; 1129 mp--; 1130 continue; 1131 } 1132 1133 /* Do an insertion sort. */ 1134 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1135 if (s < mp1->mr_start) 1136 break; 1137 if (mp1 < mp) { 1138 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1139 mp1->mr_start = s; 1140 mp1->mr_size = sz; 1141 } else { 1142 mp->mr_start = s; 1143 mp->mr_size = sz; 1144 } 1145 } 1146 availmem_regions_sz = cnt; 1147 1148 /*******************************************************/ 1149 /* Steal physical memory for kernel stack from the end */ 1150 /* of the first avail region */ 1151 /*******************************************************/ 1152 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1153 kstack0_phys = availmem_regions[0].mr_start + 1154 availmem_regions[0].mr_size; 1155 kstack0_phys -= kstack0_sz; 1156 availmem_regions[0].mr_size -= kstack0_sz; 1157 1158 /*******************************************************/ 1159 /* Fill in phys_avail table, based on availmem_regions */ 1160 /*******************************************************/ 1161 phys_avail_count = 0; 1162 physsz = 0; 1163 hwphyssz = 0; 1164 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1165 1166 debugf("fill in phys_avail:\n"); 1167 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1168 1169 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1170 availmem_regions[i].mr_start, 1171 availmem_regions[i].mr_start + 1172 availmem_regions[i].mr_size, 1173 availmem_regions[i].mr_size); 1174 1175 if (hwphyssz != 0 && 1176 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1177 debugf(" hw.physmem adjust\n"); 1178 if (physsz < hwphyssz) { 1179 phys_avail[j] = availmem_regions[i].mr_start; 1180 phys_avail[j + 1] = 1181 availmem_regions[i].mr_start + 1182 hwphyssz - physsz; 1183 physsz = hwphyssz; 1184 phys_avail_count++; 1185 } 1186 break; 1187 } 1188 1189 phys_avail[j] = availmem_regions[i].mr_start; 1190 phys_avail[j + 1] = availmem_regions[i].mr_start + 1191 availmem_regions[i].mr_size; 1192 phys_avail_count++; 1193 physsz += availmem_regions[i].mr_size; 1194 } 1195 physmem = btoc(physsz); 1196 1197 /* Calculate the last available physical address. */ 1198 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1199 ; 1200 Maxmem = powerpc_btop(phys_avail[i + 1]); 1201 1202 debugf("Maxmem = 0x%08lx\n", Maxmem); 1203 debugf("phys_avail_count = %d\n", phys_avail_count); 1204 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1205 physmem); 1206 1207 /*******************************************************/ 1208 /* Initialize (statically allocated) kernel pmap. */ 1209 /*******************************************************/ 1210 PMAP_LOCK_INIT(kernel_pmap); 1211 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1212 1213 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1214 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1215 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1216 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1217 1218 /* Initialize kernel pdir */ 1219 for (i = 0; i < kernel_ptbls; i++) 1220 kernel_pmap->pm_pdir[kptbl_min + i] = 1221 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1222 1223 for (i = 0; i < MAXCPU; i++) { 1224 kernel_pmap->pm_tid[i] = TID_KERNEL; 1225 1226 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1227 tidbusy[i][0] = kernel_pmap; 1228 } 1229 1230 /* 1231 * Fill in PTEs covering kernel code and data. They are not required 1232 * for address translation, as this area is covered by static TLB1 1233 * entries, but for pte_vatopa() to work correctly with kernel area 1234 * addresses. 1235 */ 1236 for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1237 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1238 pte->rpn = kernload + (va - KERNBASE); 1239 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1240 PTE_VALID; 1241 } 1242 /* Mark kernel_pmap active on all CPUs */ 1243 CPU_FILL(&kernel_pmap->pm_active); 1244 1245 /*******************************************************/ 1246 /* Final setup */ 1247 /*******************************************************/ 1248 1249 /* Enter kstack0 into kernel map, provide guard page */ 1250 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1251 thread0.td_kstack = kstack0; 1252 thread0.td_kstack_pages = KSTACK_PAGES; 1253 1254 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1255 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1256 kstack0_phys, kstack0_phys + kstack0_sz); 1257 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1258 1259 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1260 for (i = 0; i < KSTACK_PAGES; i++) { 1261 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1262 kstack0 += PAGE_SIZE; 1263 kstack0_phys += PAGE_SIZE; 1264 } 1265 1266 debugf("virtual_avail = %08x\n", virtual_avail); 1267 debugf("virtual_end = %08x\n", virtual_end); 1268 1269 debugf("mmu_booke_bootstrap: exit\n"); 1270 } 1271 1272 void 1273 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1274 { 1275 int i; 1276 1277 /* 1278 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1279 * have the snapshot of its contents in the s/w tlb1[] table, so use 1280 * these values directly to (re)program AP's TLB1 hardware. 1281 */ 1282 for (i = 0; i < tlb1_idx; i ++) { 1283 /* Skip invalid entries */ 1284 if (!(tlb1[i].mas1 & MAS1_VALID)) 1285 continue; 1286 1287 tlb1_write_entry(i); 1288 } 1289 1290 set_mas4_defaults(); 1291 } 1292 1293 /* 1294 * Get the physical page address for the given pmap/virtual address. 1295 */ 1296 static vm_paddr_t 1297 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1298 { 1299 vm_paddr_t pa; 1300 1301 PMAP_LOCK(pmap); 1302 pa = pte_vatopa(mmu, pmap, va); 1303 PMAP_UNLOCK(pmap); 1304 1305 return (pa); 1306 } 1307 1308 /* 1309 * Extract the physical page address associated with the given 1310 * kernel virtual address. 1311 */ 1312 static vm_paddr_t 1313 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1314 { 1315 1316 return (pte_vatopa(mmu, kernel_pmap, va)); 1317 } 1318 1319 /* 1320 * Initialize the pmap module. 1321 * Called by vm_init, to initialize any structures that the pmap 1322 * system needs to map virtual memory. 1323 */ 1324 static void 1325 mmu_booke_init(mmu_t mmu) 1326 { 1327 int shpgperproc = PMAP_SHPGPERPROC; 1328 1329 /* 1330 * Initialize the address space (zone) for the pv entries. Set a 1331 * high water mark so that the system can recover from excessive 1332 * numbers of pv entries. 1333 */ 1334 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1335 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1336 1337 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1338 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1339 1340 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1341 pv_entry_high_water = 9 * (pv_entry_max / 10); 1342 1343 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1344 1345 /* Pre-fill pvzone with initial number of pv entries. */ 1346 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1347 1348 /* Initialize ptbl allocation. */ 1349 ptbl_init(); 1350 } 1351 1352 /* 1353 * Map a list of wired pages into kernel virtual address space. This is 1354 * intended for temporary mappings which do not need page modification or 1355 * references recorded. Existing mappings in the region are overwritten. 1356 */ 1357 static void 1358 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1359 { 1360 vm_offset_t va; 1361 1362 va = sva; 1363 while (count-- > 0) { 1364 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1365 va += PAGE_SIZE; 1366 m++; 1367 } 1368 } 1369 1370 /* 1371 * Remove page mappings from kernel virtual address space. Intended for 1372 * temporary mappings entered by mmu_booke_qenter. 1373 */ 1374 static void 1375 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1376 { 1377 vm_offset_t va; 1378 1379 va = sva; 1380 while (count-- > 0) { 1381 mmu_booke_kremove(mmu, va); 1382 va += PAGE_SIZE; 1383 } 1384 } 1385 1386 /* 1387 * Map a wired page into kernel virtual address space. 1388 */ 1389 static void 1390 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1391 { 1392 unsigned int pdir_idx = PDIR_IDX(va); 1393 unsigned int ptbl_idx = PTBL_IDX(va); 1394 uint32_t flags; 1395 pte_t *pte; 1396 1397 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1398 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1399 1400 flags = 0; 1401 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1402 flags |= PTE_M; 1403 1404 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1405 1406 mtx_lock_spin(&tlbivax_mutex); 1407 tlb_miss_lock(); 1408 1409 if (PTE_ISVALID(pte)) { 1410 1411 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1412 1413 /* Flush entry from TLB0 */ 1414 tlb0_flush_entry(va); 1415 } 1416 1417 pte->rpn = pa & ~PTE_PA_MASK; 1418 pte->flags = flags; 1419 1420 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1421 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1422 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1423 1424 /* Flush the real memory from the instruction cache. */ 1425 if ((flags & (PTE_I | PTE_G)) == 0) { 1426 __syncicache((void *)va, PAGE_SIZE); 1427 } 1428 1429 tlb_miss_unlock(); 1430 mtx_unlock_spin(&tlbivax_mutex); 1431 } 1432 1433 /* 1434 * Remove a page from kernel page table. 1435 */ 1436 static void 1437 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1438 { 1439 unsigned int pdir_idx = PDIR_IDX(va); 1440 unsigned int ptbl_idx = PTBL_IDX(va); 1441 pte_t *pte; 1442 1443 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1444 1445 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1446 (va <= VM_MAX_KERNEL_ADDRESS)), 1447 ("mmu_booke_kremove: invalid va")); 1448 1449 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1450 1451 if (!PTE_ISVALID(pte)) { 1452 1453 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1454 1455 return; 1456 } 1457 1458 mtx_lock_spin(&tlbivax_mutex); 1459 tlb_miss_lock(); 1460 1461 /* Invalidate entry in TLB0, update PTE. */ 1462 tlb0_flush_entry(va); 1463 pte->flags = 0; 1464 pte->rpn = 0; 1465 1466 tlb_miss_unlock(); 1467 mtx_unlock_spin(&tlbivax_mutex); 1468 } 1469 1470 /* 1471 * Initialize pmap associated with process 0. 1472 */ 1473 static void 1474 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1475 { 1476 1477 mmu_booke_pinit(mmu, pmap); 1478 PCPU_SET(curpmap, pmap); 1479 } 1480 1481 /* 1482 * Initialize a preallocated and zeroed pmap structure, 1483 * such as one in a vmspace structure. 1484 */ 1485 static void 1486 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1487 { 1488 int i; 1489 1490 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1491 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1492 1493 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1494 1495 PMAP_LOCK_INIT(pmap); 1496 for (i = 0; i < MAXCPU; i++) 1497 pmap->pm_tid[i] = TID_NONE; 1498 CPU_ZERO(&kernel_pmap->pm_active); 1499 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1500 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1501 TAILQ_INIT(&pmap->pm_ptbl_list); 1502 } 1503 1504 /* 1505 * Release any resources held by the given physical map. 1506 * Called when a pmap initialized by mmu_booke_pinit is being released. 1507 * Should only be called if the map contains no valid mappings. 1508 */ 1509 static void 1510 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1511 { 1512 1513 KASSERT(pmap->pm_stats.resident_count == 0, 1514 ("pmap_release: pmap resident count %ld != 0", 1515 pmap->pm_stats.resident_count)); 1516 1517 PMAP_LOCK_DESTROY(pmap); 1518 } 1519 1520 /* 1521 * Insert the given physical page at the specified virtual address in the 1522 * target physical map with the protection requested. If specified the page 1523 * will be wired down. 1524 */ 1525 static void 1526 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1527 vm_prot_t prot, boolean_t wired) 1528 { 1529 1530 vm_page_lock_queues(); 1531 PMAP_LOCK(pmap); 1532 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1533 vm_page_unlock_queues(); 1534 PMAP_UNLOCK(pmap); 1535 } 1536 1537 static void 1538 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1539 vm_prot_t prot, boolean_t wired) 1540 { 1541 pte_t *pte; 1542 vm_paddr_t pa; 1543 uint32_t flags; 1544 int su, sync; 1545 1546 pa = VM_PAGE_TO_PHYS(m); 1547 su = (pmap == kernel_pmap); 1548 sync = 0; 1549 1550 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1551 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1552 // (u_int32_t)pmap, su, pmap->pm_tid, 1553 // (u_int32_t)m, va, pa, prot, wired); 1554 1555 if (su) { 1556 KASSERT(((va >= virtual_avail) && 1557 (va <= VM_MAX_KERNEL_ADDRESS)), 1558 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1559 } else { 1560 KASSERT((va <= VM_MAXUSER_ADDRESS), 1561 ("mmu_booke_enter_locked: user pmap, non user va")); 1562 } 1563 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1564 VM_OBJECT_LOCKED(m->object), 1565 ("mmu_booke_enter_locked: page %p is not busy", m)); 1566 1567 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1568 1569 /* 1570 * If there is an existing mapping, and the physical address has not 1571 * changed, must be protection or wiring change. 1572 */ 1573 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1574 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1575 1576 /* 1577 * Before actually updating pte->flags we calculate and 1578 * prepare its new value in a helper var. 1579 */ 1580 flags = pte->flags; 1581 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1582 1583 /* Wiring change, just update stats. */ 1584 if (wired) { 1585 if (!PTE_ISWIRED(pte)) { 1586 flags |= PTE_WIRED; 1587 pmap->pm_stats.wired_count++; 1588 } 1589 } else { 1590 if (PTE_ISWIRED(pte)) { 1591 flags &= ~PTE_WIRED; 1592 pmap->pm_stats.wired_count--; 1593 } 1594 } 1595 1596 if (prot & VM_PROT_WRITE) { 1597 /* Add write permissions. */ 1598 flags |= PTE_SW; 1599 if (!su) 1600 flags |= PTE_UW; 1601 1602 if ((flags & PTE_MANAGED) != 0) 1603 vm_page_aflag_set(m, PGA_WRITEABLE); 1604 } else { 1605 /* Handle modified pages, sense modify status. */ 1606 1607 /* 1608 * The PTE_MODIFIED flag could be set by underlying 1609 * TLB misses since we last read it (above), possibly 1610 * other CPUs could update it so we check in the PTE 1611 * directly rather than rely on that saved local flags 1612 * copy. 1613 */ 1614 if (PTE_ISMODIFIED(pte)) 1615 vm_page_dirty(m); 1616 } 1617 1618 if (prot & VM_PROT_EXECUTE) { 1619 flags |= PTE_SX; 1620 if (!su) 1621 flags |= PTE_UX; 1622 1623 /* 1624 * Check existing flags for execute permissions: if we 1625 * are turning execute permissions on, icache should 1626 * be flushed. 1627 */ 1628 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1629 sync++; 1630 } 1631 1632 flags &= ~PTE_REFERENCED; 1633 1634 /* 1635 * The new flags value is all calculated -- only now actually 1636 * update the PTE. 1637 */ 1638 mtx_lock_spin(&tlbivax_mutex); 1639 tlb_miss_lock(); 1640 1641 tlb0_flush_entry(va); 1642 pte->flags = flags; 1643 1644 tlb_miss_unlock(); 1645 mtx_unlock_spin(&tlbivax_mutex); 1646 1647 } else { 1648 /* 1649 * If there is an existing mapping, but it's for a different 1650 * physical address, pte_enter() will delete the old mapping. 1651 */ 1652 //if ((pte != NULL) && PTE_ISVALID(pte)) 1653 // debugf("mmu_booke_enter_locked: replace\n"); 1654 //else 1655 // debugf("mmu_booke_enter_locked: new\n"); 1656 1657 /* Now set up the flags and install the new mapping. */ 1658 flags = (PTE_SR | PTE_VALID); 1659 flags |= PTE_M; 1660 1661 if (!su) 1662 flags |= PTE_UR; 1663 1664 if (prot & VM_PROT_WRITE) { 1665 flags |= PTE_SW; 1666 if (!su) 1667 flags |= PTE_UW; 1668 1669 if ((m->oflags & VPO_UNMANAGED) == 0) 1670 vm_page_aflag_set(m, PGA_WRITEABLE); 1671 } 1672 1673 if (prot & VM_PROT_EXECUTE) { 1674 flags |= PTE_SX; 1675 if (!su) 1676 flags |= PTE_UX; 1677 } 1678 1679 /* If its wired update stats. */ 1680 if (wired) { 1681 pmap->pm_stats.wired_count++; 1682 flags |= PTE_WIRED; 1683 } 1684 1685 pte_enter(mmu, pmap, m, va, flags); 1686 1687 /* Flush the real memory from the instruction cache. */ 1688 if (prot & VM_PROT_EXECUTE) 1689 sync++; 1690 } 1691 1692 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1693 __syncicache((void *)va, PAGE_SIZE); 1694 sync = 0; 1695 } 1696 } 1697 1698 /* 1699 * Maps a sequence of resident pages belonging to the same object. 1700 * The sequence begins with the given page m_start. This page is 1701 * mapped at the given virtual address start. Each subsequent page is 1702 * mapped at a virtual address that is offset from start by the same 1703 * amount as the page is offset from m_start within the object. The 1704 * last page in the sequence is the page with the largest offset from 1705 * m_start that can be mapped at a virtual address less than the given 1706 * virtual address end. Not every virtual page between start and end 1707 * is mapped; only those for which a resident page exists with the 1708 * corresponding offset from m_start are mapped. 1709 */ 1710 static void 1711 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1712 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1713 { 1714 vm_page_t m; 1715 vm_pindex_t diff, psize; 1716 1717 psize = atop(end - start); 1718 m = m_start; 1719 vm_page_lock_queues(); 1720 PMAP_LOCK(pmap); 1721 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1722 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1723 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1724 m = TAILQ_NEXT(m, listq); 1725 } 1726 vm_page_unlock_queues(); 1727 PMAP_UNLOCK(pmap); 1728 } 1729 1730 static void 1731 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1732 vm_prot_t prot) 1733 { 1734 1735 vm_page_lock_queues(); 1736 PMAP_LOCK(pmap); 1737 mmu_booke_enter_locked(mmu, pmap, va, m, 1738 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1739 vm_page_unlock_queues(); 1740 PMAP_UNLOCK(pmap); 1741 } 1742 1743 /* 1744 * Remove the given range of addresses from the specified map. 1745 * 1746 * It is assumed that the start and end are properly rounded to the page size. 1747 */ 1748 static void 1749 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1750 { 1751 pte_t *pte; 1752 uint8_t hold_flag; 1753 1754 int su = (pmap == kernel_pmap); 1755 1756 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1757 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1758 1759 if (su) { 1760 KASSERT(((va >= virtual_avail) && 1761 (va <= VM_MAX_KERNEL_ADDRESS)), 1762 ("mmu_booke_remove: kernel pmap, non kernel va")); 1763 } else { 1764 KASSERT((va <= VM_MAXUSER_ADDRESS), 1765 ("mmu_booke_remove: user pmap, non user va")); 1766 } 1767 1768 if (PMAP_REMOVE_DONE(pmap)) { 1769 //debugf("mmu_booke_remove: e (empty)\n"); 1770 return; 1771 } 1772 1773 hold_flag = PTBL_HOLD_FLAG(pmap); 1774 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1775 1776 vm_page_lock_queues(); 1777 PMAP_LOCK(pmap); 1778 for (; va < endva; va += PAGE_SIZE) { 1779 pte = pte_find(mmu, pmap, va); 1780 if ((pte != NULL) && PTE_ISVALID(pte)) 1781 pte_remove(mmu, pmap, va, hold_flag); 1782 } 1783 PMAP_UNLOCK(pmap); 1784 vm_page_unlock_queues(); 1785 1786 //debugf("mmu_booke_remove: e\n"); 1787 } 1788 1789 /* 1790 * Remove physical page from all pmaps in which it resides. 1791 */ 1792 static void 1793 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1794 { 1795 pv_entry_t pv, pvn; 1796 uint8_t hold_flag; 1797 1798 vm_page_lock_queues(); 1799 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1800 pvn = TAILQ_NEXT(pv, pv_link); 1801 1802 PMAP_LOCK(pv->pv_pmap); 1803 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1804 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1805 PMAP_UNLOCK(pv->pv_pmap); 1806 } 1807 vm_page_aflag_clear(m, PGA_WRITEABLE); 1808 vm_page_unlock_queues(); 1809 } 1810 1811 /* 1812 * Map a range of physical addresses into kernel virtual address space. 1813 */ 1814 static vm_offset_t 1815 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1816 vm_offset_t pa_end, int prot) 1817 { 1818 vm_offset_t sva = *virt; 1819 vm_offset_t va = sva; 1820 1821 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1822 // sva, pa_start, pa_end); 1823 1824 while (pa_start < pa_end) { 1825 mmu_booke_kenter(mmu, va, pa_start); 1826 va += PAGE_SIZE; 1827 pa_start += PAGE_SIZE; 1828 } 1829 *virt = va; 1830 1831 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1832 return (sva); 1833 } 1834 1835 /* 1836 * The pmap must be activated before it's address space can be accessed in any 1837 * way. 1838 */ 1839 static void 1840 mmu_booke_activate(mmu_t mmu, struct thread *td) 1841 { 1842 pmap_t pmap; 1843 u_int cpuid; 1844 1845 pmap = &td->td_proc->p_vmspace->vm_pmap; 1846 1847 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1848 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1849 1850 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1851 1852 mtx_lock_spin(&sched_lock); 1853 1854 cpuid = PCPU_GET(cpuid); 1855 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1856 PCPU_SET(curpmap, pmap); 1857 1858 if (pmap->pm_tid[cpuid] == TID_NONE) 1859 tid_alloc(pmap); 1860 1861 /* Load PID0 register with pmap tid value. */ 1862 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1863 __asm __volatile("isync"); 1864 1865 mtx_unlock_spin(&sched_lock); 1866 1867 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1868 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1869 } 1870 1871 /* 1872 * Deactivate the specified process's address space. 1873 */ 1874 static void 1875 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1876 { 1877 pmap_t pmap; 1878 1879 pmap = &td->td_proc->p_vmspace->vm_pmap; 1880 1881 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1882 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1883 1884 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1885 PCPU_SET(curpmap, NULL); 1886 } 1887 1888 /* 1889 * Copy the range specified by src_addr/len 1890 * from the source map to the range dst_addr/len 1891 * in the destination map. 1892 * 1893 * This routine is only advisory and need not do anything. 1894 */ 1895 static void 1896 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1897 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1898 { 1899 1900 } 1901 1902 /* 1903 * Set the physical protection on the specified range of this map as requested. 1904 */ 1905 static void 1906 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1907 vm_prot_t prot) 1908 { 1909 vm_offset_t va; 1910 vm_page_t m; 1911 pte_t *pte; 1912 1913 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1914 mmu_booke_remove(mmu, pmap, sva, eva); 1915 return; 1916 } 1917 1918 if (prot & VM_PROT_WRITE) 1919 return; 1920 1921 vm_page_lock_queues(); 1922 PMAP_LOCK(pmap); 1923 for (va = sva; va < eva; va += PAGE_SIZE) { 1924 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1925 if (PTE_ISVALID(pte)) { 1926 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1927 1928 mtx_lock_spin(&tlbivax_mutex); 1929 tlb_miss_lock(); 1930 1931 /* Handle modified pages. */ 1932 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1933 vm_page_dirty(m); 1934 1935 tlb0_flush_entry(va); 1936 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1937 1938 tlb_miss_unlock(); 1939 mtx_unlock_spin(&tlbivax_mutex); 1940 } 1941 } 1942 } 1943 PMAP_UNLOCK(pmap); 1944 vm_page_unlock_queues(); 1945 } 1946 1947 /* 1948 * Clear the write and modified bits in each of the given page's mappings. 1949 */ 1950 static void 1951 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1952 { 1953 pv_entry_t pv; 1954 pte_t *pte; 1955 1956 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1957 ("mmu_booke_remove_write: page %p is not managed", m)); 1958 1959 /* 1960 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1961 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1962 * is clear, no page table entries need updating. 1963 */ 1964 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1965 if ((m->oflags & VPO_BUSY) == 0 && 1966 (m->aflags & PGA_WRITEABLE) == 0) 1967 return; 1968 vm_page_lock_queues(); 1969 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1970 PMAP_LOCK(pv->pv_pmap); 1971 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1972 if (PTE_ISVALID(pte)) { 1973 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1974 1975 mtx_lock_spin(&tlbivax_mutex); 1976 tlb_miss_lock(); 1977 1978 /* Handle modified pages. */ 1979 if (PTE_ISMODIFIED(pte)) 1980 vm_page_dirty(m); 1981 1982 /* Flush mapping from TLB0. */ 1983 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1984 1985 tlb_miss_unlock(); 1986 mtx_unlock_spin(&tlbivax_mutex); 1987 } 1988 } 1989 PMAP_UNLOCK(pv->pv_pmap); 1990 } 1991 vm_page_aflag_clear(m, PGA_WRITEABLE); 1992 vm_page_unlock_queues(); 1993 } 1994 1995 static void 1996 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1997 { 1998 pte_t *pte; 1999 pmap_t pmap; 2000 vm_page_t m; 2001 vm_offset_t addr; 2002 vm_paddr_t pa; 2003 int active, valid; 2004 2005 va = trunc_page(va); 2006 sz = round_page(sz); 2007 2008 vm_page_lock_queues(); 2009 pmap = PCPU_GET(curpmap); 2010 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2011 while (sz > 0) { 2012 PMAP_LOCK(pm); 2013 pte = pte_find(mmu, pm, va); 2014 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2015 if (valid) 2016 pa = PTE_PA(pte); 2017 PMAP_UNLOCK(pm); 2018 if (valid) { 2019 if (!active) { 2020 /* Create a mapping in the active pmap. */ 2021 addr = 0; 2022 m = PHYS_TO_VM_PAGE(pa); 2023 PMAP_LOCK(pmap); 2024 pte_enter(mmu, pmap, m, addr, 2025 PTE_SR | PTE_VALID | PTE_UR); 2026 __syncicache((void *)addr, PAGE_SIZE); 2027 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2028 PMAP_UNLOCK(pmap); 2029 } else 2030 __syncicache((void *)va, PAGE_SIZE); 2031 } 2032 va += PAGE_SIZE; 2033 sz -= PAGE_SIZE; 2034 } 2035 vm_page_unlock_queues(); 2036 } 2037 2038 /* 2039 * Atomically extract and hold the physical page with the given 2040 * pmap and virtual address pair if that mapping permits the given 2041 * protection. 2042 */ 2043 static vm_page_t 2044 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2045 vm_prot_t prot) 2046 { 2047 pte_t *pte; 2048 vm_page_t m; 2049 uint32_t pte_wbit; 2050 vm_paddr_t pa; 2051 2052 m = NULL; 2053 pa = 0; 2054 PMAP_LOCK(pmap); 2055 retry: 2056 pte = pte_find(mmu, pmap, va); 2057 if ((pte != NULL) && PTE_ISVALID(pte)) { 2058 if (pmap == kernel_pmap) 2059 pte_wbit = PTE_SW; 2060 else 2061 pte_wbit = PTE_UW; 2062 2063 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2064 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2065 goto retry; 2066 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2067 vm_page_hold(m); 2068 } 2069 } 2070 2071 PA_UNLOCK_COND(pa); 2072 PMAP_UNLOCK(pmap); 2073 return (m); 2074 } 2075 2076 /* 2077 * Initialize a vm_page's machine-dependent fields. 2078 */ 2079 static void 2080 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2081 { 2082 2083 TAILQ_INIT(&m->md.pv_list); 2084 } 2085 2086 /* 2087 * mmu_booke_zero_page_area zeros the specified hardware page by 2088 * mapping it into virtual memory and using bzero to clear 2089 * its contents. 2090 * 2091 * off and size must reside within a single page. 2092 */ 2093 static void 2094 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2095 { 2096 vm_offset_t va; 2097 2098 /* XXX KASSERT off and size are within a single page? */ 2099 2100 mtx_lock(&zero_page_mutex); 2101 va = zero_page_va; 2102 2103 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2104 bzero((caddr_t)va + off, size); 2105 mmu_booke_kremove(mmu, va); 2106 2107 mtx_unlock(&zero_page_mutex); 2108 } 2109 2110 /* 2111 * mmu_booke_zero_page zeros the specified hardware page. 2112 */ 2113 static void 2114 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2115 { 2116 2117 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2118 } 2119 2120 /* 2121 * mmu_booke_copy_page copies the specified (machine independent) page by 2122 * mapping the page into virtual memory and using memcopy to copy the page, 2123 * one machine dependent page at a time. 2124 */ 2125 static void 2126 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2127 { 2128 vm_offset_t sva, dva; 2129 2130 sva = copy_page_src_va; 2131 dva = copy_page_dst_va; 2132 2133 mtx_lock(©_page_mutex); 2134 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2135 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2136 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2137 mmu_booke_kremove(mmu, dva); 2138 mmu_booke_kremove(mmu, sva); 2139 mtx_unlock(©_page_mutex); 2140 } 2141 2142 /* 2143 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2144 * into virtual memory and using bzero to clear its contents. This is intended 2145 * to be called from the vm_pagezero process only and outside of Giant. No 2146 * lock is required. 2147 */ 2148 static void 2149 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2150 { 2151 vm_offset_t va; 2152 2153 va = zero_page_idle_va; 2154 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2155 bzero((caddr_t)va, PAGE_SIZE); 2156 mmu_booke_kremove(mmu, va); 2157 } 2158 2159 /* 2160 * Return whether or not the specified physical page was modified 2161 * in any of physical maps. 2162 */ 2163 static boolean_t 2164 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2165 { 2166 pte_t *pte; 2167 pv_entry_t pv; 2168 boolean_t rv; 2169 2170 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2171 ("mmu_booke_is_modified: page %p is not managed", m)); 2172 rv = FALSE; 2173 2174 /* 2175 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 2176 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2177 * is clear, no PTEs can be modified. 2178 */ 2179 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2180 if ((m->oflags & VPO_BUSY) == 0 && 2181 (m->aflags & PGA_WRITEABLE) == 0) 2182 return (rv); 2183 vm_page_lock_queues(); 2184 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2185 PMAP_LOCK(pv->pv_pmap); 2186 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2187 PTE_ISVALID(pte)) { 2188 if (PTE_ISMODIFIED(pte)) 2189 rv = TRUE; 2190 } 2191 PMAP_UNLOCK(pv->pv_pmap); 2192 if (rv) 2193 break; 2194 } 2195 vm_page_unlock_queues(); 2196 return (rv); 2197 } 2198 2199 /* 2200 * Return whether or not the specified virtual address is eligible 2201 * for prefault. 2202 */ 2203 static boolean_t 2204 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2205 { 2206 2207 return (FALSE); 2208 } 2209 2210 /* 2211 * Return whether or not the specified physical page was referenced 2212 * in any physical maps. 2213 */ 2214 static boolean_t 2215 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2216 { 2217 pte_t *pte; 2218 pv_entry_t pv; 2219 boolean_t rv; 2220 2221 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2222 ("mmu_booke_is_referenced: page %p is not managed", m)); 2223 rv = FALSE; 2224 vm_page_lock_queues(); 2225 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2226 PMAP_LOCK(pv->pv_pmap); 2227 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2228 PTE_ISVALID(pte)) { 2229 if (PTE_ISREFERENCED(pte)) 2230 rv = TRUE; 2231 } 2232 PMAP_UNLOCK(pv->pv_pmap); 2233 if (rv) 2234 break; 2235 } 2236 vm_page_unlock_queues(); 2237 return (rv); 2238 } 2239 2240 /* 2241 * Clear the modify bits on the specified physical page. 2242 */ 2243 static void 2244 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2245 { 2246 pte_t *pte; 2247 pv_entry_t pv; 2248 2249 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2250 ("mmu_booke_clear_modify: page %p is not managed", m)); 2251 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2252 KASSERT((m->oflags & VPO_BUSY) == 0, 2253 ("mmu_booke_clear_modify: page %p is busy", m)); 2254 2255 /* 2256 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2257 * If the object containing the page is locked and the page is not 2258 * VPO_BUSY, then PG_AWRITEABLE cannot be concurrently set. 2259 */ 2260 if ((m->aflags & PGA_WRITEABLE) == 0) 2261 return; 2262 vm_page_lock_queues(); 2263 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2264 PMAP_LOCK(pv->pv_pmap); 2265 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2266 PTE_ISVALID(pte)) { 2267 mtx_lock_spin(&tlbivax_mutex); 2268 tlb_miss_lock(); 2269 2270 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2271 tlb0_flush_entry(pv->pv_va); 2272 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2273 PTE_REFERENCED); 2274 } 2275 2276 tlb_miss_unlock(); 2277 mtx_unlock_spin(&tlbivax_mutex); 2278 } 2279 PMAP_UNLOCK(pv->pv_pmap); 2280 } 2281 vm_page_unlock_queues(); 2282 } 2283 2284 /* 2285 * Return a count of reference bits for a page, clearing those bits. 2286 * It is not necessary for every reference bit to be cleared, but it 2287 * is necessary that 0 only be returned when there are truly no 2288 * reference bits set. 2289 * 2290 * XXX: The exact number of bits to check and clear is a matter that 2291 * should be tested and standardized at some point in the future for 2292 * optimal aging of shared pages. 2293 */ 2294 static int 2295 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2296 { 2297 pte_t *pte; 2298 pv_entry_t pv; 2299 int count; 2300 2301 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2302 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2303 count = 0; 2304 vm_page_lock_queues(); 2305 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2306 PMAP_LOCK(pv->pv_pmap); 2307 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2308 PTE_ISVALID(pte)) { 2309 if (PTE_ISREFERENCED(pte)) { 2310 mtx_lock_spin(&tlbivax_mutex); 2311 tlb_miss_lock(); 2312 2313 tlb0_flush_entry(pv->pv_va); 2314 pte->flags &= ~PTE_REFERENCED; 2315 2316 tlb_miss_unlock(); 2317 mtx_unlock_spin(&tlbivax_mutex); 2318 2319 if (++count > 4) { 2320 PMAP_UNLOCK(pv->pv_pmap); 2321 break; 2322 } 2323 } 2324 } 2325 PMAP_UNLOCK(pv->pv_pmap); 2326 } 2327 vm_page_unlock_queues(); 2328 return (count); 2329 } 2330 2331 /* 2332 * Clear the reference bit on the specified physical page. 2333 */ 2334 static void 2335 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2336 { 2337 pte_t *pte; 2338 pv_entry_t pv; 2339 2340 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2341 ("mmu_booke_clear_reference: page %p is not managed", m)); 2342 vm_page_lock_queues(); 2343 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2344 PMAP_LOCK(pv->pv_pmap); 2345 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2346 PTE_ISVALID(pte)) { 2347 if (PTE_ISREFERENCED(pte)) { 2348 mtx_lock_spin(&tlbivax_mutex); 2349 tlb_miss_lock(); 2350 2351 tlb0_flush_entry(pv->pv_va); 2352 pte->flags &= ~PTE_REFERENCED; 2353 2354 tlb_miss_unlock(); 2355 mtx_unlock_spin(&tlbivax_mutex); 2356 } 2357 } 2358 PMAP_UNLOCK(pv->pv_pmap); 2359 } 2360 vm_page_unlock_queues(); 2361 } 2362 2363 /* 2364 * Change wiring attribute for a map/virtual-address pair. 2365 */ 2366 static void 2367 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2368 { 2369 pte_t *pte; 2370 2371 PMAP_LOCK(pmap); 2372 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2373 if (wired) { 2374 if (!PTE_ISWIRED(pte)) { 2375 pte->flags |= PTE_WIRED; 2376 pmap->pm_stats.wired_count++; 2377 } 2378 } else { 2379 if (PTE_ISWIRED(pte)) { 2380 pte->flags &= ~PTE_WIRED; 2381 pmap->pm_stats.wired_count--; 2382 } 2383 } 2384 } 2385 PMAP_UNLOCK(pmap); 2386 } 2387 2388 /* 2389 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2390 * page. This count may be changed upwards or downwards in the future; it is 2391 * only necessary that true be returned for a small subset of pmaps for proper 2392 * page aging. 2393 */ 2394 static boolean_t 2395 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2396 { 2397 pv_entry_t pv; 2398 int loops; 2399 boolean_t rv; 2400 2401 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2402 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2403 loops = 0; 2404 rv = FALSE; 2405 vm_page_lock_queues(); 2406 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2407 if (pv->pv_pmap == pmap) { 2408 rv = TRUE; 2409 break; 2410 } 2411 if (++loops >= 16) 2412 break; 2413 } 2414 vm_page_unlock_queues(); 2415 return (rv); 2416 } 2417 2418 /* 2419 * Return the number of managed mappings to the given physical page that are 2420 * wired. 2421 */ 2422 static int 2423 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2424 { 2425 pv_entry_t pv; 2426 pte_t *pte; 2427 int count = 0; 2428 2429 if ((m->oflags & VPO_UNMANAGED) != 0) 2430 return (count); 2431 vm_page_lock_queues(); 2432 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2433 PMAP_LOCK(pv->pv_pmap); 2434 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2435 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2436 count++; 2437 PMAP_UNLOCK(pv->pv_pmap); 2438 } 2439 vm_page_unlock_queues(); 2440 return (count); 2441 } 2442 2443 static int 2444 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2445 { 2446 int i; 2447 vm_offset_t va; 2448 2449 /* 2450 * This currently does not work for entries that 2451 * overlap TLB1 entries. 2452 */ 2453 for (i = 0; i < tlb1_idx; i ++) { 2454 if (tlb1_iomapped(i, pa, size, &va) == 0) 2455 return (0); 2456 } 2457 2458 return (EFAULT); 2459 } 2460 2461 vm_offset_t 2462 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2463 vm_size_t *sz) 2464 { 2465 vm_paddr_t pa, ppa; 2466 vm_offset_t va; 2467 vm_size_t gran; 2468 2469 /* Raw physical memory dumps don't have a virtual address. */ 2470 if (md->md_vaddr == ~0UL) { 2471 /* We always map a 256MB page at 256M. */ 2472 gran = 256 * 1024 * 1024; 2473 pa = md->md_paddr + ofs; 2474 ppa = pa & ~(gran - 1); 2475 ofs = pa - ppa; 2476 va = gran; 2477 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2478 if (*sz > (gran - ofs)) 2479 *sz = gran - ofs; 2480 return (va + ofs); 2481 } 2482 2483 /* Minidumps are based on virtual memory addresses. */ 2484 va = md->md_vaddr + ofs; 2485 if (va >= kernstart + kernsize) { 2486 gran = PAGE_SIZE - (va & PAGE_MASK); 2487 if (*sz > gran) 2488 *sz = gran; 2489 } 2490 return (va); 2491 } 2492 2493 void 2494 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2495 vm_offset_t va) 2496 { 2497 2498 /* Raw physical memory dumps don't have a virtual address. */ 2499 if (md->md_vaddr == ~0UL) { 2500 tlb1_idx--; 2501 tlb1[tlb1_idx].mas1 = 0; 2502 tlb1[tlb1_idx].mas2 = 0; 2503 tlb1[tlb1_idx].mas3 = 0; 2504 tlb1_write_entry(tlb1_idx); 2505 return; 2506 } 2507 2508 /* Minidumps are based on virtual memory addresses. */ 2509 /* Nothing to do... */ 2510 } 2511 2512 struct pmap_md * 2513 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2514 { 2515 static struct pmap_md md; 2516 pte_t *pte; 2517 vm_offset_t va; 2518 2519 if (dumpsys_minidump) { 2520 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2521 if (prev == NULL) { 2522 /* 1st: kernel .data and .bss. */ 2523 md.md_index = 1; 2524 md.md_vaddr = trunc_page((uintptr_t)_etext); 2525 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2526 return (&md); 2527 } 2528 switch (prev->md_index) { 2529 case 1: 2530 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2531 md.md_index = 2; 2532 md.md_vaddr = data_start; 2533 md.md_size = data_end - data_start; 2534 break; 2535 case 2: 2536 /* 3rd: kernel VM. */ 2537 va = prev->md_vaddr + prev->md_size; 2538 /* Find start of next chunk (from va). */ 2539 while (va < virtual_end) { 2540 /* Don't dump the buffer cache. */ 2541 if (va >= kmi.buffer_sva && 2542 va < kmi.buffer_eva) { 2543 va = kmi.buffer_eva; 2544 continue; 2545 } 2546 pte = pte_find(mmu, kernel_pmap, va); 2547 if (pte != NULL && PTE_ISVALID(pte)) 2548 break; 2549 va += PAGE_SIZE; 2550 } 2551 if (va < virtual_end) { 2552 md.md_vaddr = va; 2553 va += PAGE_SIZE; 2554 /* Find last page in chunk. */ 2555 while (va < virtual_end) { 2556 /* Don't run into the buffer cache. */ 2557 if (va == kmi.buffer_sva) 2558 break; 2559 pte = pte_find(mmu, kernel_pmap, va); 2560 if (pte == NULL || !PTE_ISVALID(pte)) 2561 break; 2562 va += PAGE_SIZE; 2563 } 2564 md.md_size = va - md.md_vaddr; 2565 break; 2566 } 2567 md.md_index = 3; 2568 /* FALLTHROUGH */ 2569 default: 2570 return (NULL); 2571 } 2572 } else { /* minidumps */ 2573 mem_regions(&physmem_regions, &physmem_regions_sz, 2574 &availmem_regions, &availmem_regions_sz); 2575 2576 if (prev == NULL) { 2577 /* first physical chunk. */ 2578 md.md_paddr = physmem_regions[0].mr_start; 2579 md.md_size = physmem_regions[0].mr_size; 2580 md.md_vaddr = ~0UL; 2581 md.md_index = 1; 2582 } else if (md.md_index < physmem_regions_sz) { 2583 md.md_paddr = physmem_regions[md.md_index].mr_start; 2584 md.md_size = physmem_regions[md.md_index].mr_size; 2585 md.md_vaddr = ~0UL; 2586 md.md_index++; 2587 } else { 2588 /* There's no next physical chunk. */ 2589 return (NULL); 2590 } 2591 } 2592 2593 return (&md); 2594 } 2595 2596 /* 2597 * Map a set of physical memory pages into the kernel virtual address space. 2598 * Return a pointer to where it is mapped. This routine is intended to be used 2599 * for mapping device memory, NOT real memory. 2600 */ 2601 static void * 2602 mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2603 { 2604 void *res; 2605 uintptr_t va; 2606 vm_size_t sz; 2607 2608 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2609 res = (void *)va; 2610 2611 do { 2612 sz = 1 << (ilog2(size) & ~1); 2613 if (bootverbose) 2614 printf("Wiring VA=%x to PA=%x (size=%x), " 2615 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2616 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2617 size -= sz; 2618 pa += sz; 2619 va += sz; 2620 } while (size > 0); 2621 2622 return (res); 2623 } 2624 2625 /* 2626 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2627 */ 2628 static void 2629 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2630 { 2631 vm_offset_t base, offset; 2632 2633 /* 2634 * Unmap only if this is inside kernel virtual space. 2635 */ 2636 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2637 base = trunc_page(va); 2638 offset = va & PAGE_MASK; 2639 size = roundup(offset + size, PAGE_SIZE); 2640 kmem_free(kernel_map, base, size); 2641 } 2642 } 2643 2644 /* 2645 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2646 * specified pmap. This eliminates the blast of soft faults on process startup 2647 * and immediately after an mmap. 2648 */ 2649 static void 2650 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2651 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2652 { 2653 2654 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2655 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2656 ("mmu_booke_object_init_pt: non-device object")); 2657 } 2658 2659 /* 2660 * Perform the pmap work for mincore. 2661 */ 2662 static int 2663 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2664 vm_paddr_t *locked_pa) 2665 { 2666 2667 TODO; 2668 return (0); 2669 } 2670 2671 /**************************************************************************/ 2672 /* TID handling */ 2673 /**************************************************************************/ 2674 2675 /* 2676 * Allocate a TID. If necessary, steal one from someone else. 2677 * The new TID is flushed from the TLB before returning. 2678 */ 2679 static tlbtid_t 2680 tid_alloc(pmap_t pmap) 2681 { 2682 tlbtid_t tid; 2683 int thiscpu; 2684 2685 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2686 2687 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2688 2689 thiscpu = PCPU_GET(cpuid); 2690 2691 tid = PCPU_GET(tid_next); 2692 if (tid > TID_MAX) 2693 tid = TID_MIN; 2694 PCPU_SET(tid_next, tid + 1); 2695 2696 /* If we are stealing TID then clear the relevant pmap's field */ 2697 if (tidbusy[thiscpu][tid] != NULL) { 2698 2699 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2700 2701 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2702 2703 /* Flush all entries from TLB0 matching this TID. */ 2704 tid_flush(tid); 2705 } 2706 2707 tidbusy[thiscpu][tid] = pmap; 2708 pmap->pm_tid[thiscpu] = tid; 2709 __asm __volatile("msync; isync"); 2710 2711 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2712 PCPU_GET(tid_next)); 2713 2714 return (tid); 2715 } 2716 2717 /**************************************************************************/ 2718 /* TLB0 handling */ 2719 /**************************************************************************/ 2720 2721 static void 2722 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2723 uint32_t mas7) 2724 { 2725 int as; 2726 char desc[3]; 2727 tlbtid_t tid; 2728 vm_size_t size; 2729 unsigned int tsize; 2730 2731 desc[2] = '\0'; 2732 if (mas1 & MAS1_VALID) 2733 desc[0] = 'V'; 2734 else 2735 desc[0] = ' '; 2736 2737 if (mas1 & MAS1_IPROT) 2738 desc[1] = 'P'; 2739 else 2740 desc[1] = ' '; 2741 2742 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2743 tid = MAS1_GETTID(mas1); 2744 2745 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2746 size = 0; 2747 if (tsize) 2748 size = tsize2size(tsize); 2749 2750 debugf("%3d: (%s) [AS=%d] " 2751 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2752 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2753 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2754 } 2755 2756 /* Convert TLB0 va and way number to tlb0[] table index. */ 2757 static inline unsigned int 2758 tlb0_tableidx(vm_offset_t va, unsigned int way) 2759 { 2760 unsigned int idx; 2761 2762 idx = (way * TLB0_ENTRIES_PER_WAY); 2763 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2764 return (idx); 2765 } 2766 2767 /* 2768 * Invalidate TLB0 entry. 2769 */ 2770 static inline void 2771 tlb0_flush_entry(vm_offset_t va) 2772 { 2773 2774 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2775 2776 mtx_assert(&tlbivax_mutex, MA_OWNED); 2777 2778 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2779 __asm __volatile("isync; msync"); 2780 __asm __volatile("tlbsync; msync"); 2781 2782 CTR1(KTR_PMAP, "%s: e", __func__); 2783 } 2784 2785 /* Print out contents of the MAS registers for each TLB0 entry */ 2786 void 2787 tlb0_print_tlbentries(void) 2788 { 2789 uint32_t mas0, mas1, mas2, mas3, mas7; 2790 int entryidx, way, idx; 2791 2792 debugf("TLB0 entries:\n"); 2793 for (way = 0; way < TLB0_WAYS; way ++) 2794 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2795 2796 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2797 mtspr(SPR_MAS0, mas0); 2798 __asm __volatile("isync"); 2799 2800 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2801 mtspr(SPR_MAS2, mas2); 2802 2803 __asm __volatile("isync; tlbre"); 2804 2805 mas1 = mfspr(SPR_MAS1); 2806 mas2 = mfspr(SPR_MAS2); 2807 mas3 = mfspr(SPR_MAS3); 2808 mas7 = mfspr(SPR_MAS7); 2809 2810 idx = tlb0_tableidx(mas2, way); 2811 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2812 } 2813 } 2814 2815 /**************************************************************************/ 2816 /* TLB1 handling */ 2817 /**************************************************************************/ 2818 2819 /* 2820 * TLB1 mapping notes: 2821 * 2822 * TLB1[0] CCSRBAR 2823 * TLB1[1] Kernel text and data. 2824 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2825 * windows, other devices mappings. 2826 */ 2827 2828 /* 2829 * Write given entry to TLB1 hardware. 2830 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2831 */ 2832 static void 2833 tlb1_write_entry(unsigned int idx) 2834 { 2835 uint32_t mas0, mas7; 2836 2837 //debugf("tlb1_write_entry: s\n"); 2838 2839 /* Clear high order RPN bits */ 2840 mas7 = 0; 2841 2842 /* Select entry */ 2843 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2844 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2845 2846 mtspr(SPR_MAS0, mas0); 2847 __asm __volatile("isync"); 2848 mtspr(SPR_MAS1, tlb1[idx].mas1); 2849 __asm __volatile("isync"); 2850 mtspr(SPR_MAS2, tlb1[idx].mas2); 2851 __asm __volatile("isync"); 2852 mtspr(SPR_MAS3, tlb1[idx].mas3); 2853 __asm __volatile("isync"); 2854 mtspr(SPR_MAS7, mas7); 2855 __asm __volatile("isync; tlbwe; isync; msync"); 2856 2857 //debugf("tlb1_write_entry: e\n"); 2858 } 2859 2860 /* 2861 * Return the largest uint value log such that 2^log <= num. 2862 */ 2863 static unsigned int 2864 ilog2(unsigned int num) 2865 { 2866 int lz; 2867 2868 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2869 return (31 - lz); 2870 } 2871 2872 /* 2873 * Convert TLB TSIZE value to mapped region size. 2874 */ 2875 static vm_size_t 2876 tsize2size(unsigned int tsize) 2877 { 2878 2879 /* 2880 * size = 4^tsize KB 2881 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2882 */ 2883 2884 return ((1 << (2 * tsize)) * 1024); 2885 } 2886 2887 /* 2888 * Convert region size (must be power of 4) to TLB TSIZE value. 2889 */ 2890 static unsigned int 2891 size2tsize(vm_size_t size) 2892 { 2893 2894 return (ilog2(size) / 2 - 5); 2895 } 2896 2897 /* 2898 * Register permanent kernel mapping in TLB1. 2899 * 2900 * Entries are created starting from index 0 (current free entry is 2901 * kept in tlb1_idx) and are not supposed to be invalidated. 2902 */ 2903 static int 2904 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2905 uint32_t flags) 2906 { 2907 uint32_t ts, tid; 2908 int tsize; 2909 2910 if (tlb1_idx >= TLB1_ENTRIES) { 2911 printf("tlb1_set_entry: TLB1 full!\n"); 2912 return (-1); 2913 } 2914 2915 /* Convert size to TSIZE */ 2916 tsize = size2tsize(size); 2917 2918 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2919 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2920 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2921 2922 /* XXX LOCK tlb1[] */ 2923 2924 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2925 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2926 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2927 2928 /* Set supervisor RWX permission bits */ 2929 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2930 2931 tlb1_write_entry(tlb1_idx++); 2932 2933 /* XXX UNLOCK tlb1[] */ 2934 2935 /* 2936 * XXX in general TLB1 updates should be propagated between CPUs, 2937 * since current design assumes to have the same TLB1 set-up on all 2938 * cores. 2939 */ 2940 return (0); 2941 } 2942 2943 /* 2944 * Map in contiguous RAM region into the TLB1 using maximum of 2945 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2946 * 2947 * If necessary round up last entry size and return total size 2948 * used by all allocated entries. 2949 */ 2950 vm_size_t 2951 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 2952 { 2953 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 2954 vm_size_t mapped, pgsz, base, mask; 2955 int idx, nents; 2956 2957 /* Round up to the next 1M */ 2958 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 2959 2960 mapped = 0; 2961 idx = 0; 2962 base = va; 2963 pgsz = 64*1024*1024; 2964 while (mapped < size) { 2965 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 2966 while (pgsz > (size - mapped)) 2967 pgsz >>= 2; 2968 pgs[idx++] = pgsz; 2969 mapped += pgsz; 2970 } 2971 2972 /* We under-map. Correct for this. */ 2973 if (mapped < size) { 2974 while (pgs[idx - 1] == pgsz) { 2975 idx--; 2976 mapped -= pgsz; 2977 } 2978 /* XXX We may increase beyond out starting point. */ 2979 pgsz <<= 2; 2980 pgs[idx++] = pgsz; 2981 mapped += pgsz; 2982 } 2983 } 2984 2985 nents = idx; 2986 mask = pgs[0] - 1; 2987 /* Align address to the boundary */ 2988 if (va & mask) { 2989 va = (va + mask) & ~mask; 2990 pa = (pa + mask) & ~mask; 2991 } 2992 2993 for (idx = 0; idx < nents; idx++) { 2994 pgsz = pgs[idx]; 2995 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 2996 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 2997 pa += pgsz; 2998 va += pgsz; 2999 } 3000 3001 mapped = (va - base); 3002 debugf("mapped size 0x%08x (wasted space 0x%08x)\n", 3003 mapped, mapped - size); 3004 return (mapped); 3005 } 3006 3007 /* 3008 * TLB1 initialization routine, to be called after the very first 3009 * assembler level setup done in locore.S. 3010 */ 3011 void 3012 tlb1_init(vm_offset_t ccsrbar) 3013 { 3014 uint32_t mas0, mas1, mas3; 3015 uint32_t tsz; 3016 u_int i; 3017 3018 if (bootinfo != NULL && bootinfo[0] != 1) { 3019 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3020 } else 3021 tlb1_idx = 1; 3022 3023 /* The first entry/entries are used to map the kernel. */ 3024 for (i = 0; i < tlb1_idx; i++) { 3025 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3026 mtspr(SPR_MAS0, mas0); 3027 __asm __volatile("isync; tlbre"); 3028 3029 mas1 = mfspr(SPR_MAS1); 3030 if ((mas1 & MAS1_VALID) == 0) 3031 continue; 3032 3033 mas3 = mfspr(SPR_MAS3); 3034 3035 tlb1[i].mas1 = mas1; 3036 tlb1[i].mas2 = mfspr(SPR_MAS2); 3037 tlb1[i].mas3 = mas3; 3038 3039 if (i == 0) 3040 kernload = mas3 & MAS3_RPN; 3041 3042 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3043 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3044 } 3045 3046 /* Map in CCSRBAR. */ 3047 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3048 3049 /* Setup TLB miss defaults */ 3050 set_mas4_defaults(); 3051 } 3052 3053 /* 3054 * Setup MAS4 defaults. 3055 * These values are loaded to MAS0-2 on a TLB miss. 3056 */ 3057 static void 3058 set_mas4_defaults(void) 3059 { 3060 uint32_t mas4; 3061 3062 /* Defaults: TLB0, PID0, TSIZED=4K */ 3063 mas4 = MAS4_TLBSELD0; 3064 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3065 #ifdef SMP 3066 mas4 |= MAS4_MD; 3067 #endif 3068 mtspr(SPR_MAS4, mas4); 3069 __asm __volatile("isync"); 3070 } 3071 3072 /* 3073 * Print out contents of the MAS registers for each TLB1 entry 3074 */ 3075 void 3076 tlb1_print_tlbentries(void) 3077 { 3078 uint32_t mas0, mas1, mas2, mas3, mas7; 3079 int i; 3080 3081 debugf("TLB1 entries:\n"); 3082 for (i = 0; i < TLB1_ENTRIES; i++) { 3083 3084 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3085 mtspr(SPR_MAS0, mas0); 3086 3087 __asm __volatile("isync; tlbre"); 3088 3089 mas1 = mfspr(SPR_MAS1); 3090 mas2 = mfspr(SPR_MAS2); 3091 mas3 = mfspr(SPR_MAS3); 3092 mas7 = mfspr(SPR_MAS7); 3093 3094 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3095 } 3096 } 3097 3098 /* 3099 * Print out contents of the in-ram tlb1 table. 3100 */ 3101 void 3102 tlb1_print_entries(void) 3103 { 3104 int i; 3105 3106 debugf("tlb1[] table entries:\n"); 3107 for (i = 0; i < TLB1_ENTRIES; i++) 3108 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3109 } 3110 3111 /* 3112 * Return 0 if the physical IO range is encompassed by one of the 3113 * the TLB1 entries, otherwise return related error code. 3114 */ 3115 static int 3116 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3117 { 3118 uint32_t prot; 3119 vm_paddr_t pa_start; 3120 vm_paddr_t pa_end; 3121 unsigned int entry_tsize; 3122 vm_size_t entry_size; 3123 3124 *va = (vm_offset_t)NULL; 3125 3126 /* Skip invalid entries */ 3127 if (!(tlb1[i].mas1 & MAS1_VALID)) 3128 return (EINVAL); 3129 3130 /* 3131 * The entry must be cache-inhibited, guarded, and r/w 3132 * so it can function as an i/o page 3133 */ 3134 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3135 if (prot != (MAS2_I | MAS2_G)) 3136 return (EPERM); 3137 3138 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3139 if (prot != (MAS3_SR | MAS3_SW)) 3140 return (EPERM); 3141 3142 /* The address should be within the entry range. */ 3143 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3144 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3145 3146 entry_size = tsize2size(entry_tsize); 3147 pa_start = tlb1[i].mas3 & MAS3_RPN; 3148 pa_end = pa_start + entry_size - 1; 3149 3150 if ((pa < pa_start) || ((pa + size) > pa_end)) 3151 return (ERANGE); 3152 3153 /* Return virtual address of this mapping. */ 3154 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3155 return (0); 3156 } 3157