1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * 32-bit pmap: 40 * Virtual address space layout: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA 47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 51 * 52 * 64-bit pmap: 53 * Virtual address space layout: 54 * ----------------------------- 55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process 56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries 57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region 58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack 59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved 60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data 61 * endkernel - msgbufp-1 : flat device tree 62 * msgbufp - kernel_pdir-1 : message buffer 63 * kernel_pdir - kernel_pp2d-1 : kernel page directory 64 * kernel_pp2d - . : kernel pointers to page directory 65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy 66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs 67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables 68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space 69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region 70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region 71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map 72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map 73 * - 0xffff_ffff_ffff_ffff : device direct map 74 */ 75 76 #include <sys/cdefs.h> 77 #include "opt_ddb.h" 78 #include "opt_kstack_pages.h" 79 80 #include <sys/param.h> 81 #include <sys/conf.h> 82 #include <sys/malloc.h> 83 #include <sys/ktr.h> 84 #include <sys/proc.h> 85 #include <sys/user.h> 86 #include <sys/queue.h> 87 #include <sys/systm.h> 88 #include <sys/kernel.h> 89 #include <sys/kerneldump.h> 90 #include <sys/linker.h> 91 #include <sys/msgbuf.h> 92 #include <sys/lock.h> 93 #include <sys/mutex.h> 94 #include <sys/rwlock.h> 95 #include <sys/sched.h> 96 #include <sys/smp.h> 97 #include <sys/vmmeter.h> 98 99 #include <vm/vm.h> 100 #include <vm/vm_param.h> 101 #include <vm/vm_page.h> 102 #include <vm/vm_kern.h> 103 #include <vm/vm_pageout.h> 104 #include <vm/vm_extern.h> 105 #include <vm/vm_object.h> 106 #include <vm/vm_map.h> 107 #include <vm/vm_pager.h> 108 #include <vm/vm_phys.h> 109 #include <vm/vm_pagequeue.h> 110 #include <vm/vm_dumpset.h> 111 #include <vm/uma.h> 112 113 #include <machine/_inttypes.h> 114 #include <machine/cpu.h> 115 #include <machine/pcb.h> 116 #include <machine/platform.h> 117 118 #include <machine/tlb.h> 119 #include <machine/spr.h> 120 #include <machine/md_var.h> 121 #include <machine/mmuvar.h> 122 #include <machine/pmap.h> 123 #include <machine/pte.h> 124 125 #include <ddb/ddb.h> 126 127 #define SPARSE_MAPDEV 128 129 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */ 130 #define POW2_MAPPINGS 131 132 #ifdef DEBUG 133 #define debugf(fmt, args...) printf(fmt, ##args) 134 #define __debug_used 135 #else 136 #define debugf(fmt, args...) 137 #define __debug_used __unused 138 #endif 139 140 #ifdef __powerpc64__ 141 #define PRI0ptrX "016lx" 142 #else 143 #define PRI0ptrX "08x" 144 #endif 145 146 #define TODO panic("%s: not implemented", __func__); 147 148 extern unsigned char _etext[]; 149 extern unsigned char _end[]; 150 151 extern uint32_t *bootinfo; 152 153 vm_paddr_t kernload; 154 vm_offset_t kernstart; 155 vm_size_t kernsize; 156 157 /* Message buffer and tables. */ 158 static vm_offset_t data_start; 159 static vm_size_t data_end; 160 161 /* Phys/avail memory regions. */ 162 static struct mem_region *availmem_regions; 163 static int availmem_regions_sz; 164 static struct mem_region *physmem_regions; 165 static int physmem_regions_sz; 166 167 #ifndef __powerpc64__ 168 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 169 static vm_offset_t zero_page_va; 170 static struct mtx zero_page_mutex; 171 172 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 173 static vm_offset_t copy_page_src_va; 174 static vm_offset_t copy_page_dst_va; 175 static struct mtx copy_page_mutex; 176 #endif 177 178 static struct mtx tlbivax_mutex; 179 180 /**************************************************************************/ 181 /* PMAP */ 182 /**************************************************************************/ 183 184 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t, 185 vm_prot_t, u_int flags, int8_t psind); 186 187 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 188 static uma_zone_t ptbl_root_zone; 189 190 /* 191 * If user pmap is processed with mmu_booke_remove and the resident count 192 * drops to 0, there are no more pages to remove, so we need not continue. 193 */ 194 #define PMAP_REMOVE_DONE(pmap) \ 195 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 196 197 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 198 extern int elf32_nxstack; 199 #endif 200 201 /**************************************************************************/ 202 /* TLB and TID handling */ 203 /**************************************************************************/ 204 205 /* Translation ID busy table */ 206 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 207 208 /* 209 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 210 * core revisions and should be read from h/w registers during early config. 211 */ 212 uint32_t tlb0_entries; 213 uint32_t tlb0_ways; 214 uint32_t tlb0_entries_per_way; 215 uint32_t tlb1_entries; 216 217 #define TLB0_ENTRIES (tlb0_entries) 218 #define TLB0_WAYS (tlb0_ways) 219 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 220 221 #define TLB1_ENTRIES (tlb1_entries) 222 223 static tlbtid_t tid_alloc(struct pmap *); 224 225 #ifdef DDB 226 #ifdef __powerpc64__ 227 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t); 228 #else 229 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 230 #endif 231 #endif 232 233 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 234 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 235 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 236 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int); 237 238 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma); 239 240 static vm_size_t tsize2size(unsigned int); 241 static unsigned int size2tsize(vm_size_t); 242 static unsigned long ilog2(unsigned long); 243 244 static void set_mas4_defaults(void); 245 246 static inline void tlb0_flush_entry(vm_offset_t); 247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 248 249 /**************************************************************************/ 250 /* Page table management */ 251 /**************************************************************************/ 252 253 static struct rwlock_padalign pvh_global_lock; 254 255 /* Data for the pv entry allocation mechanism */ 256 static uma_zone_t pvzone; 257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 258 259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 260 261 #ifndef PMAP_SHPGPERPROC 262 #define PMAP_SHPGPERPROC 200 263 #endif 264 265 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t); 266 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, bool); 267 static int pte_remove(pmap_t, vm_offset_t, uint8_t); 268 static pte_t *pte_find(pmap_t, vm_offset_t); 269 static void kernel_pte_alloc(vm_offset_t, vm_offset_t); 270 271 static pv_entry_t pv_alloc(void); 272 static void pv_free(pv_entry_t); 273 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 274 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 275 276 static void booke_pmap_init_qpages(void); 277 278 static inline void tlb_miss_lock(void); 279 static inline void tlb_miss_unlock(void); 280 281 #ifdef SMP 282 extern tlb_entry_t __boot_tlb1[]; 283 void pmap_bootstrap_ap(volatile uint32_t *); 284 #endif 285 286 /* 287 * Kernel MMU interface 288 */ 289 static void mmu_booke_clear_modify(vm_page_t); 290 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, 291 vm_size_t, vm_offset_t); 292 static void mmu_booke_copy_page(vm_page_t, vm_page_t); 293 static void mmu_booke_copy_pages(vm_page_t *, 294 vm_offset_t, vm_page_t *, vm_offset_t, int); 295 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t, 296 vm_prot_t, u_int flags, int8_t psind); 297 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t, 298 vm_page_t, vm_prot_t); 299 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t, 300 vm_prot_t); 301 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t); 302 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t, 303 vm_prot_t); 304 static void mmu_booke_init(void); 305 static bool mmu_booke_is_modified(vm_page_t); 306 static bool mmu_booke_is_prefaultable(pmap_t, vm_offset_t); 307 static bool mmu_booke_is_referenced(vm_page_t); 308 static int mmu_booke_ts_referenced(vm_page_t); 309 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, 310 int); 311 static int mmu_booke_mincore(pmap_t, vm_offset_t, 312 vm_paddr_t *); 313 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t, 314 vm_object_t, vm_pindex_t, vm_size_t); 315 static bool mmu_booke_page_exists_quick(pmap_t, vm_page_t); 316 static void mmu_booke_page_init(vm_page_t); 317 static int mmu_booke_page_wired_mappings(vm_page_t); 318 static int mmu_booke_pinit(pmap_t); 319 static void mmu_booke_pinit0(pmap_t); 320 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t, 321 vm_prot_t); 322 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int); 323 static void mmu_booke_qremove(vm_offset_t, int); 324 static void mmu_booke_release(pmap_t); 325 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t); 326 static void mmu_booke_remove_all(vm_page_t); 327 static void mmu_booke_remove_write(vm_page_t); 328 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t); 329 static void mmu_booke_zero_page(vm_page_t); 330 static void mmu_booke_zero_page_area(vm_page_t, int, int); 331 static void mmu_booke_activate(struct thread *); 332 static void mmu_booke_deactivate(struct thread *); 333 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t); 334 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t); 335 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 336 static void mmu_booke_unmapdev(void *, vm_size_t); 337 static vm_paddr_t mmu_booke_kextract(vm_offset_t); 338 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t); 339 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 340 static void mmu_booke_kremove(vm_offset_t); 341 static int mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t); 342 static void mmu_booke_sync_icache(pmap_t, vm_offset_t, 343 vm_size_t); 344 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t, 345 void **); 346 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t, 347 void *); 348 static void mmu_booke_scan_init(void); 349 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m); 350 static void mmu_booke_quick_remove_page(vm_offset_t addr); 351 static int mmu_booke_change_attr(vm_offset_t addr, 352 vm_size_t sz, vm_memattr_t mode); 353 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr, 354 int *is_user, vm_offset_t *decoded_addr); 355 static void mmu_booke_page_array_startup(long); 356 static bool mmu_booke_page_is_mapped(vm_page_t m); 357 static bool mmu_booke_ps_enabled(pmap_t pmap); 358 359 static struct pmap_funcs mmu_booke_methods = { 360 /* pmap dispatcher interface */ 361 .clear_modify = mmu_booke_clear_modify, 362 .copy = mmu_booke_copy, 363 .copy_page = mmu_booke_copy_page, 364 .copy_pages = mmu_booke_copy_pages, 365 .enter = mmu_booke_enter, 366 .enter_object = mmu_booke_enter_object, 367 .enter_quick = mmu_booke_enter_quick, 368 .extract = mmu_booke_extract, 369 .extract_and_hold = mmu_booke_extract_and_hold, 370 .init = mmu_booke_init, 371 .is_modified = mmu_booke_is_modified, 372 .is_prefaultable = mmu_booke_is_prefaultable, 373 .is_referenced = mmu_booke_is_referenced, 374 .ts_referenced = mmu_booke_ts_referenced, 375 .map = mmu_booke_map, 376 .mincore = mmu_booke_mincore, 377 .object_init_pt = mmu_booke_object_init_pt, 378 .page_exists_quick = mmu_booke_page_exists_quick, 379 .page_init = mmu_booke_page_init, 380 .page_wired_mappings = mmu_booke_page_wired_mappings, 381 .pinit = mmu_booke_pinit, 382 .pinit0 = mmu_booke_pinit0, 383 .protect = mmu_booke_protect, 384 .qenter = mmu_booke_qenter, 385 .qremove = mmu_booke_qremove, 386 .release = mmu_booke_release, 387 .remove = mmu_booke_remove, 388 .remove_all = mmu_booke_remove_all, 389 .remove_write = mmu_booke_remove_write, 390 .sync_icache = mmu_booke_sync_icache, 391 .unwire = mmu_booke_unwire, 392 .zero_page = mmu_booke_zero_page, 393 .zero_page_area = mmu_booke_zero_page_area, 394 .activate = mmu_booke_activate, 395 .deactivate = mmu_booke_deactivate, 396 .quick_enter_page = mmu_booke_quick_enter_page, 397 .quick_remove_page = mmu_booke_quick_remove_page, 398 .page_array_startup = mmu_booke_page_array_startup, 399 .page_is_mapped = mmu_booke_page_is_mapped, 400 .ps_enabled = mmu_booke_ps_enabled, 401 402 /* Internal interfaces */ 403 .bootstrap = mmu_booke_bootstrap, 404 .dev_direct_mapped = mmu_booke_dev_direct_mapped, 405 .mapdev = mmu_booke_mapdev, 406 .mapdev_attr = mmu_booke_mapdev_attr, 407 .kenter = mmu_booke_kenter, 408 .kenter_attr = mmu_booke_kenter_attr, 409 .kextract = mmu_booke_kextract, 410 .kremove = mmu_booke_kremove, 411 .unmapdev = mmu_booke_unmapdev, 412 .change_attr = mmu_booke_change_attr, 413 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr, 414 415 /* dumpsys() support */ 416 .dumpsys_map_chunk = mmu_booke_dumpsys_map, 417 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap, 418 .dumpsys_pa_init = mmu_booke_scan_init, 419 }; 420 421 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods); 422 423 #ifdef __powerpc64__ 424 #include "pmap_64.c" 425 #else 426 #include "pmap_32.c" 427 #endif 428 429 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE; 430 431 static __inline uint32_t 432 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 433 { 434 uint32_t attrib; 435 int i; 436 437 if (ma != VM_MEMATTR_DEFAULT) { 438 switch (ma) { 439 case VM_MEMATTR_UNCACHEABLE: 440 return (MAS2_I | MAS2_G); 441 case VM_MEMATTR_WRITE_COMBINING: 442 case VM_MEMATTR_WRITE_BACK: 443 case VM_MEMATTR_PREFETCHABLE: 444 return (MAS2_I); 445 case VM_MEMATTR_WRITE_THROUGH: 446 return (MAS2_W | MAS2_M); 447 case VM_MEMATTR_CACHEABLE: 448 return (MAS2_M); 449 } 450 } 451 452 /* 453 * Assume the page is cache inhibited and access is guarded unless 454 * it's in our available memory array. 455 */ 456 attrib = _TLB_ENTRY_IO; 457 for (i = 0; i < physmem_regions_sz; i++) { 458 if ((pa >= physmem_regions[i].mr_start) && 459 (pa < (physmem_regions[i].mr_start + 460 physmem_regions[i].mr_size))) { 461 attrib = _TLB_ENTRY_MEM; 462 break; 463 } 464 } 465 466 return (attrib); 467 } 468 469 static inline void 470 tlb_miss_lock(void) 471 { 472 #ifdef SMP 473 struct pcpu *pc; 474 475 if (!smp_started) 476 return; 477 478 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 479 if (pc != pcpup) { 480 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 481 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock); 482 483 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 484 ("tlb_miss_lock: tried to lock self")); 485 486 tlb_lock(pc->pc_booke.tlb_lock); 487 488 CTR1(KTR_PMAP, "%s: locked", __func__); 489 } 490 } 491 #endif 492 } 493 494 static inline void 495 tlb_miss_unlock(void) 496 { 497 #ifdef SMP 498 struct pcpu *pc; 499 500 if (!smp_started) 501 return; 502 503 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 504 if (pc != pcpup) { 505 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 506 __func__, pc->pc_cpuid); 507 508 tlb_unlock(pc->pc_booke.tlb_lock); 509 510 CTR1(KTR_PMAP, "%s: unlocked", __func__); 511 } 512 } 513 #endif 514 } 515 516 /* Return number of entries in TLB0. */ 517 static __inline void 518 tlb0_get_tlbconf(void) 519 { 520 uint32_t tlb0_cfg; 521 522 tlb0_cfg = mfspr(SPR_TLB0CFG); 523 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 524 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 525 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 526 } 527 528 /* Return number of entries in TLB1. */ 529 static __inline void 530 tlb1_get_tlbconf(void) 531 { 532 uint32_t tlb1_cfg; 533 534 tlb1_cfg = mfspr(SPR_TLB1CFG); 535 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 536 } 537 538 /**************************************************************************/ 539 /* Page table related */ 540 /**************************************************************************/ 541 542 /* Allocate pv_entry structure. */ 543 pv_entry_t 544 pv_alloc(void) 545 { 546 pv_entry_t pv; 547 548 pv_entry_count++; 549 if (pv_entry_count > pv_entry_high_water) 550 pagedaemon_wakeup(0); /* XXX powerpc NUMA */ 551 pv = uma_zalloc(pvzone, M_NOWAIT); 552 553 return (pv); 554 } 555 556 /* Free pv_entry structure. */ 557 static __inline void 558 pv_free(pv_entry_t pve) 559 { 560 561 pv_entry_count--; 562 uma_zfree(pvzone, pve); 563 } 564 565 /* Allocate and initialize pv_entry structure. */ 566 static void 567 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 568 { 569 pv_entry_t pve; 570 571 //int su = (pmap == kernel_pmap); 572 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 573 // (u_int32_t)pmap, va, (u_int32_t)m); 574 575 pve = pv_alloc(); 576 if (pve == NULL) 577 panic("pv_insert: no pv entries!"); 578 579 pve->pv_pmap = pmap; 580 pve->pv_va = va; 581 582 /* add to pv_list */ 583 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 584 rw_assert(&pvh_global_lock, RA_WLOCKED); 585 586 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 587 588 //debugf("pv_insert: e\n"); 589 } 590 591 /* Destroy pv entry. */ 592 static void 593 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 594 { 595 pv_entry_t pve; 596 597 //int su = (pmap == kernel_pmap); 598 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 599 600 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 601 rw_assert(&pvh_global_lock, RA_WLOCKED); 602 603 /* find pv entry */ 604 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 605 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 606 /* remove from pv_list */ 607 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 608 if (TAILQ_EMPTY(&m->md.pv_list)) 609 vm_page_aflag_clear(m, PGA_WRITEABLE); 610 611 /* free pv entry struct */ 612 pv_free(pve); 613 break; 614 } 615 } 616 617 //debugf("pv_remove: e\n"); 618 } 619 620 /**************************************************************************/ 621 /* PMAP related */ 622 /**************************************************************************/ 623 624 /* 625 * This is called during booke_init, before the system is really initialized. 626 */ 627 static void 628 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend) 629 { 630 vm_paddr_t phys_kernelend; 631 struct mem_region *mp, *mp1; 632 int cnt, i, j; 633 vm_paddr_t s, e, sz; 634 vm_paddr_t physsz, hwphyssz; 635 u_int phys_avail_count __debug_used; 636 vm_size_t kstack0_sz; 637 vm_paddr_t kstack0_phys; 638 vm_offset_t kstack0; 639 void *dpcpu; 640 641 debugf("mmu_booke_bootstrap: entered\n"); 642 643 /* Set interesting system properties */ 644 #ifdef __powerpc64__ 645 hw_direct_map = 1; 646 #else 647 hw_direct_map = 0; 648 #endif 649 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 650 elf32_nxstack = 1; 651 #endif 652 653 /* Initialize invalidation mutex */ 654 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 655 656 /* Read TLB0 size and associativity. */ 657 tlb0_get_tlbconf(); 658 659 /* 660 * Align kernel start and end address (kernel image). 661 * Note that kernel end does not necessarily relate to kernsize. 662 * kernsize is the size of the kernel that is actually mapped. 663 */ 664 data_start = round_page(kernelend); 665 data_end = data_start; 666 667 /* Allocate the dynamic per-cpu area. */ 668 dpcpu = (void *)data_end; 669 data_end += DPCPU_SIZE; 670 671 /* Allocate space for the message buffer. */ 672 msgbufp = (struct msgbuf *)data_end; 673 data_end += msgbufsize; 674 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 675 (uintptr_t)msgbufp, data_end); 676 677 data_end = round_page(data_end); 678 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end)); 679 680 /* Retrieve phys/avail mem regions */ 681 mem_regions(&physmem_regions, &physmem_regions_sz, 682 &availmem_regions, &availmem_regions_sz); 683 684 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz) 685 panic("mmu_booke_bootstrap: phys_avail too small"); 686 687 data_end = round_page(data_end); 688 vm_page_array = (vm_page_t)data_end; 689 /* 690 * Get a rough idea (upper bound) on the size of the page array. The 691 * vm_page_array will not handle any more pages than we have in the 692 * avail_regions array, and most likely much less. 693 */ 694 sz = 0; 695 for (mp = availmem_regions; mp->mr_size; mp++) { 696 sz += mp->mr_size; 697 } 698 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page))); 699 data_end += round_page(sz * sizeof(struct vm_page)); 700 701 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */ 702 data_end = roundup2(data_end, 1 << 20); 703 704 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end); 705 debugf(" kernstart: %#zx\n", kernstart); 706 debugf(" kernsize: %#zx\n", kernsize); 707 708 if (data_end - kernstart > kernsize) { 709 kernsize += tlb1_mapin_region(kernstart + kernsize, 710 kernload + kernsize, (data_end - kernstart) - kernsize, 711 _TLB_ENTRY_MEM); 712 } 713 data_end = kernstart + kernsize; 714 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end); 715 716 /* 717 * Clear the structures - note we can only do it safely after the 718 * possible additional TLB1 translations are in place (above) so that 719 * all range up to the currently calculated 'data_end' is covered. 720 */ 721 bzero((void *)data_start, data_end - data_start); 722 dpcpu_init(dpcpu, 0); 723 724 /*******************************************************/ 725 /* Set the start and end of kva. */ 726 /*******************************************************/ 727 virtual_avail = round_page(data_end); 728 virtual_end = VM_MAX_KERNEL_ADDRESS; 729 730 #ifndef __powerpc64__ 731 /* Allocate KVA space for page zero/copy operations. */ 732 zero_page_va = virtual_avail; 733 virtual_avail += PAGE_SIZE; 734 copy_page_src_va = virtual_avail; 735 virtual_avail += PAGE_SIZE; 736 copy_page_dst_va = virtual_avail; 737 virtual_avail += PAGE_SIZE; 738 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va); 739 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va); 740 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va); 741 742 /* Initialize page zero/copy mutexes. */ 743 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 744 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 745 746 /* Allocate KVA space for ptbl bufs. */ 747 ptbl_buf_pool_vabase = virtual_avail; 748 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 749 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 750 ptbl_buf_pool_vabase, virtual_avail); 751 #endif 752 753 /* Calculate corresponding physical addresses for the kernel region. */ 754 phys_kernelend = kernload + kernsize; 755 debugf("kernel image and allocated data:\n"); 756 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload); 757 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart); 758 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize); 759 760 /* 761 * Remove kernel physical address range from avail regions list. Page 762 * align all regions. Non-page aligned memory isn't very interesting 763 * to us. Also, sort the entries for ascending addresses. 764 */ 765 766 sz = 0; 767 cnt = availmem_regions_sz; 768 debugf("processing avail regions:\n"); 769 for (mp = availmem_regions; mp->mr_size; mp++) { 770 s = mp->mr_start; 771 e = mp->mr_start + mp->mr_size; 772 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 773 /* Check whether this region holds all of the kernel. */ 774 if (s < kernload && e > phys_kernelend) { 775 availmem_regions[cnt].mr_start = phys_kernelend; 776 availmem_regions[cnt++].mr_size = e - phys_kernelend; 777 e = kernload; 778 } 779 /* Look whether this regions starts within the kernel. */ 780 if (s >= kernload && s < phys_kernelend) { 781 if (e <= phys_kernelend) 782 goto empty; 783 s = phys_kernelend; 784 } 785 /* Now look whether this region ends within the kernel. */ 786 if (e > kernload && e <= phys_kernelend) { 787 if (s >= kernload) 788 goto empty; 789 e = kernload; 790 } 791 /* Now page align the start and size of the region. */ 792 s = round_page(s); 793 e = trunc_page(e); 794 if (e < s) 795 e = s; 796 sz = e - s; 797 debugf("%09jx-%09jx = %jx\n", 798 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 799 800 /* Check whether some memory is left here. */ 801 if (sz == 0) { 802 empty: 803 memmove(mp, mp + 1, 804 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 805 cnt--; 806 mp--; 807 continue; 808 } 809 810 /* Do an insertion sort. */ 811 for (mp1 = availmem_regions; mp1 < mp; mp1++) 812 if (s < mp1->mr_start) 813 break; 814 if (mp1 < mp) { 815 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 816 mp1->mr_start = s; 817 mp1->mr_size = sz; 818 } else { 819 mp->mr_start = s; 820 mp->mr_size = sz; 821 } 822 } 823 availmem_regions_sz = cnt; 824 825 /*******************************************************/ 826 /* Steal physical memory for kernel stack from the end */ 827 /* of the first avail region */ 828 /*******************************************************/ 829 kstack0_sz = kstack_pages * PAGE_SIZE; 830 kstack0_phys = availmem_regions[0].mr_start + 831 availmem_regions[0].mr_size; 832 kstack0_phys -= kstack0_sz; 833 availmem_regions[0].mr_size -= kstack0_sz; 834 835 /*******************************************************/ 836 /* Fill in phys_avail table, based on availmem_regions */ 837 /*******************************************************/ 838 phys_avail_count = 0; 839 physsz = 0; 840 hwphyssz = 0; 841 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 842 843 debugf("fill in phys_avail:\n"); 844 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 845 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 846 (uintmax_t)availmem_regions[i].mr_start, 847 (uintmax_t)availmem_regions[i].mr_start + 848 availmem_regions[i].mr_size, 849 (uintmax_t)availmem_regions[i].mr_size); 850 851 if (hwphyssz != 0 && 852 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 853 debugf(" hw.physmem adjust\n"); 854 if (physsz < hwphyssz) { 855 phys_avail[j] = availmem_regions[i].mr_start; 856 phys_avail[j + 1] = 857 availmem_regions[i].mr_start + 858 hwphyssz - physsz; 859 physsz = hwphyssz; 860 phys_avail_count++; 861 dump_avail[j] = phys_avail[j]; 862 dump_avail[j + 1] = phys_avail[j + 1]; 863 } 864 break; 865 } 866 867 phys_avail[j] = availmem_regions[i].mr_start; 868 phys_avail[j + 1] = availmem_regions[i].mr_start + 869 availmem_regions[i].mr_size; 870 phys_avail_count++; 871 physsz += availmem_regions[i].mr_size; 872 dump_avail[j] = phys_avail[j]; 873 dump_avail[j + 1] = phys_avail[j + 1]; 874 } 875 physmem = btoc(physsz); 876 877 /* Calculate the last available physical address. */ 878 for (i = 0; phys_avail[i + 2] != 0; i += 2) 879 ; 880 Maxmem = powerpc_btop(phys_avail[i + 1]); 881 882 debugf("Maxmem = 0x%08lx\n", Maxmem); 883 debugf("phys_avail_count = %d\n", phys_avail_count); 884 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 885 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 886 887 #ifdef __powerpc64__ 888 /* 889 * Map the physical memory contiguously in TLB1. 890 * Round so it fits into a single mapping. 891 */ 892 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0, 893 phys_avail[i + 1], _TLB_ENTRY_MEM); 894 #endif 895 896 /*******************************************************/ 897 /* Initialize (statically allocated) kernel pmap. */ 898 /*******************************************************/ 899 PMAP_LOCK_INIT(kernel_pmap); 900 901 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap); 902 kernel_pte_alloc(virtual_avail, kernstart); 903 for (i = 0; i < MAXCPU; i++) { 904 kernel_pmap->pm_tid[i] = TID_KERNEL; 905 906 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 907 tidbusy[i][TID_KERNEL] = kernel_pmap; 908 } 909 910 /* Mark kernel_pmap active on all CPUs */ 911 CPU_FILL(&kernel_pmap->pm_active); 912 913 /* 914 * Initialize the global pv list lock. 915 */ 916 rw_init(&pvh_global_lock, "pmap pv global"); 917 918 /*******************************************************/ 919 /* Final setup */ 920 /*******************************************************/ 921 922 /* Enter kstack0 into kernel map, provide guard page */ 923 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 924 thread0.td_kstack = kstack0; 925 thread0.td_kstack_pages = kstack_pages; 926 927 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz); 928 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n", 929 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz); 930 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n", 931 kstack0, kstack0 + kstack0_sz); 932 933 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 934 for (i = 0; i < kstack_pages; i++) { 935 mmu_booke_kenter(kstack0, kstack0_phys); 936 kstack0 += PAGE_SIZE; 937 kstack0_phys += PAGE_SIZE; 938 } 939 940 pmap_bootstrapped = 1; 941 942 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail); 943 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end); 944 945 debugf("mmu_booke_bootstrap: exit\n"); 946 } 947 948 #ifdef SMP 949 void 950 tlb1_ap_prep(void) 951 { 952 tlb_entry_t *e, tmp; 953 unsigned int i; 954 955 /* Prepare TLB1 image for AP processors */ 956 e = __boot_tlb1; 957 for (i = 0; i < TLB1_ENTRIES; i++) { 958 tlb1_read_entry(&tmp, i); 959 960 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 961 memcpy(e++, &tmp, sizeof(tmp)); 962 } 963 } 964 965 void 966 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 967 { 968 int i; 969 970 /* 971 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 972 * have the snapshot of its contents in the s/w __boot_tlb1[] table 973 * created by tlb1_ap_prep(), so use these values directly to 974 * (re)program AP's TLB1 hardware. 975 * 976 * Start at index 1 because index 0 has the kernel map. 977 */ 978 for (i = 1; i < TLB1_ENTRIES; i++) { 979 if (__boot_tlb1[i].mas1 & MAS1_VALID) 980 tlb1_write_entry(&__boot_tlb1[i], i); 981 } 982 983 set_mas4_defaults(); 984 } 985 #endif 986 987 static void 988 booke_pmap_init_qpages(void) 989 { 990 struct pcpu *pc; 991 int i; 992 993 CPU_FOREACH(i) { 994 pc = pcpu_find(i); 995 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 996 if (pc->pc_qmap_addr == 0) 997 panic("pmap_init_qpages: unable to allocate KVA"); 998 } 999 } 1000 1001 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1002 1003 /* 1004 * Get the physical page address for the given pmap/virtual address. 1005 */ 1006 static vm_paddr_t 1007 mmu_booke_extract(pmap_t pmap, vm_offset_t va) 1008 { 1009 vm_paddr_t pa; 1010 1011 PMAP_LOCK(pmap); 1012 pa = pte_vatopa(pmap, va); 1013 PMAP_UNLOCK(pmap); 1014 1015 return (pa); 1016 } 1017 1018 /* 1019 * Extract the physical page address associated with the given 1020 * kernel virtual address. 1021 */ 1022 static vm_paddr_t 1023 mmu_booke_kextract(vm_offset_t va) 1024 { 1025 tlb_entry_t e; 1026 vm_paddr_t p = 0; 1027 int i; 1028 1029 #ifdef __powerpc64__ 1030 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) 1031 return (DMAP_TO_PHYS(va)); 1032 #endif 1033 1034 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS) 1035 p = pte_vatopa(kernel_pmap, va); 1036 1037 if (p == 0) { 1038 /* Check TLB1 mappings */ 1039 for (i = 0; i < TLB1_ENTRIES; i++) { 1040 tlb1_read_entry(&e, i); 1041 if (!(e.mas1 & MAS1_VALID)) 1042 continue; 1043 if (va >= e.virt && va < e.virt + e.size) 1044 return (e.phys + (va - e.virt)); 1045 } 1046 } 1047 1048 return (p); 1049 } 1050 1051 /* 1052 * Initialize the pmap module. 1053 * Called by vm_init, to initialize any structures that the pmap 1054 * system needs to map virtual memory. 1055 */ 1056 static void 1057 mmu_booke_init(void) 1058 { 1059 int shpgperproc = PMAP_SHPGPERPROC; 1060 1061 /* 1062 * Initialize the address space (zone) for the pv entries. Set a 1063 * high water mark so that the system can recover from excessive 1064 * numbers of pv entries. 1065 */ 1066 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1067 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1068 1069 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1070 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1071 1072 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max); 1073 pv_entry_high_water = 9 * (pv_entry_max / 10); 1074 1075 uma_zone_reserve_kva(pvzone, pv_entry_max); 1076 1077 /* Pre-fill pvzone with initial number of pv entries. */ 1078 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1079 1080 /* Create a UMA zone for page table roots. */ 1081 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE, 1082 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM); 1083 1084 /* Initialize ptbl allocation. */ 1085 ptbl_init(); 1086 } 1087 1088 /* 1089 * Map a list of wired pages into kernel virtual address space. This is 1090 * intended for temporary mappings which do not need page modification or 1091 * references recorded. Existing mappings in the region are overwritten. 1092 */ 1093 static void 1094 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count) 1095 { 1096 vm_offset_t va; 1097 1098 va = sva; 1099 while (count-- > 0) { 1100 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m)); 1101 va += PAGE_SIZE; 1102 m++; 1103 } 1104 } 1105 1106 /* 1107 * Remove page mappings from kernel virtual address space. Intended for 1108 * temporary mappings entered by mmu_booke_qenter. 1109 */ 1110 static void 1111 mmu_booke_qremove(vm_offset_t sva, int count) 1112 { 1113 vm_offset_t va; 1114 1115 va = sva; 1116 while (count-- > 0) { 1117 mmu_booke_kremove(va); 1118 va += PAGE_SIZE; 1119 } 1120 } 1121 1122 /* 1123 * Map a wired page into kernel virtual address space. 1124 */ 1125 static void 1126 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa) 1127 { 1128 1129 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1130 } 1131 1132 static void 1133 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1134 { 1135 uint32_t flags; 1136 pte_t *pte; 1137 1138 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1139 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1140 1141 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1142 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1143 flags |= PTE_PS_4KB; 1144 1145 pte = pte_find(kernel_pmap, va); 1146 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE")); 1147 1148 mtx_lock_spin(&tlbivax_mutex); 1149 tlb_miss_lock(); 1150 1151 if (PTE_ISVALID(pte)) { 1152 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1153 1154 /* Flush entry from TLB0 */ 1155 tlb0_flush_entry(va); 1156 } 1157 1158 *pte = PTE_RPN_FROM_PA(pa) | flags; 1159 1160 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1161 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1162 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1163 1164 /* Flush the real memory from the instruction cache. */ 1165 if ((flags & (PTE_I | PTE_G)) == 0) 1166 __syncicache((void *)va, PAGE_SIZE); 1167 1168 tlb_miss_unlock(); 1169 mtx_unlock_spin(&tlbivax_mutex); 1170 } 1171 1172 /* 1173 * Remove a page from kernel page table. 1174 */ 1175 static void 1176 mmu_booke_kremove(vm_offset_t va) 1177 { 1178 pte_t *pte; 1179 1180 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va); 1181 1182 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1183 (va <= VM_MAX_KERNEL_ADDRESS)), 1184 ("mmu_booke_kremove: invalid va")); 1185 1186 pte = pte_find(kernel_pmap, va); 1187 1188 if (!PTE_ISVALID(pte)) { 1189 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1190 1191 return; 1192 } 1193 1194 mtx_lock_spin(&tlbivax_mutex); 1195 tlb_miss_lock(); 1196 1197 /* Invalidate entry in TLB0, update PTE. */ 1198 tlb0_flush_entry(va); 1199 *pte = 0; 1200 1201 tlb_miss_unlock(); 1202 mtx_unlock_spin(&tlbivax_mutex); 1203 } 1204 1205 /* 1206 * Figure out where a given kernel pointer (usually in a fault) points 1207 * to from the VM's perspective, potentially remapping into userland's 1208 * address space. 1209 */ 1210 static int 1211 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1212 vm_offset_t *decoded_addr) 1213 { 1214 1215 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS) 1216 *is_user = 1; 1217 else 1218 *is_user = 0; 1219 1220 *decoded_addr = addr; 1221 return (0); 1222 } 1223 1224 static bool 1225 mmu_booke_page_is_mapped(vm_page_t m) 1226 { 1227 1228 return (!TAILQ_EMPTY(&(m)->md.pv_list)); 1229 } 1230 1231 static bool 1232 mmu_booke_ps_enabled(pmap_t pmap __unused) 1233 { 1234 return (false); 1235 } 1236 1237 /* 1238 * Initialize pmap associated with process 0. 1239 */ 1240 static void 1241 mmu_booke_pinit0(pmap_t pmap) 1242 { 1243 1244 PMAP_LOCK_INIT(pmap); 1245 mmu_booke_pinit(pmap); 1246 PCPU_SET(curpmap, pmap); 1247 } 1248 1249 /* 1250 * Insert the given physical page at the specified virtual address in the 1251 * target physical map with the protection requested. If specified the page 1252 * will be wired down. 1253 */ 1254 static int 1255 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1256 vm_prot_t prot, u_int flags, int8_t psind) 1257 { 1258 int error; 1259 1260 rw_wlock(&pvh_global_lock); 1261 PMAP_LOCK(pmap); 1262 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind); 1263 PMAP_UNLOCK(pmap); 1264 rw_wunlock(&pvh_global_lock); 1265 return (error); 1266 } 1267 1268 static int 1269 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1270 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1271 { 1272 pte_t *pte; 1273 vm_paddr_t pa; 1274 pte_t flags; 1275 int error, su, sync; 1276 1277 pa = VM_PAGE_TO_PHYS(m); 1278 su = (pmap == kernel_pmap); 1279 sync = 0; 1280 1281 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1282 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1283 // (u_int32_t)pmap, su, pmap->pm_tid, 1284 // (u_int32_t)m, va, pa, prot, flags); 1285 1286 if (su) { 1287 KASSERT(((va >= virtual_avail) && 1288 (va <= VM_MAX_KERNEL_ADDRESS)), 1289 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1290 } else { 1291 KASSERT((va <= VM_MAXUSER_ADDRESS), 1292 ("mmu_booke_enter_locked: user pmap, non user va")); 1293 } 1294 if ((m->oflags & VPO_UNMANAGED) == 0) { 1295 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1296 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1297 else 1298 VM_OBJECT_ASSERT_LOCKED(m->object); 1299 } 1300 1301 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1302 1303 /* 1304 * If there is an existing mapping, and the physical address has not 1305 * changed, must be protection or wiring change. 1306 */ 1307 if (((pte = pte_find(pmap, va)) != NULL) && 1308 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1309 1310 /* 1311 * Before actually updating pte->flags we calculate and 1312 * prepare its new value in a helper var. 1313 */ 1314 flags = *pte; 1315 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1316 1317 /* Wiring change, just update stats. */ 1318 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1319 if (!PTE_ISWIRED(pte)) { 1320 flags |= PTE_WIRED; 1321 pmap->pm_stats.wired_count++; 1322 } 1323 } else { 1324 if (PTE_ISWIRED(pte)) { 1325 flags &= ~PTE_WIRED; 1326 pmap->pm_stats.wired_count--; 1327 } 1328 } 1329 1330 if (prot & VM_PROT_WRITE) { 1331 /* Add write permissions. */ 1332 flags |= PTE_SW; 1333 if (!su) 1334 flags |= PTE_UW; 1335 1336 if ((flags & PTE_MANAGED) != 0) 1337 vm_page_aflag_set(m, PGA_WRITEABLE); 1338 } else { 1339 /* Handle modified pages, sense modify status. */ 1340 1341 /* 1342 * The PTE_MODIFIED flag could be set by underlying 1343 * TLB misses since we last read it (above), possibly 1344 * other CPUs could update it so we check in the PTE 1345 * directly rather than rely on that saved local flags 1346 * copy. 1347 */ 1348 if (PTE_ISMODIFIED(pte)) 1349 vm_page_dirty(m); 1350 } 1351 1352 if (prot & VM_PROT_EXECUTE) { 1353 flags |= PTE_SX; 1354 if (!su) 1355 flags |= PTE_UX; 1356 1357 /* 1358 * Check existing flags for execute permissions: if we 1359 * are turning execute permissions on, icache should 1360 * be flushed. 1361 */ 1362 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1363 sync++; 1364 } 1365 1366 flags &= ~PTE_REFERENCED; 1367 1368 /* 1369 * The new flags value is all calculated -- only now actually 1370 * update the PTE. 1371 */ 1372 mtx_lock_spin(&tlbivax_mutex); 1373 tlb_miss_lock(); 1374 1375 tlb0_flush_entry(va); 1376 *pte &= ~PTE_FLAGS_MASK; 1377 *pte |= flags; 1378 1379 tlb_miss_unlock(); 1380 mtx_unlock_spin(&tlbivax_mutex); 1381 1382 } else { 1383 /* 1384 * If there is an existing mapping, but it's for a different 1385 * physical address, pte_enter() will delete the old mapping. 1386 */ 1387 //if ((pte != NULL) && PTE_ISVALID(pte)) 1388 // debugf("mmu_booke_enter_locked: replace\n"); 1389 //else 1390 // debugf("mmu_booke_enter_locked: new\n"); 1391 1392 /* Now set up the flags and install the new mapping. */ 1393 flags = (PTE_SR | PTE_VALID); 1394 flags |= PTE_M; 1395 1396 if (!su) 1397 flags |= PTE_UR; 1398 1399 if (prot & VM_PROT_WRITE) { 1400 flags |= PTE_SW; 1401 if (!su) 1402 flags |= PTE_UW; 1403 1404 if ((m->oflags & VPO_UNMANAGED) == 0) 1405 vm_page_aflag_set(m, PGA_WRITEABLE); 1406 } 1407 1408 if (prot & VM_PROT_EXECUTE) { 1409 flags |= PTE_SX; 1410 if (!su) 1411 flags |= PTE_UX; 1412 } 1413 1414 /* If its wired update stats. */ 1415 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1416 flags |= PTE_WIRED; 1417 1418 error = pte_enter(pmap, m, va, flags, 1419 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1420 if (error != 0) 1421 return (KERN_RESOURCE_SHORTAGE); 1422 1423 if ((flags & PMAP_ENTER_WIRED) != 0) 1424 pmap->pm_stats.wired_count++; 1425 1426 /* Flush the real memory from the instruction cache. */ 1427 if (prot & VM_PROT_EXECUTE) 1428 sync++; 1429 } 1430 1431 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1432 __syncicache((void *)va, PAGE_SIZE); 1433 sync = 0; 1434 } 1435 1436 return (KERN_SUCCESS); 1437 } 1438 1439 /* 1440 * Maps a sequence of resident pages belonging to the same object. 1441 * The sequence begins with the given page m_start. This page is 1442 * mapped at the given virtual address start. Each subsequent page is 1443 * mapped at a virtual address that is offset from start by the same 1444 * amount as the page is offset from m_start within the object. The 1445 * last page in the sequence is the page with the largest offset from 1446 * m_start that can be mapped at a virtual address less than the given 1447 * virtual address end. Not every virtual page between start and end 1448 * is mapped; only those for which a resident page exists with the 1449 * corresponding offset from m_start are mapped. 1450 */ 1451 static void 1452 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start, 1453 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1454 { 1455 vm_page_t m; 1456 vm_pindex_t diff, psize; 1457 1458 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1459 1460 psize = atop(end - start); 1461 m = m_start; 1462 rw_wlock(&pvh_global_lock); 1463 PMAP_LOCK(pmap); 1464 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1465 mmu_booke_enter_locked(pmap, start + ptoa(diff), m, 1466 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1467 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1468 m = TAILQ_NEXT(m, listq); 1469 } 1470 PMAP_UNLOCK(pmap); 1471 rw_wunlock(&pvh_global_lock); 1472 } 1473 1474 static void 1475 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, 1476 vm_prot_t prot) 1477 { 1478 1479 rw_wlock(&pvh_global_lock); 1480 PMAP_LOCK(pmap); 1481 mmu_booke_enter_locked(pmap, va, m, 1482 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1483 PMAP_ENTER_QUICK_LOCKED, 0); 1484 PMAP_UNLOCK(pmap); 1485 rw_wunlock(&pvh_global_lock); 1486 } 1487 1488 /* 1489 * Remove the given range of addresses from the specified map. 1490 * 1491 * It is assumed that the start and end are properly rounded to the page size. 1492 */ 1493 static void 1494 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1495 { 1496 pte_t *pte; 1497 uint8_t hold_flag; 1498 1499 int su = (pmap == kernel_pmap); 1500 1501 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1502 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1503 1504 if (su) { 1505 KASSERT(((va >= virtual_avail) && 1506 (va <= VM_MAX_KERNEL_ADDRESS)), 1507 ("mmu_booke_remove: kernel pmap, non kernel va")); 1508 } else { 1509 KASSERT((va <= VM_MAXUSER_ADDRESS), 1510 ("mmu_booke_remove: user pmap, non user va")); 1511 } 1512 1513 if (PMAP_REMOVE_DONE(pmap)) { 1514 //debugf("mmu_booke_remove: e (empty)\n"); 1515 return; 1516 } 1517 1518 hold_flag = PTBL_HOLD_FLAG(pmap); 1519 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1520 1521 rw_wlock(&pvh_global_lock); 1522 PMAP_LOCK(pmap); 1523 for (; va < endva; va += PAGE_SIZE) { 1524 pte = pte_find_next(pmap, &va); 1525 if ((pte == NULL) || !PTE_ISVALID(pte)) 1526 break; 1527 if (va >= endva) 1528 break; 1529 pte_remove(pmap, va, hold_flag); 1530 } 1531 PMAP_UNLOCK(pmap); 1532 rw_wunlock(&pvh_global_lock); 1533 1534 //debugf("mmu_booke_remove: e\n"); 1535 } 1536 1537 /* 1538 * Remove physical page from all pmaps in which it resides. 1539 */ 1540 static void 1541 mmu_booke_remove_all(vm_page_t m) 1542 { 1543 pv_entry_t pv, pvn; 1544 uint8_t hold_flag; 1545 1546 rw_wlock(&pvh_global_lock); 1547 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) { 1548 PMAP_LOCK(pv->pv_pmap); 1549 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1550 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag); 1551 PMAP_UNLOCK(pv->pv_pmap); 1552 } 1553 vm_page_aflag_clear(m, PGA_WRITEABLE); 1554 rw_wunlock(&pvh_global_lock); 1555 } 1556 1557 /* 1558 * Map a range of physical addresses into kernel virtual address space. 1559 */ 1560 static vm_offset_t 1561 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start, 1562 vm_paddr_t pa_end, int prot) 1563 { 1564 vm_offset_t sva = *virt; 1565 vm_offset_t va = sva; 1566 1567 #ifdef __powerpc64__ 1568 /* XXX: Handle memory not starting at 0x0. */ 1569 if (pa_end < ctob(Maxmem)) 1570 return (PHYS_TO_DMAP(pa_start)); 1571 #endif 1572 1573 while (pa_start < pa_end) { 1574 mmu_booke_kenter(va, pa_start); 1575 va += PAGE_SIZE; 1576 pa_start += PAGE_SIZE; 1577 } 1578 *virt = va; 1579 1580 return (sva); 1581 } 1582 1583 /* 1584 * The pmap must be activated before it's address space can be accessed in any 1585 * way. 1586 */ 1587 static void 1588 mmu_booke_activate(struct thread *td) 1589 { 1590 pmap_t pmap; 1591 u_int cpuid; 1592 1593 pmap = &td->td_proc->p_vmspace->vm_pmap; 1594 1595 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")", 1596 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1597 1598 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1599 1600 sched_pin(); 1601 1602 cpuid = PCPU_GET(cpuid); 1603 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1604 PCPU_SET(curpmap, pmap); 1605 1606 if (pmap->pm_tid[cpuid] == TID_NONE) 1607 tid_alloc(pmap); 1608 1609 /* Load PID0 register with pmap tid value. */ 1610 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1611 __asm __volatile("isync"); 1612 1613 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1614 1615 sched_unpin(); 1616 1617 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1618 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1619 } 1620 1621 /* 1622 * Deactivate the specified process's address space. 1623 */ 1624 static void 1625 mmu_booke_deactivate(struct thread *td) 1626 { 1627 pmap_t pmap; 1628 1629 pmap = &td->td_proc->p_vmspace->vm_pmap; 1630 1631 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX, 1632 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1633 1634 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 1635 1636 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1637 PCPU_SET(curpmap, NULL); 1638 } 1639 1640 /* 1641 * Copy the range specified by src_addr/len 1642 * from the source map to the range dst_addr/len 1643 * in the destination map. 1644 * 1645 * This routine is only advisory and need not do anything. 1646 */ 1647 static void 1648 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, 1649 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1650 { 1651 1652 } 1653 1654 /* 1655 * Set the physical protection on the specified range of this map as requested. 1656 */ 1657 static void 1658 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1659 vm_prot_t prot) 1660 { 1661 vm_offset_t va; 1662 vm_page_t m; 1663 pte_t *pte; 1664 1665 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1666 mmu_booke_remove(pmap, sva, eva); 1667 return; 1668 } 1669 1670 if (prot & VM_PROT_WRITE) 1671 return; 1672 1673 PMAP_LOCK(pmap); 1674 for (va = sva; va < eva; va += PAGE_SIZE) { 1675 if ((pte = pte_find(pmap, va)) != NULL) { 1676 if (PTE_ISVALID(pte)) { 1677 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1678 1679 mtx_lock_spin(&tlbivax_mutex); 1680 tlb_miss_lock(); 1681 1682 /* Handle modified pages. */ 1683 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1684 vm_page_dirty(m); 1685 1686 tlb0_flush_entry(va); 1687 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1688 1689 tlb_miss_unlock(); 1690 mtx_unlock_spin(&tlbivax_mutex); 1691 } 1692 } 1693 } 1694 PMAP_UNLOCK(pmap); 1695 } 1696 1697 /* 1698 * Clear the write and modified bits in each of the given page's mappings. 1699 */ 1700 static void 1701 mmu_booke_remove_write(vm_page_t m) 1702 { 1703 pv_entry_t pv; 1704 pte_t *pte; 1705 1706 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1707 ("mmu_booke_remove_write: page %p is not managed", m)); 1708 vm_page_assert_busied(m); 1709 1710 if (!pmap_page_is_write_mapped(m)) 1711 return; 1712 rw_wlock(&pvh_global_lock); 1713 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1714 PMAP_LOCK(pv->pv_pmap); 1715 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) { 1716 if (PTE_ISVALID(pte)) { 1717 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1718 1719 mtx_lock_spin(&tlbivax_mutex); 1720 tlb_miss_lock(); 1721 1722 /* Handle modified pages. */ 1723 if (PTE_ISMODIFIED(pte)) 1724 vm_page_dirty(m); 1725 1726 /* Flush mapping from TLB0. */ 1727 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1728 1729 tlb_miss_unlock(); 1730 mtx_unlock_spin(&tlbivax_mutex); 1731 } 1732 } 1733 PMAP_UNLOCK(pv->pv_pmap); 1734 } 1735 vm_page_aflag_clear(m, PGA_WRITEABLE); 1736 rw_wunlock(&pvh_global_lock); 1737 } 1738 1739 /* 1740 * Atomically extract and hold the physical page with the given 1741 * pmap and virtual address pair if that mapping permits the given 1742 * protection. 1743 */ 1744 static vm_page_t 1745 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va, 1746 vm_prot_t prot) 1747 { 1748 pte_t *pte; 1749 vm_page_t m; 1750 uint32_t pte_wbit; 1751 1752 m = NULL; 1753 PMAP_LOCK(pmap); 1754 pte = pte_find(pmap, va); 1755 if ((pte != NULL) && PTE_ISVALID(pte)) { 1756 if (pmap == kernel_pmap) 1757 pte_wbit = PTE_SW; 1758 else 1759 pte_wbit = PTE_UW; 1760 1761 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) { 1762 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1763 if (!vm_page_wire_mapped(m)) 1764 m = NULL; 1765 } 1766 } 1767 PMAP_UNLOCK(pmap); 1768 return (m); 1769 } 1770 1771 /* 1772 * Initialize a vm_page's machine-dependent fields. 1773 */ 1774 static void 1775 mmu_booke_page_init(vm_page_t m) 1776 { 1777 1778 m->md.pv_tracked = 0; 1779 TAILQ_INIT(&m->md.pv_list); 1780 } 1781 1782 /* 1783 * Return whether or not the specified physical page was modified 1784 * in any of physical maps. 1785 */ 1786 static bool 1787 mmu_booke_is_modified(vm_page_t m) 1788 { 1789 pte_t *pte; 1790 pv_entry_t pv; 1791 bool rv; 1792 1793 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1794 ("mmu_booke_is_modified: page %p is not managed", m)); 1795 rv = false; 1796 1797 /* 1798 * If the page is not busied then this check is racy. 1799 */ 1800 if (!pmap_page_is_write_mapped(m)) 1801 return (false); 1802 1803 rw_wlock(&pvh_global_lock); 1804 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1805 PMAP_LOCK(pv->pv_pmap); 1806 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1807 PTE_ISVALID(pte)) { 1808 if (PTE_ISMODIFIED(pte)) 1809 rv = true; 1810 } 1811 PMAP_UNLOCK(pv->pv_pmap); 1812 if (rv) 1813 break; 1814 } 1815 rw_wunlock(&pvh_global_lock); 1816 return (rv); 1817 } 1818 1819 /* 1820 * Return whether or not the specified virtual address is eligible 1821 * for prefault. 1822 */ 1823 static bool 1824 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1825 { 1826 1827 return (false); 1828 } 1829 1830 /* 1831 * Return whether or not the specified physical page was referenced 1832 * in any physical maps. 1833 */ 1834 static bool 1835 mmu_booke_is_referenced(vm_page_t m) 1836 { 1837 pte_t *pte; 1838 pv_entry_t pv; 1839 bool rv; 1840 1841 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1842 ("mmu_booke_is_referenced: page %p is not managed", m)); 1843 rv = false; 1844 rw_wlock(&pvh_global_lock); 1845 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1846 PMAP_LOCK(pv->pv_pmap); 1847 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1848 PTE_ISVALID(pte)) { 1849 if (PTE_ISREFERENCED(pte)) 1850 rv = true; 1851 } 1852 PMAP_UNLOCK(pv->pv_pmap); 1853 if (rv) 1854 break; 1855 } 1856 rw_wunlock(&pvh_global_lock); 1857 return (rv); 1858 } 1859 1860 /* 1861 * Clear the modify bits on the specified physical page. 1862 */ 1863 static void 1864 mmu_booke_clear_modify(vm_page_t m) 1865 { 1866 pte_t *pte; 1867 pv_entry_t pv; 1868 1869 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1870 ("mmu_booke_clear_modify: page %p is not managed", m)); 1871 vm_page_assert_busied(m); 1872 1873 if (!pmap_page_is_write_mapped(m)) 1874 return; 1875 1876 rw_wlock(&pvh_global_lock); 1877 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1878 PMAP_LOCK(pv->pv_pmap); 1879 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1880 PTE_ISVALID(pte)) { 1881 mtx_lock_spin(&tlbivax_mutex); 1882 tlb_miss_lock(); 1883 1884 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 1885 tlb0_flush_entry(pv->pv_va); 1886 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 1887 PTE_REFERENCED); 1888 } 1889 1890 tlb_miss_unlock(); 1891 mtx_unlock_spin(&tlbivax_mutex); 1892 } 1893 PMAP_UNLOCK(pv->pv_pmap); 1894 } 1895 rw_wunlock(&pvh_global_lock); 1896 } 1897 1898 /* 1899 * Return a count of reference bits for a page, clearing those bits. 1900 * It is not necessary for every reference bit to be cleared, but it 1901 * is necessary that 0 only be returned when there are truly no 1902 * reference bits set. 1903 * 1904 * As an optimization, update the page's dirty field if a modified bit is 1905 * found while counting reference bits. This opportunistic update can be 1906 * performed at low cost and can eliminate the need for some future calls 1907 * to pmap_is_modified(). However, since this function stops after 1908 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 1909 * dirty pages. Those dirty pages will only be detected by a future call 1910 * to pmap_is_modified(). 1911 */ 1912 static int 1913 mmu_booke_ts_referenced(vm_page_t m) 1914 { 1915 pte_t *pte; 1916 pv_entry_t pv; 1917 int count; 1918 1919 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1920 ("mmu_booke_ts_referenced: page %p is not managed", m)); 1921 count = 0; 1922 rw_wlock(&pvh_global_lock); 1923 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1924 PMAP_LOCK(pv->pv_pmap); 1925 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1926 PTE_ISVALID(pte)) { 1927 if (PTE_ISMODIFIED(pte)) 1928 vm_page_dirty(m); 1929 if (PTE_ISREFERENCED(pte)) { 1930 mtx_lock_spin(&tlbivax_mutex); 1931 tlb_miss_lock(); 1932 1933 tlb0_flush_entry(pv->pv_va); 1934 *pte &= ~PTE_REFERENCED; 1935 1936 tlb_miss_unlock(); 1937 mtx_unlock_spin(&tlbivax_mutex); 1938 1939 if (++count >= PMAP_TS_REFERENCED_MAX) { 1940 PMAP_UNLOCK(pv->pv_pmap); 1941 break; 1942 } 1943 } 1944 } 1945 PMAP_UNLOCK(pv->pv_pmap); 1946 } 1947 rw_wunlock(&pvh_global_lock); 1948 return (count); 1949 } 1950 1951 /* 1952 * Clear the wired attribute from the mappings for the specified range of 1953 * addresses in the given pmap. Every valid mapping within that range must 1954 * have the wired attribute set. In contrast, invalid mappings cannot have 1955 * the wired attribute set, so they are ignored. 1956 * 1957 * The wired attribute of the page table entry is not a hardware feature, so 1958 * there is no need to invalidate any TLB entries. 1959 */ 1960 static void 1961 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1962 { 1963 vm_offset_t va; 1964 pte_t *pte; 1965 1966 PMAP_LOCK(pmap); 1967 for (va = sva; va < eva; va += PAGE_SIZE) { 1968 if ((pte = pte_find(pmap, va)) != NULL && 1969 PTE_ISVALID(pte)) { 1970 if (!PTE_ISWIRED(pte)) 1971 panic("mmu_booke_unwire: pte %p isn't wired", 1972 pte); 1973 *pte &= ~PTE_WIRED; 1974 pmap->pm_stats.wired_count--; 1975 } 1976 } 1977 PMAP_UNLOCK(pmap); 1978 1979 } 1980 1981 /* 1982 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 1983 * page. This count may be changed upwards or downwards in the future; it is 1984 * only necessary that true be returned for a small subset of pmaps for proper 1985 * page aging. 1986 */ 1987 static bool 1988 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m) 1989 { 1990 pv_entry_t pv; 1991 int loops; 1992 bool rv; 1993 1994 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1995 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 1996 loops = 0; 1997 rv = false; 1998 rw_wlock(&pvh_global_lock); 1999 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2000 if (pv->pv_pmap == pmap) { 2001 rv = true; 2002 break; 2003 } 2004 if (++loops >= 16) 2005 break; 2006 } 2007 rw_wunlock(&pvh_global_lock); 2008 return (rv); 2009 } 2010 2011 /* 2012 * Return the number of managed mappings to the given physical page that are 2013 * wired. 2014 */ 2015 static int 2016 mmu_booke_page_wired_mappings(vm_page_t m) 2017 { 2018 pv_entry_t pv; 2019 pte_t *pte; 2020 int count = 0; 2021 2022 if ((m->oflags & VPO_UNMANAGED) != 0) 2023 return (count); 2024 rw_wlock(&pvh_global_lock); 2025 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2026 PMAP_LOCK(pv->pv_pmap); 2027 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) 2028 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2029 count++; 2030 PMAP_UNLOCK(pv->pv_pmap); 2031 } 2032 rw_wunlock(&pvh_global_lock); 2033 return (count); 2034 } 2035 2036 static int 2037 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2038 { 2039 int i; 2040 vm_offset_t va; 2041 2042 /* 2043 * This currently does not work for entries that 2044 * overlap TLB1 entries. 2045 */ 2046 for (i = 0; i < TLB1_ENTRIES; i ++) { 2047 if (tlb1_iomapped(i, pa, size, &va) == 0) 2048 return (0); 2049 } 2050 2051 return (EFAULT); 2052 } 2053 2054 void 2055 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2056 { 2057 vm_paddr_t ppa; 2058 vm_offset_t ofs; 2059 vm_size_t gran; 2060 2061 /* Minidumps are based on virtual memory addresses. */ 2062 if (do_minidump) { 2063 *va = (void *)(vm_offset_t)pa; 2064 return; 2065 } 2066 2067 /* Raw physical memory dumps don't have a virtual address. */ 2068 /* We always map a 256MB page at 256M. */ 2069 gran = 256 * 1024 * 1024; 2070 ppa = rounddown2(pa, gran); 2071 ofs = pa - ppa; 2072 *va = (void *)gran; 2073 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2074 2075 if (sz > (gran - ofs)) 2076 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2077 _TLB_ENTRY_IO); 2078 } 2079 2080 void 2081 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va) 2082 { 2083 vm_paddr_t ppa; 2084 vm_offset_t ofs; 2085 vm_size_t gran; 2086 tlb_entry_t e; 2087 int i; 2088 2089 /* Minidumps are based on virtual memory addresses. */ 2090 /* Nothing to do... */ 2091 if (do_minidump) 2092 return; 2093 2094 for (i = 0; i < TLB1_ENTRIES; i++) { 2095 tlb1_read_entry(&e, i); 2096 if (!(e.mas1 & MAS1_VALID)) 2097 break; 2098 } 2099 2100 /* Raw physical memory dumps don't have a virtual address. */ 2101 i--; 2102 e.mas1 = 0; 2103 e.mas2 = 0; 2104 e.mas3 = 0; 2105 tlb1_write_entry(&e, i); 2106 2107 gran = 256 * 1024 * 1024; 2108 ppa = rounddown2(pa, gran); 2109 ofs = pa - ppa; 2110 if (sz > (gran - ofs)) { 2111 i--; 2112 e.mas1 = 0; 2113 e.mas2 = 0; 2114 e.mas3 = 0; 2115 tlb1_write_entry(&e, i); 2116 } 2117 } 2118 2119 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2120 2121 void 2122 mmu_booke_scan_init(void) 2123 { 2124 vm_offset_t va; 2125 pte_t *pte; 2126 int i; 2127 2128 if (!do_minidump) { 2129 /* Initialize phys. segments for dumpsys(). */ 2130 memset(&dump_map, 0, sizeof(dump_map)); 2131 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2132 &availmem_regions_sz); 2133 for (i = 0; i < physmem_regions_sz; i++) { 2134 dump_map[i].pa_start = physmem_regions[i].mr_start; 2135 dump_map[i].pa_size = physmem_regions[i].mr_size; 2136 } 2137 return; 2138 } 2139 2140 /* Virtual segments for minidumps: */ 2141 memset(&dump_map, 0, sizeof(dump_map)); 2142 2143 /* 1st: kernel .data and .bss. */ 2144 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2145 dump_map[0].pa_size = 2146 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2147 2148 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2149 dump_map[1].pa_start = data_start; 2150 dump_map[1].pa_size = data_end - data_start; 2151 2152 /* 3rd: kernel VM. */ 2153 va = dump_map[1].pa_start + dump_map[1].pa_size; 2154 /* Find start of next chunk (from va). */ 2155 while (va < virtual_end) { 2156 /* Don't dump the buffer cache. */ 2157 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2158 va = kmi.buffer_eva; 2159 continue; 2160 } 2161 pte = pte_find(kernel_pmap, va); 2162 if (pte != NULL && PTE_ISVALID(pte)) 2163 break; 2164 va += PAGE_SIZE; 2165 } 2166 if (va < virtual_end) { 2167 dump_map[2].pa_start = va; 2168 va += PAGE_SIZE; 2169 /* Find last page in chunk. */ 2170 while (va < virtual_end) { 2171 /* Don't run into the buffer cache. */ 2172 if (va == kmi.buffer_sva) 2173 break; 2174 pte = pte_find(kernel_pmap, va); 2175 if (pte == NULL || !PTE_ISVALID(pte)) 2176 break; 2177 va += PAGE_SIZE; 2178 } 2179 dump_map[2].pa_size = va - dump_map[2].pa_start; 2180 } 2181 } 2182 2183 /* 2184 * Map a set of physical memory pages into the kernel virtual address space. 2185 * Return a pointer to where it is mapped. This routine is intended to be used 2186 * for mapping device memory, NOT real memory. 2187 */ 2188 static void * 2189 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size) 2190 { 2191 2192 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2193 } 2194 2195 static int 2196 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e) 2197 { 2198 int i; 2199 2200 for (i = 0; i < TLB1_ENTRIES; i++) { 2201 tlb1_read_entry(e, i); 2202 if ((e->mas1 & MAS1_VALID) == 0) 2203 continue; 2204 if (e->phys == pa) 2205 return (i); 2206 } 2207 return (-1); 2208 } 2209 2210 static void * 2211 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2212 { 2213 tlb_entry_t e; 2214 vm_paddr_t tmppa; 2215 #ifndef __powerpc64__ 2216 uintptr_t tmpva; 2217 #endif 2218 uintptr_t va, retva; 2219 vm_size_t sz; 2220 int i; 2221 int wimge; 2222 2223 /* 2224 * Check if this is premapped in TLB1. 2225 */ 2226 sz = size; 2227 tmppa = pa; 2228 va = ~0; 2229 wimge = tlb_calc_wimg(pa, ma); 2230 for (i = 0; i < TLB1_ENTRIES; i++) { 2231 tlb1_read_entry(&e, i); 2232 if (!(e.mas1 & MAS1_VALID)) 2233 continue; 2234 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))) 2235 continue; 2236 if (tmppa >= e.phys && tmppa < e.phys + e.size) { 2237 va = e.virt + (pa - e.phys); 2238 tmppa = e.phys + e.size; 2239 sz -= MIN(sz, e.size - (pa - e.phys)); 2240 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) { 2241 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))) 2242 break; 2243 sz -= MIN(sz, e.size); 2244 tmppa = e.phys + e.size; 2245 } 2246 if (sz != 0) 2247 break; 2248 return ((void *)va); 2249 } 2250 } 2251 2252 size = roundup(size, PAGE_SIZE); 2253 2254 #ifdef __powerpc64__ 2255 KASSERT(pa < VM_MAPDEV_PA_MAX, 2256 ("Unsupported physical address! %lx", pa)); 2257 va = VM_MAPDEV_BASE + pa; 2258 retva = va; 2259 #ifdef POW2_MAPPINGS 2260 /* 2261 * Align the mapping to a power of 2 size, taking into account that we 2262 * may need to increase the size multiple times to satisfy the size and 2263 * alignment requirements. 2264 * 2265 * This works in the general case because it's very rare (near never?) 2266 * to have different access properties (WIMG) within a single 2267 * power-of-two region. If a design does call for that, POW2_MAPPINGS 2268 * can be undefined, and exact mappings will be used instead. 2269 */ 2270 sz = size; 2271 size = roundup2(size, 1 << ilog2(size)); 2272 while (rounddown2(va, size) + size < va + sz) 2273 size <<= 1; 2274 va = rounddown2(va, size); 2275 pa = rounddown2(pa, size); 2276 #endif 2277 #else 2278 /* 2279 * The device mapping area is between VM_MAXUSER_ADDRESS and 2280 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 2281 */ 2282 #ifdef SPARSE_MAPDEV 2283 /* 2284 * With a sparse mapdev, align to the largest starting region. This 2285 * could feasibly be optimized for a 'best-fit' alignment, but that 2286 * calculation could be very costly. 2287 * Align to the smaller of: 2288 * - first set bit in overlap of (pa & size mask) 2289 * - largest size envelope 2290 * 2291 * It's possible the device mapping may start at a PA that's not larger 2292 * than the size mask, so we need to offset in to maximize the TLB entry 2293 * range and minimize the number of used TLB entries. 2294 */ 2295 do { 2296 tmpva = tlb1_map_base; 2297 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa); 2298 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1; 2299 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa); 2300 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 2301 #endif 2302 va = atomic_fetchadd_int(&tlb1_map_base, size); 2303 retva = va; 2304 #endif 2305 2306 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size) 2307 return (NULL); 2308 2309 return ((void *)retva); 2310 } 2311 2312 /* 2313 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2314 */ 2315 static void 2316 mmu_booke_unmapdev(void *p, vm_size_t size) 2317 { 2318 #ifdef SUPPORTS_SHRINKING_TLB1 2319 vm_offset_t base, offset, va; 2320 2321 /* 2322 * Unmap only if this is inside kernel virtual space. 2323 */ 2324 va = (vm_offset_t)p; 2325 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2326 base = trunc_page(va); 2327 offset = va & PAGE_MASK; 2328 size = roundup(offset + size, PAGE_SIZE); 2329 mmu_booke_qremove(base, atop(size)); 2330 kva_free(base, size); 2331 } 2332 #endif 2333 } 2334 2335 /* 2336 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2337 * specified pmap. This eliminates the blast of soft faults on process startup 2338 * and immediately after an mmap. 2339 */ 2340 static void 2341 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr, 2342 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2343 { 2344 2345 VM_OBJECT_ASSERT_WLOCKED(object); 2346 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2347 ("mmu_booke_object_init_pt: non-device object")); 2348 } 2349 2350 /* 2351 * Perform the pmap work for mincore. 2352 */ 2353 static int 2354 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 2355 { 2356 2357 /* XXX: this should be implemented at some point */ 2358 return (0); 2359 } 2360 2361 static int 2362 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode) 2363 { 2364 vm_offset_t va; 2365 pte_t *pte; 2366 int i, j; 2367 tlb_entry_t e; 2368 2369 addr = trunc_page(addr); 2370 2371 /* Only allow changes to mapped kernel addresses. This includes: 2372 * - KVA 2373 * - DMAP (powerpc64) 2374 * - Device mappings 2375 */ 2376 if (addr <= VM_MAXUSER_ADDRESS || 2377 #ifdef __powerpc64__ 2378 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) || 2379 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) || 2380 #else 2381 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) || 2382 #endif 2383 (addr > VM_MAX_KERNEL_ADDRESS)) 2384 return (EINVAL); 2385 2386 /* Check TLB1 mappings */ 2387 for (i = 0; i < TLB1_ENTRIES; i++) { 2388 tlb1_read_entry(&e, i); 2389 if (!(e.mas1 & MAS1_VALID)) 2390 continue; 2391 if (addr >= e.virt && addr < e.virt + e.size) 2392 break; 2393 } 2394 if (i < TLB1_ENTRIES) { 2395 /* Only allow full mappings to be modified for now. */ 2396 /* Validate the range. */ 2397 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 2398 tlb1_read_entry(&e, j); 2399 if (va != e.virt || (sz - (va - addr) < e.size)) 2400 return (EINVAL); 2401 } 2402 for (va = addr; va < addr + sz; va += e.size, i++) { 2403 tlb1_read_entry(&e, i); 2404 e.mas2 &= ~MAS2_WIMGE_MASK; 2405 e.mas2 |= tlb_calc_wimg(e.phys, mode); 2406 2407 /* 2408 * Write it out to the TLB. Should really re-sync with other 2409 * cores. 2410 */ 2411 tlb1_write_entry(&e, i); 2412 } 2413 return (0); 2414 } 2415 2416 /* Not in TLB1, try through pmap */ 2417 /* First validate the range. */ 2418 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2419 pte = pte_find(kernel_pmap, va); 2420 if (pte == NULL || !PTE_ISVALID(pte)) 2421 return (EINVAL); 2422 } 2423 2424 mtx_lock_spin(&tlbivax_mutex); 2425 tlb_miss_lock(); 2426 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2427 pte = pte_find(kernel_pmap, va); 2428 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2429 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 2430 tlb0_flush_entry(va); 2431 } 2432 tlb_miss_unlock(); 2433 mtx_unlock_spin(&tlbivax_mutex); 2434 2435 return (0); 2436 } 2437 2438 static void 2439 mmu_booke_page_array_startup(long pages) 2440 { 2441 vm_page_array_size = pages; 2442 } 2443 2444 /**************************************************************************/ 2445 /* TID handling */ 2446 /**************************************************************************/ 2447 2448 /* 2449 * Allocate a TID. If necessary, steal one from someone else. 2450 * The new TID is flushed from the TLB before returning. 2451 */ 2452 static tlbtid_t 2453 tid_alloc(pmap_t pmap) 2454 { 2455 tlbtid_t tid; 2456 int thiscpu; 2457 2458 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2459 2460 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2461 2462 thiscpu = PCPU_GET(cpuid); 2463 2464 tid = PCPU_GET(booke.tid_next); 2465 if (tid > TID_MAX) 2466 tid = TID_MIN; 2467 PCPU_SET(booke.tid_next, tid + 1); 2468 2469 /* If we are stealing TID then clear the relevant pmap's field */ 2470 if (tidbusy[thiscpu][tid] != NULL) { 2471 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2472 2473 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2474 2475 /* Flush all entries from TLB0 matching this TID. */ 2476 tid_flush(tid); 2477 } 2478 2479 tidbusy[thiscpu][tid] = pmap; 2480 pmap->pm_tid[thiscpu] = tid; 2481 __asm __volatile("msync; isync"); 2482 2483 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2484 PCPU_GET(booke.tid_next)); 2485 2486 return (tid); 2487 } 2488 2489 /**************************************************************************/ 2490 /* TLB0 handling */ 2491 /**************************************************************************/ 2492 2493 /* Convert TLB0 va and way number to tlb0[] table index. */ 2494 static inline unsigned int 2495 tlb0_tableidx(vm_offset_t va, unsigned int way) 2496 { 2497 unsigned int idx; 2498 2499 idx = (way * TLB0_ENTRIES_PER_WAY); 2500 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2501 return (idx); 2502 } 2503 2504 /* 2505 * Invalidate TLB0 entry. 2506 */ 2507 static inline void 2508 tlb0_flush_entry(vm_offset_t va) 2509 { 2510 2511 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2512 2513 mtx_assert(&tlbivax_mutex, MA_OWNED); 2514 2515 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2516 __asm __volatile("isync; msync"); 2517 __asm __volatile("tlbsync; msync"); 2518 2519 CTR1(KTR_PMAP, "%s: e", __func__); 2520 } 2521 2522 /**************************************************************************/ 2523 /* TLB1 handling */ 2524 /**************************************************************************/ 2525 2526 /* 2527 * TLB1 mapping notes: 2528 * 2529 * TLB1[0] Kernel text and data. 2530 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2531 * windows, other devices mappings. 2532 */ 2533 2534 /* 2535 * Read an entry from given TLB1 slot. 2536 */ 2537 void 2538 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 2539 { 2540 register_t msr; 2541 uint32_t mas0; 2542 2543 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 2544 2545 msr = mfmsr(); 2546 __asm __volatile("wrteei 0"); 2547 2548 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 2549 mtspr(SPR_MAS0, mas0); 2550 __asm __volatile("isync; tlbre"); 2551 2552 entry->mas1 = mfspr(SPR_MAS1); 2553 entry->mas2 = mfspr(SPR_MAS2); 2554 entry->mas3 = mfspr(SPR_MAS3); 2555 2556 switch ((mfpvr() >> 16) & 0xFFFF) { 2557 case FSL_E500v2: 2558 case FSL_E500mc: 2559 case FSL_E5500: 2560 case FSL_E6500: 2561 entry->mas7 = mfspr(SPR_MAS7); 2562 break; 2563 default: 2564 entry->mas7 = 0; 2565 break; 2566 } 2567 __asm __volatile("wrtee %0" :: "r"(msr)); 2568 2569 entry->virt = entry->mas2 & MAS2_EPN_MASK; 2570 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 2571 (entry->mas3 & MAS3_RPN); 2572 entry->size = 2573 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 2574 } 2575 2576 struct tlbwrite_args { 2577 tlb_entry_t *e; 2578 unsigned int idx; 2579 }; 2580 2581 static uint32_t 2582 tlb1_find_free(void) 2583 { 2584 tlb_entry_t e; 2585 int i; 2586 2587 for (i = 0; i < TLB1_ENTRIES; i++) { 2588 tlb1_read_entry(&e, i); 2589 if ((e.mas1 & MAS1_VALID) == 0) 2590 return (i); 2591 } 2592 return (-1); 2593 } 2594 2595 static void 2596 tlb1_purge_va_range(vm_offset_t va, vm_size_t size) 2597 { 2598 tlb_entry_t e; 2599 int i; 2600 2601 for (i = 0; i < TLB1_ENTRIES; i++) { 2602 tlb1_read_entry(&e, i); 2603 if ((e.mas1 & MAS1_VALID) == 0) 2604 continue; 2605 if ((e.mas2 & MAS2_EPN_MASK) >= va && 2606 (e.mas2 & MAS2_EPN_MASK) < va + size) { 2607 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID); 2608 __asm __volatile("isync; tlbwe; isync; msync"); 2609 } 2610 } 2611 } 2612 2613 static void 2614 tlb1_write_entry_int(void *arg) 2615 { 2616 struct tlbwrite_args *args = arg; 2617 uint32_t idx, mas0; 2618 2619 idx = args->idx; 2620 if (idx == -1) { 2621 tlb1_purge_va_range(args->e->virt, args->e->size); 2622 idx = tlb1_find_free(); 2623 if (idx == -1) 2624 panic("No free TLB1 entries!\n"); 2625 } 2626 /* Select entry */ 2627 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2628 2629 mtspr(SPR_MAS0, mas0); 2630 mtspr(SPR_MAS1, args->e->mas1); 2631 mtspr(SPR_MAS2, args->e->mas2); 2632 mtspr(SPR_MAS3, args->e->mas3); 2633 switch ((mfpvr() >> 16) & 0xFFFF) { 2634 case FSL_E500mc: 2635 case FSL_E5500: 2636 case FSL_E6500: 2637 mtspr(SPR_MAS8, 0); 2638 /* FALLTHROUGH */ 2639 case FSL_E500v2: 2640 mtspr(SPR_MAS7, args->e->mas7); 2641 break; 2642 default: 2643 break; 2644 } 2645 2646 __asm __volatile("isync; tlbwe; isync; msync"); 2647 2648 } 2649 2650 static void 2651 tlb1_write_entry_sync(void *arg) 2652 { 2653 /* Empty synchronization point for smp_rendezvous(). */ 2654 } 2655 2656 /* 2657 * Write given entry to TLB1 hardware. 2658 */ 2659 static void 2660 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 2661 { 2662 struct tlbwrite_args args; 2663 2664 args.e = e; 2665 args.idx = idx; 2666 2667 #ifdef SMP 2668 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) { 2669 mb(); 2670 smp_rendezvous(tlb1_write_entry_sync, 2671 tlb1_write_entry_int, 2672 tlb1_write_entry_sync, &args); 2673 } else 2674 #endif 2675 { 2676 register_t msr; 2677 2678 msr = mfmsr(); 2679 __asm __volatile("wrteei 0"); 2680 tlb1_write_entry_int(&args); 2681 __asm __volatile("wrtee %0" :: "r"(msr)); 2682 } 2683 } 2684 2685 /* 2686 * Convert TLB TSIZE value to mapped region size. 2687 */ 2688 static vm_size_t 2689 tsize2size(unsigned int tsize) 2690 { 2691 2692 /* 2693 * size = 4^tsize KB 2694 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2695 */ 2696 2697 return ((1 << (2 * tsize)) * 1024); 2698 } 2699 2700 /* 2701 * Convert region size (must be power of 4) to TLB TSIZE value. 2702 */ 2703 static unsigned int 2704 size2tsize(vm_size_t size) 2705 { 2706 2707 return (ilog2(size) / 2 - 5); 2708 } 2709 2710 /* 2711 * Register permanent kernel mapping in TLB1. 2712 * 2713 * Entries are created starting from index 0 (current free entry is 2714 * kept in tlb1_idx) and are not supposed to be invalidated. 2715 */ 2716 int 2717 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 2718 uint32_t flags) 2719 { 2720 tlb_entry_t e; 2721 uint32_t ts, tid; 2722 int tsize, index; 2723 2724 /* First try to update an existing entry. */ 2725 for (index = 0; index < TLB1_ENTRIES; index++) { 2726 tlb1_read_entry(&e, index); 2727 /* Check if we're just updating the flags, and update them. */ 2728 if (e.phys == pa && e.virt == va && e.size == size) { 2729 e.mas2 = (va & MAS2_EPN_MASK) | flags; 2730 tlb1_write_entry(&e, index); 2731 return (0); 2732 } 2733 } 2734 2735 /* Convert size to TSIZE */ 2736 tsize = size2tsize(size); 2737 2738 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2739 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2740 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2741 2742 e.phys = pa; 2743 e.virt = va; 2744 e.size = size; 2745 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2746 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2747 e.mas2 = (va & MAS2_EPN_MASK) | flags; 2748 2749 /* Set supervisor RWX permission bits */ 2750 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2751 e.mas7 = (pa >> 32) & MAS7_RPN; 2752 2753 tlb1_write_entry(&e, -1); 2754 2755 return (0); 2756 } 2757 2758 /* 2759 * Map in contiguous RAM region into the TLB1. 2760 */ 2761 static vm_size_t 2762 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge) 2763 { 2764 vm_offset_t base; 2765 vm_size_t mapped, sz, ssize; 2766 2767 mapped = 0; 2768 base = va; 2769 ssize = size; 2770 2771 while (size > 0) { 2772 sz = 1UL << (ilog2(size) & ~1); 2773 /* Align size to PA */ 2774 if (pa % sz != 0) { 2775 do { 2776 sz >>= 2; 2777 } while (pa % sz != 0); 2778 } 2779 /* Now align from there to VA */ 2780 if (va % sz != 0) { 2781 do { 2782 sz >>= 2; 2783 } while (va % sz != 0); 2784 } 2785 #ifdef __powerpc64__ 2786 /* 2787 * Clamp TLB1 entries to 4G. 2788 * 2789 * While the e6500 supports up to 1TB mappings, the e5500 2790 * only supports up to 4G mappings. (0b1011) 2791 * 2792 * If any e6500 machines capable of supporting a very 2793 * large amount of memory appear in the future, we can 2794 * revisit this. 2795 * 2796 * For now, though, since we have plenty of space in TLB1, 2797 * always avoid creating entries larger than 4GB. 2798 */ 2799 sz = MIN(sz, 1UL << 32); 2800 #endif 2801 if (bootverbose) 2802 printf("Wiring VA=%p to PA=%jx (size=%lx)\n", 2803 (void *)va, (uintmax_t)pa, (long)sz); 2804 if (tlb1_set_entry(va, pa, sz, 2805 _TLB_ENTRY_SHARED | wimge) < 0) 2806 return (mapped); 2807 size -= sz; 2808 pa += sz; 2809 va += sz; 2810 } 2811 2812 mapped = (va - base); 2813 if (bootverbose) 2814 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n", 2815 mapped, mapped - ssize); 2816 2817 return (mapped); 2818 } 2819 2820 /* 2821 * TLB1 initialization routine, to be called after the very first 2822 * assembler level setup done in locore.S. 2823 */ 2824 void 2825 tlb1_init(void) 2826 { 2827 vm_offset_t mas2; 2828 uint32_t mas0, mas1, mas3, mas7; 2829 uint32_t tsz; 2830 2831 tlb1_get_tlbconf(); 2832 2833 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 2834 mtspr(SPR_MAS0, mas0); 2835 __asm __volatile("isync; tlbre"); 2836 2837 mas1 = mfspr(SPR_MAS1); 2838 mas2 = mfspr(SPR_MAS2); 2839 mas3 = mfspr(SPR_MAS3); 2840 mas7 = mfspr(SPR_MAS7); 2841 2842 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 2843 (mas3 & MAS3_RPN); 2844 2845 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2846 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 2847 kernstart = trunc_page(mas2); 2848 2849 /* Setup TLB miss defaults */ 2850 set_mas4_defaults(); 2851 } 2852 2853 /* 2854 * pmap_early_io_unmap() should be used in short conjunction with 2855 * pmap_early_io_map(), as in the following snippet: 2856 * 2857 * x = pmap_early_io_map(...); 2858 * <do something with x> 2859 * pmap_early_io_unmap(x, size); 2860 * 2861 * And avoiding more allocations between. 2862 */ 2863 void 2864 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 2865 { 2866 int i; 2867 tlb_entry_t e; 2868 vm_size_t isize; 2869 2870 size = roundup(size, PAGE_SIZE); 2871 isize = size; 2872 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 2873 tlb1_read_entry(&e, i); 2874 if (!(e.mas1 & MAS1_VALID)) 2875 continue; 2876 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 2877 size -= e.size; 2878 e.mas1 &= ~MAS1_VALID; 2879 tlb1_write_entry(&e, i); 2880 } 2881 } 2882 if (tlb1_map_base == va + isize) 2883 tlb1_map_base -= isize; 2884 } 2885 2886 vm_offset_t 2887 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 2888 { 2889 vm_paddr_t pa_base; 2890 vm_offset_t va, sz; 2891 int i; 2892 tlb_entry_t e; 2893 2894 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 2895 2896 for (i = 0; i < TLB1_ENTRIES; i++) { 2897 tlb1_read_entry(&e, i); 2898 if (!(e.mas1 & MAS1_VALID)) 2899 continue; 2900 if (pa >= e.phys && (pa + size) <= 2901 (e.phys + e.size)) 2902 return (e.virt + (pa - e.phys)); 2903 } 2904 2905 pa_base = rounddown(pa, PAGE_SIZE); 2906 size = roundup(size + (pa - pa_base), PAGE_SIZE); 2907 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 2908 va = tlb1_map_base + (pa - pa_base); 2909 2910 do { 2911 sz = 1 << (ilog2(size) & ~1); 2912 tlb1_set_entry(tlb1_map_base, pa_base, sz, 2913 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 2914 size -= sz; 2915 pa_base += sz; 2916 tlb1_map_base += sz; 2917 } while (size > 0); 2918 2919 return (va); 2920 } 2921 2922 void 2923 pmap_track_page(pmap_t pmap, vm_offset_t va) 2924 { 2925 vm_paddr_t pa; 2926 vm_page_t page; 2927 struct pv_entry *pve; 2928 2929 va = trunc_page(va); 2930 pa = pmap_kextract(va); 2931 page = PHYS_TO_VM_PAGE(pa); 2932 2933 rw_wlock(&pvh_global_lock); 2934 PMAP_LOCK(pmap); 2935 2936 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 2937 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 2938 goto out; 2939 } 2940 } 2941 page->md.pv_tracked = true; 2942 pv_insert(pmap, va, page); 2943 out: 2944 PMAP_UNLOCK(pmap); 2945 rw_wunlock(&pvh_global_lock); 2946 } 2947 2948 /* 2949 * Setup MAS4 defaults. 2950 * These values are loaded to MAS0-2 on a TLB miss. 2951 */ 2952 static void 2953 set_mas4_defaults(void) 2954 { 2955 uint32_t mas4; 2956 2957 /* Defaults: TLB0, PID0, TSIZED=4K */ 2958 mas4 = MAS4_TLBSELD0; 2959 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 2960 #ifdef SMP 2961 mas4 |= MAS4_MD; 2962 #endif 2963 mtspr(SPR_MAS4, mas4); 2964 __asm __volatile("isync"); 2965 } 2966 2967 /* 2968 * Return 0 if the physical IO range is encompassed by one of the 2969 * the TLB1 entries, otherwise return related error code. 2970 */ 2971 static int 2972 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 2973 { 2974 uint32_t prot; 2975 vm_paddr_t pa_start; 2976 vm_paddr_t pa_end; 2977 unsigned int entry_tsize; 2978 vm_size_t entry_size; 2979 tlb_entry_t e; 2980 2981 *va = (vm_offset_t)NULL; 2982 2983 tlb1_read_entry(&e, i); 2984 /* Skip invalid entries */ 2985 if (!(e.mas1 & MAS1_VALID)) 2986 return (EINVAL); 2987 2988 /* 2989 * The entry must be cache-inhibited, guarded, and r/w 2990 * so it can function as an i/o page 2991 */ 2992 prot = e.mas2 & (MAS2_I | MAS2_G); 2993 if (prot != (MAS2_I | MAS2_G)) 2994 return (EPERM); 2995 2996 prot = e.mas3 & (MAS3_SR | MAS3_SW); 2997 if (prot != (MAS3_SR | MAS3_SW)) 2998 return (EPERM); 2999 3000 /* The address should be within the entry range. */ 3001 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3002 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3003 3004 entry_size = tsize2size(entry_tsize); 3005 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 3006 (e.mas3 & MAS3_RPN); 3007 pa_end = pa_start + entry_size; 3008 3009 if ((pa < pa_start) || ((pa + size) > pa_end)) 3010 return (ERANGE); 3011 3012 /* Return virtual address of this mapping. */ 3013 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3014 return (0); 3015 } 3016 3017 #ifdef DDB 3018 /* Print out contents of the MAS registers for each TLB0 entry */ 3019 static void 3020 #ifdef __powerpc64__ 3021 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3, 3022 #else 3023 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3024 #endif 3025 uint32_t mas7) 3026 { 3027 int as; 3028 char desc[3]; 3029 tlbtid_t tid; 3030 vm_size_t size; 3031 unsigned int tsize; 3032 3033 desc[2] = '\0'; 3034 if (mas1 & MAS1_VALID) 3035 desc[0] = 'V'; 3036 else 3037 desc[0] = ' '; 3038 3039 if (mas1 & MAS1_IPROT) 3040 desc[1] = 'P'; 3041 else 3042 desc[1] = ' '; 3043 3044 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3045 tid = MAS1_GETTID(mas1); 3046 3047 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3048 size = 0; 3049 if (tsize) 3050 size = tsize2size(tsize); 3051 3052 printf("%3d: (%s) [AS=%d] " 3053 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x " 3054 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3055 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7); 3056 } 3057 3058 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries) 3059 { 3060 uint32_t mas0, mas1, mas3, mas7; 3061 #ifdef __powerpc64__ 3062 uint64_t mas2; 3063 #else 3064 uint32_t mas2; 3065 #endif 3066 int entryidx, way, idx; 3067 3068 printf("TLB0 entries:\n"); 3069 for (way = 0; way < TLB0_WAYS; way ++) 3070 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3071 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3072 mtspr(SPR_MAS0, mas0); 3073 3074 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3075 mtspr(SPR_MAS2, mas2); 3076 3077 __asm __volatile("isync; tlbre"); 3078 3079 mas1 = mfspr(SPR_MAS1); 3080 mas2 = mfspr(SPR_MAS2); 3081 mas3 = mfspr(SPR_MAS3); 3082 mas7 = mfspr(SPR_MAS7); 3083 3084 idx = tlb0_tableidx(mas2, way); 3085 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3086 } 3087 } 3088 3089 /* 3090 * Print out contents of the MAS registers for each TLB1 entry 3091 */ 3092 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries) 3093 { 3094 uint32_t mas0, mas1, mas3, mas7; 3095 #ifdef __powerpc64__ 3096 uint64_t mas2; 3097 #else 3098 uint32_t mas2; 3099 #endif 3100 int i; 3101 3102 printf("TLB1 entries:\n"); 3103 for (i = 0; i < TLB1_ENTRIES; i++) { 3104 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3105 mtspr(SPR_MAS0, mas0); 3106 3107 __asm __volatile("isync; tlbre"); 3108 3109 mas1 = mfspr(SPR_MAS1); 3110 mas2 = mfspr(SPR_MAS2); 3111 mas3 = mfspr(SPR_MAS3); 3112 mas7 = mfspr(SPR_MAS7); 3113 3114 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3115 } 3116 } 3117 #endif 3118