1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * 32-bit pmap: 40 * Virtual address space layout: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA 47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 51 * 52 * 64-bit pmap: 53 * Virtual address space layout: 54 * ----------------------------- 55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process 56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries 57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region 58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack 59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved 60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data 61 * endkernel - msgbufp-1 : flat device tree 62 * msgbufp - ptbl_bufs-1 : message buffer 63 * ptbl_bufs - kernel_pdir-1 : kernel page tables 64 * kernel_pdir - kernel_pp2d-1 : kernel page directory 65 * kernel_pp2d - . : kernel pointers to page directory 66 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy 67 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs 68 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables 69 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space 70 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region 71 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region 72 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map 73 * 0xf000_0000_0000_0000 - +Maxmem : physmem map 74 * - 0xffff_ffff_ffff_ffff : device direct map 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include "opt_ddb.h" 81 #include "opt_kstack_pages.h" 82 83 #include <sys/param.h> 84 #include <sys/conf.h> 85 #include <sys/malloc.h> 86 #include <sys/ktr.h> 87 #include <sys/proc.h> 88 #include <sys/user.h> 89 #include <sys/queue.h> 90 #include <sys/systm.h> 91 #include <sys/kernel.h> 92 #include <sys/kerneldump.h> 93 #include <sys/linker.h> 94 #include <sys/msgbuf.h> 95 #include <sys/lock.h> 96 #include <sys/mutex.h> 97 #include <sys/rwlock.h> 98 #include <sys/sched.h> 99 #include <sys/smp.h> 100 #include <sys/vmmeter.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_page.h> 104 #include <vm/vm_kern.h> 105 #include <vm/vm_pageout.h> 106 #include <vm/vm_extern.h> 107 #include <vm/vm_object.h> 108 #include <vm/vm_param.h> 109 #include <vm/vm_map.h> 110 #include <vm/vm_pager.h> 111 #include <vm/vm_phys.h> 112 #include <vm/vm_pagequeue.h> 113 #include <vm/uma.h> 114 115 #include <machine/_inttypes.h> 116 #include <machine/cpu.h> 117 #include <machine/pcb.h> 118 #include <machine/platform.h> 119 120 #include <machine/tlb.h> 121 #include <machine/spr.h> 122 #include <machine/md_var.h> 123 #include <machine/mmuvar.h> 124 #include <machine/pmap.h> 125 #include <machine/pte.h> 126 127 #include <ddb/ddb.h> 128 129 #include "mmu_if.h" 130 131 #define SPARSE_MAPDEV 132 #ifdef DEBUG 133 #define debugf(fmt, args...) printf(fmt, ##args) 134 #else 135 #define debugf(fmt, args...) 136 #endif 137 138 #ifdef __powerpc64__ 139 #define PRI0ptrX "016lx" 140 #else 141 #define PRI0ptrX "08x" 142 #endif 143 144 #define TODO panic("%s: not implemented", __func__); 145 146 extern unsigned char _etext[]; 147 extern unsigned char _end[]; 148 149 extern uint32_t *bootinfo; 150 151 vm_paddr_t kernload; 152 vm_offset_t kernstart; 153 vm_size_t kernsize; 154 155 /* Message buffer and tables. */ 156 static vm_offset_t data_start; 157 static vm_size_t data_end; 158 159 /* Phys/avail memory regions. */ 160 static struct mem_region *availmem_regions; 161 static int availmem_regions_sz; 162 static struct mem_region *physmem_regions; 163 static int physmem_regions_sz; 164 165 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 166 static vm_offset_t zero_page_va; 167 static struct mtx zero_page_mutex; 168 169 static struct mtx tlbivax_mutex; 170 171 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 172 static vm_offset_t copy_page_src_va; 173 static vm_offset_t copy_page_dst_va; 174 static struct mtx copy_page_mutex; 175 176 /**************************************************************************/ 177 /* PMAP */ 178 /**************************************************************************/ 179 180 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 181 vm_prot_t, u_int flags, int8_t psind); 182 183 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 184 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 185 #ifdef __powerpc64__ 186 unsigned int kernel_pdirs; 187 #endif 188 189 /* 190 * If user pmap is processed with mmu_booke_remove and the resident count 191 * drops to 0, there are no more pages to remove, so we need not continue. 192 */ 193 #define PMAP_REMOVE_DONE(pmap) \ 194 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 195 196 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 197 extern int elf32_nxstack; 198 #endif 199 200 /**************************************************************************/ 201 /* TLB and TID handling */ 202 /**************************************************************************/ 203 204 /* Translation ID busy table */ 205 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 206 207 /* 208 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 209 * core revisions and should be read from h/w registers during early config. 210 */ 211 uint32_t tlb0_entries; 212 uint32_t tlb0_ways; 213 uint32_t tlb0_entries_per_way; 214 uint32_t tlb1_entries; 215 216 #define TLB0_ENTRIES (tlb0_entries) 217 #define TLB0_WAYS (tlb0_ways) 218 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 219 220 #define TLB1_ENTRIES (tlb1_entries) 221 222 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE; 223 224 static tlbtid_t tid_alloc(struct pmap *); 225 static void tid_flush(tlbtid_t tid); 226 227 #ifdef DDB 228 #ifdef __powerpc64__ 229 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t); 230 #else 231 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 232 #endif 233 #endif 234 235 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 236 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 237 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 238 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 239 240 static vm_size_t tsize2size(unsigned int); 241 static unsigned int size2tsize(vm_size_t); 242 static unsigned int ilog2(unsigned long); 243 244 static void set_mas4_defaults(void); 245 246 static inline void tlb0_flush_entry(vm_offset_t); 247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 248 249 /**************************************************************************/ 250 /* Page table management */ 251 /**************************************************************************/ 252 253 static struct rwlock_padalign pvh_global_lock; 254 255 /* Data for the pv entry allocation mechanism */ 256 static uma_zone_t pvzone; 257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 258 259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 260 261 #ifndef PMAP_SHPGPERPROC 262 #define PMAP_SHPGPERPROC 200 263 #endif 264 265 static void ptbl_init(void); 266 static struct ptbl_buf *ptbl_buf_alloc(void); 267 static void ptbl_buf_free(struct ptbl_buf *); 268 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 269 270 #ifdef __powerpc64__ 271 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **, 272 unsigned int, boolean_t); 273 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int); 274 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int); 275 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t); 276 #else 277 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 278 static void ptbl_free(mmu_t, pmap_t, unsigned int); 279 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 280 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 281 #endif 282 283 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 284 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 285 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 286 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 287 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t); 288 289 static pv_entry_t pv_alloc(void); 290 static void pv_free(pv_entry_t); 291 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 292 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 293 294 static void booke_pmap_init_qpages(void); 295 296 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 297 #ifdef __powerpc64__ 298 #define PTBL_BUFS (16UL * 16 * 16) 299 #else 300 #define PTBL_BUFS (128 * 16) 301 #endif 302 303 struct ptbl_buf { 304 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 305 vm_offset_t kva; /* va of mapping */ 306 }; 307 308 /* ptbl free list and a lock used for access synchronization. */ 309 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 310 static struct mtx ptbl_buf_freelist_lock; 311 312 /* Base address of kva space allocated fot ptbl bufs. */ 313 static vm_offset_t ptbl_buf_pool_vabase; 314 315 /* Pointer to ptbl_buf structures. */ 316 static struct ptbl_buf *ptbl_bufs; 317 318 #ifdef SMP 319 extern tlb_entry_t __boot_tlb1[]; 320 void pmap_bootstrap_ap(volatile uint32_t *); 321 #endif 322 323 /* 324 * Kernel MMU interface 325 */ 326 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 327 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 328 vm_size_t, vm_offset_t); 329 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 330 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 331 vm_offset_t, vm_page_t *, vm_offset_t, int); 332 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 333 vm_prot_t, u_int flags, int8_t psind); 334 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 335 vm_page_t, vm_prot_t); 336 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 337 vm_prot_t); 338 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 339 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 340 vm_prot_t); 341 static void mmu_booke_init(mmu_t); 342 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 343 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 344 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 345 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 346 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 347 int); 348 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 349 vm_paddr_t *); 350 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 351 vm_object_t, vm_pindex_t, vm_size_t); 352 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 353 static void mmu_booke_page_init(mmu_t, vm_page_t); 354 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 355 static void mmu_booke_pinit(mmu_t, pmap_t); 356 static void mmu_booke_pinit0(mmu_t, pmap_t); 357 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 358 vm_prot_t); 359 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 360 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 361 static void mmu_booke_release(mmu_t, pmap_t); 362 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 363 static void mmu_booke_remove_all(mmu_t, vm_page_t); 364 static void mmu_booke_remove_write(mmu_t, vm_page_t); 365 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 366 static void mmu_booke_zero_page(mmu_t, vm_page_t); 367 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 368 static void mmu_booke_activate(mmu_t, struct thread *); 369 static void mmu_booke_deactivate(mmu_t, struct thread *); 370 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 371 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 372 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 373 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 374 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 375 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 376 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 377 static void mmu_booke_kremove(mmu_t, vm_offset_t); 378 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 379 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 380 vm_size_t); 381 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 382 void **); 383 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 384 void *); 385 static void mmu_booke_scan_init(mmu_t); 386 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 387 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 388 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 389 vm_size_t sz, vm_memattr_t mode); 390 static int mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, 391 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 392 static int mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 393 int *is_user, vm_offset_t *decoded_addr); 394 395 396 static mmu_method_t mmu_booke_methods[] = { 397 /* pmap dispatcher interface */ 398 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 399 MMUMETHOD(mmu_copy, mmu_booke_copy), 400 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 401 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 402 MMUMETHOD(mmu_enter, mmu_booke_enter), 403 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 404 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 405 MMUMETHOD(mmu_extract, mmu_booke_extract), 406 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 407 MMUMETHOD(mmu_init, mmu_booke_init), 408 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 409 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 410 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 411 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 412 MMUMETHOD(mmu_map, mmu_booke_map), 413 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 414 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 415 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 416 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 417 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 418 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 419 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 420 MMUMETHOD(mmu_protect, mmu_booke_protect), 421 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 422 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 423 MMUMETHOD(mmu_release, mmu_booke_release), 424 MMUMETHOD(mmu_remove, mmu_booke_remove), 425 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 426 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 427 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 428 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 429 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 430 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 431 MMUMETHOD(mmu_activate, mmu_booke_activate), 432 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 433 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 434 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 435 436 /* Internal interfaces */ 437 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 438 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 439 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 440 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 441 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 442 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 443 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 444 MMUMETHOD(mmu_kremove, mmu_booke_kremove), 445 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 446 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 447 MMUMETHOD(mmu_map_user_ptr, mmu_booke_map_user_ptr), 448 MMUMETHOD(mmu_decode_kernel_ptr, mmu_booke_decode_kernel_ptr), 449 450 /* dumpsys() support */ 451 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 452 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 453 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 454 455 { 0, 0 } 456 }; 457 458 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 459 460 static __inline uint32_t 461 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 462 { 463 uint32_t attrib; 464 int i; 465 466 if (ma != VM_MEMATTR_DEFAULT) { 467 switch (ma) { 468 case VM_MEMATTR_UNCACHEABLE: 469 return (MAS2_I | MAS2_G); 470 case VM_MEMATTR_WRITE_COMBINING: 471 case VM_MEMATTR_WRITE_BACK: 472 case VM_MEMATTR_PREFETCHABLE: 473 return (MAS2_I); 474 case VM_MEMATTR_WRITE_THROUGH: 475 return (MAS2_W | MAS2_M); 476 case VM_MEMATTR_CACHEABLE: 477 return (MAS2_M); 478 } 479 } 480 481 /* 482 * Assume the page is cache inhibited and access is guarded unless 483 * it's in our available memory array. 484 */ 485 attrib = _TLB_ENTRY_IO; 486 for (i = 0; i < physmem_regions_sz; i++) { 487 if ((pa >= physmem_regions[i].mr_start) && 488 (pa < (physmem_regions[i].mr_start + 489 physmem_regions[i].mr_size))) { 490 attrib = _TLB_ENTRY_MEM; 491 break; 492 } 493 } 494 495 return (attrib); 496 } 497 498 static inline void 499 tlb_miss_lock(void) 500 { 501 #ifdef SMP 502 struct pcpu *pc; 503 504 if (!smp_started) 505 return; 506 507 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 508 if (pc != pcpup) { 509 510 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 511 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock); 512 513 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 514 ("tlb_miss_lock: tried to lock self")); 515 516 tlb_lock(pc->pc_booke.tlb_lock); 517 518 CTR1(KTR_PMAP, "%s: locked", __func__); 519 } 520 } 521 #endif 522 } 523 524 static inline void 525 tlb_miss_unlock(void) 526 { 527 #ifdef SMP 528 struct pcpu *pc; 529 530 if (!smp_started) 531 return; 532 533 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 534 if (pc != pcpup) { 535 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 536 __func__, pc->pc_cpuid); 537 538 tlb_unlock(pc->pc_booke.tlb_lock); 539 540 CTR1(KTR_PMAP, "%s: unlocked", __func__); 541 } 542 } 543 #endif 544 } 545 546 /* Return number of entries in TLB0. */ 547 static __inline void 548 tlb0_get_tlbconf(void) 549 { 550 uint32_t tlb0_cfg; 551 552 tlb0_cfg = mfspr(SPR_TLB0CFG); 553 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 554 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 555 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 556 } 557 558 /* Return number of entries in TLB1. */ 559 static __inline void 560 tlb1_get_tlbconf(void) 561 { 562 uint32_t tlb1_cfg; 563 564 tlb1_cfg = mfspr(SPR_TLB1CFG); 565 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 566 } 567 568 /**************************************************************************/ 569 /* Page table related */ 570 /**************************************************************************/ 571 572 #ifdef __powerpc64__ 573 /* Initialize pool of kva ptbl buffers. */ 574 static void 575 ptbl_init(void) 576 { 577 int i; 578 579 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 580 TAILQ_INIT(&ptbl_buf_freelist); 581 582 for (i = 0; i < PTBL_BUFS; i++) { 583 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + 584 i * MAX(PTBL_PAGES,PDIR_PAGES) * PAGE_SIZE; 585 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 586 } 587 } 588 589 /* Get an sf_buf from the freelist. */ 590 static struct ptbl_buf * 591 ptbl_buf_alloc(void) 592 { 593 struct ptbl_buf *buf; 594 595 mtx_lock(&ptbl_buf_freelist_lock); 596 buf = TAILQ_FIRST(&ptbl_buf_freelist); 597 if (buf != NULL) 598 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 599 mtx_unlock(&ptbl_buf_freelist_lock); 600 601 return (buf); 602 } 603 604 /* Return ptbl buff to free pool. */ 605 static void 606 ptbl_buf_free(struct ptbl_buf *buf) 607 { 608 mtx_lock(&ptbl_buf_freelist_lock); 609 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 610 mtx_unlock(&ptbl_buf_freelist_lock); 611 } 612 613 /* 614 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 615 */ 616 static void 617 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t * ptbl) 618 { 619 struct ptbl_buf *pbuf; 620 621 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) { 622 if (pbuf->kva == (vm_offset_t) ptbl) { 623 /* Remove from pmap ptbl buf list. */ 624 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 625 626 /* Free corresponding ptbl buf. */ 627 ptbl_buf_free(pbuf); 628 629 break; 630 } 631 } 632 } 633 634 /* Get a pointer to a PTE in a page table. */ 635 static __inline pte_t * 636 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 637 { 638 pte_t **pdir; 639 pte_t *ptbl; 640 641 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 642 643 pdir = pmap->pm_pp2d[PP2D_IDX(va)]; 644 if (!pdir) 645 return NULL; 646 ptbl = pdir[PDIR_IDX(va)]; 647 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL); 648 } 649 650 /* 651 * Search the list of allocated pdir bufs and find on list of allocated pdirs 652 */ 653 static void 654 ptbl_free_pmap_pdir(mmu_t mmu, pmap_t pmap, pte_t ** pdir) 655 { 656 struct ptbl_buf *pbuf; 657 658 TAILQ_FOREACH(pbuf, &pmap->pm_pdir_list, link) { 659 if (pbuf->kva == (vm_offset_t) pdir) { 660 /* Remove from pmap ptbl buf list. */ 661 TAILQ_REMOVE(&pmap->pm_pdir_list, pbuf, link); 662 663 /* Free corresponding pdir buf. */ 664 ptbl_buf_free(pbuf); 665 666 break; 667 } 668 } 669 } 670 /* Free pdir pages and invalidate pdir entry. */ 671 static void 672 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx) 673 { 674 pte_t **pdir; 675 vm_paddr_t pa; 676 vm_offset_t va; 677 vm_page_t m; 678 int i; 679 680 pdir = pmap->pm_pp2d[pp2d_idx]; 681 682 KASSERT((pdir != NULL), ("pdir_free: null pdir")); 683 684 pmap->pm_pp2d[pp2d_idx] = NULL; 685 686 for (i = 0; i < PDIR_PAGES; i++) { 687 va = ((vm_offset_t) pdir + (i * PAGE_SIZE)); 688 pa = pte_vatopa(mmu, kernel_pmap, va); 689 m = PHYS_TO_VM_PAGE(pa); 690 vm_page_free_zero(m); 691 vm_wire_sub(1); 692 pmap_kremove(va); 693 } 694 695 ptbl_free_pmap_pdir(mmu, pmap, pdir); 696 } 697 698 /* 699 * Decrement pdir pages hold count and attempt to free pdir pages. Called 700 * when removing directory entry from pdir. 701 * 702 * Return 1 if pdir pages were freed. 703 */ 704 static int 705 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx) 706 { 707 pte_t **pdir; 708 vm_paddr_t pa; 709 vm_page_t m; 710 int i; 711 712 KASSERT((pmap != kernel_pmap), 713 ("pdir_unhold: unholding kernel pdir!")); 714 715 pdir = pmap->pm_pp2d[pp2d_idx]; 716 717 KASSERT(((vm_offset_t) pdir >= VM_MIN_KERNEL_ADDRESS), 718 ("pdir_unhold: non kva pdir")); 719 720 /* decrement hold count */ 721 for (i = 0; i < PDIR_PAGES; i++) { 722 pa = pte_vatopa(mmu, kernel_pmap, 723 (vm_offset_t) pdir + (i * PAGE_SIZE)); 724 m = PHYS_TO_VM_PAGE(pa); 725 m->wire_count--; 726 } 727 728 /* 729 * Free pdir pages if there are no dir entries in this pdir. 730 * wire_count has the same value for all ptbl pages, so check the 731 * last page. 732 */ 733 if (m->wire_count == 0) { 734 pdir_free(mmu, pmap, pp2d_idx); 735 return (1); 736 } 737 return (0); 738 } 739 740 /* 741 * Increment hold count for pdir pages. This routine is used when new ptlb 742 * entry is being inserted into pdir. 743 */ 744 static void 745 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir) 746 { 747 vm_paddr_t pa; 748 vm_page_t m; 749 int i; 750 751 KASSERT((pmap != kernel_pmap), 752 ("pdir_hold: holding kernel pdir!")); 753 754 KASSERT((pdir != NULL), ("pdir_hold: null pdir")); 755 756 for (i = 0; i < PDIR_PAGES; i++) { 757 pa = pte_vatopa(mmu, kernel_pmap, 758 (vm_offset_t) pdir + (i * PAGE_SIZE)); 759 m = PHYS_TO_VM_PAGE(pa); 760 m->wire_count++; 761 } 762 } 763 764 /* Allocate page table. */ 765 static pte_t * 766 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx, 767 boolean_t nosleep) 768 { 769 vm_page_t mtbl [PTBL_PAGES]; 770 vm_page_t m; 771 struct ptbl_buf *pbuf; 772 unsigned int pidx; 773 pte_t *ptbl; 774 int i, j; 775 int req; 776 777 KASSERT((pdir[pdir_idx] == NULL), 778 ("%s: valid ptbl entry exists!", __func__)); 779 780 pbuf = ptbl_buf_alloc(); 781 if (pbuf == NULL) 782 panic("%s: couldn't alloc kernel virtual memory", __func__); 783 784 ptbl = (pte_t *) pbuf->kva; 785 786 for (i = 0; i < PTBL_PAGES; i++) { 787 pidx = (PTBL_PAGES * pdir_idx) + i; 788 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED; 789 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) { 790 PMAP_UNLOCK(pmap); 791 rw_wunlock(&pvh_global_lock); 792 if (nosleep) { 793 ptbl_free_pmap_ptbl(pmap, ptbl); 794 for (j = 0; j < i; j++) 795 vm_page_free(mtbl[j]); 796 vm_wire_sub(i); 797 return (NULL); 798 } 799 vm_wait(NULL); 800 rw_wlock(&pvh_global_lock); 801 PMAP_LOCK(pmap); 802 } 803 mtbl[i] = m; 804 } 805 806 /* Mapin allocated pages into kernel_pmap. */ 807 mmu_booke_qenter(mmu, (vm_offset_t) ptbl, mtbl, PTBL_PAGES); 808 /* Zero whole ptbl. */ 809 bzero((caddr_t) ptbl, PTBL_PAGES * PAGE_SIZE); 810 811 /* Add pbuf to the pmap ptbl bufs list. */ 812 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 813 814 return (ptbl); 815 } 816 817 /* Free ptbl pages and invalidate pdir entry. */ 818 static void 819 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx) 820 { 821 pte_t *ptbl; 822 vm_paddr_t pa; 823 vm_offset_t va; 824 vm_page_t m; 825 int i; 826 827 ptbl = pdir[pdir_idx]; 828 829 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 830 831 pdir[pdir_idx] = NULL; 832 833 for (i = 0; i < PTBL_PAGES; i++) { 834 va = ((vm_offset_t) ptbl + (i * PAGE_SIZE)); 835 pa = pte_vatopa(mmu, kernel_pmap, va); 836 m = PHYS_TO_VM_PAGE(pa); 837 vm_page_free_zero(m); 838 vm_wire_sub(1); 839 pmap_kremove(va); 840 } 841 842 ptbl_free_pmap_ptbl(pmap, ptbl); 843 } 844 845 /* 846 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called 847 * when removing pte entry from ptbl. 848 * 849 * Return 1 if ptbl pages were freed. 850 */ 851 static int 852 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va) 853 { 854 pte_t *ptbl; 855 vm_paddr_t pa; 856 vm_page_t m; 857 u_int pp2d_idx; 858 pte_t **pdir; 859 u_int pdir_idx; 860 int i; 861 862 pp2d_idx = PP2D_IDX(va); 863 pdir_idx = PDIR_IDX(va); 864 865 KASSERT((pmap != kernel_pmap), 866 ("ptbl_unhold: unholding kernel ptbl!")); 867 868 pdir = pmap->pm_pp2d[pp2d_idx]; 869 ptbl = pdir[pdir_idx]; 870 871 KASSERT(((vm_offset_t) ptbl >= VM_MIN_KERNEL_ADDRESS), 872 ("ptbl_unhold: non kva ptbl")); 873 874 /* decrement hold count */ 875 for (i = 0; i < PTBL_PAGES; i++) { 876 pa = pte_vatopa(mmu, kernel_pmap, 877 (vm_offset_t) ptbl + (i * PAGE_SIZE)); 878 m = PHYS_TO_VM_PAGE(pa); 879 m->wire_count--; 880 } 881 882 /* 883 * Free ptbl pages if there are no pte entries in this ptbl. 884 * wire_count has the same value for all ptbl pages, so check the 885 * last page. 886 */ 887 if (m->wire_count == 0) { 888 /* A pair of indirect entries might point to this ptbl page */ 889 #if 0 890 tlb_flush_entry(pmap, va & ~((2UL * PAGE_SIZE_1M) - 1), 891 TLB_SIZE_1M, MAS6_SIND); 892 tlb_flush_entry(pmap, (va & ~((2UL * PAGE_SIZE_1M) - 1)) | PAGE_SIZE_1M, 893 TLB_SIZE_1M, MAS6_SIND); 894 #endif 895 ptbl_free(mmu, pmap, pdir, pdir_idx); 896 pdir_unhold(mmu, pmap, pp2d_idx); 897 return (1); 898 } 899 return (0); 900 } 901 902 /* 903 * Increment hold count for ptbl pages. This routine is used when new pte 904 * entry is being inserted into ptbl. 905 */ 906 static void 907 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx) 908 { 909 vm_paddr_t pa; 910 pte_t *ptbl; 911 vm_page_t m; 912 int i; 913 914 KASSERT((pmap != kernel_pmap), 915 ("ptbl_hold: holding kernel ptbl!")); 916 917 ptbl = pdir[pdir_idx]; 918 919 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 920 921 for (i = 0; i < PTBL_PAGES; i++) { 922 pa = pte_vatopa(mmu, kernel_pmap, 923 (vm_offset_t) ptbl + (i * PAGE_SIZE)); 924 m = PHYS_TO_VM_PAGE(pa); 925 m->wire_count++; 926 } 927 } 928 #else 929 930 /* Initialize pool of kva ptbl buffers. */ 931 static void 932 ptbl_init(void) 933 { 934 int i; 935 936 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 937 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 938 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 939 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 940 941 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 942 TAILQ_INIT(&ptbl_buf_freelist); 943 944 for (i = 0; i < PTBL_BUFS; i++) { 945 ptbl_bufs[i].kva = 946 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 947 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 948 } 949 } 950 951 /* Get a ptbl_buf from the freelist. */ 952 static struct ptbl_buf * 953 ptbl_buf_alloc(void) 954 { 955 struct ptbl_buf *buf; 956 957 mtx_lock(&ptbl_buf_freelist_lock); 958 buf = TAILQ_FIRST(&ptbl_buf_freelist); 959 if (buf != NULL) 960 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 961 mtx_unlock(&ptbl_buf_freelist_lock); 962 963 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 964 965 return (buf); 966 } 967 968 /* Return ptbl buff to free pool. */ 969 static void 970 ptbl_buf_free(struct ptbl_buf *buf) 971 { 972 973 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 974 975 mtx_lock(&ptbl_buf_freelist_lock); 976 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 977 mtx_unlock(&ptbl_buf_freelist_lock); 978 } 979 980 /* 981 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 982 */ 983 static void 984 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 985 { 986 struct ptbl_buf *pbuf; 987 988 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 989 990 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 991 992 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 993 if (pbuf->kva == (vm_offset_t)ptbl) { 994 /* Remove from pmap ptbl buf list. */ 995 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 996 997 /* Free corresponding ptbl buf. */ 998 ptbl_buf_free(pbuf); 999 break; 1000 } 1001 } 1002 1003 /* Allocate page table. */ 1004 static pte_t * 1005 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 1006 { 1007 vm_page_t mtbl[PTBL_PAGES]; 1008 vm_page_t m; 1009 struct ptbl_buf *pbuf; 1010 unsigned int pidx; 1011 pte_t *ptbl; 1012 int i, j; 1013 1014 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1015 (pmap == kernel_pmap), pdir_idx); 1016 1017 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1018 ("ptbl_alloc: invalid pdir_idx")); 1019 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 1020 ("pte_alloc: valid ptbl entry exists!")); 1021 1022 pbuf = ptbl_buf_alloc(); 1023 if (pbuf == NULL) 1024 panic("pte_alloc: couldn't alloc kernel virtual memory"); 1025 1026 ptbl = (pte_t *)pbuf->kva; 1027 1028 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 1029 1030 for (i = 0; i < PTBL_PAGES; i++) { 1031 pidx = (PTBL_PAGES * pdir_idx) + i; 1032 while ((m = vm_page_alloc(NULL, pidx, 1033 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 1034 PMAP_UNLOCK(pmap); 1035 rw_wunlock(&pvh_global_lock); 1036 if (nosleep) { 1037 ptbl_free_pmap_ptbl(pmap, ptbl); 1038 for (j = 0; j < i; j++) 1039 vm_page_free(mtbl[j]); 1040 vm_wire_sub(i); 1041 return (NULL); 1042 } 1043 vm_wait(NULL); 1044 rw_wlock(&pvh_global_lock); 1045 PMAP_LOCK(pmap); 1046 } 1047 mtbl[i] = m; 1048 } 1049 1050 /* Map allocated pages into kernel_pmap. */ 1051 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 1052 1053 /* Zero whole ptbl. */ 1054 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 1055 1056 /* Add pbuf to the pmap ptbl bufs list. */ 1057 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 1058 1059 return (ptbl); 1060 } 1061 1062 /* Free ptbl pages and invalidate pdir entry. */ 1063 static void 1064 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1065 { 1066 pte_t *ptbl; 1067 vm_paddr_t pa; 1068 vm_offset_t va; 1069 vm_page_t m; 1070 int i; 1071 1072 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1073 (pmap == kernel_pmap), pdir_idx); 1074 1075 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1076 ("ptbl_free: invalid pdir_idx")); 1077 1078 ptbl = pmap->pm_pdir[pdir_idx]; 1079 1080 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 1081 1082 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 1083 1084 /* 1085 * Invalidate the pdir entry as soon as possible, so that other CPUs 1086 * don't attempt to look up the page tables we are releasing. 1087 */ 1088 mtx_lock_spin(&tlbivax_mutex); 1089 tlb_miss_lock(); 1090 1091 pmap->pm_pdir[pdir_idx] = NULL; 1092 1093 tlb_miss_unlock(); 1094 mtx_unlock_spin(&tlbivax_mutex); 1095 1096 for (i = 0; i < PTBL_PAGES; i++) { 1097 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 1098 pa = pte_vatopa(mmu, kernel_pmap, va); 1099 m = PHYS_TO_VM_PAGE(pa); 1100 vm_page_free_zero(m); 1101 vm_wire_sub(1); 1102 mmu_booke_kremove(mmu, va); 1103 } 1104 1105 ptbl_free_pmap_ptbl(pmap, ptbl); 1106 } 1107 1108 /* 1109 * Decrement ptbl pages hold count and attempt to free ptbl pages. 1110 * Called when removing pte entry from ptbl. 1111 * 1112 * Return 1 if ptbl pages were freed. 1113 */ 1114 static int 1115 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1116 { 1117 pte_t *ptbl; 1118 vm_paddr_t pa; 1119 vm_page_t m; 1120 int i; 1121 1122 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1123 (pmap == kernel_pmap), pdir_idx); 1124 1125 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1126 ("ptbl_unhold: invalid pdir_idx")); 1127 KASSERT((pmap != kernel_pmap), 1128 ("ptbl_unhold: unholding kernel ptbl!")); 1129 1130 ptbl = pmap->pm_pdir[pdir_idx]; 1131 1132 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 1133 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 1134 ("ptbl_unhold: non kva ptbl")); 1135 1136 /* decrement hold count */ 1137 for (i = 0; i < PTBL_PAGES; i++) { 1138 pa = pte_vatopa(mmu, kernel_pmap, 1139 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 1140 m = PHYS_TO_VM_PAGE(pa); 1141 m->wire_count--; 1142 } 1143 1144 /* 1145 * Free ptbl pages if there are no pte etries in this ptbl. 1146 * wire_count has the same value for all ptbl pages, so check the last 1147 * page. 1148 */ 1149 if (m->wire_count == 0) { 1150 ptbl_free(mmu, pmap, pdir_idx); 1151 1152 //debugf("ptbl_unhold: e (freed ptbl)\n"); 1153 return (1); 1154 } 1155 1156 return (0); 1157 } 1158 1159 /* 1160 * Increment hold count for ptbl pages. This routine is used when a new pte 1161 * entry is being inserted into the ptbl. 1162 */ 1163 static void 1164 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1165 { 1166 vm_paddr_t pa; 1167 pte_t *ptbl; 1168 vm_page_t m; 1169 int i; 1170 1171 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 1172 pdir_idx); 1173 1174 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1175 ("ptbl_hold: invalid pdir_idx")); 1176 KASSERT((pmap != kernel_pmap), 1177 ("ptbl_hold: holding kernel ptbl!")); 1178 1179 ptbl = pmap->pm_pdir[pdir_idx]; 1180 1181 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 1182 1183 for (i = 0; i < PTBL_PAGES; i++) { 1184 pa = pte_vatopa(mmu, kernel_pmap, 1185 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 1186 m = PHYS_TO_VM_PAGE(pa); 1187 m->wire_count++; 1188 } 1189 } 1190 #endif 1191 1192 /* Allocate pv_entry structure. */ 1193 pv_entry_t 1194 pv_alloc(void) 1195 { 1196 pv_entry_t pv; 1197 1198 pv_entry_count++; 1199 if (pv_entry_count > pv_entry_high_water) 1200 pagedaemon_wakeup(0); /* XXX powerpc NUMA */ 1201 pv = uma_zalloc(pvzone, M_NOWAIT); 1202 1203 return (pv); 1204 } 1205 1206 /* Free pv_entry structure. */ 1207 static __inline void 1208 pv_free(pv_entry_t pve) 1209 { 1210 1211 pv_entry_count--; 1212 uma_zfree(pvzone, pve); 1213 } 1214 1215 1216 /* Allocate and initialize pv_entry structure. */ 1217 static void 1218 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 1219 { 1220 pv_entry_t pve; 1221 1222 //int su = (pmap == kernel_pmap); 1223 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 1224 // (u_int32_t)pmap, va, (u_int32_t)m); 1225 1226 pve = pv_alloc(); 1227 if (pve == NULL) 1228 panic("pv_insert: no pv entries!"); 1229 1230 pve->pv_pmap = pmap; 1231 pve->pv_va = va; 1232 1233 /* add to pv_list */ 1234 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1235 rw_assert(&pvh_global_lock, RA_WLOCKED); 1236 1237 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 1238 1239 //debugf("pv_insert: e\n"); 1240 } 1241 1242 /* Destroy pv entry. */ 1243 static void 1244 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 1245 { 1246 pv_entry_t pve; 1247 1248 //int su = (pmap == kernel_pmap); 1249 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 1250 1251 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1252 rw_assert(&pvh_global_lock, RA_WLOCKED); 1253 1254 /* find pv entry */ 1255 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 1256 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 1257 /* remove from pv_list */ 1258 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 1259 if (TAILQ_EMPTY(&m->md.pv_list)) 1260 vm_page_aflag_clear(m, PGA_WRITEABLE); 1261 1262 /* free pv entry struct */ 1263 pv_free(pve); 1264 break; 1265 } 1266 } 1267 1268 //debugf("pv_remove: e\n"); 1269 } 1270 1271 #ifdef __powerpc64__ 1272 /* 1273 * Clean pte entry, try to free page table page if requested. 1274 * 1275 * Return 1 if ptbl pages were freed, otherwise return 0. 1276 */ 1277 static int 1278 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags) 1279 { 1280 vm_page_t m; 1281 pte_t *pte; 1282 1283 pte = pte_find(mmu, pmap, va); 1284 KASSERT(pte != NULL, ("%s: NULL pte", __func__)); 1285 1286 if (!PTE_ISVALID(pte)) 1287 return (0); 1288 1289 /* Get vm_page_t for mapped pte. */ 1290 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1291 1292 if (PTE_ISWIRED(pte)) 1293 pmap->pm_stats.wired_count--; 1294 1295 /* Handle managed entry. */ 1296 if (PTE_ISMANAGED(pte)) { 1297 1298 /* Handle modified pages. */ 1299 if (PTE_ISMODIFIED(pte)) 1300 vm_page_dirty(m); 1301 1302 /* Referenced pages. */ 1303 if (PTE_ISREFERENCED(pte)) 1304 vm_page_aflag_set(m, PGA_REFERENCED); 1305 1306 /* Remove pv_entry from pv_list. */ 1307 pv_remove(pmap, va, m); 1308 } else if (m->md.pv_tracked) { 1309 pv_remove(pmap, va, m); 1310 if (TAILQ_EMPTY(&m->md.pv_list)) 1311 m->md.pv_tracked = false; 1312 } 1313 mtx_lock_spin(&tlbivax_mutex); 1314 tlb_miss_lock(); 1315 1316 tlb0_flush_entry(va); 1317 *pte = 0; 1318 1319 tlb_miss_unlock(); 1320 mtx_unlock_spin(&tlbivax_mutex); 1321 1322 pmap->pm_stats.resident_count--; 1323 1324 if (flags & PTBL_UNHOLD) { 1325 return (ptbl_unhold(mmu, pmap, va)); 1326 } 1327 return (0); 1328 } 1329 1330 /* 1331 * allocate a page of pointers to page directories, do not preallocate the 1332 * page tables 1333 */ 1334 static pte_t ** 1335 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep) 1336 { 1337 vm_page_t mtbl [PDIR_PAGES]; 1338 vm_page_t m; 1339 struct ptbl_buf *pbuf; 1340 pte_t **pdir; 1341 unsigned int pidx; 1342 int i; 1343 int req; 1344 1345 pbuf = ptbl_buf_alloc(); 1346 1347 if (pbuf == NULL) 1348 panic("%s: couldn't alloc kernel virtual memory", __func__); 1349 1350 /* Allocate pdir pages, this will sleep! */ 1351 for (i = 0; i < PDIR_PAGES; i++) { 1352 pidx = (PDIR_PAGES * pp2d_idx) + i; 1353 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED; 1354 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) { 1355 PMAP_UNLOCK(pmap); 1356 vm_wait(NULL); 1357 PMAP_LOCK(pmap); 1358 } 1359 mtbl[i] = m; 1360 } 1361 1362 /* Mapin allocated pages into kernel_pmap. */ 1363 pdir = (pte_t **) pbuf->kva; 1364 pmap_qenter((vm_offset_t) pdir, mtbl, PDIR_PAGES); 1365 1366 /* Zero whole pdir. */ 1367 bzero((caddr_t) pdir, PDIR_PAGES * PAGE_SIZE); 1368 1369 /* Add pdir to the pmap pdir bufs list. */ 1370 TAILQ_INSERT_TAIL(&pmap->pm_pdir_list, pbuf, link); 1371 1372 return pdir; 1373 } 1374 1375 /* 1376 * Insert PTE for a given page and virtual address. 1377 */ 1378 static int 1379 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 1380 boolean_t nosleep) 1381 { 1382 unsigned int pp2d_idx = PP2D_IDX(va); 1383 unsigned int pdir_idx = PDIR_IDX(va); 1384 unsigned int ptbl_idx = PTBL_IDX(va); 1385 pte_t *ptbl, *pte, pte_tmp; 1386 pte_t **pdir; 1387 1388 /* Get the page directory pointer. */ 1389 pdir = pmap->pm_pp2d[pp2d_idx]; 1390 if (pdir == NULL) 1391 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep); 1392 1393 /* Get the page table pointer. */ 1394 ptbl = pdir[pdir_idx]; 1395 1396 if (ptbl == NULL) { 1397 /* Allocate page table pages. */ 1398 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep); 1399 if (ptbl == NULL) { 1400 KASSERT(nosleep, ("nosleep and NULL ptbl")); 1401 return (ENOMEM); 1402 } 1403 pte = &ptbl[ptbl_idx]; 1404 } else { 1405 /* 1406 * Check if there is valid mapping for requested va, if there 1407 * is, remove it. 1408 */ 1409 pte = &ptbl[ptbl_idx]; 1410 if (PTE_ISVALID(pte)) { 1411 pte_remove(mmu, pmap, va, PTBL_HOLD); 1412 } else { 1413 /* 1414 * pte is not used, increment hold count for ptbl 1415 * pages. 1416 */ 1417 if (pmap != kernel_pmap) 1418 ptbl_hold(mmu, pmap, pdir, pdir_idx); 1419 } 1420 } 1421 1422 if (pdir[pdir_idx] == NULL) { 1423 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL) 1424 pdir_hold(mmu, pmap, pdir); 1425 pdir[pdir_idx] = ptbl; 1426 } 1427 if (pmap->pm_pp2d[pp2d_idx] == NULL) 1428 pmap->pm_pp2d[pp2d_idx] = pdir; 1429 1430 /* 1431 * Insert pv_entry into pv_list for mapped page if part of managed 1432 * memory. 1433 */ 1434 if ((m->oflags & VPO_UNMANAGED) == 0) { 1435 flags |= PTE_MANAGED; 1436 1437 /* Create and insert pv entry. */ 1438 pv_insert(pmap, va, m); 1439 } 1440 1441 pmap->pm_stats.resident_count++; 1442 1443 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 1444 pte_tmp |= (PTE_VALID | flags); 1445 1446 mtx_lock_spin(&tlbivax_mutex); 1447 tlb_miss_lock(); 1448 1449 tlb0_flush_entry(va); 1450 *pte = pte_tmp; 1451 1452 tlb_miss_unlock(); 1453 mtx_unlock_spin(&tlbivax_mutex); 1454 1455 return (0); 1456 } 1457 1458 /* Return the pa for the given pmap/va. */ 1459 static vm_paddr_t 1460 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1461 { 1462 vm_paddr_t pa = 0; 1463 pte_t *pte; 1464 1465 pte = pte_find(mmu, pmap, va); 1466 if ((pte != NULL) && PTE_ISVALID(pte)) 1467 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1468 return (pa); 1469 } 1470 1471 1472 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */ 1473 static void 1474 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1475 { 1476 int i, j; 1477 vm_offset_t va; 1478 pte_t *pte; 1479 1480 va = addr; 1481 /* Initialize kernel pdir */ 1482 for (i = 0; i < kernel_pdirs; i++) { 1483 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] = 1484 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES)); 1485 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES)); 1486 j < PDIR_NENTRIES; j++) { 1487 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] = 1488 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE * PDIR_PAGES) + 1489 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE * PTBL_PAGES)); 1490 } 1491 } 1492 1493 /* 1494 * Fill in PTEs covering kernel code and data. They are not required 1495 * for address translation, as this area is covered by static TLB1 1496 * entries, but for pte_vatopa() to work correctly with kernel area 1497 * addresses. 1498 */ 1499 for (va = addr; va < data_end; va += PAGE_SIZE) { 1500 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]); 1501 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1502 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1503 PTE_VALID | PTE_PS_4KB; 1504 } 1505 } 1506 #else 1507 /* 1508 * Clean pte entry, try to free page table page if requested. 1509 * 1510 * Return 1 if ptbl pages were freed, otherwise return 0. 1511 */ 1512 static int 1513 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 1514 { 1515 unsigned int pdir_idx = PDIR_IDX(va); 1516 unsigned int ptbl_idx = PTBL_IDX(va); 1517 vm_page_t m; 1518 pte_t *ptbl; 1519 pte_t *pte; 1520 1521 //int su = (pmap == kernel_pmap); 1522 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 1523 // su, (u_int32_t)pmap, va, flags); 1524 1525 ptbl = pmap->pm_pdir[pdir_idx]; 1526 KASSERT(ptbl, ("pte_remove: null ptbl")); 1527 1528 pte = &ptbl[ptbl_idx]; 1529 1530 if (pte == NULL || !PTE_ISVALID(pte)) 1531 return (0); 1532 1533 if (PTE_ISWIRED(pte)) 1534 pmap->pm_stats.wired_count--; 1535 1536 /* Get vm_page_t for mapped pte. */ 1537 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1538 1539 /* Handle managed entry. */ 1540 if (PTE_ISMANAGED(pte)) { 1541 1542 if (PTE_ISMODIFIED(pte)) 1543 vm_page_dirty(m); 1544 1545 if (PTE_ISREFERENCED(pte)) 1546 vm_page_aflag_set(m, PGA_REFERENCED); 1547 1548 pv_remove(pmap, va, m); 1549 } else if (m->md.pv_tracked) { 1550 /* 1551 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is 1552 * used. This is needed by the NCSW support code for fast 1553 * VA<->PA translation. 1554 */ 1555 pv_remove(pmap, va, m); 1556 if (TAILQ_EMPTY(&m->md.pv_list)) 1557 m->md.pv_tracked = false; 1558 } 1559 1560 mtx_lock_spin(&tlbivax_mutex); 1561 tlb_miss_lock(); 1562 1563 tlb0_flush_entry(va); 1564 *pte = 0; 1565 1566 tlb_miss_unlock(); 1567 mtx_unlock_spin(&tlbivax_mutex); 1568 1569 pmap->pm_stats.resident_count--; 1570 1571 if (flags & PTBL_UNHOLD) { 1572 //debugf("pte_remove: e (unhold)\n"); 1573 return (ptbl_unhold(mmu, pmap, pdir_idx)); 1574 } 1575 1576 //debugf("pte_remove: e\n"); 1577 return (0); 1578 } 1579 1580 /* 1581 * Insert PTE for a given page and virtual address. 1582 */ 1583 static int 1584 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 1585 boolean_t nosleep) 1586 { 1587 unsigned int pdir_idx = PDIR_IDX(va); 1588 unsigned int ptbl_idx = PTBL_IDX(va); 1589 pte_t *ptbl, *pte, pte_tmp; 1590 1591 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 1592 pmap == kernel_pmap, pmap, va); 1593 1594 /* Get the page table pointer. */ 1595 ptbl = pmap->pm_pdir[pdir_idx]; 1596 1597 if (ptbl == NULL) { 1598 /* Allocate page table pages. */ 1599 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 1600 if (ptbl == NULL) { 1601 KASSERT(nosleep, ("nosleep and NULL ptbl")); 1602 return (ENOMEM); 1603 } 1604 pmap->pm_pdir[pdir_idx] = ptbl; 1605 pte = &ptbl[ptbl_idx]; 1606 } else { 1607 /* 1608 * Check if there is valid mapping for requested 1609 * va, if there is, remove it. 1610 */ 1611 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 1612 if (PTE_ISVALID(pte)) { 1613 pte_remove(mmu, pmap, va, PTBL_HOLD); 1614 } else { 1615 /* 1616 * pte is not used, increment hold count 1617 * for ptbl pages. 1618 */ 1619 if (pmap != kernel_pmap) 1620 ptbl_hold(mmu, pmap, pdir_idx); 1621 } 1622 } 1623 1624 /* 1625 * Insert pv_entry into pv_list for mapped page if part of managed 1626 * memory. 1627 */ 1628 if ((m->oflags & VPO_UNMANAGED) == 0) { 1629 flags |= PTE_MANAGED; 1630 1631 /* Create and insert pv entry. */ 1632 pv_insert(pmap, va, m); 1633 } 1634 1635 pmap->pm_stats.resident_count++; 1636 1637 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 1638 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 1639 1640 mtx_lock_spin(&tlbivax_mutex); 1641 tlb_miss_lock(); 1642 1643 tlb0_flush_entry(va); 1644 *pte = pte_tmp; 1645 1646 tlb_miss_unlock(); 1647 mtx_unlock_spin(&tlbivax_mutex); 1648 return (0); 1649 } 1650 1651 /* Return the pa for the given pmap/va. */ 1652 static vm_paddr_t 1653 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1654 { 1655 vm_paddr_t pa = 0; 1656 pte_t *pte; 1657 1658 pte = pte_find(mmu, pmap, va); 1659 if ((pte != NULL) && PTE_ISVALID(pte)) 1660 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1661 return (pa); 1662 } 1663 1664 /* Get a pointer to a PTE in a page table. */ 1665 static pte_t * 1666 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1667 { 1668 unsigned int pdir_idx = PDIR_IDX(va); 1669 unsigned int ptbl_idx = PTBL_IDX(va); 1670 1671 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1672 1673 if (pmap->pm_pdir[pdir_idx]) 1674 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1675 1676 return (NULL); 1677 } 1678 1679 /* Set up kernel page tables. */ 1680 static void 1681 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1682 { 1683 int i; 1684 vm_offset_t va; 1685 pte_t *pte; 1686 1687 /* Initialize kernel pdir */ 1688 for (i = 0; i < kernel_ptbls; i++) 1689 kernel_pmap->pm_pdir[kptbl_min + i] = 1690 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1691 1692 /* 1693 * Fill in PTEs covering kernel code and data. They are not required 1694 * for address translation, as this area is covered by static TLB1 1695 * entries, but for pte_vatopa() to work correctly with kernel area 1696 * addresses. 1697 */ 1698 for (va = addr; va < data_end; va += PAGE_SIZE) { 1699 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1700 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1701 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1702 PTE_VALID | PTE_PS_4KB; 1703 } 1704 } 1705 #endif 1706 1707 /**************************************************************************/ 1708 /* PMAP related */ 1709 /**************************************************************************/ 1710 1711 /* 1712 * This is called during booke_init, before the system is really initialized. 1713 */ 1714 static void 1715 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1716 { 1717 vm_paddr_t phys_kernelend; 1718 struct mem_region *mp, *mp1; 1719 int cnt, i, j; 1720 vm_paddr_t s, e, sz; 1721 vm_paddr_t physsz, hwphyssz; 1722 u_int phys_avail_count; 1723 vm_size_t kstack0_sz; 1724 vm_offset_t kernel_pdir, kstack0; 1725 vm_paddr_t kstack0_phys; 1726 void *dpcpu; 1727 1728 debugf("mmu_booke_bootstrap: entered\n"); 1729 1730 /* Set interesting system properties */ 1731 #ifdef __powerpc64__ 1732 hw_direct_map = 1; 1733 #else 1734 hw_direct_map = 0; 1735 #endif 1736 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 1737 elf32_nxstack = 1; 1738 #endif 1739 1740 /* Initialize invalidation mutex */ 1741 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1742 1743 /* Read TLB0 size and associativity. */ 1744 tlb0_get_tlbconf(); 1745 1746 /* 1747 * Align kernel start and end address (kernel image). 1748 * Note that kernel end does not necessarily relate to kernsize. 1749 * kernsize is the size of the kernel that is actually mapped. 1750 */ 1751 kernstart = trunc_page(start); 1752 data_start = round_page(kernelend); 1753 data_end = data_start; 1754 1755 /* Allocate the dynamic per-cpu area. */ 1756 dpcpu = (void *)data_end; 1757 data_end += DPCPU_SIZE; 1758 1759 /* Allocate space for the message buffer. */ 1760 msgbufp = (struct msgbuf *)data_end; 1761 data_end += msgbufsize; 1762 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1763 (uintptr_t)msgbufp, data_end); 1764 1765 data_end = round_page(data_end); 1766 1767 /* Allocate space for ptbl_bufs. */ 1768 ptbl_bufs = (struct ptbl_buf *)data_end; 1769 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1770 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1771 (uintptr_t)ptbl_bufs, data_end); 1772 1773 data_end = round_page(data_end); 1774 1775 /* Allocate PTE tables for kernel KVA. */ 1776 kernel_pdir = data_end; 1777 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS, 1778 PDIR_SIZE); 1779 #ifdef __powerpc64__ 1780 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES); 1781 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE; 1782 #endif 1783 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1784 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1785 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1786 kernel_pdir, data_end); 1787 1788 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end); 1789 if (data_end - kernstart > kernsize) { 1790 kernsize += tlb1_mapin_region(kernstart + kernsize, 1791 kernload + kernsize, (data_end - kernstart) - kernsize); 1792 } 1793 data_end = kernstart + kernsize; 1794 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end); 1795 1796 /* 1797 * Clear the structures - note we can only do it safely after the 1798 * possible additional TLB1 translations are in place (above) so that 1799 * all range up to the currently calculated 'data_end' is covered. 1800 */ 1801 dpcpu_init(dpcpu, 0); 1802 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1803 #ifdef __powerpc64__ 1804 memset((void *)kernel_pdir, 0, 1805 kernel_pdirs * PDIR_PAGES * PAGE_SIZE + 1806 kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1807 #else 1808 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1809 #endif 1810 1811 /*******************************************************/ 1812 /* Set the start and end of kva. */ 1813 /*******************************************************/ 1814 virtual_avail = round_page(data_end); 1815 virtual_end = VM_MAX_KERNEL_ADDRESS; 1816 1817 /* Allocate KVA space for page zero/copy operations. */ 1818 zero_page_va = virtual_avail; 1819 virtual_avail += PAGE_SIZE; 1820 copy_page_src_va = virtual_avail; 1821 virtual_avail += PAGE_SIZE; 1822 copy_page_dst_va = virtual_avail; 1823 virtual_avail += PAGE_SIZE; 1824 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va); 1825 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va); 1826 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va); 1827 1828 /* Initialize page zero/copy mutexes. */ 1829 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1830 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1831 1832 /* Allocate KVA space for ptbl bufs. */ 1833 ptbl_buf_pool_vabase = virtual_avail; 1834 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1835 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1836 ptbl_buf_pool_vabase, virtual_avail); 1837 1838 /* Calculate corresponding physical addresses for the kernel region. */ 1839 phys_kernelend = kernload + kernsize; 1840 debugf("kernel image and allocated data:\n"); 1841 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1842 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart); 1843 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize); 1844 1845 /* 1846 * Remove kernel physical address range from avail regions list. Page 1847 * align all regions. Non-page aligned memory isn't very interesting 1848 * to us. Also, sort the entries for ascending addresses. 1849 */ 1850 1851 /* Retrieve phys/avail mem regions */ 1852 mem_regions(&physmem_regions, &physmem_regions_sz, 1853 &availmem_regions, &availmem_regions_sz); 1854 1855 if (nitems(phys_avail) < availmem_regions_sz) 1856 panic("mmu_booke_bootstrap: phys_avail too small"); 1857 1858 sz = 0; 1859 cnt = availmem_regions_sz; 1860 debugf("processing avail regions:\n"); 1861 for (mp = availmem_regions; mp->mr_size; mp++) { 1862 s = mp->mr_start; 1863 e = mp->mr_start + mp->mr_size; 1864 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1865 /* Check whether this region holds all of the kernel. */ 1866 if (s < kernload && e > phys_kernelend) { 1867 availmem_regions[cnt].mr_start = phys_kernelend; 1868 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1869 e = kernload; 1870 } 1871 /* Look whether this regions starts within the kernel. */ 1872 if (s >= kernload && s < phys_kernelend) { 1873 if (e <= phys_kernelend) 1874 goto empty; 1875 s = phys_kernelend; 1876 } 1877 /* Now look whether this region ends within the kernel. */ 1878 if (e > kernload && e <= phys_kernelend) { 1879 if (s >= kernload) 1880 goto empty; 1881 e = kernload; 1882 } 1883 /* Now page align the start and size of the region. */ 1884 s = round_page(s); 1885 e = trunc_page(e); 1886 if (e < s) 1887 e = s; 1888 sz = e - s; 1889 debugf("%09jx-%09jx = %jx\n", 1890 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1891 1892 /* Check whether some memory is left here. */ 1893 if (sz == 0) { 1894 empty: 1895 memmove(mp, mp + 1, 1896 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1897 cnt--; 1898 mp--; 1899 continue; 1900 } 1901 1902 /* Do an insertion sort. */ 1903 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1904 if (s < mp1->mr_start) 1905 break; 1906 if (mp1 < mp) { 1907 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1908 mp1->mr_start = s; 1909 mp1->mr_size = sz; 1910 } else { 1911 mp->mr_start = s; 1912 mp->mr_size = sz; 1913 } 1914 } 1915 availmem_regions_sz = cnt; 1916 1917 /*******************************************************/ 1918 /* Steal physical memory for kernel stack from the end */ 1919 /* of the first avail region */ 1920 /*******************************************************/ 1921 kstack0_sz = kstack_pages * PAGE_SIZE; 1922 kstack0_phys = availmem_regions[0].mr_start + 1923 availmem_regions[0].mr_size; 1924 kstack0_phys -= kstack0_sz; 1925 availmem_regions[0].mr_size -= kstack0_sz; 1926 1927 /*******************************************************/ 1928 /* Fill in phys_avail table, based on availmem_regions */ 1929 /*******************************************************/ 1930 phys_avail_count = 0; 1931 physsz = 0; 1932 hwphyssz = 0; 1933 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1934 1935 debugf("fill in phys_avail:\n"); 1936 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1937 1938 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1939 (uintmax_t)availmem_regions[i].mr_start, 1940 (uintmax_t)availmem_regions[i].mr_start + 1941 availmem_regions[i].mr_size, 1942 (uintmax_t)availmem_regions[i].mr_size); 1943 1944 if (hwphyssz != 0 && 1945 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1946 debugf(" hw.physmem adjust\n"); 1947 if (physsz < hwphyssz) { 1948 phys_avail[j] = availmem_regions[i].mr_start; 1949 phys_avail[j + 1] = 1950 availmem_regions[i].mr_start + 1951 hwphyssz - physsz; 1952 physsz = hwphyssz; 1953 phys_avail_count++; 1954 } 1955 break; 1956 } 1957 1958 phys_avail[j] = availmem_regions[i].mr_start; 1959 phys_avail[j + 1] = availmem_regions[i].mr_start + 1960 availmem_regions[i].mr_size; 1961 phys_avail_count++; 1962 physsz += availmem_regions[i].mr_size; 1963 } 1964 physmem = btoc(physsz); 1965 1966 /* Calculate the last available physical address. */ 1967 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1968 ; 1969 Maxmem = powerpc_btop(phys_avail[i + 1]); 1970 1971 debugf("Maxmem = 0x%08lx\n", Maxmem); 1972 debugf("phys_avail_count = %d\n", phys_avail_count); 1973 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1974 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1975 1976 #ifdef __powerpc64__ 1977 /* 1978 * Map the physical memory contiguously in TLB1. 1979 * Round so it fits into a single mapping. 1980 */ 1981 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0, 1982 phys_avail[i + 1]); 1983 #endif 1984 1985 /*******************************************************/ 1986 /* Initialize (statically allocated) kernel pmap. */ 1987 /*******************************************************/ 1988 PMAP_LOCK_INIT(kernel_pmap); 1989 #ifndef __powerpc64__ 1990 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1991 #endif 1992 1993 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap); 1994 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir); 1995 for (i = 0; i < MAXCPU; i++) { 1996 kernel_pmap->pm_tid[i] = TID_KERNEL; 1997 1998 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1999 tidbusy[i][TID_KERNEL] = kernel_pmap; 2000 } 2001 2002 /* Mark kernel_pmap active on all CPUs */ 2003 CPU_FILL(&kernel_pmap->pm_active); 2004 2005 /* 2006 * Initialize the global pv list lock. 2007 */ 2008 rw_init(&pvh_global_lock, "pmap pv global"); 2009 2010 /*******************************************************/ 2011 /* Final setup */ 2012 /*******************************************************/ 2013 2014 /* Enter kstack0 into kernel map, provide guard page */ 2015 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 2016 thread0.td_kstack = kstack0; 2017 thread0.td_kstack_pages = kstack_pages; 2018 2019 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 2020 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 2021 kstack0_phys, kstack0_phys + kstack0_sz); 2022 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n", 2023 kstack0, kstack0 + kstack0_sz); 2024 2025 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 2026 for (i = 0; i < kstack_pages; i++) { 2027 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 2028 kstack0 += PAGE_SIZE; 2029 kstack0_phys += PAGE_SIZE; 2030 } 2031 2032 pmap_bootstrapped = 1; 2033 2034 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail); 2035 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end); 2036 2037 debugf("mmu_booke_bootstrap: exit\n"); 2038 } 2039 2040 #ifdef SMP 2041 void 2042 tlb1_ap_prep(void) 2043 { 2044 tlb_entry_t *e, tmp; 2045 unsigned int i; 2046 2047 /* Prepare TLB1 image for AP processors */ 2048 e = __boot_tlb1; 2049 for (i = 0; i < TLB1_ENTRIES; i++) { 2050 tlb1_read_entry(&tmp, i); 2051 2052 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 2053 memcpy(e++, &tmp, sizeof(tmp)); 2054 } 2055 } 2056 2057 void 2058 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 2059 { 2060 int i; 2061 2062 /* 2063 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 2064 * have the snapshot of its contents in the s/w __boot_tlb1[] table 2065 * created by tlb1_ap_prep(), so use these values directly to 2066 * (re)program AP's TLB1 hardware. 2067 * 2068 * Start at index 1 because index 0 has the kernel map. 2069 */ 2070 for (i = 1; i < TLB1_ENTRIES; i++) { 2071 if (__boot_tlb1[i].mas1 & MAS1_VALID) 2072 tlb1_write_entry(&__boot_tlb1[i], i); 2073 } 2074 2075 set_mas4_defaults(); 2076 } 2077 #endif 2078 2079 static void 2080 booke_pmap_init_qpages(void) 2081 { 2082 struct pcpu *pc; 2083 int i; 2084 2085 CPU_FOREACH(i) { 2086 pc = pcpu_find(i); 2087 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 2088 if (pc->pc_qmap_addr == 0) 2089 panic("pmap_init_qpages: unable to allocate KVA"); 2090 } 2091 } 2092 2093 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 2094 2095 /* 2096 * Get the physical page address for the given pmap/virtual address. 2097 */ 2098 static vm_paddr_t 2099 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 2100 { 2101 vm_paddr_t pa; 2102 2103 PMAP_LOCK(pmap); 2104 pa = pte_vatopa(mmu, pmap, va); 2105 PMAP_UNLOCK(pmap); 2106 2107 return (pa); 2108 } 2109 2110 /* 2111 * Extract the physical page address associated with the given 2112 * kernel virtual address. 2113 */ 2114 static vm_paddr_t 2115 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 2116 { 2117 tlb_entry_t e; 2118 vm_paddr_t p = 0; 2119 int i; 2120 2121 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS) 2122 p = pte_vatopa(mmu, kernel_pmap, va); 2123 2124 if (p == 0) { 2125 /* Check TLB1 mappings */ 2126 for (i = 0; i < TLB1_ENTRIES; i++) { 2127 tlb1_read_entry(&e, i); 2128 if (!(e.mas1 & MAS1_VALID)) 2129 continue; 2130 if (va >= e.virt && va < e.virt + e.size) 2131 return (e.phys + (va - e.virt)); 2132 } 2133 } 2134 2135 return (p); 2136 } 2137 2138 /* 2139 * Initialize the pmap module. 2140 * Called by vm_init, to initialize any structures that the pmap 2141 * system needs to map virtual memory. 2142 */ 2143 static void 2144 mmu_booke_init(mmu_t mmu) 2145 { 2146 int shpgperproc = PMAP_SHPGPERPROC; 2147 2148 /* 2149 * Initialize the address space (zone) for the pv entries. Set a 2150 * high water mark so that the system can recover from excessive 2151 * numbers of pv entries. 2152 */ 2153 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 2154 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 2155 2156 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 2157 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 2158 2159 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 2160 pv_entry_high_water = 9 * (pv_entry_max / 10); 2161 2162 uma_zone_reserve_kva(pvzone, pv_entry_max); 2163 2164 /* Pre-fill pvzone with initial number of pv entries. */ 2165 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 2166 2167 /* Initialize ptbl allocation. */ 2168 ptbl_init(); 2169 } 2170 2171 /* 2172 * Map a list of wired pages into kernel virtual address space. This is 2173 * intended for temporary mappings which do not need page modification or 2174 * references recorded. Existing mappings in the region are overwritten. 2175 */ 2176 static void 2177 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 2178 { 2179 vm_offset_t va; 2180 2181 va = sva; 2182 while (count-- > 0) { 2183 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2184 va += PAGE_SIZE; 2185 m++; 2186 } 2187 } 2188 2189 /* 2190 * Remove page mappings from kernel virtual address space. Intended for 2191 * temporary mappings entered by mmu_booke_qenter. 2192 */ 2193 static void 2194 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 2195 { 2196 vm_offset_t va; 2197 2198 va = sva; 2199 while (count-- > 0) { 2200 mmu_booke_kremove(mmu, va); 2201 va += PAGE_SIZE; 2202 } 2203 } 2204 2205 /* 2206 * Map a wired page into kernel virtual address space. 2207 */ 2208 static void 2209 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 2210 { 2211 2212 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 2213 } 2214 2215 static void 2216 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 2217 { 2218 uint32_t flags; 2219 pte_t *pte; 2220 2221 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 2222 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 2223 2224 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2225 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 2226 flags |= PTE_PS_4KB; 2227 2228 pte = pte_find(mmu, kernel_pmap, va); 2229 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE")); 2230 2231 mtx_lock_spin(&tlbivax_mutex); 2232 tlb_miss_lock(); 2233 2234 if (PTE_ISVALID(pte)) { 2235 2236 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 2237 2238 /* Flush entry from TLB0 */ 2239 tlb0_flush_entry(va); 2240 } 2241 2242 *pte = PTE_RPN_FROM_PA(pa) | flags; 2243 2244 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 2245 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 2246 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 2247 2248 /* Flush the real memory from the instruction cache. */ 2249 if ((flags & (PTE_I | PTE_G)) == 0) 2250 __syncicache((void *)va, PAGE_SIZE); 2251 2252 tlb_miss_unlock(); 2253 mtx_unlock_spin(&tlbivax_mutex); 2254 } 2255 2256 /* 2257 * Remove a page from kernel page table. 2258 */ 2259 static void 2260 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 2261 { 2262 pte_t *pte; 2263 2264 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va); 2265 2266 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 2267 (va <= VM_MAX_KERNEL_ADDRESS)), 2268 ("mmu_booke_kremove: invalid va")); 2269 2270 pte = pte_find(mmu, kernel_pmap, va); 2271 2272 if (!PTE_ISVALID(pte)) { 2273 2274 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 2275 2276 return; 2277 } 2278 2279 mtx_lock_spin(&tlbivax_mutex); 2280 tlb_miss_lock(); 2281 2282 /* Invalidate entry in TLB0, update PTE. */ 2283 tlb0_flush_entry(va); 2284 *pte = 0; 2285 2286 tlb_miss_unlock(); 2287 mtx_unlock_spin(&tlbivax_mutex); 2288 } 2289 2290 /* 2291 * Provide a kernel pointer corresponding to a given userland pointer. 2292 * The returned pointer is valid until the next time this function is 2293 * called in this thread. This is used internally in copyin/copyout. 2294 */ 2295 int 2296 mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 2297 void **kaddr, size_t ulen, size_t *klen) 2298 { 2299 2300 if ((uintptr_t)uaddr + ulen > VM_MAXUSER_ADDRESS + PAGE_SIZE) 2301 return (EFAULT); 2302 2303 *kaddr = (void *)(uintptr_t)uaddr; 2304 if (klen) 2305 *klen = ulen; 2306 2307 return (0); 2308 } 2309 2310 /* 2311 * Figure out where a given kernel pointer (usually in a fault) points 2312 * to from the VM's perspective, potentially remapping into userland's 2313 * address space. 2314 */ 2315 static int 2316 mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2317 vm_offset_t *decoded_addr) 2318 { 2319 2320 if (addr < VM_MAXUSER_ADDRESS) 2321 *is_user = 1; 2322 else 2323 *is_user = 0; 2324 2325 *decoded_addr = addr; 2326 return (0); 2327 } 2328 2329 /* 2330 * Initialize pmap associated with process 0. 2331 */ 2332 static void 2333 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 2334 { 2335 2336 PMAP_LOCK_INIT(pmap); 2337 mmu_booke_pinit(mmu, pmap); 2338 PCPU_SET(curpmap, pmap); 2339 } 2340 2341 /* 2342 * Initialize a preallocated and zeroed pmap structure, 2343 * such as one in a vmspace structure. 2344 */ 2345 static void 2346 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 2347 { 2348 int i; 2349 2350 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 2351 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 2352 2353 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 2354 2355 for (i = 0; i < MAXCPU; i++) 2356 pmap->pm_tid[i] = TID_NONE; 2357 CPU_ZERO(&kernel_pmap->pm_active); 2358 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2359 #ifdef __powerpc64__ 2360 bzero(&pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES); 2361 TAILQ_INIT(&pmap->pm_pdir_list); 2362 #else 2363 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 2364 #endif 2365 TAILQ_INIT(&pmap->pm_ptbl_list); 2366 } 2367 2368 /* 2369 * Release any resources held by the given physical map. 2370 * Called when a pmap initialized by mmu_booke_pinit is being released. 2371 * Should only be called if the map contains no valid mappings. 2372 */ 2373 static void 2374 mmu_booke_release(mmu_t mmu, pmap_t pmap) 2375 { 2376 2377 KASSERT(pmap->pm_stats.resident_count == 0, 2378 ("pmap_release: pmap resident count %ld != 0", 2379 pmap->pm_stats.resident_count)); 2380 } 2381 2382 /* 2383 * Insert the given physical page at the specified virtual address in the 2384 * target physical map with the protection requested. If specified the page 2385 * will be wired down. 2386 */ 2387 static int 2388 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2389 vm_prot_t prot, u_int flags, int8_t psind) 2390 { 2391 int error; 2392 2393 rw_wlock(&pvh_global_lock); 2394 PMAP_LOCK(pmap); 2395 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 2396 PMAP_UNLOCK(pmap); 2397 rw_wunlock(&pvh_global_lock); 2398 return (error); 2399 } 2400 2401 static int 2402 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2403 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 2404 { 2405 pte_t *pte; 2406 vm_paddr_t pa; 2407 uint32_t flags; 2408 int error, su, sync; 2409 2410 pa = VM_PAGE_TO_PHYS(m); 2411 su = (pmap == kernel_pmap); 2412 sync = 0; 2413 2414 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 2415 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 2416 // (u_int32_t)pmap, su, pmap->pm_tid, 2417 // (u_int32_t)m, va, pa, prot, flags); 2418 2419 if (su) { 2420 KASSERT(((va >= virtual_avail) && 2421 (va <= VM_MAX_KERNEL_ADDRESS)), 2422 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 2423 } else { 2424 KASSERT((va <= VM_MAXUSER_ADDRESS), 2425 ("mmu_booke_enter_locked: user pmap, non user va")); 2426 } 2427 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2428 VM_OBJECT_ASSERT_LOCKED(m->object); 2429 2430 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2431 2432 /* 2433 * If there is an existing mapping, and the physical address has not 2434 * changed, must be protection or wiring change. 2435 */ 2436 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 2437 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 2438 2439 /* 2440 * Before actually updating pte->flags we calculate and 2441 * prepare its new value in a helper var. 2442 */ 2443 flags = *pte; 2444 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 2445 2446 /* Wiring change, just update stats. */ 2447 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 2448 if (!PTE_ISWIRED(pte)) { 2449 flags |= PTE_WIRED; 2450 pmap->pm_stats.wired_count++; 2451 } 2452 } else { 2453 if (PTE_ISWIRED(pte)) { 2454 flags &= ~PTE_WIRED; 2455 pmap->pm_stats.wired_count--; 2456 } 2457 } 2458 2459 if (prot & VM_PROT_WRITE) { 2460 /* Add write permissions. */ 2461 flags |= PTE_SW; 2462 if (!su) 2463 flags |= PTE_UW; 2464 2465 if ((flags & PTE_MANAGED) != 0) 2466 vm_page_aflag_set(m, PGA_WRITEABLE); 2467 } else { 2468 /* Handle modified pages, sense modify status. */ 2469 2470 /* 2471 * The PTE_MODIFIED flag could be set by underlying 2472 * TLB misses since we last read it (above), possibly 2473 * other CPUs could update it so we check in the PTE 2474 * directly rather than rely on that saved local flags 2475 * copy. 2476 */ 2477 if (PTE_ISMODIFIED(pte)) 2478 vm_page_dirty(m); 2479 } 2480 2481 if (prot & VM_PROT_EXECUTE) { 2482 flags |= PTE_SX; 2483 if (!su) 2484 flags |= PTE_UX; 2485 2486 /* 2487 * Check existing flags for execute permissions: if we 2488 * are turning execute permissions on, icache should 2489 * be flushed. 2490 */ 2491 if ((*pte & (PTE_UX | PTE_SX)) == 0) 2492 sync++; 2493 } 2494 2495 flags &= ~PTE_REFERENCED; 2496 2497 /* 2498 * The new flags value is all calculated -- only now actually 2499 * update the PTE. 2500 */ 2501 mtx_lock_spin(&tlbivax_mutex); 2502 tlb_miss_lock(); 2503 2504 tlb0_flush_entry(va); 2505 *pte &= ~PTE_FLAGS_MASK; 2506 *pte |= flags; 2507 2508 tlb_miss_unlock(); 2509 mtx_unlock_spin(&tlbivax_mutex); 2510 2511 } else { 2512 /* 2513 * If there is an existing mapping, but it's for a different 2514 * physical address, pte_enter() will delete the old mapping. 2515 */ 2516 //if ((pte != NULL) && PTE_ISVALID(pte)) 2517 // debugf("mmu_booke_enter_locked: replace\n"); 2518 //else 2519 // debugf("mmu_booke_enter_locked: new\n"); 2520 2521 /* Now set up the flags and install the new mapping. */ 2522 flags = (PTE_SR | PTE_VALID); 2523 flags |= PTE_M; 2524 2525 if (!su) 2526 flags |= PTE_UR; 2527 2528 if (prot & VM_PROT_WRITE) { 2529 flags |= PTE_SW; 2530 if (!su) 2531 flags |= PTE_UW; 2532 2533 if ((m->oflags & VPO_UNMANAGED) == 0) 2534 vm_page_aflag_set(m, PGA_WRITEABLE); 2535 } 2536 2537 if (prot & VM_PROT_EXECUTE) { 2538 flags |= PTE_SX; 2539 if (!su) 2540 flags |= PTE_UX; 2541 } 2542 2543 /* If its wired update stats. */ 2544 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 2545 flags |= PTE_WIRED; 2546 2547 error = pte_enter(mmu, pmap, m, va, flags, 2548 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 2549 if (error != 0) 2550 return (KERN_RESOURCE_SHORTAGE); 2551 2552 if ((flags & PMAP_ENTER_WIRED) != 0) 2553 pmap->pm_stats.wired_count++; 2554 2555 /* Flush the real memory from the instruction cache. */ 2556 if (prot & VM_PROT_EXECUTE) 2557 sync++; 2558 } 2559 2560 if (sync && (su || pmap == PCPU_GET(curpmap))) { 2561 __syncicache((void *)va, PAGE_SIZE); 2562 sync = 0; 2563 } 2564 2565 return (KERN_SUCCESS); 2566 } 2567 2568 /* 2569 * Maps a sequence of resident pages belonging to the same object. 2570 * The sequence begins with the given page m_start. This page is 2571 * mapped at the given virtual address start. Each subsequent page is 2572 * mapped at a virtual address that is offset from start by the same 2573 * amount as the page is offset from m_start within the object. The 2574 * last page in the sequence is the page with the largest offset from 2575 * m_start that can be mapped at a virtual address less than the given 2576 * virtual address end. Not every virtual page between start and end 2577 * is mapped; only those for which a resident page exists with the 2578 * corresponding offset from m_start are mapped. 2579 */ 2580 static void 2581 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 2582 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 2583 { 2584 vm_page_t m; 2585 vm_pindex_t diff, psize; 2586 2587 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2588 2589 psize = atop(end - start); 2590 m = m_start; 2591 rw_wlock(&pvh_global_lock); 2592 PMAP_LOCK(pmap); 2593 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2594 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 2595 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 2596 PMAP_ENTER_NOSLEEP, 0); 2597 m = TAILQ_NEXT(m, listq); 2598 } 2599 rw_wunlock(&pvh_global_lock); 2600 PMAP_UNLOCK(pmap); 2601 } 2602 2603 static void 2604 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2605 vm_prot_t prot) 2606 { 2607 2608 rw_wlock(&pvh_global_lock); 2609 PMAP_LOCK(pmap); 2610 mmu_booke_enter_locked(mmu, pmap, va, m, 2611 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 2612 0); 2613 rw_wunlock(&pvh_global_lock); 2614 PMAP_UNLOCK(pmap); 2615 } 2616 2617 /* 2618 * Remove the given range of addresses from the specified map. 2619 * 2620 * It is assumed that the start and end are properly rounded to the page size. 2621 */ 2622 static void 2623 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 2624 { 2625 pte_t *pte; 2626 uint8_t hold_flag; 2627 2628 int su = (pmap == kernel_pmap); 2629 2630 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 2631 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 2632 2633 if (su) { 2634 KASSERT(((va >= virtual_avail) && 2635 (va <= VM_MAX_KERNEL_ADDRESS)), 2636 ("mmu_booke_remove: kernel pmap, non kernel va")); 2637 } else { 2638 KASSERT((va <= VM_MAXUSER_ADDRESS), 2639 ("mmu_booke_remove: user pmap, non user va")); 2640 } 2641 2642 if (PMAP_REMOVE_DONE(pmap)) { 2643 //debugf("mmu_booke_remove: e (empty)\n"); 2644 return; 2645 } 2646 2647 hold_flag = PTBL_HOLD_FLAG(pmap); 2648 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 2649 2650 rw_wlock(&pvh_global_lock); 2651 PMAP_LOCK(pmap); 2652 for (; va < endva; va += PAGE_SIZE) { 2653 pte = pte_find(mmu, pmap, va); 2654 if ((pte != NULL) && PTE_ISVALID(pte)) 2655 pte_remove(mmu, pmap, va, hold_flag); 2656 } 2657 PMAP_UNLOCK(pmap); 2658 rw_wunlock(&pvh_global_lock); 2659 2660 //debugf("mmu_booke_remove: e\n"); 2661 } 2662 2663 /* 2664 * Remove physical page from all pmaps in which it resides. 2665 */ 2666 static void 2667 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 2668 { 2669 pv_entry_t pv, pvn; 2670 uint8_t hold_flag; 2671 2672 rw_wlock(&pvh_global_lock); 2673 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 2674 pvn = TAILQ_NEXT(pv, pv_link); 2675 2676 PMAP_LOCK(pv->pv_pmap); 2677 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 2678 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 2679 PMAP_UNLOCK(pv->pv_pmap); 2680 } 2681 vm_page_aflag_clear(m, PGA_WRITEABLE); 2682 rw_wunlock(&pvh_global_lock); 2683 } 2684 2685 /* 2686 * Map a range of physical addresses into kernel virtual address space. 2687 */ 2688 static vm_offset_t 2689 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2690 vm_paddr_t pa_end, int prot) 2691 { 2692 vm_offset_t sva = *virt; 2693 vm_offset_t va = sva; 2694 2695 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 2696 // sva, pa_start, pa_end); 2697 2698 while (pa_start < pa_end) { 2699 mmu_booke_kenter(mmu, va, pa_start); 2700 va += PAGE_SIZE; 2701 pa_start += PAGE_SIZE; 2702 } 2703 *virt = va; 2704 2705 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 2706 return (sva); 2707 } 2708 2709 /* 2710 * The pmap must be activated before it's address space can be accessed in any 2711 * way. 2712 */ 2713 static void 2714 mmu_booke_activate(mmu_t mmu, struct thread *td) 2715 { 2716 pmap_t pmap; 2717 u_int cpuid; 2718 2719 pmap = &td->td_proc->p_vmspace->vm_pmap; 2720 2721 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")", 2722 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2723 2724 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 2725 2726 sched_pin(); 2727 2728 cpuid = PCPU_GET(cpuid); 2729 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 2730 PCPU_SET(curpmap, pmap); 2731 2732 if (pmap->pm_tid[cpuid] == TID_NONE) 2733 tid_alloc(pmap); 2734 2735 /* Load PID0 register with pmap tid value. */ 2736 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 2737 __asm __volatile("isync"); 2738 2739 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2740 2741 sched_unpin(); 2742 2743 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2744 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2745 } 2746 2747 /* 2748 * Deactivate the specified process's address space. 2749 */ 2750 static void 2751 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2752 { 2753 pmap_t pmap; 2754 2755 pmap = &td->td_proc->p_vmspace->vm_pmap; 2756 2757 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX, 2758 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2759 2760 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2761 2762 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2763 PCPU_SET(curpmap, NULL); 2764 } 2765 2766 /* 2767 * Copy the range specified by src_addr/len 2768 * from the source map to the range dst_addr/len 2769 * in the destination map. 2770 * 2771 * This routine is only advisory and need not do anything. 2772 */ 2773 static void 2774 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2775 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2776 { 2777 2778 } 2779 2780 /* 2781 * Set the physical protection on the specified range of this map as requested. 2782 */ 2783 static void 2784 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2785 vm_prot_t prot) 2786 { 2787 vm_offset_t va; 2788 vm_page_t m; 2789 pte_t *pte; 2790 2791 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2792 mmu_booke_remove(mmu, pmap, sva, eva); 2793 return; 2794 } 2795 2796 if (prot & VM_PROT_WRITE) 2797 return; 2798 2799 PMAP_LOCK(pmap); 2800 for (va = sva; va < eva; va += PAGE_SIZE) { 2801 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2802 if (PTE_ISVALID(pte)) { 2803 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2804 2805 mtx_lock_spin(&tlbivax_mutex); 2806 tlb_miss_lock(); 2807 2808 /* Handle modified pages. */ 2809 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2810 vm_page_dirty(m); 2811 2812 tlb0_flush_entry(va); 2813 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2814 2815 tlb_miss_unlock(); 2816 mtx_unlock_spin(&tlbivax_mutex); 2817 } 2818 } 2819 } 2820 PMAP_UNLOCK(pmap); 2821 } 2822 2823 /* 2824 * Clear the write and modified bits in each of the given page's mappings. 2825 */ 2826 static void 2827 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2828 { 2829 pv_entry_t pv; 2830 pte_t *pte; 2831 2832 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2833 ("mmu_booke_remove_write: page %p is not managed", m)); 2834 2835 /* 2836 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2837 * set by another thread while the object is locked. Thus, 2838 * if PGA_WRITEABLE is clear, no page table entries need updating. 2839 */ 2840 VM_OBJECT_ASSERT_WLOCKED(m->object); 2841 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2842 return; 2843 rw_wlock(&pvh_global_lock); 2844 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2845 PMAP_LOCK(pv->pv_pmap); 2846 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2847 if (PTE_ISVALID(pte)) { 2848 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2849 2850 mtx_lock_spin(&tlbivax_mutex); 2851 tlb_miss_lock(); 2852 2853 /* Handle modified pages. */ 2854 if (PTE_ISMODIFIED(pte)) 2855 vm_page_dirty(m); 2856 2857 /* Flush mapping from TLB0. */ 2858 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2859 2860 tlb_miss_unlock(); 2861 mtx_unlock_spin(&tlbivax_mutex); 2862 } 2863 } 2864 PMAP_UNLOCK(pv->pv_pmap); 2865 } 2866 vm_page_aflag_clear(m, PGA_WRITEABLE); 2867 rw_wunlock(&pvh_global_lock); 2868 } 2869 2870 static void 2871 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2872 { 2873 pte_t *pte; 2874 vm_paddr_t pa = 0; 2875 int sync_sz, valid; 2876 #ifndef __powerpc64__ 2877 pmap_t pmap; 2878 vm_page_t m; 2879 vm_offset_t addr; 2880 int active; 2881 #endif 2882 2883 #ifndef __powerpc64__ 2884 rw_wlock(&pvh_global_lock); 2885 pmap = PCPU_GET(curpmap); 2886 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2887 #endif 2888 while (sz > 0) { 2889 PMAP_LOCK(pm); 2890 pte = pte_find(mmu, pm, va); 2891 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2892 if (valid) 2893 pa = PTE_PA(pte); 2894 PMAP_UNLOCK(pm); 2895 sync_sz = PAGE_SIZE - (va & PAGE_MASK); 2896 sync_sz = min(sync_sz, sz); 2897 if (valid) { 2898 #ifdef __powerpc64__ 2899 pa += (va & PAGE_MASK); 2900 __syncicache((void *)PHYS_TO_DMAP(pa), sync_sz); 2901 #else 2902 if (!active) { 2903 /* Create a mapping in the active pmap. */ 2904 addr = 0; 2905 m = PHYS_TO_VM_PAGE(pa); 2906 PMAP_LOCK(pmap); 2907 pte_enter(mmu, pmap, m, addr, 2908 PTE_SR | PTE_VALID, FALSE); 2909 addr += (va & PAGE_MASK); 2910 __syncicache((void *)addr, sync_sz); 2911 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2912 PMAP_UNLOCK(pmap); 2913 } else 2914 __syncicache((void *)va, sync_sz); 2915 #endif 2916 } 2917 va += sync_sz; 2918 sz -= sync_sz; 2919 } 2920 #ifndef __powerpc64__ 2921 rw_wunlock(&pvh_global_lock); 2922 #endif 2923 } 2924 2925 /* 2926 * Atomically extract and hold the physical page with the given 2927 * pmap and virtual address pair if that mapping permits the given 2928 * protection. 2929 */ 2930 static vm_page_t 2931 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2932 vm_prot_t prot) 2933 { 2934 pte_t *pte; 2935 vm_page_t m; 2936 uint32_t pte_wbit; 2937 vm_paddr_t pa; 2938 2939 m = NULL; 2940 pa = 0; 2941 PMAP_LOCK(pmap); 2942 retry: 2943 pte = pte_find(mmu, pmap, va); 2944 if ((pte != NULL) && PTE_ISVALID(pte)) { 2945 if (pmap == kernel_pmap) 2946 pte_wbit = PTE_SW; 2947 else 2948 pte_wbit = PTE_UW; 2949 2950 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2951 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2952 goto retry; 2953 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2954 vm_page_hold(m); 2955 } 2956 } 2957 2958 PA_UNLOCK_COND(pa); 2959 PMAP_UNLOCK(pmap); 2960 return (m); 2961 } 2962 2963 /* 2964 * Initialize a vm_page's machine-dependent fields. 2965 */ 2966 static void 2967 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2968 { 2969 2970 m->md.pv_tracked = 0; 2971 TAILQ_INIT(&m->md.pv_list); 2972 } 2973 2974 /* 2975 * mmu_booke_zero_page_area zeros the specified hardware page by 2976 * mapping it into virtual memory and using bzero to clear 2977 * its contents. 2978 * 2979 * off and size must reside within a single page. 2980 */ 2981 static void 2982 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2983 { 2984 vm_offset_t va; 2985 2986 /* XXX KASSERT off and size are within a single page? */ 2987 2988 #ifdef __powerpc64__ 2989 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 2990 bzero((caddr_t)va + off, size); 2991 #else 2992 mtx_lock(&zero_page_mutex); 2993 va = zero_page_va; 2994 2995 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2996 bzero((caddr_t)va + off, size); 2997 mmu_booke_kremove(mmu, va); 2998 2999 mtx_unlock(&zero_page_mutex); 3000 #endif 3001 } 3002 3003 /* 3004 * mmu_booke_zero_page zeros the specified hardware page. 3005 */ 3006 static void 3007 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 3008 { 3009 vm_offset_t off, va; 3010 3011 #ifdef __powerpc64__ 3012 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3013 3014 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 3015 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 3016 #else 3017 va = zero_page_va; 3018 mtx_lock(&zero_page_mutex); 3019 3020 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 3021 3022 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 3023 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 3024 3025 mmu_booke_kremove(mmu, va); 3026 3027 mtx_unlock(&zero_page_mutex); 3028 #endif 3029 } 3030 3031 /* 3032 * mmu_booke_copy_page copies the specified (machine independent) page by 3033 * mapping the page into virtual memory and using memcopy to copy the page, 3034 * one machine dependent page at a time. 3035 */ 3036 static void 3037 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 3038 { 3039 vm_offset_t sva, dva; 3040 3041 #ifdef __powerpc64__ 3042 sva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(sm)); 3043 dva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dm)); 3044 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 3045 #else 3046 mtx_lock(©_page_mutex); 3047 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 3048 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 3049 sva = copy_page_src_va; 3050 dva = copy_page_dst_va; 3051 3052 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 3053 3054 mmu_booke_kremove(mmu, dva); 3055 mmu_booke_kremove(mmu, sva); 3056 mtx_unlock(©_page_mutex); 3057 #endif 3058 } 3059 3060 static inline void 3061 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 3062 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 3063 { 3064 void *a_cp, *b_cp; 3065 vm_offset_t a_pg_offset, b_pg_offset; 3066 int cnt; 3067 3068 #ifdef __powerpc64__ 3069 vm_page_t pa, pb; 3070 3071 while (xfersize > 0) { 3072 a_pg_offset = a_offset & PAGE_MASK; 3073 pa = ma[a_offset >> PAGE_SHIFT]; 3074 b_pg_offset = b_offset & PAGE_MASK; 3075 pb = mb[b_offset >> PAGE_SHIFT]; 3076 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3077 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3078 a_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pa)) + 3079 a_pg_offset); 3080 b_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pb)) + 3081 b_pg_offset); 3082 bcopy(a_cp, b_cp, cnt); 3083 a_offset += cnt; 3084 b_offset += cnt; 3085 xfersize -= cnt; 3086 } 3087 #else 3088 mtx_lock(©_page_mutex); 3089 while (xfersize > 0) { 3090 a_pg_offset = a_offset & PAGE_MASK; 3091 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3092 mmu_booke_kenter(mmu, copy_page_src_va, 3093 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 3094 a_cp = (char *)copy_page_src_va + a_pg_offset; 3095 b_pg_offset = b_offset & PAGE_MASK; 3096 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3097 mmu_booke_kenter(mmu, copy_page_dst_va, 3098 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 3099 b_cp = (char *)copy_page_dst_va + b_pg_offset; 3100 bcopy(a_cp, b_cp, cnt); 3101 mmu_booke_kremove(mmu, copy_page_dst_va); 3102 mmu_booke_kremove(mmu, copy_page_src_va); 3103 a_offset += cnt; 3104 b_offset += cnt; 3105 xfersize -= cnt; 3106 } 3107 mtx_unlock(©_page_mutex); 3108 #endif 3109 } 3110 3111 static vm_offset_t 3112 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 3113 { 3114 #ifdef __powerpc64__ 3115 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 3116 #else 3117 vm_paddr_t paddr; 3118 vm_offset_t qaddr; 3119 uint32_t flags; 3120 pte_t *pte; 3121 3122 paddr = VM_PAGE_TO_PHYS(m); 3123 3124 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 3125 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 3126 flags |= PTE_PS_4KB; 3127 3128 critical_enter(); 3129 qaddr = PCPU_GET(qmap_addr); 3130 3131 pte = pte_find(mmu, kernel_pmap, qaddr); 3132 3133 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 3134 3135 /* 3136 * XXX: tlbivax is broadcast to other cores, but qaddr should 3137 * not be present in other TLBs. Is there a better instruction 3138 * sequence to use? Or just forget it & use mmu_booke_kenter()... 3139 */ 3140 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 3141 __asm __volatile("isync; msync"); 3142 3143 *pte = PTE_RPN_FROM_PA(paddr) | flags; 3144 3145 /* Flush the real memory from the instruction cache. */ 3146 if ((flags & (PTE_I | PTE_G)) == 0) 3147 __syncicache((void *)qaddr, PAGE_SIZE); 3148 3149 return (qaddr); 3150 #endif 3151 } 3152 3153 static void 3154 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 3155 { 3156 #ifndef __powerpc64__ 3157 pte_t *pte; 3158 3159 pte = pte_find(mmu, kernel_pmap, addr); 3160 3161 KASSERT(PCPU_GET(qmap_addr) == addr, 3162 ("mmu_booke_quick_remove_page: invalid address")); 3163 KASSERT(*pte != 0, 3164 ("mmu_booke_quick_remove_page: PTE not in use")); 3165 3166 *pte = 0; 3167 critical_exit(); 3168 #endif 3169 } 3170 3171 /* 3172 * Return whether or not the specified physical page was modified 3173 * in any of physical maps. 3174 */ 3175 static boolean_t 3176 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 3177 { 3178 pte_t *pte; 3179 pv_entry_t pv; 3180 boolean_t rv; 3181 3182 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3183 ("mmu_booke_is_modified: page %p is not managed", m)); 3184 rv = FALSE; 3185 3186 /* 3187 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3188 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3189 * is clear, no PTEs can be modified. 3190 */ 3191 VM_OBJECT_ASSERT_WLOCKED(m->object); 3192 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3193 return (rv); 3194 rw_wlock(&pvh_global_lock); 3195 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3196 PMAP_LOCK(pv->pv_pmap); 3197 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3198 PTE_ISVALID(pte)) { 3199 if (PTE_ISMODIFIED(pte)) 3200 rv = TRUE; 3201 } 3202 PMAP_UNLOCK(pv->pv_pmap); 3203 if (rv) 3204 break; 3205 } 3206 rw_wunlock(&pvh_global_lock); 3207 return (rv); 3208 } 3209 3210 /* 3211 * Return whether or not the specified virtual address is eligible 3212 * for prefault. 3213 */ 3214 static boolean_t 3215 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 3216 { 3217 3218 return (FALSE); 3219 } 3220 3221 /* 3222 * Return whether or not the specified physical page was referenced 3223 * in any physical maps. 3224 */ 3225 static boolean_t 3226 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 3227 { 3228 pte_t *pte; 3229 pv_entry_t pv; 3230 boolean_t rv; 3231 3232 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3233 ("mmu_booke_is_referenced: page %p is not managed", m)); 3234 rv = FALSE; 3235 rw_wlock(&pvh_global_lock); 3236 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3237 PMAP_LOCK(pv->pv_pmap); 3238 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3239 PTE_ISVALID(pte)) { 3240 if (PTE_ISREFERENCED(pte)) 3241 rv = TRUE; 3242 } 3243 PMAP_UNLOCK(pv->pv_pmap); 3244 if (rv) 3245 break; 3246 } 3247 rw_wunlock(&pvh_global_lock); 3248 return (rv); 3249 } 3250 3251 /* 3252 * Clear the modify bits on the specified physical page. 3253 */ 3254 static void 3255 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 3256 { 3257 pte_t *pte; 3258 pv_entry_t pv; 3259 3260 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3261 ("mmu_booke_clear_modify: page %p is not managed", m)); 3262 VM_OBJECT_ASSERT_WLOCKED(m->object); 3263 KASSERT(!vm_page_xbusied(m), 3264 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 3265 3266 /* 3267 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 3268 * If the object containing the page is locked and the page is not 3269 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 3270 */ 3271 if ((m->aflags & PGA_WRITEABLE) == 0) 3272 return; 3273 rw_wlock(&pvh_global_lock); 3274 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3275 PMAP_LOCK(pv->pv_pmap); 3276 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3277 PTE_ISVALID(pte)) { 3278 mtx_lock_spin(&tlbivax_mutex); 3279 tlb_miss_lock(); 3280 3281 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 3282 tlb0_flush_entry(pv->pv_va); 3283 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 3284 PTE_REFERENCED); 3285 } 3286 3287 tlb_miss_unlock(); 3288 mtx_unlock_spin(&tlbivax_mutex); 3289 } 3290 PMAP_UNLOCK(pv->pv_pmap); 3291 } 3292 rw_wunlock(&pvh_global_lock); 3293 } 3294 3295 /* 3296 * Return a count of reference bits for a page, clearing those bits. 3297 * It is not necessary for every reference bit to be cleared, but it 3298 * is necessary that 0 only be returned when there are truly no 3299 * reference bits set. 3300 * 3301 * As an optimization, update the page's dirty field if a modified bit is 3302 * found while counting reference bits. This opportunistic update can be 3303 * performed at low cost and can eliminate the need for some future calls 3304 * to pmap_is_modified(). However, since this function stops after 3305 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 3306 * dirty pages. Those dirty pages will only be detected by a future call 3307 * to pmap_is_modified(). 3308 */ 3309 static int 3310 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 3311 { 3312 pte_t *pte; 3313 pv_entry_t pv; 3314 int count; 3315 3316 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3317 ("mmu_booke_ts_referenced: page %p is not managed", m)); 3318 count = 0; 3319 rw_wlock(&pvh_global_lock); 3320 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3321 PMAP_LOCK(pv->pv_pmap); 3322 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3323 PTE_ISVALID(pte)) { 3324 if (PTE_ISMODIFIED(pte)) 3325 vm_page_dirty(m); 3326 if (PTE_ISREFERENCED(pte)) { 3327 mtx_lock_spin(&tlbivax_mutex); 3328 tlb_miss_lock(); 3329 3330 tlb0_flush_entry(pv->pv_va); 3331 *pte &= ~PTE_REFERENCED; 3332 3333 tlb_miss_unlock(); 3334 mtx_unlock_spin(&tlbivax_mutex); 3335 3336 if (++count >= PMAP_TS_REFERENCED_MAX) { 3337 PMAP_UNLOCK(pv->pv_pmap); 3338 break; 3339 } 3340 } 3341 } 3342 PMAP_UNLOCK(pv->pv_pmap); 3343 } 3344 rw_wunlock(&pvh_global_lock); 3345 return (count); 3346 } 3347 3348 /* 3349 * Clear the wired attribute from the mappings for the specified range of 3350 * addresses in the given pmap. Every valid mapping within that range must 3351 * have the wired attribute set. In contrast, invalid mappings cannot have 3352 * the wired attribute set, so they are ignored. 3353 * 3354 * The wired attribute of the page table entry is not a hardware feature, so 3355 * there is no need to invalidate any TLB entries. 3356 */ 3357 static void 3358 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3359 { 3360 vm_offset_t va; 3361 pte_t *pte; 3362 3363 PMAP_LOCK(pmap); 3364 for (va = sva; va < eva; va += PAGE_SIZE) { 3365 if ((pte = pte_find(mmu, pmap, va)) != NULL && 3366 PTE_ISVALID(pte)) { 3367 if (!PTE_ISWIRED(pte)) 3368 panic("mmu_booke_unwire: pte %p isn't wired", 3369 pte); 3370 *pte &= ~PTE_WIRED; 3371 pmap->pm_stats.wired_count--; 3372 } 3373 } 3374 PMAP_UNLOCK(pmap); 3375 3376 } 3377 3378 /* 3379 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 3380 * page. This count may be changed upwards or downwards in the future; it is 3381 * only necessary that true be returned for a small subset of pmaps for proper 3382 * page aging. 3383 */ 3384 static boolean_t 3385 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 3386 { 3387 pv_entry_t pv; 3388 int loops; 3389 boolean_t rv; 3390 3391 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3392 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 3393 loops = 0; 3394 rv = FALSE; 3395 rw_wlock(&pvh_global_lock); 3396 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3397 if (pv->pv_pmap == pmap) { 3398 rv = TRUE; 3399 break; 3400 } 3401 if (++loops >= 16) 3402 break; 3403 } 3404 rw_wunlock(&pvh_global_lock); 3405 return (rv); 3406 } 3407 3408 /* 3409 * Return the number of managed mappings to the given physical page that are 3410 * wired. 3411 */ 3412 static int 3413 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 3414 { 3415 pv_entry_t pv; 3416 pte_t *pte; 3417 int count = 0; 3418 3419 if ((m->oflags & VPO_UNMANAGED) != 0) 3420 return (count); 3421 rw_wlock(&pvh_global_lock); 3422 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3423 PMAP_LOCK(pv->pv_pmap); 3424 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 3425 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 3426 count++; 3427 PMAP_UNLOCK(pv->pv_pmap); 3428 } 3429 rw_wunlock(&pvh_global_lock); 3430 return (count); 3431 } 3432 3433 static int 3434 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 3435 { 3436 int i; 3437 vm_offset_t va; 3438 3439 /* 3440 * This currently does not work for entries that 3441 * overlap TLB1 entries. 3442 */ 3443 for (i = 0; i < TLB1_ENTRIES; i ++) { 3444 if (tlb1_iomapped(i, pa, size, &va) == 0) 3445 return (0); 3446 } 3447 3448 return (EFAULT); 3449 } 3450 3451 void 3452 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 3453 { 3454 vm_paddr_t ppa; 3455 vm_offset_t ofs; 3456 vm_size_t gran; 3457 3458 /* Minidumps are based on virtual memory addresses. */ 3459 if (do_minidump) { 3460 *va = (void *)(vm_offset_t)pa; 3461 return; 3462 } 3463 3464 /* Raw physical memory dumps don't have a virtual address. */ 3465 /* We always map a 256MB page at 256M. */ 3466 gran = 256 * 1024 * 1024; 3467 ppa = rounddown2(pa, gran); 3468 ofs = pa - ppa; 3469 *va = (void *)gran; 3470 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 3471 3472 if (sz > (gran - ofs)) 3473 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 3474 _TLB_ENTRY_IO); 3475 } 3476 3477 void 3478 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 3479 { 3480 vm_paddr_t ppa; 3481 vm_offset_t ofs; 3482 vm_size_t gran; 3483 tlb_entry_t e; 3484 int i; 3485 3486 /* Minidumps are based on virtual memory addresses. */ 3487 /* Nothing to do... */ 3488 if (do_minidump) 3489 return; 3490 3491 for (i = 0; i < TLB1_ENTRIES; i++) { 3492 tlb1_read_entry(&e, i); 3493 if (!(e.mas1 & MAS1_VALID)) 3494 break; 3495 } 3496 3497 /* Raw physical memory dumps don't have a virtual address. */ 3498 i--; 3499 e.mas1 = 0; 3500 e.mas2 = 0; 3501 e.mas3 = 0; 3502 tlb1_write_entry(&e, i); 3503 3504 gran = 256 * 1024 * 1024; 3505 ppa = rounddown2(pa, gran); 3506 ofs = pa - ppa; 3507 if (sz > (gran - ofs)) { 3508 i--; 3509 e.mas1 = 0; 3510 e.mas2 = 0; 3511 e.mas3 = 0; 3512 tlb1_write_entry(&e, i); 3513 } 3514 } 3515 3516 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 3517 3518 void 3519 mmu_booke_scan_init(mmu_t mmu) 3520 { 3521 vm_offset_t va; 3522 pte_t *pte; 3523 int i; 3524 3525 if (!do_minidump) { 3526 /* Initialize phys. segments for dumpsys(). */ 3527 memset(&dump_map, 0, sizeof(dump_map)); 3528 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 3529 &availmem_regions_sz); 3530 for (i = 0; i < physmem_regions_sz; i++) { 3531 dump_map[i].pa_start = physmem_regions[i].mr_start; 3532 dump_map[i].pa_size = physmem_regions[i].mr_size; 3533 } 3534 return; 3535 } 3536 3537 /* Virtual segments for minidumps: */ 3538 memset(&dump_map, 0, sizeof(dump_map)); 3539 3540 /* 1st: kernel .data and .bss. */ 3541 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 3542 dump_map[0].pa_size = 3543 round_page((uintptr_t)_end) - dump_map[0].pa_start; 3544 3545 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 3546 dump_map[1].pa_start = data_start; 3547 dump_map[1].pa_size = data_end - data_start; 3548 3549 /* 3rd: kernel VM. */ 3550 va = dump_map[1].pa_start + dump_map[1].pa_size; 3551 /* Find start of next chunk (from va). */ 3552 while (va < virtual_end) { 3553 /* Don't dump the buffer cache. */ 3554 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 3555 va = kmi.buffer_eva; 3556 continue; 3557 } 3558 pte = pte_find(mmu, kernel_pmap, va); 3559 if (pte != NULL && PTE_ISVALID(pte)) 3560 break; 3561 va += PAGE_SIZE; 3562 } 3563 if (va < virtual_end) { 3564 dump_map[2].pa_start = va; 3565 va += PAGE_SIZE; 3566 /* Find last page in chunk. */ 3567 while (va < virtual_end) { 3568 /* Don't run into the buffer cache. */ 3569 if (va == kmi.buffer_sva) 3570 break; 3571 pte = pte_find(mmu, kernel_pmap, va); 3572 if (pte == NULL || !PTE_ISVALID(pte)) 3573 break; 3574 va += PAGE_SIZE; 3575 } 3576 dump_map[2].pa_size = va - dump_map[2].pa_start; 3577 } 3578 } 3579 3580 /* 3581 * Map a set of physical memory pages into the kernel virtual address space. 3582 * Return a pointer to where it is mapped. This routine is intended to be used 3583 * for mapping device memory, NOT real memory. 3584 */ 3585 static void * 3586 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 3587 { 3588 3589 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 3590 } 3591 3592 static void * 3593 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 3594 { 3595 tlb_entry_t e; 3596 void *res; 3597 uintptr_t va, tmpva; 3598 vm_size_t sz; 3599 int i; 3600 3601 /* 3602 * Check if this is premapped in TLB1. Note: this should probably also 3603 * check whether a sequence of TLB1 entries exist that match the 3604 * requirement, but now only checks the easy case. 3605 */ 3606 for (i = 0; i < TLB1_ENTRIES; i++) { 3607 tlb1_read_entry(&e, i); 3608 if (!(e.mas1 & MAS1_VALID)) 3609 continue; 3610 if (pa >= e.phys && 3611 (pa + size) <= (e.phys + e.size) && 3612 (ma == VM_MEMATTR_DEFAULT || 3613 tlb_calc_wimg(pa, ma) == 3614 (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))) 3615 return (void *)(e.virt + 3616 (vm_offset_t)(pa - e.phys)); 3617 } 3618 3619 size = roundup(size, PAGE_SIZE); 3620 3621 /* 3622 * The device mapping area is between VM_MAXUSER_ADDRESS and 3623 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 3624 */ 3625 #ifdef SPARSE_MAPDEV 3626 /* 3627 * With a sparse mapdev, align to the largest starting region. This 3628 * could feasibly be optimized for a 'best-fit' alignment, but that 3629 * calculation could be very costly. 3630 * Align to the smaller of: 3631 * - first set bit in overlap of (pa & size mask) 3632 * - largest size envelope 3633 * 3634 * It's possible the device mapping may start at a PA that's not larger 3635 * than the size mask, so we need to offset in to maximize the TLB entry 3636 * range and minimize the number of used TLB entries. 3637 */ 3638 do { 3639 tmpva = tlb1_map_base; 3640 sz = ffsl(((1 << flsl(size-1)) - 1) & pa); 3641 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1; 3642 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa); 3643 #ifdef __powerpc64__ 3644 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size)); 3645 #else 3646 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 3647 #endif 3648 #else 3649 #ifdef __powerpc64__ 3650 va = atomic_fetchadd_long(&tlb1_map_base, size); 3651 #else 3652 va = atomic_fetchadd_int(&tlb1_map_base, size); 3653 #endif 3654 #endif 3655 res = (void *)va; 3656 3657 do { 3658 sz = 1 << (ilog2(size) & ~1); 3659 /* Align size to PA */ 3660 if (pa % sz != 0) { 3661 do { 3662 sz >>= 2; 3663 } while (pa % sz != 0); 3664 } 3665 /* Now align from there to VA */ 3666 if (va % sz != 0) { 3667 do { 3668 sz >>= 2; 3669 } while (va % sz != 0); 3670 } 3671 if (bootverbose) 3672 printf("Wiring VA=%lx to PA=%jx (size=%lx)\n", 3673 va, (uintmax_t)pa, sz); 3674 if (tlb1_set_entry(va, pa, sz, 3675 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)) < 0) 3676 return (NULL); 3677 size -= sz; 3678 pa += sz; 3679 va += sz; 3680 } while (size > 0); 3681 3682 return (res); 3683 } 3684 3685 /* 3686 * 'Unmap' a range mapped by mmu_booke_mapdev(). 3687 */ 3688 static void 3689 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 3690 { 3691 #ifdef SUPPORTS_SHRINKING_TLB1 3692 vm_offset_t base, offset; 3693 3694 /* 3695 * Unmap only if this is inside kernel virtual space. 3696 */ 3697 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 3698 base = trunc_page(va); 3699 offset = va & PAGE_MASK; 3700 size = roundup(offset + size, PAGE_SIZE); 3701 kva_free(base, size); 3702 } 3703 #endif 3704 } 3705 3706 /* 3707 * mmu_booke_object_init_pt preloads the ptes for a given object into the 3708 * specified pmap. This eliminates the blast of soft faults on process startup 3709 * and immediately after an mmap. 3710 */ 3711 static void 3712 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 3713 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 3714 { 3715 3716 VM_OBJECT_ASSERT_WLOCKED(object); 3717 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3718 ("mmu_booke_object_init_pt: non-device object")); 3719 } 3720 3721 /* 3722 * Perform the pmap work for mincore. 3723 */ 3724 static int 3725 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 3726 vm_paddr_t *locked_pa) 3727 { 3728 3729 /* XXX: this should be implemented at some point */ 3730 return (0); 3731 } 3732 3733 static int 3734 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 3735 vm_memattr_t mode) 3736 { 3737 vm_offset_t va; 3738 pte_t *pte; 3739 int i, j; 3740 tlb_entry_t e; 3741 3742 /* Check TLB1 mappings */ 3743 for (i = 0; i < TLB1_ENTRIES; i++) { 3744 tlb1_read_entry(&e, i); 3745 if (!(e.mas1 & MAS1_VALID)) 3746 continue; 3747 if (addr >= e.virt && addr < e.virt + e.size) 3748 break; 3749 } 3750 if (i < TLB1_ENTRIES) { 3751 /* Only allow full mappings to be modified for now. */ 3752 /* Validate the range. */ 3753 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 3754 tlb1_read_entry(&e, j); 3755 if (va != e.virt || (sz - (va - addr) < e.size)) 3756 return (EINVAL); 3757 } 3758 for (va = addr; va < addr + sz; va += e.size, i++) { 3759 tlb1_read_entry(&e, i); 3760 e.mas2 &= ~MAS2_WIMGE_MASK; 3761 e.mas2 |= tlb_calc_wimg(e.phys, mode); 3762 3763 /* 3764 * Write it out to the TLB. Should really re-sync with other 3765 * cores. 3766 */ 3767 tlb1_write_entry(&e, i); 3768 } 3769 return (0); 3770 } 3771 3772 /* Not in TLB1, try through pmap */ 3773 /* First validate the range. */ 3774 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 3775 pte = pte_find(mmu, kernel_pmap, va); 3776 if (pte == NULL || !PTE_ISVALID(pte)) 3777 return (EINVAL); 3778 } 3779 3780 mtx_lock_spin(&tlbivax_mutex); 3781 tlb_miss_lock(); 3782 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 3783 pte = pte_find(mmu, kernel_pmap, va); 3784 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 3785 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 3786 tlb0_flush_entry(va); 3787 } 3788 tlb_miss_unlock(); 3789 mtx_unlock_spin(&tlbivax_mutex); 3790 3791 return (0); 3792 } 3793 3794 /**************************************************************************/ 3795 /* TID handling */ 3796 /**************************************************************************/ 3797 3798 /* 3799 * Allocate a TID. If necessary, steal one from someone else. 3800 * The new TID is flushed from the TLB before returning. 3801 */ 3802 static tlbtid_t 3803 tid_alloc(pmap_t pmap) 3804 { 3805 tlbtid_t tid; 3806 int thiscpu; 3807 3808 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 3809 3810 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 3811 3812 thiscpu = PCPU_GET(cpuid); 3813 3814 tid = PCPU_GET(booke.tid_next); 3815 if (tid > TID_MAX) 3816 tid = TID_MIN; 3817 PCPU_SET(booke.tid_next, tid + 1); 3818 3819 /* If we are stealing TID then clear the relevant pmap's field */ 3820 if (tidbusy[thiscpu][tid] != NULL) { 3821 3822 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 3823 3824 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 3825 3826 /* Flush all entries from TLB0 matching this TID. */ 3827 tid_flush(tid); 3828 } 3829 3830 tidbusy[thiscpu][tid] = pmap; 3831 pmap->pm_tid[thiscpu] = tid; 3832 __asm __volatile("msync; isync"); 3833 3834 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3835 PCPU_GET(booke.tid_next)); 3836 3837 return (tid); 3838 } 3839 3840 /**************************************************************************/ 3841 /* TLB0 handling */ 3842 /**************************************************************************/ 3843 3844 /* Convert TLB0 va and way number to tlb0[] table index. */ 3845 static inline unsigned int 3846 tlb0_tableidx(vm_offset_t va, unsigned int way) 3847 { 3848 unsigned int idx; 3849 3850 idx = (way * TLB0_ENTRIES_PER_WAY); 3851 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3852 return (idx); 3853 } 3854 3855 /* 3856 * Invalidate TLB0 entry. 3857 */ 3858 static inline void 3859 tlb0_flush_entry(vm_offset_t va) 3860 { 3861 3862 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3863 3864 mtx_assert(&tlbivax_mutex, MA_OWNED); 3865 3866 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3867 __asm __volatile("isync; msync"); 3868 __asm __volatile("tlbsync; msync"); 3869 3870 CTR1(KTR_PMAP, "%s: e", __func__); 3871 } 3872 3873 3874 /**************************************************************************/ 3875 /* TLB1 handling */ 3876 /**************************************************************************/ 3877 3878 /* 3879 * TLB1 mapping notes: 3880 * 3881 * TLB1[0] Kernel text and data. 3882 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3883 * windows, other devices mappings. 3884 */ 3885 3886 /* 3887 * Read an entry from given TLB1 slot. 3888 */ 3889 void 3890 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 3891 { 3892 register_t msr; 3893 uint32_t mas0; 3894 3895 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 3896 3897 msr = mfmsr(); 3898 __asm __volatile("wrteei 0"); 3899 3900 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 3901 mtspr(SPR_MAS0, mas0); 3902 __asm __volatile("isync; tlbre"); 3903 3904 entry->mas1 = mfspr(SPR_MAS1); 3905 entry->mas2 = mfspr(SPR_MAS2); 3906 entry->mas3 = mfspr(SPR_MAS3); 3907 3908 switch ((mfpvr() >> 16) & 0xFFFF) { 3909 case FSL_E500v2: 3910 case FSL_E500mc: 3911 case FSL_E5500: 3912 case FSL_E6500: 3913 entry->mas7 = mfspr(SPR_MAS7); 3914 break; 3915 default: 3916 entry->mas7 = 0; 3917 break; 3918 } 3919 mtmsr(msr); 3920 3921 entry->virt = entry->mas2 & MAS2_EPN_MASK; 3922 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 3923 (entry->mas3 & MAS3_RPN); 3924 entry->size = 3925 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 3926 } 3927 3928 struct tlbwrite_args { 3929 tlb_entry_t *e; 3930 unsigned int idx; 3931 }; 3932 3933 static void 3934 tlb1_write_entry_int(void *arg) 3935 { 3936 struct tlbwrite_args *args = arg; 3937 uint32_t mas0; 3938 3939 /* Select entry */ 3940 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx); 3941 3942 mtspr(SPR_MAS0, mas0); 3943 mtspr(SPR_MAS1, args->e->mas1); 3944 mtspr(SPR_MAS2, args->e->mas2); 3945 mtspr(SPR_MAS3, args->e->mas3); 3946 switch ((mfpvr() >> 16) & 0xFFFF) { 3947 case FSL_E500mc: 3948 case FSL_E5500: 3949 case FSL_E6500: 3950 mtspr(SPR_MAS8, 0); 3951 /* FALLTHROUGH */ 3952 case FSL_E500v2: 3953 mtspr(SPR_MAS7, args->e->mas7); 3954 break; 3955 default: 3956 break; 3957 } 3958 3959 __asm __volatile("isync; tlbwe; isync; msync"); 3960 3961 } 3962 3963 static void 3964 tlb1_write_entry_sync(void *arg) 3965 { 3966 /* Empty synchronization point for smp_rendezvous(). */ 3967 } 3968 3969 /* 3970 * Write given entry to TLB1 hardware. 3971 */ 3972 static void 3973 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 3974 { 3975 struct tlbwrite_args args; 3976 3977 args.e = e; 3978 args.idx = idx; 3979 3980 #ifdef SMP 3981 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) { 3982 mb(); 3983 smp_rendezvous(tlb1_write_entry_sync, 3984 tlb1_write_entry_int, 3985 tlb1_write_entry_sync, &args); 3986 } else 3987 #endif 3988 { 3989 register_t msr; 3990 3991 msr = mfmsr(); 3992 __asm __volatile("wrteei 0"); 3993 tlb1_write_entry_int(&args); 3994 mtmsr(msr); 3995 } 3996 } 3997 3998 /* 3999 * Return the largest uint value log such that 2^log <= num. 4000 */ 4001 static unsigned int 4002 ilog2(unsigned long num) 4003 { 4004 long lz; 4005 4006 #ifdef __powerpc64__ 4007 __asm ("cntlzd %0, %1" : "=r" (lz) : "r" (num)); 4008 return (63 - lz); 4009 #else 4010 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 4011 return (31 - lz); 4012 #endif 4013 } 4014 4015 /* 4016 * Convert TLB TSIZE value to mapped region size. 4017 */ 4018 static vm_size_t 4019 tsize2size(unsigned int tsize) 4020 { 4021 4022 /* 4023 * size = 4^tsize KB 4024 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 4025 */ 4026 4027 return ((1 << (2 * tsize)) * 1024); 4028 } 4029 4030 /* 4031 * Convert region size (must be power of 4) to TLB TSIZE value. 4032 */ 4033 static unsigned int 4034 size2tsize(vm_size_t size) 4035 { 4036 4037 return (ilog2(size) / 2 - 5); 4038 } 4039 4040 /* 4041 * Register permanent kernel mapping in TLB1. 4042 * 4043 * Entries are created starting from index 0 (current free entry is 4044 * kept in tlb1_idx) and are not supposed to be invalidated. 4045 */ 4046 int 4047 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 4048 uint32_t flags) 4049 { 4050 tlb_entry_t e; 4051 uint32_t ts, tid; 4052 int tsize, index; 4053 4054 for (index = 0; index < TLB1_ENTRIES; index++) { 4055 tlb1_read_entry(&e, index); 4056 if ((e.mas1 & MAS1_VALID) == 0) 4057 break; 4058 /* Check if we're just updating the flags, and update them. */ 4059 if (e.phys == pa && e.virt == va && e.size == size) { 4060 e.mas2 = (va & MAS2_EPN_MASK) | flags; 4061 tlb1_write_entry(&e, index); 4062 return (0); 4063 } 4064 } 4065 if (index >= TLB1_ENTRIES) { 4066 printf("tlb1_set_entry: TLB1 full!\n"); 4067 return (-1); 4068 } 4069 4070 /* Convert size to TSIZE */ 4071 tsize = size2tsize(size); 4072 4073 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 4074 /* XXX TS is hard coded to 0 for now as we only use single address space */ 4075 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 4076 4077 e.phys = pa; 4078 e.virt = va; 4079 e.size = size; 4080 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 4081 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 4082 e.mas2 = (va & MAS2_EPN_MASK) | flags; 4083 4084 /* Set supervisor RWX permission bits */ 4085 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 4086 e.mas7 = (pa >> 32) & MAS7_RPN; 4087 4088 tlb1_write_entry(&e, index); 4089 4090 /* 4091 * XXX in general TLB1 updates should be propagated between CPUs, 4092 * since current design assumes to have the same TLB1 set-up on all 4093 * cores. 4094 */ 4095 return (0); 4096 } 4097 4098 /* 4099 * Map in contiguous RAM region into the TLB1 using maximum of 4100 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 4101 * 4102 * If necessary round up last entry size and return total size 4103 * used by all allocated entries. 4104 */ 4105 vm_size_t 4106 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 4107 { 4108 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 4109 vm_size_t mapped, pgsz, base, mask; 4110 int idx, nents; 4111 4112 /* Round up to the next 1M */ 4113 size = roundup2(size, 1 << 20); 4114 4115 mapped = 0; 4116 idx = 0; 4117 base = va; 4118 pgsz = 64*1024*1024; 4119 while (mapped < size) { 4120 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 4121 while (pgsz > (size - mapped)) 4122 pgsz >>= 2; 4123 pgs[idx++] = pgsz; 4124 mapped += pgsz; 4125 } 4126 4127 /* We under-map. Correct for this. */ 4128 if (mapped < size) { 4129 while (pgs[idx - 1] == pgsz) { 4130 idx--; 4131 mapped -= pgsz; 4132 } 4133 /* XXX We may increase beyond out starting point. */ 4134 pgsz <<= 2; 4135 pgs[idx++] = pgsz; 4136 mapped += pgsz; 4137 } 4138 } 4139 4140 nents = idx; 4141 mask = pgs[0] - 1; 4142 /* Align address to the boundary */ 4143 if (va & mask) { 4144 va = (va + mask) & ~mask; 4145 pa = (pa + mask) & ~mask; 4146 } 4147 4148 for (idx = 0; idx < nents; idx++) { 4149 pgsz = pgs[idx]; 4150 debugf("%u: %llx -> %jx, size=%jx\n", idx, pa, 4151 (uintmax_t)va, (uintmax_t)pgsz); 4152 tlb1_set_entry(va, pa, pgsz, 4153 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM); 4154 pa += pgsz; 4155 va += pgsz; 4156 } 4157 4158 mapped = (va - base); 4159 if (bootverbose) 4160 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n", 4161 mapped, mapped - size); 4162 return (mapped); 4163 } 4164 4165 /* 4166 * TLB1 initialization routine, to be called after the very first 4167 * assembler level setup done in locore.S. 4168 */ 4169 void 4170 tlb1_init() 4171 { 4172 uint32_t mas0, mas1, mas2, mas3, mas7; 4173 uint32_t tsz; 4174 4175 tlb1_get_tlbconf(); 4176 4177 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 4178 mtspr(SPR_MAS0, mas0); 4179 __asm __volatile("isync; tlbre"); 4180 4181 mas1 = mfspr(SPR_MAS1); 4182 mas2 = mfspr(SPR_MAS2); 4183 mas3 = mfspr(SPR_MAS3); 4184 mas7 = mfspr(SPR_MAS7); 4185 4186 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 4187 (mas3 & MAS3_RPN); 4188 4189 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4190 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 4191 4192 /* Setup TLB miss defaults */ 4193 set_mas4_defaults(); 4194 } 4195 4196 /* 4197 * pmap_early_io_unmap() should be used in short conjunction with 4198 * pmap_early_io_map(), as in the following snippet: 4199 * 4200 * x = pmap_early_io_map(...); 4201 * <do something with x> 4202 * pmap_early_io_unmap(x, size); 4203 * 4204 * And avoiding more allocations between. 4205 */ 4206 void 4207 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 4208 { 4209 int i; 4210 tlb_entry_t e; 4211 vm_size_t isize; 4212 4213 size = roundup(size, PAGE_SIZE); 4214 isize = size; 4215 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 4216 tlb1_read_entry(&e, i); 4217 if (!(e.mas1 & MAS1_VALID)) 4218 continue; 4219 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 4220 size -= e.size; 4221 e.mas1 &= ~MAS1_VALID; 4222 tlb1_write_entry(&e, i); 4223 } 4224 } 4225 if (tlb1_map_base == va + isize) 4226 tlb1_map_base -= isize; 4227 } 4228 4229 vm_offset_t 4230 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 4231 { 4232 vm_paddr_t pa_base; 4233 vm_offset_t va, sz; 4234 int i; 4235 tlb_entry_t e; 4236 4237 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 4238 4239 for (i = 0; i < TLB1_ENTRIES; i++) { 4240 tlb1_read_entry(&e, i); 4241 if (!(e.mas1 & MAS1_VALID)) 4242 continue; 4243 if (pa >= e.phys && (pa + size) <= 4244 (e.phys + e.size)) 4245 return (e.virt + (pa - e.phys)); 4246 } 4247 4248 pa_base = rounddown(pa, PAGE_SIZE); 4249 size = roundup(size + (pa - pa_base), PAGE_SIZE); 4250 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 4251 va = tlb1_map_base + (pa - pa_base); 4252 4253 do { 4254 sz = 1 << (ilog2(size) & ~1); 4255 tlb1_set_entry(tlb1_map_base, pa_base, sz, 4256 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 4257 size -= sz; 4258 pa_base += sz; 4259 tlb1_map_base += sz; 4260 } while (size > 0); 4261 4262 return (va); 4263 } 4264 4265 void 4266 pmap_track_page(pmap_t pmap, vm_offset_t va) 4267 { 4268 vm_paddr_t pa; 4269 vm_page_t page; 4270 struct pv_entry *pve; 4271 4272 va = trunc_page(va); 4273 pa = pmap_kextract(va); 4274 page = PHYS_TO_VM_PAGE(pa); 4275 4276 rw_wlock(&pvh_global_lock); 4277 PMAP_LOCK(pmap); 4278 4279 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 4280 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 4281 goto out; 4282 } 4283 } 4284 page->md.pv_tracked = true; 4285 pv_insert(pmap, va, page); 4286 out: 4287 PMAP_UNLOCK(pmap); 4288 rw_wunlock(&pvh_global_lock); 4289 } 4290 4291 4292 /* 4293 * Setup MAS4 defaults. 4294 * These values are loaded to MAS0-2 on a TLB miss. 4295 */ 4296 static void 4297 set_mas4_defaults(void) 4298 { 4299 uint32_t mas4; 4300 4301 /* Defaults: TLB0, PID0, TSIZED=4K */ 4302 mas4 = MAS4_TLBSELD0; 4303 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 4304 #ifdef SMP 4305 mas4 |= MAS4_MD; 4306 #endif 4307 mtspr(SPR_MAS4, mas4); 4308 __asm __volatile("isync"); 4309 } 4310 4311 4312 /* 4313 * Return 0 if the physical IO range is encompassed by one of the 4314 * the TLB1 entries, otherwise return related error code. 4315 */ 4316 static int 4317 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 4318 { 4319 uint32_t prot; 4320 vm_paddr_t pa_start; 4321 vm_paddr_t pa_end; 4322 unsigned int entry_tsize; 4323 vm_size_t entry_size; 4324 tlb_entry_t e; 4325 4326 *va = (vm_offset_t)NULL; 4327 4328 tlb1_read_entry(&e, i); 4329 /* Skip invalid entries */ 4330 if (!(e.mas1 & MAS1_VALID)) 4331 return (EINVAL); 4332 4333 /* 4334 * The entry must be cache-inhibited, guarded, and r/w 4335 * so it can function as an i/o page 4336 */ 4337 prot = e.mas2 & (MAS2_I | MAS2_G); 4338 if (prot != (MAS2_I | MAS2_G)) 4339 return (EPERM); 4340 4341 prot = e.mas3 & (MAS3_SR | MAS3_SW); 4342 if (prot != (MAS3_SR | MAS3_SW)) 4343 return (EPERM); 4344 4345 /* The address should be within the entry range. */ 4346 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4347 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 4348 4349 entry_size = tsize2size(entry_tsize); 4350 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 4351 (e.mas3 & MAS3_RPN); 4352 pa_end = pa_start + entry_size; 4353 4354 if ((pa < pa_start) || ((pa + size) > pa_end)) 4355 return (ERANGE); 4356 4357 /* Return virtual address of this mapping. */ 4358 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 4359 return (0); 4360 } 4361 4362 /* 4363 * Invalidate all TLB0 entries which match the given TID. Note this is 4364 * dedicated for cases when invalidations should NOT be propagated to other 4365 * CPUs. 4366 */ 4367 static void 4368 tid_flush(tlbtid_t tid) 4369 { 4370 register_t msr; 4371 uint32_t mas0, mas1, mas2; 4372 int entry, way; 4373 4374 4375 /* Don't evict kernel translations */ 4376 if (tid == TID_KERNEL) 4377 return; 4378 4379 msr = mfmsr(); 4380 __asm __volatile("wrteei 0"); 4381 4382 /* 4383 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use 4384 * it for PID invalidation. 4385 */ 4386 switch ((mfpvr() >> 16) & 0xffff) { 4387 case FSL_E500mc: 4388 case FSL_E5500: 4389 case FSL_E6500: 4390 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT); 4391 /* tlbilxpid */ 4392 __asm __volatile("isync; .long 0x7c000024; isync; msync"); 4393 mtmsr(msr); 4394 return; 4395 } 4396 4397 for (way = 0; way < TLB0_WAYS; way++) 4398 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 4399 4400 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 4401 mtspr(SPR_MAS0, mas0); 4402 4403 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 4404 mtspr(SPR_MAS2, mas2); 4405 4406 __asm __volatile("isync; tlbre"); 4407 4408 mas1 = mfspr(SPR_MAS1); 4409 4410 if (!(mas1 & MAS1_VALID)) 4411 continue; 4412 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 4413 continue; 4414 mas1 &= ~MAS1_VALID; 4415 mtspr(SPR_MAS1, mas1); 4416 __asm __volatile("isync; tlbwe; isync; msync"); 4417 } 4418 mtmsr(msr); 4419 } 4420 4421 #ifdef DDB 4422 /* Print out contents of the MAS registers for each TLB0 entry */ 4423 static void 4424 #ifdef __powerpc64__ 4425 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3, 4426 #else 4427 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 4428 #endif 4429 uint32_t mas7) 4430 { 4431 int as; 4432 char desc[3]; 4433 tlbtid_t tid; 4434 vm_size_t size; 4435 unsigned int tsize; 4436 4437 desc[2] = '\0'; 4438 if (mas1 & MAS1_VALID) 4439 desc[0] = 'V'; 4440 else 4441 desc[0] = ' '; 4442 4443 if (mas1 & MAS1_IPROT) 4444 desc[1] = 'P'; 4445 else 4446 desc[1] = ' '; 4447 4448 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 4449 tid = MAS1_GETTID(mas1); 4450 4451 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4452 size = 0; 4453 if (tsize) 4454 size = tsize2size(tsize); 4455 4456 printf("%3d: (%s) [AS=%d] " 4457 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 4458 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n", 4459 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 4460 } 4461 4462 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries) 4463 { 4464 uint32_t mas0, mas1, mas3, mas7; 4465 #ifdef __powerpc64__ 4466 uint64_t mas2; 4467 #else 4468 uint32_t mas2; 4469 #endif 4470 int entryidx, way, idx; 4471 4472 printf("TLB0 entries:\n"); 4473 for (way = 0; way < TLB0_WAYS; way ++) 4474 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 4475 4476 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 4477 mtspr(SPR_MAS0, mas0); 4478 4479 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 4480 mtspr(SPR_MAS2, mas2); 4481 4482 __asm __volatile("isync; tlbre"); 4483 4484 mas1 = mfspr(SPR_MAS1); 4485 mas2 = mfspr(SPR_MAS2); 4486 mas3 = mfspr(SPR_MAS3); 4487 mas7 = mfspr(SPR_MAS7); 4488 4489 idx = tlb0_tableidx(mas2, way); 4490 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 4491 } 4492 } 4493 4494 /* 4495 * Print out contents of the MAS registers for each TLB1 entry 4496 */ 4497 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries) 4498 { 4499 uint32_t mas0, mas1, mas3, mas7; 4500 #ifdef __powerpc64__ 4501 uint64_t mas2; 4502 #else 4503 uint32_t mas2; 4504 #endif 4505 int i; 4506 4507 printf("TLB1 entries:\n"); 4508 for (i = 0; i < TLB1_ENTRIES; i++) { 4509 4510 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 4511 mtspr(SPR_MAS0, mas0); 4512 4513 __asm __volatile("isync; tlbre"); 4514 4515 mas1 = mfspr(SPR_MAS1); 4516 mas2 = mfspr(SPR_MAS2); 4517 mas3 = mfspr(SPR_MAS3); 4518 mas7 = mfspr(SPR_MAS7); 4519 4520 tlb_print_entry(i, mas1, mas2, mas3, mas7); 4521 } 4522 } 4523 #endif 4524