1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * 32-bit pmap: 40 * Virtual address space layout: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA 47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 51 * 52 * 64-bit pmap: 53 * Virtual address space layout: 54 * ----------------------------- 55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process 56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries 57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region 58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack 59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved 60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data 61 * endkernel - msgbufp-1 : flat device tree 62 * msgbufp - kernel_pdir-1 : message buffer 63 * kernel_pdir - kernel_pp2d-1 : kernel page directory 64 * kernel_pp2d - . : kernel pointers to page directory 65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy 66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs 67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables 68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space 69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region 70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region 71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map 72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map 73 * - 0xffff_ffff_ffff_ffff : device direct map 74 */ 75 76 #include <sys/cdefs.h> 77 #include "opt_ddb.h" 78 #include "opt_kstack_pages.h" 79 80 #include <sys/param.h> 81 #include <sys/conf.h> 82 #include <sys/malloc.h> 83 #include <sys/ktr.h> 84 #include <sys/proc.h> 85 #include <sys/user.h> 86 #include <sys/queue.h> 87 #include <sys/systm.h> 88 #include <sys/kernel.h> 89 #include <sys/kerneldump.h> 90 #include <sys/linker.h> 91 #include <sys/msgbuf.h> 92 #include <sys/lock.h> 93 #include <sys/mutex.h> 94 #include <sys/rwlock.h> 95 #include <sys/sched.h> 96 #include <sys/smp.h> 97 #include <sys/vmmeter.h> 98 99 #include <vm/vm.h> 100 #include <vm/vm_param.h> 101 #include <vm/vm_page.h> 102 #include <vm/vm_kern.h> 103 #include <vm/vm_pageout.h> 104 #include <vm/vm_extern.h> 105 #include <vm/vm_object.h> 106 #include <vm/vm_map.h> 107 #include <vm/vm_pager.h> 108 #include <vm/vm_phys.h> 109 #include <vm/vm_pagequeue.h> 110 #include <vm/vm_radix.h> 111 #include <vm/vm_dumpset.h> 112 #include <vm/uma.h> 113 114 #include <machine/_inttypes.h> 115 #include <machine/cpu.h> 116 #include <machine/pcb.h> 117 #include <machine/platform.h> 118 119 #include <machine/tlb.h> 120 #include <machine/spr.h> 121 #include <machine/md_var.h> 122 #include <machine/mmuvar.h> 123 #include <machine/pmap.h> 124 #include <machine/pte.h> 125 126 #include <ddb/ddb.h> 127 128 #define SPARSE_MAPDEV 129 130 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */ 131 #define POW2_MAPPINGS 132 133 #ifdef DEBUG 134 #define debugf(fmt, args...) printf(fmt, ##args) 135 #define __debug_used 136 #else 137 #define debugf(fmt, args...) 138 #define __debug_used __unused 139 #endif 140 141 #ifdef __powerpc64__ 142 #define PRI0ptrX "016lx" 143 #else 144 #define PRI0ptrX "08x" 145 #endif 146 147 #define TODO panic("%s: not implemented", __func__); 148 149 extern unsigned char _etext[]; 150 extern unsigned char _end[]; 151 152 extern uint32_t *bootinfo; 153 154 vm_paddr_t kernload; 155 vm_offset_t kernstart; 156 vm_size_t kernsize; 157 158 /* Message buffer and tables. */ 159 static vm_offset_t data_start; 160 static vm_size_t data_end; 161 162 /* Phys/avail memory regions. */ 163 static struct mem_region *availmem_regions; 164 static int availmem_regions_sz; 165 static struct mem_region *physmem_regions; 166 static int physmem_regions_sz; 167 168 #ifndef __powerpc64__ 169 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 170 static vm_offset_t zero_page_va; 171 static struct mtx zero_page_mutex; 172 173 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 174 static vm_offset_t copy_page_src_va; 175 static vm_offset_t copy_page_dst_va; 176 static struct mtx copy_page_mutex; 177 #endif 178 179 static struct mtx tlbivax_mutex; 180 181 /**************************************************************************/ 182 /* PMAP */ 183 /**************************************************************************/ 184 185 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t, 186 vm_prot_t, u_int flags, int8_t psind); 187 188 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 189 static uma_zone_t ptbl_root_zone; 190 191 /* 192 * If user pmap is processed with mmu_booke_remove and the resident count 193 * drops to 0, there are no more pages to remove, so we need not continue. 194 */ 195 #define PMAP_REMOVE_DONE(pmap) \ 196 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 197 198 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 199 extern int elf32_nxstack; 200 #endif 201 202 /**************************************************************************/ 203 /* TLB and TID handling */ 204 /**************************************************************************/ 205 206 /* Translation ID busy table */ 207 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 208 209 /* 210 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 211 * core revisions and should be read from h/w registers during early config. 212 */ 213 uint32_t tlb0_entries; 214 uint32_t tlb0_ways; 215 uint32_t tlb0_entries_per_way; 216 uint32_t tlb1_entries; 217 218 #define TLB0_ENTRIES (tlb0_entries) 219 #define TLB0_WAYS (tlb0_ways) 220 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 221 222 #define TLB1_ENTRIES (tlb1_entries) 223 224 static tlbtid_t tid_alloc(struct pmap *); 225 226 #ifdef DDB 227 #ifdef __powerpc64__ 228 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t); 229 #else 230 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 231 #endif 232 #endif 233 234 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 235 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 236 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 237 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int); 238 239 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma); 240 241 static vm_size_t tsize2size(unsigned int); 242 static unsigned int size2tsize(vm_size_t); 243 244 static void set_mas4_defaults(void); 245 246 static inline void tlb0_flush_entry(vm_offset_t); 247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 248 249 /**************************************************************************/ 250 /* Page table management */ 251 /**************************************************************************/ 252 253 static struct rwlock_padalign pvh_global_lock; 254 255 /* Data for the pv entry allocation mechanism */ 256 static uma_zone_t pvzone; 257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 258 259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 260 261 #ifndef PMAP_SHPGPERPROC 262 #define PMAP_SHPGPERPROC 200 263 #endif 264 265 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t); 266 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, bool); 267 static int pte_remove(pmap_t, vm_offset_t, uint8_t); 268 static pte_t *pte_find(pmap_t, vm_offset_t); 269 static void kernel_pte_alloc(vm_offset_t, vm_offset_t); 270 271 static pv_entry_t pv_alloc(void); 272 static void pv_free(pv_entry_t); 273 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 274 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 275 276 static void booke_pmap_init_qpages(void); 277 278 static inline void tlb_miss_lock(void); 279 static inline void tlb_miss_unlock(void); 280 281 #ifdef SMP 282 extern tlb_entry_t __boot_tlb1[]; 283 void pmap_bootstrap_ap(volatile uint32_t *); 284 #endif 285 286 /* 287 * Kernel MMU interface 288 */ 289 static void mmu_booke_clear_modify(vm_page_t); 290 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, 291 vm_size_t, vm_offset_t); 292 static void mmu_booke_copy_page(vm_page_t, vm_page_t); 293 static void mmu_booke_copy_pages(vm_page_t *, 294 vm_offset_t, vm_page_t *, vm_offset_t, int); 295 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t, 296 vm_prot_t, u_int flags, int8_t psind); 297 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t, 298 vm_page_t, vm_prot_t); 299 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t, 300 vm_prot_t); 301 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t); 302 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t, 303 vm_prot_t); 304 static void mmu_booke_init(void); 305 static bool mmu_booke_is_modified(vm_page_t); 306 static bool mmu_booke_is_prefaultable(pmap_t, vm_offset_t); 307 static bool mmu_booke_is_referenced(vm_page_t); 308 static int mmu_booke_ts_referenced(vm_page_t); 309 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, 310 int); 311 static int mmu_booke_mincore(pmap_t, vm_offset_t, 312 vm_paddr_t *); 313 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t, 314 vm_object_t, vm_pindex_t, vm_size_t); 315 static bool mmu_booke_page_exists_quick(pmap_t, vm_page_t); 316 static void mmu_booke_page_init(vm_page_t); 317 static int mmu_booke_page_wired_mappings(vm_page_t); 318 static int mmu_booke_pinit(pmap_t); 319 static void mmu_booke_pinit0(pmap_t); 320 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t, 321 vm_prot_t); 322 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int); 323 static void mmu_booke_qremove(vm_offset_t, int); 324 static void mmu_booke_release(pmap_t); 325 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t); 326 static void mmu_booke_remove_all(vm_page_t); 327 static void mmu_booke_remove_write(vm_page_t); 328 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t); 329 static void mmu_booke_zero_page(vm_page_t); 330 static void mmu_booke_zero_page_area(vm_page_t, int, int); 331 static void mmu_booke_activate(struct thread *); 332 static void mmu_booke_deactivate(struct thread *); 333 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t); 334 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t); 335 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 336 static void mmu_booke_unmapdev(void *, vm_size_t); 337 static vm_paddr_t mmu_booke_kextract(vm_offset_t); 338 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t); 339 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 340 static void mmu_booke_kremove(vm_offset_t); 341 static int mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t); 342 static void mmu_booke_sync_icache(pmap_t, vm_offset_t, 343 vm_size_t); 344 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t, 345 void **); 346 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t, 347 void *); 348 static void mmu_booke_scan_init(void); 349 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m); 350 static void mmu_booke_quick_remove_page(vm_offset_t addr); 351 static int mmu_booke_change_attr(vm_offset_t addr, 352 vm_size_t sz, vm_memattr_t mode); 353 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr, 354 int *is_user, vm_offset_t *decoded_addr); 355 static void mmu_booke_page_array_startup(long); 356 static bool mmu_booke_page_is_mapped(vm_page_t m); 357 static bool mmu_booke_ps_enabled(pmap_t pmap); 358 359 static struct pmap_funcs mmu_booke_methods = { 360 /* pmap dispatcher interface */ 361 .clear_modify = mmu_booke_clear_modify, 362 .copy = mmu_booke_copy, 363 .copy_page = mmu_booke_copy_page, 364 .copy_pages = mmu_booke_copy_pages, 365 .enter = mmu_booke_enter, 366 .enter_object = mmu_booke_enter_object, 367 .enter_quick = mmu_booke_enter_quick, 368 .extract = mmu_booke_extract, 369 .extract_and_hold = mmu_booke_extract_and_hold, 370 .init = mmu_booke_init, 371 .is_modified = mmu_booke_is_modified, 372 .is_prefaultable = mmu_booke_is_prefaultable, 373 .is_referenced = mmu_booke_is_referenced, 374 .ts_referenced = mmu_booke_ts_referenced, 375 .map = mmu_booke_map, 376 .mincore = mmu_booke_mincore, 377 .object_init_pt = mmu_booke_object_init_pt, 378 .page_exists_quick = mmu_booke_page_exists_quick, 379 .page_init = mmu_booke_page_init, 380 .page_wired_mappings = mmu_booke_page_wired_mappings, 381 .pinit = mmu_booke_pinit, 382 .pinit0 = mmu_booke_pinit0, 383 .protect = mmu_booke_protect, 384 .qenter = mmu_booke_qenter, 385 .qremove = mmu_booke_qremove, 386 .release = mmu_booke_release, 387 .remove = mmu_booke_remove, 388 .remove_all = mmu_booke_remove_all, 389 .remove_write = mmu_booke_remove_write, 390 .sync_icache = mmu_booke_sync_icache, 391 .unwire = mmu_booke_unwire, 392 .zero_page = mmu_booke_zero_page, 393 .zero_page_area = mmu_booke_zero_page_area, 394 .activate = mmu_booke_activate, 395 .deactivate = mmu_booke_deactivate, 396 .quick_enter_page = mmu_booke_quick_enter_page, 397 .quick_remove_page = mmu_booke_quick_remove_page, 398 .page_array_startup = mmu_booke_page_array_startup, 399 .page_is_mapped = mmu_booke_page_is_mapped, 400 .ps_enabled = mmu_booke_ps_enabled, 401 402 /* Internal interfaces */ 403 .bootstrap = mmu_booke_bootstrap, 404 .dev_direct_mapped = mmu_booke_dev_direct_mapped, 405 .mapdev = mmu_booke_mapdev, 406 .mapdev_attr = mmu_booke_mapdev_attr, 407 .kenter = mmu_booke_kenter, 408 .kenter_attr = mmu_booke_kenter_attr, 409 .kextract = mmu_booke_kextract, 410 .kremove = mmu_booke_kremove, 411 .unmapdev = mmu_booke_unmapdev, 412 .change_attr = mmu_booke_change_attr, 413 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr, 414 415 /* dumpsys() support */ 416 .dumpsys_map_chunk = mmu_booke_dumpsys_map, 417 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap, 418 .dumpsys_pa_init = mmu_booke_scan_init, 419 }; 420 421 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods); 422 423 #ifdef __powerpc64__ 424 #include "pmap_64.c" 425 #else 426 #include "pmap_32.c" 427 #endif 428 429 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE; 430 431 static __inline uint32_t 432 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 433 { 434 uint32_t attrib; 435 int i; 436 437 if (ma != VM_MEMATTR_DEFAULT) { 438 switch (ma) { 439 case VM_MEMATTR_UNCACHEABLE: 440 return (MAS2_I | MAS2_G); 441 case VM_MEMATTR_WRITE_COMBINING: 442 case VM_MEMATTR_WRITE_BACK: 443 case VM_MEMATTR_PREFETCHABLE: 444 return (MAS2_I); 445 case VM_MEMATTR_WRITE_THROUGH: 446 return (MAS2_W | MAS2_M); 447 case VM_MEMATTR_CACHEABLE: 448 return (MAS2_M); 449 } 450 } 451 452 /* 453 * Assume the page is cache inhibited and access is guarded unless 454 * it's in our available memory array. 455 */ 456 attrib = _TLB_ENTRY_IO; 457 for (i = 0; i < physmem_regions_sz; i++) { 458 if ((pa >= physmem_regions[i].mr_start) && 459 (pa < (physmem_regions[i].mr_start + 460 physmem_regions[i].mr_size))) { 461 attrib = _TLB_ENTRY_MEM; 462 break; 463 } 464 } 465 466 return (attrib); 467 } 468 469 static inline void 470 tlb_miss_lock(void) 471 { 472 #ifdef SMP 473 struct pcpu *pc; 474 475 if (!smp_started) 476 return; 477 478 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 479 if (pc != pcpup) { 480 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 481 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock); 482 483 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 484 ("tlb_miss_lock: tried to lock self")); 485 486 tlb_lock(pc->pc_booke.tlb_lock); 487 488 CTR1(KTR_PMAP, "%s: locked", __func__); 489 } 490 } 491 #endif 492 } 493 494 static inline void 495 tlb_miss_unlock(void) 496 { 497 #ifdef SMP 498 struct pcpu *pc; 499 500 if (!smp_started) 501 return; 502 503 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 504 if (pc != pcpup) { 505 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 506 __func__, pc->pc_cpuid); 507 508 tlb_unlock(pc->pc_booke.tlb_lock); 509 510 CTR1(KTR_PMAP, "%s: unlocked", __func__); 511 } 512 } 513 #endif 514 } 515 516 /* Return number of entries in TLB0. */ 517 static __inline void 518 tlb0_get_tlbconf(void) 519 { 520 uint32_t tlb0_cfg; 521 522 tlb0_cfg = mfspr(SPR_TLB0CFG); 523 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 524 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 525 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 526 } 527 528 /* Return number of entries in TLB1. */ 529 static __inline void 530 tlb1_get_tlbconf(void) 531 { 532 uint32_t tlb1_cfg; 533 534 tlb1_cfg = mfspr(SPR_TLB1CFG); 535 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 536 } 537 538 /**************************************************************************/ 539 /* Page table related */ 540 /**************************************************************************/ 541 542 /* Allocate pv_entry structure. */ 543 pv_entry_t 544 pv_alloc(void) 545 { 546 pv_entry_t pv; 547 548 pv_entry_count++; 549 if (pv_entry_count > pv_entry_high_water) 550 pagedaemon_wakeup(0); /* XXX powerpc NUMA */ 551 pv = uma_zalloc(pvzone, M_NOWAIT); 552 553 return (pv); 554 } 555 556 /* Free pv_entry structure. */ 557 static __inline void 558 pv_free(pv_entry_t pve) 559 { 560 561 pv_entry_count--; 562 uma_zfree(pvzone, pve); 563 } 564 565 /* Allocate and initialize pv_entry structure. */ 566 static void 567 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 568 { 569 pv_entry_t pve; 570 571 //int su = (pmap == kernel_pmap); 572 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 573 // (u_int32_t)pmap, va, (u_int32_t)m); 574 575 pve = pv_alloc(); 576 if (pve == NULL) 577 panic("pv_insert: no pv entries!"); 578 579 pve->pv_pmap = pmap; 580 pve->pv_va = va; 581 582 /* add to pv_list */ 583 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 584 rw_assert(&pvh_global_lock, RA_WLOCKED); 585 586 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 587 588 //debugf("pv_insert: e\n"); 589 } 590 591 /* Destroy pv entry. */ 592 static void 593 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 594 { 595 pv_entry_t pve; 596 597 //int su = (pmap == kernel_pmap); 598 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 599 600 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 601 rw_assert(&pvh_global_lock, RA_WLOCKED); 602 603 /* find pv entry */ 604 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 605 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 606 /* remove from pv_list */ 607 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 608 if (TAILQ_EMPTY(&m->md.pv_list)) 609 vm_page_aflag_clear(m, PGA_WRITEABLE); 610 611 /* free pv entry struct */ 612 pv_free(pve); 613 break; 614 } 615 } 616 617 //debugf("pv_remove: e\n"); 618 } 619 620 /**************************************************************************/ 621 /* PMAP related */ 622 /**************************************************************************/ 623 624 /* 625 * This is called during booke_init, before the system is really initialized. 626 */ 627 static void 628 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend) 629 { 630 vm_paddr_t phys_kernelend; 631 struct mem_region *mp, *mp1; 632 int cnt, i, j; 633 vm_paddr_t s, e, sz; 634 vm_paddr_t physsz, hwphyssz; 635 u_int phys_avail_count __debug_used; 636 vm_size_t kstack0_sz; 637 vm_paddr_t kstack0_phys; 638 vm_offset_t kstack0; 639 void *dpcpu; 640 641 debugf("mmu_booke_bootstrap: entered\n"); 642 643 /* Set interesting system properties */ 644 #ifdef __powerpc64__ 645 hw_direct_map = 1; 646 #else 647 hw_direct_map = 0; 648 #endif 649 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 650 elf32_nxstack = 1; 651 #endif 652 653 /* Initialize invalidation mutex */ 654 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 655 656 /* Read TLB0 size and associativity. */ 657 tlb0_get_tlbconf(); 658 659 /* 660 * Align kernel start and end address (kernel image). 661 * Note that kernel end does not necessarily relate to kernsize. 662 * kernsize is the size of the kernel that is actually mapped. 663 */ 664 data_start = round_page(kernelend); 665 data_end = data_start; 666 667 /* Allocate the dynamic per-cpu area. */ 668 dpcpu = (void *)data_end; 669 data_end += DPCPU_SIZE; 670 671 /* Allocate space for the message buffer. */ 672 msgbufp = (struct msgbuf *)data_end; 673 data_end += msgbufsize; 674 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 675 (uintptr_t)msgbufp, data_end); 676 677 data_end = round_page(data_end); 678 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end)); 679 680 /* Retrieve phys/avail mem regions */ 681 mem_regions(&physmem_regions, &physmem_regions_sz, 682 &availmem_regions, &availmem_regions_sz); 683 684 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz) 685 panic("mmu_booke_bootstrap: phys_avail too small"); 686 687 data_end = round_page(data_end); 688 vm_page_array = (vm_page_t)data_end; 689 /* 690 * Get a rough idea (upper bound) on the size of the page array. The 691 * vm_page_array will not handle any more pages than we have in the 692 * avail_regions array, and most likely much less. 693 */ 694 sz = 0; 695 for (mp = availmem_regions; mp->mr_size; mp++) { 696 sz += mp->mr_size; 697 } 698 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page))); 699 data_end += round_page(sz * sizeof(struct vm_page)); 700 701 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */ 702 data_end = roundup2(data_end, 1 << 20); 703 704 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end); 705 debugf(" kernstart: %#zx\n", kernstart); 706 debugf(" kernsize: %#zx\n", kernsize); 707 708 if (data_end - kernstart > kernsize) { 709 kernsize += tlb1_mapin_region(kernstart + kernsize, 710 kernload + kernsize, (data_end - kernstart) - kernsize, 711 _TLB_ENTRY_MEM); 712 } 713 data_end = kernstart + kernsize; 714 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end); 715 716 /* 717 * Clear the structures - note we can only do it safely after the 718 * possible additional TLB1 translations are in place (above) so that 719 * all range up to the currently calculated 'data_end' is covered. 720 */ 721 bzero((void *)data_start, data_end - data_start); 722 dpcpu_init(dpcpu, 0); 723 724 /*******************************************************/ 725 /* Set the start and end of kva. */ 726 /*******************************************************/ 727 virtual_avail = round_page(data_end); 728 virtual_end = VM_MAX_KERNEL_ADDRESS; 729 730 #ifndef __powerpc64__ 731 /* Allocate KVA space for page zero/copy operations. */ 732 zero_page_va = virtual_avail; 733 virtual_avail += PAGE_SIZE; 734 copy_page_src_va = virtual_avail; 735 virtual_avail += PAGE_SIZE; 736 copy_page_dst_va = virtual_avail; 737 virtual_avail += PAGE_SIZE; 738 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va); 739 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va); 740 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va); 741 742 /* Initialize page zero/copy mutexes. */ 743 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 744 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 745 746 /* Allocate KVA space for ptbl bufs. */ 747 ptbl_buf_pool_vabase = virtual_avail; 748 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 749 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 750 ptbl_buf_pool_vabase, virtual_avail); 751 #endif 752 #ifdef __powerpc64__ 753 /* Allocate KVA space for crashdumpmap. */ 754 crashdumpmap = (caddr_t)virtual_avail; 755 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 756 #endif 757 758 /* Calculate corresponding physical addresses for the kernel region. */ 759 phys_kernelend = kernload + kernsize; 760 debugf("kernel image and allocated data:\n"); 761 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload); 762 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart); 763 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize); 764 765 /* 766 * Remove kernel physical address range from avail regions list. Page 767 * align all regions. Non-page aligned memory isn't very interesting 768 * to us. Also, sort the entries for ascending addresses. 769 */ 770 771 sz = 0; 772 cnt = availmem_regions_sz; 773 debugf("processing avail regions:\n"); 774 for (mp = availmem_regions; mp->mr_size; mp++) { 775 s = mp->mr_start; 776 e = mp->mr_start + mp->mr_size; 777 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 778 /* Check whether this region holds all of the kernel. */ 779 if (s < kernload && e > phys_kernelend) { 780 availmem_regions[cnt].mr_start = phys_kernelend; 781 availmem_regions[cnt++].mr_size = e - phys_kernelend; 782 e = kernload; 783 } 784 /* Look whether this regions starts within the kernel. */ 785 if (s >= kernload && s < phys_kernelend) { 786 if (e <= phys_kernelend) 787 goto empty; 788 s = phys_kernelend; 789 } 790 /* Now look whether this region ends within the kernel. */ 791 if (e > kernload && e <= phys_kernelend) { 792 if (s >= kernload) 793 goto empty; 794 e = kernload; 795 } 796 /* Now page align the start and size of the region. */ 797 s = round_page(s); 798 e = trunc_page(e); 799 if (e < s) 800 e = s; 801 sz = e - s; 802 debugf("%09jx-%09jx = %jx\n", 803 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 804 805 /* Check whether some memory is left here. */ 806 if (sz == 0) { 807 empty: 808 memmove(mp, mp + 1, 809 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 810 cnt--; 811 mp--; 812 continue; 813 } 814 815 /* Do an insertion sort. */ 816 for (mp1 = availmem_regions; mp1 < mp; mp1++) 817 if (s < mp1->mr_start) 818 break; 819 if (mp1 < mp) { 820 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 821 mp1->mr_start = s; 822 mp1->mr_size = sz; 823 } else { 824 mp->mr_start = s; 825 mp->mr_size = sz; 826 } 827 } 828 availmem_regions_sz = cnt; 829 830 /*******************************************************/ 831 /* Steal physical memory for kernel stack from the end */ 832 /* of the first avail region */ 833 /*******************************************************/ 834 kstack0_sz = kstack_pages * PAGE_SIZE; 835 kstack0_phys = availmem_regions[0].mr_start + 836 availmem_regions[0].mr_size; 837 kstack0_phys -= kstack0_sz; 838 availmem_regions[0].mr_size -= kstack0_sz; 839 840 /*******************************************************/ 841 /* Fill in phys_avail table, based on availmem_regions */ 842 /*******************************************************/ 843 phys_avail_count = 0; 844 physsz = 0; 845 hwphyssz = 0; 846 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 847 848 debugf("fill in phys_avail:\n"); 849 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 850 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 851 (uintmax_t)availmem_regions[i].mr_start, 852 (uintmax_t)availmem_regions[i].mr_start + 853 availmem_regions[i].mr_size, 854 (uintmax_t)availmem_regions[i].mr_size); 855 856 if (hwphyssz != 0 && 857 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 858 debugf(" hw.physmem adjust\n"); 859 if (physsz < hwphyssz) { 860 phys_avail[j] = availmem_regions[i].mr_start; 861 phys_avail[j + 1] = 862 availmem_regions[i].mr_start + 863 hwphyssz - physsz; 864 physsz = hwphyssz; 865 phys_avail_count++; 866 dump_avail[j] = phys_avail[j]; 867 dump_avail[j + 1] = phys_avail[j + 1]; 868 } 869 break; 870 } 871 872 phys_avail[j] = availmem_regions[i].mr_start; 873 phys_avail[j + 1] = availmem_regions[i].mr_start + 874 availmem_regions[i].mr_size; 875 phys_avail_count++; 876 physsz += availmem_regions[i].mr_size; 877 dump_avail[j] = phys_avail[j]; 878 dump_avail[j + 1] = phys_avail[j + 1]; 879 } 880 physmem = btoc(physsz); 881 882 /* Calculate the last available physical address. */ 883 for (i = 0; phys_avail[i + 2] != 0; i += 2) 884 ; 885 Maxmem = powerpc_btop(phys_avail[i + 1]); 886 887 debugf("Maxmem = 0x%08lx\n", Maxmem); 888 debugf("phys_avail_count = %d\n", phys_avail_count); 889 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 890 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 891 892 #ifdef __powerpc64__ 893 /* 894 * Map the physical memory contiguously in TLB1. 895 * Round so it fits into a single mapping. 896 */ 897 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0, 898 phys_avail[i + 1], _TLB_ENTRY_MEM); 899 #endif 900 901 /*******************************************************/ 902 /* Initialize (statically allocated) kernel pmap. */ 903 /*******************************************************/ 904 PMAP_LOCK_INIT(kernel_pmap); 905 906 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap); 907 kernel_pte_alloc(virtual_avail, kernstart); 908 for (i = 0; i < MAXCPU; i++) { 909 kernel_pmap->pm_tid[i] = TID_KERNEL; 910 911 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 912 tidbusy[i][TID_KERNEL] = kernel_pmap; 913 } 914 915 /* Mark kernel_pmap active on all CPUs */ 916 CPU_FILL(&kernel_pmap->pm_active); 917 918 /* 919 * Initialize the global pv list lock. 920 */ 921 rw_init(&pvh_global_lock, "pmap pv global"); 922 923 /*******************************************************/ 924 /* Final setup */ 925 /*******************************************************/ 926 927 /* Enter kstack0 into kernel map, provide guard page */ 928 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 929 thread0.td_kstack = kstack0; 930 thread0.td_kstack_pages = kstack_pages; 931 932 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz); 933 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n", 934 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz); 935 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n", 936 kstack0, kstack0 + kstack0_sz); 937 938 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 939 for (i = 0; i < kstack_pages; i++) { 940 mmu_booke_kenter(kstack0, kstack0_phys); 941 kstack0 += PAGE_SIZE; 942 kstack0_phys += PAGE_SIZE; 943 } 944 945 pmap_bootstrapped = 1; 946 947 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail); 948 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end); 949 950 debugf("mmu_booke_bootstrap: exit\n"); 951 } 952 953 #ifdef SMP 954 void 955 tlb1_ap_prep(void) 956 { 957 tlb_entry_t *e, tmp; 958 unsigned int i; 959 960 /* Prepare TLB1 image for AP processors */ 961 e = __boot_tlb1; 962 for (i = 0; i < TLB1_ENTRIES; i++) { 963 tlb1_read_entry(&tmp, i); 964 965 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 966 memcpy(e++, &tmp, sizeof(tmp)); 967 } 968 } 969 970 void 971 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 972 { 973 int i; 974 975 /* 976 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 977 * have the snapshot of its contents in the s/w __boot_tlb1[] table 978 * created by tlb1_ap_prep(), so use these values directly to 979 * (re)program AP's TLB1 hardware. 980 * 981 * Start at index 1 because index 0 has the kernel map. 982 */ 983 for (i = 1; i < TLB1_ENTRIES; i++) { 984 if (__boot_tlb1[i].mas1 & MAS1_VALID) 985 tlb1_write_entry(&__boot_tlb1[i], i); 986 } 987 988 set_mas4_defaults(); 989 } 990 #endif 991 992 static void 993 booke_pmap_init_qpages(void) 994 { 995 struct pcpu *pc; 996 int i; 997 998 CPU_FOREACH(i) { 999 pc = pcpu_find(i); 1000 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1001 if (pc->pc_qmap_addr == 0) 1002 panic("pmap_init_qpages: unable to allocate KVA"); 1003 } 1004 } 1005 1006 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1007 1008 /* 1009 * Get the physical page address for the given pmap/virtual address. 1010 */ 1011 static vm_paddr_t 1012 mmu_booke_extract(pmap_t pmap, vm_offset_t va) 1013 { 1014 vm_paddr_t pa; 1015 1016 PMAP_LOCK(pmap); 1017 pa = pte_vatopa(pmap, va); 1018 PMAP_UNLOCK(pmap); 1019 1020 return (pa); 1021 } 1022 1023 /* 1024 * Extract the physical page address associated with the given 1025 * kernel virtual address. 1026 */ 1027 static vm_paddr_t 1028 mmu_booke_kextract(vm_offset_t va) 1029 { 1030 tlb_entry_t e; 1031 vm_paddr_t p = 0; 1032 int i; 1033 1034 #ifdef __powerpc64__ 1035 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) 1036 return (DMAP_TO_PHYS(va)); 1037 #endif 1038 1039 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS) 1040 p = pte_vatopa(kernel_pmap, va); 1041 1042 if (p == 0) { 1043 /* Check TLB1 mappings */ 1044 for (i = 0; i < TLB1_ENTRIES; i++) { 1045 tlb1_read_entry(&e, i); 1046 if (!(e.mas1 & MAS1_VALID)) 1047 continue; 1048 if (va >= e.virt && va < e.virt + e.size) 1049 return (e.phys + (va - e.virt)); 1050 } 1051 } 1052 1053 return (p); 1054 } 1055 1056 /* 1057 * Initialize the pmap module. 1058 * 1059 * Called by vm_mem_init(), to initialize any structures that the pmap system 1060 * needs to map virtual memory. 1061 */ 1062 static void 1063 mmu_booke_init(void) 1064 { 1065 int shpgperproc = PMAP_SHPGPERPROC; 1066 1067 /* 1068 * Initialize the address space (zone) for the pv entries. Set a 1069 * high water mark so that the system can recover from excessive 1070 * numbers of pv entries. 1071 */ 1072 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1073 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1074 1075 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1076 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1077 1078 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max); 1079 pv_entry_high_water = 9 * (pv_entry_max / 10); 1080 1081 uma_zone_reserve_kva(pvzone, pv_entry_max); 1082 1083 /* Pre-fill pvzone with initial number of pv entries. */ 1084 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1085 1086 /* Create a UMA zone for page table roots. */ 1087 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE, 1088 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM); 1089 1090 /* Initialize ptbl allocation. */ 1091 ptbl_init(); 1092 } 1093 1094 /* 1095 * Map a list of wired pages into kernel virtual address space. This is 1096 * intended for temporary mappings which do not need page modification or 1097 * references recorded. Existing mappings in the region are overwritten. 1098 */ 1099 static void 1100 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count) 1101 { 1102 vm_offset_t va; 1103 1104 va = sva; 1105 while (count-- > 0) { 1106 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m)); 1107 va += PAGE_SIZE; 1108 m++; 1109 } 1110 } 1111 1112 /* 1113 * Remove page mappings from kernel virtual address space. Intended for 1114 * temporary mappings entered by mmu_booke_qenter. 1115 */ 1116 static void 1117 mmu_booke_qremove(vm_offset_t sva, int count) 1118 { 1119 vm_offset_t va; 1120 1121 va = sva; 1122 while (count-- > 0) { 1123 mmu_booke_kremove(va); 1124 va += PAGE_SIZE; 1125 } 1126 } 1127 1128 /* 1129 * Map a wired page into kernel virtual address space. 1130 */ 1131 static void 1132 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa) 1133 { 1134 1135 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1136 } 1137 1138 static void 1139 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1140 { 1141 uint32_t flags; 1142 pte_t *pte; 1143 1144 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1145 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1146 1147 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1148 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1149 flags |= PTE_PS_4KB; 1150 1151 pte = pte_find(kernel_pmap, va); 1152 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE")); 1153 1154 mtx_lock_spin(&tlbivax_mutex); 1155 tlb_miss_lock(); 1156 1157 if (PTE_ISVALID(pte)) { 1158 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1159 1160 /* Flush entry from TLB0 */ 1161 tlb0_flush_entry(va); 1162 } 1163 1164 *pte = PTE_RPN_FROM_PA(pa) | flags; 1165 1166 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1167 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1168 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1169 1170 /* Flush the real memory from the instruction cache. */ 1171 if ((flags & (PTE_I | PTE_G)) == 0) 1172 __syncicache((void *)va, PAGE_SIZE); 1173 1174 tlb_miss_unlock(); 1175 mtx_unlock_spin(&tlbivax_mutex); 1176 } 1177 1178 /* 1179 * Remove a page from kernel page table. 1180 */ 1181 static void 1182 mmu_booke_kremove(vm_offset_t va) 1183 { 1184 pte_t *pte; 1185 1186 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va); 1187 1188 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1189 (va <= VM_MAX_KERNEL_ADDRESS)), 1190 ("mmu_booke_kremove: invalid va")); 1191 1192 pte = pte_find(kernel_pmap, va); 1193 1194 if (!PTE_ISVALID(pte)) { 1195 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1196 1197 return; 1198 } 1199 1200 mtx_lock_spin(&tlbivax_mutex); 1201 tlb_miss_lock(); 1202 1203 /* Invalidate entry in TLB0, update PTE. */ 1204 tlb0_flush_entry(va); 1205 *pte = 0; 1206 1207 tlb_miss_unlock(); 1208 mtx_unlock_spin(&tlbivax_mutex); 1209 } 1210 1211 /* 1212 * Figure out where a given kernel pointer (usually in a fault) points 1213 * to from the VM's perspective, potentially remapping into userland's 1214 * address space. 1215 */ 1216 static int 1217 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1218 vm_offset_t *decoded_addr) 1219 { 1220 1221 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS) 1222 *is_user = 1; 1223 else 1224 *is_user = 0; 1225 1226 *decoded_addr = addr; 1227 return (0); 1228 } 1229 1230 static bool 1231 mmu_booke_page_is_mapped(vm_page_t m) 1232 { 1233 1234 return (!TAILQ_EMPTY(&(m)->md.pv_list)); 1235 } 1236 1237 static bool 1238 mmu_booke_ps_enabled(pmap_t pmap __unused) 1239 { 1240 return (false); 1241 } 1242 1243 /* 1244 * Initialize pmap associated with process 0. 1245 */ 1246 static void 1247 mmu_booke_pinit0(pmap_t pmap) 1248 { 1249 1250 PMAP_LOCK_INIT(pmap); 1251 mmu_booke_pinit(pmap); 1252 PCPU_SET(curpmap, pmap); 1253 } 1254 1255 /* 1256 * Insert the given physical page at the specified virtual address in the 1257 * target physical map with the protection requested. If specified the page 1258 * will be wired down. 1259 */ 1260 static int 1261 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1262 vm_prot_t prot, u_int flags, int8_t psind) 1263 { 1264 int error; 1265 1266 rw_wlock(&pvh_global_lock); 1267 PMAP_LOCK(pmap); 1268 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind); 1269 PMAP_UNLOCK(pmap); 1270 rw_wunlock(&pvh_global_lock); 1271 return (error); 1272 } 1273 1274 static int 1275 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1276 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1277 { 1278 pte_t *pte; 1279 vm_paddr_t pa; 1280 pte_t flags; 1281 int error, su, sync; 1282 1283 pa = VM_PAGE_TO_PHYS(m); 1284 su = (pmap == kernel_pmap); 1285 sync = 0; 1286 1287 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1288 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1289 // (u_int32_t)pmap, su, pmap->pm_tid, 1290 // (u_int32_t)m, va, pa, prot, flags); 1291 1292 if (su) { 1293 KASSERT(((va >= virtual_avail) && 1294 (va <= VM_MAX_KERNEL_ADDRESS)), 1295 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1296 } else { 1297 KASSERT((va <= VM_MAXUSER_ADDRESS), 1298 ("mmu_booke_enter_locked: user pmap, non user va")); 1299 } 1300 if ((m->oflags & VPO_UNMANAGED) == 0) { 1301 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1302 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1303 else 1304 VM_OBJECT_ASSERT_LOCKED(m->object); 1305 } 1306 1307 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1308 1309 /* 1310 * If there is an existing mapping, and the physical address has not 1311 * changed, must be protection or wiring change. 1312 */ 1313 if (((pte = pte_find(pmap, va)) != NULL) && 1314 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1315 1316 /* 1317 * Before actually updating pte->flags we calculate and 1318 * prepare its new value in a helper var. 1319 */ 1320 flags = *pte; 1321 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1322 1323 /* Wiring change, just update stats. */ 1324 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1325 if (!PTE_ISWIRED(pte)) { 1326 flags |= PTE_WIRED; 1327 pmap->pm_stats.wired_count++; 1328 } 1329 } else { 1330 if (PTE_ISWIRED(pte)) { 1331 flags &= ~PTE_WIRED; 1332 pmap->pm_stats.wired_count--; 1333 } 1334 } 1335 1336 if (prot & VM_PROT_WRITE) { 1337 /* Add write permissions. */ 1338 flags |= PTE_SW; 1339 if (!su) 1340 flags |= PTE_UW; 1341 1342 if ((flags & PTE_MANAGED) != 0) 1343 vm_page_aflag_set(m, PGA_WRITEABLE); 1344 } else { 1345 /* Handle modified pages, sense modify status. */ 1346 1347 /* 1348 * The PTE_MODIFIED flag could be set by underlying 1349 * TLB misses since we last read it (above), possibly 1350 * other CPUs could update it so we check in the PTE 1351 * directly rather than rely on that saved local flags 1352 * copy. 1353 */ 1354 if (PTE_ISMODIFIED(pte)) 1355 vm_page_dirty(m); 1356 } 1357 1358 if (prot & VM_PROT_EXECUTE) { 1359 flags |= PTE_SX; 1360 if (!su) 1361 flags |= PTE_UX; 1362 1363 /* 1364 * Check existing flags for execute permissions: if we 1365 * are turning execute permissions on, icache should 1366 * be flushed. 1367 */ 1368 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1369 sync++; 1370 } 1371 1372 flags &= ~PTE_REFERENCED; 1373 1374 /* 1375 * The new flags value is all calculated -- only now actually 1376 * update the PTE. 1377 */ 1378 mtx_lock_spin(&tlbivax_mutex); 1379 tlb_miss_lock(); 1380 1381 tlb0_flush_entry(va); 1382 *pte &= ~PTE_FLAGS_MASK; 1383 *pte |= flags; 1384 1385 tlb_miss_unlock(); 1386 mtx_unlock_spin(&tlbivax_mutex); 1387 1388 } else { 1389 /* 1390 * If there is an existing mapping, but it's for a different 1391 * physical address, pte_enter() will delete the old mapping. 1392 */ 1393 //if ((pte != NULL) && PTE_ISVALID(pte)) 1394 // debugf("mmu_booke_enter_locked: replace\n"); 1395 //else 1396 // debugf("mmu_booke_enter_locked: new\n"); 1397 1398 /* Now set up the flags and install the new mapping. */ 1399 flags = (PTE_SR | PTE_VALID); 1400 flags |= PTE_M; 1401 1402 if (!su) 1403 flags |= PTE_UR; 1404 1405 if (prot & VM_PROT_WRITE) { 1406 flags |= PTE_SW; 1407 if (!su) 1408 flags |= PTE_UW; 1409 1410 if ((m->oflags & VPO_UNMANAGED) == 0) 1411 vm_page_aflag_set(m, PGA_WRITEABLE); 1412 } 1413 1414 if (prot & VM_PROT_EXECUTE) { 1415 flags |= PTE_SX; 1416 if (!su) 1417 flags |= PTE_UX; 1418 } 1419 1420 /* If its wired update stats. */ 1421 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1422 flags |= PTE_WIRED; 1423 1424 error = pte_enter(pmap, m, va, flags, 1425 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1426 if (error != 0) 1427 return (KERN_RESOURCE_SHORTAGE); 1428 1429 if ((flags & PMAP_ENTER_WIRED) != 0) 1430 pmap->pm_stats.wired_count++; 1431 1432 /* Flush the real memory from the instruction cache. */ 1433 if (prot & VM_PROT_EXECUTE) 1434 sync++; 1435 } 1436 1437 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1438 __syncicache((void *)va, PAGE_SIZE); 1439 sync = 0; 1440 } 1441 1442 return (KERN_SUCCESS); 1443 } 1444 1445 /* 1446 * Maps a sequence of resident pages belonging to the same object. 1447 * The sequence begins with the given page m_start. This page is 1448 * mapped at the given virtual address start. Each subsequent page is 1449 * mapped at a virtual address that is offset from start by the same 1450 * amount as the page is offset from m_start within the object. The 1451 * last page in the sequence is the page with the largest offset from 1452 * m_start that can be mapped at a virtual address less than the given 1453 * virtual address end. Not every virtual page between start and end 1454 * is mapped; only those for which a resident page exists with the 1455 * corresponding offset from m_start are mapped. 1456 */ 1457 static void 1458 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start, 1459 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1460 { 1461 struct pctrie_iter pages; 1462 vm_offset_t va; 1463 vm_page_t m; 1464 1465 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1466 1467 vm_page_iter_limit_init(&pages, m_start->object, 1468 m_start->pindex + atop(end - start)); 1469 m = vm_radix_iter_lookup(&pages, m_start->pindex); 1470 rw_wlock(&pvh_global_lock); 1471 PMAP_LOCK(pmap); 1472 while (m != NULL) { 1473 va = start + ptoa(m->pindex - m_start->pindex); 1474 mmu_booke_enter_locked(pmap, va, m, 1475 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1476 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1477 m = vm_radix_iter_step(&pages); 1478 } 1479 PMAP_UNLOCK(pmap); 1480 rw_wunlock(&pvh_global_lock); 1481 } 1482 1483 static void 1484 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, 1485 vm_prot_t prot) 1486 { 1487 1488 rw_wlock(&pvh_global_lock); 1489 PMAP_LOCK(pmap); 1490 mmu_booke_enter_locked(pmap, va, m, 1491 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1492 PMAP_ENTER_QUICK_LOCKED, 0); 1493 PMAP_UNLOCK(pmap); 1494 rw_wunlock(&pvh_global_lock); 1495 } 1496 1497 /* 1498 * Remove the given range of addresses from the specified map. 1499 * 1500 * It is assumed that the start and end are properly rounded to the page size. 1501 */ 1502 static void 1503 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1504 { 1505 pte_t *pte; 1506 uint8_t hold_flag; 1507 1508 int su = (pmap == kernel_pmap); 1509 1510 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1511 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1512 1513 if (su) { 1514 KASSERT(((va >= virtual_avail) && 1515 (va <= VM_MAX_KERNEL_ADDRESS)), 1516 ("mmu_booke_remove: kernel pmap, non kernel va")); 1517 } else { 1518 KASSERT((va <= VM_MAXUSER_ADDRESS), 1519 ("mmu_booke_remove: user pmap, non user va")); 1520 } 1521 1522 if (PMAP_REMOVE_DONE(pmap)) { 1523 //debugf("mmu_booke_remove: e (empty)\n"); 1524 return; 1525 } 1526 1527 hold_flag = PTBL_HOLD_FLAG(pmap); 1528 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1529 1530 rw_wlock(&pvh_global_lock); 1531 PMAP_LOCK(pmap); 1532 for (; va < endva; va += PAGE_SIZE) { 1533 pte = pte_find_next(pmap, &va); 1534 if ((pte == NULL) || !PTE_ISVALID(pte)) 1535 break; 1536 if (va >= endva) 1537 break; 1538 pte_remove(pmap, va, hold_flag); 1539 } 1540 PMAP_UNLOCK(pmap); 1541 rw_wunlock(&pvh_global_lock); 1542 1543 //debugf("mmu_booke_remove: e\n"); 1544 } 1545 1546 /* 1547 * Remove physical page from all pmaps in which it resides. 1548 */ 1549 static void 1550 mmu_booke_remove_all(vm_page_t m) 1551 { 1552 pv_entry_t pv, pvn; 1553 uint8_t hold_flag; 1554 1555 rw_wlock(&pvh_global_lock); 1556 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) { 1557 PMAP_LOCK(pv->pv_pmap); 1558 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1559 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag); 1560 PMAP_UNLOCK(pv->pv_pmap); 1561 } 1562 vm_page_aflag_clear(m, PGA_WRITEABLE); 1563 rw_wunlock(&pvh_global_lock); 1564 } 1565 1566 /* 1567 * Map a range of physical addresses into kernel virtual address space. 1568 */ 1569 static vm_offset_t 1570 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start, 1571 vm_paddr_t pa_end, int prot) 1572 { 1573 vm_offset_t sva = *virt; 1574 vm_offset_t va = sva; 1575 1576 #ifdef __powerpc64__ 1577 /* XXX: Handle memory not starting at 0x0. */ 1578 if (pa_end < ctob(Maxmem)) 1579 return (PHYS_TO_DMAP(pa_start)); 1580 #endif 1581 1582 while (pa_start < pa_end) { 1583 mmu_booke_kenter(va, pa_start); 1584 va += PAGE_SIZE; 1585 pa_start += PAGE_SIZE; 1586 } 1587 *virt = va; 1588 1589 return (sva); 1590 } 1591 1592 /* 1593 * The pmap must be activated before it's address space can be accessed in any 1594 * way. 1595 */ 1596 static void 1597 mmu_booke_activate(struct thread *td) 1598 { 1599 pmap_t pmap; 1600 u_int cpuid; 1601 1602 pmap = &td->td_proc->p_vmspace->vm_pmap; 1603 1604 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")", 1605 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1606 1607 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1608 1609 sched_pin(); 1610 1611 cpuid = PCPU_GET(cpuid); 1612 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1613 PCPU_SET(curpmap, pmap); 1614 1615 if (pmap->pm_tid[cpuid] == TID_NONE) 1616 tid_alloc(pmap); 1617 1618 /* Load PID0 register with pmap tid value. */ 1619 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1620 __asm __volatile("isync"); 1621 1622 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1623 1624 sched_unpin(); 1625 1626 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1627 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1628 } 1629 1630 /* 1631 * Deactivate the specified process's address space. 1632 */ 1633 static void 1634 mmu_booke_deactivate(struct thread *td) 1635 { 1636 pmap_t pmap; 1637 1638 pmap = &td->td_proc->p_vmspace->vm_pmap; 1639 1640 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX, 1641 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1642 1643 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 1644 1645 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1646 PCPU_SET(curpmap, NULL); 1647 } 1648 1649 /* 1650 * Copy the range specified by src_addr/len 1651 * from the source map to the range dst_addr/len 1652 * in the destination map. 1653 * 1654 * This routine is only advisory and need not do anything. 1655 */ 1656 static void 1657 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, 1658 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1659 { 1660 1661 } 1662 1663 /* 1664 * Set the physical protection on the specified range of this map as requested. 1665 */ 1666 static void 1667 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1668 vm_prot_t prot) 1669 { 1670 vm_offset_t va; 1671 vm_page_t m; 1672 pte_t *pte; 1673 1674 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1675 mmu_booke_remove(pmap, sva, eva); 1676 return; 1677 } 1678 1679 if (prot & VM_PROT_WRITE) 1680 return; 1681 1682 PMAP_LOCK(pmap); 1683 for (va = sva; va < eva; va += PAGE_SIZE) { 1684 if ((pte = pte_find(pmap, va)) != NULL) { 1685 if (PTE_ISVALID(pte)) { 1686 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1687 1688 mtx_lock_spin(&tlbivax_mutex); 1689 tlb_miss_lock(); 1690 1691 /* Handle modified pages. */ 1692 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1693 vm_page_dirty(m); 1694 1695 tlb0_flush_entry(va); 1696 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1697 1698 tlb_miss_unlock(); 1699 mtx_unlock_spin(&tlbivax_mutex); 1700 } 1701 } 1702 } 1703 PMAP_UNLOCK(pmap); 1704 } 1705 1706 /* 1707 * Clear the write and modified bits in each of the given page's mappings. 1708 */ 1709 static void 1710 mmu_booke_remove_write(vm_page_t m) 1711 { 1712 pv_entry_t pv; 1713 pte_t *pte; 1714 1715 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1716 ("mmu_booke_remove_write: page %p is not managed", m)); 1717 vm_page_assert_busied(m); 1718 1719 if (!pmap_page_is_write_mapped(m)) 1720 return; 1721 rw_wlock(&pvh_global_lock); 1722 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1723 PMAP_LOCK(pv->pv_pmap); 1724 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) { 1725 if (PTE_ISVALID(pte)) { 1726 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1727 1728 mtx_lock_spin(&tlbivax_mutex); 1729 tlb_miss_lock(); 1730 1731 /* Handle modified pages. */ 1732 if (PTE_ISMODIFIED(pte)) 1733 vm_page_dirty(m); 1734 1735 /* Flush mapping from TLB0. */ 1736 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1737 1738 tlb_miss_unlock(); 1739 mtx_unlock_spin(&tlbivax_mutex); 1740 } 1741 } 1742 PMAP_UNLOCK(pv->pv_pmap); 1743 } 1744 vm_page_aflag_clear(m, PGA_WRITEABLE); 1745 rw_wunlock(&pvh_global_lock); 1746 } 1747 1748 /* 1749 * Atomically extract and hold the physical page with the given 1750 * pmap and virtual address pair if that mapping permits the given 1751 * protection. 1752 */ 1753 static vm_page_t 1754 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va, 1755 vm_prot_t prot) 1756 { 1757 pte_t *pte; 1758 vm_page_t m; 1759 uint32_t pte_wbit; 1760 1761 m = NULL; 1762 PMAP_LOCK(pmap); 1763 pte = pte_find(pmap, va); 1764 if ((pte != NULL) && PTE_ISVALID(pte)) { 1765 if (pmap == kernel_pmap) 1766 pte_wbit = PTE_SW; 1767 else 1768 pte_wbit = PTE_UW; 1769 1770 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) { 1771 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1772 if (!vm_page_wire_mapped(m)) 1773 m = NULL; 1774 } 1775 } 1776 PMAP_UNLOCK(pmap); 1777 return (m); 1778 } 1779 1780 /* 1781 * Initialize a vm_page's machine-dependent fields. 1782 */ 1783 static void 1784 mmu_booke_page_init(vm_page_t m) 1785 { 1786 1787 m->md.pv_tracked = 0; 1788 TAILQ_INIT(&m->md.pv_list); 1789 } 1790 1791 /* 1792 * Return whether or not the specified physical page was modified 1793 * in any of physical maps. 1794 */ 1795 static bool 1796 mmu_booke_is_modified(vm_page_t m) 1797 { 1798 pte_t *pte; 1799 pv_entry_t pv; 1800 bool rv; 1801 1802 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1803 ("mmu_booke_is_modified: page %p is not managed", m)); 1804 rv = false; 1805 1806 /* 1807 * If the page is not busied then this check is racy. 1808 */ 1809 if (!pmap_page_is_write_mapped(m)) 1810 return (false); 1811 1812 rw_wlock(&pvh_global_lock); 1813 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1814 PMAP_LOCK(pv->pv_pmap); 1815 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1816 PTE_ISVALID(pte)) { 1817 if (PTE_ISMODIFIED(pte)) 1818 rv = true; 1819 } 1820 PMAP_UNLOCK(pv->pv_pmap); 1821 if (rv) 1822 break; 1823 } 1824 rw_wunlock(&pvh_global_lock); 1825 return (rv); 1826 } 1827 1828 /* 1829 * Return whether or not the specified virtual address is eligible 1830 * for prefault. 1831 */ 1832 static bool 1833 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1834 { 1835 1836 return (false); 1837 } 1838 1839 /* 1840 * Return whether or not the specified physical page was referenced 1841 * in any physical maps. 1842 */ 1843 static bool 1844 mmu_booke_is_referenced(vm_page_t m) 1845 { 1846 pte_t *pte; 1847 pv_entry_t pv; 1848 bool rv; 1849 1850 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1851 ("mmu_booke_is_referenced: page %p is not managed", m)); 1852 rv = false; 1853 rw_wlock(&pvh_global_lock); 1854 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1855 PMAP_LOCK(pv->pv_pmap); 1856 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1857 PTE_ISVALID(pte)) { 1858 if (PTE_ISREFERENCED(pte)) 1859 rv = true; 1860 } 1861 PMAP_UNLOCK(pv->pv_pmap); 1862 if (rv) 1863 break; 1864 } 1865 rw_wunlock(&pvh_global_lock); 1866 return (rv); 1867 } 1868 1869 /* 1870 * Clear the modify bits on the specified physical page. 1871 */ 1872 static void 1873 mmu_booke_clear_modify(vm_page_t m) 1874 { 1875 pte_t *pte; 1876 pv_entry_t pv; 1877 1878 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1879 ("mmu_booke_clear_modify: page %p is not managed", m)); 1880 vm_page_assert_busied(m); 1881 1882 if (!pmap_page_is_write_mapped(m)) 1883 return; 1884 1885 rw_wlock(&pvh_global_lock); 1886 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1887 PMAP_LOCK(pv->pv_pmap); 1888 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1889 PTE_ISVALID(pte)) { 1890 mtx_lock_spin(&tlbivax_mutex); 1891 tlb_miss_lock(); 1892 1893 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 1894 tlb0_flush_entry(pv->pv_va); 1895 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 1896 PTE_REFERENCED); 1897 } 1898 1899 tlb_miss_unlock(); 1900 mtx_unlock_spin(&tlbivax_mutex); 1901 } 1902 PMAP_UNLOCK(pv->pv_pmap); 1903 } 1904 rw_wunlock(&pvh_global_lock); 1905 } 1906 1907 /* 1908 * Return a count of reference bits for a page, clearing those bits. 1909 * It is not necessary for every reference bit to be cleared, but it 1910 * is necessary that 0 only be returned when there are truly no 1911 * reference bits set. 1912 * 1913 * As an optimization, update the page's dirty field if a modified bit is 1914 * found while counting reference bits. This opportunistic update can be 1915 * performed at low cost and can eliminate the need for some future calls 1916 * to pmap_is_modified(). However, since this function stops after 1917 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 1918 * dirty pages. Those dirty pages will only be detected by a future call 1919 * to pmap_is_modified(). 1920 */ 1921 static int 1922 mmu_booke_ts_referenced(vm_page_t m) 1923 { 1924 pte_t *pte; 1925 pv_entry_t pv; 1926 int count; 1927 1928 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1929 ("mmu_booke_ts_referenced: page %p is not managed", m)); 1930 count = 0; 1931 rw_wlock(&pvh_global_lock); 1932 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1933 PMAP_LOCK(pv->pv_pmap); 1934 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL && 1935 PTE_ISVALID(pte)) { 1936 if (PTE_ISMODIFIED(pte)) 1937 vm_page_dirty(m); 1938 if (PTE_ISREFERENCED(pte)) { 1939 mtx_lock_spin(&tlbivax_mutex); 1940 tlb_miss_lock(); 1941 1942 tlb0_flush_entry(pv->pv_va); 1943 *pte &= ~PTE_REFERENCED; 1944 1945 tlb_miss_unlock(); 1946 mtx_unlock_spin(&tlbivax_mutex); 1947 1948 if (++count >= PMAP_TS_REFERENCED_MAX) { 1949 PMAP_UNLOCK(pv->pv_pmap); 1950 break; 1951 } 1952 } 1953 } 1954 PMAP_UNLOCK(pv->pv_pmap); 1955 } 1956 rw_wunlock(&pvh_global_lock); 1957 return (count); 1958 } 1959 1960 /* 1961 * Clear the wired attribute from the mappings for the specified range of 1962 * addresses in the given pmap. Every valid mapping within that range must 1963 * have the wired attribute set. In contrast, invalid mappings cannot have 1964 * the wired attribute set, so they are ignored. 1965 * 1966 * The wired attribute of the page table entry is not a hardware feature, so 1967 * there is no need to invalidate any TLB entries. 1968 */ 1969 static void 1970 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1971 { 1972 vm_offset_t va; 1973 pte_t *pte; 1974 1975 PMAP_LOCK(pmap); 1976 for (va = sva; va < eva; va += PAGE_SIZE) { 1977 if ((pte = pte_find(pmap, va)) != NULL && 1978 PTE_ISVALID(pte)) { 1979 if (!PTE_ISWIRED(pte)) 1980 panic("mmu_booke_unwire: pte %p isn't wired", 1981 pte); 1982 *pte &= ~PTE_WIRED; 1983 pmap->pm_stats.wired_count--; 1984 } 1985 } 1986 PMAP_UNLOCK(pmap); 1987 1988 } 1989 1990 /* 1991 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 1992 * page. This count may be changed upwards or downwards in the future; it is 1993 * only necessary that true be returned for a small subset of pmaps for proper 1994 * page aging. 1995 */ 1996 static bool 1997 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m) 1998 { 1999 pv_entry_t pv; 2000 int loops; 2001 bool rv; 2002 2003 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2004 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2005 loops = 0; 2006 rv = false; 2007 rw_wlock(&pvh_global_lock); 2008 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2009 if (pv->pv_pmap == pmap) { 2010 rv = true; 2011 break; 2012 } 2013 if (++loops >= 16) 2014 break; 2015 } 2016 rw_wunlock(&pvh_global_lock); 2017 return (rv); 2018 } 2019 2020 /* 2021 * Return the number of managed mappings to the given physical page that are 2022 * wired. 2023 */ 2024 static int 2025 mmu_booke_page_wired_mappings(vm_page_t m) 2026 { 2027 pv_entry_t pv; 2028 pte_t *pte; 2029 int count = 0; 2030 2031 if ((m->oflags & VPO_UNMANAGED) != 0) 2032 return (count); 2033 rw_wlock(&pvh_global_lock); 2034 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2035 PMAP_LOCK(pv->pv_pmap); 2036 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) 2037 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2038 count++; 2039 PMAP_UNLOCK(pv->pv_pmap); 2040 } 2041 rw_wunlock(&pvh_global_lock); 2042 return (count); 2043 } 2044 2045 static int 2046 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2047 { 2048 int i; 2049 vm_offset_t va; 2050 2051 /* 2052 * This currently does not work for entries that 2053 * overlap TLB1 entries. 2054 */ 2055 for (i = 0; i < TLB1_ENTRIES; i ++) { 2056 if (tlb1_iomapped(i, pa, size, &va) == 0) 2057 return (0); 2058 } 2059 2060 return (EFAULT); 2061 } 2062 2063 void 2064 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2065 { 2066 vm_paddr_t ppa; 2067 vm_offset_t ofs; 2068 vm_size_t gran; 2069 2070 /* Minidumps are based on virtual memory addresses. */ 2071 if (do_minidump) { 2072 *va = (void *)(vm_offset_t)pa; 2073 return; 2074 } 2075 2076 /* Raw physical memory dumps don't have a virtual address. */ 2077 /* We always map a 256MB page at 256M. */ 2078 gran = 256 * 1024 * 1024; 2079 ppa = rounddown2(pa, gran); 2080 ofs = pa - ppa; 2081 *va = (void *)gran; 2082 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2083 2084 if (sz > (gran - ofs)) 2085 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2086 _TLB_ENTRY_IO); 2087 } 2088 2089 void 2090 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va) 2091 { 2092 vm_paddr_t ppa; 2093 vm_offset_t ofs; 2094 vm_size_t gran; 2095 tlb_entry_t e; 2096 int i; 2097 2098 /* Minidumps are based on virtual memory addresses. */ 2099 /* Nothing to do... */ 2100 if (do_minidump) 2101 return; 2102 2103 for (i = 0; i < TLB1_ENTRIES; i++) { 2104 tlb1_read_entry(&e, i); 2105 if (!(e.mas1 & MAS1_VALID)) 2106 break; 2107 } 2108 2109 /* Raw physical memory dumps don't have a virtual address. */ 2110 i--; 2111 e.mas1 = 0; 2112 e.mas2 = 0; 2113 e.mas3 = 0; 2114 tlb1_write_entry(&e, i); 2115 2116 gran = 256 * 1024 * 1024; 2117 ppa = rounddown2(pa, gran); 2118 ofs = pa - ppa; 2119 if (sz > (gran - ofs)) { 2120 i--; 2121 e.mas1 = 0; 2122 e.mas2 = 0; 2123 e.mas3 = 0; 2124 tlb1_write_entry(&e, i); 2125 } 2126 } 2127 2128 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2129 2130 void 2131 mmu_booke_scan_init(void) 2132 { 2133 vm_offset_t va; 2134 pte_t *pte; 2135 int i; 2136 2137 if (!do_minidump) { 2138 /* Initialize phys. segments for dumpsys(). */ 2139 memset(&dump_map, 0, sizeof(dump_map)); 2140 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2141 &availmem_regions_sz); 2142 for (i = 0; i < physmem_regions_sz; i++) { 2143 dump_map[i].pa_start = physmem_regions[i].mr_start; 2144 dump_map[i].pa_size = physmem_regions[i].mr_size; 2145 } 2146 return; 2147 } 2148 2149 /* Virtual segments for minidumps: */ 2150 memset(&dump_map, 0, sizeof(dump_map)); 2151 2152 /* 1st: kernel .data and .bss. */ 2153 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2154 dump_map[0].pa_size = 2155 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2156 2157 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2158 dump_map[1].pa_start = data_start; 2159 dump_map[1].pa_size = data_end - data_start; 2160 2161 /* 3rd: kernel VM. */ 2162 va = dump_map[1].pa_start + dump_map[1].pa_size; 2163 /* Find start of next chunk (from va). */ 2164 while (va < virtual_end) { 2165 /* Don't dump the buffer cache. */ 2166 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2167 va = kmi.buffer_eva; 2168 continue; 2169 } 2170 pte = pte_find(kernel_pmap, va); 2171 if (pte != NULL && PTE_ISVALID(pte)) 2172 break; 2173 va += PAGE_SIZE; 2174 } 2175 if (va < virtual_end) { 2176 dump_map[2].pa_start = va; 2177 va += PAGE_SIZE; 2178 /* Find last page in chunk. */ 2179 while (va < virtual_end) { 2180 /* Don't run into the buffer cache. */ 2181 if (va == kmi.buffer_sva) 2182 break; 2183 pte = pte_find(kernel_pmap, va); 2184 if (pte == NULL || !PTE_ISVALID(pte)) 2185 break; 2186 va += PAGE_SIZE; 2187 } 2188 dump_map[2].pa_size = va - dump_map[2].pa_start; 2189 } 2190 } 2191 2192 /* 2193 * Map a set of physical memory pages into the kernel virtual address space. 2194 * Return a pointer to where it is mapped. This routine is intended to be used 2195 * for mapping device memory, NOT real memory. 2196 */ 2197 static void * 2198 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size) 2199 { 2200 2201 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2202 } 2203 2204 static int 2205 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e) 2206 { 2207 int i; 2208 2209 for (i = 0; i < TLB1_ENTRIES; i++) { 2210 tlb1_read_entry(e, i); 2211 if ((e->mas1 & MAS1_VALID) == 0) 2212 continue; 2213 if (e->phys == pa) 2214 return (i); 2215 } 2216 return (-1); 2217 } 2218 2219 static void * 2220 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2221 { 2222 tlb_entry_t e; 2223 vm_paddr_t tmppa; 2224 #ifndef __powerpc64__ 2225 uintptr_t tmpva; 2226 #endif 2227 uintptr_t va, retva; 2228 vm_size_t sz; 2229 int i; 2230 int wimge; 2231 2232 /* 2233 * Check if this is premapped in TLB1. 2234 */ 2235 sz = size; 2236 tmppa = pa; 2237 va = ~0; 2238 wimge = tlb_calc_wimg(pa, ma); 2239 for (i = 0; i < TLB1_ENTRIES; i++) { 2240 tlb1_read_entry(&e, i); 2241 if (!(e.mas1 & MAS1_VALID)) 2242 continue; 2243 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))) 2244 continue; 2245 if (tmppa >= e.phys && tmppa < e.phys + e.size) { 2246 va = e.virt + (pa - e.phys); 2247 tmppa = e.phys + e.size; 2248 sz -= MIN(sz, e.size - (pa - e.phys)); 2249 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) { 2250 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))) 2251 break; 2252 sz -= MIN(sz, e.size); 2253 tmppa = e.phys + e.size; 2254 } 2255 if (sz != 0) 2256 break; 2257 return ((void *)va); 2258 } 2259 } 2260 2261 size = roundup(size, PAGE_SIZE); 2262 2263 #ifdef __powerpc64__ 2264 KASSERT(pa < VM_MAPDEV_PA_MAX, 2265 ("Unsupported physical address! %lx", pa)); 2266 va = VM_MAPDEV_BASE + pa; 2267 retva = va; 2268 #ifdef POW2_MAPPINGS 2269 /* 2270 * Align the mapping to a power of 2 size, taking into account that we 2271 * may need to increase the size multiple times to satisfy the size and 2272 * alignment requirements. 2273 * 2274 * This works in the general case because it's very rare (near never?) 2275 * to have different access properties (WIMG) within a single 2276 * power-of-two region. If a design does call for that, POW2_MAPPINGS 2277 * can be undefined, and exact mappings will be used instead. 2278 */ 2279 sz = size; 2280 size = roundup2(size, 1 << ilog2(size)); 2281 while (rounddown2(va, size) + size < va + sz) 2282 size <<= 1; 2283 va = rounddown2(va, size); 2284 pa = rounddown2(pa, size); 2285 #endif 2286 #else 2287 /* 2288 * The device mapping area is between VM_MAXUSER_ADDRESS and 2289 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 2290 */ 2291 #ifdef SPARSE_MAPDEV 2292 /* 2293 * With a sparse mapdev, align to the largest starting region. This 2294 * could feasibly be optimized for a 'best-fit' alignment, but that 2295 * calculation could be very costly. 2296 * Align to the smaller of: 2297 * - first set bit in overlap of (pa & size mask) 2298 * - largest size envelope 2299 * 2300 * It's possible the device mapping may start at a PA that's not larger 2301 * than the size mask, so we need to offset in to maximize the TLB entry 2302 * range and minimize the number of used TLB entries. 2303 */ 2304 do { 2305 tmpva = tlb1_map_base; 2306 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa); 2307 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1; 2308 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa); 2309 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 2310 #endif 2311 va = atomic_fetchadd_int(&tlb1_map_base, size); 2312 retva = va; 2313 #endif 2314 2315 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size) 2316 return (NULL); 2317 2318 return ((void *)retva); 2319 } 2320 2321 /* 2322 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2323 */ 2324 static void 2325 mmu_booke_unmapdev(void *p, vm_size_t size) 2326 { 2327 #ifdef SUPPORTS_SHRINKING_TLB1 2328 vm_offset_t base, offset, va; 2329 2330 /* 2331 * Unmap only if this is inside kernel virtual space. 2332 */ 2333 va = (vm_offset_t)p; 2334 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2335 base = trunc_page(va); 2336 offset = va & PAGE_MASK; 2337 size = roundup(offset + size, PAGE_SIZE); 2338 mmu_booke_qremove(base, atop(size)); 2339 kva_free(base, size); 2340 } 2341 #endif 2342 } 2343 2344 /* 2345 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2346 * specified pmap. This eliminates the blast of soft faults on process startup 2347 * and immediately after an mmap. 2348 */ 2349 static void 2350 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr, 2351 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2352 { 2353 2354 VM_OBJECT_ASSERT_WLOCKED(object); 2355 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2356 ("mmu_booke_object_init_pt: non-device object")); 2357 } 2358 2359 /* 2360 * Perform the pmap work for mincore. 2361 */ 2362 static int 2363 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 2364 { 2365 2366 /* XXX: this should be implemented at some point */ 2367 return (0); 2368 } 2369 2370 static int 2371 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode) 2372 { 2373 vm_offset_t va; 2374 pte_t *pte; 2375 int i, j; 2376 tlb_entry_t e; 2377 2378 addr = trunc_page(addr); 2379 2380 /* Only allow changes to mapped kernel addresses. This includes: 2381 * - KVA 2382 * - DMAP (powerpc64) 2383 * - Device mappings 2384 */ 2385 if (addr <= VM_MAXUSER_ADDRESS || 2386 #ifdef __powerpc64__ 2387 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) || 2388 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) || 2389 #else 2390 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) || 2391 #endif 2392 (addr > VM_MAX_KERNEL_ADDRESS)) 2393 return (EINVAL); 2394 2395 /* Check TLB1 mappings */ 2396 for (i = 0; i < TLB1_ENTRIES; i++) { 2397 tlb1_read_entry(&e, i); 2398 if (!(e.mas1 & MAS1_VALID)) 2399 continue; 2400 if (addr >= e.virt && addr < e.virt + e.size) 2401 break; 2402 } 2403 if (i < TLB1_ENTRIES) { 2404 /* Only allow full mappings to be modified for now. */ 2405 /* Validate the range. */ 2406 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 2407 tlb1_read_entry(&e, j); 2408 if (va != e.virt || (sz - (va - addr) < e.size)) 2409 return (EINVAL); 2410 } 2411 for (va = addr; va < addr + sz; va += e.size, i++) { 2412 tlb1_read_entry(&e, i); 2413 e.mas2 &= ~MAS2_WIMGE_MASK; 2414 e.mas2 |= tlb_calc_wimg(e.phys, mode); 2415 2416 /* 2417 * Write it out to the TLB. Should really re-sync with other 2418 * cores. 2419 */ 2420 tlb1_write_entry(&e, i); 2421 } 2422 return (0); 2423 } 2424 2425 /* Not in TLB1, try through pmap */ 2426 /* First validate the range. */ 2427 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2428 pte = pte_find(kernel_pmap, va); 2429 if (pte == NULL || !PTE_ISVALID(pte)) 2430 return (EINVAL); 2431 } 2432 2433 mtx_lock_spin(&tlbivax_mutex); 2434 tlb_miss_lock(); 2435 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2436 pte = pte_find(kernel_pmap, va); 2437 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2438 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 2439 tlb0_flush_entry(va); 2440 } 2441 tlb_miss_unlock(); 2442 mtx_unlock_spin(&tlbivax_mutex); 2443 2444 return (0); 2445 } 2446 2447 static void 2448 mmu_booke_page_array_startup(long pages) 2449 { 2450 vm_page_array_size = pages; 2451 } 2452 2453 /**************************************************************************/ 2454 /* TID handling */ 2455 /**************************************************************************/ 2456 2457 /* 2458 * Allocate a TID. If necessary, steal one from someone else. 2459 * The new TID is flushed from the TLB before returning. 2460 */ 2461 static tlbtid_t 2462 tid_alloc(pmap_t pmap) 2463 { 2464 tlbtid_t tid; 2465 int thiscpu; 2466 2467 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2468 2469 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2470 2471 thiscpu = PCPU_GET(cpuid); 2472 2473 tid = PCPU_GET(booke.tid_next); 2474 if (tid > TID_MAX) 2475 tid = TID_MIN; 2476 PCPU_SET(booke.tid_next, tid + 1); 2477 2478 /* If we are stealing TID then clear the relevant pmap's field */ 2479 if (tidbusy[thiscpu][tid] != NULL) { 2480 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2481 2482 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2483 2484 /* Flush all entries from TLB0 matching this TID. */ 2485 tid_flush(tid); 2486 } 2487 2488 tidbusy[thiscpu][tid] = pmap; 2489 pmap->pm_tid[thiscpu] = tid; 2490 __asm __volatile("msync; isync"); 2491 2492 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2493 PCPU_GET(booke.tid_next)); 2494 2495 return (tid); 2496 } 2497 2498 /**************************************************************************/ 2499 /* TLB0 handling */ 2500 /**************************************************************************/ 2501 2502 /* Convert TLB0 va and way number to tlb0[] table index. */ 2503 static inline unsigned int 2504 tlb0_tableidx(vm_offset_t va, unsigned int way) 2505 { 2506 unsigned int idx; 2507 2508 idx = (way * TLB0_ENTRIES_PER_WAY); 2509 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2510 return (idx); 2511 } 2512 2513 /* 2514 * Invalidate TLB0 entry. 2515 */ 2516 static inline void 2517 tlb0_flush_entry(vm_offset_t va) 2518 { 2519 2520 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2521 2522 mtx_assert(&tlbivax_mutex, MA_OWNED); 2523 2524 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2525 __asm __volatile("isync; msync"); 2526 __asm __volatile("tlbsync; msync"); 2527 2528 CTR1(KTR_PMAP, "%s: e", __func__); 2529 } 2530 2531 /**************************************************************************/ 2532 /* TLB1 handling */ 2533 /**************************************************************************/ 2534 2535 /* 2536 * TLB1 mapping notes: 2537 * 2538 * TLB1[0] Kernel text and data. 2539 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2540 * windows, other devices mappings. 2541 */ 2542 2543 /* 2544 * Read an entry from given TLB1 slot. 2545 */ 2546 void 2547 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 2548 { 2549 register_t msr; 2550 uint32_t mas0; 2551 2552 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 2553 2554 msr = mfmsr(); 2555 __asm __volatile("wrteei 0"); 2556 2557 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 2558 mtspr(SPR_MAS0, mas0); 2559 __asm __volatile("isync; tlbre"); 2560 2561 entry->mas1 = mfspr(SPR_MAS1); 2562 entry->mas2 = mfspr(SPR_MAS2); 2563 entry->mas3 = mfspr(SPR_MAS3); 2564 2565 switch ((mfpvr() >> 16) & 0xFFFF) { 2566 case FSL_E500v2: 2567 case FSL_E500mc: 2568 case FSL_E5500: 2569 case FSL_E6500: 2570 entry->mas7 = mfspr(SPR_MAS7); 2571 break; 2572 default: 2573 entry->mas7 = 0; 2574 break; 2575 } 2576 __asm __volatile("wrtee %0" :: "r"(msr)); 2577 2578 entry->virt = entry->mas2 & MAS2_EPN_MASK; 2579 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 2580 (entry->mas3 & MAS3_RPN); 2581 entry->size = 2582 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 2583 } 2584 2585 struct tlbwrite_args { 2586 tlb_entry_t *e; 2587 unsigned int idx; 2588 }; 2589 2590 static uint32_t 2591 tlb1_find_free(void) 2592 { 2593 tlb_entry_t e; 2594 int i; 2595 2596 for (i = 0; i < TLB1_ENTRIES; i++) { 2597 tlb1_read_entry(&e, i); 2598 if ((e.mas1 & MAS1_VALID) == 0) 2599 return (i); 2600 } 2601 return (-1); 2602 } 2603 2604 static void 2605 tlb1_purge_va_range(vm_offset_t va, vm_size_t size) 2606 { 2607 tlb_entry_t e; 2608 int i; 2609 2610 for (i = 0; i < TLB1_ENTRIES; i++) { 2611 tlb1_read_entry(&e, i); 2612 if ((e.mas1 & MAS1_VALID) == 0) 2613 continue; 2614 if ((e.mas2 & MAS2_EPN_MASK) >= va && 2615 (e.mas2 & MAS2_EPN_MASK) < va + size) { 2616 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID); 2617 __asm __volatile("isync; tlbwe; isync; msync"); 2618 } 2619 } 2620 } 2621 2622 static void 2623 tlb1_write_entry_int(void *arg) 2624 { 2625 struct tlbwrite_args *args = arg; 2626 uint32_t idx, mas0; 2627 2628 idx = args->idx; 2629 if (idx == -1) { 2630 tlb1_purge_va_range(args->e->virt, args->e->size); 2631 idx = tlb1_find_free(); 2632 if (idx == -1) 2633 panic("No free TLB1 entries!\n"); 2634 } 2635 /* Select entry */ 2636 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2637 2638 mtspr(SPR_MAS0, mas0); 2639 mtspr(SPR_MAS1, args->e->mas1); 2640 mtspr(SPR_MAS2, args->e->mas2); 2641 mtspr(SPR_MAS3, args->e->mas3); 2642 switch ((mfpvr() >> 16) & 0xFFFF) { 2643 case FSL_E500mc: 2644 case FSL_E5500: 2645 case FSL_E6500: 2646 mtspr(SPR_MAS8, 0); 2647 /* FALLTHROUGH */ 2648 case FSL_E500v2: 2649 mtspr(SPR_MAS7, args->e->mas7); 2650 break; 2651 default: 2652 break; 2653 } 2654 2655 __asm __volatile("isync; tlbwe; isync; msync"); 2656 2657 } 2658 2659 static void 2660 tlb1_write_entry_sync(void *arg) 2661 { 2662 /* Empty synchronization point for smp_rendezvous(). */ 2663 } 2664 2665 /* 2666 * Write given entry to TLB1 hardware. 2667 */ 2668 static void 2669 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 2670 { 2671 struct tlbwrite_args args; 2672 2673 args.e = e; 2674 args.idx = idx; 2675 2676 #ifdef SMP 2677 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) { 2678 mb(); 2679 smp_rendezvous(tlb1_write_entry_sync, 2680 tlb1_write_entry_int, 2681 tlb1_write_entry_sync, &args); 2682 } else 2683 #endif 2684 { 2685 register_t msr; 2686 2687 msr = mfmsr(); 2688 __asm __volatile("wrteei 0"); 2689 tlb1_write_entry_int(&args); 2690 __asm __volatile("wrtee %0" :: "r"(msr)); 2691 } 2692 } 2693 2694 /* 2695 * Convert TLB TSIZE value to mapped region size. 2696 */ 2697 static vm_size_t 2698 tsize2size(unsigned int tsize) 2699 { 2700 2701 /* 2702 * size = 4^tsize KB 2703 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2704 */ 2705 2706 return ((1 << (2 * tsize)) * 1024); 2707 } 2708 2709 /* 2710 * Convert region size (must be power of 4) to TLB TSIZE value. 2711 */ 2712 static unsigned int 2713 size2tsize(vm_size_t size) 2714 { 2715 2716 return (ilog2(size) / 2 - 5); 2717 } 2718 2719 /* 2720 * Register permanent kernel mapping in TLB1. 2721 * 2722 * Entries are created starting from index 0 (current free entry is 2723 * kept in tlb1_idx) and are not supposed to be invalidated. 2724 */ 2725 int 2726 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 2727 uint32_t flags) 2728 { 2729 tlb_entry_t e; 2730 uint32_t ts, tid; 2731 int tsize, index; 2732 2733 /* First try to update an existing entry. */ 2734 for (index = 0; index < TLB1_ENTRIES; index++) { 2735 tlb1_read_entry(&e, index); 2736 /* Check if we're just updating the flags, and update them. */ 2737 if (e.phys == pa && e.virt == va && e.size == size) { 2738 e.mas2 = (va & MAS2_EPN_MASK) | flags; 2739 tlb1_write_entry(&e, index); 2740 return (0); 2741 } 2742 } 2743 2744 /* Convert size to TSIZE */ 2745 tsize = size2tsize(size); 2746 2747 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2748 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2749 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2750 2751 e.phys = pa; 2752 e.virt = va; 2753 e.size = size; 2754 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2755 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2756 e.mas2 = (va & MAS2_EPN_MASK) | flags; 2757 2758 /* Set supervisor RWX permission bits */ 2759 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2760 e.mas7 = (pa >> 32) & MAS7_RPN; 2761 2762 tlb1_write_entry(&e, -1); 2763 2764 return (0); 2765 } 2766 2767 /* 2768 * Map in contiguous RAM region into the TLB1. 2769 */ 2770 static vm_size_t 2771 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge) 2772 { 2773 vm_offset_t base; 2774 vm_size_t mapped, sz, ssize; 2775 2776 mapped = 0; 2777 base = va; 2778 ssize = size; 2779 2780 while (size > 0) { 2781 sz = 1UL << (ilog2(size) & ~1); 2782 /* Align size to PA */ 2783 if (pa % sz != 0) { 2784 do { 2785 sz >>= 2; 2786 } while (pa % sz != 0); 2787 } 2788 /* Now align from there to VA */ 2789 if (va % sz != 0) { 2790 do { 2791 sz >>= 2; 2792 } while (va % sz != 0); 2793 } 2794 #ifdef __powerpc64__ 2795 /* 2796 * Clamp TLB1 entries to 4G. 2797 * 2798 * While the e6500 supports up to 1TB mappings, the e5500 2799 * only supports up to 4G mappings. (0b1011) 2800 * 2801 * If any e6500 machines capable of supporting a very 2802 * large amount of memory appear in the future, we can 2803 * revisit this. 2804 * 2805 * For now, though, since we have plenty of space in TLB1, 2806 * always avoid creating entries larger than 4GB. 2807 */ 2808 sz = MIN(sz, 1UL << 32); 2809 #endif 2810 if (bootverbose) 2811 printf("Wiring VA=%p to PA=%jx (size=%lx)\n", 2812 (void *)va, (uintmax_t)pa, (long)sz); 2813 if (tlb1_set_entry(va, pa, sz, 2814 _TLB_ENTRY_SHARED | wimge) < 0) 2815 return (mapped); 2816 size -= sz; 2817 pa += sz; 2818 va += sz; 2819 } 2820 2821 mapped = (va - base); 2822 if (bootverbose) 2823 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n", 2824 mapped, mapped - ssize); 2825 2826 return (mapped); 2827 } 2828 2829 /* 2830 * TLB1 initialization routine, to be called after the very first 2831 * assembler level setup done in locore.S. 2832 */ 2833 void 2834 tlb1_init(void) 2835 { 2836 vm_offset_t mas2; 2837 uint32_t mas0, mas1, mas3, mas7; 2838 uint32_t tsz; 2839 2840 tlb1_get_tlbconf(); 2841 2842 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 2843 mtspr(SPR_MAS0, mas0); 2844 __asm __volatile("isync; tlbre"); 2845 2846 mas1 = mfspr(SPR_MAS1); 2847 mas2 = mfspr(SPR_MAS2); 2848 mas3 = mfspr(SPR_MAS3); 2849 mas7 = mfspr(SPR_MAS7); 2850 2851 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 2852 (mas3 & MAS3_RPN); 2853 2854 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2855 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 2856 kernstart = trunc_page(mas2); 2857 2858 /* Setup TLB miss defaults */ 2859 set_mas4_defaults(); 2860 } 2861 2862 /* 2863 * pmap_early_io_unmap() should be used in short conjunction with 2864 * pmap_early_io_map(), as in the following snippet: 2865 * 2866 * x = pmap_early_io_map(...); 2867 * <do something with x> 2868 * pmap_early_io_unmap(x, size); 2869 * 2870 * And avoiding more allocations between. 2871 */ 2872 void 2873 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 2874 { 2875 int i; 2876 tlb_entry_t e; 2877 vm_size_t isize; 2878 2879 size = roundup(size, PAGE_SIZE); 2880 isize = size; 2881 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 2882 tlb1_read_entry(&e, i); 2883 if (!(e.mas1 & MAS1_VALID)) 2884 continue; 2885 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 2886 size -= e.size; 2887 e.mas1 &= ~MAS1_VALID; 2888 tlb1_write_entry(&e, i); 2889 } 2890 } 2891 if (tlb1_map_base == va + isize) 2892 tlb1_map_base -= isize; 2893 } 2894 2895 vm_offset_t 2896 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 2897 { 2898 vm_paddr_t pa_base; 2899 vm_offset_t va, sz; 2900 int i; 2901 tlb_entry_t e; 2902 2903 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 2904 2905 for (i = 0; i < TLB1_ENTRIES; i++) { 2906 tlb1_read_entry(&e, i); 2907 if (!(e.mas1 & MAS1_VALID)) 2908 continue; 2909 if (pa >= e.phys && (pa + size) <= 2910 (e.phys + e.size)) 2911 return (e.virt + (pa - e.phys)); 2912 } 2913 2914 pa_base = rounddown(pa, PAGE_SIZE); 2915 size = roundup(size + (pa - pa_base), PAGE_SIZE); 2916 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 2917 va = tlb1_map_base + (pa - pa_base); 2918 2919 do { 2920 sz = 1 << (ilog2(size) & ~1); 2921 tlb1_set_entry(tlb1_map_base, pa_base, sz, 2922 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 2923 size -= sz; 2924 pa_base += sz; 2925 tlb1_map_base += sz; 2926 } while (size > 0); 2927 2928 return (va); 2929 } 2930 2931 void 2932 pmap_track_page(pmap_t pmap, vm_offset_t va) 2933 { 2934 vm_paddr_t pa; 2935 vm_page_t page; 2936 struct pv_entry *pve; 2937 2938 va = trunc_page(va); 2939 pa = pmap_kextract(va); 2940 page = PHYS_TO_VM_PAGE(pa); 2941 2942 rw_wlock(&pvh_global_lock); 2943 PMAP_LOCK(pmap); 2944 2945 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 2946 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 2947 goto out; 2948 } 2949 } 2950 page->md.pv_tracked = true; 2951 pv_insert(pmap, va, page); 2952 out: 2953 PMAP_UNLOCK(pmap); 2954 rw_wunlock(&pvh_global_lock); 2955 } 2956 2957 /* 2958 * Setup MAS4 defaults. 2959 * These values are loaded to MAS0-2 on a TLB miss. 2960 */ 2961 static void 2962 set_mas4_defaults(void) 2963 { 2964 uint32_t mas4; 2965 2966 /* Defaults: TLB0, PID0, TSIZED=4K */ 2967 mas4 = MAS4_TLBSELD0; 2968 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 2969 #ifdef SMP 2970 mas4 |= MAS4_MD; 2971 #endif 2972 mtspr(SPR_MAS4, mas4); 2973 __asm __volatile("isync"); 2974 } 2975 2976 /* 2977 * Return 0 if the physical IO range is encompassed by one of the 2978 * the TLB1 entries, otherwise return related error code. 2979 */ 2980 static int 2981 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 2982 { 2983 uint32_t prot; 2984 vm_paddr_t pa_start; 2985 vm_paddr_t pa_end; 2986 unsigned int entry_tsize; 2987 vm_size_t entry_size; 2988 tlb_entry_t e; 2989 2990 *va = (vm_offset_t)NULL; 2991 2992 tlb1_read_entry(&e, i); 2993 /* Skip invalid entries */ 2994 if (!(e.mas1 & MAS1_VALID)) 2995 return (EINVAL); 2996 2997 /* 2998 * The entry must be cache-inhibited, guarded, and r/w 2999 * so it can function as an i/o page 3000 */ 3001 prot = e.mas2 & (MAS2_I | MAS2_G); 3002 if (prot != (MAS2_I | MAS2_G)) 3003 return (EPERM); 3004 3005 prot = e.mas3 & (MAS3_SR | MAS3_SW); 3006 if (prot != (MAS3_SR | MAS3_SW)) 3007 return (EPERM); 3008 3009 /* The address should be within the entry range. */ 3010 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3011 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3012 3013 entry_size = tsize2size(entry_tsize); 3014 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 3015 (e.mas3 & MAS3_RPN); 3016 pa_end = pa_start + entry_size; 3017 3018 if ((pa < pa_start) || ((pa + size) > pa_end)) 3019 return (ERANGE); 3020 3021 /* Return virtual address of this mapping. */ 3022 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3023 return (0); 3024 } 3025 3026 #ifdef DDB 3027 /* Print out contents of the MAS registers for each TLB0 entry */ 3028 static void 3029 #ifdef __powerpc64__ 3030 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3, 3031 #else 3032 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3033 #endif 3034 uint32_t mas7) 3035 { 3036 int as; 3037 char desc[3]; 3038 tlbtid_t tid; 3039 vm_size_t size; 3040 unsigned int tsize; 3041 3042 desc[2] = '\0'; 3043 if (mas1 & MAS1_VALID) 3044 desc[0] = 'V'; 3045 else 3046 desc[0] = ' '; 3047 3048 if (mas1 & MAS1_IPROT) 3049 desc[1] = 'P'; 3050 else 3051 desc[1] = ' '; 3052 3053 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3054 tid = MAS1_GETTID(mas1); 3055 3056 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3057 size = 0; 3058 if (tsize) 3059 size = tsize2size(tsize); 3060 3061 printf("%3d: (%s) [AS=%d] " 3062 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x " 3063 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3064 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7); 3065 } 3066 3067 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries) 3068 { 3069 uint32_t mas0, mas1, mas3, mas7; 3070 #ifdef __powerpc64__ 3071 uint64_t mas2; 3072 #else 3073 uint32_t mas2; 3074 #endif 3075 int entryidx, way, idx; 3076 3077 printf("TLB0 entries:\n"); 3078 for (way = 0; way < TLB0_WAYS; way ++) 3079 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3080 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3081 mtspr(SPR_MAS0, mas0); 3082 3083 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3084 mtspr(SPR_MAS2, mas2); 3085 3086 __asm __volatile("isync; tlbre"); 3087 3088 mas1 = mfspr(SPR_MAS1); 3089 mas2 = mfspr(SPR_MAS2); 3090 mas3 = mfspr(SPR_MAS3); 3091 mas7 = mfspr(SPR_MAS7); 3092 3093 idx = tlb0_tableidx(mas2, way); 3094 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3095 } 3096 } 3097 3098 /* 3099 * Print out contents of the MAS registers for each TLB1 entry 3100 */ 3101 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries) 3102 { 3103 uint32_t mas0, mas1, mas3, mas7; 3104 #ifdef __powerpc64__ 3105 uint64_t mas2; 3106 #else 3107 uint32_t mas2; 3108 #endif 3109 int i; 3110 3111 printf("TLB1 entries:\n"); 3112 for (i = 0; i < TLB1_ENTRIES; i++) { 3113 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3114 mtspr(SPR_MAS0, mas0); 3115 3116 __asm __volatile("isync; tlbre"); 3117 3118 mas1 = mfspr(SPR_MAS1); 3119 mas2 = mfspr(SPR_MAS2); 3120 mas3 = mfspr(SPR_MAS3); 3121 mas7 = mfspr(SPR_MAS7); 3122 3123 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3124 } 3125 } 3126 #endif 3127