1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include <sys/param.h> 55 #include <sys/conf.h> 56 #include <sys/malloc.h> 57 #include <sys/ktr.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/kerneldump.h> 64 #include <sys/linker.h> 65 #include <sys/msgbuf.h> 66 #include <sys/lock.h> 67 #include <sys/mutex.h> 68 #include <sys/rwlock.h> 69 #include <sys/sched.h> 70 #include <sys/smp.h> 71 #include <sys/vmmeter.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_page.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_pageout.h> 77 #include <vm/vm_extern.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_param.h> 80 #include <vm/vm_map.h> 81 #include <vm/vm_pager.h> 82 #include <vm/uma.h> 83 84 #include <machine/cpu.h> 85 #include <machine/pcb.h> 86 #include <machine/platform.h> 87 88 #include <machine/tlb.h> 89 #include <machine/spr.h> 90 #include <machine/md_var.h> 91 #include <machine/mmuvar.h> 92 #include <machine/pmap.h> 93 #include <machine/pte.h> 94 95 #include "mmu_if.h" 96 97 #ifdef DEBUG 98 #define debugf(fmt, args...) printf(fmt, ##args) 99 #else 100 #define debugf(fmt, args...) 101 #endif 102 103 #define TODO panic("%s: not implemented", __func__); 104 105 extern unsigned char _etext[]; 106 extern unsigned char _end[]; 107 108 extern uint32_t *bootinfo; 109 110 #ifdef SMP 111 extern uint32_t bp_ntlb1s; 112 #endif 113 114 vm_paddr_t kernload; 115 vm_offset_t kernstart; 116 vm_size_t kernsize; 117 118 /* Message buffer and tables. */ 119 static vm_offset_t data_start; 120 static vm_size_t data_end; 121 122 /* Phys/avail memory regions. */ 123 static struct mem_region *availmem_regions; 124 static int availmem_regions_sz; 125 static struct mem_region *physmem_regions; 126 static int physmem_regions_sz; 127 128 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 129 static vm_offset_t zero_page_va; 130 static struct mtx zero_page_mutex; 131 132 static struct mtx tlbivax_mutex; 133 134 /* 135 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 136 * by idle thred only, no lock required. 137 */ 138 static vm_offset_t zero_page_idle_va; 139 140 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 141 static vm_offset_t copy_page_src_va; 142 static vm_offset_t copy_page_dst_va; 143 static struct mtx copy_page_mutex; 144 145 /**************************************************************************/ 146 /* PMAP */ 147 /**************************************************************************/ 148 149 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 150 vm_prot_t, u_int flags, int8_t psind); 151 152 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 153 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 154 155 /* 156 * If user pmap is processed with mmu_booke_remove and the resident count 157 * drops to 0, there are no more pages to remove, so we need not continue. 158 */ 159 #define PMAP_REMOVE_DONE(pmap) \ 160 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 161 162 extern void tid_flush(tlbtid_t tid, int tlb0_ways, int tlb0_entries_per_way); 163 extern int elf32_nxstack; 164 165 /**************************************************************************/ 166 /* TLB and TID handling */ 167 /**************************************************************************/ 168 169 /* Translation ID busy table */ 170 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 171 172 /* 173 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 174 * core revisions and should be read from h/w registers during early config. 175 */ 176 uint32_t tlb0_entries; 177 uint32_t tlb0_ways; 178 uint32_t tlb0_entries_per_way; 179 180 #define TLB0_ENTRIES (tlb0_entries) 181 #define TLB0_WAYS (tlb0_ways) 182 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 183 184 #define TLB1_ENTRIES 16 185 186 /* In-ram copy of the TLB1 */ 187 static tlb_entry_t tlb1[TLB1_ENTRIES]; 188 189 /* Next free entry in the TLB1 */ 190 static unsigned int tlb1_idx; 191 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 192 193 static tlbtid_t tid_alloc(struct pmap *); 194 195 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 196 197 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 198 static void tlb1_write_entry(unsigned int); 199 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 200 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 201 202 static vm_size_t tsize2size(unsigned int); 203 static unsigned int size2tsize(vm_size_t); 204 static unsigned int ilog2(unsigned int); 205 206 static void set_mas4_defaults(void); 207 208 static inline void tlb0_flush_entry(vm_offset_t); 209 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 210 211 /**************************************************************************/ 212 /* Page table management */ 213 /**************************************************************************/ 214 215 static struct rwlock_padalign pvh_global_lock; 216 217 /* Data for the pv entry allocation mechanism */ 218 static uma_zone_t pvzone; 219 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 220 221 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 222 223 #ifndef PMAP_SHPGPERPROC 224 #define PMAP_SHPGPERPROC 200 225 #endif 226 227 static void ptbl_init(void); 228 static struct ptbl_buf *ptbl_buf_alloc(void); 229 static void ptbl_buf_free(struct ptbl_buf *); 230 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 231 232 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 233 static void ptbl_free(mmu_t, pmap_t, unsigned int); 234 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 235 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 236 237 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 238 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 239 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 240 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 241 242 static pv_entry_t pv_alloc(void); 243 static void pv_free(pv_entry_t); 244 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 245 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 246 247 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 248 #define PTBL_BUFS (128 * 16) 249 250 struct ptbl_buf { 251 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 252 vm_offset_t kva; /* va of mapping */ 253 }; 254 255 /* ptbl free list and a lock used for access synchronization. */ 256 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 257 static struct mtx ptbl_buf_freelist_lock; 258 259 /* Base address of kva space allocated fot ptbl bufs. */ 260 static vm_offset_t ptbl_buf_pool_vabase; 261 262 /* Pointer to ptbl_buf structures. */ 263 static struct ptbl_buf *ptbl_bufs; 264 265 #ifdef SMP 266 void pmap_bootstrap_ap(volatile uint32_t *); 267 #endif 268 269 /* 270 * Kernel MMU interface 271 */ 272 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 273 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 274 vm_size_t, vm_offset_t); 275 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 276 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 277 vm_offset_t, vm_page_t *, vm_offset_t, int); 278 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 279 vm_prot_t, u_int flags, int8_t psind); 280 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 281 vm_page_t, vm_prot_t); 282 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 285 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 286 vm_prot_t); 287 static void mmu_booke_init(mmu_t); 288 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 289 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 291 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 292 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 293 int); 294 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 295 vm_paddr_t *); 296 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 297 vm_object_t, vm_pindex_t, vm_size_t); 298 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 299 static void mmu_booke_page_init(mmu_t, vm_page_t); 300 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 301 static void mmu_booke_pinit(mmu_t, pmap_t); 302 static void mmu_booke_pinit0(mmu_t, pmap_t); 303 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 304 vm_prot_t); 305 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 306 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 307 static void mmu_booke_release(mmu_t, pmap_t); 308 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 309 static void mmu_booke_remove_all(mmu_t, vm_page_t); 310 static void mmu_booke_remove_write(mmu_t, vm_page_t); 311 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 312 static void mmu_booke_zero_page(mmu_t, vm_page_t); 313 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 314 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 315 static void mmu_booke_activate(mmu_t, struct thread *); 316 static void mmu_booke_deactivate(mmu_t, struct thread *); 317 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 318 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 319 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 320 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 321 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 322 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 323 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 324 static void mmu_booke_kremove(mmu_t, vm_offset_t); 325 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 326 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 327 vm_size_t); 328 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 329 void **); 330 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 331 void *); 332 static void mmu_booke_scan_init(mmu_t); 333 334 static mmu_method_t mmu_booke_methods[] = { 335 /* pmap dispatcher interface */ 336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 337 MMUMETHOD(mmu_copy, mmu_booke_copy), 338 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 339 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 340 MMUMETHOD(mmu_enter, mmu_booke_enter), 341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 343 MMUMETHOD(mmu_extract, mmu_booke_extract), 344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 345 MMUMETHOD(mmu_init, mmu_booke_init), 346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 350 MMUMETHOD(mmu_map, mmu_booke_map), 351 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 354 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 356 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 358 MMUMETHOD(mmu_protect, mmu_booke_protect), 359 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 360 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 361 MMUMETHOD(mmu_release, mmu_booke_release), 362 MMUMETHOD(mmu_remove, mmu_booke_remove), 363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 366 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 367 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 368 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 369 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 370 MMUMETHOD(mmu_activate, mmu_booke_activate), 371 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 372 373 /* Internal interfaces */ 374 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 375 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 376 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 377 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 378 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 379 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 380 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 381 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 382 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 383 384 /* dumpsys() support */ 385 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 386 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 387 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 388 389 { 0, 0 } 390 }; 391 392 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 393 394 static __inline uint32_t 395 tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 396 { 397 uint32_t attrib; 398 int i; 399 400 if (ma != VM_MEMATTR_DEFAULT) { 401 switch (ma) { 402 case VM_MEMATTR_UNCACHEABLE: 403 return (PTE_I | PTE_G); 404 case VM_MEMATTR_WRITE_COMBINING: 405 case VM_MEMATTR_WRITE_BACK: 406 case VM_MEMATTR_PREFETCHABLE: 407 return (PTE_I); 408 case VM_MEMATTR_WRITE_THROUGH: 409 return (PTE_W | PTE_M); 410 } 411 } 412 413 /* 414 * Assume the page is cache inhibited and access is guarded unless 415 * it's in our available memory array. 416 */ 417 attrib = _TLB_ENTRY_IO; 418 for (i = 0; i < physmem_regions_sz; i++) { 419 if ((pa >= physmem_regions[i].mr_start) && 420 (pa < (physmem_regions[i].mr_start + 421 physmem_regions[i].mr_size))) { 422 attrib = _TLB_ENTRY_MEM; 423 break; 424 } 425 } 426 427 return (attrib); 428 } 429 430 static inline void 431 tlb_miss_lock(void) 432 { 433 #ifdef SMP 434 struct pcpu *pc; 435 436 if (!smp_started) 437 return; 438 439 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 440 if (pc != pcpup) { 441 442 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 443 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 444 445 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 446 ("tlb_miss_lock: tried to lock self")); 447 448 tlb_lock(pc->pc_booke_tlb_lock); 449 450 CTR1(KTR_PMAP, "%s: locked", __func__); 451 } 452 } 453 #endif 454 } 455 456 static inline void 457 tlb_miss_unlock(void) 458 { 459 #ifdef SMP 460 struct pcpu *pc; 461 462 if (!smp_started) 463 return; 464 465 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 466 if (pc != pcpup) { 467 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 468 __func__, pc->pc_cpuid); 469 470 tlb_unlock(pc->pc_booke_tlb_lock); 471 472 CTR1(KTR_PMAP, "%s: unlocked", __func__); 473 } 474 } 475 #endif 476 } 477 478 /* Return number of entries in TLB0. */ 479 static __inline void 480 tlb0_get_tlbconf(void) 481 { 482 uint32_t tlb0_cfg; 483 484 tlb0_cfg = mfspr(SPR_TLB0CFG); 485 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 486 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 487 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 488 } 489 490 /* Initialize pool of kva ptbl buffers. */ 491 static void 492 ptbl_init(void) 493 { 494 int i; 495 496 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 497 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 498 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 499 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 500 501 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 502 TAILQ_INIT(&ptbl_buf_freelist); 503 504 for (i = 0; i < PTBL_BUFS; i++) { 505 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 506 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 507 } 508 } 509 510 /* Get a ptbl_buf from the freelist. */ 511 static struct ptbl_buf * 512 ptbl_buf_alloc(void) 513 { 514 struct ptbl_buf *buf; 515 516 mtx_lock(&ptbl_buf_freelist_lock); 517 buf = TAILQ_FIRST(&ptbl_buf_freelist); 518 if (buf != NULL) 519 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 520 mtx_unlock(&ptbl_buf_freelist_lock); 521 522 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 523 524 return (buf); 525 } 526 527 /* Return ptbl buff to free pool. */ 528 static void 529 ptbl_buf_free(struct ptbl_buf *buf) 530 { 531 532 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 533 534 mtx_lock(&ptbl_buf_freelist_lock); 535 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 536 mtx_unlock(&ptbl_buf_freelist_lock); 537 } 538 539 /* 540 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 541 */ 542 static void 543 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 544 { 545 struct ptbl_buf *pbuf; 546 547 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 548 549 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 550 551 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 552 if (pbuf->kva == (vm_offset_t)ptbl) { 553 /* Remove from pmap ptbl buf list. */ 554 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 555 556 /* Free corresponding ptbl buf. */ 557 ptbl_buf_free(pbuf); 558 break; 559 } 560 } 561 562 /* Allocate page table. */ 563 static pte_t * 564 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 565 { 566 vm_page_t mtbl[PTBL_PAGES]; 567 vm_page_t m; 568 struct ptbl_buf *pbuf; 569 unsigned int pidx; 570 pte_t *ptbl; 571 int i, j; 572 573 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 574 (pmap == kernel_pmap), pdir_idx); 575 576 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 577 ("ptbl_alloc: invalid pdir_idx")); 578 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 579 ("pte_alloc: valid ptbl entry exists!")); 580 581 pbuf = ptbl_buf_alloc(); 582 if (pbuf == NULL) 583 panic("pte_alloc: couldn't alloc kernel virtual memory"); 584 585 ptbl = (pte_t *)pbuf->kva; 586 587 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 588 589 /* Allocate ptbl pages, this will sleep! */ 590 for (i = 0; i < PTBL_PAGES; i++) { 591 pidx = (PTBL_PAGES * pdir_idx) + i; 592 while ((m = vm_page_alloc(NULL, pidx, 593 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 594 PMAP_UNLOCK(pmap); 595 rw_wunlock(&pvh_global_lock); 596 if (nosleep) { 597 ptbl_free_pmap_ptbl(pmap, ptbl); 598 for (j = 0; j < i; j++) 599 vm_page_free(mtbl[j]); 600 atomic_subtract_int(&vm_cnt.v_wire_count, i); 601 return (NULL); 602 } 603 VM_WAIT; 604 rw_wlock(&pvh_global_lock); 605 PMAP_LOCK(pmap); 606 } 607 mtbl[i] = m; 608 } 609 610 /* Map allocated pages into kernel_pmap. */ 611 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 612 613 /* Zero whole ptbl. */ 614 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 615 616 /* Add pbuf to the pmap ptbl bufs list. */ 617 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 618 619 return (ptbl); 620 } 621 622 /* Free ptbl pages and invalidate pdir entry. */ 623 static void 624 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 625 { 626 pte_t *ptbl; 627 vm_paddr_t pa; 628 vm_offset_t va; 629 vm_page_t m; 630 int i; 631 632 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 633 (pmap == kernel_pmap), pdir_idx); 634 635 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 636 ("ptbl_free: invalid pdir_idx")); 637 638 ptbl = pmap->pm_pdir[pdir_idx]; 639 640 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 641 642 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 643 644 /* 645 * Invalidate the pdir entry as soon as possible, so that other CPUs 646 * don't attempt to look up the page tables we are releasing. 647 */ 648 mtx_lock_spin(&tlbivax_mutex); 649 tlb_miss_lock(); 650 651 pmap->pm_pdir[pdir_idx] = NULL; 652 653 tlb_miss_unlock(); 654 mtx_unlock_spin(&tlbivax_mutex); 655 656 for (i = 0; i < PTBL_PAGES; i++) { 657 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 658 pa = pte_vatopa(mmu, kernel_pmap, va); 659 m = PHYS_TO_VM_PAGE(pa); 660 vm_page_free_zero(m); 661 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 662 mmu_booke_kremove(mmu, va); 663 } 664 665 ptbl_free_pmap_ptbl(pmap, ptbl); 666 } 667 668 /* 669 * Decrement ptbl pages hold count and attempt to free ptbl pages. 670 * Called when removing pte entry from ptbl. 671 * 672 * Return 1 if ptbl pages were freed. 673 */ 674 static int 675 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 676 { 677 pte_t *ptbl; 678 vm_paddr_t pa; 679 vm_page_t m; 680 int i; 681 682 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 683 (pmap == kernel_pmap), pdir_idx); 684 685 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 686 ("ptbl_unhold: invalid pdir_idx")); 687 KASSERT((pmap != kernel_pmap), 688 ("ptbl_unhold: unholding kernel ptbl!")); 689 690 ptbl = pmap->pm_pdir[pdir_idx]; 691 692 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 693 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 694 ("ptbl_unhold: non kva ptbl")); 695 696 /* decrement hold count */ 697 for (i = 0; i < PTBL_PAGES; i++) { 698 pa = pte_vatopa(mmu, kernel_pmap, 699 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 700 m = PHYS_TO_VM_PAGE(pa); 701 m->wire_count--; 702 } 703 704 /* 705 * Free ptbl pages if there are no pte etries in this ptbl. 706 * wire_count has the same value for all ptbl pages, so check the last 707 * page. 708 */ 709 if (m->wire_count == 0) { 710 ptbl_free(mmu, pmap, pdir_idx); 711 712 //debugf("ptbl_unhold: e (freed ptbl)\n"); 713 return (1); 714 } 715 716 return (0); 717 } 718 719 /* 720 * Increment hold count for ptbl pages. This routine is used when a new pte 721 * entry is being inserted into the ptbl. 722 */ 723 static void 724 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 725 { 726 vm_paddr_t pa; 727 pte_t *ptbl; 728 vm_page_t m; 729 int i; 730 731 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 732 pdir_idx); 733 734 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 735 ("ptbl_hold: invalid pdir_idx")); 736 KASSERT((pmap != kernel_pmap), 737 ("ptbl_hold: holding kernel ptbl!")); 738 739 ptbl = pmap->pm_pdir[pdir_idx]; 740 741 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 742 743 for (i = 0; i < PTBL_PAGES; i++) { 744 pa = pte_vatopa(mmu, kernel_pmap, 745 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 746 m = PHYS_TO_VM_PAGE(pa); 747 m->wire_count++; 748 } 749 } 750 751 /* Allocate pv_entry structure. */ 752 pv_entry_t 753 pv_alloc(void) 754 { 755 pv_entry_t pv; 756 757 pv_entry_count++; 758 if (pv_entry_count > pv_entry_high_water) 759 pagedaemon_wakeup(); 760 pv = uma_zalloc(pvzone, M_NOWAIT); 761 762 return (pv); 763 } 764 765 /* Free pv_entry structure. */ 766 static __inline void 767 pv_free(pv_entry_t pve) 768 { 769 770 pv_entry_count--; 771 uma_zfree(pvzone, pve); 772 } 773 774 775 /* Allocate and initialize pv_entry structure. */ 776 static void 777 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 778 { 779 pv_entry_t pve; 780 781 //int su = (pmap == kernel_pmap); 782 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 783 // (u_int32_t)pmap, va, (u_int32_t)m); 784 785 pve = pv_alloc(); 786 if (pve == NULL) 787 panic("pv_insert: no pv entries!"); 788 789 pve->pv_pmap = pmap; 790 pve->pv_va = va; 791 792 /* add to pv_list */ 793 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 794 rw_assert(&pvh_global_lock, RA_WLOCKED); 795 796 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 797 798 //debugf("pv_insert: e\n"); 799 } 800 801 /* Destroy pv entry. */ 802 static void 803 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 804 { 805 pv_entry_t pve; 806 807 //int su = (pmap == kernel_pmap); 808 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 809 810 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 811 rw_assert(&pvh_global_lock, RA_WLOCKED); 812 813 /* find pv entry */ 814 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 815 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 816 /* remove from pv_list */ 817 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 818 if (TAILQ_EMPTY(&m->md.pv_list)) 819 vm_page_aflag_clear(m, PGA_WRITEABLE); 820 821 /* free pv entry struct */ 822 pv_free(pve); 823 break; 824 } 825 } 826 827 //debugf("pv_remove: e\n"); 828 } 829 830 /* 831 * Clean pte entry, try to free page table page if requested. 832 * 833 * Return 1 if ptbl pages were freed, otherwise return 0. 834 */ 835 static int 836 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 837 { 838 unsigned int pdir_idx = PDIR_IDX(va); 839 unsigned int ptbl_idx = PTBL_IDX(va); 840 vm_page_t m; 841 pte_t *ptbl; 842 pte_t *pte; 843 844 //int su = (pmap == kernel_pmap); 845 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 846 // su, (u_int32_t)pmap, va, flags); 847 848 ptbl = pmap->pm_pdir[pdir_idx]; 849 KASSERT(ptbl, ("pte_remove: null ptbl")); 850 851 pte = &ptbl[ptbl_idx]; 852 853 if (pte == NULL || !PTE_ISVALID(pte)) 854 return (0); 855 856 if (PTE_ISWIRED(pte)) 857 pmap->pm_stats.wired_count--; 858 859 /* Handle managed entry. */ 860 if (PTE_ISMANAGED(pte)) { 861 /* Get vm_page_t for mapped pte. */ 862 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 863 864 if (PTE_ISMODIFIED(pte)) 865 vm_page_dirty(m); 866 867 if (PTE_ISREFERENCED(pte)) 868 vm_page_aflag_set(m, PGA_REFERENCED); 869 870 pv_remove(pmap, va, m); 871 } 872 873 mtx_lock_spin(&tlbivax_mutex); 874 tlb_miss_lock(); 875 876 tlb0_flush_entry(va); 877 pte->flags = 0; 878 pte->rpn = 0; 879 880 tlb_miss_unlock(); 881 mtx_unlock_spin(&tlbivax_mutex); 882 883 pmap->pm_stats.resident_count--; 884 885 if (flags & PTBL_UNHOLD) { 886 //debugf("pte_remove: e (unhold)\n"); 887 return (ptbl_unhold(mmu, pmap, pdir_idx)); 888 } 889 890 //debugf("pte_remove: e\n"); 891 return (0); 892 } 893 894 /* 895 * Insert PTE for a given page and virtual address. 896 */ 897 static int 898 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 899 boolean_t nosleep) 900 { 901 unsigned int pdir_idx = PDIR_IDX(va); 902 unsigned int ptbl_idx = PTBL_IDX(va); 903 pte_t *ptbl, *pte; 904 905 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 906 pmap == kernel_pmap, pmap, va); 907 908 /* Get the page table pointer. */ 909 ptbl = pmap->pm_pdir[pdir_idx]; 910 911 if (ptbl == NULL) { 912 /* Allocate page table pages. */ 913 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 914 if (ptbl == NULL) { 915 KASSERT(nosleep, ("nosleep and NULL ptbl")); 916 return (ENOMEM); 917 } 918 } else { 919 /* 920 * Check if there is valid mapping for requested 921 * va, if there is, remove it. 922 */ 923 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 924 if (PTE_ISVALID(pte)) { 925 pte_remove(mmu, pmap, va, PTBL_HOLD); 926 } else { 927 /* 928 * pte is not used, increment hold count 929 * for ptbl pages. 930 */ 931 if (pmap != kernel_pmap) 932 ptbl_hold(mmu, pmap, pdir_idx); 933 } 934 } 935 936 /* 937 * Insert pv_entry into pv_list for mapped page if part of managed 938 * memory. 939 */ 940 if ((m->oflags & VPO_UNMANAGED) == 0) { 941 flags |= PTE_MANAGED; 942 943 /* Create and insert pv entry. */ 944 pv_insert(pmap, va, m); 945 } 946 947 pmap->pm_stats.resident_count++; 948 949 mtx_lock_spin(&tlbivax_mutex); 950 tlb_miss_lock(); 951 952 tlb0_flush_entry(va); 953 if (pmap->pm_pdir[pdir_idx] == NULL) { 954 /* 955 * If we just allocated a new page table, hook it in 956 * the pdir. 957 */ 958 pmap->pm_pdir[pdir_idx] = ptbl; 959 } 960 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 961 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 962 pte->flags |= (PTE_VALID | flags); 963 964 tlb_miss_unlock(); 965 mtx_unlock_spin(&tlbivax_mutex); 966 return (0); 967 } 968 969 /* Return the pa for the given pmap/va. */ 970 static vm_paddr_t 971 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 972 { 973 vm_paddr_t pa = 0; 974 pte_t *pte; 975 976 pte = pte_find(mmu, pmap, va); 977 if ((pte != NULL) && PTE_ISVALID(pte)) 978 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 979 return (pa); 980 } 981 982 /* Get a pointer to a PTE in a page table. */ 983 static pte_t * 984 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 985 { 986 unsigned int pdir_idx = PDIR_IDX(va); 987 unsigned int ptbl_idx = PTBL_IDX(va); 988 989 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 990 991 if (pmap->pm_pdir[pdir_idx]) 992 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 993 994 return (NULL); 995 } 996 997 /**************************************************************************/ 998 /* PMAP related */ 999 /**************************************************************************/ 1000 1001 /* 1002 * This is called during booke_init, before the system is really initialized. 1003 */ 1004 static void 1005 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1006 { 1007 vm_offset_t phys_kernelend; 1008 struct mem_region *mp, *mp1; 1009 int cnt, i, j; 1010 u_int s, e, sz; 1011 u_int phys_avail_count; 1012 vm_size_t physsz, hwphyssz, kstack0_sz; 1013 vm_offset_t kernel_pdir, kstack0, va; 1014 vm_paddr_t kstack0_phys; 1015 void *dpcpu; 1016 pte_t *pte; 1017 1018 debugf("mmu_booke_bootstrap: entered\n"); 1019 1020 /* Set interesting system properties */ 1021 hw_direct_map = 0; 1022 elf32_nxstack = 1; 1023 1024 /* Initialize invalidation mutex */ 1025 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1026 1027 /* Read TLB0 size and associativity. */ 1028 tlb0_get_tlbconf(); 1029 1030 /* 1031 * Align kernel start and end address (kernel image). 1032 * Note that kernel end does not necessarily relate to kernsize. 1033 * kernsize is the size of the kernel that is actually mapped. 1034 */ 1035 kernstart = trunc_page(start); 1036 data_start = round_page(kernelend); 1037 data_end = data_start; 1038 1039 /* 1040 * Addresses of preloaded modules (like file systems) use 1041 * physical addresses. Make sure we relocate those into 1042 * virtual addresses. 1043 */ 1044 preload_addr_relocate = kernstart - kernload; 1045 1046 /* Allocate the dynamic per-cpu area. */ 1047 dpcpu = (void *)data_end; 1048 data_end += DPCPU_SIZE; 1049 1050 /* Allocate space for the message buffer. */ 1051 msgbufp = (struct msgbuf *)data_end; 1052 data_end += msgbufsize; 1053 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1054 data_end); 1055 1056 data_end = round_page(data_end); 1057 1058 /* Allocate space for ptbl_bufs. */ 1059 ptbl_bufs = (struct ptbl_buf *)data_end; 1060 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1061 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1062 data_end); 1063 1064 data_end = round_page(data_end); 1065 1066 /* Allocate PTE tables for kernel KVA. */ 1067 kernel_pdir = data_end; 1068 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1069 PDIR_SIZE - 1) / PDIR_SIZE; 1070 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1071 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1072 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1073 1074 debugf(" data_end: 0x%08x\n", data_end); 1075 if (data_end - kernstart > kernsize) { 1076 kernsize += tlb1_mapin_region(kernstart + kernsize, 1077 kernload + kernsize, (data_end - kernstart) - kernsize); 1078 } 1079 data_end = kernstart + kernsize; 1080 debugf(" updated data_end: 0x%08x\n", data_end); 1081 1082 /* 1083 * Clear the structures - note we can only do it safely after the 1084 * possible additional TLB1 translations are in place (above) so that 1085 * all range up to the currently calculated 'data_end' is covered. 1086 */ 1087 dpcpu_init(dpcpu, 0); 1088 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1089 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1090 1091 /*******************************************************/ 1092 /* Set the start and end of kva. */ 1093 /*******************************************************/ 1094 virtual_avail = round_page(data_end); 1095 virtual_end = VM_MAX_KERNEL_ADDRESS; 1096 1097 /* Allocate KVA space for page zero/copy operations. */ 1098 zero_page_va = virtual_avail; 1099 virtual_avail += PAGE_SIZE; 1100 zero_page_idle_va = virtual_avail; 1101 virtual_avail += PAGE_SIZE; 1102 copy_page_src_va = virtual_avail; 1103 virtual_avail += PAGE_SIZE; 1104 copy_page_dst_va = virtual_avail; 1105 virtual_avail += PAGE_SIZE; 1106 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1107 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1108 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1109 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1110 1111 /* Initialize page zero/copy mutexes. */ 1112 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1113 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1114 1115 /* Allocate KVA space for ptbl bufs. */ 1116 ptbl_buf_pool_vabase = virtual_avail; 1117 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1118 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1119 ptbl_buf_pool_vabase, virtual_avail); 1120 1121 /* Calculate corresponding physical addresses for the kernel region. */ 1122 phys_kernelend = kernload + kernsize; 1123 debugf("kernel image and allocated data:\n"); 1124 debugf(" kernload = 0x%08x\n", kernload); 1125 debugf(" kernstart = 0x%08x\n", kernstart); 1126 debugf(" kernsize = 0x%08x\n", kernsize); 1127 1128 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1129 panic("mmu_booke_bootstrap: phys_avail too small"); 1130 1131 /* 1132 * Remove kernel physical address range from avail regions list. Page 1133 * align all regions. Non-page aligned memory isn't very interesting 1134 * to us. Also, sort the entries for ascending addresses. 1135 */ 1136 1137 /* Retrieve phys/avail mem regions */ 1138 mem_regions(&physmem_regions, &physmem_regions_sz, 1139 &availmem_regions, &availmem_regions_sz); 1140 sz = 0; 1141 cnt = availmem_regions_sz; 1142 debugf("processing avail regions:\n"); 1143 for (mp = availmem_regions; mp->mr_size; mp++) { 1144 s = mp->mr_start; 1145 e = mp->mr_start + mp->mr_size; 1146 debugf(" %08x-%08x -> ", s, e); 1147 /* Check whether this region holds all of the kernel. */ 1148 if (s < kernload && e > phys_kernelend) { 1149 availmem_regions[cnt].mr_start = phys_kernelend; 1150 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1151 e = kernload; 1152 } 1153 /* Look whether this regions starts within the kernel. */ 1154 if (s >= kernload && s < phys_kernelend) { 1155 if (e <= phys_kernelend) 1156 goto empty; 1157 s = phys_kernelend; 1158 } 1159 /* Now look whether this region ends within the kernel. */ 1160 if (e > kernload && e <= phys_kernelend) { 1161 if (s >= kernload) 1162 goto empty; 1163 e = kernload; 1164 } 1165 /* Now page align the start and size of the region. */ 1166 s = round_page(s); 1167 e = trunc_page(e); 1168 if (e < s) 1169 e = s; 1170 sz = e - s; 1171 debugf("%08x-%08x = %x\n", s, e, sz); 1172 1173 /* Check whether some memory is left here. */ 1174 if (sz == 0) { 1175 empty: 1176 memmove(mp, mp + 1, 1177 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1178 cnt--; 1179 mp--; 1180 continue; 1181 } 1182 1183 /* Do an insertion sort. */ 1184 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1185 if (s < mp1->mr_start) 1186 break; 1187 if (mp1 < mp) { 1188 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1189 mp1->mr_start = s; 1190 mp1->mr_size = sz; 1191 } else { 1192 mp->mr_start = s; 1193 mp->mr_size = sz; 1194 } 1195 } 1196 availmem_regions_sz = cnt; 1197 1198 /*******************************************************/ 1199 /* Steal physical memory for kernel stack from the end */ 1200 /* of the first avail region */ 1201 /*******************************************************/ 1202 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1203 kstack0_phys = availmem_regions[0].mr_start + 1204 availmem_regions[0].mr_size; 1205 kstack0_phys -= kstack0_sz; 1206 availmem_regions[0].mr_size -= kstack0_sz; 1207 1208 /*******************************************************/ 1209 /* Fill in phys_avail table, based on availmem_regions */ 1210 /*******************************************************/ 1211 phys_avail_count = 0; 1212 physsz = 0; 1213 hwphyssz = 0; 1214 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1215 1216 debugf("fill in phys_avail:\n"); 1217 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1218 1219 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1220 availmem_regions[i].mr_start, 1221 availmem_regions[i].mr_start + 1222 availmem_regions[i].mr_size, 1223 availmem_regions[i].mr_size); 1224 1225 if (hwphyssz != 0 && 1226 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1227 debugf(" hw.physmem adjust\n"); 1228 if (physsz < hwphyssz) { 1229 phys_avail[j] = availmem_regions[i].mr_start; 1230 phys_avail[j + 1] = 1231 availmem_regions[i].mr_start + 1232 hwphyssz - physsz; 1233 physsz = hwphyssz; 1234 phys_avail_count++; 1235 } 1236 break; 1237 } 1238 1239 phys_avail[j] = availmem_regions[i].mr_start; 1240 phys_avail[j + 1] = availmem_regions[i].mr_start + 1241 availmem_regions[i].mr_size; 1242 phys_avail_count++; 1243 physsz += availmem_regions[i].mr_size; 1244 } 1245 physmem = btoc(physsz); 1246 1247 /* Calculate the last available physical address. */ 1248 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1249 ; 1250 Maxmem = powerpc_btop(phys_avail[i + 1]); 1251 1252 debugf("Maxmem = 0x%08lx\n", Maxmem); 1253 debugf("phys_avail_count = %d\n", phys_avail_count); 1254 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1255 physmem); 1256 1257 /*******************************************************/ 1258 /* Initialize (statically allocated) kernel pmap. */ 1259 /*******************************************************/ 1260 PMAP_LOCK_INIT(kernel_pmap); 1261 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1262 1263 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1264 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1265 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1266 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1267 1268 /* Initialize kernel pdir */ 1269 for (i = 0; i < kernel_ptbls; i++) 1270 kernel_pmap->pm_pdir[kptbl_min + i] = 1271 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1272 1273 for (i = 0; i < MAXCPU; i++) { 1274 kernel_pmap->pm_tid[i] = TID_KERNEL; 1275 1276 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1277 tidbusy[i][0] = kernel_pmap; 1278 } 1279 1280 /* 1281 * Fill in PTEs covering kernel code and data. They are not required 1282 * for address translation, as this area is covered by static TLB1 1283 * entries, but for pte_vatopa() to work correctly with kernel area 1284 * addresses. 1285 */ 1286 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1287 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1288 pte->rpn = kernload + (va - kernstart); 1289 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1290 PTE_VALID; 1291 } 1292 /* Mark kernel_pmap active on all CPUs */ 1293 CPU_FILL(&kernel_pmap->pm_active); 1294 1295 /* 1296 * Initialize the global pv list lock. 1297 */ 1298 rw_init(&pvh_global_lock, "pmap pv global"); 1299 1300 /*******************************************************/ 1301 /* Final setup */ 1302 /*******************************************************/ 1303 1304 /* Enter kstack0 into kernel map, provide guard page */ 1305 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1306 thread0.td_kstack = kstack0; 1307 thread0.td_kstack_pages = KSTACK_PAGES; 1308 1309 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1310 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1311 kstack0_phys, kstack0_phys + kstack0_sz); 1312 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1313 1314 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1315 for (i = 0; i < KSTACK_PAGES; i++) { 1316 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1317 kstack0 += PAGE_SIZE; 1318 kstack0_phys += PAGE_SIZE; 1319 } 1320 1321 pmap_bootstrapped = 1; 1322 1323 debugf("virtual_avail = %08x\n", virtual_avail); 1324 debugf("virtual_end = %08x\n", virtual_end); 1325 1326 debugf("mmu_booke_bootstrap: exit\n"); 1327 } 1328 1329 #ifdef SMP 1330 void 1331 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1332 { 1333 int i; 1334 1335 /* 1336 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1337 * have the snapshot of its contents in the s/w tlb1[] table, so use 1338 * these values directly to (re)program AP's TLB1 hardware. 1339 */ 1340 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1341 /* Skip invalid entries */ 1342 if (!(tlb1[i].mas1 & MAS1_VALID)) 1343 continue; 1344 1345 tlb1_write_entry(i); 1346 } 1347 1348 set_mas4_defaults(); 1349 } 1350 #endif 1351 1352 /* 1353 * Get the physical page address for the given pmap/virtual address. 1354 */ 1355 static vm_paddr_t 1356 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1357 { 1358 vm_paddr_t pa; 1359 1360 PMAP_LOCK(pmap); 1361 pa = pte_vatopa(mmu, pmap, va); 1362 PMAP_UNLOCK(pmap); 1363 1364 return (pa); 1365 } 1366 1367 /* 1368 * Extract the physical page address associated with the given 1369 * kernel virtual address. 1370 */ 1371 static vm_paddr_t 1372 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1373 { 1374 int i; 1375 1376 /* Check TLB1 mappings */ 1377 for (i = 0; i < tlb1_idx; i++) { 1378 if (!(tlb1[i].mas1 & MAS1_VALID)) 1379 continue; 1380 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1381 return (tlb1[i].phys + (va - tlb1[i].virt)); 1382 } 1383 1384 return (pte_vatopa(mmu, kernel_pmap, va)); 1385 } 1386 1387 /* 1388 * Initialize the pmap module. 1389 * Called by vm_init, to initialize any structures that the pmap 1390 * system needs to map virtual memory. 1391 */ 1392 static void 1393 mmu_booke_init(mmu_t mmu) 1394 { 1395 int shpgperproc = PMAP_SHPGPERPROC; 1396 1397 /* 1398 * Initialize the address space (zone) for the pv entries. Set a 1399 * high water mark so that the system can recover from excessive 1400 * numbers of pv entries. 1401 */ 1402 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1403 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1404 1405 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1406 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1407 1408 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1409 pv_entry_high_water = 9 * (pv_entry_max / 10); 1410 1411 uma_zone_reserve_kva(pvzone, pv_entry_max); 1412 1413 /* Pre-fill pvzone with initial number of pv entries. */ 1414 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1415 1416 /* Initialize ptbl allocation. */ 1417 ptbl_init(); 1418 } 1419 1420 /* 1421 * Map a list of wired pages into kernel virtual address space. This is 1422 * intended for temporary mappings which do not need page modification or 1423 * references recorded. Existing mappings in the region are overwritten. 1424 */ 1425 static void 1426 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1427 { 1428 vm_offset_t va; 1429 1430 va = sva; 1431 while (count-- > 0) { 1432 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1433 va += PAGE_SIZE; 1434 m++; 1435 } 1436 } 1437 1438 /* 1439 * Remove page mappings from kernel virtual address space. Intended for 1440 * temporary mappings entered by mmu_booke_qenter. 1441 */ 1442 static void 1443 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1444 { 1445 vm_offset_t va; 1446 1447 va = sva; 1448 while (count-- > 0) { 1449 mmu_booke_kremove(mmu, va); 1450 va += PAGE_SIZE; 1451 } 1452 } 1453 1454 /* 1455 * Map a wired page into kernel virtual address space. 1456 */ 1457 static void 1458 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1459 { 1460 1461 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1462 } 1463 1464 static void 1465 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1466 { 1467 unsigned int pdir_idx = PDIR_IDX(va); 1468 unsigned int ptbl_idx = PTBL_IDX(va); 1469 uint32_t flags; 1470 pte_t *pte; 1471 1472 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1473 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1474 1475 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1476 flags |= tlb_calc_wimg(pa, ma); 1477 1478 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1479 1480 mtx_lock_spin(&tlbivax_mutex); 1481 tlb_miss_lock(); 1482 1483 if (PTE_ISVALID(pte)) { 1484 1485 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1486 1487 /* Flush entry from TLB0 */ 1488 tlb0_flush_entry(va); 1489 } 1490 1491 pte->rpn = pa & ~PTE_PA_MASK; 1492 pte->flags = flags; 1493 1494 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1495 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1496 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1497 1498 /* Flush the real memory from the instruction cache. */ 1499 if ((flags & (PTE_I | PTE_G)) == 0) { 1500 __syncicache((void *)va, PAGE_SIZE); 1501 } 1502 1503 tlb_miss_unlock(); 1504 mtx_unlock_spin(&tlbivax_mutex); 1505 } 1506 1507 /* 1508 * Remove a page from kernel page table. 1509 */ 1510 static void 1511 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1512 { 1513 unsigned int pdir_idx = PDIR_IDX(va); 1514 unsigned int ptbl_idx = PTBL_IDX(va); 1515 pte_t *pte; 1516 1517 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1518 1519 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1520 (va <= VM_MAX_KERNEL_ADDRESS)), 1521 ("mmu_booke_kremove: invalid va")); 1522 1523 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1524 1525 if (!PTE_ISVALID(pte)) { 1526 1527 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1528 1529 return; 1530 } 1531 1532 mtx_lock_spin(&tlbivax_mutex); 1533 tlb_miss_lock(); 1534 1535 /* Invalidate entry in TLB0, update PTE. */ 1536 tlb0_flush_entry(va); 1537 pte->flags = 0; 1538 pte->rpn = 0; 1539 1540 tlb_miss_unlock(); 1541 mtx_unlock_spin(&tlbivax_mutex); 1542 } 1543 1544 /* 1545 * Initialize pmap associated with process 0. 1546 */ 1547 static void 1548 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1549 { 1550 1551 PMAP_LOCK_INIT(pmap); 1552 mmu_booke_pinit(mmu, pmap); 1553 PCPU_SET(curpmap, pmap); 1554 } 1555 1556 /* 1557 * Initialize a preallocated and zeroed pmap structure, 1558 * such as one in a vmspace structure. 1559 */ 1560 static void 1561 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1562 { 1563 int i; 1564 1565 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1566 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1567 1568 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1569 1570 for (i = 0; i < MAXCPU; i++) 1571 pmap->pm_tid[i] = TID_NONE; 1572 CPU_ZERO(&kernel_pmap->pm_active); 1573 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1574 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1575 TAILQ_INIT(&pmap->pm_ptbl_list); 1576 } 1577 1578 /* 1579 * Release any resources held by the given physical map. 1580 * Called when a pmap initialized by mmu_booke_pinit is being released. 1581 * Should only be called if the map contains no valid mappings. 1582 */ 1583 static void 1584 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1585 { 1586 1587 KASSERT(pmap->pm_stats.resident_count == 0, 1588 ("pmap_release: pmap resident count %ld != 0", 1589 pmap->pm_stats.resident_count)); 1590 } 1591 1592 /* 1593 * Insert the given physical page at the specified virtual address in the 1594 * target physical map with the protection requested. If specified the page 1595 * will be wired down. 1596 */ 1597 static int 1598 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1599 vm_prot_t prot, u_int flags, int8_t psind) 1600 { 1601 int error; 1602 1603 rw_wlock(&pvh_global_lock); 1604 PMAP_LOCK(pmap); 1605 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1606 rw_wunlock(&pvh_global_lock); 1607 PMAP_UNLOCK(pmap); 1608 return (error); 1609 } 1610 1611 static int 1612 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1613 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1614 { 1615 pte_t *pte; 1616 vm_paddr_t pa; 1617 uint32_t flags; 1618 int error, su, sync; 1619 1620 pa = VM_PAGE_TO_PHYS(m); 1621 su = (pmap == kernel_pmap); 1622 sync = 0; 1623 1624 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1625 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1626 // (u_int32_t)pmap, su, pmap->pm_tid, 1627 // (u_int32_t)m, va, pa, prot, flags); 1628 1629 if (su) { 1630 KASSERT(((va >= virtual_avail) && 1631 (va <= VM_MAX_KERNEL_ADDRESS)), 1632 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1633 } else { 1634 KASSERT((va <= VM_MAXUSER_ADDRESS), 1635 ("mmu_booke_enter_locked: user pmap, non user va")); 1636 } 1637 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1638 VM_OBJECT_ASSERT_LOCKED(m->object); 1639 1640 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1641 1642 /* 1643 * If there is an existing mapping, and the physical address has not 1644 * changed, must be protection or wiring change. 1645 */ 1646 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1647 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1648 1649 /* 1650 * Before actually updating pte->flags we calculate and 1651 * prepare its new value in a helper var. 1652 */ 1653 flags = pte->flags; 1654 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1655 1656 /* Wiring change, just update stats. */ 1657 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1658 if (!PTE_ISWIRED(pte)) { 1659 flags |= PTE_WIRED; 1660 pmap->pm_stats.wired_count++; 1661 } 1662 } else { 1663 if (PTE_ISWIRED(pte)) { 1664 flags &= ~PTE_WIRED; 1665 pmap->pm_stats.wired_count--; 1666 } 1667 } 1668 1669 if (prot & VM_PROT_WRITE) { 1670 /* Add write permissions. */ 1671 flags |= PTE_SW; 1672 if (!su) 1673 flags |= PTE_UW; 1674 1675 if ((flags & PTE_MANAGED) != 0) 1676 vm_page_aflag_set(m, PGA_WRITEABLE); 1677 } else { 1678 /* Handle modified pages, sense modify status. */ 1679 1680 /* 1681 * The PTE_MODIFIED flag could be set by underlying 1682 * TLB misses since we last read it (above), possibly 1683 * other CPUs could update it so we check in the PTE 1684 * directly rather than rely on that saved local flags 1685 * copy. 1686 */ 1687 if (PTE_ISMODIFIED(pte)) 1688 vm_page_dirty(m); 1689 } 1690 1691 if (prot & VM_PROT_EXECUTE) { 1692 flags |= PTE_SX; 1693 if (!su) 1694 flags |= PTE_UX; 1695 1696 /* 1697 * Check existing flags for execute permissions: if we 1698 * are turning execute permissions on, icache should 1699 * be flushed. 1700 */ 1701 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1702 sync++; 1703 } 1704 1705 flags &= ~PTE_REFERENCED; 1706 1707 /* 1708 * The new flags value is all calculated -- only now actually 1709 * update the PTE. 1710 */ 1711 mtx_lock_spin(&tlbivax_mutex); 1712 tlb_miss_lock(); 1713 1714 tlb0_flush_entry(va); 1715 pte->flags = flags; 1716 1717 tlb_miss_unlock(); 1718 mtx_unlock_spin(&tlbivax_mutex); 1719 1720 } else { 1721 /* 1722 * If there is an existing mapping, but it's for a different 1723 * physical address, pte_enter() will delete the old mapping. 1724 */ 1725 //if ((pte != NULL) && PTE_ISVALID(pte)) 1726 // debugf("mmu_booke_enter_locked: replace\n"); 1727 //else 1728 // debugf("mmu_booke_enter_locked: new\n"); 1729 1730 /* Now set up the flags and install the new mapping. */ 1731 flags = (PTE_SR | PTE_VALID); 1732 flags |= PTE_M; 1733 1734 if (!su) 1735 flags |= PTE_UR; 1736 1737 if (prot & VM_PROT_WRITE) { 1738 flags |= PTE_SW; 1739 if (!su) 1740 flags |= PTE_UW; 1741 1742 if ((m->oflags & VPO_UNMANAGED) == 0) 1743 vm_page_aflag_set(m, PGA_WRITEABLE); 1744 } 1745 1746 if (prot & VM_PROT_EXECUTE) { 1747 flags |= PTE_SX; 1748 if (!su) 1749 flags |= PTE_UX; 1750 } 1751 1752 /* If its wired update stats. */ 1753 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1754 flags |= PTE_WIRED; 1755 1756 error = pte_enter(mmu, pmap, m, va, flags, 1757 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1758 if (error != 0) 1759 return (KERN_RESOURCE_SHORTAGE); 1760 1761 if ((flags & PMAP_ENTER_WIRED) != 0) 1762 pmap->pm_stats.wired_count++; 1763 1764 /* Flush the real memory from the instruction cache. */ 1765 if (prot & VM_PROT_EXECUTE) 1766 sync++; 1767 } 1768 1769 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1770 __syncicache((void *)va, PAGE_SIZE); 1771 sync = 0; 1772 } 1773 1774 return (KERN_SUCCESS); 1775 } 1776 1777 /* 1778 * Maps a sequence of resident pages belonging to the same object. 1779 * The sequence begins with the given page m_start. This page is 1780 * mapped at the given virtual address start. Each subsequent page is 1781 * mapped at a virtual address that is offset from start by the same 1782 * amount as the page is offset from m_start within the object. The 1783 * last page in the sequence is the page with the largest offset from 1784 * m_start that can be mapped at a virtual address less than the given 1785 * virtual address end. Not every virtual page between start and end 1786 * is mapped; only those for which a resident page exists with the 1787 * corresponding offset from m_start are mapped. 1788 */ 1789 static void 1790 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1791 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1792 { 1793 vm_page_t m; 1794 vm_pindex_t diff, psize; 1795 1796 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1797 1798 psize = atop(end - start); 1799 m = m_start; 1800 rw_wlock(&pvh_global_lock); 1801 PMAP_LOCK(pmap); 1802 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1803 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1804 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1805 PMAP_ENTER_NOSLEEP, 0); 1806 m = TAILQ_NEXT(m, listq); 1807 } 1808 rw_wunlock(&pvh_global_lock); 1809 PMAP_UNLOCK(pmap); 1810 } 1811 1812 static void 1813 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1814 vm_prot_t prot) 1815 { 1816 1817 rw_wlock(&pvh_global_lock); 1818 PMAP_LOCK(pmap); 1819 mmu_booke_enter_locked(mmu, pmap, va, m, 1820 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1821 0); 1822 rw_wunlock(&pvh_global_lock); 1823 PMAP_UNLOCK(pmap); 1824 } 1825 1826 /* 1827 * Remove the given range of addresses from the specified map. 1828 * 1829 * It is assumed that the start and end are properly rounded to the page size. 1830 */ 1831 static void 1832 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1833 { 1834 pte_t *pte; 1835 uint8_t hold_flag; 1836 1837 int su = (pmap == kernel_pmap); 1838 1839 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1840 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1841 1842 if (su) { 1843 KASSERT(((va >= virtual_avail) && 1844 (va <= VM_MAX_KERNEL_ADDRESS)), 1845 ("mmu_booke_remove: kernel pmap, non kernel va")); 1846 } else { 1847 KASSERT((va <= VM_MAXUSER_ADDRESS), 1848 ("mmu_booke_remove: user pmap, non user va")); 1849 } 1850 1851 if (PMAP_REMOVE_DONE(pmap)) { 1852 //debugf("mmu_booke_remove: e (empty)\n"); 1853 return; 1854 } 1855 1856 hold_flag = PTBL_HOLD_FLAG(pmap); 1857 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1858 1859 rw_wlock(&pvh_global_lock); 1860 PMAP_LOCK(pmap); 1861 for (; va < endva; va += PAGE_SIZE) { 1862 pte = pte_find(mmu, pmap, va); 1863 if ((pte != NULL) && PTE_ISVALID(pte)) 1864 pte_remove(mmu, pmap, va, hold_flag); 1865 } 1866 PMAP_UNLOCK(pmap); 1867 rw_wunlock(&pvh_global_lock); 1868 1869 //debugf("mmu_booke_remove: e\n"); 1870 } 1871 1872 /* 1873 * Remove physical page from all pmaps in which it resides. 1874 */ 1875 static void 1876 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1877 { 1878 pv_entry_t pv, pvn; 1879 uint8_t hold_flag; 1880 1881 rw_wlock(&pvh_global_lock); 1882 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1883 pvn = TAILQ_NEXT(pv, pv_link); 1884 1885 PMAP_LOCK(pv->pv_pmap); 1886 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1887 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1888 PMAP_UNLOCK(pv->pv_pmap); 1889 } 1890 vm_page_aflag_clear(m, PGA_WRITEABLE); 1891 rw_wunlock(&pvh_global_lock); 1892 } 1893 1894 /* 1895 * Map a range of physical addresses into kernel virtual address space. 1896 */ 1897 static vm_offset_t 1898 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1899 vm_paddr_t pa_end, int prot) 1900 { 1901 vm_offset_t sva = *virt; 1902 vm_offset_t va = sva; 1903 1904 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1905 // sva, pa_start, pa_end); 1906 1907 while (pa_start < pa_end) { 1908 mmu_booke_kenter(mmu, va, pa_start); 1909 va += PAGE_SIZE; 1910 pa_start += PAGE_SIZE; 1911 } 1912 *virt = va; 1913 1914 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1915 return (sva); 1916 } 1917 1918 /* 1919 * The pmap must be activated before it's address space can be accessed in any 1920 * way. 1921 */ 1922 static void 1923 mmu_booke_activate(mmu_t mmu, struct thread *td) 1924 { 1925 pmap_t pmap; 1926 u_int cpuid; 1927 1928 pmap = &td->td_proc->p_vmspace->vm_pmap; 1929 1930 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1931 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1932 1933 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1934 1935 sched_pin(); 1936 1937 cpuid = PCPU_GET(cpuid); 1938 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1939 PCPU_SET(curpmap, pmap); 1940 1941 if (pmap->pm_tid[cpuid] == TID_NONE) 1942 tid_alloc(pmap); 1943 1944 /* Load PID0 register with pmap tid value. */ 1945 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1946 __asm __volatile("isync"); 1947 1948 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1949 1950 sched_unpin(); 1951 1952 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1953 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1954 } 1955 1956 /* 1957 * Deactivate the specified process's address space. 1958 */ 1959 static void 1960 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1961 { 1962 pmap_t pmap; 1963 1964 pmap = &td->td_proc->p_vmspace->vm_pmap; 1965 1966 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1967 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1968 1969 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 1970 1971 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1972 PCPU_SET(curpmap, NULL); 1973 } 1974 1975 /* 1976 * Copy the range specified by src_addr/len 1977 * from the source map to the range dst_addr/len 1978 * in the destination map. 1979 * 1980 * This routine is only advisory and need not do anything. 1981 */ 1982 static void 1983 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1984 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1985 { 1986 1987 } 1988 1989 /* 1990 * Set the physical protection on the specified range of this map as requested. 1991 */ 1992 static void 1993 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1994 vm_prot_t prot) 1995 { 1996 vm_offset_t va; 1997 vm_page_t m; 1998 pte_t *pte; 1999 2000 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2001 mmu_booke_remove(mmu, pmap, sva, eva); 2002 return; 2003 } 2004 2005 if (prot & VM_PROT_WRITE) 2006 return; 2007 2008 PMAP_LOCK(pmap); 2009 for (va = sva; va < eva; va += PAGE_SIZE) { 2010 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2011 if (PTE_ISVALID(pte)) { 2012 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2013 2014 mtx_lock_spin(&tlbivax_mutex); 2015 tlb_miss_lock(); 2016 2017 /* Handle modified pages. */ 2018 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2019 vm_page_dirty(m); 2020 2021 tlb0_flush_entry(va); 2022 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2023 2024 tlb_miss_unlock(); 2025 mtx_unlock_spin(&tlbivax_mutex); 2026 } 2027 } 2028 } 2029 PMAP_UNLOCK(pmap); 2030 } 2031 2032 /* 2033 * Clear the write and modified bits in each of the given page's mappings. 2034 */ 2035 static void 2036 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2037 { 2038 pv_entry_t pv; 2039 pte_t *pte; 2040 2041 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2042 ("mmu_booke_remove_write: page %p is not managed", m)); 2043 2044 /* 2045 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2046 * set by another thread while the object is locked. Thus, 2047 * if PGA_WRITEABLE is clear, no page table entries need updating. 2048 */ 2049 VM_OBJECT_ASSERT_WLOCKED(m->object); 2050 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2051 return; 2052 rw_wlock(&pvh_global_lock); 2053 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2054 PMAP_LOCK(pv->pv_pmap); 2055 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2056 if (PTE_ISVALID(pte)) { 2057 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2058 2059 mtx_lock_spin(&tlbivax_mutex); 2060 tlb_miss_lock(); 2061 2062 /* Handle modified pages. */ 2063 if (PTE_ISMODIFIED(pte)) 2064 vm_page_dirty(m); 2065 2066 /* Flush mapping from TLB0. */ 2067 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2068 2069 tlb_miss_unlock(); 2070 mtx_unlock_spin(&tlbivax_mutex); 2071 } 2072 } 2073 PMAP_UNLOCK(pv->pv_pmap); 2074 } 2075 vm_page_aflag_clear(m, PGA_WRITEABLE); 2076 rw_wunlock(&pvh_global_lock); 2077 } 2078 2079 static void 2080 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2081 { 2082 pte_t *pte; 2083 pmap_t pmap; 2084 vm_page_t m; 2085 vm_offset_t addr; 2086 vm_paddr_t pa = 0; 2087 int active, valid; 2088 2089 va = trunc_page(va); 2090 sz = round_page(sz); 2091 2092 rw_wlock(&pvh_global_lock); 2093 pmap = PCPU_GET(curpmap); 2094 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2095 while (sz > 0) { 2096 PMAP_LOCK(pm); 2097 pte = pte_find(mmu, pm, va); 2098 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2099 if (valid) 2100 pa = PTE_PA(pte); 2101 PMAP_UNLOCK(pm); 2102 if (valid) { 2103 if (!active) { 2104 /* Create a mapping in the active pmap. */ 2105 addr = 0; 2106 m = PHYS_TO_VM_PAGE(pa); 2107 PMAP_LOCK(pmap); 2108 pte_enter(mmu, pmap, m, addr, 2109 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2110 __syncicache((void *)addr, PAGE_SIZE); 2111 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2112 PMAP_UNLOCK(pmap); 2113 } else 2114 __syncicache((void *)va, PAGE_SIZE); 2115 } 2116 va += PAGE_SIZE; 2117 sz -= PAGE_SIZE; 2118 } 2119 rw_wunlock(&pvh_global_lock); 2120 } 2121 2122 /* 2123 * Atomically extract and hold the physical page with the given 2124 * pmap and virtual address pair if that mapping permits the given 2125 * protection. 2126 */ 2127 static vm_page_t 2128 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2129 vm_prot_t prot) 2130 { 2131 pte_t *pte; 2132 vm_page_t m; 2133 uint32_t pte_wbit; 2134 vm_paddr_t pa; 2135 2136 m = NULL; 2137 pa = 0; 2138 PMAP_LOCK(pmap); 2139 retry: 2140 pte = pte_find(mmu, pmap, va); 2141 if ((pte != NULL) && PTE_ISVALID(pte)) { 2142 if (pmap == kernel_pmap) 2143 pte_wbit = PTE_SW; 2144 else 2145 pte_wbit = PTE_UW; 2146 2147 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2148 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2149 goto retry; 2150 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2151 vm_page_hold(m); 2152 } 2153 } 2154 2155 PA_UNLOCK_COND(pa); 2156 PMAP_UNLOCK(pmap); 2157 return (m); 2158 } 2159 2160 /* 2161 * Initialize a vm_page's machine-dependent fields. 2162 */ 2163 static void 2164 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2165 { 2166 2167 TAILQ_INIT(&m->md.pv_list); 2168 } 2169 2170 /* 2171 * mmu_booke_zero_page_area zeros the specified hardware page by 2172 * mapping it into virtual memory and using bzero to clear 2173 * its contents. 2174 * 2175 * off and size must reside within a single page. 2176 */ 2177 static void 2178 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2179 { 2180 vm_offset_t va; 2181 2182 /* XXX KASSERT off and size are within a single page? */ 2183 2184 mtx_lock(&zero_page_mutex); 2185 va = zero_page_va; 2186 2187 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2188 bzero((caddr_t)va + off, size); 2189 mmu_booke_kremove(mmu, va); 2190 2191 mtx_unlock(&zero_page_mutex); 2192 } 2193 2194 /* 2195 * mmu_booke_zero_page zeros the specified hardware page. 2196 */ 2197 static void 2198 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2199 { 2200 2201 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2202 } 2203 2204 /* 2205 * mmu_booke_copy_page copies the specified (machine independent) page by 2206 * mapping the page into virtual memory and using memcopy to copy the page, 2207 * one machine dependent page at a time. 2208 */ 2209 static void 2210 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2211 { 2212 vm_offset_t sva, dva; 2213 2214 sva = copy_page_src_va; 2215 dva = copy_page_dst_va; 2216 2217 mtx_lock(©_page_mutex); 2218 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2219 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2220 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2221 mmu_booke_kremove(mmu, dva); 2222 mmu_booke_kremove(mmu, sva); 2223 mtx_unlock(©_page_mutex); 2224 } 2225 2226 static inline void 2227 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2228 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2229 { 2230 void *a_cp, *b_cp; 2231 vm_offset_t a_pg_offset, b_pg_offset; 2232 int cnt; 2233 2234 mtx_lock(©_page_mutex); 2235 while (xfersize > 0) { 2236 a_pg_offset = a_offset & PAGE_MASK; 2237 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2238 mmu_booke_kenter(mmu, copy_page_src_va, 2239 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2240 a_cp = (char *)copy_page_src_va + a_pg_offset; 2241 b_pg_offset = b_offset & PAGE_MASK; 2242 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2243 mmu_booke_kenter(mmu, copy_page_dst_va, 2244 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2245 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2246 bcopy(a_cp, b_cp, cnt); 2247 mmu_booke_kremove(mmu, copy_page_dst_va); 2248 mmu_booke_kremove(mmu, copy_page_src_va); 2249 a_offset += cnt; 2250 b_offset += cnt; 2251 xfersize -= cnt; 2252 } 2253 mtx_unlock(©_page_mutex); 2254 } 2255 2256 /* 2257 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2258 * into virtual memory and using bzero to clear its contents. This is intended 2259 * to be called from the vm_pagezero process only and outside of Giant. No 2260 * lock is required. 2261 */ 2262 static void 2263 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2264 { 2265 vm_offset_t va; 2266 2267 va = zero_page_idle_va; 2268 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2269 bzero((caddr_t)va, PAGE_SIZE); 2270 mmu_booke_kremove(mmu, va); 2271 } 2272 2273 /* 2274 * Return whether or not the specified physical page was modified 2275 * in any of physical maps. 2276 */ 2277 static boolean_t 2278 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2279 { 2280 pte_t *pte; 2281 pv_entry_t pv; 2282 boolean_t rv; 2283 2284 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2285 ("mmu_booke_is_modified: page %p is not managed", m)); 2286 rv = FALSE; 2287 2288 /* 2289 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2290 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2291 * is clear, no PTEs can be modified. 2292 */ 2293 VM_OBJECT_ASSERT_WLOCKED(m->object); 2294 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2295 return (rv); 2296 rw_wlock(&pvh_global_lock); 2297 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2298 PMAP_LOCK(pv->pv_pmap); 2299 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2300 PTE_ISVALID(pte)) { 2301 if (PTE_ISMODIFIED(pte)) 2302 rv = TRUE; 2303 } 2304 PMAP_UNLOCK(pv->pv_pmap); 2305 if (rv) 2306 break; 2307 } 2308 rw_wunlock(&pvh_global_lock); 2309 return (rv); 2310 } 2311 2312 /* 2313 * Return whether or not the specified virtual address is eligible 2314 * for prefault. 2315 */ 2316 static boolean_t 2317 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2318 { 2319 2320 return (FALSE); 2321 } 2322 2323 /* 2324 * Return whether or not the specified physical page was referenced 2325 * in any physical maps. 2326 */ 2327 static boolean_t 2328 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2329 { 2330 pte_t *pte; 2331 pv_entry_t pv; 2332 boolean_t rv; 2333 2334 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2335 ("mmu_booke_is_referenced: page %p is not managed", m)); 2336 rv = FALSE; 2337 rw_wlock(&pvh_global_lock); 2338 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2339 PMAP_LOCK(pv->pv_pmap); 2340 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2341 PTE_ISVALID(pte)) { 2342 if (PTE_ISREFERENCED(pte)) 2343 rv = TRUE; 2344 } 2345 PMAP_UNLOCK(pv->pv_pmap); 2346 if (rv) 2347 break; 2348 } 2349 rw_wunlock(&pvh_global_lock); 2350 return (rv); 2351 } 2352 2353 /* 2354 * Clear the modify bits on the specified physical page. 2355 */ 2356 static void 2357 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2358 { 2359 pte_t *pte; 2360 pv_entry_t pv; 2361 2362 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2363 ("mmu_booke_clear_modify: page %p is not managed", m)); 2364 VM_OBJECT_ASSERT_WLOCKED(m->object); 2365 KASSERT(!vm_page_xbusied(m), 2366 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2367 2368 /* 2369 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2370 * If the object containing the page is locked and the page is not 2371 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2372 */ 2373 if ((m->aflags & PGA_WRITEABLE) == 0) 2374 return; 2375 rw_wlock(&pvh_global_lock); 2376 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2377 PMAP_LOCK(pv->pv_pmap); 2378 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2379 PTE_ISVALID(pte)) { 2380 mtx_lock_spin(&tlbivax_mutex); 2381 tlb_miss_lock(); 2382 2383 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2384 tlb0_flush_entry(pv->pv_va); 2385 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2386 PTE_REFERENCED); 2387 } 2388 2389 tlb_miss_unlock(); 2390 mtx_unlock_spin(&tlbivax_mutex); 2391 } 2392 PMAP_UNLOCK(pv->pv_pmap); 2393 } 2394 rw_wunlock(&pvh_global_lock); 2395 } 2396 2397 /* 2398 * Return a count of reference bits for a page, clearing those bits. 2399 * It is not necessary for every reference bit to be cleared, but it 2400 * is necessary that 0 only be returned when there are truly no 2401 * reference bits set. 2402 * 2403 * XXX: The exact number of bits to check and clear is a matter that 2404 * should be tested and standardized at some point in the future for 2405 * optimal aging of shared pages. 2406 */ 2407 static int 2408 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2409 { 2410 pte_t *pte; 2411 pv_entry_t pv; 2412 int count; 2413 2414 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2415 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2416 count = 0; 2417 rw_wlock(&pvh_global_lock); 2418 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2419 PMAP_LOCK(pv->pv_pmap); 2420 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2421 PTE_ISVALID(pte)) { 2422 if (PTE_ISREFERENCED(pte)) { 2423 mtx_lock_spin(&tlbivax_mutex); 2424 tlb_miss_lock(); 2425 2426 tlb0_flush_entry(pv->pv_va); 2427 pte->flags &= ~PTE_REFERENCED; 2428 2429 tlb_miss_unlock(); 2430 mtx_unlock_spin(&tlbivax_mutex); 2431 2432 if (++count > 4) { 2433 PMAP_UNLOCK(pv->pv_pmap); 2434 break; 2435 } 2436 } 2437 } 2438 PMAP_UNLOCK(pv->pv_pmap); 2439 } 2440 rw_wunlock(&pvh_global_lock); 2441 return (count); 2442 } 2443 2444 /* 2445 * Clear the wired attribute from the mappings for the specified range of 2446 * addresses in the given pmap. Every valid mapping within that range must 2447 * have the wired attribute set. In contrast, invalid mappings cannot have 2448 * the wired attribute set, so they are ignored. 2449 * 2450 * The wired attribute of the page table entry is not a hardware feature, so 2451 * there is no need to invalidate any TLB entries. 2452 */ 2453 static void 2454 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2455 { 2456 vm_offset_t va; 2457 pte_t *pte; 2458 2459 PMAP_LOCK(pmap); 2460 for (va = sva; va < eva; va += PAGE_SIZE) { 2461 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2462 PTE_ISVALID(pte)) { 2463 if (!PTE_ISWIRED(pte)) 2464 panic("mmu_booke_unwire: pte %p isn't wired", 2465 pte); 2466 pte->flags &= ~PTE_WIRED; 2467 pmap->pm_stats.wired_count--; 2468 } 2469 } 2470 PMAP_UNLOCK(pmap); 2471 2472 } 2473 2474 /* 2475 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2476 * page. This count may be changed upwards or downwards in the future; it is 2477 * only necessary that true be returned for a small subset of pmaps for proper 2478 * page aging. 2479 */ 2480 static boolean_t 2481 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2482 { 2483 pv_entry_t pv; 2484 int loops; 2485 boolean_t rv; 2486 2487 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2488 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2489 loops = 0; 2490 rv = FALSE; 2491 rw_wlock(&pvh_global_lock); 2492 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2493 if (pv->pv_pmap == pmap) { 2494 rv = TRUE; 2495 break; 2496 } 2497 if (++loops >= 16) 2498 break; 2499 } 2500 rw_wunlock(&pvh_global_lock); 2501 return (rv); 2502 } 2503 2504 /* 2505 * Return the number of managed mappings to the given physical page that are 2506 * wired. 2507 */ 2508 static int 2509 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2510 { 2511 pv_entry_t pv; 2512 pte_t *pte; 2513 int count = 0; 2514 2515 if ((m->oflags & VPO_UNMANAGED) != 0) 2516 return (count); 2517 rw_wlock(&pvh_global_lock); 2518 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2519 PMAP_LOCK(pv->pv_pmap); 2520 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2521 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2522 count++; 2523 PMAP_UNLOCK(pv->pv_pmap); 2524 } 2525 rw_wunlock(&pvh_global_lock); 2526 return (count); 2527 } 2528 2529 static int 2530 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2531 { 2532 int i; 2533 vm_offset_t va; 2534 2535 /* 2536 * This currently does not work for entries that 2537 * overlap TLB1 entries. 2538 */ 2539 for (i = 0; i < tlb1_idx; i ++) { 2540 if (tlb1_iomapped(i, pa, size, &va) == 0) 2541 return (0); 2542 } 2543 2544 return (EFAULT); 2545 } 2546 2547 void 2548 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2549 { 2550 vm_paddr_t ppa; 2551 vm_offset_t ofs; 2552 vm_size_t gran; 2553 2554 /* Minidumps are based on virtual memory addresses. */ 2555 if (do_minidump) { 2556 *va = (void *)pa; 2557 return; 2558 } 2559 2560 /* Raw physical memory dumps don't have a virtual address. */ 2561 /* We always map a 256MB page at 256M. */ 2562 gran = 256 * 1024 * 1024; 2563 ppa = pa & ~(gran - 1); 2564 ofs = pa - ppa; 2565 *va = (void *)gran; 2566 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2567 2568 if (sz > (gran - ofs)) 2569 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2570 _TLB_ENTRY_IO); 2571 } 2572 2573 void 2574 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2575 { 2576 vm_paddr_t ppa; 2577 vm_offset_t ofs; 2578 vm_size_t gran; 2579 2580 /* Minidumps are based on virtual memory addresses. */ 2581 /* Nothing to do... */ 2582 if (do_minidump) 2583 return; 2584 2585 /* Raw physical memory dumps don't have a virtual address. */ 2586 tlb1_idx--; 2587 tlb1[tlb1_idx].mas1 = 0; 2588 tlb1[tlb1_idx].mas2 = 0; 2589 tlb1[tlb1_idx].mas3 = 0; 2590 tlb1_write_entry(tlb1_idx); 2591 2592 gran = 256 * 1024 * 1024; 2593 ppa = pa & ~(gran - 1); 2594 ofs = pa - ppa; 2595 if (sz > (gran - ofs)) { 2596 tlb1_idx--; 2597 tlb1[tlb1_idx].mas1 = 0; 2598 tlb1[tlb1_idx].mas2 = 0; 2599 tlb1[tlb1_idx].mas3 = 0; 2600 tlb1_write_entry(tlb1_idx); 2601 } 2602 } 2603 2604 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2605 2606 void 2607 mmu_booke_scan_init(mmu_t mmu) 2608 { 2609 vm_offset_t va; 2610 pte_t *pte; 2611 int i; 2612 2613 if (!do_minidump) { 2614 /* Initialize phys. segments for dumpsys(). */ 2615 memset(&dump_map, 0, sizeof(dump_map)); 2616 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2617 &availmem_regions_sz); 2618 for (i = 0; i < physmem_regions_sz; i++) { 2619 dump_map[i].pa_start = physmem_regions[i].mr_start; 2620 dump_map[i].pa_size = physmem_regions[i].mr_size; 2621 } 2622 return; 2623 } 2624 2625 /* Virtual segments for minidumps: */ 2626 memset(&dump_map, 0, sizeof(dump_map)); 2627 2628 /* 1st: kernel .data and .bss. */ 2629 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2630 dump_map[0].pa_size = 2631 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2632 2633 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2634 dump_map[1].pa_start = data_start; 2635 dump_map[1].pa_size = data_end - data_start; 2636 2637 /* 3rd: kernel VM. */ 2638 va = dump_map[1].pa_start + dump_map[1].pa_size; 2639 /* Find start of next chunk (from va). */ 2640 while (va < virtual_end) { 2641 /* Don't dump the buffer cache. */ 2642 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2643 va = kmi.buffer_eva; 2644 continue; 2645 } 2646 pte = pte_find(mmu, kernel_pmap, va); 2647 if (pte != NULL && PTE_ISVALID(pte)) 2648 break; 2649 va += PAGE_SIZE; 2650 } 2651 if (va < virtual_end) { 2652 dump_map[2].pa_start = va; 2653 va += PAGE_SIZE; 2654 /* Find last page in chunk. */ 2655 while (va < virtual_end) { 2656 /* Don't run into the buffer cache. */ 2657 if (va == kmi.buffer_sva) 2658 break; 2659 pte = pte_find(mmu, kernel_pmap, va); 2660 if (pte == NULL || !PTE_ISVALID(pte)) 2661 break; 2662 va += PAGE_SIZE; 2663 } 2664 dump_map[2].pa_size = va - dump_map[2].pa_start; 2665 } 2666 } 2667 2668 /* 2669 * Map a set of physical memory pages into the kernel virtual address space. 2670 * Return a pointer to where it is mapped. This routine is intended to be used 2671 * for mapping device memory, NOT real memory. 2672 */ 2673 static void * 2674 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2675 { 2676 2677 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2678 } 2679 2680 static void * 2681 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2682 { 2683 void *res; 2684 uintptr_t va; 2685 vm_size_t sz; 2686 int i; 2687 2688 /* 2689 * Check if this is premapped in TLB1. Note: this should probably also 2690 * check whether a sequence of TLB1 entries exist that match the 2691 * requirement, but now only checks the easy case. 2692 */ 2693 if (ma == VM_MEMATTR_DEFAULT) { 2694 for (i = 0; i < tlb1_idx; i++) { 2695 if (!(tlb1[i].mas1 & MAS1_VALID)) 2696 continue; 2697 if (pa >= tlb1[i].phys && 2698 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2699 return (void *)(tlb1[i].virt + 2700 (pa - tlb1[i].phys)); 2701 } 2702 } 2703 2704 size = roundup(size, PAGE_SIZE); 2705 2706 /* 2707 * We leave a hole for device direct mapping between the maximum user 2708 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2709 * devices are in there, just map them 1:1. If not, map them to the 2710 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2711 * addresses should be pulled from an allocator, but since we do not 2712 * ever free TLB1 entries, it is safe just to increment a counter. 2713 * Note that there isn't a lot of address space here (128 MB) and it 2714 * is not at all difficult to imagine running out, since that is a 4:1 2715 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2716 * mapped there. 2717 */ 2718 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2719 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2720 va = pa; 2721 else 2722 va = atomic_fetchadd_int(&tlb1_map_base, size); 2723 res = (void *)va; 2724 2725 do { 2726 sz = 1 << (ilog2(size) & ~1); 2727 if (bootverbose) 2728 printf("Wiring VA=%x to PA=%x (size=%x), " 2729 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2730 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2731 size -= sz; 2732 pa += sz; 2733 va += sz; 2734 } while (size > 0); 2735 2736 return (res); 2737 } 2738 2739 /* 2740 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2741 */ 2742 static void 2743 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2744 { 2745 #ifdef SUPPORTS_SHRINKING_TLB1 2746 vm_offset_t base, offset; 2747 2748 /* 2749 * Unmap only if this is inside kernel virtual space. 2750 */ 2751 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2752 base = trunc_page(va); 2753 offset = va & PAGE_MASK; 2754 size = roundup(offset + size, PAGE_SIZE); 2755 kva_free(base, size); 2756 } 2757 #endif 2758 } 2759 2760 /* 2761 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2762 * specified pmap. This eliminates the blast of soft faults on process startup 2763 * and immediately after an mmap. 2764 */ 2765 static void 2766 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2767 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2768 { 2769 2770 VM_OBJECT_ASSERT_WLOCKED(object); 2771 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2772 ("mmu_booke_object_init_pt: non-device object")); 2773 } 2774 2775 /* 2776 * Perform the pmap work for mincore. 2777 */ 2778 static int 2779 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2780 vm_paddr_t *locked_pa) 2781 { 2782 2783 /* XXX: this should be implemented at some point */ 2784 return (0); 2785 } 2786 2787 /**************************************************************************/ 2788 /* TID handling */ 2789 /**************************************************************************/ 2790 2791 /* 2792 * Allocate a TID. If necessary, steal one from someone else. 2793 * The new TID is flushed from the TLB before returning. 2794 */ 2795 static tlbtid_t 2796 tid_alloc(pmap_t pmap) 2797 { 2798 tlbtid_t tid; 2799 int thiscpu; 2800 2801 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2802 2803 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2804 2805 thiscpu = PCPU_GET(cpuid); 2806 2807 tid = PCPU_GET(tid_next); 2808 if (tid > TID_MAX) 2809 tid = TID_MIN; 2810 PCPU_SET(tid_next, tid + 1); 2811 2812 /* If we are stealing TID then clear the relevant pmap's field */ 2813 if (tidbusy[thiscpu][tid] != NULL) { 2814 2815 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2816 2817 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2818 2819 /* Flush all entries from TLB0 matching this TID. */ 2820 tid_flush(tid, tlb0_ways, tlb0_entries_per_way); 2821 } 2822 2823 tidbusy[thiscpu][tid] = pmap; 2824 pmap->pm_tid[thiscpu] = tid; 2825 __asm __volatile("msync; isync"); 2826 2827 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2828 PCPU_GET(tid_next)); 2829 2830 return (tid); 2831 } 2832 2833 /**************************************************************************/ 2834 /* TLB0 handling */ 2835 /**************************************************************************/ 2836 2837 static void 2838 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2839 uint32_t mas7) 2840 { 2841 int as; 2842 char desc[3]; 2843 tlbtid_t tid; 2844 vm_size_t size; 2845 unsigned int tsize; 2846 2847 desc[2] = '\0'; 2848 if (mas1 & MAS1_VALID) 2849 desc[0] = 'V'; 2850 else 2851 desc[0] = ' '; 2852 2853 if (mas1 & MAS1_IPROT) 2854 desc[1] = 'P'; 2855 else 2856 desc[1] = ' '; 2857 2858 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2859 tid = MAS1_GETTID(mas1); 2860 2861 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2862 size = 0; 2863 if (tsize) 2864 size = tsize2size(tsize); 2865 2866 debugf("%3d: (%s) [AS=%d] " 2867 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2868 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2869 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2870 } 2871 2872 /* Convert TLB0 va and way number to tlb0[] table index. */ 2873 static inline unsigned int 2874 tlb0_tableidx(vm_offset_t va, unsigned int way) 2875 { 2876 unsigned int idx; 2877 2878 idx = (way * TLB0_ENTRIES_PER_WAY); 2879 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2880 return (idx); 2881 } 2882 2883 /* 2884 * Invalidate TLB0 entry. 2885 */ 2886 static inline void 2887 tlb0_flush_entry(vm_offset_t va) 2888 { 2889 2890 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2891 2892 mtx_assert(&tlbivax_mutex, MA_OWNED); 2893 2894 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2895 __asm __volatile("isync; msync"); 2896 __asm __volatile("tlbsync; msync"); 2897 2898 CTR1(KTR_PMAP, "%s: e", __func__); 2899 } 2900 2901 /* Print out contents of the MAS registers for each TLB0 entry */ 2902 void 2903 tlb0_print_tlbentries(void) 2904 { 2905 uint32_t mas0, mas1, mas2, mas3, mas7; 2906 int entryidx, way, idx; 2907 2908 debugf("TLB0 entries:\n"); 2909 for (way = 0; way < TLB0_WAYS; way ++) 2910 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2911 2912 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2913 mtspr(SPR_MAS0, mas0); 2914 __asm __volatile("isync"); 2915 2916 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2917 mtspr(SPR_MAS2, mas2); 2918 2919 __asm __volatile("isync; tlbre"); 2920 2921 mas1 = mfspr(SPR_MAS1); 2922 mas2 = mfspr(SPR_MAS2); 2923 mas3 = mfspr(SPR_MAS3); 2924 mas7 = mfspr(SPR_MAS7); 2925 2926 idx = tlb0_tableidx(mas2, way); 2927 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2928 } 2929 } 2930 2931 /**************************************************************************/ 2932 /* TLB1 handling */ 2933 /**************************************************************************/ 2934 2935 /* 2936 * TLB1 mapping notes: 2937 * 2938 * TLB1[0] Kernel text and data. 2939 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 2940 * windows, other devices mappings. 2941 */ 2942 2943 /* 2944 * Write given entry to TLB1 hardware. 2945 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2946 */ 2947 static void 2948 tlb1_write_entry(unsigned int idx) 2949 { 2950 uint32_t mas0, mas7; 2951 2952 //debugf("tlb1_write_entry: s\n"); 2953 2954 /* Clear high order RPN bits */ 2955 mas7 = 0; 2956 2957 /* Select entry */ 2958 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2959 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2960 2961 mtspr(SPR_MAS0, mas0); 2962 __asm __volatile("isync"); 2963 mtspr(SPR_MAS1, tlb1[idx].mas1); 2964 __asm __volatile("isync"); 2965 mtspr(SPR_MAS2, tlb1[idx].mas2); 2966 __asm __volatile("isync"); 2967 mtspr(SPR_MAS3, tlb1[idx].mas3); 2968 __asm __volatile("isync"); 2969 mtspr(SPR_MAS7, mas7); 2970 __asm __volatile("isync; tlbwe; isync; msync"); 2971 2972 //debugf("tlb1_write_entry: e\n"); 2973 } 2974 2975 /* 2976 * Return the largest uint value log such that 2^log <= num. 2977 */ 2978 static unsigned int 2979 ilog2(unsigned int num) 2980 { 2981 int lz; 2982 2983 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2984 return (31 - lz); 2985 } 2986 2987 /* 2988 * Convert TLB TSIZE value to mapped region size. 2989 */ 2990 static vm_size_t 2991 tsize2size(unsigned int tsize) 2992 { 2993 2994 /* 2995 * size = 4^tsize KB 2996 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2997 */ 2998 2999 return ((1 << (2 * tsize)) * 1024); 3000 } 3001 3002 /* 3003 * Convert region size (must be power of 4) to TLB TSIZE value. 3004 */ 3005 static unsigned int 3006 size2tsize(vm_size_t size) 3007 { 3008 3009 return (ilog2(size) / 2 - 5); 3010 } 3011 3012 /* 3013 * Register permanent kernel mapping in TLB1. 3014 * 3015 * Entries are created starting from index 0 (current free entry is 3016 * kept in tlb1_idx) and are not supposed to be invalidated. 3017 */ 3018 static int 3019 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 3020 uint32_t flags) 3021 { 3022 uint32_t ts, tid; 3023 int tsize, index; 3024 3025 index = atomic_fetchadd_int(&tlb1_idx, 1); 3026 if (index >= TLB1_ENTRIES) { 3027 printf("tlb1_set_entry: TLB1 full!\n"); 3028 return (-1); 3029 } 3030 3031 /* Convert size to TSIZE */ 3032 tsize = size2tsize(size); 3033 3034 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3035 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3036 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3037 3038 /* 3039 * Atomicity is preserved by the atomic increment above since nothing 3040 * is ever removed from tlb1. 3041 */ 3042 3043 tlb1[index].phys = pa; 3044 tlb1[index].virt = va; 3045 tlb1[index].size = size; 3046 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3047 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3048 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3049 3050 /* Set supervisor RWX permission bits */ 3051 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3052 3053 tlb1_write_entry(index); 3054 3055 /* 3056 * XXX in general TLB1 updates should be propagated between CPUs, 3057 * since current design assumes to have the same TLB1 set-up on all 3058 * cores. 3059 */ 3060 return (0); 3061 } 3062 3063 /* 3064 * Map in contiguous RAM region into the TLB1 using maximum of 3065 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3066 * 3067 * If necessary round up last entry size and return total size 3068 * used by all allocated entries. 3069 */ 3070 vm_size_t 3071 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3072 { 3073 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3074 vm_size_t mapped, pgsz, base, mask; 3075 int idx, nents; 3076 3077 /* Round up to the next 1M */ 3078 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3079 3080 mapped = 0; 3081 idx = 0; 3082 base = va; 3083 pgsz = 64*1024*1024; 3084 while (mapped < size) { 3085 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3086 while (pgsz > (size - mapped)) 3087 pgsz >>= 2; 3088 pgs[idx++] = pgsz; 3089 mapped += pgsz; 3090 } 3091 3092 /* We under-map. Correct for this. */ 3093 if (mapped < size) { 3094 while (pgs[idx - 1] == pgsz) { 3095 idx--; 3096 mapped -= pgsz; 3097 } 3098 /* XXX We may increase beyond out starting point. */ 3099 pgsz <<= 2; 3100 pgs[idx++] = pgsz; 3101 mapped += pgsz; 3102 } 3103 } 3104 3105 nents = idx; 3106 mask = pgs[0] - 1; 3107 /* Align address to the boundary */ 3108 if (va & mask) { 3109 va = (va + mask) & ~mask; 3110 pa = (pa + mask) & ~mask; 3111 } 3112 3113 for (idx = 0; idx < nents; idx++) { 3114 pgsz = pgs[idx]; 3115 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3116 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3117 pa += pgsz; 3118 va += pgsz; 3119 } 3120 3121 mapped = (va - base); 3122 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3123 mapped, mapped - size); 3124 return (mapped); 3125 } 3126 3127 /* 3128 * TLB1 initialization routine, to be called after the very first 3129 * assembler level setup done in locore.S. 3130 */ 3131 void 3132 tlb1_init() 3133 { 3134 uint32_t mas0, mas1, mas2, mas3; 3135 uint32_t tsz; 3136 u_int i; 3137 3138 if (bootinfo != NULL && bootinfo[0] != 1) { 3139 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3140 } else 3141 tlb1_idx = 1; 3142 3143 /* The first entry/entries are used to map the kernel. */ 3144 for (i = 0; i < tlb1_idx; i++) { 3145 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3146 mtspr(SPR_MAS0, mas0); 3147 __asm __volatile("isync; tlbre"); 3148 3149 mas1 = mfspr(SPR_MAS1); 3150 if ((mas1 & MAS1_VALID) == 0) 3151 continue; 3152 3153 mas2 = mfspr(SPR_MAS2); 3154 mas3 = mfspr(SPR_MAS3); 3155 3156 tlb1[i].mas1 = mas1; 3157 tlb1[i].mas2 = mfspr(SPR_MAS2); 3158 tlb1[i].mas3 = mas3; 3159 tlb1[i].virt = mas2 & MAS2_EPN_MASK; 3160 tlb1[i].phys = mas3 & MAS3_RPN; 3161 3162 if (i == 0) 3163 kernload = mas3 & MAS3_RPN; 3164 3165 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3166 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0; 3167 kernsize += tlb1[i].size; 3168 } 3169 3170 #ifdef SMP 3171 bp_ntlb1s = tlb1_idx; 3172 #endif 3173 3174 /* Purge the remaining entries */ 3175 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3176 tlb1_write_entry(i); 3177 3178 /* Setup TLB miss defaults */ 3179 set_mas4_defaults(); 3180 } 3181 3182 vm_offset_t 3183 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3184 { 3185 vm_paddr_t pa_base; 3186 vm_offset_t va, sz; 3187 int i; 3188 3189 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3190 3191 for (i = 0; i < tlb1_idx; i++) { 3192 if (!(tlb1[i].mas1 & MAS1_VALID)) 3193 continue; 3194 if (pa >= tlb1[i].phys && (pa + size) <= 3195 (tlb1[i].phys + tlb1[i].size)) 3196 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3197 } 3198 3199 pa_base = trunc_page(pa); 3200 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3201 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3202 va = tlb1_map_base + (pa - pa_base); 3203 3204 do { 3205 sz = 1 << (ilog2(size) & ~1); 3206 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3207 size -= sz; 3208 pa_base += sz; 3209 tlb1_map_base += sz; 3210 } while (size > 0); 3211 3212 #ifdef SMP 3213 bp_ntlb1s = tlb1_idx; 3214 #endif 3215 3216 return (va); 3217 } 3218 3219 /* 3220 * Setup MAS4 defaults. 3221 * These values are loaded to MAS0-2 on a TLB miss. 3222 */ 3223 static void 3224 set_mas4_defaults(void) 3225 { 3226 uint32_t mas4; 3227 3228 /* Defaults: TLB0, PID0, TSIZED=4K */ 3229 mas4 = MAS4_TLBSELD0; 3230 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3231 #ifdef SMP 3232 mas4 |= MAS4_MD; 3233 #endif 3234 mtspr(SPR_MAS4, mas4); 3235 __asm __volatile("isync"); 3236 } 3237 3238 /* 3239 * Print out contents of the MAS registers for each TLB1 entry 3240 */ 3241 void 3242 tlb1_print_tlbentries(void) 3243 { 3244 uint32_t mas0, mas1, mas2, mas3, mas7; 3245 int i; 3246 3247 debugf("TLB1 entries:\n"); 3248 for (i = 0; i < TLB1_ENTRIES; i++) { 3249 3250 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3251 mtspr(SPR_MAS0, mas0); 3252 3253 __asm __volatile("isync; tlbre"); 3254 3255 mas1 = mfspr(SPR_MAS1); 3256 mas2 = mfspr(SPR_MAS2); 3257 mas3 = mfspr(SPR_MAS3); 3258 mas7 = mfspr(SPR_MAS7); 3259 3260 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3261 } 3262 } 3263 3264 /* 3265 * Print out contents of the in-ram tlb1 table. 3266 */ 3267 void 3268 tlb1_print_entries(void) 3269 { 3270 int i; 3271 3272 debugf("tlb1[] table entries:\n"); 3273 for (i = 0; i < TLB1_ENTRIES; i++) 3274 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3275 } 3276 3277 /* 3278 * Return 0 if the physical IO range is encompassed by one of the 3279 * the TLB1 entries, otherwise return related error code. 3280 */ 3281 static int 3282 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3283 { 3284 uint32_t prot; 3285 vm_paddr_t pa_start; 3286 vm_paddr_t pa_end; 3287 unsigned int entry_tsize; 3288 vm_size_t entry_size; 3289 3290 *va = (vm_offset_t)NULL; 3291 3292 /* Skip invalid entries */ 3293 if (!(tlb1[i].mas1 & MAS1_VALID)) 3294 return (EINVAL); 3295 3296 /* 3297 * The entry must be cache-inhibited, guarded, and r/w 3298 * so it can function as an i/o page 3299 */ 3300 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3301 if (prot != (MAS2_I | MAS2_G)) 3302 return (EPERM); 3303 3304 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3305 if (prot != (MAS3_SR | MAS3_SW)) 3306 return (EPERM); 3307 3308 /* The address should be within the entry range. */ 3309 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3310 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3311 3312 entry_size = tsize2size(entry_tsize); 3313 pa_start = tlb1[i].mas3 & MAS3_RPN; 3314 pa_end = pa_start + entry_size - 1; 3315 3316 if ((pa < pa_start) || ((pa + size) > pa_end)) 3317 return (ERANGE); 3318 3319 /* Return virtual address of this mapping. */ 3320 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3321 return (0); 3322 } 3323