1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #ifdef DEBUG 100 #define debugf(fmt, args...) printf(fmt, ##args) 101 #else 102 #define debugf(fmt, args...) 103 #endif 104 105 #define TODO panic("%s: not implemented", __func__); 106 107 extern unsigned char _etext[]; 108 extern unsigned char _end[]; 109 110 extern uint32_t *bootinfo; 111 112 #ifdef SMP 113 extern uint32_t bp_ntlb1s; 114 #endif 115 116 vm_paddr_t kernload; 117 vm_offset_t kernstart; 118 vm_size_t kernsize; 119 120 /* Message buffer and tables. */ 121 static vm_offset_t data_start; 122 static vm_size_t data_end; 123 124 /* Phys/avail memory regions. */ 125 static struct mem_region *availmem_regions; 126 static int availmem_regions_sz; 127 static struct mem_region *physmem_regions; 128 static int physmem_regions_sz; 129 130 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 131 static vm_offset_t zero_page_va; 132 static struct mtx zero_page_mutex; 133 134 static struct mtx tlbivax_mutex; 135 136 /* 137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 138 * by idle thred only, no lock required. 139 */ 140 static vm_offset_t zero_page_idle_va; 141 142 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 143 static vm_offset_t copy_page_src_va; 144 static vm_offset_t copy_page_dst_va; 145 static struct mtx copy_page_mutex; 146 147 /**************************************************************************/ 148 /* PMAP */ 149 /**************************************************************************/ 150 151 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 152 vm_prot_t, u_int flags, int8_t psind); 153 154 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 155 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 156 157 /* 158 * If user pmap is processed with mmu_booke_remove and the resident count 159 * drops to 0, there are no more pages to remove, so we need not continue. 160 */ 161 #define PMAP_REMOVE_DONE(pmap) \ 162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 163 164 extern int elf32_nxstack; 165 166 /**************************************************************************/ 167 /* TLB and TID handling */ 168 /**************************************************************************/ 169 170 /* Translation ID busy table */ 171 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 172 173 /* 174 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 175 * core revisions and should be read from h/w registers during early config. 176 */ 177 uint32_t tlb0_entries; 178 uint32_t tlb0_ways; 179 uint32_t tlb0_entries_per_way; 180 uint32_t tlb1_entries; 181 182 #define TLB0_ENTRIES (tlb0_entries) 183 #define TLB0_WAYS (tlb0_ways) 184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186 #define TLB1_ENTRIES (tlb1_entries) 187 #define TLB1_MAXENTRIES 64 188 189 /* In-ram copy of the TLB1 */ 190 static tlb_entry_t tlb1[TLB1_MAXENTRIES]; 191 192 /* Next free entry in the TLB1 */ 193 static unsigned int tlb1_idx; 194 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS; 195 196 static tlbtid_t tid_alloc(struct pmap *); 197 static void tid_flush(tlbtid_t tid); 198 199 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 200 201 static int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t); 202 static void tlb1_write_entry(unsigned int); 203 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 204 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 205 206 static vm_size_t tsize2size(unsigned int); 207 static unsigned int size2tsize(vm_size_t); 208 static unsigned int ilog2(unsigned int); 209 210 static void set_mas4_defaults(void); 211 212 static inline void tlb0_flush_entry(vm_offset_t); 213 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 214 215 /**************************************************************************/ 216 /* Page table management */ 217 /**************************************************************************/ 218 219 static struct rwlock_padalign pvh_global_lock; 220 221 /* Data for the pv entry allocation mechanism */ 222 static uma_zone_t pvzone; 223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227 #ifndef PMAP_SHPGPERPROC 228 #define PMAP_SHPGPERPROC 200 229 #endif 230 231 static void ptbl_init(void); 232 static struct ptbl_buf *ptbl_buf_alloc(void); 233 static void ptbl_buf_free(struct ptbl_buf *); 234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 237 static void ptbl_free(mmu_t, pmap_t, unsigned int); 238 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 245 static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, 246 vm_offset_t pdir); 247 248 static pv_entry_t pv_alloc(void); 249 static void pv_free(pv_entry_t); 250 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 251 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 252 253 static void booke_pmap_init_qpages(void); 254 255 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 256 #define PTBL_BUFS (128 * 16) 257 258 struct ptbl_buf { 259 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 260 vm_offset_t kva; /* va of mapping */ 261 }; 262 263 /* ptbl free list and a lock used for access synchronization. */ 264 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 265 static struct mtx ptbl_buf_freelist_lock; 266 267 /* Base address of kva space allocated fot ptbl bufs. */ 268 static vm_offset_t ptbl_buf_pool_vabase; 269 270 /* Pointer to ptbl_buf structures. */ 271 static struct ptbl_buf *ptbl_bufs; 272 273 #ifdef SMP 274 void pmap_bootstrap_ap(volatile uint32_t *); 275 #endif 276 277 /* 278 * Kernel MMU interface 279 */ 280 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 281 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 282 vm_size_t, vm_offset_t); 283 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 284 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 285 vm_offset_t, vm_page_t *, vm_offset_t, int); 286 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 287 vm_prot_t, u_int flags, int8_t psind); 288 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 289 vm_page_t, vm_prot_t); 290 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 291 vm_prot_t); 292 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 293 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 294 vm_prot_t); 295 static void mmu_booke_init(mmu_t); 296 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 297 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 298 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 299 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 300 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 301 int); 302 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 303 vm_paddr_t *); 304 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 305 vm_object_t, vm_pindex_t, vm_size_t); 306 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 307 static void mmu_booke_page_init(mmu_t, vm_page_t); 308 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 309 static void mmu_booke_pinit(mmu_t, pmap_t); 310 static void mmu_booke_pinit0(mmu_t, pmap_t); 311 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 312 vm_prot_t); 313 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 314 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 315 static void mmu_booke_release(mmu_t, pmap_t); 316 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 317 static void mmu_booke_remove_all(mmu_t, vm_page_t); 318 static void mmu_booke_remove_write(mmu_t, vm_page_t); 319 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 320 static void mmu_booke_zero_page(mmu_t, vm_page_t); 321 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 322 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 323 static void mmu_booke_activate(mmu_t, struct thread *); 324 static void mmu_booke_deactivate(mmu_t, struct thread *); 325 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 326 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 327 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 328 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 329 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 330 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 331 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 332 static void mmu_booke_kremove(mmu_t, vm_offset_t); 333 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 334 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 335 vm_size_t); 336 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 337 void **); 338 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 339 void *); 340 static void mmu_booke_scan_init(mmu_t); 341 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 342 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 343 344 static mmu_method_t mmu_booke_methods[] = { 345 /* pmap dispatcher interface */ 346 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 347 MMUMETHOD(mmu_copy, mmu_booke_copy), 348 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 349 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 350 MMUMETHOD(mmu_enter, mmu_booke_enter), 351 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 352 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 353 MMUMETHOD(mmu_extract, mmu_booke_extract), 354 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 355 MMUMETHOD(mmu_init, mmu_booke_init), 356 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 357 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 358 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 359 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 360 MMUMETHOD(mmu_map, mmu_booke_map), 361 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 362 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 363 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 364 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 365 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 366 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 367 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 368 MMUMETHOD(mmu_protect, mmu_booke_protect), 369 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 370 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 371 MMUMETHOD(mmu_release, mmu_booke_release), 372 MMUMETHOD(mmu_remove, mmu_booke_remove), 373 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 374 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 375 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 376 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 377 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 378 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 379 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 380 MMUMETHOD(mmu_activate, mmu_booke_activate), 381 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 382 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 383 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 384 385 /* Internal interfaces */ 386 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 387 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 388 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 389 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 390 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 391 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 392 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 393 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 394 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 395 396 /* dumpsys() support */ 397 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 398 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 399 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 400 401 { 0, 0 } 402 }; 403 404 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 405 406 static __inline uint32_t 407 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 408 { 409 uint32_t attrib; 410 int i; 411 412 if (ma != VM_MEMATTR_DEFAULT) { 413 switch (ma) { 414 case VM_MEMATTR_UNCACHEABLE: 415 return (MAS2_I | MAS2_G); 416 case VM_MEMATTR_WRITE_COMBINING: 417 case VM_MEMATTR_WRITE_BACK: 418 case VM_MEMATTR_PREFETCHABLE: 419 return (MAS2_I); 420 case VM_MEMATTR_WRITE_THROUGH: 421 return (MAS2_W | MAS2_M); 422 } 423 } 424 425 /* 426 * Assume the page is cache inhibited and access is guarded unless 427 * it's in our available memory array. 428 */ 429 attrib = _TLB_ENTRY_IO; 430 for (i = 0; i < physmem_regions_sz; i++) { 431 if ((pa >= physmem_regions[i].mr_start) && 432 (pa < (physmem_regions[i].mr_start + 433 physmem_regions[i].mr_size))) { 434 attrib = _TLB_ENTRY_MEM; 435 break; 436 } 437 } 438 439 return (attrib); 440 } 441 442 static inline void 443 tlb_miss_lock(void) 444 { 445 #ifdef SMP 446 struct pcpu *pc; 447 448 if (!smp_started) 449 return; 450 451 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 452 if (pc != pcpup) { 453 454 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 455 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 456 457 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 458 ("tlb_miss_lock: tried to lock self")); 459 460 tlb_lock(pc->pc_booke_tlb_lock); 461 462 CTR1(KTR_PMAP, "%s: locked", __func__); 463 } 464 } 465 #endif 466 } 467 468 static inline void 469 tlb_miss_unlock(void) 470 { 471 #ifdef SMP 472 struct pcpu *pc; 473 474 if (!smp_started) 475 return; 476 477 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 478 if (pc != pcpup) { 479 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 480 __func__, pc->pc_cpuid); 481 482 tlb_unlock(pc->pc_booke_tlb_lock); 483 484 CTR1(KTR_PMAP, "%s: unlocked", __func__); 485 } 486 } 487 #endif 488 } 489 490 /* Return number of entries in TLB0. */ 491 static __inline void 492 tlb0_get_tlbconf(void) 493 { 494 uint32_t tlb0_cfg; 495 496 tlb0_cfg = mfspr(SPR_TLB0CFG); 497 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 498 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 499 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 500 } 501 502 /* Return number of entries in TLB1. */ 503 static __inline void 504 tlb1_get_tlbconf(void) 505 { 506 uint32_t tlb1_cfg; 507 508 tlb1_cfg = mfspr(SPR_TLB1CFG); 509 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 510 } 511 512 /**************************************************************************/ 513 /* Page table related */ 514 /**************************************************************************/ 515 516 /* Initialize pool of kva ptbl buffers. */ 517 static void 518 ptbl_init(void) 519 { 520 int i; 521 522 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 523 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 524 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 525 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 526 527 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 528 TAILQ_INIT(&ptbl_buf_freelist); 529 530 for (i = 0; i < PTBL_BUFS; i++) { 531 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 532 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 533 } 534 } 535 536 /* Get a ptbl_buf from the freelist. */ 537 static struct ptbl_buf * 538 ptbl_buf_alloc(void) 539 { 540 struct ptbl_buf *buf; 541 542 mtx_lock(&ptbl_buf_freelist_lock); 543 buf = TAILQ_FIRST(&ptbl_buf_freelist); 544 if (buf != NULL) 545 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 546 mtx_unlock(&ptbl_buf_freelist_lock); 547 548 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 549 550 return (buf); 551 } 552 553 /* Return ptbl buff to free pool. */ 554 static void 555 ptbl_buf_free(struct ptbl_buf *buf) 556 { 557 558 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 559 560 mtx_lock(&ptbl_buf_freelist_lock); 561 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 562 mtx_unlock(&ptbl_buf_freelist_lock); 563 } 564 565 /* 566 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 567 */ 568 static void 569 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 570 { 571 struct ptbl_buf *pbuf; 572 573 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 574 575 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 576 577 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 578 if (pbuf->kva == (vm_offset_t)ptbl) { 579 /* Remove from pmap ptbl buf list. */ 580 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 581 582 /* Free corresponding ptbl buf. */ 583 ptbl_buf_free(pbuf); 584 break; 585 } 586 } 587 588 /* Allocate page table. */ 589 static pte_t * 590 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 591 { 592 vm_page_t mtbl[PTBL_PAGES]; 593 vm_page_t m; 594 struct ptbl_buf *pbuf; 595 unsigned int pidx; 596 pte_t *ptbl; 597 int i, j; 598 599 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 600 (pmap == kernel_pmap), pdir_idx); 601 602 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 603 ("ptbl_alloc: invalid pdir_idx")); 604 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 605 ("pte_alloc: valid ptbl entry exists!")); 606 607 pbuf = ptbl_buf_alloc(); 608 if (pbuf == NULL) 609 panic("pte_alloc: couldn't alloc kernel virtual memory"); 610 611 ptbl = (pte_t *)pbuf->kva; 612 613 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 614 615 /* Allocate ptbl pages, this will sleep! */ 616 for (i = 0; i < PTBL_PAGES; i++) { 617 pidx = (PTBL_PAGES * pdir_idx) + i; 618 while ((m = vm_page_alloc(NULL, pidx, 619 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 620 PMAP_UNLOCK(pmap); 621 rw_wunlock(&pvh_global_lock); 622 if (nosleep) { 623 ptbl_free_pmap_ptbl(pmap, ptbl); 624 for (j = 0; j < i; j++) 625 vm_page_free(mtbl[j]); 626 atomic_subtract_int(&vm_cnt.v_wire_count, i); 627 return (NULL); 628 } 629 VM_WAIT; 630 rw_wlock(&pvh_global_lock); 631 PMAP_LOCK(pmap); 632 } 633 mtbl[i] = m; 634 } 635 636 /* Map allocated pages into kernel_pmap. */ 637 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 638 639 /* Zero whole ptbl. */ 640 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 641 642 /* Add pbuf to the pmap ptbl bufs list. */ 643 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 644 645 return (ptbl); 646 } 647 648 /* Free ptbl pages and invalidate pdir entry. */ 649 static void 650 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 651 { 652 pte_t *ptbl; 653 vm_paddr_t pa; 654 vm_offset_t va; 655 vm_page_t m; 656 int i; 657 658 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 659 (pmap == kernel_pmap), pdir_idx); 660 661 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 662 ("ptbl_free: invalid pdir_idx")); 663 664 ptbl = pmap->pm_pdir[pdir_idx]; 665 666 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 667 668 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 669 670 /* 671 * Invalidate the pdir entry as soon as possible, so that other CPUs 672 * don't attempt to look up the page tables we are releasing. 673 */ 674 mtx_lock_spin(&tlbivax_mutex); 675 tlb_miss_lock(); 676 677 pmap->pm_pdir[pdir_idx] = NULL; 678 679 tlb_miss_unlock(); 680 mtx_unlock_spin(&tlbivax_mutex); 681 682 for (i = 0; i < PTBL_PAGES; i++) { 683 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 684 pa = pte_vatopa(mmu, kernel_pmap, va); 685 m = PHYS_TO_VM_PAGE(pa); 686 vm_page_free_zero(m); 687 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 688 mmu_booke_kremove(mmu, va); 689 } 690 691 ptbl_free_pmap_ptbl(pmap, ptbl); 692 } 693 694 /* 695 * Decrement ptbl pages hold count and attempt to free ptbl pages. 696 * Called when removing pte entry from ptbl. 697 * 698 * Return 1 if ptbl pages were freed. 699 */ 700 static int 701 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 702 { 703 pte_t *ptbl; 704 vm_paddr_t pa; 705 vm_page_t m; 706 int i; 707 708 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 709 (pmap == kernel_pmap), pdir_idx); 710 711 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 712 ("ptbl_unhold: invalid pdir_idx")); 713 KASSERT((pmap != kernel_pmap), 714 ("ptbl_unhold: unholding kernel ptbl!")); 715 716 ptbl = pmap->pm_pdir[pdir_idx]; 717 718 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 719 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 720 ("ptbl_unhold: non kva ptbl")); 721 722 /* decrement hold count */ 723 for (i = 0; i < PTBL_PAGES; i++) { 724 pa = pte_vatopa(mmu, kernel_pmap, 725 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 726 m = PHYS_TO_VM_PAGE(pa); 727 m->wire_count--; 728 } 729 730 /* 731 * Free ptbl pages if there are no pte etries in this ptbl. 732 * wire_count has the same value for all ptbl pages, so check the last 733 * page. 734 */ 735 if (m->wire_count == 0) { 736 ptbl_free(mmu, pmap, pdir_idx); 737 738 //debugf("ptbl_unhold: e (freed ptbl)\n"); 739 return (1); 740 } 741 742 return (0); 743 } 744 745 /* 746 * Increment hold count for ptbl pages. This routine is used when a new pte 747 * entry is being inserted into the ptbl. 748 */ 749 static void 750 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 751 { 752 vm_paddr_t pa; 753 pte_t *ptbl; 754 vm_page_t m; 755 int i; 756 757 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 758 pdir_idx); 759 760 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 761 ("ptbl_hold: invalid pdir_idx")); 762 KASSERT((pmap != kernel_pmap), 763 ("ptbl_hold: holding kernel ptbl!")); 764 765 ptbl = pmap->pm_pdir[pdir_idx]; 766 767 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 768 769 for (i = 0; i < PTBL_PAGES; i++) { 770 pa = pte_vatopa(mmu, kernel_pmap, 771 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 772 m = PHYS_TO_VM_PAGE(pa); 773 m->wire_count++; 774 } 775 } 776 777 /* Allocate pv_entry structure. */ 778 pv_entry_t 779 pv_alloc(void) 780 { 781 pv_entry_t pv; 782 783 pv_entry_count++; 784 if (pv_entry_count > pv_entry_high_water) 785 pagedaemon_wakeup(); 786 pv = uma_zalloc(pvzone, M_NOWAIT); 787 788 return (pv); 789 } 790 791 /* Free pv_entry structure. */ 792 static __inline void 793 pv_free(pv_entry_t pve) 794 { 795 796 pv_entry_count--; 797 uma_zfree(pvzone, pve); 798 } 799 800 801 /* Allocate and initialize pv_entry structure. */ 802 static void 803 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 804 { 805 pv_entry_t pve; 806 807 //int su = (pmap == kernel_pmap); 808 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 809 // (u_int32_t)pmap, va, (u_int32_t)m); 810 811 pve = pv_alloc(); 812 if (pve == NULL) 813 panic("pv_insert: no pv entries!"); 814 815 pve->pv_pmap = pmap; 816 pve->pv_va = va; 817 818 /* add to pv_list */ 819 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 820 rw_assert(&pvh_global_lock, RA_WLOCKED); 821 822 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 823 824 //debugf("pv_insert: e\n"); 825 } 826 827 /* Destroy pv entry. */ 828 static void 829 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 830 { 831 pv_entry_t pve; 832 833 //int su = (pmap == kernel_pmap); 834 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 835 836 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 837 rw_assert(&pvh_global_lock, RA_WLOCKED); 838 839 /* find pv entry */ 840 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 841 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 842 /* remove from pv_list */ 843 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 844 if (TAILQ_EMPTY(&m->md.pv_list)) 845 vm_page_aflag_clear(m, PGA_WRITEABLE); 846 847 /* free pv entry struct */ 848 pv_free(pve); 849 break; 850 } 851 } 852 853 //debugf("pv_remove: e\n"); 854 } 855 856 /* 857 * Clean pte entry, try to free page table page if requested. 858 * 859 * Return 1 if ptbl pages were freed, otherwise return 0. 860 */ 861 static int 862 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 863 { 864 unsigned int pdir_idx = PDIR_IDX(va); 865 unsigned int ptbl_idx = PTBL_IDX(va); 866 vm_page_t m; 867 pte_t *ptbl; 868 pte_t *pte; 869 870 //int su = (pmap == kernel_pmap); 871 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 872 // su, (u_int32_t)pmap, va, flags); 873 874 ptbl = pmap->pm_pdir[pdir_idx]; 875 KASSERT(ptbl, ("pte_remove: null ptbl")); 876 877 pte = &ptbl[ptbl_idx]; 878 879 if (pte == NULL || !PTE_ISVALID(pte)) 880 return (0); 881 882 if (PTE_ISWIRED(pte)) 883 pmap->pm_stats.wired_count--; 884 885 /* Handle managed entry. */ 886 if (PTE_ISMANAGED(pte)) { 887 /* Get vm_page_t for mapped pte. */ 888 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 889 890 if (PTE_ISMODIFIED(pte)) 891 vm_page_dirty(m); 892 893 if (PTE_ISREFERENCED(pte)) 894 vm_page_aflag_set(m, PGA_REFERENCED); 895 896 pv_remove(pmap, va, m); 897 } 898 899 mtx_lock_spin(&tlbivax_mutex); 900 tlb_miss_lock(); 901 902 tlb0_flush_entry(va); 903 *pte = 0; 904 905 tlb_miss_unlock(); 906 mtx_unlock_spin(&tlbivax_mutex); 907 908 pmap->pm_stats.resident_count--; 909 910 if (flags & PTBL_UNHOLD) { 911 //debugf("pte_remove: e (unhold)\n"); 912 return (ptbl_unhold(mmu, pmap, pdir_idx)); 913 } 914 915 //debugf("pte_remove: e\n"); 916 return (0); 917 } 918 919 /* 920 * Insert PTE for a given page and virtual address. 921 */ 922 static int 923 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 924 boolean_t nosleep) 925 { 926 unsigned int pdir_idx = PDIR_IDX(va); 927 unsigned int ptbl_idx = PTBL_IDX(va); 928 pte_t *ptbl, *pte; 929 930 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 931 pmap == kernel_pmap, pmap, va); 932 933 /* Get the page table pointer. */ 934 ptbl = pmap->pm_pdir[pdir_idx]; 935 936 if (ptbl == NULL) { 937 /* Allocate page table pages. */ 938 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 939 if (ptbl == NULL) { 940 KASSERT(nosleep, ("nosleep and NULL ptbl")); 941 return (ENOMEM); 942 } 943 } else { 944 /* 945 * Check if there is valid mapping for requested 946 * va, if there is, remove it. 947 */ 948 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 949 if (PTE_ISVALID(pte)) { 950 pte_remove(mmu, pmap, va, PTBL_HOLD); 951 } else { 952 /* 953 * pte is not used, increment hold count 954 * for ptbl pages. 955 */ 956 if (pmap != kernel_pmap) 957 ptbl_hold(mmu, pmap, pdir_idx); 958 } 959 } 960 961 /* 962 * Insert pv_entry into pv_list for mapped page if part of managed 963 * memory. 964 */ 965 if ((m->oflags & VPO_UNMANAGED) == 0) { 966 flags |= PTE_MANAGED; 967 968 /* Create and insert pv entry. */ 969 pv_insert(pmap, va, m); 970 } 971 972 pmap->pm_stats.resident_count++; 973 974 mtx_lock_spin(&tlbivax_mutex); 975 tlb_miss_lock(); 976 977 tlb0_flush_entry(va); 978 if (pmap->pm_pdir[pdir_idx] == NULL) { 979 /* 980 * If we just allocated a new page table, hook it in 981 * the pdir. 982 */ 983 pmap->pm_pdir[pdir_idx] = ptbl; 984 } 985 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 986 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 987 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 988 989 tlb_miss_unlock(); 990 mtx_unlock_spin(&tlbivax_mutex); 991 return (0); 992 } 993 994 /* Return the pa for the given pmap/va. */ 995 static vm_paddr_t 996 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 997 { 998 vm_paddr_t pa = 0; 999 pte_t *pte; 1000 1001 pte = pte_find(mmu, pmap, va); 1002 if ((pte != NULL) && PTE_ISVALID(pte)) 1003 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1004 return (pa); 1005 } 1006 1007 /* Get a pointer to a PTE in a page table. */ 1008 static pte_t * 1009 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1010 { 1011 unsigned int pdir_idx = PDIR_IDX(va); 1012 unsigned int ptbl_idx = PTBL_IDX(va); 1013 1014 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1015 1016 if (pmap->pm_pdir[pdir_idx]) 1017 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1018 1019 return (NULL); 1020 } 1021 1022 /* Set up kernel page tables. */ 1023 static void 1024 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1025 { 1026 int i; 1027 vm_offset_t va; 1028 pte_t *pte; 1029 1030 /* Initialize kernel pdir */ 1031 for (i = 0; i < kernel_ptbls; i++) 1032 kernel_pmap->pm_pdir[kptbl_min + i] = 1033 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1034 1035 /* 1036 * Fill in PTEs covering kernel code and data. They are not required 1037 * for address translation, as this area is covered by static TLB1 1038 * entries, but for pte_vatopa() to work correctly with kernel area 1039 * addresses. 1040 */ 1041 for (va = addr; va < data_end; va += PAGE_SIZE) { 1042 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1043 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1044 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1045 PTE_VALID | PTE_PS_4KB; 1046 } 1047 } 1048 1049 /**************************************************************************/ 1050 /* PMAP related */ 1051 /**************************************************************************/ 1052 1053 /* 1054 * This is called during booke_init, before the system is really initialized. 1055 */ 1056 static void 1057 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1058 { 1059 vm_paddr_t phys_kernelend; 1060 struct mem_region *mp, *mp1; 1061 int cnt, i, j; 1062 vm_paddr_t s, e, sz; 1063 vm_paddr_t physsz, hwphyssz; 1064 u_int phys_avail_count; 1065 vm_size_t kstack0_sz; 1066 vm_offset_t kernel_pdir, kstack0; 1067 vm_paddr_t kstack0_phys; 1068 void *dpcpu; 1069 1070 debugf("mmu_booke_bootstrap: entered\n"); 1071 1072 /* Set interesting system properties */ 1073 hw_direct_map = 0; 1074 elf32_nxstack = 1; 1075 1076 /* Initialize invalidation mutex */ 1077 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1078 1079 /* Read TLB0 size and associativity. */ 1080 tlb0_get_tlbconf(); 1081 1082 /* 1083 * Align kernel start and end address (kernel image). 1084 * Note that kernel end does not necessarily relate to kernsize. 1085 * kernsize is the size of the kernel that is actually mapped. 1086 */ 1087 kernstart = trunc_page(start); 1088 data_start = round_page(kernelend); 1089 data_end = data_start; 1090 1091 /* 1092 * Addresses of preloaded modules (like file systems) use 1093 * physical addresses. Make sure we relocate those into 1094 * virtual addresses. 1095 */ 1096 preload_addr_relocate = kernstart - kernload; 1097 1098 /* Allocate the dynamic per-cpu area. */ 1099 dpcpu = (void *)data_end; 1100 data_end += DPCPU_SIZE; 1101 1102 /* Allocate space for the message buffer. */ 1103 msgbufp = (struct msgbuf *)data_end; 1104 data_end += msgbufsize; 1105 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1106 data_end); 1107 1108 data_end = round_page(data_end); 1109 1110 /* Allocate space for ptbl_bufs. */ 1111 ptbl_bufs = (struct ptbl_buf *)data_end; 1112 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1113 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1114 data_end); 1115 1116 data_end = round_page(data_end); 1117 1118 /* Allocate PTE tables for kernel KVA. */ 1119 kernel_pdir = data_end; 1120 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1121 PDIR_SIZE - 1) / PDIR_SIZE; 1122 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1123 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1124 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1125 1126 debugf(" data_end: 0x%08x\n", data_end); 1127 if (data_end - kernstart > kernsize) { 1128 kernsize += tlb1_mapin_region(kernstart + kernsize, 1129 kernload + kernsize, (data_end - kernstart) - kernsize); 1130 } 1131 data_end = kernstart + kernsize; 1132 debugf(" updated data_end: 0x%08x\n", data_end); 1133 1134 /* 1135 * Clear the structures - note we can only do it safely after the 1136 * possible additional TLB1 translations are in place (above) so that 1137 * all range up to the currently calculated 'data_end' is covered. 1138 */ 1139 dpcpu_init(dpcpu, 0); 1140 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1141 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1142 1143 /*******************************************************/ 1144 /* Set the start and end of kva. */ 1145 /*******************************************************/ 1146 virtual_avail = round_page(data_end); 1147 virtual_end = VM_MAX_KERNEL_ADDRESS; 1148 1149 /* Allocate KVA space for page zero/copy operations. */ 1150 zero_page_va = virtual_avail; 1151 virtual_avail += PAGE_SIZE; 1152 zero_page_idle_va = virtual_avail; 1153 virtual_avail += PAGE_SIZE; 1154 copy_page_src_va = virtual_avail; 1155 virtual_avail += PAGE_SIZE; 1156 copy_page_dst_va = virtual_avail; 1157 virtual_avail += PAGE_SIZE; 1158 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1159 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1160 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1161 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1162 1163 /* Initialize page zero/copy mutexes. */ 1164 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1165 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1166 1167 /* Allocate KVA space for ptbl bufs. */ 1168 ptbl_buf_pool_vabase = virtual_avail; 1169 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1170 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1171 ptbl_buf_pool_vabase, virtual_avail); 1172 1173 /* Calculate corresponding physical addresses for the kernel region. */ 1174 phys_kernelend = kernload + kernsize; 1175 debugf("kernel image and allocated data:\n"); 1176 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1177 debugf(" kernstart = 0x%08x\n", kernstart); 1178 debugf(" kernsize = 0x%08x\n", kernsize); 1179 1180 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1181 panic("mmu_booke_bootstrap: phys_avail too small"); 1182 1183 /* 1184 * Remove kernel physical address range from avail regions list. Page 1185 * align all regions. Non-page aligned memory isn't very interesting 1186 * to us. Also, sort the entries for ascending addresses. 1187 */ 1188 1189 /* Retrieve phys/avail mem regions */ 1190 mem_regions(&physmem_regions, &physmem_regions_sz, 1191 &availmem_regions, &availmem_regions_sz); 1192 sz = 0; 1193 cnt = availmem_regions_sz; 1194 debugf("processing avail regions:\n"); 1195 for (mp = availmem_regions; mp->mr_size; mp++) { 1196 s = mp->mr_start; 1197 e = mp->mr_start + mp->mr_size; 1198 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1199 /* Check whether this region holds all of the kernel. */ 1200 if (s < kernload && e > phys_kernelend) { 1201 availmem_regions[cnt].mr_start = phys_kernelend; 1202 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1203 e = kernload; 1204 } 1205 /* Look whether this regions starts within the kernel. */ 1206 if (s >= kernload && s < phys_kernelend) { 1207 if (e <= phys_kernelend) 1208 goto empty; 1209 s = phys_kernelend; 1210 } 1211 /* Now look whether this region ends within the kernel. */ 1212 if (e > kernload && e <= phys_kernelend) { 1213 if (s >= kernload) 1214 goto empty; 1215 e = kernload; 1216 } 1217 /* Now page align the start and size of the region. */ 1218 s = round_page(s); 1219 e = trunc_page(e); 1220 if (e < s) 1221 e = s; 1222 sz = e - s; 1223 debugf("%09jx-%09jx = %jx\n", 1224 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1225 1226 /* Check whether some memory is left here. */ 1227 if (sz == 0) { 1228 empty: 1229 memmove(mp, mp + 1, 1230 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1231 cnt--; 1232 mp--; 1233 continue; 1234 } 1235 1236 /* Do an insertion sort. */ 1237 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1238 if (s < mp1->mr_start) 1239 break; 1240 if (mp1 < mp) { 1241 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1242 mp1->mr_start = s; 1243 mp1->mr_size = sz; 1244 } else { 1245 mp->mr_start = s; 1246 mp->mr_size = sz; 1247 } 1248 } 1249 availmem_regions_sz = cnt; 1250 1251 /*******************************************************/ 1252 /* Steal physical memory for kernel stack from the end */ 1253 /* of the first avail region */ 1254 /*******************************************************/ 1255 kstack0_sz = kstack_pages * PAGE_SIZE; 1256 kstack0_phys = availmem_regions[0].mr_start + 1257 availmem_regions[0].mr_size; 1258 kstack0_phys -= kstack0_sz; 1259 availmem_regions[0].mr_size -= kstack0_sz; 1260 1261 /*******************************************************/ 1262 /* Fill in phys_avail table, based on availmem_regions */ 1263 /*******************************************************/ 1264 phys_avail_count = 0; 1265 physsz = 0; 1266 hwphyssz = 0; 1267 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1268 1269 debugf("fill in phys_avail:\n"); 1270 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1271 1272 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1273 (uintmax_t)availmem_regions[i].mr_start, 1274 (uintmax_t)availmem_regions[i].mr_start + 1275 availmem_regions[i].mr_size, 1276 (uintmax_t)availmem_regions[i].mr_size); 1277 1278 if (hwphyssz != 0 && 1279 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1280 debugf(" hw.physmem adjust\n"); 1281 if (physsz < hwphyssz) { 1282 phys_avail[j] = availmem_regions[i].mr_start; 1283 phys_avail[j + 1] = 1284 availmem_regions[i].mr_start + 1285 hwphyssz - physsz; 1286 physsz = hwphyssz; 1287 phys_avail_count++; 1288 } 1289 break; 1290 } 1291 1292 phys_avail[j] = availmem_regions[i].mr_start; 1293 phys_avail[j + 1] = availmem_regions[i].mr_start + 1294 availmem_regions[i].mr_size; 1295 phys_avail_count++; 1296 physsz += availmem_regions[i].mr_size; 1297 } 1298 physmem = btoc(physsz); 1299 1300 /* Calculate the last available physical address. */ 1301 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1302 ; 1303 Maxmem = powerpc_btop(phys_avail[i + 1]); 1304 1305 debugf("Maxmem = 0x%08lx\n", Maxmem); 1306 debugf("phys_avail_count = %d\n", phys_avail_count); 1307 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1308 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1309 1310 /*******************************************************/ 1311 /* Initialize (statically allocated) kernel pmap. */ 1312 /*******************************************************/ 1313 PMAP_LOCK_INIT(kernel_pmap); 1314 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1315 1316 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1317 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1318 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1319 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1320 1321 kernel_pte_alloc(data_end, kernstart, kernel_pdir); 1322 for (i = 0; i < MAXCPU; i++) { 1323 kernel_pmap->pm_tid[i] = TID_KERNEL; 1324 1325 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1326 tidbusy[i][TID_KERNEL] = kernel_pmap; 1327 } 1328 1329 /* Mark kernel_pmap active on all CPUs */ 1330 CPU_FILL(&kernel_pmap->pm_active); 1331 1332 /* 1333 * Initialize the global pv list lock. 1334 */ 1335 rw_init(&pvh_global_lock, "pmap pv global"); 1336 1337 /*******************************************************/ 1338 /* Final setup */ 1339 /*******************************************************/ 1340 1341 /* Enter kstack0 into kernel map, provide guard page */ 1342 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1343 thread0.td_kstack = kstack0; 1344 thread0.td_kstack_pages = kstack_pages; 1345 1346 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1347 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1348 kstack0_phys, kstack0_phys + kstack0_sz); 1349 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1350 1351 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1352 for (i = 0; i < kstack_pages; i++) { 1353 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1354 kstack0 += PAGE_SIZE; 1355 kstack0_phys += PAGE_SIZE; 1356 } 1357 1358 pmap_bootstrapped = 1; 1359 1360 debugf("virtual_avail = %08x\n", virtual_avail); 1361 debugf("virtual_end = %08x\n", virtual_end); 1362 1363 debugf("mmu_booke_bootstrap: exit\n"); 1364 } 1365 1366 #ifdef SMP 1367 void 1368 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1369 { 1370 int i; 1371 1372 /* 1373 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1374 * have the snapshot of its contents in the s/w tlb1[] table, so use 1375 * these values directly to (re)program AP's TLB1 hardware. 1376 */ 1377 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1378 /* Skip invalid entries */ 1379 if (!(tlb1[i].mas1 & MAS1_VALID)) 1380 continue; 1381 1382 tlb1_write_entry(i); 1383 } 1384 1385 set_mas4_defaults(); 1386 } 1387 #endif 1388 1389 static void 1390 booke_pmap_init_qpages(void) 1391 { 1392 struct pcpu *pc; 1393 int i; 1394 1395 CPU_FOREACH(i) { 1396 pc = pcpu_find(i); 1397 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1398 if (pc->pc_qmap_addr == 0) 1399 panic("pmap_init_qpages: unable to allocate KVA"); 1400 } 1401 } 1402 1403 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1404 1405 /* 1406 * Get the physical page address for the given pmap/virtual address. 1407 */ 1408 static vm_paddr_t 1409 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1410 { 1411 vm_paddr_t pa; 1412 1413 PMAP_LOCK(pmap); 1414 pa = pte_vatopa(mmu, pmap, va); 1415 PMAP_UNLOCK(pmap); 1416 1417 return (pa); 1418 } 1419 1420 /* 1421 * Extract the physical page address associated with the given 1422 * kernel virtual address. 1423 */ 1424 static vm_paddr_t 1425 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1426 { 1427 int i; 1428 1429 /* Check TLB1 mappings */ 1430 for (i = 0; i < tlb1_idx; i++) { 1431 if (!(tlb1[i].mas1 & MAS1_VALID)) 1432 continue; 1433 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size) 1434 return (tlb1[i].phys + (va - tlb1[i].virt)); 1435 } 1436 1437 return (pte_vatopa(mmu, kernel_pmap, va)); 1438 } 1439 1440 /* 1441 * Initialize the pmap module. 1442 * Called by vm_init, to initialize any structures that the pmap 1443 * system needs to map virtual memory. 1444 */ 1445 static void 1446 mmu_booke_init(mmu_t mmu) 1447 { 1448 int shpgperproc = PMAP_SHPGPERPROC; 1449 1450 /* 1451 * Initialize the address space (zone) for the pv entries. Set a 1452 * high water mark so that the system can recover from excessive 1453 * numbers of pv entries. 1454 */ 1455 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1456 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1457 1458 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1459 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1460 1461 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1462 pv_entry_high_water = 9 * (pv_entry_max / 10); 1463 1464 uma_zone_reserve_kva(pvzone, pv_entry_max); 1465 1466 /* Pre-fill pvzone with initial number of pv entries. */ 1467 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1468 1469 /* Initialize ptbl allocation. */ 1470 ptbl_init(); 1471 } 1472 1473 /* 1474 * Map a list of wired pages into kernel virtual address space. This is 1475 * intended for temporary mappings which do not need page modification or 1476 * references recorded. Existing mappings in the region are overwritten. 1477 */ 1478 static void 1479 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1480 { 1481 vm_offset_t va; 1482 1483 va = sva; 1484 while (count-- > 0) { 1485 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1486 va += PAGE_SIZE; 1487 m++; 1488 } 1489 } 1490 1491 /* 1492 * Remove page mappings from kernel virtual address space. Intended for 1493 * temporary mappings entered by mmu_booke_qenter. 1494 */ 1495 static void 1496 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1497 { 1498 vm_offset_t va; 1499 1500 va = sva; 1501 while (count-- > 0) { 1502 mmu_booke_kremove(mmu, va); 1503 va += PAGE_SIZE; 1504 } 1505 } 1506 1507 /* 1508 * Map a wired page into kernel virtual address space. 1509 */ 1510 static void 1511 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1512 { 1513 1514 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1515 } 1516 1517 static void 1518 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1519 { 1520 uint32_t flags; 1521 pte_t *pte; 1522 1523 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1524 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1525 1526 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1527 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1528 flags |= PTE_PS_4KB; 1529 1530 pte = pte_find(mmu, kernel_pmap, va); 1531 1532 mtx_lock_spin(&tlbivax_mutex); 1533 tlb_miss_lock(); 1534 1535 if (PTE_ISVALID(pte)) { 1536 1537 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1538 1539 /* Flush entry from TLB0 */ 1540 tlb0_flush_entry(va); 1541 } 1542 1543 *pte = PTE_RPN_FROM_PA(pa) | flags; 1544 1545 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1546 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1547 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1548 1549 /* Flush the real memory from the instruction cache. */ 1550 if ((flags & (PTE_I | PTE_G)) == 0) 1551 __syncicache((void *)va, PAGE_SIZE); 1552 1553 tlb_miss_unlock(); 1554 mtx_unlock_spin(&tlbivax_mutex); 1555 } 1556 1557 /* 1558 * Remove a page from kernel page table. 1559 */ 1560 static void 1561 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1562 { 1563 pte_t *pte; 1564 1565 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 1566 1567 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1568 (va <= VM_MAX_KERNEL_ADDRESS)), 1569 ("mmu_booke_kremove: invalid va")); 1570 1571 pte = pte_find(mmu, kernel_pmap, va); 1572 1573 if (!PTE_ISVALID(pte)) { 1574 1575 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1576 1577 return; 1578 } 1579 1580 mtx_lock_spin(&tlbivax_mutex); 1581 tlb_miss_lock(); 1582 1583 /* Invalidate entry in TLB0, update PTE. */ 1584 tlb0_flush_entry(va); 1585 *pte = 0; 1586 1587 tlb_miss_unlock(); 1588 mtx_unlock_spin(&tlbivax_mutex); 1589 } 1590 1591 /* 1592 * Initialize pmap associated with process 0. 1593 */ 1594 static void 1595 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1596 { 1597 1598 PMAP_LOCK_INIT(pmap); 1599 mmu_booke_pinit(mmu, pmap); 1600 PCPU_SET(curpmap, pmap); 1601 } 1602 1603 /* 1604 * Initialize a preallocated and zeroed pmap structure, 1605 * such as one in a vmspace structure. 1606 */ 1607 static void 1608 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1609 { 1610 int i; 1611 1612 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1613 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1614 1615 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1616 1617 for (i = 0; i < MAXCPU; i++) 1618 pmap->pm_tid[i] = TID_NONE; 1619 CPU_ZERO(&kernel_pmap->pm_active); 1620 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1621 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1622 TAILQ_INIT(&pmap->pm_ptbl_list); 1623 } 1624 1625 /* 1626 * Release any resources held by the given physical map. 1627 * Called when a pmap initialized by mmu_booke_pinit is being released. 1628 * Should only be called if the map contains no valid mappings. 1629 */ 1630 static void 1631 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1632 { 1633 1634 KASSERT(pmap->pm_stats.resident_count == 0, 1635 ("pmap_release: pmap resident count %ld != 0", 1636 pmap->pm_stats.resident_count)); 1637 } 1638 1639 /* 1640 * Insert the given physical page at the specified virtual address in the 1641 * target physical map with the protection requested. If specified the page 1642 * will be wired down. 1643 */ 1644 static int 1645 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1646 vm_prot_t prot, u_int flags, int8_t psind) 1647 { 1648 int error; 1649 1650 rw_wlock(&pvh_global_lock); 1651 PMAP_LOCK(pmap); 1652 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1653 rw_wunlock(&pvh_global_lock); 1654 PMAP_UNLOCK(pmap); 1655 return (error); 1656 } 1657 1658 static int 1659 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1660 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1661 { 1662 pte_t *pte; 1663 vm_paddr_t pa; 1664 uint32_t flags; 1665 int error, su, sync; 1666 1667 pa = VM_PAGE_TO_PHYS(m); 1668 su = (pmap == kernel_pmap); 1669 sync = 0; 1670 1671 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1672 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1673 // (u_int32_t)pmap, su, pmap->pm_tid, 1674 // (u_int32_t)m, va, pa, prot, flags); 1675 1676 if (su) { 1677 KASSERT(((va >= virtual_avail) && 1678 (va <= VM_MAX_KERNEL_ADDRESS)), 1679 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1680 } else { 1681 KASSERT((va <= VM_MAXUSER_ADDRESS), 1682 ("mmu_booke_enter_locked: user pmap, non user va")); 1683 } 1684 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1685 VM_OBJECT_ASSERT_LOCKED(m->object); 1686 1687 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1688 1689 /* 1690 * If there is an existing mapping, and the physical address has not 1691 * changed, must be protection or wiring change. 1692 */ 1693 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1694 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1695 1696 /* 1697 * Before actually updating pte->flags we calculate and 1698 * prepare its new value in a helper var. 1699 */ 1700 flags = *pte; 1701 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1702 1703 /* Wiring change, just update stats. */ 1704 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1705 if (!PTE_ISWIRED(pte)) { 1706 flags |= PTE_WIRED; 1707 pmap->pm_stats.wired_count++; 1708 } 1709 } else { 1710 if (PTE_ISWIRED(pte)) { 1711 flags &= ~PTE_WIRED; 1712 pmap->pm_stats.wired_count--; 1713 } 1714 } 1715 1716 if (prot & VM_PROT_WRITE) { 1717 /* Add write permissions. */ 1718 flags |= PTE_SW; 1719 if (!su) 1720 flags |= PTE_UW; 1721 1722 if ((flags & PTE_MANAGED) != 0) 1723 vm_page_aflag_set(m, PGA_WRITEABLE); 1724 } else { 1725 /* Handle modified pages, sense modify status. */ 1726 1727 /* 1728 * The PTE_MODIFIED flag could be set by underlying 1729 * TLB misses since we last read it (above), possibly 1730 * other CPUs could update it so we check in the PTE 1731 * directly rather than rely on that saved local flags 1732 * copy. 1733 */ 1734 if (PTE_ISMODIFIED(pte)) 1735 vm_page_dirty(m); 1736 } 1737 1738 if (prot & VM_PROT_EXECUTE) { 1739 flags |= PTE_SX; 1740 if (!su) 1741 flags |= PTE_UX; 1742 1743 /* 1744 * Check existing flags for execute permissions: if we 1745 * are turning execute permissions on, icache should 1746 * be flushed. 1747 */ 1748 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1749 sync++; 1750 } 1751 1752 flags &= ~PTE_REFERENCED; 1753 1754 /* 1755 * The new flags value is all calculated -- only now actually 1756 * update the PTE. 1757 */ 1758 mtx_lock_spin(&tlbivax_mutex); 1759 tlb_miss_lock(); 1760 1761 tlb0_flush_entry(va); 1762 *pte &= ~PTE_FLAGS_MASK; 1763 *pte |= flags; 1764 1765 tlb_miss_unlock(); 1766 mtx_unlock_spin(&tlbivax_mutex); 1767 1768 } else { 1769 /* 1770 * If there is an existing mapping, but it's for a different 1771 * physical address, pte_enter() will delete the old mapping. 1772 */ 1773 //if ((pte != NULL) && PTE_ISVALID(pte)) 1774 // debugf("mmu_booke_enter_locked: replace\n"); 1775 //else 1776 // debugf("mmu_booke_enter_locked: new\n"); 1777 1778 /* Now set up the flags and install the new mapping. */ 1779 flags = (PTE_SR | PTE_VALID); 1780 flags |= PTE_M; 1781 1782 if (!su) 1783 flags |= PTE_UR; 1784 1785 if (prot & VM_PROT_WRITE) { 1786 flags |= PTE_SW; 1787 if (!su) 1788 flags |= PTE_UW; 1789 1790 if ((m->oflags & VPO_UNMANAGED) == 0) 1791 vm_page_aflag_set(m, PGA_WRITEABLE); 1792 } 1793 1794 if (prot & VM_PROT_EXECUTE) { 1795 flags |= PTE_SX; 1796 if (!su) 1797 flags |= PTE_UX; 1798 } 1799 1800 /* If its wired update stats. */ 1801 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1802 flags |= PTE_WIRED; 1803 1804 error = pte_enter(mmu, pmap, m, va, flags, 1805 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1806 if (error != 0) 1807 return (KERN_RESOURCE_SHORTAGE); 1808 1809 if ((flags & PMAP_ENTER_WIRED) != 0) 1810 pmap->pm_stats.wired_count++; 1811 1812 /* Flush the real memory from the instruction cache. */ 1813 if (prot & VM_PROT_EXECUTE) 1814 sync++; 1815 } 1816 1817 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1818 __syncicache((void *)va, PAGE_SIZE); 1819 sync = 0; 1820 } 1821 1822 return (KERN_SUCCESS); 1823 } 1824 1825 /* 1826 * Maps a sequence of resident pages belonging to the same object. 1827 * The sequence begins with the given page m_start. This page is 1828 * mapped at the given virtual address start. Each subsequent page is 1829 * mapped at a virtual address that is offset from start by the same 1830 * amount as the page is offset from m_start within the object. The 1831 * last page in the sequence is the page with the largest offset from 1832 * m_start that can be mapped at a virtual address less than the given 1833 * virtual address end. Not every virtual page between start and end 1834 * is mapped; only those for which a resident page exists with the 1835 * corresponding offset from m_start are mapped. 1836 */ 1837 static void 1838 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1839 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1840 { 1841 vm_page_t m; 1842 vm_pindex_t diff, psize; 1843 1844 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1845 1846 psize = atop(end - start); 1847 m = m_start; 1848 rw_wlock(&pvh_global_lock); 1849 PMAP_LOCK(pmap); 1850 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1851 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1852 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1853 PMAP_ENTER_NOSLEEP, 0); 1854 m = TAILQ_NEXT(m, listq); 1855 } 1856 rw_wunlock(&pvh_global_lock); 1857 PMAP_UNLOCK(pmap); 1858 } 1859 1860 static void 1861 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1862 vm_prot_t prot) 1863 { 1864 1865 rw_wlock(&pvh_global_lock); 1866 PMAP_LOCK(pmap); 1867 mmu_booke_enter_locked(mmu, pmap, va, m, 1868 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1869 0); 1870 rw_wunlock(&pvh_global_lock); 1871 PMAP_UNLOCK(pmap); 1872 } 1873 1874 /* 1875 * Remove the given range of addresses from the specified map. 1876 * 1877 * It is assumed that the start and end are properly rounded to the page size. 1878 */ 1879 static void 1880 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1881 { 1882 pte_t *pte; 1883 uint8_t hold_flag; 1884 1885 int su = (pmap == kernel_pmap); 1886 1887 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1888 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1889 1890 if (su) { 1891 KASSERT(((va >= virtual_avail) && 1892 (va <= VM_MAX_KERNEL_ADDRESS)), 1893 ("mmu_booke_remove: kernel pmap, non kernel va")); 1894 } else { 1895 KASSERT((va <= VM_MAXUSER_ADDRESS), 1896 ("mmu_booke_remove: user pmap, non user va")); 1897 } 1898 1899 if (PMAP_REMOVE_DONE(pmap)) { 1900 //debugf("mmu_booke_remove: e (empty)\n"); 1901 return; 1902 } 1903 1904 hold_flag = PTBL_HOLD_FLAG(pmap); 1905 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1906 1907 rw_wlock(&pvh_global_lock); 1908 PMAP_LOCK(pmap); 1909 for (; va < endva; va += PAGE_SIZE) { 1910 pte = pte_find(mmu, pmap, va); 1911 if ((pte != NULL) && PTE_ISVALID(pte)) 1912 pte_remove(mmu, pmap, va, hold_flag); 1913 } 1914 PMAP_UNLOCK(pmap); 1915 rw_wunlock(&pvh_global_lock); 1916 1917 //debugf("mmu_booke_remove: e\n"); 1918 } 1919 1920 /* 1921 * Remove physical page from all pmaps in which it resides. 1922 */ 1923 static void 1924 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1925 { 1926 pv_entry_t pv, pvn; 1927 uint8_t hold_flag; 1928 1929 rw_wlock(&pvh_global_lock); 1930 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1931 pvn = TAILQ_NEXT(pv, pv_link); 1932 1933 PMAP_LOCK(pv->pv_pmap); 1934 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1935 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1936 PMAP_UNLOCK(pv->pv_pmap); 1937 } 1938 vm_page_aflag_clear(m, PGA_WRITEABLE); 1939 rw_wunlock(&pvh_global_lock); 1940 } 1941 1942 /* 1943 * Map a range of physical addresses into kernel virtual address space. 1944 */ 1945 static vm_offset_t 1946 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1947 vm_paddr_t pa_end, int prot) 1948 { 1949 vm_offset_t sva = *virt; 1950 vm_offset_t va = sva; 1951 1952 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1953 // sva, pa_start, pa_end); 1954 1955 while (pa_start < pa_end) { 1956 mmu_booke_kenter(mmu, va, pa_start); 1957 va += PAGE_SIZE; 1958 pa_start += PAGE_SIZE; 1959 } 1960 *virt = va; 1961 1962 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1963 return (sva); 1964 } 1965 1966 /* 1967 * The pmap must be activated before it's address space can be accessed in any 1968 * way. 1969 */ 1970 static void 1971 mmu_booke_activate(mmu_t mmu, struct thread *td) 1972 { 1973 pmap_t pmap; 1974 u_int cpuid; 1975 1976 pmap = &td->td_proc->p_vmspace->vm_pmap; 1977 1978 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1979 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1980 1981 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1982 1983 sched_pin(); 1984 1985 cpuid = PCPU_GET(cpuid); 1986 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1987 PCPU_SET(curpmap, pmap); 1988 1989 if (pmap->pm_tid[cpuid] == TID_NONE) 1990 tid_alloc(pmap); 1991 1992 /* Load PID0 register with pmap tid value. */ 1993 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1994 __asm __volatile("isync"); 1995 1996 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 1997 1998 sched_unpin(); 1999 2000 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2001 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2002 } 2003 2004 /* 2005 * Deactivate the specified process's address space. 2006 */ 2007 static void 2008 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2009 { 2010 pmap_t pmap; 2011 2012 pmap = &td->td_proc->p_vmspace->vm_pmap; 2013 2014 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2015 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2016 2017 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2018 2019 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2020 PCPU_SET(curpmap, NULL); 2021 } 2022 2023 /* 2024 * Copy the range specified by src_addr/len 2025 * from the source map to the range dst_addr/len 2026 * in the destination map. 2027 * 2028 * This routine is only advisory and need not do anything. 2029 */ 2030 static void 2031 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2032 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2033 { 2034 2035 } 2036 2037 /* 2038 * Set the physical protection on the specified range of this map as requested. 2039 */ 2040 static void 2041 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2042 vm_prot_t prot) 2043 { 2044 vm_offset_t va; 2045 vm_page_t m; 2046 pte_t *pte; 2047 2048 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2049 mmu_booke_remove(mmu, pmap, sva, eva); 2050 return; 2051 } 2052 2053 if (prot & VM_PROT_WRITE) 2054 return; 2055 2056 PMAP_LOCK(pmap); 2057 for (va = sva; va < eva; va += PAGE_SIZE) { 2058 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2059 if (PTE_ISVALID(pte)) { 2060 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2061 2062 mtx_lock_spin(&tlbivax_mutex); 2063 tlb_miss_lock(); 2064 2065 /* Handle modified pages. */ 2066 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2067 vm_page_dirty(m); 2068 2069 tlb0_flush_entry(va); 2070 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2071 2072 tlb_miss_unlock(); 2073 mtx_unlock_spin(&tlbivax_mutex); 2074 } 2075 } 2076 } 2077 PMAP_UNLOCK(pmap); 2078 } 2079 2080 /* 2081 * Clear the write and modified bits in each of the given page's mappings. 2082 */ 2083 static void 2084 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2085 { 2086 pv_entry_t pv; 2087 pte_t *pte; 2088 2089 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2090 ("mmu_booke_remove_write: page %p is not managed", m)); 2091 2092 /* 2093 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2094 * set by another thread while the object is locked. Thus, 2095 * if PGA_WRITEABLE is clear, no page table entries need updating. 2096 */ 2097 VM_OBJECT_ASSERT_WLOCKED(m->object); 2098 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2099 return; 2100 rw_wlock(&pvh_global_lock); 2101 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2102 PMAP_LOCK(pv->pv_pmap); 2103 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2104 if (PTE_ISVALID(pte)) { 2105 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2106 2107 mtx_lock_spin(&tlbivax_mutex); 2108 tlb_miss_lock(); 2109 2110 /* Handle modified pages. */ 2111 if (PTE_ISMODIFIED(pte)) 2112 vm_page_dirty(m); 2113 2114 /* Flush mapping from TLB0. */ 2115 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2116 2117 tlb_miss_unlock(); 2118 mtx_unlock_spin(&tlbivax_mutex); 2119 } 2120 } 2121 PMAP_UNLOCK(pv->pv_pmap); 2122 } 2123 vm_page_aflag_clear(m, PGA_WRITEABLE); 2124 rw_wunlock(&pvh_global_lock); 2125 } 2126 2127 static void 2128 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2129 { 2130 pte_t *pte; 2131 pmap_t pmap; 2132 vm_page_t m; 2133 vm_offset_t addr; 2134 vm_paddr_t pa = 0; 2135 int active, valid; 2136 2137 va = trunc_page(va); 2138 sz = round_page(sz); 2139 2140 rw_wlock(&pvh_global_lock); 2141 pmap = PCPU_GET(curpmap); 2142 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2143 while (sz > 0) { 2144 PMAP_LOCK(pm); 2145 pte = pte_find(mmu, pm, va); 2146 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2147 if (valid) 2148 pa = PTE_PA(pte); 2149 PMAP_UNLOCK(pm); 2150 if (valid) { 2151 if (!active) { 2152 /* Create a mapping in the active pmap. */ 2153 addr = 0; 2154 m = PHYS_TO_VM_PAGE(pa); 2155 PMAP_LOCK(pmap); 2156 pte_enter(mmu, pmap, m, addr, 2157 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2158 __syncicache((void *)addr, PAGE_SIZE); 2159 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2160 PMAP_UNLOCK(pmap); 2161 } else 2162 __syncicache((void *)va, PAGE_SIZE); 2163 } 2164 va += PAGE_SIZE; 2165 sz -= PAGE_SIZE; 2166 } 2167 rw_wunlock(&pvh_global_lock); 2168 } 2169 2170 /* 2171 * Atomically extract and hold the physical page with the given 2172 * pmap and virtual address pair if that mapping permits the given 2173 * protection. 2174 */ 2175 static vm_page_t 2176 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2177 vm_prot_t prot) 2178 { 2179 pte_t *pte; 2180 vm_page_t m; 2181 uint32_t pte_wbit; 2182 vm_paddr_t pa; 2183 2184 m = NULL; 2185 pa = 0; 2186 PMAP_LOCK(pmap); 2187 retry: 2188 pte = pte_find(mmu, pmap, va); 2189 if ((pte != NULL) && PTE_ISVALID(pte)) { 2190 if (pmap == kernel_pmap) 2191 pte_wbit = PTE_SW; 2192 else 2193 pte_wbit = PTE_UW; 2194 2195 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2196 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2197 goto retry; 2198 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2199 vm_page_hold(m); 2200 } 2201 } 2202 2203 PA_UNLOCK_COND(pa); 2204 PMAP_UNLOCK(pmap); 2205 return (m); 2206 } 2207 2208 /* 2209 * Initialize a vm_page's machine-dependent fields. 2210 */ 2211 static void 2212 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2213 { 2214 2215 TAILQ_INIT(&m->md.pv_list); 2216 } 2217 2218 /* 2219 * mmu_booke_zero_page_area zeros the specified hardware page by 2220 * mapping it into virtual memory and using bzero to clear 2221 * its contents. 2222 * 2223 * off and size must reside within a single page. 2224 */ 2225 static void 2226 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2227 { 2228 vm_offset_t va; 2229 2230 /* XXX KASSERT off and size are within a single page? */ 2231 2232 mtx_lock(&zero_page_mutex); 2233 va = zero_page_va; 2234 2235 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2236 bzero((caddr_t)va + off, size); 2237 mmu_booke_kremove(mmu, va); 2238 2239 mtx_unlock(&zero_page_mutex); 2240 } 2241 2242 /* 2243 * mmu_booke_zero_page zeros the specified hardware page. 2244 */ 2245 static void 2246 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2247 { 2248 vm_offset_t off, va; 2249 2250 mtx_lock(&zero_page_mutex); 2251 va = zero_page_va; 2252 2253 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2254 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2255 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 2256 mmu_booke_kremove(mmu, va); 2257 2258 mtx_unlock(&zero_page_mutex); 2259 } 2260 2261 /* 2262 * mmu_booke_copy_page copies the specified (machine independent) page by 2263 * mapping the page into virtual memory and using memcopy to copy the page, 2264 * one machine dependent page at a time. 2265 */ 2266 static void 2267 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2268 { 2269 vm_offset_t sva, dva; 2270 2271 sva = copy_page_src_va; 2272 dva = copy_page_dst_va; 2273 2274 mtx_lock(©_page_mutex); 2275 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2276 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2277 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2278 mmu_booke_kremove(mmu, dva); 2279 mmu_booke_kremove(mmu, sva); 2280 mtx_unlock(©_page_mutex); 2281 } 2282 2283 static inline void 2284 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2285 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2286 { 2287 void *a_cp, *b_cp; 2288 vm_offset_t a_pg_offset, b_pg_offset; 2289 int cnt; 2290 2291 mtx_lock(©_page_mutex); 2292 while (xfersize > 0) { 2293 a_pg_offset = a_offset & PAGE_MASK; 2294 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2295 mmu_booke_kenter(mmu, copy_page_src_va, 2296 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2297 a_cp = (char *)copy_page_src_va + a_pg_offset; 2298 b_pg_offset = b_offset & PAGE_MASK; 2299 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2300 mmu_booke_kenter(mmu, copy_page_dst_va, 2301 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2302 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2303 bcopy(a_cp, b_cp, cnt); 2304 mmu_booke_kremove(mmu, copy_page_dst_va); 2305 mmu_booke_kremove(mmu, copy_page_src_va); 2306 a_offset += cnt; 2307 b_offset += cnt; 2308 xfersize -= cnt; 2309 } 2310 mtx_unlock(©_page_mutex); 2311 } 2312 2313 /* 2314 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2315 * into virtual memory and using bzero to clear its contents. This is intended 2316 * to be called from the vm_pagezero process only and outside of Giant. No 2317 * lock is required. 2318 */ 2319 static void 2320 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2321 { 2322 vm_offset_t va; 2323 2324 va = zero_page_idle_va; 2325 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2326 bzero((caddr_t)va, PAGE_SIZE); 2327 mmu_booke_kremove(mmu, va); 2328 } 2329 2330 static vm_offset_t 2331 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2332 { 2333 vm_paddr_t paddr; 2334 vm_offset_t qaddr; 2335 uint32_t flags; 2336 pte_t *pte; 2337 2338 paddr = VM_PAGE_TO_PHYS(m); 2339 2340 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2341 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 2342 flags |= PTE_PS_4KB; 2343 2344 critical_enter(); 2345 qaddr = PCPU_GET(qmap_addr); 2346 2347 pte = pte_find(mmu, kernel_pmap, qaddr); 2348 2349 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2350 2351 /* 2352 * XXX: tlbivax is broadcast to other cores, but qaddr should 2353 * not be present in other TLBs. Is there a better instruction 2354 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2355 */ 2356 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2357 __asm __volatile("isync; msync"); 2358 2359 *pte = PTE_RPN_FROM_PA(paddr) | flags; 2360 2361 /* Flush the real memory from the instruction cache. */ 2362 if ((flags & (PTE_I | PTE_G)) == 0) 2363 __syncicache((void *)qaddr, PAGE_SIZE); 2364 2365 return (qaddr); 2366 } 2367 2368 static void 2369 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2370 { 2371 pte_t *pte; 2372 2373 pte = pte_find(mmu, kernel_pmap, addr); 2374 2375 KASSERT(PCPU_GET(qmap_addr) == addr, 2376 ("mmu_booke_quick_remove_page: invalid address")); 2377 KASSERT(*pte != 0, 2378 ("mmu_booke_quick_remove_page: PTE not in use")); 2379 2380 *pte = 0; 2381 critical_exit(); 2382 } 2383 2384 /* 2385 * Return whether or not the specified physical page was modified 2386 * in any of physical maps. 2387 */ 2388 static boolean_t 2389 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2390 { 2391 pte_t *pte; 2392 pv_entry_t pv; 2393 boolean_t rv; 2394 2395 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2396 ("mmu_booke_is_modified: page %p is not managed", m)); 2397 rv = FALSE; 2398 2399 /* 2400 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2401 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2402 * is clear, no PTEs can be modified. 2403 */ 2404 VM_OBJECT_ASSERT_WLOCKED(m->object); 2405 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2406 return (rv); 2407 rw_wlock(&pvh_global_lock); 2408 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2409 PMAP_LOCK(pv->pv_pmap); 2410 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2411 PTE_ISVALID(pte)) { 2412 if (PTE_ISMODIFIED(pte)) 2413 rv = TRUE; 2414 } 2415 PMAP_UNLOCK(pv->pv_pmap); 2416 if (rv) 2417 break; 2418 } 2419 rw_wunlock(&pvh_global_lock); 2420 return (rv); 2421 } 2422 2423 /* 2424 * Return whether or not the specified virtual address is eligible 2425 * for prefault. 2426 */ 2427 static boolean_t 2428 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2429 { 2430 2431 return (FALSE); 2432 } 2433 2434 /* 2435 * Return whether or not the specified physical page was referenced 2436 * in any physical maps. 2437 */ 2438 static boolean_t 2439 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2440 { 2441 pte_t *pte; 2442 pv_entry_t pv; 2443 boolean_t rv; 2444 2445 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2446 ("mmu_booke_is_referenced: page %p is not managed", m)); 2447 rv = FALSE; 2448 rw_wlock(&pvh_global_lock); 2449 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2450 PMAP_LOCK(pv->pv_pmap); 2451 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2452 PTE_ISVALID(pte)) { 2453 if (PTE_ISREFERENCED(pte)) 2454 rv = TRUE; 2455 } 2456 PMAP_UNLOCK(pv->pv_pmap); 2457 if (rv) 2458 break; 2459 } 2460 rw_wunlock(&pvh_global_lock); 2461 return (rv); 2462 } 2463 2464 /* 2465 * Clear the modify bits on the specified physical page. 2466 */ 2467 static void 2468 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2469 { 2470 pte_t *pte; 2471 pv_entry_t pv; 2472 2473 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2474 ("mmu_booke_clear_modify: page %p is not managed", m)); 2475 VM_OBJECT_ASSERT_WLOCKED(m->object); 2476 KASSERT(!vm_page_xbusied(m), 2477 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2478 2479 /* 2480 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2481 * If the object containing the page is locked and the page is not 2482 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2483 */ 2484 if ((m->aflags & PGA_WRITEABLE) == 0) 2485 return; 2486 rw_wlock(&pvh_global_lock); 2487 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2488 PMAP_LOCK(pv->pv_pmap); 2489 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2490 PTE_ISVALID(pte)) { 2491 mtx_lock_spin(&tlbivax_mutex); 2492 tlb_miss_lock(); 2493 2494 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2495 tlb0_flush_entry(pv->pv_va); 2496 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2497 PTE_REFERENCED); 2498 } 2499 2500 tlb_miss_unlock(); 2501 mtx_unlock_spin(&tlbivax_mutex); 2502 } 2503 PMAP_UNLOCK(pv->pv_pmap); 2504 } 2505 rw_wunlock(&pvh_global_lock); 2506 } 2507 2508 /* 2509 * Return a count of reference bits for a page, clearing those bits. 2510 * It is not necessary for every reference bit to be cleared, but it 2511 * is necessary that 0 only be returned when there are truly no 2512 * reference bits set. 2513 * 2514 * XXX: The exact number of bits to check and clear is a matter that 2515 * should be tested and standardized at some point in the future for 2516 * optimal aging of shared pages. 2517 */ 2518 static int 2519 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2520 { 2521 pte_t *pte; 2522 pv_entry_t pv; 2523 int count; 2524 2525 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2526 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2527 count = 0; 2528 rw_wlock(&pvh_global_lock); 2529 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2530 PMAP_LOCK(pv->pv_pmap); 2531 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2532 PTE_ISVALID(pte)) { 2533 if (PTE_ISREFERENCED(pte)) { 2534 mtx_lock_spin(&tlbivax_mutex); 2535 tlb_miss_lock(); 2536 2537 tlb0_flush_entry(pv->pv_va); 2538 *pte &= ~PTE_REFERENCED; 2539 2540 tlb_miss_unlock(); 2541 mtx_unlock_spin(&tlbivax_mutex); 2542 2543 if (++count > 4) { 2544 PMAP_UNLOCK(pv->pv_pmap); 2545 break; 2546 } 2547 } 2548 } 2549 PMAP_UNLOCK(pv->pv_pmap); 2550 } 2551 rw_wunlock(&pvh_global_lock); 2552 return (count); 2553 } 2554 2555 /* 2556 * Clear the wired attribute from the mappings for the specified range of 2557 * addresses in the given pmap. Every valid mapping within that range must 2558 * have the wired attribute set. In contrast, invalid mappings cannot have 2559 * the wired attribute set, so they are ignored. 2560 * 2561 * The wired attribute of the page table entry is not a hardware feature, so 2562 * there is no need to invalidate any TLB entries. 2563 */ 2564 static void 2565 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2566 { 2567 vm_offset_t va; 2568 pte_t *pte; 2569 2570 PMAP_LOCK(pmap); 2571 for (va = sva; va < eva; va += PAGE_SIZE) { 2572 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2573 PTE_ISVALID(pte)) { 2574 if (!PTE_ISWIRED(pte)) 2575 panic("mmu_booke_unwire: pte %p isn't wired", 2576 pte); 2577 *pte &= ~PTE_WIRED; 2578 pmap->pm_stats.wired_count--; 2579 } 2580 } 2581 PMAP_UNLOCK(pmap); 2582 2583 } 2584 2585 /* 2586 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2587 * page. This count may be changed upwards or downwards in the future; it is 2588 * only necessary that true be returned for a small subset of pmaps for proper 2589 * page aging. 2590 */ 2591 static boolean_t 2592 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2593 { 2594 pv_entry_t pv; 2595 int loops; 2596 boolean_t rv; 2597 2598 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2599 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2600 loops = 0; 2601 rv = FALSE; 2602 rw_wlock(&pvh_global_lock); 2603 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2604 if (pv->pv_pmap == pmap) { 2605 rv = TRUE; 2606 break; 2607 } 2608 if (++loops >= 16) 2609 break; 2610 } 2611 rw_wunlock(&pvh_global_lock); 2612 return (rv); 2613 } 2614 2615 /* 2616 * Return the number of managed mappings to the given physical page that are 2617 * wired. 2618 */ 2619 static int 2620 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2621 { 2622 pv_entry_t pv; 2623 pte_t *pte; 2624 int count = 0; 2625 2626 if ((m->oflags & VPO_UNMANAGED) != 0) 2627 return (count); 2628 rw_wlock(&pvh_global_lock); 2629 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2630 PMAP_LOCK(pv->pv_pmap); 2631 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2632 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2633 count++; 2634 PMAP_UNLOCK(pv->pv_pmap); 2635 } 2636 rw_wunlock(&pvh_global_lock); 2637 return (count); 2638 } 2639 2640 static int 2641 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2642 { 2643 int i; 2644 vm_offset_t va; 2645 2646 /* 2647 * This currently does not work for entries that 2648 * overlap TLB1 entries. 2649 */ 2650 for (i = 0; i < tlb1_idx; i ++) { 2651 if (tlb1_iomapped(i, pa, size, &va) == 0) 2652 return (0); 2653 } 2654 2655 return (EFAULT); 2656 } 2657 2658 void 2659 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2660 { 2661 vm_paddr_t ppa; 2662 vm_offset_t ofs; 2663 vm_size_t gran; 2664 2665 /* Minidumps are based on virtual memory addresses. */ 2666 if (do_minidump) { 2667 *va = (void *)(vm_offset_t)pa; 2668 return; 2669 } 2670 2671 /* Raw physical memory dumps don't have a virtual address. */ 2672 /* We always map a 256MB page at 256M. */ 2673 gran = 256 * 1024 * 1024; 2674 ppa = pa & ~(gran - 1); 2675 ofs = pa - ppa; 2676 *va = (void *)gran; 2677 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2678 2679 if (sz > (gran - ofs)) 2680 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2681 _TLB_ENTRY_IO); 2682 } 2683 2684 void 2685 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2686 { 2687 vm_paddr_t ppa; 2688 vm_offset_t ofs; 2689 vm_size_t gran; 2690 2691 /* Minidumps are based on virtual memory addresses. */ 2692 /* Nothing to do... */ 2693 if (do_minidump) 2694 return; 2695 2696 /* Raw physical memory dumps don't have a virtual address. */ 2697 tlb1_idx--; 2698 tlb1[tlb1_idx].mas1 = 0; 2699 tlb1[tlb1_idx].mas2 = 0; 2700 tlb1[tlb1_idx].mas3 = 0; 2701 tlb1_write_entry(tlb1_idx); 2702 2703 gran = 256 * 1024 * 1024; 2704 ppa = pa & ~(gran - 1); 2705 ofs = pa - ppa; 2706 if (sz > (gran - ofs)) { 2707 tlb1_idx--; 2708 tlb1[tlb1_idx].mas1 = 0; 2709 tlb1[tlb1_idx].mas2 = 0; 2710 tlb1[tlb1_idx].mas3 = 0; 2711 tlb1_write_entry(tlb1_idx); 2712 } 2713 } 2714 2715 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2716 2717 void 2718 mmu_booke_scan_init(mmu_t mmu) 2719 { 2720 vm_offset_t va; 2721 pte_t *pte; 2722 int i; 2723 2724 if (!do_minidump) { 2725 /* Initialize phys. segments for dumpsys(). */ 2726 memset(&dump_map, 0, sizeof(dump_map)); 2727 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2728 &availmem_regions_sz); 2729 for (i = 0; i < physmem_regions_sz; i++) { 2730 dump_map[i].pa_start = physmem_regions[i].mr_start; 2731 dump_map[i].pa_size = physmem_regions[i].mr_size; 2732 } 2733 return; 2734 } 2735 2736 /* Virtual segments for minidumps: */ 2737 memset(&dump_map, 0, sizeof(dump_map)); 2738 2739 /* 1st: kernel .data and .bss. */ 2740 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2741 dump_map[0].pa_size = 2742 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2743 2744 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2745 dump_map[1].pa_start = data_start; 2746 dump_map[1].pa_size = data_end - data_start; 2747 2748 /* 3rd: kernel VM. */ 2749 va = dump_map[1].pa_start + dump_map[1].pa_size; 2750 /* Find start of next chunk (from va). */ 2751 while (va < virtual_end) { 2752 /* Don't dump the buffer cache. */ 2753 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2754 va = kmi.buffer_eva; 2755 continue; 2756 } 2757 pte = pte_find(mmu, kernel_pmap, va); 2758 if (pte != NULL && PTE_ISVALID(pte)) 2759 break; 2760 va += PAGE_SIZE; 2761 } 2762 if (va < virtual_end) { 2763 dump_map[2].pa_start = va; 2764 va += PAGE_SIZE; 2765 /* Find last page in chunk. */ 2766 while (va < virtual_end) { 2767 /* Don't run into the buffer cache. */ 2768 if (va == kmi.buffer_sva) 2769 break; 2770 pte = pte_find(mmu, kernel_pmap, va); 2771 if (pte == NULL || !PTE_ISVALID(pte)) 2772 break; 2773 va += PAGE_SIZE; 2774 } 2775 dump_map[2].pa_size = va - dump_map[2].pa_start; 2776 } 2777 } 2778 2779 /* 2780 * Map a set of physical memory pages into the kernel virtual address space. 2781 * Return a pointer to where it is mapped. This routine is intended to be used 2782 * for mapping device memory, NOT real memory. 2783 */ 2784 static void * 2785 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2786 { 2787 2788 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2789 } 2790 2791 static void * 2792 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2793 { 2794 void *res; 2795 uintptr_t va; 2796 vm_size_t sz; 2797 int i; 2798 2799 /* 2800 * Check if this is premapped in TLB1. Note: this should probably also 2801 * check whether a sequence of TLB1 entries exist that match the 2802 * requirement, but now only checks the easy case. 2803 */ 2804 if (ma == VM_MEMATTR_DEFAULT) { 2805 for (i = 0; i < tlb1_idx; i++) { 2806 if (!(tlb1[i].mas1 & MAS1_VALID)) 2807 continue; 2808 if (pa >= tlb1[i].phys && 2809 (pa + size) <= (tlb1[i].phys + tlb1[i].size)) 2810 return (void *)(tlb1[i].virt + 2811 (vm_offset_t)(pa - tlb1[i].phys)); 2812 } 2813 } 2814 2815 size = roundup(size, PAGE_SIZE); 2816 2817 /* 2818 * We leave a hole for device direct mapping between the maximum user 2819 * address (0x8000000) and the minimum KVA address (0xc0000000). If 2820 * devices are in there, just map them 1:1. If not, map them to the 2821 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped 2822 * addresses should be pulled from an allocator, but since we do not 2823 * ever free TLB1 entries, it is safe just to increment a counter. 2824 * Note that there isn't a lot of address space here (128 MB) and it 2825 * is not at all difficult to imagine running out, since that is a 4:1 2826 * compression from the 0xc0000000 - 0xf0000000 address space that gets 2827 * mapped there. 2828 */ 2829 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) && 2830 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS) 2831 va = pa; 2832 else 2833 va = atomic_fetchadd_int(&tlb1_map_base, size); 2834 res = (void *)va; 2835 2836 do { 2837 sz = 1 << (ilog2(size) & ~1); 2838 if (va % sz != 0) { 2839 do { 2840 sz >>= 2; 2841 } while (va % sz != 0); 2842 } 2843 if (bootverbose) 2844 printf("Wiring VA=%x to PA=%jx (size=%x), " 2845 "using TLB1[%d]\n", va, (uintmax_t)pa, sz, tlb1_idx); 2846 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma)); 2847 size -= sz; 2848 pa += sz; 2849 va += sz; 2850 } while (size > 0); 2851 2852 return (res); 2853 } 2854 2855 /* 2856 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2857 */ 2858 static void 2859 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2860 { 2861 #ifdef SUPPORTS_SHRINKING_TLB1 2862 vm_offset_t base, offset; 2863 2864 /* 2865 * Unmap only if this is inside kernel virtual space. 2866 */ 2867 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2868 base = trunc_page(va); 2869 offset = va & PAGE_MASK; 2870 size = roundup(offset + size, PAGE_SIZE); 2871 kva_free(base, size); 2872 } 2873 #endif 2874 } 2875 2876 /* 2877 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2878 * specified pmap. This eliminates the blast of soft faults on process startup 2879 * and immediately after an mmap. 2880 */ 2881 static void 2882 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2883 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2884 { 2885 2886 VM_OBJECT_ASSERT_WLOCKED(object); 2887 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2888 ("mmu_booke_object_init_pt: non-device object")); 2889 } 2890 2891 /* 2892 * Perform the pmap work for mincore. 2893 */ 2894 static int 2895 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2896 vm_paddr_t *locked_pa) 2897 { 2898 2899 /* XXX: this should be implemented at some point */ 2900 return (0); 2901 } 2902 2903 /**************************************************************************/ 2904 /* TID handling */ 2905 /**************************************************************************/ 2906 2907 /* 2908 * Allocate a TID. If necessary, steal one from someone else. 2909 * The new TID is flushed from the TLB before returning. 2910 */ 2911 static tlbtid_t 2912 tid_alloc(pmap_t pmap) 2913 { 2914 tlbtid_t tid; 2915 int thiscpu; 2916 2917 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2918 2919 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2920 2921 thiscpu = PCPU_GET(cpuid); 2922 2923 tid = PCPU_GET(tid_next); 2924 if (tid > TID_MAX) 2925 tid = TID_MIN; 2926 PCPU_SET(tid_next, tid + 1); 2927 2928 /* If we are stealing TID then clear the relevant pmap's field */ 2929 if (tidbusy[thiscpu][tid] != NULL) { 2930 2931 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2932 2933 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2934 2935 /* Flush all entries from TLB0 matching this TID. */ 2936 tid_flush(tid); 2937 } 2938 2939 tidbusy[thiscpu][tid] = pmap; 2940 pmap->pm_tid[thiscpu] = tid; 2941 __asm __volatile("msync; isync"); 2942 2943 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2944 PCPU_GET(tid_next)); 2945 2946 return (tid); 2947 } 2948 2949 /**************************************************************************/ 2950 /* TLB0 handling */ 2951 /**************************************************************************/ 2952 2953 static void 2954 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2955 uint32_t mas7) 2956 { 2957 int as; 2958 char desc[3]; 2959 tlbtid_t tid; 2960 vm_size_t size; 2961 unsigned int tsize; 2962 2963 desc[2] = '\0'; 2964 if (mas1 & MAS1_VALID) 2965 desc[0] = 'V'; 2966 else 2967 desc[0] = ' '; 2968 2969 if (mas1 & MAS1_IPROT) 2970 desc[1] = 'P'; 2971 else 2972 desc[1] = ' '; 2973 2974 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2975 tid = MAS1_GETTID(mas1); 2976 2977 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2978 size = 0; 2979 if (tsize) 2980 size = tsize2size(tsize); 2981 2982 debugf("%3d: (%s) [AS=%d] " 2983 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2984 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2985 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2986 } 2987 2988 /* Convert TLB0 va and way number to tlb0[] table index. */ 2989 static inline unsigned int 2990 tlb0_tableidx(vm_offset_t va, unsigned int way) 2991 { 2992 unsigned int idx; 2993 2994 idx = (way * TLB0_ENTRIES_PER_WAY); 2995 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2996 return (idx); 2997 } 2998 2999 /* 3000 * Invalidate TLB0 entry. 3001 */ 3002 static inline void 3003 tlb0_flush_entry(vm_offset_t va) 3004 { 3005 3006 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3007 3008 mtx_assert(&tlbivax_mutex, MA_OWNED); 3009 3010 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3011 __asm __volatile("isync; msync"); 3012 __asm __volatile("tlbsync; msync"); 3013 3014 CTR1(KTR_PMAP, "%s: e", __func__); 3015 } 3016 3017 /* Print out contents of the MAS registers for each TLB0 entry */ 3018 void 3019 tlb0_print_tlbentries(void) 3020 { 3021 uint32_t mas0, mas1, mas2, mas3, mas7; 3022 int entryidx, way, idx; 3023 3024 debugf("TLB0 entries:\n"); 3025 for (way = 0; way < TLB0_WAYS; way ++) 3026 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3027 3028 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3029 mtspr(SPR_MAS0, mas0); 3030 __asm __volatile("isync"); 3031 3032 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3033 mtspr(SPR_MAS2, mas2); 3034 3035 __asm __volatile("isync; tlbre"); 3036 3037 mas1 = mfspr(SPR_MAS1); 3038 mas2 = mfspr(SPR_MAS2); 3039 mas3 = mfspr(SPR_MAS3); 3040 mas7 = mfspr(SPR_MAS7); 3041 3042 idx = tlb0_tableidx(mas2, way); 3043 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3044 } 3045 } 3046 3047 /**************************************************************************/ 3048 /* TLB1 handling */ 3049 /**************************************************************************/ 3050 3051 /* 3052 * TLB1 mapping notes: 3053 * 3054 * TLB1[0] Kernel text and data. 3055 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3056 * windows, other devices mappings. 3057 */ 3058 3059 /* 3060 * Write given entry to TLB1 hardware. 3061 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3062 */ 3063 static void 3064 tlb1_write_entry(unsigned int idx) 3065 { 3066 uint32_t mas0; 3067 3068 //debugf("tlb1_write_entry: s\n"); 3069 3070 /* Select entry */ 3071 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3072 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3073 3074 mtspr(SPR_MAS0, mas0); 3075 __asm __volatile("isync"); 3076 mtspr(SPR_MAS1, tlb1[idx].mas1); 3077 __asm __volatile("isync"); 3078 mtspr(SPR_MAS2, tlb1[idx].mas2); 3079 __asm __volatile("isync"); 3080 mtspr(SPR_MAS3, tlb1[idx].mas3); 3081 __asm __volatile("isync"); 3082 switch ((mfpvr() >> 16) & 0xFFFF) { 3083 case FSL_E500mc: 3084 case FSL_E5500: 3085 mtspr(SPR_MAS8, 0); 3086 __asm __volatile("isync"); 3087 /* FALLTHROUGH */ 3088 case FSL_E500v2: 3089 mtspr(SPR_MAS7, tlb1[idx].mas7); 3090 __asm __volatile("isync"); 3091 break; 3092 default: 3093 break; 3094 } 3095 3096 __asm __volatile("tlbwe; isync; msync"); 3097 3098 //debugf("tlb1_write_entry: e\n"); 3099 } 3100 3101 /* 3102 * Return the largest uint value log such that 2^log <= num. 3103 */ 3104 static unsigned int 3105 ilog2(unsigned int num) 3106 { 3107 int lz; 3108 3109 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3110 return (31 - lz); 3111 } 3112 3113 /* 3114 * Convert TLB TSIZE value to mapped region size. 3115 */ 3116 static vm_size_t 3117 tsize2size(unsigned int tsize) 3118 { 3119 3120 /* 3121 * size = 4^tsize KB 3122 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3123 */ 3124 3125 return ((1 << (2 * tsize)) * 1024); 3126 } 3127 3128 /* 3129 * Convert region size (must be power of 4) to TLB TSIZE value. 3130 */ 3131 static unsigned int 3132 size2tsize(vm_size_t size) 3133 { 3134 3135 return (ilog2(size) / 2 - 5); 3136 } 3137 3138 /* 3139 * Register permanent kernel mapping in TLB1. 3140 * 3141 * Entries are created starting from index 0 (current free entry is 3142 * kept in tlb1_idx) and are not supposed to be invalidated. 3143 */ 3144 static int 3145 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3146 uint32_t flags) 3147 { 3148 uint32_t ts, tid; 3149 int tsize, index; 3150 3151 index = atomic_fetchadd_int(&tlb1_idx, 1); 3152 if (index >= TLB1_ENTRIES) { 3153 printf("tlb1_set_entry: TLB1 full!\n"); 3154 return (-1); 3155 } 3156 3157 /* Convert size to TSIZE */ 3158 tsize = size2tsize(size); 3159 3160 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3161 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3162 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3163 3164 /* 3165 * Atomicity is preserved by the atomic increment above since nothing 3166 * is ever removed from tlb1. 3167 */ 3168 3169 tlb1[index].phys = pa; 3170 tlb1[index].virt = va; 3171 tlb1[index].size = size; 3172 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3173 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3174 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags; 3175 3176 /* Set supervisor RWX permission bits */ 3177 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3178 tlb1[index].mas7 = (pa >> 32) & MAS7_RPN; 3179 3180 tlb1_write_entry(index); 3181 3182 /* 3183 * XXX in general TLB1 updates should be propagated between CPUs, 3184 * since current design assumes to have the same TLB1 set-up on all 3185 * cores. 3186 */ 3187 return (0); 3188 } 3189 3190 /* 3191 * Map in contiguous RAM region into the TLB1 using maximum of 3192 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3193 * 3194 * If necessary round up last entry size and return total size 3195 * used by all allocated entries. 3196 */ 3197 vm_size_t 3198 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3199 { 3200 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3201 vm_size_t mapped, pgsz, base, mask; 3202 int idx, nents; 3203 3204 /* Round up to the next 1M */ 3205 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 3206 3207 mapped = 0; 3208 idx = 0; 3209 base = va; 3210 pgsz = 64*1024*1024; 3211 while (mapped < size) { 3212 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3213 while (pgsz > (size - mapped)) 3214 pgsz >>= 2; 3215 pgs[idx++] = pgsz; 3216 mapped += pgsz; 3217 } 3218 3219 /* We under-map. Correct for this. */ 3220 if (mapped < size) { 3221 while (pgs[idx - 1] == pgsz) { 3222 idx--; 3223 mapped -= pgsz; 3224 } 3225 /* XXX We may increase beyond out starting point. */ 3226 pgsz <<= 2; 3227 pgs[idx++] = pgsz; 3228 mapped += pgsz; 3229 } 3230 } 3231 3232 nents = idx; 3233 mask = pgs[0] - 1; 3234 /* Align address to the boundary */ 3235 if (va & mask) { 3236 va = (va + mask) & ~mask; 3237 pa = (pa + mask) & ~mask; 3238 } 3239 3240 for (idx = 0; idx < nents; idx++) { 3241 pgsz = pgs[idx]; 3242 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3243 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3244 pa += pgsz; 3245 va += pgsz; 3246 } 3247 3248 mapped = (va - base); 3249 #ifdef __powerpc64__ 3250 printf("mapped size 0x%016lx (wasted space 0x%16lx)\n", 3251 #else 3252 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3253 #endif 3254 mapped, mapped - size); 3255 return (mapped); 3256 } 3257 3258 /* 3259 * TLB1 initialization routine, to be called after the very first 3260 * assembler level setup done in locore.S. 3261 */ 3262 void 3263 tlb1_init() 3264 { 3265 uint32_t mas0, mas1, mas2, mas3, mas7; 3266 uint32_t tsz; 3267 int i; 3268 3269 tlb1_idx = 1; 3270 3271 tlb1_get_tlbconf(); 3272 3273 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3274 mtspr(SPR_MAS0, mas0); 3275 __asm __volatile("isync; tlbre"); 3276 3277 mas1 = mfspr(SPR_MAS1); 3278 mas2 = mfspr(SPR_MAS2); 3279 mas3 = mfspr(SPR_MAS3); 3280 mas7 = mfspr(SPR_MAS7); 3281 3282 tlb1[0].mas1 = mas1; 3283 tlb1[0].mas2 = mfspr(SPR_MAS2); 3284 tlb1[0].mas3 = mas3; 3285 tlb1[0].mas7 = mas7; 3286 tlb1[0].virt = mas2 & MAS2_EPN_MASK; 3287 tlb1[0].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3288 (mas3 & MAS3_RPN); 3289 3290 kernload = tlb1[0].phys; 3291 3292 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3293 tlb1[0].size = (tsz > 0) ? tsize2size(tsz) : 0; 3294 kernsize += tlb1[0].size; 3295 3296 #ifdef SMP 3297 bp_ntlb1s = tlb1_idx; 3298 #endif 3299 3300 /* Purge the remaining entries */ 3301 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3302 tlb1_write_entry(i); 3303 3304 /* Setup TLB miss defaults */ 3305 set_mas4_defaults(); 3306 } 3307 3308 vm_offset_t 3309 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3310 { 3311 vm_paddr_t pa_base; 3312 vm_offset_t va, sz; 3313 int i; 3314 3315 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3316 3317 for (i = 0; i < tlb1_idx; i++) { 3318 if (!(tlb1[i].mas1 & MAS1_VALID)) 3319 continue; 3320 if (pa >= tlb1[i].phys && (pa + size) <= 3321 (tlb1[i].phys + tlb1[i].size)) 3322 return (tlb1[i].virt + (pa - tlb1[i].phys)); 3323 } 3324 3325 pa_base = rounddown(pa, PAGE_SIZE); 3326 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3327 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3328 va = tlb1_map_base + (pa - pa_base); 3329 3330 do { 3331 sz = 1 << (ilog2(size) & ~1); 3332 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO); 3333 size -= sz; 3334 pa_base += sz; 3335 tlb1_map_base += sz; 3336 } while (size > 0); 3337 3338 #ifdef SMP 3339 bp_ntlb1s = tlb1_idx; 3340 #endif 3341 3342 return (va); 3343 } 3344 3345 /* 3346 * Setup MAS4 defaults. 3347 * These values are loaded to MAS0-2 on a TLB miss. 3348 */ 3349 static void 3350 set_mas4_defaults(void) 3351 { 3352 uint32_t mas4; 3353 3354 /* Defaults: TLB0, PID0, TSIZED=4K */ 3355 mas4 = MAS4_TLBSELD0; 3356 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3357 #ifdef SMP 3358 mas4 |= MAS4_MD; 3359 #endif 3360 mtspr(SPR_MAS4, mas4); 3361 __asm __volatile("isync"); 3362 } 3363 3364 /* 3365 * Print out contents of the MAS registers for each TLB1 entry 3366 */ 3367 void 3368 tlb1_print_tlbentries(void) 3369 { 3370 uint32_t mas0, mas1, mas2, mas3, mas7; 3371 int i; 3372 3373 debugf("TLB1 entries:\n"); 3374 for (i = 0; i < TLB1_ENTRIES; i++) { 3375 3376 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3377 mtspr(SPR_MAS0, mas0); 3378 3379 __asm __volatile("isync; tlbre"); 3380 3381 mas1 = mfspr(SPR_MAS1); 3382 mas2 = mfspr(SPR_MAS2); 3383 mas3 = mfspr(SPR_MAS3); 3384 mas7 = mfspr(SPR_MAS7); 3385 3386 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3387 } 3388 } 3389 3390 /* 3391 * Print out contents of the in-ram tlb1 table. 3392 */ 3393 void 3394 tlb1_print_entries(void) 3395 { 3396 int i; 3397 3398 debugf("tlb1[] table entries:\n"); 3399 for (i = 0; i < TLB1_ENTRIES; i++) 3400 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 3401 tlb1[i].mas7); 3402 } 3403 3404 /* 3405 * Return 0 if the physical IO range is encompassed by one of the 3406 * the TLB1 entries, otherwise return related error code. 3407 */ 3408 static int 3409 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3410 { 3411 uint32_t prot; 3412 vm_paddr_t pa_start; 3413 vm_paddr_t pa_end; 3414 unsigned int entry_tsize; 3415 vm_size_t entry_size; 3416 3417 *va = (vm_offset_t)NULL; 3418 3419 /* Skip invalid entries */ 3420 if (!(tlb1[i].mas1 & MAS1_VALID)) 3421 return (EINVAL); 3422 3423 /* 3424 * The entry must be cache-inhibited, guarded, and r/w 3425 * so it can function as an i/o page 3426 */ 3427 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3428 if (prot != (MAS2_I | MAS2_G)) 3429 return (EPERM); 3430 3431 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3432 if (prot != (MAS3_SR | MAS3_SW)) 3433 return (EPERM); 3434 3435 /* The address should be within the entry range. */ 3436 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3437 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3438 3439 entry_size = tsize2size(entry_tsize); 3440 pa_start = (((vm_paddr_t)tlb1[i].mas7 & MAS7_RPN) << 32) | 3441 (tlb1[i].mas3 & MAS3_RPN); 3442 pa_end = pa_start + entry_size; 3443 3444 if ((pa < pa_start) || ((pa + size) > pa_end)) 3445 return (ERANGE); 3446 3447 /* Return virtual address of this mapping. */ 3448 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3449 return (0); 3450 } 3451 3452 /* 3453 * Invalidate all TLB0 entries which match the given TID. Note this is 3454 * dedicated for cases when invalidations should NOT be propagated to other 3455 * CPUs. 3456 */ 3457 static void 3458 tid_flush(tlbtid_t tid) 3459 { 3460 register_t msr; 3461 uint32_t mas0, mas1, mas2; 3462 int entry, way; 3463 3464 3465 /* Don't evict kernel translations */ 3466 if (tid == TID_KERNEL) 3467 return; 3468 3469 msr = mfmsr(); 3470 __asm __volatile("wrteei 0"); 3471 3472 for (way = 0; way < TLB0_WAYS; way++) 3473 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3474 3475 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3476 mtspr(SPR_MAS0, mas0); 3477 __asm __volatile("isync"); 3478 3479 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3480 mtspr(SPR_MAS2, mas2); 3481 3482 __asm __volatile("isync; tlbre"); 3483 3484 mas1 = mfspr(SPR_MAS1); 3485 3486 if (!(mas1 & MAS1_VALID)) 3487 continue; 3488 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3489 continue; 3490 mas1 &= ~MAS1_VALID; 3491 mtspr(SPR_MAS1, mas1); 3492 __asm __volatile("isync; tlbwe; isync; msync"); 3493 } 3494 mtmsr(msr); 3495 } 3496