1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * 32-bit pmap: 40 * Virtual address space layout: 41 * ----------------------------- 42 * 0x0000_0000 - 0x7fff_ffff : user process 43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 46 * 0xc100_0000 - 0xffff_ffff : KVA 47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 51 * 52 * 64-bit pmap: 53 * Virtual address space layout: 54 * ----------------------------- 55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process 56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries 57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region 58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack 59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved 60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data 61 * endkernel - msgbufp-1 : flat device tree 62 * msgbufp - ptbl_bufs-1 : message buffer 63 * ptbl_bufs - kernel_pdir-1 : kernel page tables 64 * kernel_pdir - kernel_pp2d-1 : kernel page directory 65 * kernel_pp2d - . : kernel pointers to page directory 66 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy 67 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs 68 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables 69 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space 70 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region 71 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region 72 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map 73 * 0xf000_0000_0000_0000 - +Maxmem : physmem map 74 * - 0xffff_ffff_ffff_ffff : device direct map 75 */ 76 77 #include <sys/cdefs.h> 78 __FBSDID("$FreeBSD$"); 79 80 #include "opt_kstack_pages.h" 81 82 #include <sys/param.h> 83 #include <sys/conf.h> 84 #include <sys/malloc.h> 85 #include <sys/ktr.h> 86 #include <sys/proc.h> 87 #include <sys/user.h> 88 #include <sys/queue.h> 89 #include <sys/systm.h> 90 #include <sys/kernel.h> 91 #include <sys/kerneldump.h> 92 #include <sys/linker.h> 93 #include <sys/msgbuf.h> 94 #include <sys/lock.h> 95 #include <sys/mutex.h> 96 #include <sys/rwlock.h> 97 #include <sys/sched.h> 98 #include <sys/smp.h> 99 #include <sys/vmmeter.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_page.h> 103 #include <vm/vm_kern.h> 104 #include <vm/vm_pageout.h> 105 #include <vm/vm_extern.h> 106 #include <vm/vm_object.h> 107 #include <vm/vm_param.h> 108 #include <vm/vm_map.h> 109 #include <vm/vm_pager.h> 110 #include <vm/uma.h> 111 112 #include <machine/_inttypes.h> 113 #include <machine/cpu.h> 114 #include <machine/pcb.h> 115 #include <machine/platform.h> 116 117 #include <machine/tlb.h> 118 #include <machine/spr.h> 119 #include <machine/md_var.h> 120 #include <machine/mmuvar.h> 121 #include <machine/pmap.h> 122 #include <machine/pte.h> 123 124 #include "mmu_if.h" 125 126 #define SPARSE_MAPDEV 127 #ifdef DEBUG 128 #define debugf(fmt, args...) printf(fmt, ##args) 129 #else 130 #define debugf(fmt, args...) 131 #endif 132 133 #ifdef __powerpc64__ 134 #define PRI0ptrX "016lx" 135 #else 136 #define PRI0ptrX "08x" 137 #endif 138 139 #define TODO panic("%s: not implemented", __func__); 140 141 extern unsigned char _etext[]; 142 extern unsigned char _end[]; 143 144 extern uint32_t *bootinfo; 145 146 vm_paddr_t kernload; 147 vm_offset_t kernstart; 148 vm_size_t kernsize; 149 150 /* Message buffer and tables. */ 151 static vm_offset_t data_start; 152 static vm_size_t data_end; 153 154 /* Phys/avail memory regions. */ 155 static struct mem_region *availmem_regions; 156 static int availmem_regions_sz; 157 static struct mem_region *physmem_regions; 158 static int physmem_regions_sz; 159 160 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 161 static vm_offset_t zero_page_va; 162 static struct mtx zero_page_mutex; 163 164 static struct mtx tlbivax_mutex; 165 166 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 167 static vm_offset_t copy_page_src_va; 168 static vm_offset_t copy_page_dst_va; 169 static struct mtx copy_page_mutex; 170 171 /**************************************************************************/ 172 /* PMAP */ 173 /**************************************************************************/ 174 175 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 176 vm_prot_t, u_int flags, int8_t psind); 177 178 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 179 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 180 #ifdef __powerpc64__ 181 unsigned int kernel_pdirs; 182 #endif 183 184 /* 185 * If user pmap is processed with mmu_booke_remove and the resident count 186 * drops to 0, there are no more pages to remove, so we need not continue. 187 */ 188 #define PMAP_REMOVE_DONE(pmap) \ 189 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 190 191 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 192 extern int elf32_nxstack; 193 #endif 194 195 /**************************************************************************/ 196 /* TLB and TID handling */ 197 /**************************************************************************/ 198 199 /* Translation ID busy table */ 200 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 201 202 /* 203 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 204 * core revisions and should be read from h/w registers during early config. 205 */ 206 uint32_t tlb0_entries; 207 uint32_t tlb0_ways; 208 uint32_t tlb0_entries_per_way; 209 uint32_t tlb1_entries; 210 211 #define TLB0_ENTRIES (tlb0_entries) 212 #define TLB0_WAYS (tlb0_ways) 213 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 214 215 #define TLB1_ENTRIES (tlb1_entries) 216 217 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE; 218 219 static tlbtid_t tid_alloc(struct pmap *); 220 static void tid_flush(tlbtid_t tid); 221 222 #ifdef __powerpc64__ 223 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t); 224 #else 225 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 226 #endif 227 228 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 229 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 230 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 231 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 232 233 static vm_size_t tsize2size(unsigned int); 234 static unsigned int size2tsize(vm_size_t); 235 static unsigned int ilog2(unsigned int); 236 237 static void set_mas4_defaults(void); 238 239 static inline void tlb0_flush_entry(vm_offset_t); 240 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 241 242 /**************************************************************************/ 243 /* Page table management */ 244 /**************************************************************************/ 245 246 static struct rwlock_padalign pvh_global_lock; 247 248 /* Data for the pv entry allocation mechanism */ 249 static uma_zone_t pvzone; 250 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 251 252 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 253 254 #ifndef PMAP_SHPGPERPROC 255 #define PMAP_SHPGPERPROC 200 256 #endif 257 258 static void ptbl_init(void); 259 static struct ptbl_buf *ptbl_buf_alloc(void); 260 static void ptbl_buf_free(struct ptbl_buf *); 261 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 262 263 #ifdef __powerpc64__ 264 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **, 265 unsigned int, boolean_t); 266 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int); 267 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int); 268 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t); 269 #else 270 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 271 static void ptbl_free(mmu_t, pmap_t, unsigned int); 272 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 273 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 274 #endif 275 276 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 277 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 278 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 279 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 280 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t); 281 282 static pv_entry_t pv_alloc(void); 283 static void pv_free(pv_entry_t); 284 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 285 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 286 287 static void booke_pmap_init_qpages(void); 288 289 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 290 #ifdef __powerpc64__ 291 #define PTBL_BUFS (16UL * 16 * 16) 292 #else 293 #define PTBL_BUFS (128 * 16) 294 #endif 295 296 struct ptbl_buf { 297 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 298 vm_offset_t kva; /* va of mapping */ 299 }; 300 301 /* ptbl free list and a lock used for access synchronization. */ 302 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 303 static struct mtx ptbl_buf_freelist_lock; 304 305 /* Base address of kva space allocated fot ptbl bufs. */ 306 static vm_offset_t ptbl_buf_pool_vabase; 307 308 /* Pointer to ptbl_buf structures. */ 309 static struct ptbl_buf *ptbl_bufs; 310 311 #ifdef SMP 312 extern tlb_entry_t __boot_tlb1[]; 313 void pmap_bootstrap_ap(volatile uint32_t *); 314 #endif 315 316 /* 317 * Kernel MMU interface 318 */ 319 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 320 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 321 vm_size_t, vm_offset_t); 322 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 323 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 324 vm_offset_t, vm_page_t *, vm_offset_t, int); 325 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 326 vm_prot_t, u_int flags, int8_t psind); 327 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 328 vm_page_t, vm_prot_t); 329 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 330 vm_prot_t); 331 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 332 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 333 vm_prot_t); 334 static void mmu_booke_init(mmu_t); 335 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 336 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 337 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 338 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 339 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 340 int); 341 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 342 vm_paddr_t *); 343 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 344 vm_object_t, vm_pindex_t, vm_size_t); 345 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 346 static void mmu_booke_page_init(mmu_t, vm_page_t); 347 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 348 static void mmu_booke_pinit(mmu_t, pmap_t); 349 static void mmu_booke_pinit0(mmu_t, pmap_t); 350 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 351 vm_prot_t); 352 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 353 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 354 static void mmu_booke_release(mmu_t, pmap_t); 355 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 356 static void mmu_booke_remove_all(mmu_t, vm_page_t); 357 static void mmu_booke_remove_write(mmu_t, vm_page_t); 358 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 359 static void mmu_booke_zero_page(mmu_t, vm_page_t); 360 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 361 static void mmu_booke_activate(mmu_t, struct thread *); 362 static void mmu_booke_deactivate(mmu_t, struct thread *); 363 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 364 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 365 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 366 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 367 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 368 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 369 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 370 static void mmu_booke_kremove(mmu_t, vm_offset_t); 371 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 372 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 373 vm_size_t); 374 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 375 void **); 376 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 377 void *); 378 static void mmu_booke_scan_init(mmu_t); 379 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 380 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 381 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 382 vm_size_t sz, vm_memattr_t mode); 383 384 static mmu_method_t mmu_booke_methods[] = { 385 /* pmap dispatcher interface */ 386 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 387 MMUMETHOD(mmu_copy, mmu_booke_copy), 388 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 389 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 390 MMUMETHOD(mmu_enter, mmu_booke_enter), 391 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 392 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 393 MMUMETHOD(mmu_extract, mmu_booke_extract), 394 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 395 MMUMETHOD(mmu_init, mmu_booke_init), 396 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 397 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 398 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 399 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 400 MMUMETHOD(mmu_map, mmu_booke_map), 401 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 402 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 403 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 404 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 405 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 406 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 407 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 408 MMUMETHOD(mmu_protect, mmu_booke_protect), 409 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 410 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 411 MMUMETHOD(mmu_release, mmu_booke_release), 412 MMUMETHOD(mmu_remove, mmu_booke_remove), 413 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 414 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 415 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 416 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 417 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 418 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 419 MMUMETHOD(mmu_activate, mmu_booke_activate), 420 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 421 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 422 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 423 424 /* Internal interfaces */ 425 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 426 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 427 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 428 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 429 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 430 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 431 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 432 MMUMETHOD(mmu_kremove, mmu_booke_kremove), 433 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 434 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 435 436 /* dumpsys() support */ 437 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 438 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 439 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 440 441 { 0, 0 } 442 }; 443 444 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 445 446 static __inline uint32_t 447 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 448 { 449 uint32_t attrib; 450 int i; 451 452 if (ma != VM_MEMATTR_DEFAULT) { 453 switch (ma) { 454 case VM_MEMATTR_UNCACHEABLE: 455 return (MAS2_I | MAS2_G); 456 case VM_MEMATTR_WRITE_COMBINING: 457 case VM_MEMATTR_WRITE_BACK: 458 case VM_MEMATTR_PREFETCHABLE: 459 return (MAS2_I); 460 case VM_MEMATTR_WRITE_THROUGH: 461 return (MAS2_W | MAS2_M); 462 case VM_MEMATTR_CACHEABLE: 463 return (MAS2_M); 464 } 465 } 466 467 /* 468 * Assume the page is cache inhibited and access is guarded unless 469 * it's in our available memory array. 470 */ 471 attrib = _TLB_ENTRY_IO; 472 for (i = 0; i < physmem_regions_sz; i++) { 473 if ((pa >= physmem_regions[i].mr_start) && 474 (pa < (physmem_regions[i].mr_start + 475 physmem_regions[i].mr_size))) { 476 attrib = _TLB_ENTRY_MEM; 477 break; 478 } 479 } 480 481 return (attrib); 482 } 483 484 static inline void 485 tlb_miss_lock(void) 486 { 487 #ifdef SMP 488 struct pcpu *pc; 489 490 if (!smp_started) 491 return; 492 493 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 494 if (pc != pcpup) { 495 496 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 497 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 498 499 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 500 ("tlb_miss_lock: tried to lock self")); 501 502 tlb_lock(pc->pc_booke_tlb_lock); 503 504 CTR1(KTR_PMAP, "%s: locked", __func__); 505 } 506 } 507 #endif 508 } 509 510 static inline void 511 tlb_miss_unlock(void) 512 { 513 #ifdef SMP 514 struct pcpu *pc; 515 516 if (!smp_started) 517 return; 518 519 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 520 if (pc != pcpup) { 521 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 522 __func__, pc->pc_cpuid); 523 524 tlb_unlock(pc->pc_booke_tlb_lock); 525 526 CTR1(KTR_PMAP, "%s: unlocked", __func__); 527 } 528 } 529 #endif 530 } 531 532 /* Return number of entries in TLB0. */ 533 static __inline void 534 tlb0_get_tlbconf(void) 535 { 536 uint32_t tlb0_cfg; 537 538 tlb0_cfg = mfspr(SPR_TLB0CFG); 539 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 540 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 541 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 542 } 543 544 /* Return number of entries in TLB1. */ 545 static __inline void 546 tlb1_get_tlbconf(void) 547 { 548 uint32_t tlb1_cfg; 549 550 tlb1_cfg = mfspr(SPR_TLB1CFG); 551 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 552 } 553 554 /**************************************************************************/ 555 /* Page table related */ 556 /**************************************************************************/ 557 558 #ifdef __powerpc64__ 559 /* Initialize pool of kva ptbl buffers. */ 560 static void 561 ptbl_init(void) 562 { 563 int i; 564 565 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 566 TAILQ_INIT(&ptbl_buf_freelist); 567 568 for (i = 0; i < PTBL_BUFS; i++) { 569 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + 570 i * MAX(PTBL_PAGES,PDIR_PAGES) * PAGE_SIZE; 571 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 572 } 573 } 574 575 /* Get an sf_buf from the freelist. */ 576 static struct ptbl_buf * 577 ptbl_buf_alloc(void) 578 { 579 struct ptbl_buf *buf; 580 581 mtx_lock(&ptbl_buf_freelist_lock); 582 buf = TAILQ_FIRST(&ptbl_buf_freelist); 583 if (buf != NULL) 584 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 585 mtx_unlock(&ptbl_buf_freelist_lock); 586 587 return (buf); 588 } 589 590 /* Return ptbl buff to free pool. */ 591 static void 592 ptbl_buf_free(struct ptbl_buf *buf) 593 { 594 mtx_lock(&ptbl_buf_freelist_lock); 595 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 596 mtx_unlock(&ptbl_buf_freelist_lock); 597 } 598 599 /* 600 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 601 */ 602 static void 603 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t * ptbl) 604 { 605 struct ptbl_buf *pbuf; 606 607 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) { 608 if (pbuf->kva == (vm_offset_t) ptbl) { 609 /* Remove from pmap ptbl buf list. */ 610 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 611 612 /* Free corresponding ptbl buf. */ 613 ptbl_buf_free(pbuf); 614 615 break; 616 } 617 } 618 } 619 620 /* Get a pointer to a PTE in a page table. */ 621 static __inline pte_t * 622 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 623 { 624 pte_t **pdir; 625 pte_t *ptbl; 626 627 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 628 629 pdir = pmap->pm_pp2d[PP2D_IDX(va)]; 630 if (!pdir) 631 return NULL; 632 ptbl = pdir[PDIR_IDX(va)]; 633 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL); 634 } 635 636 /* 637 * Search the list of allocated pdir bufs and find on list of allocated pdirs 638 */ 639 static void 640 ptbl_free_pmap_pdir(mmu_t mmu, pmap_t pmap, pte_t ** pdir) 641 { 642 struct ptbl_buf *pbuf; 643 644 TAILQ_FOREACH(pbuf, &pmap->pm_pdir_list, link) { 645 if (pbuf->kva == (vm_offset_t) pdir) { 646 /* Remove from pmap ptbl buf list. */ 647 TAILQ_REMOVE(&pmap->pm_pdir_list, pbuf, link); 648 649 /* Free corresponding pdir buf. */ 650 ptbl_buf_free(pbuf); 651 652 break; 653 } 654 } 655 } 656 /* Free pdir pages and invalidate pdir entry. */ 657 static void 658 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx) 659 { 660 pte_t **pdir; 661 vm_paddr_t pa; 662 vm_offset_t va; 663 vm_page_t m; 664 int i; 665 666 pdir = pmap->pm_pp2d[pp2d_idx]; 667 668 KASSERT((pdir != NULL), ("pdir_free: null pdir")); 669 670 pmap->pm_pp2d[pp2d_idx] = NULL; 671 672 for (i = 0; i < PDIR_PAGES; i++) { 673 va = ((vm_offset_t) pdir + (i * PAGE_SIZE)); 674 pa = pte_vatopa(mmu, kernel_pmap, va); 675 m = PHYS_TO_VM_PAGE(pa); 676 vm_page_free_zero(m); 677 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 678 pmap_kremove(va); 679 } 680 681 ptbl_free_pmap_pdir(mmu, pmap, pdir); 682 } 683 684 /* 685 * Decrement pdir pages hold count and attempt to free pdir pages. Called 686 * when removing directory entry from pdir. 687 * 688 * Return 1 if pdir pages were freed. 689 */ 690 static int 691 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx) 692 { 693 pte_t **pdir; 694 vm_paddr_t pa; 695 vm_page_t m; 696 int i; 697 698 KASSERT((pmap != kernel_pmap), 699 ("pdir_unhold: unholding kernel pdir!")); 700 701 pdir = pmap->pm_pp2d[pp2d_idx]; 702 703 KASSERT(((vm_offset_t) pdir >= VM_MIN_KERNEL_ADDRESS), 704 ("pdir_unhold: non kva pdir")); 705 706 /* decrement hold count */ 707 for (i = 0; i < PDIR_PAGES; i++) { 708 pa = pte_vatopa(mmu, kernel_pmap, 709 (vm_offset_t) pdir + (i * PAGE_SIZE)); 710 m = PHYS_TO_VM_PAGE(pa); 711 m->wire_count--; 712 } 713 714 /* 715 * Free pdir pages if there are no dir entries in this pdir. 716 * wire_count has the same value for all ptbl pages, so check the 717 * last page. 718 */ 719 if (m->wire_count == 0) { 720 pdir_free(mmu, pmap, pp2d_idx); 721 return (1); 722 } 723 return (0); 724 } 725 726 /* 727 * Increment hold count for pdir pages. This routine is used when new ptlb 728 * entry is being inserted into pdir. 729 */ 730 static void 731 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir) 732 { 733 vm_paddr_t pa; 734 vm_page_t m; 735 int i; 736 737 KASSERT((pmap != kernel_pmap), 738 ("pdir_hold: holding kernel pdir!")); 739 740 KASSERT((pdir != NULL), ("pdir_hold: null pdir")); 741 742 for (i = 0; i < PDIR_PAGES; i++) { 743 pa = pte_vatopa(mmu, kernel_pmap, 744 (vm_offset_t) pdir + (i * PAGE_SIZE)); 745 m = PHYS_TO_VM_PAGE(pa); 746 m->wire_count++; 747 } 748 } 749 750 /* Allocate page table. */ 751 static pte_t * 752 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx, 753 boolean_t nosleep) 754 { 755 vm_page_t mtbl [PTBL_PAGES]; 756 vm_page_t m; 757 struct ptbl_buf *pbuf; 758 unsigned int pidx; 759 pte_t *ptbl; 760 int i, j; 761 int req; 762 763 KASSERT((pdir[pdir_idx] == NULL), 764 ("%s: valid ptbl entry exists!", __func__)); 765 766 pbuf = ptbl_buf_alloc(); 767 if (pbuf == NULL) 768 panic("%s: couldn't alloc kernel virtual memory", __func__); 769 770 ptbl = (pte_t *) pbuf->kva; 771 772 for (i = 0; i < PTBL_PAGES; i++) { 773 pidx = (PTBL_PAGES * pdir_idx) + i; 774 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED; 775 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) { 776 PMAP_UNLOCK(pmap); 777 rw_wunlock(&pvh_global_lock); 778 if (nosleep) { 779 ptbl_free_pmap_ptbl(pmap, ptbl); 780 for (j = 0; j < i; j++) 781 vm_page_free(mtbl[j]); 782 atomic_subtract_int(&vm_cnt.v_wire_count, i); 783 return (NULL); 784 } 785 VM_WAIT; 786 rw_wlock(&pvh_global_lock); 787 PMAP_LOCK(pmap); 788 } 789 mtbl[i] = m; 790 } 791 792 /* Mapin allocated pages into kernel_pmap. */ 793 mmu_booke_qenter(mmu, (vm_offset_t) ptbl, mtbl, PTBL_PAGES); 794 /* Zero whole ptbl. */ 795 bzero((caddr_t) ptbl, PTBL_PAGES * PAGE_SIZE); 796 797 /* Add pbuf to the pmap ptbl bufs list. */ 798 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 799 800 return (ptbl); 801 } 802 803 /* Free ptbl pages and invalidate pdir entry. */ 804 static void 805 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx) 806 { 807 pte_t *ptbl; 808 vm_paddr_t pa; 809 vm_offset_t va; 810 vm_page_t m; 811 int i; 812 813 ptbl = pdir[pdir_idx]; 814 815 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 816 817 pdir[pdir_idx] = NULL; 818 819 for (i = 0; i < PTBL_PAGES; i++) { 820 va = ((vm_offset_t) ptbl + (i * PAGE_SIZE)); 821 pa = pte_vatopa(mmu, kernel_pmap, va); 822 m = PHYS_TO_VM_PAGE(pa); 823 vm_page_free_zero(m); 824 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 825 pmap_kremove(va); 826 } 827 828 ptbl_free_pmap_ptbl(pmap, ptbl); 829 } 830 831 /* 832 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called 833 * when removing pte entry from ptbl. 834 * 835 * Return 1 if ptbl pages were freed. 836 */ 837 static int 838 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va) 839 { 840 pte_t *ptbl; 841 vm_paddr_t pa; 842 vm_page_t m; 843 u_int pp2d_idx; 844 pte_t **pdir; 845 u_int pdir_idx; 846 int i; 847 848 pp2d_idx = PP2D_IDX(va); 849 pdir_idx = PDIR_IDX(va); 850 851 KASSERT((pmap != kernel_pmap), 852 ("ptbl_unhold: unholding kernel ptbl!")); 853 854 pdir = pmap->pm_pp2d[pp2d_idx]; 855 ptbl = pdir[pdir_idx]; 856 857 KASSERT(((vm_offset_t) ptbl >= VM_MIN_KERNEL_ADDRESS), 858 ("ptbl_unhold: non kva ptbl")); 859 860 /* decrement hold count */ 861 for (i = 0; i < PTBL_PAGES; i++) { 862 pa = pte_vatopa(mmu, kernel_pmap, 863 (vm_offset_t) ptbl + (i * PAGE_SIZE)); 864 m = PHYS_TO_VM_PAGE(pa); 865 m->wire_count--; 866 } 867 868 /* 869 * Free ptbl pages if there are no pte entries in this ptbl. 870 * wire_count has the same value for all ptbl pages, so check the 871 * last page. 872 */ 873 if (m->wire_count == 0) { 874 /* A pair of indirect entries might point to this ptbl page */ 875 #if 0 876 tlb_flush_entry(pmap, va & ~((2UL * PAGE_SIZE_1M) - 1), 877 TLB_SIZE_1M, MAS6_SIND); 878 tlb_flush_entry(pmap, (va & ~((2UL * PAGE_SIZE_1M) - 1)) | PAGE_SIZE_1M, 879 TLB_SIZE_1M, MAS6_SIND); 880 #endif 881 ptbl_free(mmu, pmap, pdir, pdir_idx); 882 pdir_unhold(mmu, pmap, pp2d_idx); 883 return (1); 884 } 885 return (0); 886 } 887 888 /* 889 * Increment hold count for ptbl pages. This routine is used when new pte 890 * entry is being inserted into ptbl. 891 */ 892 static void 893 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx) 894 { 895 vm_paddr_t pa; 896 pte_t *ptbl; 897 vm_page_t m; 898 int i; 899 900 KASSERT((pmap != kernel_pmap), 901 ("ptbl_hold: holding kernel ptbl!")); 902 903 ptbl = pdir[pdir_idx]; 904 905 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 906 907 for (i = 0; i < PTBL_PAGES; i++) { 908 pa = pte_vatopa(mmu, kernel_pmap, 909 (vm_offset_t) ptbl + (i * PAGE_SIZE)); 910 m = PHYS_TO_VM_PAGE(pa); 911 m->wire_count++; 912 } 913 } 914 #else 915 916 /* Initialize pool of kva ptbl buffers. */ 917 static void 918 ptbl_init(void) 919 { 920 int i; 921 922 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 923 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 924 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 925 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 926 927 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 928 TAILQ_INIT(&ptbl_buf_freelist); 929 930 for (i = 0; i < PTBL_BUFS; i++) { 931 ptbl_bufs[i].kva = 932 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 933 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 934 } 935 } 936 937 /* Get a ptbl_buf from the freelist. */ 938 static struct ptbl_buf * 939 ptbl_buf_alloc(void) 940 { 941 struct ptbl_buf *buf; 942 943 mtx_lock(&ptbl_buf_freelist_lock); 944 buf = TAILQ_FIRST(&ptbl_buf_freelist); 945 if (buf != NULL) 946 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 947 mtx_unlock(&ptbl_buf_freelist_lock); 948 949 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 950 951 return (buf); 952 } 953 954 /* Return ptbl buff to free pool. */ 955 static void 956 ptbl_buf_free(struct ptbl_buf *buf) 957 { 958 959 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 960 961 mtx_lock(&ptbl_buf_freelist_lock); 962 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 963 mtx_unlock(&ptbl_buf_freelist_lock); 964 } 965 966 /* 967 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 968 */ 969 static void 970 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 971 { 972 struct ptbl_buf *pbuf; 973 974 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 975 976 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 977 978 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 979 if (pbuf->kva == (vm_offset_t)ptbl) { 980 /* Remove from pmap ptbl buf list. */ 981 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 982 983 /* Free corresponding ptbl buf. */ 984 ptbl_buf_free(pbuf); 985 break; 986 } 987 } 988 989 /* Allocate page table. */ 990 static pte_t * 991 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 992 { 993 vm_page_t mtbl[PTBL_PAGES]; 994 vm_page_t m; 995 struct ptbl_buf *pbuf; 996 unsigned int pidx; 997 pte_t *ptbl; 998 int i, j; 999 1000 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1001 (pmap == kernel_pmap), pdir_idx); 1002 1003 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1004 ("ptbl_alloc: invalid pdir_idx")); 1005 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 1006 ("pte_alloc: valid ptbl entry exists!")); 1007 1008 pbuf = ptbl_buf_alloc(); 1009 if (pbuf == NULL) 1010 panic("pte_alloc: couldn't alloc kernel virtual memory"); 1011 1012 ptbl = (pte_t *)pbuf->kva; 1013 1014 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 1015 1016 for (i = 0; i < PTBL_PAGES; i++) { 1017 pidx = (PTBL_PAGES * pdir_idx) + i; 1018 while ((m = vm_page_alloc(NULL, pidx, 1019 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 1020 PMAP_UNLOCK(pmap); 1021 rw_wunlock(&pvh_global_lock); 1022 if (nosleep) { 1023 ptbl_free_pmap_ptbl(pmap, ptbl); 1024 for (j = 0; j < i; j++) 1025 vm_page_free(mtbl[j]); 1026 atomic_subtract_int(&vm_cnt.v_wire_count, i); 1027 return (NULL); 1028 } 1029 VM_WAIT; 1030 rw_wlock(&pvh_global_lock); 1031 PMAP_LOCK(pmap); 1032 } 1033 mtbl[i] = m; 1034 } 1035 1036 /* Map allocated pages into kernel_pmap. */ 1037 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 1038 1039 /* Zero whole ptbl. */ 1040 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 1041 1042 /* Add pbuf to the pmap ptbl bufs list. */ 1043 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 1044 1045 return (ptbl); 1046 } 1047 1048 /* Free ptbl pages and invalidate pdir entry. */ 1049 static void 1050 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1051 { 1052 pte_t *ptbl; 1053 vm_paddr_t pa; 1054 vm_offset_t va; 1055 vm_page_t m; 1056 int i; 1057 1058 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1059 (pmap == kernel_pmap), pdir_idx); 1060 1061 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1062 ("ptbl_free: invalid pdir_idx")); 1063 1064 ptbl = pmap->pm_pdir[pdir_idx]; 1065 1066 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 1067 1068 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 1069 1070 /* 1071 * Invalidate the pdir entry as soon as possible, so that other CPUs 1072 * don't attempt to look up the page tables we are releasing. 1073 */ 1074 mtx_lock_spin(&tlbivax_mutex); 1075 tlb_miss_lock(); 1076 1077 pmap->pm_pdir[pdir_idx] = NULL; 1078 1079 tlb_miss_unlock(); 1080 mtx_unlock_spin(&tlbivax_mutex); 1081 1082 for (i = 0; i < PTBL_PAGES; i++) { 1083 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 1084 pa = pte_vatopa(mmu, kernel_pmap, va); 1085 m = PHYS_TO_VM_PAGE(pa); 1086 vm_page_free_zero(m); 1087 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1088 mmu_booke_kremove(mmu, va); 1089 } 1090 1091 ptbl_free_pmap_ptbl(pmap, ptbl); 1092 } 1093 1094 /* 1095 * Decrement ptbl pages hold count and attempt to free ptbl pages. 1096 * Called when removing pte entry from ptbl. 1097 * 1098 * Return 1 if ptbl pages were freed. 1099 */ 1100 static int 1101 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1102 { 1103 pte_t *ptbl; 1104 vm_paddr_t pa; 1105 vm_page_t m; 1106 int i; 1107 1108 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 1109 (pmap == kernel_pmap), pdir_idx); 1110 1111 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1112 ("ptbl_unhold: invalid pdir_idx")); 1113 KASSERT((pmap != kernel_pmap), 1114 ("ptbl_unhold: unholding kernel ptbl!")); 1115 1116 ptbl = pmap->pm_pdir[pdir_idx]; 1117 1118 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 1119 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 1120 ("ptbl_unhold: non kva ptbl")); 1121 1122 /* decrement hold count */ 1123 for (i = 0; i < PTBL_PAGES; i++) { 1124 pa = pte_vatopa(mmu, kernel_pmap, 1125 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 1126 m = PHYS_TO_VM_PAGE(pa); 1127 m->wire_count--; 1128 } 1129 1130 /* 1131 * Free ptbl pages if there are no pte etries in this ptbl. 1132 * wire_count has the same value for all ptbl pages, so check the last 1133 * page. 1134 */ 1135 if (m->wire_count == 0) { 1136 ptbl_free(mmu, pmap, pdir_idx); 1137 1138 //debugf("ptbl_unhold: e (freed ptbl)\n"); 1139 return (1); 1140 } 1141 1142 return (0); 1143 } 1144 1145 /* 1146 * Increment hold count for ptbl pages. This routine is used when a new pte 1147 * entry is being inserted into the ptbl. 1148 */ 1149 static void 1150 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 1151 { 1152 vm_paddr_t pa; 1153 pte_t *ptbl; 1154 vm_page_t m; 1155 int i; 1156 1157 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 1158 pdir_idx); 1159 1160 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 1161 ("ptbl_hold: invalid pdir_idx")); 1162 KASSERT((pmap != kernel_pmap), 1163 ("ptbl_hold: holding kernel ptbl!")); 1164 1165 ptbl = pmap->pm_pdir[pdir_idx]; 1166 1167 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 1168 1169 for (i = 0; i < PTBL_PAGES; i++) { 1170 pa = pte_vatopa(mmu, kernel_pmap, 1171 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 1172 m = PHYS_TO_VM_PAGE(pa); 1173 m->wire_count++; 1174 } 1175 } 1176 #endif 1177 1178 /* Allocate pv_entry structure. */ 1179 pv_entry_t 1180 pv_alloc(void) 1181 { 1182 pv_entry_t pv; 1183 1184 pv_entry_count++; 1185 if (pv_entry_count > pv_entry_high_water) 1186 pagedaemon_wakeup(); 1187 pv = uma_zalloc(pvzone, M_NOWAIT); 1188 1189 return (pv); 1190 } 1191 1192 /* Free pv_entry structure. */ 1193 static __inline void 1194 pv_free(pv_entry_t pve) 1195 { 1196 1197 pv_entry_count--; 1198 uma_zfree(pvzone, pve); 1199 } 1200 1201 1202 /* Allocate and initialize pv_entry structure. */ 1203 static void 1204 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 1205 { 1206 pv_entry_t pve; 1207 1208 //int su = (pmap == kernel_pmap); 1209 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 1210 // (u_int32_t)pmap, va, (u_int32_t)m); 1211 1212 pve = pv_alloc(); 1213 if (pve == NULL) 1214 panic("pv_insert: no pv entries!"); 1215 1216 pve->pv_pmap = pmap; 1217 pve->pv_va = va; 1218 1219 /* add to pv_list */ 1220 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1221 rw_assert(&pvh_global_lock, RA_WLOCKED); 1222 1223 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 1224 1225 //debugf("pv_insert: e\n"); 1226 } 1227 1228 /* Destroy pv entry. */ 1229 static void 1230 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 1231 { 1232 pv_entry_t pve; 1233 1234 //int su = (pmap == kernel_pmap); 1235 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 1236 1237 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1238 rw_assert(&pvh_global_lock, RA_WLOCKED); 1239 1240 /* find pv entry */ 1241 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 1242 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 1243 /* remove from pv_list */ 1244 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 1245 if (TAILQ_EMPTY(&m->md.pv_list)) 1246 vm_page_aflag_clear(m, PGA_WRITEABLE); 1247 1248 /* free pv entry struct */ 1249 pv_free(pve); 1250 break; 1251 } 1252 } 1253 1254 //debugf("pv_remove: e\n"); 1255 } 1256 1257 #ifdef __powerpc64__ 1258 /* 1259 * Clean pte entry, try to free page table page if requested. 1260 * 1261 * Return 1 if ptbl pages were freed, otherwise return 0. 1262 */ 1263 static int 1264 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags) 1265 { 1266 vm_page_t m; 1267 pte_t *pte; 1268 1269 pte = pte_find(mmu, pmap, va); 1270 KASSERT(pte != NULL, ("%s: NULL pte", __func__)); 1271 1272 if (!PTE_ISVALID(pte)) 1273 return (0); 1274 1275 /* Get vm_page_t for mapped pte. */ 1276 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1277 1278 if (PTE_ISWIRED(pte)) 1279 pmap->pm_stats.wired_count--; 1280 1281 /* Handle managed entry. */ 1282 if (PTE_ISMANAGED(pte)) { 1283 1284 /* Handle modified pages. */ 1285 if (PTE_ISMODIFIED(pte)) 1286 vm_page_dirty(m); 1287 1288 /* Referenced pages. */ 1289 if (PTE_ISREFERENCED(pte)) 1290 vm_page_aflag_set(m, PGA_REFERENCED); 1291 1292 /* Remove pv_entry from pv_list. */ 1293 pv_remove(pmap, va, m); 1294 } 1295 mtx_lock_spin(&tlbivax_mutex); 1296 tlb_miss_lock(); 1297 1298 tlb0_flush_entry(va); 1299 *pte = 0; 1300 1301 tlb_miss_unlock(); 1302 mtx_unlock_spin(&tlbivax_mutex); 1303 1304 pmap->pm_stats.resident_count--; 1305 1306 if (flags & PTBL_UNHOLD) { 1307 return (ptbl_unhold(mmu, pmap, va)); 1308 } 1309 return (0); 1310 } 1311 1312 /* 1313 * allocate a page of pointers to page directories, do not preallocate the 1314 * page tables 1315 */ 1316 static pte_t ** 1317 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep) 1318 { 1319 vm_page_t mtbl [PDIR_PAGES]; 1320 vm_page_t m; 1321 struct ptbl_buf *pbuf; 1322 pte_t **pdir; 1323 unsigned int pidx; 1324 int i; 1325 int req; 1326 1327 pbuf = ptbl_buf_alloc(); 1328 1329 if (pbuf == NULL) 1330 panic("%s: couldn't alloc kernel virtual memory", __func__); 1331 1332 /* Allocate pdir pages, this will sleep! */ 1333 for (i = 0; i < PDIR_PAGES; i++) { 1334 pidx = (PDIR_PAGES * pp2d_idx) + i; 1335 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED; 1336 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) { 1337 PMAP_UNLOCK(pmap); 1338 VM_WAIT; 1339 PMAP_LOCK(pmap); 1340 } 1341 mtbl[i] = m; 1342 } 1343 1344 /* Mapin allocated pages into kernel_pmap. */ 1345 pdir = (pte_t **) pbuf->kva; 1346 pmap_qenter((vm_offset_t) pdir, mtbl, PDIR_PAGES); 1347 1348 /* Zero whole pdir. */ 1349 bzero((caddr_t) pdir, PDIR_PAGES * PAGE_SIZE); 1350 1351 /* Add pdir to the pmap pdir bufs list. */ 1352 TAILQ_INSERT_TAIL(&pmap->pm_pdir_list, pbuf, link); 1353 1354 return pdir; 1355 } 1356 1357 /* 1358 * Insert PTE for a given page and virtual address. 1359 */ 1360 static int 1361 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 1362 boolean_t nosleep) 1363 { 1364 unsigned int pp2d_idx = PP2D_IDX(va); 1365 unsigned int pdir_idx = PDIR_IDX(va); 1366 unsigned int ptbl_idx = PTBL_IDX(va); 1367 pte_t *ptbl, *pte; 1368 pte_t **pdir; 1369 1370 /* Get the page directory pointer. */ 1371 pdir = pmap->pm_pp2d[pp2d_idx]; 1372 if (pdir == NULL) 1373 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep); 1374 1375 /* Get the page table pointer. */ 1376 ptbl = pdir[pdir_idx]; 1377 1378 if (ptbl == NULL) { 1379 /* Allocate page table pages. */ 1380 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep); 1381 if (ptbl == NULL) { 1382 KASSERT(nosleep, ("nosleep and NULL ptbl")); 1383 return (ENOMEM); 1384 } 1385 } else { 1386 /* 1387 * Check if there is valid mapping for requested va, if there 1388 * is, remove it. 1389 */ 1390 pte = &pdir[pdir_idx][ptbl_idx]; 1391 if (PTE_ISVALID(pte)) { 1392 pte_remove(mmu, pmap, va, PTBL_HOLD); 1393 } else { 1394 /* 1395 * pte is not used, increment hold count for ptbl 1396 * pages. 1397 */ 1398 if (pmap != kernel_pmap) 1399 ptbl_hold(mmu, pmap, pdir, pdir_idx); 1400 } 1401 } 1402 1403 if (pdir[pdir_idx] == NULL) { 1404 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL) 1405 pdir_hold(mmu, pmap, pdir); 1406 pdir[pdir_idx] = ptbl; 1407 } 1408 if (pmap->pm_pp2d[pp2d_idx] == NULL) 1409 pmap->pm_pp2d[pp2d_idx] = pdir; 1410 1411 /* 1412 * Insert pv_entry into pv_list for mapped page if part of managed 1413 * memory. 1414 */ 1415 if ((m->oflags & VPO_UNMANAGED) == 0) { 1416 flags |= PTE_MANAGED; 1417 1418 /* Create and insert pv entry. */ 1419 pv_insert(pmap, va, m); 1420 } 1421 1422 mtx_lock_spin(&tlbivax_mutex); 1423 tlb_miss_lock(); 1424 1425 tlb0_flush_entry(va); 1426 pmap->pm_stats.resident_count++; 1427 pte = &pdir[pdir_idx][ptbl_idx]; 1428 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 1429 *pte |= (PTE_VALID | flags); 1430 1431 tlb_miss_unlock(); 1432 mtx_unlock_spin(&tlbivax_mutex); 1433 1434 return (0); 1435 } 1436 1437 /* Return the pa for the given pmap/va. */ 1438 static vm_paddr_t 1439 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1440 { 1441 vm_paddr_t pa = 0; 1442 pte_t *pte; 1443 1444 pte = pte_find(mmu, pmap, va); 1445 if ((pte != NULL) && PTE_ISVALID(pte)) 1446 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1447 return (pa); 1448 } 1449 1450 1451 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */ 1452 static void 1453 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1454 { 1455 int i, j; 1456 vm_offset_t va; 1457 pte_t *pte; 1458 1459 va = addr; 1460 /* Initialize kernel pdir */ 1461 for (i = 0; i < kernel_pdirs; i++) { 1462 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] = 1463 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES)); 1464 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES)); 1465 j < PDIR_NENTRIES; j++) { 1466 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] = 1467 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE * PDIR_PAGES) + 1468 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE * PTBL_PAGES)); 1469 } 1470 } 1471 1472 /* 1473 * Fill in PTEs covering kernel code and data. They are not required 1474 * for address translation, as this area is covered by static TLB1 1475 * entries, but for pte_vatopa() to work correctly with kernel area 1476 * addresses. 1477 */ 1478 for (va = addr; va < data_end; va += PAGE_SIZE) { 1479 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]); 1480 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1481 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1482 PTE_VALID | PTE_PS_4KB; 1483 } 1484 } 1485 #else 1486 /* 1487 * Clean pte entry, try to free page table page if requested. 1488 * 1489 * Return 1 if ptbl pages were freed, otherwise return 0. 1490 */ 1491 static int 1492 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 1493 { 1494 unsigned int pdir_idx = PDIR_IDX(va); 1495 unsigned int ptbl_idx = PTBL_IDX(va); 1496 vm_page_t m; 1497 pte_t *ptbl; 1498 pte_t *pte; 1499 1500 //int su = (pmap == kernel_pmap); 1501 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 1502 // su, (u_int32_t)pmap, va, flags); 1503 1504 ptbl = pmap->pm_pdir[pdir_idx]; 1505 KASSERT(ptbl, ("pte_remove: null ptbl")); 1506 1507 pte = &ptbl[ptbl_idx]; 1508 1509 if (pte == NULL || !PTE_ISVALID(pte)) 1510 return (0); 1511 1512 if (PTE_ISWIRED(pte)) 1513 pmap->pm_stats.wired_count--; 1514 1515 /* Get vm_page_t for mapped pte. */ 1516 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1517 1518 /* Handle managed entry. */ 1519 if (PTE_ISMANAGED(pte)) { 1520 1521 if (PTE_ISMODIFIED(pte)) 1522 vm_page_dirty(m); 1523 1524 if (PTE_ISREFERENCED(pte)) 1525 vm_page_aflag_set(m, PGA_REFERENCED); 1526 1527 pv_remove(pmap, va, m); 1528 } else if (m->md.pv_tracked) { 1529 /* 1530 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is 1531 * used. This is needed by the NCSW support code for fast 1532 * VA<->PA translation. 1533 */ 1534 pv_remove(pmap, va, m); 1535 if (TAILQ_EMPTY(&m->md.pv_list)) 1536 m->md.pv_tracked = false; 1537 } 1538 1539 mtx_lock_spin(&tlbivax_mutex); 1540 tlb_miss_lock(); 1541 1542 tlb0_flush_entry(va); 1543 *pte = 0; 1544 1545 tlb_miss_unlock(); 1546 mtx_unlock_spin(&tlbivax_mutex); 1547 1548 pmap->pm_stats.resident_count--; 1549 1550 if (flags & PTBL_UNHOLD) { 1551 //debugf("pte_remove: e (unhold)\n"); 1552 return (ptbl_unhold(mmu, pmap, pdir_idx)); 1553 } 1554 1555 //debugf("pte_remove: e\n"); 1556 return (0); 1557 } 1558 1559 /* 1560 * Insert PTE for a given page and virtual address. 1561 */ 1562 static int 1563 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 1564 boolean_t nosleep) 1565 { 1566 unsigned int pdir_idx = PDIR_IDX(va); 1567 unsigned int ptbl_idx = PTBL_IDX(va); 1568 pte_t *ptbl, *pte; 1569 1570 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 1571 pmap == kernel_pmap, pmap, va); 1572 1573 /* Get the page table pointer. */ 1574 ptbl = pmap->pm_pdir[pdir_idx]; 1575 1576 if (ptbl == NULL) { 1577 /* Allocate page table pages. */ 1578 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 1579 if (ptbl == NULL) { 1580 KASSERT(nosleep, ("nosleep and NULL ptbl")); 1581 return (ENOMEM); 1582 } 1583 } else { 1584 /* 1585 * Check if there is valid mapping for requested 1586 * va, if there is, remove it. 1587 */ 1588 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 1589 if (PTE_ISVALID(pte)) { 1590 pte_remove(mmu, pmap, va, PTBL_HOLD); 1591 } else { 1592 /* 1593 * pte is not used, increment hold count 1594 * for ptbl pages. 1595 */ 1596 if (pmap != kernel_pmap) 1597 ptbl_hold(mmu, pmap, pdir_idx); 1598 } 1599 } 1600 1601 /* 1602 * Insert pv_entry into pv_list for mapped page if part of managed 1603 * memory. 1604 */ 1605 if ((m->oflags & VPO_UNMANAGED) == 0) { 1606 flags |= PTE_MANAGED; 1607 1608 /* Create and insert pv entry. */ 1609 pv_insert(pmap, va, m); 1610 } 1611 1612 pmap->pm_stats.resident_count++; 1613 1614 mtx_lock_spin(&tlbivax_mutex); 1615 tlb_miss_lock(); 1616 1617 tlb0_flush_entry(va); 1618 if (pmap->pm_pdir[pdir_idx] == NULL) { 1619 /* 1620 * If we just allocated a new page table, hook it in 1621 * the pdir. 1622 */ 1623 pmap->pm_pdir[pdir_idx] = ptbl; 1624 } 1625 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 1626 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 1627 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 1628 1629 tlb_miss_unlock(); 1630 mtx_unlock_spin(&tlbivax_mutex); 1631 return (0); 1632 } 1633 1634 /* Return the pa for the given pmap/va. */ 1635 static vm_paddr_t 1636 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1637 { 1638 vm_paddr_t pa = 0; 1639 pte_t *pte; 1640 1641 pte = pte_find(mmu, pmap, va); 1642 if ((pte != NULL) && PTE_ISVALID(pte)) 1643 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1644 return (pa); 1645 } 1646 1647 /* Get a pointer to a PTE in a page table. */ 1648 static pte_t * 1649 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1650 { 1651 unsigned int pdir_idx = PDIR_IDX(va); 1652 unsigned int ptbl_idx = PTBL_IDX(va); 1653 1654 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1655 1656 if (pmap->pm_pdir[pdir_idx]) 1657 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1658 1659 return (NULL); 1660 } 1661 1662 /* Set up kernel page tables. */ 1663 static void 1664 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1665 { 1666 int i; 1667 vm_offset_t va; 1668 pte_t *pte; 1669 1670 /* Initialize kernel pdir */ 1671 for (i = 0; i < kernel_ptbls; i++) 1672 kernel_pmap->pm_pdir[kptbl_min + i] = 1673 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1674 1675 /* 1676 * Fill in PTEs covering kernel code and data. They are not required 1677 * for address translation, as this area is covered by static TLB1 1678 * entries, but for pte_vatopa() to work correctly with kernel area 1679 * addresses. 1680 */ 1681 for (va = addr; va < data_end; va += PAGE_SIZE) { 1682 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1683 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1684 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1685 PTE_VALID | PTE_PS_4KB; 1686 } 1687 } 1688 #endif 1689 1690 /**************************************************************************/ 1691 /* PMAP related */ 1692 /**************************************************************************/ 1693 1694 /* 1695 * This is called during booke_init, before the system is really initialized. 1696 */ 1697 static void 1698 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1699 { 1700 vm_paddr_t phys_kernelend; 1701 struct mem_region *mp, *mp1; 1702 int cnt, i, j; 1703 vm_paddr_t s, e, sz; 1704 vm_paddr_t physsz, hwphyssz; 1705 u_int phys_avail_count; 1706 vm_size_t kstack0_sz; 1707 vm_offset_t kernel_pdir, kstack0; 1708 vm_paddr_t kstack0_phys; 1709 void *dpcpu; 1710 1711 debugf("mmu_booke_bootstrap: entered\n"); 1712 1713 /* Set interesting system properties */ 1714 hw_direct_map = 0; 1715 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__) 1716 elf32_nxstack = 1; 1717 #endif 1718 1719 /* Initialize invalidation mutex */ 1720 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1721 1722 /* Read TLB0 size and associativity. */ 1723 tlb0_get_tlbconf(); 1724 1725 /* 1726 * Align kernel start and end address (kernel image). 1727 * Note that kernel end does not necessarily relate to kernsize. 1728 * kernsize is the size of the kernel that is actually mapped. 1729 */ 1730 kernstart = trunc_page(start); 1731 data_start = round_page(kernelend); 1732 data_end = data_start; 1733 1734 /* 1735 * Addresses of preloaded modules (like file systems) use 1736 * physical addresses. Make sure we relocate those into 1737 * virtual addresses. 1738 */ 1739 preload_addr_relocate = kernstart - kernload; 1740 1741 /* Allocate the dynamic per-cpu area. */ 1742 dpcpu = (void *)data_end; 1743 data_end += DPCPU_SIZE; 1744 1745 /* Allocate space for the message buffer. */ 1746 msgbufp = (struct msgbuf *)data_end; 1747 data_end += msgbufsize; 1748 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1749 (uintptr_t)msgbufp, data_end); 1750 1751 data_end = round_page(data_end); 1752 1753 /* Allocate space for ptbl_bufs. */ 1754 ptbl_bufs = (struct ptbl_buf *)data_end; 1755 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1756 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1757 (uintptr_t)ptbl_bufs, data_end); 1758 1759 data_end = round_page(data_end); 1760 1761 /* Allocate PTE tables for kernel KVA. */ 1762 kernel_pdir = data_end; 1763 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS, 1764 PDIR_SIZE); 1765 #ifdef __powerpc64__ 1766 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES); 1767 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE; 1768 #endif 1769 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1770 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1771 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n", 1772 kernel_pdir, data_end); 1773 1774 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end); 1775 if (data_end - kernstart > kernsize) { 1776 kernsize += tlb1_mapin_region(kernstart + kernsize, 1777 kernload + kernsize, (data_end - kernstart) - kernsize); 1778 } 1779 data_end = kernstart + kernsize; 1780 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end); 1781 1782 /* 1783 * Clear the structures - note we can only do it safely after the 1784 * possible additional TLB1 translations are in place (above) so that 1785 * all range up to the currently calculated 'data_end' is covered. 1786 */ 1787 dpcpu_init(dpcpu, 0); 1788 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1789 #ifdef __powerpc64__ 1790 memset((void *)kernel_pdir, 0, 1791 kernel_pdirs * PDIR_PAGES * PAGE_SIZE + 1792 kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1793 #else 1794 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1795 #endif 1796 1797 /*******************************************************/ 1798 /* Set the start and end of kva. */ 1799 /*******************************************************/ 1800 virtual_avail = round_page(data_end); 1801 virtual_end = VM_MAX_KERNEL_ADDRESS; 1802 1803 /* Allocate KVA space for page zero/copy operations. */ 1804 zero_page_va = virtual_avail; 1805 virtual_avail += PAGE_SIZE; 1806 copy_page_src_va = virtual_avail; 1807 virtual_avail += PAGE_SIZE; 1808 copy_page_dst_va = virtual_avail; 1809 virtual_avail += PAGE_SIZE; 1810 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1811 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1812 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1813 1814 /* Initialize page zero/copy mutexes. */ 1815 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1816 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1817 1818 /* Allocate KVA space for ptbl bufs. */ 1819 ptbl_buf_pool_vabase = virtual_avail; 1820 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1821 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1822 ptbl_buf_pool_vabase, virtual_avail); 1823 1824 /* Calculate corresponding physical addresses for the kernel region. */ 1825 phys_kernelend = kernload + kernsize; 1826 debugf("kernel image and allocated data:\n"); 1827 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1828 debugf(" kernstart = 0x%08x\n", kernstart); 1829 debugf(" kernsize = 0x%08x\n", kernsize); 1830 1831 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1832 panic("mmu_booke_bootstrap: phys_avail too small"); 1833 1834 /* 1835 * Remove kernel physical address range from avail regions list. Page 1836 * align all regions. Non-page aligned memory isn't very interesting 1837 * to us. Also, sort the entries for ascending addresses. 1838 */ 1839 1840 /* Retrieve phys/avail mem regions */ 1841 mem_regions(&physmem_regions, &physmem_regions_sz, 1842 &availmem_regions, &availmem_regions_sz); 1843 sz = 0; 1844 cnt = availmem_regions_sz; 1845 debugf("processing avail regions:\n"); 1846 for (mp = availmem_regions; mp->mr_size; mp++) { 1847 s = mp->mr_start; 1848 e = mp->mr_start + mp->mr_size; 1849 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1850 /* Check whether this region holds all of the kernel. */ 1851 if (s < kernload && e > phys_kernelend) { 1852 availmem_regions[cnt].mr_start = phys_kernelend; 1853 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1854 e = kernload; 1855 } 1856 /* Look whether this regions starts within the kernel. */ 1857 if (s >= kernload && s < phys_kernelend) { 1858 if (e <= phys_kernelend) 1859 goto empty; 1860 s = phys_kernelend; 1861 } 1862 /* Now look whether this region ends within the kernel. */ 1863 if (e > kernload && e <= phys_kernelend) { 1864 if (s >= kernload) 1865 goto empty; 1866 e = kernload; 1867 } 1868 /* Now page align the start and size of the region. */ 1869 s = round_page(s); 1870 e = trunc_page(e); 1871 if (e < s) 1872 e = s; 1873 sz = e - s; 1874 debugf("%09jx-%09jx = %jx\n", 1875 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1876 1877 /* Check whether some memory is left here. */ 1878 if (sz == 0) { 1879 empty: 1880 memmove(mp, mp + 1, 1881 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1882 cnt--; 1883 mp--; 1884 continue; 1885 } 1886 1887 /* Do an insertion sort. */ 1888 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1889 if (s < mp1->mr_start) 1890 break; 1891 if (mp1 < mp) { 1892 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1893 mp1->mr_start = s; 1894 mp1->mr_size = sz; 1895 } else { 1896 mp->mr_start = s; 1897 mp->mr_size = sz; 1898 } 1899 } 1900 availmem_regions_sz = cnt; 1901 1902 /*******************************************************/ 1903 /* Steal physical memory for kernel stack from the end */ 1904 /* of the first avail region */ 1905 /*******************************************************/ 1906 kstack0_sz = kstack_pages * PAGE_SIZE; 1907 kstack0_phys = availmem_regions[0].mr_start + 1908 availmem_regions[0].mr_size; 1909 kstack0_phys -= kstack0_sz; 1910 availmem_regions[0].mr_size -= kstack0_sz; 1911 1912 /*******************************************************/ 1913 /* Fill in phys_avail table, based on availmem_regions */ 1914 /*******************************************************/ 1915 phys_avail_count = 0; 1916 physsz = 0; 1917 hwphyssz = 0; 1918 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1919 1920 debugf("fill in phys_avail:\n"); 1921 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1922 1923 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1924 (uintmax_t)availmem_regions[i].mr_start, 1925 (uintmax_t)availmem_regions[i].mr_start + 1926 availmem_regions[i].mr_size, 1927 (uintmax_t)availmem_regions[i].mr_size); 1928 1929 if (hwphyssz != 0 && 1930 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1931 debugf(" hw.physmem adjust\n"); 1932 if (physsz < hwphyssz) { 1933 phys_avail[j] = availmem_regions[i].mr_start; 1934 phys_avail[j + 1] = 1935 availmem_regions[i].mr_start + 1936 hwphyssz - physsz; 1937 physsz = hwphyssz; 1938 phys_avail_count++; 1939 } 1940 break; 1941 } 1942 1943 phys_avail[j] = availmem_regions[i].mr_start; 1944 phys_avail[j + 1] = availmem_regions[i].mr_start + 1945 availmem_regions[i].mr_size; 1946 phys_avail_count++; 1947 physsz += availmem_regions[i].mr_size; 1948 } 1949 physmem = btoc(physsz); 1950 1951 /* Calculate the last available physical address. */ 1952 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1953 ; 1954 Maxmem = powerpc_btop(phys_avail[i + 1]); 1955 1956 debugf("Maxmem = 0x%08lx\n", Maxmem); 1957 debugf("phys_avail_count = %d\n", phys_avail_count); 1958 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1959 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1960 1961 /*******************************************************/ 1962 /* Initialize (statically allocated) kernel pmap. */ 1963 /*******************************************************/ 1964 PMAP_LOCK_INIT(kernel_pmap); 1965 #ifndef __powerpc64__ 1966 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1967 #endif 1968 1969 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap); 1970 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir); 1971 for (i = 0; i < MAXCPU; i++) { 1972 kernel_pmap->pm_tid[i] = TID_KERNEL; 1973 1974 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1975 tidbusy[i][TID_KERNEL] = kernel_pmap; 1976 } 1977 1978 /* Mark kernel_pmap active on all CPUs */ 1979 CPU_FILL(&kernel_pmap->pm_active); 1980 1981 /* 1982 * Initialize the global pv list lock. 1983 */ 1984 rw_init(&pvh_global_lock, "pmap pv global"); 1985 1986 /*******************************************************/ 1987 /* Final setup */ 1988 /*******************************************************/ 1989 1990 /* Enter kstack0 into kernel map, provide guard page */ 1991 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1992 thread0.td_kstack = kstack0; 1993 thread0.td_kstack_pages = kstack_pages; 1994 1995 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1996 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1997 kstack0_phys, kstack0_phys + kstack0_sz); 1998 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n", 1999 kstack0, kstack0 + kstack0_sz); 2000 2001 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 2002 for (i = 0; i < kstack_pages; i++) { 2003 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 2004 kstack0 += PAGE_SIZE; 2005 kstack0_phys += PAGE_SIZE; 2006 } 2007 2008 pmap_bootstrapped = 1; 2009 2010 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail); 2011 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end); 2012 2013 debugf("mmu_booke_bootstrap: exit\n"); 2014 } 2015 2016 #ifdef SMP 2017 void 2018 tlb1_ap_prep(void) 2019 { 2020 tlb_entry_t *e, tmp; 2021 unsigned int i; 2022 2023 /* Prepare TLB1 image for AP processors */ 2024 e = __boot_tlb1; 2025 for (i = 0; i < TLB1_ENTRIES; i++) { 2026 tlb1_read_entry(&tmp, i); 2027 2028 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 2029 memcpy(e++, &tmp, sizeof(tmp)); 2030 } 2031 } 2032 2033 void 2034 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 2035 { 2036 int i; 2037 2038 /* 2039 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 2040 * have the snapshot of its contents in the s/w __boot_tlb1[] table 2041 * created by tlb1_ap_prep(), so use these values directly to 2042 * (re)program AP's TLB1 hardware. 2043 * 2044 * Start at index 1 because index 0 has the kernel map. 2045 */ 2046 for (i = 1; i < TLB1_ENTRIES; i++) { 2047 if (__boot_tlb1[i].mas1 & MAS1_VALID) 2048 tlb1_write_entry(&__boot_tlb1[i], i); 2049 } 2050 2051 set_mas4_defaults(); 2052 } 2053 #endif 2054 2055 static void 2056 booke_pmap_init_qpages(void) 2057 { 2058 struct pcpu *pc; 2059 int i; 2060 2061 CPU_FOREACH(i) { 2062 pc = pcpu_find(i); 2063 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 2064 if (pc->pc_qmap_addr == 0) 2065 panic("pmap_init_qpages: unable to allocate KVA"); 2066 } 2067 } 2068 2069 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 2070 2071 /* 2072 * Get the physical page address for the given pmap/virtual address. 2073 */ 2074 static vm_paddr_t 2075 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 2076 { 2077 vm_paddr_t pa; 2078 2079 PMAP_LOCK(pmap); 2080 pa = pte_vatopa(mmu, pmap, va); 2081 PMAP_UNLOCK(pmap); 2082 2083 return (pa); 2084 } 2085 2086 /* 2087 * Extract the physical page address associated with the given 2088 * kernel virtual address. 2089 */ 2090 static vm_paddr_t 2091 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 2092 { 2093 tlb_entry_t e; 2094 vm_paddr_t p; 2095 int i; 2096 2097 p = pte_vatopa(mmu, kernel_pmap, va); 2098 2099 if (p == 0) { 2100 /* Check TLB1 mappings */ 2101 for (i = 0; i < TLB1_ENTRIES; i++) { 2102 tlb1_read_entry(&e, i); 2103 if (!(e.mas1 & MAS1_VALID)) 2104 continue; 2105 if (va >= e.virt && va < e.virt + e.size) 2106 return (e.phys + (va - e.virt)); 2107 } 2108 } 2109 2110 return (p); 2111 } 2112 2113 /* 2114 * Initialize the pmap module. 2115 * Called by vm_init, to initialize any structures that the pmap 2116 * system needs to map virtual memory. 2117 */ 2118 static void 2119 mmu_booke_init(mmu_t mmu) 2120 { 2121 int shpgperproc = PMAP_SHPGPERPROC; 2122 2123 /* 2124 * Initialize the address space (zone) for the pv entries. Set a 2125 * high water mark so that the system can recover from excessive 2126 * numbers of pv entries. 2127 */ 2128 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 2129 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 2130 2131 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 2132 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 2133 2134 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 2135 pv_entry_high_water = 9 * (pv_entry_max / 10); 2136 2137 uma_zone_reserve_kva(pvzone, pv_entry_max); 2138 2139 /* Pre-fill pvzone with initial number of pv entries. */ 2140 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 2141 2142 /* Initialize ptbl allocation. */ 2143 ptbl_init(); 2144 } 2145 2146 /* 2147 * Map a list of wired pages into kernel virtual address space. This is 2148 * intended for temporary mappings which do not need page modification or 2149 * references recorded. Existing mappings in the region are overwritten. 2150 */ 2151 static void 2152 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 2153 { 2154 vm_offset_t va; 2155 2156 va = sva; 2157 while (count-- > 0) { 2158 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2159 va += PAGE_SIZE; 2160 m++; 2161 } 2162 } 2163 2164 /* 2165 * Remove page mappings from kernel virtual address space. Intended for 2166 * temporary mappings entered by mmu_booke_qenter. 2167 */ 2168 static void 2169 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 2170 { 2171 vm_offset_t va; 2172 2173 va = sva; 2174 while (count-- > 0) { 2175 mmu_booke_kremove(mmu, va); 2176 va += PAGE_SIZE; 2177 } 2178 } 2179 2180 /* 2181 * Map a wired page into kernel virtual address space. 2182 */ 2183 static void 2184 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 2185 { 2186 2187 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 2188 } 2189 2190 static void 2191 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 2192 { 2193 uint32_t flags; 2194 pte_t *pte; 2195 2196 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 2197 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 2198 2199 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2200 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 2201 flags |= PTE_PS_4KB; 2202 2203 pte = pte_find(mmu, kernel_pmap, va); 2204 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE")); 2205 2206 mtx_lock_spin(&tlbivax_mutex); 2207 tlb_miss_lock(); 2208 2209 if (PTE_ISVALID(pte)) { 2210 2211 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 2212 2213 /* Flush entry from TLB0 */ 2214 tlb0_flush_entry(va); 2215 } 2216 2217 *pte = PTE_RPN_FROM_PA(pa) | flags; 2218 2219 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 2220 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 2221 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 2222 2223 /* Flush the real memory from the instruction cache. */ 2224 if ((flags & (PTE_I | PTE_G)) == 0) 2225 __syncicache((void *)va, PAGE_SIZE); 2226 2227 tlb_miss_unlock(); 2228 mtx_unlock_spin(&tlbivax_mutex); 2229 } 2230 2231 /* 2232 * Remove a page from kernel page table. 2233 */ 2234 static void 2235 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 2236 { 2237 pte_t *pte; 2238 2239 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 2240 2241 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 2242 (va <= VM_MAX_KERNEL_ADDRESS)), 2243 ("mmu_booke_kremove: invalid va")); 2244 2245 pte = pte_find(mmu, kernel_pmap, va); 2246 2247 if (!PTE_ISVALID(pte)) { 2248 2249 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 2250 2251 return; 2252 } 2253 2254 mtx_lock_spin(&tlbivax_mutex); 2255 tlb_miss_lock(); 2256 2257 /* Invalidate entry in TLB0, update PTE. */ 2258 tlb0_flush_entry(va); 2259 *pte = 0; 2260 2261 tlb_miss_unlock(); 2262 mtx_unlock_spin(&tlbivax_mutex); 2263 } 2264 2265 /* 2266 * Initialize pmap associated with process 0. 2267 */ 2268 static void 2269 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 2270 { 2271 2272 PMAP_LOCK_INIT(pmap); 2273 mmu_booke_pinit(mmu, pmap); 2274 PCPU_SET(curpmap, pmap); 2275 } 2276 2277 /* 2278 * Initialize a preallocated and zeroed pmap structure, 2279 * such as one in a vmspace structure. 2280 */ 2281 static void 2282 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 2283 { 2284 int i; 2285 2286 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 2287 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 2288 2289 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 2290 2291 for (i = 0; i < MAXCPU; i++) 2292 pmap->pm_tid[i] = TID_NONE; 2293 CPU_ZERO(&kernel_pmap->pm_active); 2294 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2295 #ifdef __powerpc64__ 2296 bzero(&pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES); 2297 TAILQ_INIT(&pmap->pm_pdir_list); 2298 #else 2299 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 2300 #endif 2301 TAILQ_INIT(&pmap->pm_ptbl_list); 2302 } 2303 2304 /* 2305 * Release any resources held by the given physical map. 2306 * Called when a pmap initialized by mmu_booke_pinit is being released. 2307 * Should only be called if the map contains no valid mappings. 2308 */ 2309 static void 2310 mmu_booke_release(mmu_t mmu, pmap_t pmap) 2311 { 2312 2313 KASSERT(pmap->pm_stats.resident_count == 0, 2314 ("pmap_release: pmap resident count %ld != 0", 2315 pmap->pm_stats.resident_count)); 2316 } 2317 2318 /* 2319 * Insert the given physical page at the specified virtual address in the 2320 * target physical map with the protection requested. If specified the page 2321 * will be wired down. 2322 */ 2323 static int 2324 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2325 vm_prot_t prot, u_int flags, int8_t psind) 2326 { 2327 int error; 2328 2329 rw_wlock(&pvh_global_lock); 2330 PMAP_LOCK(pmap); 2331 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 2332 PMAP_UNLOCK(pmap); 2333 rw_wunlock(&pvh_global_lock); 2334 return (error); 2335 } 2336 2337 static int 2338 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2339 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 2340 { 2341 pte_t *pte; 2342 vm_paddr_t pa; 2343 uint32_t flags; 2344 int error, su, sync; 2345 2346 pa = VM_PAGE_TO_PHYS(m); 2347 su = (pmap == kernel_pmap); 2348 sync = 0; 2349 2350 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 2351 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 2352 // (u_int32_t)pmap, su, pmap->pm_tid, 2353 // (u_int32_t)m, va, pa, prot, flags); 2354 2355 if (su) { 2356 KASSERT(((va >= virtual_avail) && 2357 (va <= VM_MAX_KERNEL_ADDRESS)), 2358 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 2359 } else { 2360 KASSERT((va <= VM_MAXUSER_ADDRESS), 2361 ("mmu_booke_enter_locked: user pmap, non user va")); 2362 } 2363 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2364 VM_OBJECT_ASSERT_LOCKED(m->object); 2365 2366 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2367 2368 /* 2369 * If there is an existing mapping, and the physical address has not 2370 * changed, must be protection or wiring change. 2371 */ 2372 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 2373 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 2374 2375 /* 2376 * Before actually updating pte->flags we calculate and 2377 * prepare its new value in a helper var. 2378 */ 2379 flags = *pte; 2380 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 2381 2382 /* Wiring change, just update stats. */ 2383 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 2384 if (!PTE_ISWIRED(pte)) { 2385 flags |= PTE_WIRED; 2386 pmap->pm_stats.wired_count++; 2387 } 2388 } else { 2389 if (PTE_ISWIRED(pte)) { 2390 flags &= ~PTE_WIRED; 2391 pmap->pm_stats.wired_count--; 2392 } 2393 } 2394 2395 if (prot & VM_PROT_WRITE) { 2396 /* Add write permissions. */ 2397 flags |= PTE_SW; 2398 if (!su) 2399 flags |= PTE_UW; 2400 2401 if ((flags & PTE_MANAGED) != 0) 2402 vm_page_aflag_set(m, PGA_WRITEABLE); 2403 } else { 2404 /* Handle modified pages, sense modify status. */ 2405 2406 /* 2407 * The PTE_MODIFIED flag could be set by underlying 2408 * TLB misses since we last read it (above), possibly 2409 * other CPUs could update it so we check in the PTE 2410 * directly rather than rely on that saved local flags 2411 * copy. 2412 */ 2413 if (PTE_ISMODIFIED(pte)) 2414 vm_page_dirty(m); 2415 } 2416 2417 if (prot & VM_PROT_EXECUTE) { 2418 flags |= PTE_SX; 2419 if (!su) 2420 flags |= PTE_UX; 2421 2422 /* 2423 * Check existing flags for execute permissions: if we 2424 * are turning execute permissions on, icache should 2425 * be flushed. 2426 */ 2427 if ((*pte & (PTE_UX | PTE_SX)) == 0) 2428 sync++; 2429 } 2430 2431 flags &= ~PTE_REFERENCED; 2432 2433 /* 2434 * The new flags value is all calculated -- only now actually 2435 * update the PTE. 2436 */ 2437 mtx_lock_spin(&tlbivax_mutex); 2438 tlb_miss_lock(); 2439 2440 tlb0_flush_entry(va); 2441 *pte &= ~PTE_FLAGS_MASK; 2442 *pte |= flags; 2443 2444 tlb_miss_unlock(); 2445 mtx_unlock_spin(&tlbivax_mutex); 2446 2447 } else { 2448 /* 2449 * If there is an existing mapping, but it's for a different 2450 * physical address, pte_enter() will delete the old mapping. 2451 */ 2452 //if ((pte != NULL) && PTE_ISVALID(pte)) 2453 // debugf("mmu_booke_enter_locked: replace\n"); 2454 //else 2455 // debugf("mmu_booke_enter_locked: new\n"); 2456 2457 /* Now set up the flags and install the new mapping. */ 2458 flags = (PTE_SR | PTE_VALID); 2459 flags |= PTE_M; 2460 2461 if (!su) 2462 flags |= PTE_UR; 2463 2464 if (prot & VM_PROT_WRITE) { 2465 flags |= PTE_SW; 2466 if (!su) 2467 flags |= PTE_UW; 2468 2469 if ((m->oflags & VPO_UNMANAGED) == 0) 2470 vm_page_aflag_set(m, PGA_WRITEABLE); 2471 } 2472 2473 if (prot & VM_PROT_EXECUTE) { 2474 flags |= PTE_SX; 2475 if (!su) 2476 flags |= PTE_UX; 2477 } 2478 2479 /* If its wired update stats. */ 2480 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 2481 flags |= PTE_WIRED; 2482 2483 error = pte_enter(mmu, pmap, m, va, flags, 2484 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 2485 if (error != 0) 2486 return (KERN_RESOURCE_SHORTAGE); 2487 2488 if ((flags & PMAP_ENTER_WIRED) != 0) 2489 pmap->pm_stats.wired_count++; 2490 2491 /* Flush the real memory from the instruction cache. */ 2492 if (prot & VM_PROT_EXECUTE) 2493 sync++; 2494 } 2495 2496 if (sync && (su || pmap == PCPU_GET(curpmap))) { 2497 __syncicache((void *)va, PAGE_SIZE); 2498 sync = 0; 2499 } 2500 2501 return (KERN_SUCCESS); 2502 } 2503 2504 /* 2505 * Maps a sequence of resident pages belonging to the same object. 2506 * The sequence begins with the given page m_start. This page is 2507 * mapped at the given virtual address start. Each subsequent page is 2508 * mapped at a virtual address that is offset from start by the same 2509 * amount as the page is offset from m_start within the object. The 2510 * last page in the sequence is the page with the largest offset from 2511 * m_start that can be mapped at a virtual address less than the given 2512 * virtual address end. Not every virtual page between start and end 2513 * is mapped; only those for which a resident page exists with the 2514 * corresponding offset from m_start are mapped. 2515 */ 2516 static void 2517 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 2518 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 2519 { 2520 vm_page_t m; 2521 vm_pindex_t diff, psize; 2522 2523 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2524 2525 psize = atop(end - start); 2526 m = m_start; 2527 rw_wlock(&pvh_global_lock); 2528 PMAP_LOCK(pmap); 2529 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2530 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 2531 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 2532 PMAP_ENTER_NOSLEEP, 0); 2533 m = TAILQ_NEXT(m, listq); 2534 } 2535 rw_wunlock(&pvh_global_lock); 2536 PMAP_UNLOCK(pmap); 2537 } 2538 2539 static void 2540 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 2541 vm_prot_t prot) 2542 { 2543 2544 rw_wlock(&pvh_global_lock); 2545 PMAP_LOCK(pmap); 2546 mmu_booke_enter_locked(mmu, pmap, va, m, 2547 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 2548 0); 2549 rw_wunlock(&pvh_global_lock); 2550 PMAP_UNLOCK(pmap); 2551 } 2552 2553 /* 2554 * Remove the given range of addresses from the specified map. 2555 * 2556 * It is assumed that the start and end are properly rounded to the page size. 2557 */ 2558 static void 2559 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 2560 { 2561 pte_t *pte; 2562 uint8_t hold_flag; 2563 2564 int su = (pmap == kernel_pmap); 2565 2566 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 2567 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 2568 2569 if (su) { 2570 KASSERT(((va >= virtual_avail) && 2571 (va <= VM_MAX_KERNEL_ADDRESS)), 2572 ("mmu_booke_remove: kernel pmap, non kernel va")); 2573 } else { 2574 KASSERT((va <= VM_MAXUSER_ADDRESS), 2575 ("mmu_booke_remove: user pmap, non user va")); 2576 } 2577 2578 if (PMAP_REMOVE_DONE(pmap)) { 2579 //debugf("mmu_booke_remove: e (empty)\n"); 2580 return; 2581 } 2582 2583 hold_flag = PTBL_HOLD_FLAG(pmap); 2584 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 2585 2586 rw_wlock(&pvh_global_lock); 2587 PMAP_LOCK(pmap); 2588 for (; va < endva; va += PAGE_SIZE) { 2589 pte = pte_find(mmu, pmap, va); 2590 if ((pte != NULL) && PTE_ISVALID(pte)) 2591 pte_remove(mmu, pmap, va, hold_flag); 2592 } 2593 PMAP_UNLOCK(pmap); 2594 rw_wunlock(&pvh_global_lock); 2595 2596 //debugf("mmu_booke_remove: e\n"); 2597 } 2598 2599 /* 2600 * Remove physical page from all pmaps in which it resides. 2601 */ 2602 static void 2603 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 2604 { 2605 pv_entry_t pv, pvn; 2606 uint8_t hold_flag; 2607 2608 rw_wlock(&pvh_global_lock); 2609 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 2610 pvn = TAILQ_NEXT(pv, pv_link); 2611 2612 PMAP_LOCK(pv->pv_pmap); 2613 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 2614 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 2615 PMAP_UNLOCK(pv->pv_pmap); 2616 } 2617 vm_page_aflag_clear(m, PGA_WRITEABLE); 2618 rw_wunlock(&pvh_global_lock); 2619 } 2620 2621 /* 2622 * Map a range of physical addresses into kernel virtual address space. 2623 */ 2624 static vm_offset_t 2625 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2626 vm_paddr_t pa_end, int prot) 2627 { 2628 vm_offset_t sva = *virt; 2629 vm_offset_t va = sva; 2630 2631 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 2632 // sva, pa_start, pa_end); 2633 2634 while (pa_start < pa_end) { 2635 mmu_booke_kenter(mmu, va, pa_start); 2636 va += PAGE_SIZE; 2637 pa_start += PAGE_SIZE; 2638 } 2639 *virt = va; 2640 2641 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 2642 return (sva); 2643 } 2644 2645 /* 2646 * The pmap must be activated before it's address space can be accessed in any 2647 * way. 2648 */ 2649 static void 2650 mmu_booke_activate(mmu_t mmu, struct thread *td) 2651 { 2652 pmap_t pmap; 2653 u_int cpuid; 2654 2655 pmap = &td->td_proc->p_vmspace->vm_pmap; 2656 2657 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 2658 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2659 2660 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 2661 2662 sched_pin(); 2663 2664 cpuid = PCPU_GET(cpuid); 2665 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 2666 PCPU_SET(curpmap, pmap); 2667 2668 if (pmap->pm_tid[cpuid] == TID_NONE) 2669 tid_alloc(pmap); 2670 2671 /* Load PID0 register with pmap tid value. */ 2672 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 2673 __asm __volatile("isync"); 2674 2675 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2676 2677 sched_unpin(); 2678 2679 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2680 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2681 } 2682 2683 /* 2684 * Deactivate the specified process's address space. 2685 */ 2686 static void 2687 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2688 { 2689 pmap_t pmap; 2690 2691 pmap = &td->td_proc->p_vmspace->vm_pmap; 2692 2693 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2694 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2695 2696 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2697 2698 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2699 PCPU_SET(curpmap, NULL); 2700 } 2701 2702 /* 2703 * Copy the range specified by src_addr/len 2704 * from the source map to the range dst_addr/len 2705 * in the destination map. 2706 * 2707 * This routine is only advisory and need not do anything. 2708 */ 2709 static void 2710 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2711 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2712 { 2713 2714 } 2715 2716 /* 2717 * Set the physical protection on the specified range of this map as requested. 2718 */ 2719 static void 2720 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2721 vm_prot_t prot) 2722 { 2723 vm_offset_t va; 2724 vm_page_t m; 2725 pte_t *pte; 2726 2727 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2728 mmu_booke_remove(mmu, pmap, sva, eva); 2729 return; 2730 } 2731 2732 if (prot & VM_PROT_WRITE) 2733 return; 2734 2735 PMAP_LOCK(pmap); 2736 for (va = sva; va < eva; va += PAGE_SIZE) { 2737 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2738 if (PTE_ISVALID(pte)) { 2739 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2740 2741 mtx_lock_spin(&tlbivax_mutex); 2742 tlb_miss_lock(); 2743 2744 /* Handle modified pages. */ 2745 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2746 vm_page_dirty(m); 2747 2748 tlb0_flush_entry(va); 2749 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2750 2751 tlb_miss_unlock(); 2752 mtx_unlock_spin(&tlbivax_mutex); 2753 } 2754 } 2755 } 2756 PMAP_UNLOCK(pmap); 2757 } 2758 2759 /* 2760 * Clear the write and modified bits in each of the given page's mappings. 2761 */ 2762 static void 2763 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2764 { 2765 pv_entry_t pv; 2766 pte_t *pte; 2767 2768 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2769 ("mmu_booke_remove_write: page %p is not managed", m)); 2770 2771 /* 2772 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2773 * set by another thread while the object is locked. Thus, 2774 * if PGA_WRITEABLE is clear, no page table entries need updating. 2775 */ 2776 VM_OBJECT_ASSERT_WLOCKED(m->object); 2777 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2778 return; 2779 rw_wlock(&pvh_global_lock); 2780 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2781 PMAP_LOCK(pv->pv_pmap); 2782 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2783 if (PTE_ISVALID(pte)) { 2784 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2785 2786 mtx_lock_spin(&tlbivax_mutex); 2787 tlb_miss_lock(); 2788 2789 /* Handle modified pages. */ 2790 if (PTE_ISMODIFIED(pte)) 2791 vm_page_dirty(m); 2792 2793 /* Flush mapping from TLB0. */ 2794 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2795 2796 tlb_miss_unlock(); 2797 mtx_unlock_spin(&tlbivax_mutex); 2798 } 2799 } 2800 PMAP_UNLOCK(pv->pv_pmap); 2801 } 2802 vm_page_aflag_clear(m, PGA_WRITEABLE); 2803 rw_wunlock(&pvh_global_lock); 2804 } 2805 2806 static void 2807 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2808 { 2809 pte_t *pte; 2810 pmap_t pmap; 2811 vm_page_t m; 2812 vm_offset_t addr; 2813 vm_paddr_t pa = 0; 2814 int active, valid; 2815 2816 va = trunc_page(va); 2817 sz = round_page(sz); 2818 2819 rw_wlock(&pvh_global_lock); 2820 pmap = PCPU_GET(curpmap); 2821 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2822 while (sz > 0) { 2823 PMAP_LOCK(pm); 2824 pte = pte_find(mmu, pm, va); 2825 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2826 if (valid) 2827 pa = PTE_PA(pte); 2828 PMAP_UNLOCK(pm); 2829 if (valid) { 2830 if (!active) { 2831 /* Create a mapping in the active pmap. */ 2832 addr = 0; 2833 m = PHYS_TO_VM_PAGE(pa); 2834 PMAP_LOCK(pmap); 2835 pte_enter(mmu, pmap, m, addr, 2836 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2837 __syncicache((void *)addr, PAGE_SIZE); 2838 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2839 PMAP_UNLOCK(pmap); 2840 } else 2841 __syncicache((void *)va, PAGE_SIZE); 2842 } 2843 va += PAGE_SIZE; 2844 sz -= PAGE_SIZE; 2845 } 2846 rw_wunlock(&pvh_global_lock); 2847 } 2848 2849 /* 2850 * Atomically extract and hold the physical page with the given 2851 * pmap and virtual address pair if that mapping permits the given 2852 * protection. 2853 */ 2854 static vm_page_t 2855 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2856 vm_prot_t prot) 2857 { 2858 pte_t *pte; 2859 vm_page_t m; 2860 uint32_t pte_wbit; 2861 vm_paddr_t pa; 2862 2863 m = NULL; 2864 pa = 0; 2865 PMAP_LOCK(pmap); 2866 retry: 2867 pte = pte_find(mmu, pmap, va); 2868 if ((pte != NULL) && PTE_ISVALID(pte)) { 2869 if (pmap == kernel_pmap) 2870 pte_wbit = PTE_SW; 2871 else 2872 pte_wbit = PTE_UW; 2873 2874 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2875 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2876 goto retry; 2877 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2878 vm_page_hold(m); 2879 } 2880 } 2881 2882 PA_UNLOCK_COND(pa); 2883 PMAP_UNLOCK(pmap); 2884 return (m); 2885 } 2886 2887 /* 2888 * Initialize a vm_page's machine-dependent fields. 2889 */ 2890 static void 2891 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2892 { 2893 2894 m->md.pv_tracked = 0; 2895 TAILQ_INIT(&m->md.pv_list); 2896 } 2897 2898 /* 2899 * mmu_booke_zero_page_area zeros the specified hardware page by 2900 * mapping it into virtual memory and using bzero to clear 2901 * its contents. 2902 * 2903 * off and size must reside within a single page. 2904 */ 2905 static void 2906 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2907 { 2908 vm_offset_t va; 2909 2910 /* XXX KASSERT off and size are within a single page? */ 2911 2912 mtx_lock(&zero_page_mutex); 2913 va = zero_page_va; 2914 2915 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2916 bzero((caddr_t)va + off, size); 2917 mmu_booke_kremove(mmu, va); 2918 2919 mtx_unlock(&zero_page_mutex); 2920 } 2921 2922 /* 2923 * mmu_booke_zero_page zeros the specified hardware page. 2924 */ 2925 static void 2926 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2927 { 2928 vm_offset_t off, va; 2929 2930 mtx_lock(&zero_page_mutex); 2931 va = zero_page_va; 2932 2933 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2934 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2935 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 2936 mmu_booke_kremove(mmu, va); 2937 2938 mtx_unlock(&zero_page_mutex); 2939 } 2940 2941 /* 2942 * mmu_booke_copy_page copies the specified (machine independent) page by 2943 * mapping the page into virtual memory and using memcopy to copy the page, 2944 * one machine dependent page at a time. 2945 */ 2946 static void 2947 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2948 { 2949 vm_offset_t sva, dva; 2950 2951 sva = copy_page_src_va; 2952 dva = copy_page_dst_va; 2953 2954 mtx_lock(©_page_mutex); 2955 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2956 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2957 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2958 mmu_booke_kremove(mmu, dva); 2959 mmu_booke_kremove(mmu, sva); 2960 mtx_unlock(©_page_mutex); 2961 } 2962 2963 static inline void 2964 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2965 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2966 { 2967 void *a_cp, *b_cp; 2968 vm_offset_t a_pg_offset, b_pg_offset; 2969 int cnt; 2970 2971 mtx_lock(©_page_mutex); 2972 while (xfersize > 0) { 2973 a_pg_offset = a_offset & PAGE_MASK; 2974 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2975 mmu_booke_kenter(mmu, copy_page_src_va, 2976 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2977 a_cp = (char *)copy_page_src_va + a_pg_offset; 2978 b_pg_offset = b_offset & PAGE_MASK; 2979 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2980 mmu_booke_kenter(mmu, copy_page_dst_va, 2981 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2982 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2983 bcopy(a_cp, b_cp, cnt); 2984 mmu_booke_kremove(mmu, copy_page_dst_va); 2985 mmu_booke_kremove(mmu, copy_page_src_va); 2986 a_offset += cnt; 2987 b_offset += cnt; 2988 xfersize -= cnt; 2989 } 2990 mtx_unlock(©_page_mutex); 2991 } 2992 2993 static vm_offset_t 2994 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2995 { 2996 vm_paddr_t paddr; 2997 vm_offset_t qaddr; 2998 uint32_t flags; 2999 pte_t *pte; 3000 3001 paddr = VM_PAGE_TO_PHYS(m); 3002 3003 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 3004 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 3005 flags |= PTE_PS_4KB; 3006 3007 critical_enter(); 3008 qaddr = PCPU_GET(qmap_addr); 3009 3010 pte = pte_find(mmu, kernel_pmap, qaddr); 3011 3012 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 3013 3014 /* 3015 * XXX: tlbivax is broadcast to other cores, but qaddr should 3016 * not be present in other TLBs. Is there a better instruction 3017 * sequence to use? Or just forget it & use mmu_booke_kenter()... 3018 */ 3019 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 3020 __asm __volatile("isync; msync"); 3021 3022 *pte = PTE_RPN_FROM_PA(paddr) | flags; 3023 3024 /* Flush the real memory from the instruction cache. */ 3025 if ((flags & (PTE_I | PTE_G)) == 0) 3026 __syncicache((void *)qaddr, PAGE_SIZE); 3027 3028 return (qaddr); 3029 } 3030 3031 static void 3032 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 3033 { 3034 pte_t *pte; 3035 3036 pte = pte_find(mmu, kernel_pmap, addr); 3037 3038 KASSERT(PCPU_GET(qmap_addr) == addr, 3039 ("mmu_booke_quick_remove_page: invalid address")); 3040 KASSERT(*pte != 0, 3041 ("mmu_booke_quick_remove_page: PTE not in use")); 3042 3043 *pte = 0; 3044 critical_exit(); 3045 } 3046 3047 /* 3048 * Return whether or not the specified physical page was modified 3049 * in any of physical maps. 3050 */ 3051 static boolean_t 3052 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 3053 { 3054 pte_t *pte; 3055 pv_entry_t pv; 3056 boolean_t rv; 3057 3058 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3059 ("mmu_booke_is_modified: page %p is not managed", m)); 3060 rv = FALSE; 3061 3062 /* 3063 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3064 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3065 * is clear, no PTEs can be modified. 3066 */ 3067 VM_OBJECT_ASSERT_WLOCKED(m->object); 3068 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3069 return (rv); 3070 rw_wlock(&pvh_global_lock); 3071 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3072 PMAP_LOCK(pv->pv_pmap); 3073 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3074 PTE_ISVALID(pte)) { 3075 if (PTE_ISMODIFIED(pte)) 3076 rv = TRUE; 3077 } 3078 PMAP_UNLOCK(pv->pv_pmap); 3079 if (rv) 3080 break; 3081 } 3082 rw_wunlock(&pvh_global_lock); 3083 return (rv); 3084 } 3085 3086 /* 3087 * Return whether or not the specified virtual address is eligible 3088 * for prefault. 3089 */ 3090 static boolean_t 3091 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 3092 { 3093 3094 return (FALSE); 3095 } 3096 3097 /* 3098 * Return whether or not the specified physical page was referenced 3099 * in any physical maps. 3100 */ 3101 static boolean_t 3102 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 3103 { 3104 pte_t *pte; 3105 pv_entry_t pv; 3106 boolean_t rv; 3107 3108 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3109 ("mmu_booke_is_referenced: page %p is not managed", m)); 3110 rv = FALSE; 3111 rw_wlock(&pvh_global_lock); 3112 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3113 PMAP_LOCK(pv->pv_pmap); 3114 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3115 PTE_ISVALID(pte)) { 3116 if (PTE_ISREFERENCED(pte)) 3117 rv = TRUE; 3118 } 3119 PMAP_UNLOCK(pv->pv_pmap); 3120 if (rv) 3121 break; 3122 } 3123 rw_wunlock(&pvh_global_lock); 3124 return (rv); 3125 } 3126 3127 /* 3128 * Clear the modify bits on the specified physical page. 3129 */ 3130 static void 3131 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 3132 { 3133 pte_t *pte; 3134 pv_entry_t pv; 3135 3136 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3137 ("mmu_booke_clear_modify: page %p is not managed", m)); 3138 VM_OBJECT_ASSERT_WLOCKED(m->object); 3139 KASSERT(!vm_page_xbusied(m), 3140 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 3141 3142 /* 3143 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 3144 * If the object containing the page is locked and the page is not 3145 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 3146 */ 3147 if ((m->aflags & PGA_WRITEABLE) == 0) 3148 return; 3149 rw_wlock(&pvh_global_lock); 3150 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3151 PMAP_LOCK(pv->pv_pmap); 3152 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3153 PTE_ISVALID(pte)) { 3154 mtx_lock_spin(&tlbivax_mutex); 3155 tlb_miss_lock(); 3156 3157 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 3158 tlb0_flush_entry(pv->pv_va); 3159 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 3160 PTE_REFERENCED); 3161 } 3162 3163 tlb_miss_unlock(); 3164 mtx_unlock_spin(&tlbivax_mutex); 3165 } 3166 PMAP_UNLOCK(pv->pv_pmap); 3167 } 3168 rw_wunlock(&pvh_global_lock); 3169 } 3170 3171 /* 3172 * Return a count of reference bits for a page, clearing those bits. 3173 * It is not necessary for every reference bit to be cleared, but it 3174 * is necessary that 0 only be returned when there are truly no 3175 * reference bits set. 3176 * 3177 * As an optimization, update the page's dirty field if a modified bit is 3178 * found while counting reference bits. This opportunistic update can be 3179 * performed at low cost and can eliminate the need for some future calls 3180 * to pmap_is_modified(). However, since this function stops after 3181 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 3182 * dirty pages. Those dirty pages will only be detected by a future call 3183 * to pmap_is_modified(). 3184 */ 3185 static int 3186 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 3187 { 3188 pte_t *pte; 3189 pv_entry_t pv; 3190 int count; 3191 3192 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3193 ("mmu_booke_ts_referenced: page %p is not managed", m)); 3194 count = 0; 3195 rw_wlock(&pvh_global_lock); 3196 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3197 PMAP_LOCK(pv->pv_pmap); 3198 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 3199 PTE_ISVALID(pte)) { 3200 if (PTE_ISMODIFIED(pte)) 3201 vm_page_dirty(m); 3202 if (PTE_ISREFERENCED(pte)) { 3203 mtx_lock_spin(&tlbivax_mutex); 3204 tlb_miss_lock(); 3205 3206 tlb0_flush_entry(pv->pv_va); 3207 *pte &= ~PTE_REFERENCED; 3208 3209 tlb_miss_unlock(); 3210 mtx_unlock_spin(&tlbivax_mutex); 3211 3212 if (++count >= PMAP_TS_REFERENCED_MAX) { 3213 PMAP_UNLOCK(pv->pv_pmap); 3214 break; 3215 } 3216 } 3217 } 3218 PMAP_UNLOCK(pv->pv_pmap); 3219 } 3220 rw_wunlock(&pvh_global_lock); 3221 return (count); 3222 } 3223 3224 /* 3225 * Clear the wired attribute from the mappings for the specified range of 3226 * addresses in the given pmap. Every valid mapping within that range must 3227 * have the wired attribute set. In contrast, invalid mappings cannot have 3228 * the wired attribute set, so they are ignored. 3229 * 3230 * The wired attribute of the page table entry is not a hardware feature, so 3231 * there is no need to invalidate any TLB entries. 3232 */ 3233 static void 3234 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3235 { 3236 vm_offset_t va; 3237 pte_t *pte; 3238 3239 PMAP_LOCK(pmap); 3240 for (va = sva; va < eva; va += PAGE_SIZE) { 3241 if ((pte = pte_find(mmu, pmap, va)) != NULL && 3242 PTE_ISVALID(pte)) { 3243 if (!PTE_ISWIRED(pte)) 3244 panic("mmu_booke_unwire: pte %p isn't wired", 3245 pte); 3246 *pte &= ~PTE_WIRED; 3247 pmap->pm_stats.wired_count--; 3248 } 3249 } 3250 PMAP_UNLOCK(pmap); 3251 3252 } 3253 3254 /* 3255 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 3256 * page. This count may be changed upwards or downwards in the future; it is 3257 * only necessary that true be returned for a small subset of pmaps for proper 3258 * page aging. 3259 */ 3260 static boolean_t 3261 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 3262 { 3263 pv_entry_t pv; 3264 int loops; 3265 boolean_t rv; 3266 3267 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3268 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 3269 loops = 0; 3270 rv = FALSE; 3271 rw_wlock(&pvh_global_lock); 3272 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3273 if (pv->pv_pmap == pmap) { 3274 rv = TRUE; 3275 break; 3276 } 3277 if (++loops >= 16) 3278 break; 3279 } 3280 rw_wunlock(&pvh_global_lock); 3281 return (rv); 3282 } 3283 3284 /* 3285 * Return the number of managed mappings to the given physical page that are 3286 * wired. 3287 */ 3288 static int 3289 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 3290 { 3291 pv_entry_t pv; 3292 pte_t *pte; 3293 int count = 0; 3294 3295 if ((m->oflags & VPO_UNMANAGED) != 0) 3296 return (count); 3297 rw_wlock(&pvh_global_lock); 3298 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 3299 PMAP_LOCK(pv->pv_pmap); 3300 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 3301 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 3302 count++; 3303 PMAP_UNLOCK(pv->pv_pmap); 3304 } 3305 rw_wunlock(&pvh_global_lock); 3306 return (count); 3307 } 3308 3309 static int 3310 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 3311 { 3312 int i; 3313 vm_offset_t va; 3314 3315 /* 3316 * This currently does not work for entries that 3317 * overlap TLB1 entries. 3318 */ 3319 for (i = 0; i < TLB1_ENTRIES; i ++) { 3320 if (tlb1_iomapped(i, pa, size, &va) == 0) 3321 return (0); 3322 } 3323 3324 return (EFAULT); 3325 } 3326 3327 void 3328 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 3329 { 3330 vm_paddr_t ppa; 3331 vm_offset_t ofs; 3332 vm_size_t gran; 3333 3334 /* Minidumps are based on virtual memory addresses. */ 3335 if (do_minidump) { 3336 *va = (void *)(vm_offset_t)pa; 3337 return; 3338 } 3339 3340 /* Raw physical memory dumps don't have a virtual address. */ 3341 /* We always map a 256MB page at 256M. */ 3342 gran = 256 * 1024 * 1024; 3343 ppa = rounddown2(pa, gran); 3344 ofs = pa - ppa; 3345 *va = (void *)gran; 3346 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 3347 3348 if (sz > (gran - ofs)) 3349 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 3350 _TLB_ENTRY_IO); 3351 } 3352 3353 void 3354 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 3355 { 3356 vm_paddr_t ppa; 3357 vm_offset_t ofs; 3358 vm_size_t gran; 3359 tlb_entry_t e; 3360 int i; 3361 3362 /* Minidumps are based on virtual memory addresses. */ 3363 /* Nothing to do... */ 3364 if (do_minidump) 3365 return; 3366 3367 for (i = 0; i < TLB1_ENTRIES; i++) { 3368 tlb1_read_entry(&e, i); 3369 if (!(e.mas1 & MAS1_VALID)) 3370 break; 3371 } 3372 3373 /* Raw physical memory dumps don't have a virtual address. */ 3374 i--; 3375 e.mas1 = 0; 3376 e.mas2 = 0; 3377 e.mas3 = 0; 3378 tlb1_write_entry(&e, i); 3379 3380 gran = 256 * 1024 * 1024; 3381 ppa = rounddown2(pa, gran); 3382 ofs = pa - ppa; 3383 if (sz > (gran - ofs)) { 3384 i--; 3385 e.mas1 = 0; 3386 e.mas2 = 0; 3387 e.mas3 = 0; 3388 tlb1_write_entry(&e, i); 3389 } 3390 } 3391 3392 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 3393 3394 void 3395 mmu_booke_scan_init(mmu_t mmu) 3396 { 3397 vm_offset_t va; 3398 pte_t *pte; 3399 int i; 3400 3401 if (!do_minidump) { 3402 /* Initialize phys. segments for dumpsys(). */ 3403 memset(&dump_map, 0, sizeof(dump_map)); 3404 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 3405 &availmem_regions_sz); 3406 for (i = 0; i < physmem_regions_sz; i++) { 3407 dump_map[i].pa_start = physmem_regions[i].mr_start; 3408 dump_map[i].pa_size = physmem_regions[i].mr_size; 3409 } 3410 return; 3411 } 3412 3413 /* Virtual segments for minidumps: */ 3414 memset(&dump_map, 0, sizeof(dump_map)); 3415 3416 /* 1st: kernel .data and .bss. */ 3417 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 3418 dump_map[0].pa_size = 3419 round_page((uintptr_t)_end) - dump_map[0].pa_start; 3420 3421 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 3422 dump_map[1].pa_start = data_start; 3423 dump_map[1].pa_size = data_end - data_start; 3424 3425 /* 3rd: kernel VM. */ 3426 va = dump_map[1].pa_start + dump_map[1].pa_size; 3427 /* Find start of next chunk (from va). */ 3428 while (va < virtual_end) { 3429 /* Don't dump the buffer cache. */ 3430 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 3431 va = kmi.buffer_eva; 3432 continue; 3433 } 3434 pte = pte_find(mmu, kernel_pmap, va); 3435 if (pte != NULL && PTE_ISVALID(pte)) 3436 break; 3437 va += PAGE_SIZE; 3438 } 3439 if (va < virtual_end) { 3440 dump_map[2].pa_start = va; 3441 va += PAGE_SIZE; 3442 /* Find last page in chunk. */ 3443 while (va < virtual_end) { 3444 /* Don't run into the buffer cache. */ 3445 if (va == kmi.buffer_sva) 3446 break; 3447 pte = pte_find(mmu, kernel_pmap, va); 3448 if (pte == NULL || !PTE_ISVALID(pte)) 3449 break; 3450 va += PAGE_SIZE; 3451 } 3452 dump_map[2].pa_size = va - dump_map[2].pa_start; 3453 } 3454 } 3455 3456 /* 3457 * Map a set of physical memory pages into the kernel virtual address space. 3458 * Return a pointer to where it is mapped. This routine is intended to be used 3459 * for mapping device memory, NOT real memory. 3460 */ 3461 static void * 3462 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 3463 { 3464 3465 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 3466 } 3467 3468 static void * 3469 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 3470 { 3471 tlb_entry_t e; 3472 void *res; 3473 uintptr_t va, tmpva; 3474 vm_size_t sz; 3475 int i; 3476 3477 /* 3478 * Check if this is premapped in TLB1. Note: this should probably also 3479 * check whether a sequence of TLB1 entries exist that match the 3480 * requirement, but now only checks the easy case. 3481 */ 3482 for (i = 0; i < TLB1_ENTRIES; i++) { 3483 tlb1_read_entry(&e, i); 3484 if (!(e.mas1 & MAS1_VALID)) 3485 continue; 3486 if (pa >= e.phys && 3487 (pa + size) <= (e.phys + e.size) && 3488 (ma == VM_MEMATTR_DEFAULT || 3489 tlb_calc_wimg(pa, ma) == 3490 (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))) 3491 return (void *)(e.virt + 3492 (vm_offset_t)(pa - e.phys)); 3493 } 3494 3495 size = roundup(size, PAGE_SIZE); 3496 3497 /* 3498 * The device mapping area is between VM_MAXUSER_ADDRESS and 3499 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 3500 */ 3501 #ifdef SPARSE_MAPDEV 3502 /* 3503 * With a sparse mapdev, align to the largest starting region. This 3504 * could feasibly be optimized for a 'best-fit' alignment, but that 3505 * calculation could be very costly. 3506 * Align to the smaller of: 3507 * - first set bit in overlap of (pa & size mask) 3508 * - largest size envelope 3509 * 3510 * It's possible the device mapping may start at a PA that's not larger 3511 * than the size mask, so we need to offset in to maximize the TLB entry 3512 * range and minimize the number of used TLB entries. 3513 */ 3514 do { 3515 tmpva = tlb1_map_base; 3516 sz = ffsl(((1 << flsl(size-1)) - 1) & pa); 3517 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1; 3518 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa); 3519 #ifdef __powerpc64__ 3520 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size)); 3521 #else 3522 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 3523 #endif 3524 #else 3525 #ifdef __powerpc64__ 3526 va = atomic_fetchadd_long(&tlb1_map_base, size); 3527 #else 3528 va = atomic_fetchadd_int(&tlb1_map_base, size); 3529 #endif 3530 #endif 3531 res = (void *)va; 3532 3533 do { 3534 sz = 1 << (ilog2(size) & ~1); 3535 /* Align size to PA */ 3536 if (pa % sz != 0) { 3537 do { 3538 sz >>= 2; 3539 } while (pa % sz != 0); 3540 } 3541 /* Now align from there to VA */ 3542 if (va % sz != 0) { 3543 do { 3544 sz >>= 2; 3545 } while (va % sz != 0); 3546 } 3547 if (bootverbose) 3548 printf("Wiring VA=%lx to PA=%jx (size=%lx)\n", 3549 va, (uintmax_t)pa, sz); 3550 if (tlb1_set_entry(va, pa, sz, 3551 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)) < 0) 3552 return (NULL); 3553 size -= sz; 3554 pa += sz; 3555 va += sz; 3556 } while (size > 0); 3557 3558 return (res); 3559 } 3560 3561 /* 3562 * 'Unmap' a range mapped by mmu_booke_mapdev(). 3563 */ 3564 static void 3565 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 3566 { 3567 #ifdef SUPPORTS_SHRINKING_TLB1 3568 vm_offset_t base, offset; 3569 3570 /* 3571 * Unmap only if this is inside kernel virtual space. 3572 */ 3573 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 3574 base = trunc_page(va); 3575 offset = va & PAGE_MASK; 3576 size = roundup(offset + size, PAGE_SIZE); 3577 kva_free(base, size); 3578 } 3579 #endif 3580 } 3581 3582 /* 3583 * mmu_booke_object_init_pt preloads the ptes for a given object into the 3584 * specified pmap. This eliminates the blast of soft faults on process startup 3585 * and immediately after an mmap. 3586 */ 3587 static void 3588 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 3589 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 3590 { 3591 3592 VM_OBJECT_ASSERT_WLOCKED(object); 3593 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3594 ("mmu_booke_object_init_pt: non-device object")); 3595 } 3596 3597 /* 3598 * Perform the pmap work for mincore. 3599 */ 3600 static int 3601 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 3602 vm_paddr_t *locked_pa) 3603 { 3604 3605 /* XXX: this should be implemented at some point */ 3606 return (0); 3607 } 3608 3609 static int 3610 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 3611 vm_memattr_t mode) 3612 { 3613 vm_offset_t va; 3614 pte_t *pte; 3615 int i, j; 3616 tlb_entry_t e; 3617 3618 /* Check TLB1 mappings */ 3619 for (i = 0; i < TLB1_ENTRIES; i++) { 3620 tlb1_read_entry(&e, i); 3621 if (!(e.mas1 & MAS1_VALID)) 3622 continue; 3623 if (addr >= e.virt && addr < e.virt + e.size) 3624 break; 3625 } 3626 if (i < TLB1_ENTRIES) { 3627 /* Only allow full mappings to be modified for now. */ 3628 /* Validate the range. */ 3629 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 3630 tlb1_read_entry(&e, j); 3631 if (va != e.virt || (sz - (va - addr) < e.size)) 3632 return (EINVAL); 3633 } 3634 for (va = addr; va < addr + sz; va += e.size, i++) { 3635 tlb1_read_entry(&e, i); 3636 e.mas2 &= ~MAS2_WIMGE_MASK; 3637 e.mas2 |= tlb_calc_wimg(e.phys, mode); 3638 3639 /* 3640 * Write it out to the TLB. Should really re-sync with other 3641 * cores. 3642 */ 3643 tlb1_write_entry(&e, i); 3644 } 3645 return (0); 3646 } 3647 3648 /* Not in TLB1, try through pmap */ 3649 /* First validate the range. */ 3650 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 3651 pte = pte_find(mmu, kernel_pmap, va); 3652 if (pte == NULL || !PTE_ISVALID(pte)) 3653 return (EINVAL); 3654 } 3655 3656 mtx_lock_spin(&tlbivax_mutex); 3657 tlb_miss_lock(); 3658 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 3659 pte = pte_find(mmu, kernel_pmap, va); 3660 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 3661 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 3662 tlb0_flush_entry(va); 3663 } 3664 tlb_miss_unlock(); 3665 mtx_unlock_spin(&tlbivax_mutex); 3666 3667 return (0); 3668 } 3669 3670 /**************************************************************************/ 3671 /* TID handling */ 3672 /**************************************************************************/ 3673 3674 /* 3675 * Allocate a TID. If necessary, steal one from someone else. 3676 * The new TID is flushed from the TLB before returning. 3677 */ 3678 static tlbtid_t 3679 tid_alloc(pmap_t pmap) 3680 { 3681 tlbtid_t tid; 3682 int thiscpu; 3683 3684 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 3685 3686 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 3687 3688 thiscpu = PCPU_GET(cpuid); 3689 3690 tid = PCPU_GET(tid_next); 3691 if (tid > TID_MAX) 3692 tid = TID_MIN; 3693 PCPU_SET(tid_next, tid + 1); 3694 3695 /* If we are stealing TID then clear the relevant pmap's field */ 3696 if (tidbusy[thiscpu][tid] != NULL) { 3697 3698 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 3699 3700 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 3701 3702 /* Flush all entries from TLB0 matching this TID. */ 3703 tid_flush(tid); 3704 } 3705 3706 tidbusy[thiscpu][tid] = pmap; 3707 pmap->pm_tid[thiscpu] = tid; 3708 __asm __volatile("msync; isync"); 3709 3710 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3711 PCPU_GET(tid_next)); 3712 3713 return (tid); 3714 } 3715 3716 /**************************************************************************/ 3717 /* TLB0 handling */ 3718 /**************************************************************************/ 3719 3720 static void 3721 #ifdef __powerpc64__ 3722 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3, 3723 #else 3724 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3725 #endif 3726 uint32_t mas7) 3727 { 3728 int as; 3729 char desc[3]; 3730 tlbtid_t tid; 3731 vm_size_t size; 3732 unsigned int tsize; 3733 3734 desc[2] = '\0'; 3735 if (mas1 & MAS1_VALID) 3736 desc[0] = 'V'; 3737 else 3738 desc[0] = ' '; 3739 3740 if (mas1 & MAS1_IPROT) 3741 desc[1] = 'P'; 3742 else 3743 desc[1] = ' '; 3744 3745 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3746 tid = MAS1_GETTID(mas1); 3747 3748 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3749 size = 0; 3750 if (tsize) 3751 size = tsize2size(tsize); 3752 3753 debugf("%3d: (%s) [AS=%d] " 3754 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 3755 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3756 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 3757 } 3758 3759 /* Convert TLB0 va and way number to tlb0[] table index. */ 3760 static inline unsigned int 3761 tlb0_tableidx(vm_offset_t va, unsigned int way) 3762 { 3763 unsigned int idx; 3764 3765 idx = (way * TLB0_ENTRIES_PER_WAY); 3766 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3767 return (idx); 3768 } 3769 3770 /* 3771 * Invalidate TLB0 entry. 3772 */ 3773 static inline void 3774 tlb0_flush_entry(vm_offset_t va) 3775 { 3776 3777 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3778 3779 mtx_assert(&tlbivax_mutex, MA_OWNED); 3780 3781 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3782 __asm __volatile("isync; msync"); 3783 __asm __volatile("tlbsync; msync"); 3784 3785 CTR1(KTR_PMAP, "%s: e", __func__); 3786 } 3787 3788 /* Print out contents of the MAS registers for each TLB0 entry */ 3789 void 3790 tlb0_print_tlbentries(void) 3791 { 3792 uint32_t mas0, mas1, mas3, mas7; 3793 #ifdef __powerpc64__ 3794 uint64_t mas2; 3795 #else 3796 uint32_t mas2; 3797 #endif 3798 int entryidx, way, idx; 3799 3800 debugf("TLB0 entries:\n"); 3801 for (way = 0; way < TLB0_WAYS; way ++) 3802 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3803 3804 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3805 mtspr(SPR_MAS0, mas0); 3806 __asm __volatile("isync"); 3807 3808 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3809 mtspr(SPR_MAS2, mas2); 3810 3811 __asm __volatile("isync; tlbre"); 3812 3813 mas1 = mfspr(SPR_MAS1); 3814 mas2 = mfspr(SPR_MAS2); 3815 mas3 = mfspr(SPR_MAS3); 3816 mas7 = mfspr(SPR_MAS7); 3817 3818 idx = tlb0_tableidx(mas2, way); 3819 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3820 } 3821 } 3822 3823 /**************************************************************************/ 3824 /* TLB1 handling */ 3825 /**************************************************************************/ 3826 3827 /* 3828 * TLB1 mapping notes: 3829 * 3830 * TLB1[0] Kernel text and data. 3831 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3832 * windows, other devices mappings. 3833 */ 3834 3835 /* 3836 * Read an entry from given TLB1 slot. 3837 */ 3838 void 3839 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 3840 { 3841 register_t msr; 3842 uint32_t mas0; 3843 3844 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 3845 3846 msr = mfmsr(); 3847 __asm __volatile("wrteei 0"); 3848 3849 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 3850 mtspr(SPR_MAS0, mas0); 3851 __asm __volatile("isync; tlbre"); 3852 3853 entry->mas1 = mfspr(SPR_MAS1); 3854 entry->mas2 = mfspr(SPR_MAS2); 3855 entry->mas3 = mfspr(SPR_MAS3); 3856 3857 switch ((mfpvr() >> 16) & 0xFFFF) { 3858 case FSL_E500v2: 3859 case FSL_E500mc: 3860 case FSL_E5500: 3861 case FSL_E6500: 3862 entry->mas7 = mfspr(SPR_MAS7); 3863 break; 3864 default: 3865 entry->mas7 = 0; 3866 break; 3867 } 3868 mtmsr(msr); 3869 3870 entry->virt = entry->mas2 & MAS2_EPN_MASK; 3871 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 3872 (entry->mas3 & MAS3_RPN); 3873 entry->size = 3874 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 3875 } 3876 3877 struct tlbwrite_args { 3878 tlb_entry_t *e; 3879 unsigned int idx; 3880 }; 3881 3882 static void 3883 tlb1_write_entry_int(void *arg) 3884 { 3885 struct tlbwrite_args *args = arg; 3886 uint32_t mas0; 3887 3888 /* Select entry */ 3889 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx); 3890 3891 mtspr(SPR_MAS0, mas0); 3892 __asm __volatile("isync"); 3893 mtspr(SPR_MAS1, args->e->mas1); 3894 __asm __volatile("isync"); 3895 mtspr(SPR_MAS2, args->e->mas2); 3896 __asm __volatile("isync"); 3897 mtspr(SPR_MAS3, args->e->mas3); 3898 __asm __volatile("isync"); 3899 switch ((mfpvr() >> 16) & 0xFFFF) { 3900 case FSL_E500mc: 3901 case FSL_E5500: 3902 case FSL_E6500: 3903 mtspr(SPR_MAS8, 0); 3904 __asm __volatile("isync"); 3905 /* FALLTHROUGH */ 3906 case FSL_E500v2: 3907 mtspr(SPR_MAS7, args->e->mas7); 3908 __asm __volatile("isync"); 3909 break; 3910 default: 3911 break; 3912 } 3913 3914 __asm __volatile("tlbwe; isync; msync"); 3915 3916 } 3917 3918 static void 3919 tlb1_write_entry_sync(void *arg) 3920 { 3921 /* Empty synchronization point for smp_rendezvous(). */ 3922 } 3923 3924 /* 3925 * Write given entry to TLB1 hardware. 3926 */ 3927 static void 3928 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 3929 { 3930 struct tlbwrite_args args; 3931 3932 args.e = e; 3933 args.idx = idx; 3934 3935 #ifdef SMP 3936 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) { 3937 mb(); 3938 smp_rendezvous(tlb1_write_entry_sync, 3939 tlb1_write_entry_int, 3940 tlb1_write_entry_sync, &args); 3941 } else 3942 #endif 3943 { 3944 register_t msr; 3945 3946 msr = mfmsr(); 3947 __asm __volatile("wrteei 0"); 3948 tlb1_write_entry_int(&args); 3949 mtmsr(msr); 3950 } 3951 } 3952 3953 /* 3954 * Return the largest uint value log such that 2^log <= num. 3955 */ 3956 static unsigned int 3957 ilog2(unsigned int num) 3958 { 3959 int lz; 3960 3961 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3962 return (31 - lz); 3963 } 3964 3965 /* 3966 * Convert TLB TSIZE value to mapped region size. 3967 */ 3968 static vm_size_t 3969 tsize2size(unsigned int tsize) 3970 { 3971 3972 /* 3973 * size = 4^tsize KB 3974 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3975 */ 3976 3977 return ((1 << (2 * tsize)) * 1024); 3978 } 3979 3980 /* 3981 * Convert region size (must be power of 4) to TLB TSIZE value. 3982 */ 3983 static unsigned int 3984 size2tsize(vm_size_t size) 3985 { 3986 3987 return (ilog2(size) / 2 - 5); 3988 } 3989 3990 /* 3991 * Register permanent kernel mapping in TLB1. 3992 * 3993 * Entries are created starting from index 0 (current free entry is 3994 * kept in tlb1_idx) and are not supposed to be invalidated. 3995 */ 3996 int 3997 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3998 uint32_t flags) 3999 { 4000 tlb_entry_t e; 4001 uint32_t ts, tid; 4002 int tsize, index; 4003 4004 for (index = 0; index < TLB1_ENTRIES; index++) { 4005 tlb1_read_entry(&e, index); 4006 if ((e.mas1 & MAS1_VALID) == 0) 4007 break; 4008 /* Check if we're just updating the flags, and update them. */ 4009 if (e.phys == pa && e.virt == va && e.size == size) { 4010 e.mas2 = (va & MAS2_EPN_MASK) | flags; 4011 tlb1_write_entry(&e, index); 4012 return (0); 4013 } 4014 } 4015 if (index >= TLB1_ENTRIES) { 4016 printf("tlb1_set_entry: TLB1 full!\n"); 4017 return (-1); 4018 } 4019 4020 /* Convert size to TSIZE */ 4021 tsize = size2tsize(size); 4022 4023 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 4024 /* XXX TS is hard coded to 0 for now as we only use single address space */ 4025 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 4026 4027 e.phys = pa; 4028 e.virt = va; 4029 e.size = size; 4030 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 4031 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 4032 e.mas2 = (va & MAS2_EPN_MASK) | flags; 4033 4034 /* Set supervisor RWX permission bits */ 4035 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 4036 e.mas7 = (pa >> 32) & MAS7_RPN; 4037 4038 tlb1_write_entry(&e, index); 4039 4040 /* 4041 * XXX in general TLB1 updates should be propagated between CPUs, 4042 * since current design assumes to have the same TLB1 set-up on all 4043 * cores. 4044 */ 4045 return (0); 4046 } 4047 4048 /* 4049 * Map in contiguous RAM region into the TLB1 using maximum of 4050 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 4051 * 4052 * If necessary round up last entry size and return total size 4053 * used by all allocated entries. 4054 */ 4055 vm_size_t 4056 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 4057 { 4058 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 4059 vm_size_t mapped, pgsz, base, mask; 4060 int idx, nents; 4061 4062 /* Round up to the next 1M */ 4063 size = roundup2(size, 1 << 20); 4064 4065 mapped = 0; 4066 idx = 0; 4067 base = va; 4068 pgsz = 64*1024*1024; 4069 while (mapped < size) { 4070 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 4071 while (pgsz > (size - mapped)) 4072 pgsz >>= 2; 4073 pgs[idx++] = pgsz; 4074 mapped += pgsz; 4075 } 4076 4077 /* We under-map. Correct for this. */ 4078 if (mapped < size) { 4079 while (pgs[idx - 1] == pgsz) { 4080 idx--; 4081 mapped -= pgsz; 4082 } 4083 /* XXX We may increase beyond out starting point. */ 4084 pgsz <<= 2; 4085 pgs[idx++] = pgsz; 4086 mapped += pgsz; 4087 } 4088 } 4089 4090 nents = idx; 4091 mask = pgs[0] - 1; 4092 /* Align address to the boundary */ 4093 if (va & mask) { 4094 va = (va + mask) & ~mask; 4095 pa = (pa + mask) & ~mask; 4096 } 4097 4098 for (idx = 0; idx < nents; idx++) { 4099 pgsz = pgs[idx]; 4100 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 4101 tlb1_set_entry(va, pa, pgsz, 4102 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM); 4103 pa += pgsz; 4104 va += pgsz; 4105 } 4106 4107 mapped = (va - base); 4108 printf("mapped size 0x%"PRI0ptrX" (wasted space 0x%"PRIxPTR")\n", 4109 mapped, mapped - size); 4110 return (mapped); 4111 } 4112 4113 /* 4114 * TLB1 initialization routine, to be called after the very first 4115 * assembler level setup done in locore.S. 4116 */ 4117 void 4118 tlb1_init() 4119 { 4120 uint32_t mas0, mas1, mas2, mas3, mas7; 4121 uint32_t tsz; 4122 4123 tlb1_get_tlbconf(); 4124 4125 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 4126 mtspr(SPR_MAS0, mas0); 4127 __asm __volatile("isync; tlbre"); 4128 4129 mas1 = mfspr(SPR_MAS1); 4130 mas2 = mfspr(SPR_MAS2); 4131 mas3 = mfspr(SPR_MAS3); 4132 mas7 = mfspr(SPR_MAS7); 4133 4134 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 4135 (mas3 & MAS3_RPN); 4136 4137 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4138 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 4139 4140 /* Setup TLB miss defaults */ 4141 set_mas4_defaults(); 4142 } 4143 4144 /* 4145 * pmap_early_io_unmap() should be used in short conjunction with 4146 * pmap_early_io_map(), as in the following snippet: 4147 * 4148 * x = pmap_early_io_map(...); 4149 * <do something with x> 4150 * pmap_early_io_unmap(x, size); 4151 * 4152 * And avoiding more allocations between. 4153 */ 4154 void 4155 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 4156 { 4157 int i; 4158 tlb_entry_t e; 4159 vm_size_t isize; 4160 4161 size = roundup(size, PAGE_SIZE); 4162 isize = size; 4163 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 4164 tlb1_read_entry(&e, i); 4165 if (!(e.mas1 & MAS1_VALID)) 4166 continue; 4167 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 4168 size -= e.size; 4169 e.mas1 &= ~MAS1_VALID; 4170 tlb1_write_entry(&e, i); 4171 } 4172 } 4173 if (tlb1_map_base == va + isize) 4174 tlb1_map_base -= isize; 4175 } 4176 4177 vm_offset_t 4178 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 4179 { 4180 vm_paddr_t pa_base; 4181 vm_offset_t va, sz; 4182 int i; 4183 tlb_entry_t e; 4184 4185 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 4186 4187 for (i = 0; i < TLB1_ENTRIES; i++) { 4188 tlb1_read_entry(&e, i); 4189 if (!(e.mas1 & MAS1_VALID)) 4190 continue; 4191 if (pa >= e.phys && (pa + size) <= 4192 (e.phys + e.size)) 4193 return (e.virt + (pa - e.phys)); 4194 } 4195 4196 pa_base = rounddown(pa, PAGE_SIZE); 4197 size = roundup(size + (pa - pa_base), PAGE_SIZE); 4198 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 4199 va = tlb1_map_base + (pa - pa_base); 4200 4201 do { 4202 sz = 1 << (ilog2(size) & ~1); 4203 tlb1_set_entry(tlb1_map_base, pa_base, sz, 4204 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 4205 size -= sz; 4206 pa_base += sz; 4207 tlb1_map_base += sz; 4208 } while (size > 0); 4209 4210 return (va); 4211 } 4212 4213 void 4214 pmap_track_page(pmap_t pmap, vm_offset_t va) 4215 { 4216 vm_paddr_t pa; 4217 vm_page_t page; 4218 struct pv_entry *pve; 4219 4220 va = trunc_page(va); 4221 pa = pmap_kextract(va); 4222 4223 rw_wlock(&pvh_global_lock); 4224 PMAP_LOCK(pmap); 4225 page = PHYS_TO_VM_PAGE(pa); 4226 4227 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 4228 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 4229 goto out; 4230 } 4231 } 4232 page->md.pv_tracked = true; 4233 pv_insert(pmap, va, page); 4234 out: 4235 PMAP_UNLOCK(pmap); 4236 rw_wunlock(&pvh_global_lock); 4237 } 4238 4239 4240 /* 4241 * Setup MAS4 defaults. 4242 * These values are loaded to MAS0-2 on a TLB miss. 4243 */ 4244 static void 4245 set_mas4_defaults(void) 4246 { 4247 uint32_t mas4; 4248 4249 /* Defaults: TLB0, PID0, TSIZED=4K */ 4250 mas4 = MAS4_TLBSELD0; 4251 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 4252 #ifdef SMP 4253 mas4 |= MAS4_MD; 4254 #endif 4255 mtspr(SPR_MAS4, mas4); 4256 __asm __volatile("isync"); 4257 } 4258 4259 /* 4260 * Print out contents of the MAS registers for each TLB1 entry 4261 */ 4262 void 4263 tlb1_print_tlbentries(void) 4264 { 4265 uint32_t mas0, mas1, mas3, mas7; 4266 #ifdef __powerpc64__ 4267 uint64_t mas2; 4268 #else 4269 uint32_t mas2; 4270 #endif 4271 int i; 4272 4273 debugf("TLB1 entries:\n"); 4274 for (i = 0; i < TLB1_ENTRIES; i++) { 4275 4276 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 4277 mtspr(SPR_MAS0, mas0); 4278 4279 __asm __volatile("isync; tlbre"); 4280 4281 mas1 = mfspr(SPR_MAS1); 4282 mas2 = mfspr(SPR_MAS2); 4283 mas3 = mfspr(SPR_MAS3); 4284 mas7 = mfspr(SPR_MAS7); 4285 4286 tlb_print_entry(i, mas1, mas2, mas3, mas7); 4287 } 4288 } 4289 4290 /* 4291 * Return 0 if the physical IO range is encompassed by one of the 4292 * the TLB1 entries, otherwise return related error code. 4293 */ 4294 static int 4295 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 4296 { 4297 uint32_t prot; 4298 vm_paddr_t pa_start; 4299 vm_paddr_t pa_end; 4300 unsigned int entry_tsize; 4301 vm_size_t entry_size; 4302 tlb_entry_t e; 4303 4304 *va = (vm_offset_t)NULL; 4305 4306 tlb1_read_entry(&e, i); 4307 /* Skip invalid entries */ 4308 if (!(e.mas1 & MAS1_VALID)) 4309 return (EINVAL); 4310 4311 /* 4312 * The entry must be cache-inhibited, guarded, and r/w 4313 * so it can function as an i/o page 4314 */ 4315 prot = e.mas2 & (MAS2_I | MAS2_G); 4316 if (prot != (MAS2_I | MAS2_G)) 4317 return (EPERM); 4318 4319 prot = e.mas3 & (MAS3_SR | MAS3_SW); 4320 if (prot != (MAS3_SR | MAS3_SW)) 4321 return (EPERM); 4322 4323 /* The address should be within the entry range. */ 4324 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 4325 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 4326 4327 entry_size = tsize2size(entry_tsize); 4328 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 4329 (e.mas3 & MAS3_RPN); 4330 pa_end = pa_start + entry_size; 4331 4332 if ((pa < pa_start) || ((pa + size) > pa_end)) 4333 return (ERANGE); 4334 4335 /* Return virtual address of this mapping. */ 4336 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 4337 return (0); 4338 } 4339 4340 /* 4341 * Invalidate all TLB0 entries which match the given TID. Note this is 4342 * dedicated for cases when invalidations should NOT be propagated to other 4343 * CPUs. 4344 */ 4345 static void 4346 tid_flush(tlbtid_t tid) 4347 { 4348 register_t msr; 4349 uint32_t mas0, mas1, mas2; 4350 int entry, way; 4351 4352 4353 /* Don't evict kernel translations */ 4354 if (tid == TID_KERNEL) 4355 return; 4356 4357 msr = mfmsr(); 4358 __asm __volatile("wrteei 0"); 4359 4360 for (way = 0; way < TLB0_WAYS; way++) 4361 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 4362 4363 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 4364 mtspr(SPR_MAS0, mas0); 4365 __asm __volatile("isync"); 4366 4367 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 4368 mtspr(SPR_MAS2, mas2); 4369 4370 __asm __volatile("isync; tlbre"); 4371 4372 mas1 = mfspr(SPR_MAS1); 4373 4374 if (!(mas1 & MAS1_VALID)) 4375 continue; 4376 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 4377 continue; 4378 mas1 &= ~MAS1_VALID; 4379 mtspr(SPR_MAS1, mas1); 4380 __asm __volatile("isync; tlbwe; isync; msync"); 4381 } 4382 mtmsr(msr); 4383 } 4384