1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include <sys/types.h> 55 #include <sys/param.h> 56 #include <sys/malloc.h> 57 #include <sys/ktr.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/msgbuf.h> 64 #include <sys/lock.h> 65 #include <sys/mutex.h> 66 #include <sys/smp.h> 67 #include <sys/vmmeter.h> 68 69 #include <vm/vm.h> 70 #include <vm/vm_page.h> 71 #include <vm/vm_kern.h> 72 #include <vm/vm_pageout.h> 73 #include <vm/vm_extern.h> 74 #include <vm/vm_object.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_map.h> 77 #include <vm/vm_pager.h> 78 #include <vm/uma.h> 79 80 #include <machine/bootinfo.h> 81 #include <machine/cpu.h> 82 #include <machine/pcb.h> 83 #include <machine/platform.h> 84 85 #include <machine/tlb.h> 86 #include <machine/spr.h> 87 #include <machine/vmparam.h> 88 #include <machine/md_var.h> 89 #include <machine/mmuvar.h> 90 #include <machine/pmap.h> 91 #include <machine/pte.h> 92 93 #include "mmu_if.h" 94 95 #define DEBUG 96 #undef DEBUG 97 98 #ifdef DEBUG 99 #define debugf(fmt, args...) printf(fmt, ##args) 100 #else 101 #define debugf(fmt, args...) 102 #endif 103 104 #define TODO panic("%s: not implemented", __func__); 105 106 #include "opt_sched.h" 107 #ifndef SCHED_4BSD 108 #error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 109 #endif 110 extern struct mtx sched_lock; 111 112 extern int dumpsys_minidump; 113 114 extern unsigned char _etext[]; 115 extern unsigned char _end[]; 116 117 /* Kernel physical load address. */ 118 extern uint32_t kernload; 119 vm_offset_t kernstart; 120 vm_size_t kernsize; 121 122 /* Message buffer and tables. */ 123 static vm_offset_t data_start; 124 static vm_size_t data_end; 125 126 /* Phys/avail memory regions. */ 127 static struct mem_region *availmem_regions; 128 static int availmem_regions_sz; 129 static struct mem_region *physmem_regions; 130 static int physmem_regions_sz; 131 132 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 133 static vm_offset_t zero_page_va; 134 static struct mtx zero_page_mutex; 135 136 static struct mtx tlbivax_mutex; 137 138 /* 139 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 140 * by idle thred only, no lock required. 141 */ 142 static vm_offset_t zero_page_idle_va; 143 144 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 145 static vm_offset_t copy_page_src_va; 146 static vm_offset_t copy_page_dst_va; 147 static struct mtx copy_page_mutex; 148 149 /**************************************************************************/ 150 /* PMAP */ 151 /**************************************************************************/ 152 153 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 154 vm_prot_t, boolean_t); 155 156 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 157 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 158 159 static int pagedaemon_waken; 160 161 /* 162 * If user pmap is processed with mmu_booke_remove and the resident count 163 * drops to 0, there are no more pages to remove, so we need not continue. 164 */ 165 #define PMAP_REMOVE_DONE(pmap) \ 166 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 167 168 extern void tlb_lock(uint32_t *); 169 extern void tlb_unlock(uint32_t *); 170 extern void tid_flush(tlbtid_t); 171 172 /**************************************************************************/ 173 /* TLB and TID handling */ 174 /**************************************************************************/ 175 176 /* Translation ID busy table */ 177 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 178 179 /* 180 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 181 * core revisions and should be read from h/w registers during early config. 182 */ 183 uint32_t tlb0_entries; 184 uint32_t tlb0_ways; 185 uint32_t tlb0_entries_per_way; 186 187 #define TLB0_ENTRIES (tlb0_entries) 188 #define TLB0_WAYS (tlb0_ways) 189 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 190 191 #define TLB1_ENTRIES 16 192 193 /* In-ram copy of the TLB1 */ 194 static tlb_entry_t tlb1[TLB1_ENTRIES]; 195 196 /* Next free entry in the TLB1 */ 197 static unsigned int tlb1_idx; 198 199 static tlbtid_t tid_alloc(struct pmap *); 200 201 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 202 203 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 204 static void tlb1_write_entry(unsigned int); 205 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 206 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 207 208 static vm_size_t tsize2size(unsigned int); 209 static unsigned int size2tsize(vm_size_t); 210 static unsigned int ilog2(unsigned int); 211 212 static void set_mas4_defaults(void); 213 214 static inline void tlb0_flush_entry(vm_offset_t); 215 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 216 217 /**************************************************************************/ 218 /* Page table management */ 219 /**************************************************************************/ 220 221 /* Data for the pv entry allocation mechanism */ 222 static uma_zone_t pvzone; 223 static struct vm_object pvzone_obj; 224 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 225 226 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 227 228 #ifndef PMAP_SHPGPERPROC 229 #define PMAP_SHPGPERPROC 200 230 #endif 231 232 static void ptbl_init(void); 233 static struct ptbl_buf *ptbl_buf_alloc(void); 234 static void ptbl_buf_free(struct ptbl_buf *); 235 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 236 237 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 238 static void ptbl_free(mmu_t, pmap_t, unsigned int); 239 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 240 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 241 242 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 243 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 244 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 245 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 246 247 static pv_entry_t pv_alloc(void); 248 static void pv_free(pv_entry_t); 249 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 250 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 251 252 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 253 #define PTBL_BUFS (128 * 16) 254 255 struct ptbl_buf { 256 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 257 vm_offset_t kva; /* va of mapping */ 258 }; 259 260 /* ptbl free list and a lock used for access synchronization. */ 261 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 262 static struct mtx ptbl_buf_freelist_lock; 263 264 /* Base address of kva space allocated fot ptbl bufs. */ 265 static vm_offset_t ptbl_buf_pool_vabase; 266 267 /* Pointer to ptbl_buf structures. */ 268 static struct ptbl_buf *ptbl_bufs; 269 270 void pmap_bootstrap_ap(volatile uint32_t *); 271 272 /* 273 * Kernel MMU interface 274 */ 275 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 276 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 277 static void mmu_booke_clear_reference(mmu_t, vm_page_t); 278 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, vm_size_t, 279 vm_offset_t); 280 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 281 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 282 vm_prot_t, boolean_t); 283 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 284 vm_page_t, vm_prot_t); 285 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 286 vm_prot_t); 287 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 288 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 289 vm_prot_t); 290 static void mmu_booke_init(mmu_t); 291 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 292 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 293 static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 294 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 295 int); 296 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t); 297 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 298 vm_object_t, vm_pindex_t, vm_size_t); 299 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 300 static void mmu_booke_page_init(mmu_t, vm_page_t); 301 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 302 static void mmu_booke_pinit(mmu_t, pmap_t); 303 static void mmu_booke_pinit0(mmu_t, pmap_t); 304 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 305 vm_prot_t); 306 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 307 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 308 static void mmu_booke_release(mmu_t, pmap_t); 309 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 310 static void mmu_booke_remove_all(mmu_t, vm_page_t); 311 static void mmu_booke_remove_write(mmu_t, vm_page_t); 312 static void mmu_booke_zero_page(mmu_t, vm_page_t); 313 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 314 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 315 static void mmu_booke_activate(mmu_t, struct thread *); 316 static void mmu_booke_deactivate(mmu_t, struct thread *); 317 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 318 static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 319 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 320 static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 321 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 322 static void mmu_booke_kremove(mmu_t, vm_offset_t); 323 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 324 static boolean_t mmu_booke_page_executable(mmu_t, vm_page_t); 325 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 326 vm_size_t, vm_size_t *); 327 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 328 vm_size_t, vm_offset_t); 329 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 330 331 static mmu_method_t mmu_booke_methods[] = { 332 /* pmap dispatcher interface */ 333 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 334 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 336 MMUMETHOD(mmu_copy, mmu_booke_copy), 337 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 338 MMUMETHOD(mmu_enter, mmu_booke_enter), 339 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341 MMUMETHOD(mmu_extract, mmu_booke_extract), 342 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343 MMUMETHOD(mmu_init, mmu_booke_init), 344 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 347 MMUMETHOD(mmu_map, mmu_booke_map), 348 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 349 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 350 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 351 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 352 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 353 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 354 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 355 MMUMETHOD(mmu_protect, mmu_booke_protect), 356 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 357 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 358 MMUMETHOD(mmu_release, mmu_booke_release), 359 MMUMETHOD(mmu_remove, mmu_booke_remove), 360 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 361 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 362 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 363 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 364 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 365 MMUMETHOD(mmu_activate, mmu_booke_activate), 366 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 370 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 371 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 372 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 373 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 374 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 375 MMUMETHOD(mmu_page_executable, mmu_booke_page_executable), 376 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 377 378 /* dumpsys() support */ 379 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 380 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 381 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 382 383 { 0, 0 } 384 }; 385 386 static mmu_def_t booke_mmu = { 387 MMU_TYPE_BOOKE, 388 mmu_booke_methods, 389 0 390 }; 391 MMU_DEF(booke_mmu); 392 393 static inline void 394 tlb_miss_lock(void) 395 { 396 #ifdef SMP 397 struct pcpu *pc; 398 399 if (!smp_started) 400 return; 401 402 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 403 if (pc != pcpup) { 404 405 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 406 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 407 408 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 409 ("tlb_miss_lock: tried to lock self")); 410 411 tlb_lock(pc->pc_booke_tlb_lock); 412 413 CTR1(KTR_PMAP, "%s: locked", __func__); 414 } 415 } 416 #endif 417 } 418 419 static inline void 420 tlb_miss_unlock(void) 421 { 422 #ifdef SMP 423 struct pcpu *pc; 424 425 if (!smp_started) 426 return; 427 428 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 429 if (pc != pcpup) { 430 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 431 __func__, pc->pc_cpuid); 432 433 tlb_unlock(pc->pc_booke_tlb_lock); 434 435 CTR1(KTR_PMAP, "%s: unlocked", __func__); 436 } 437 } 438 #endif 439 } 440 441 /* Return number of entries in TLB0. */ 442 static __inline void 443 tlb0_get_tlbconf(void) 444 { 445 uint32_t tlb0_cfg; 446 447 tlb0_cfg = mfspr(SPR_TLB0CFG); 448 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 449 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 450 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 451 } 452 453 /* Initialize pool of kva ptbl buffers. */ 454 static void 455 ptbl_init(void) 456 { 457 int i; 458 459 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 460 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 461 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 462 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 463 464 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 465 TAILQ_INIT(&ptbl_buf_freelist); 466 467 for (i = 0; i < PTBL_BUFS; i++) { 468 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 469 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 470 } 471 } 472 473 /* Get a ptbl_buf from the freelist. */ 474 static struct ptbl_buf * 475 ptbl_buf_alloc(void) 476 { 477 struct ptbl_buf *buf; 478 479 mtx_lock(&ptbl_buf_freelist_lock); 480 buf = TAILQ_FIRST(&ptbl_buf_freelist); 481 if (buf != NULL) 482 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 483 mtx_unlock(&ptbl_buf_freelist_lock); 484 485 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 486 487 return (buf); 488 } 489 490 /* Return ptbl buff to free pool. */ 491 static void 492 ptbl_buf_free(struct ptbl_buf *buf) 493 { 494 495 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 496 497 mtx_lock(&ptbl_buf_freelist_lock); 498 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 499 mtx_unlock(&ptbl_buf_freelist_lock); 500 } 501 502 /* 503 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 504 */ 505 static void 506 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 507 { 508 struct ptbl_buf *pbuf; 509 510 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 511 512 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 513 514 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 515 if (pbuf->kva == (vm_offset_t)ptbl) { 516 /* Remove from pmap ptbl buf list. */ 517 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 518 519 /* Free corresponding ptbl buf. */ 520 ptbl_buf_free(pbuf); 521 break; 522 } 523 } 524 525 /* Allocate page table. */ 526 static pte_t * 527 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 528 { 529 vm_page_t mtbl[PTBL_PAGES]; 530 vm_page_t m; 531 struct ptbl_buf *pbuf; 532 unsigned int pidx; 533 pte_t *ptbl; 534 int i; 535 536 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 537 (pmap == kernel_pmap), pdir_idx); 538 539 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 540 ("ptbl_alloc: invalid pdir_idx")); 541 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 542 ("pte_alloc: valid ptbl entry exists!")); 543 544 pbuf = ptbl_buf_alloc(); 545 if (pbuf == NULL) 546 panic("pte_alloc: couldn't alloc kernel virtual memory"); 547 548 ptbl = (pte_t *)pbuf->kva; 549 550 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 551 552 /* Allocate ptbl pages, this will sleep! */ 553 for (i = 0; i < PTBL_PAGES; i++) { 554 pidx = (PTBL_PAGES * pdir_idx) + i; 555 while ((m = vm_page_alloc(NULL, pidx, 556 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 557 558 PMAP_UNLOCK(pmap); 559 vm_page_unlock_queues(); 560 VM_WAIT; 561 vm_page_lock_queues(); 562 PMAP_LOCK(pmap); 563 } 564 mtbl[i] = m; 565 } 566 567 /* Map allocated pages into kernel_pmap. */ 568 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 569 570 /* Zero whole ptbl. */ 571 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 572 573 /* Add pbuf to the pmap ptbl bufs list. */ 574 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 575 576 return (ptbl); 577 } 578 579 /* Free ptbl pages and invalidate pdir entry. */ 580 static void 581 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 582 { 583 pte_t *ptbl; 584 vm_paddr_t pa; 585 vm_offset_t va; 586 vm_page_t m; 587 int i; 588 589 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 590 (pmap == kernel_pmap), pdir_idx); 591 592 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 593 ("ptbl_free: invalid pdir_idx")); 594 595 ptbl = pmap->pm_pdir[pdir_idx]; 596 597 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 598 599 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 600 601 /* 602 * Invalidate the pdir entry as soon as possible, so that other CPUs 603 * don't attempt to look up the page tables we are releasing. 604 */ 605 mtx_lock_spin(&tlbivax_mutex); 606 tlb_miss_lock(); 607 608 pmap->pm_pdir[pdir_idx] = NULL; 609 610 tlb_miss_unlock(); 611 mtx_unlock_spin(&tlbivax_mutex); 612 613 for (i = 0; i < PTBL_PAGES; i++) { 614 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 615 pa = pte_vatopa(mmu, kernel_pmap, va); 616 m = PHYS_TO_VM_PAGE(pa); 617 vm_page_free_zero(m); 618 atomic_subtract_int(&cnt.v_wire_count, 1); 619 mmu_booke_kremove(mmu, va); 620 } 621 622 ptbl_free_pmap_ptbl(pmap, ptbl); 623 } 624 625 /* 626 * Decrement ptbl pages hold count and attempt to free ptbl pages. 627 * Called when removing pte entry from ptbl. 628 * 629 * Return 1 if ptbl pages were freed. 630 */ 631 static int 632 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 633 { 634 pte_t *ptbl; 635 vm_paddr_t pa; 636 vm_page_t m; 637 int i; 638 639 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 640 (pmap == kernel_pmap), pdir_idx); 641 642 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 643 ("ptbl_unhold: invalid pdir_idx")); 644 KASSERT((pmap != kernel_pmap), 645 ("ptbl_unhold: unholding kernel ptbl!")); 646 647 ptbl = pmap->pm_pdir[pdir_idx]; 648 649 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 650 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 651 ("ptbl_unhold: non kva ptbl")); 652 653 /* decrement hold count */ 654 for (i = 0; i < PTBL_PAGES; i++) { 655 pa = pte_vatopa(mmu, kernel_pmap, 656 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 657 m = PHYS_TO_VM_PAGE(pa); 658 m->wire_count--; 659 } 660 661 /* 662 * Free ptbl pages if there are no pte etries in this ptbl. 663 * wire_count has the same value for all ptbl pages, so check the last 664 * page. 665 */ 666 if (m->wire_count == 0) { 667 ptbl_free(mmu, pmap, pdir_idx); 668 669 //debugf("ptbl_unhold: e (freed ptbl)\n"); 670 return (1); 671 } 672 673 return (0); 674 } 675 676 /* 677 * Increment hold count for ptbl pages. This routine is used when a new pte 678 * entry is being inserted into the ptbl. 679 */ 680 static void 681 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 682 { 683 vm_paddr_t pa; 684 pte_t *ptbl; 685 vm_page_t m; 686 int i; 687 688 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 689 pdir_idx); 690 691 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 692 ("ptbl_hold: invalid pdir_idx")); 693 KASSERT((pmap != kernel_pmap), 694 ("ptbl_hold: holding kernel ptbl!")); 695 696 ptbl = pmap->pm_pdir[pdir_idx]; 697 698 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 699 700 for (i = 0; i < PTBL_PAGES; i++) { 701 pa = pte_vatopa(mmu, kernel_pmap, 702 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 703 m = PHYS_TO_VM_PAGE(pa); 704 m->wire_count++; 705 } 706 } 707 708 /* Allocate pv_entry structure. */ 709 pv_entry_t 710 pv_alloc(void) 711 { 712 pv_entry_t pv; 713 714 pv_entry_count++; 715 if ((pv_entry_count > pv_entry_high_water) && 716 (pagedaemon_waken == 0)) { 717 pagedaemon_waken = 1; 718 wakeup(&vm_pages_needed); 719 } 720 pv = uma_zalloc(pvzone, M_NOWAIT); 721 722 return (pv); 723 } 724 725 /* Free pv_entry structure. */ 726 static __inline void 727 pv_free(pv_entry_t pve) 728 { 729 730 pv_entry_count--; 731 uma_zfree(pvzone, pve); 732 } 733 734 735 /* Allocate and initialize pv_entry structure. */ 736 static void 737 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 738 { 739 pv_entry_t pve; 740 741 //int su = (pmap == kernel_pmap); 742 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 743 // (u_int32_t)pmap, va, (u_int32_t)m); 744 745 pve = pv_alloc(); 746 if (pve == NULL) 747 panic("pv_insert: no pv entries!"); 748 749 pve->pv_pmap = pmap; 750 pve->pv_va = va; 751 752 /* add to pv_list */ 753 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 754 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 755 756 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 757 758 //debugf("pv_insert: e\n"); 759 } 760 761 /* Destroy pv entry. */ 762 static void 763 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 764 { 765 pv_entry_t pve; 766 767 //int su = (pmap == kernel_pmap); 768 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 769 770 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 771 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 772 773 /* find pv entry */ 774 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 775 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 776 /* remove from pv_list */ 777 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 778 if (TAILQ_EMPTY(&m->md.pv_list)) 779 vm_page_flag_clear(m, PG_WRITEABLE); 780 781 /* free pv entry struct */ 782 pv_free(pve); 783 break; 784 } 785 } 786 787 //debugf("pv_remove: e\n"); 788 } 789 790 /* 791 * Clean pte entry, try to free page table page if requested. 792 * 793 * Return 1 if ptbl pages were freed, otherwise return 0. 794 */ 795 static int 796 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 797 { 798 unsigned int pdir_idx = PDIR_IDX(va); 799 unsigned int ptbl_idx = PTBL_IDX(va); 800 vm_page_t m; 801 pte_t *ptbl; 802 pte_t *pte; 803 804 //int su = (pmap == kernel_pmap); 805 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 806 // su, (u_int32_t)pmap, va, flags); 807 808 ptbl = pmap->pm_pdir[pdir_idx]; 809 KASSERT(ptbl, ("pte_remove: null ptbl")); 810 811 pte = &ptbl[ptbl_idx]; 812 813 if (pte == NULL || !PTE_ISVALID(pte)) 814 return (0); 815 816 if (PTE_ISWIRED(pte)) 817 pmap->pm_stats.wired_count--; 818 819 /* Handle managed entry. */ 820 if (PTE_ISMANAGED(pte)) { 821 /* Get vm_page_t for mapped pte. */ 822 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 823 824 if (PTE_ISMODIFIED(pte)) 825 vm_page_dirty(m); 826 827 if (PTE_ISREFERENCED(pte)) 828 vm_page_flag_set(m, PG_REFERENCED); 829 830 pv_remove(pmap, va, m); 831 } 832 833 mtx_lock_spin(&tlbivax_mutex); 834 tlb_miss_lock(); 835 836 tlb0_flush_entry(va); 837 pte->flags = 0; 838 pte->rpn = 0; 839 840 tlb_miss_unlock(); 841 mtx_unlock_spin(&tlbivax_mutex); 842 843 pmap->pm_stats.resident_count--; 844 845 if (flags & PTBL_UNHOLD) { 846 //debugf("pte_remove: e (unhold)\n"); 847 return (ptbl_unhold(mmu, pmap, pdir_idx)); 848 } 849 850 //debugf("pte_remove: e\n"); 851 return (0); 852 } 853 854 /* 855 * Insert PTE for a given page and virtual address. 856 */ 857 static void 858 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 859 { 860 unsigned int pdir_idx = PDIR_IDX(va); 861 unsigned int ptbl_idx = PTBL_IDX(va); 862 pte_t *ptbl, *pte; 863 864 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 865 pmap == kernel_pmap, pmap, va); 866 867 /* Get the page table pointer. */ 868 ptbl = pmap->pm_pdir[pdir_idx]; 869 870 if (ptbl == NULL) { 871 /* Allocate page table pages. */ 872 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 873 } else { 874 /* 875 * Check if there is valid mapping for requested 876 * va, if there is, remove it. 877 */ 878 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 879 if (PTE_ISVALID(pte)) { 880 pte_remove(mmu, pmap, va, PTBL_HOLD); 881 } else { 882 /* 883 * pte is not used, increment hold count 884 * for ptbl pages. 885 */ 886 if (pmap != kernel_pmap) 887 ptbl_hold(mmu, pmap, pdir_idx); 888 } 889 } 890 891 /* 892 * Insert pv_entry into pv_list for mapped page if part of managed 893 * memory. 894 */ 895 if ((m->flags & PG_FICTITIOUS) == 0) { 896 if ((m->flags & PG_UNMANAGED) == 0) { 897 flags |= PTE_MANAGED; 898 899 /* Create and insert pv entry. */ 900 pv_insert(pmap, va, m); 901 } 902 } 903 904 pmap->pm_stats.resident_count++; 905 906 mtx_lock_spin(&tlbivax_mutex); 907 tlb_miss_lock(); 908 909 tlb0_flush_entry(va); 910 if (pmap->pm_pdir[pdir_idx] == NULL) { 911 /* 912 * If we just allocated a new page table, hook it in 913 * the pdir. 914 */ 915 pmap->pm_pdir[pdir_idx] = ptbl; 916 } 917 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 918 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 919 pte->flags |= (PTE_VALID | flags); 920 921 tlb_miss_unlock(); 922 mtx_unlock_spin(&tlbivax_mutex); 923 } 924 925 /* Return the pa for the given pmap/va. */ 926 static vm_paddr_t 927 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 928 { 929 vm_paddr_t pa = 0; 930 pte_t *pte; 931 932 pte = pte_find(mmu, pmap, va); 933 if ((pte != NULL) && PTE_ISVALID(pte)) 934 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 935 return (pa); 936 } 937 938 /* Get a pointer to a PTE in a page table. */ 939 static pte_t * 940 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 941 { 942 unsigned int pdir_idx = PDIR_IDX(va); 943 unsigned int ptbl_idx = PTBL_IDX(va); 944 945 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 946 947 if (pmap->pm_pdir[pdir_idx]) 948 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 949 950 return (NULL); 951 } 952 953 /**************************************************************************/ 954 /* PMAP related */ 955 /**************************************************************************/ 956 957 /* 958 * This is called during e500_init, before the system is really initialized. 959 */ 960 static void 961 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 962 { 963 vm_offset_t phys_kernelend; 964 struct mem_region *mp, *mp1; 965 int cnt, i, j; 966 u_int s, e, sz; 967 u_int phys_avail_count; 968 vm_size_t physsz, hwphyssz, kstack0_sz; 969 vm_offset_t kernel_pdir, kstack0; 970 vm_paddr_t kstack0_phys; 971 972 debugf("mmu_booke_bootstrap: entered\n"); 973 974 /* Initialize invalidation mutex */ 975 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 976 977 /* Read TLB0 size and associativity. */ 978 tlb0_get_tlbconf(); 979 980 /* Align kernel start and end address (kernel image). */ 981 kernstart = trunc_page(start); 982 data_start = round_page(kernelend); 983 kernsize = data_start - kernstart; 984 985 data_end = data_start; 986 987 /* Allocate space for the message buffer. */ 988 msgbufp = (struct msgbuf *)data_end; 989 data_end += MSGBUF_SIZE; 990 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 991 data_end); 992 993 data_end = round_page(data_end); 994 995 /* Allocate space for ptbl_bufs. */ 996 ptbl_bufs = (struct ptbl_buf *)data_end; 997 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 998 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 999 data_end); 1000 1001 data_end = round_page(data_end); 1002 1003 /* Allocate PTE tables for kernel KVA. */ 1004 kernel_pdir = data_end; 1005 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1006 PDIR_SIZE - 1) / PDIR_SIZE; 1007 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1008 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1009 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1010 1011 debugf(" data_end: 0x%08x\n", data_end); 1012 if (data_end - kernstart > 0x1000000) { 1013 data_end = (data_end + 0x3fffff) & ~0x3fffff; 1014 tlb1_mapin_region(kernstart + 0x1000000, 1015 kernload + 0x1000000, data_end - kernstart - 0x1000000); 1016 } else 1017 data_end = (data_end + 0xffffff) & ~0xffffff; 1018 1019 debugf(" updated data_end: 0x%08x\n", data_end); 1020 1021 kernsize += data_end - data_start; 1022 1023 /* 1024 * Clear the structures - note we can only do it safely after the 1025 * possible additional TLB1 translations are in place (above) so that 1026 * all range up to the currently calculated 'data_end' is covered. 1027 */ 1028 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1029 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1030 1031 /*******************************************************/ 1032 /* Set the start and end of kva. */ 1033 /*******************************************************/ 1034 virtual_avail = round_page(data_end); 1035 virtual_end = VM_MAX_KERNEL_ADDRESS; 1036 1037 /* Allocate KVA space for page zero/copy operations. */ 1038 zero_page_va = virtual_avail; 1039 virtual_avail += PAGE_SIZE; 1040 zero_page_idle_va = virtual_avail; 1041 virtual_avail += PAGE_SIZE; 1042 copy_page_src_va = virtual_avail; 1043 virtual_avail += PAGE_SIZE; 1044 copy_page_dst_va = virtual_avail; 1045 virtual_avail += PAGE_SIZE; 1046 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1047 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1048 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1049 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1050 1051 /* Initialize page zero/copy mutexes. */ 1052 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1053 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1054 1055 /* Allocate KVA space for ptbl bufs. */ 1056 ptbl_buf_pool_vabase = virtual_avail; 1057 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1058 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1059 ptbl_buf_pool_vabase, virtual_avail); 1060 1061 /* Calculate corresponding physical addresses for the kernel region. */ 1062 phys_kernelend = kernload + kernsize; 1063 debugf("kernel image and allocated data:\n"); 1064 debugf(" kernload = 0x%08x\n", kernload); 1065 debugf(" kernstart = 0x%08x\n", kernstart); 1066 debugf(" kernsize = 0x%08x\n", kernsize); 1067 1068 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1069 panic("mmu_booke_bootstrap: phys_avail too small"); 1070 1071 /* 1072 * Remove kernel physical address range from avail regions list. Page 1073 * align all regions. Non-page aligned memory isn't very interesting 1074 * to us. Also, sort the entries for ascending addresses. 1075 */ 1076 1077 /* Retrieve phys/avail mem regions */ 1078 mem_regions(&physmem_regions, &physmem_regions_sz, 1079 &availmem_regions, &availmem_regions_sz); 1080 sz = 0; 1081 cnt = availmem_regions_sz; 1082 debugf("processing avail regions:\n"); 1083 for (mp = availmem_regions; mp->mr_size; mp++) { 1084 s = mp->mr_start; 1085 e = mp->mr_start + mp->mr_size; 1086 debugf(" %08x-%08x -> ", s, e); 1087 /* Check whether this region holds all of the kernel. */ 1088 if (s < kernload && e > phys_kernelend) { 1089 availmem_regions[cnt].mr_start = phys_kernelend; 1090 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1091 e = kernload; 1092 } 1093 /* Look whether this regions starts within the kernel. */ 1094 if (s >= kernload && s < phys_kernelend) { 1095 if (e <= phys_kernelend) 1096 goto empty; 1097 s = phys_kernelend; 1098 } 1099 /* Now look whether this region ends within the kernel. */ 1100 if (e > kernload && e <= phys_kernelend) { 1101 if (s >= kernload) 1102 goto empty; 1103 e = kernload; 1104 } 1105 /* Now page align the start and size of the region. */ 1106 s = round_page(s); 1107 e = trunc_page(e); 1108 if (e < s) 1109 e = s; 1110 sz = e - s; 1111 debugf("%08x-%08x = %x\n", s, e, sz); 1112 1113 /* Check whether some memory is left here. */ 1114 if (sz == 0) { 1115 empty: 1116 memmove(mp, mp + 1, 1117 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1118 cnt--; 1119 mp--; 1120 continue; 1121 } 1122 1123 /* Do an insertion sort. */ 1124 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1125 if (s < mp1->mr_start) 1126 break; 1127 if (mp1 < mp) { 1128 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1129 mp1->mr_start = s; 1130 mp1->mr_size = sz; 1131 } else { 1132 mp->mr_start = s; 1133 mp->mr_size = sz; 1134 } 1135 } 1136 availmem_regions_sz = cnt; 1137 1138 /*******************************************************/ 1139 /* Steal physical memory for kernel stack from the end */ 1140 /* of the first avail region */ 1141 /*******************************************************/ 1142 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1143 kstack0_phys = availmem_regions[0].mr_start + 1144 availmem_regions[0].mr_size; 1145 kstack0_phys -= kstack0_sz; 1146 availmem_regions[0].mr_size -= kstack0_sz; 1147 1148 /*******************************************************/ 1149 /* Fill in phys_avail table, based on availmem_regions */ 1150 /*******************************************************/ 1151 phys_avail_count = 0; 1152 physsz = 0; 1153 hwphyssz = 0; 1154 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1155 1156 debugf("fill in phys_avail:\n"); 1157 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1158 1159 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1160 availmem_regions[i].mr_start, 1161 availmem_regions[i].mr_start + 1162 availmem_regions[i].mr_size, 1163 availmem_regions[i].mr_size); 1164 1165 if (hwphyssz != 0 && 1166 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1167 debugf(" hw.physmem adjust\n"); 1168 if (physsz < hwphyssz) { 1169 phys_avail[j] = availmem_regions[i].mr_start; 1170 phys_avail[j + 1] = 1171 availmem_regions[i].mr_start + 1172 hwphyssz - physsz; 1173 physsz = hwphyssz; 1174 phys_avail_count++; 1175 } 1176 break; 1177 } 1178 1179 phys_avail[j] = availmem_regions[i].mr_start; 1180 phys_avail[j + 1] = availmem_regions[i].mr_start + 1181 availmem_regions[i].mr_size; 1182 phys_avail_count++; 1183 physsz += availmem_regions[i].mr_size; 1184 } 1185 physmem = btoc(physsz); 1186 1187 /* Calculate the last available physical address. */ 1188 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1189 ; 1190 Maxmem = powerpc_btop(phys_avail[i + 1]); 1191 1192 debugf("Maxmem = 0x%08lx\n", Maxmem); 1193 debugf("phys_avail_count = %d\n", phys_avail_count); 1194 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1195 physmem); 1196 1197 /*******************************************************/ 1198 /* Initialize (statically allocated) kernel pmap. */ 1199 /*******************************************************/ 1200 PMAP_LOCK_INIT(kernel_pmap); 1201 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1202 1203 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1204 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1205 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1206 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1207 1208 /* Initialize kernel pdir */ 1209 for (i = 0; i < kernel_ptbls; i++) 1210 kernel_pmap->pm_pdir[kptbl_min + i] = 1211 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1212 1213 for (i = 0; i < MAXCPU; i++) { 1214 kernel_pmap->pm_tid[i] = TID_KERNEL; 1215 1216 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1217 tidbusy[i][0] = kernel_pmap; 1218 } 1219 /* Mark kernel_pmap active on all CPUs */ 1220 kernel_pmap->pm_active = ~0; 1221 1222 /*******************************************************/ 1223 /* Final setup */ 1224 /*******************************************************/ 1225 1226 /* Enter kstack0 into kernel map, provide guard page */ 1227 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1228 thread0.td_kstack = kstack0; 1229 thread0.td_kstack_pages = KSTACK_PAGES; 1230 1231 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1232 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1233 kstack0_phys, kstack0_phys + kstack0_sz); 1234 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1235 1236 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1237 for (i = 0; i < KSTACK_PAGES; i++) { 1238 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1239 kstack0 += PAGE_SIZE; 1240 kstack0_phys += PAGE_SIZE; 1241 } 1242 1243 debugf("virtual_avail = %08x\n", virtual_avail); 1244 debugf("virtual_end = %08x\n", virtual_end); 1245 1246 debugf("mmu_booke_bootstrap: exit\n"); 1247 } 1248 1249 void 1250 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1251 { 1252 int i; 1253 1254 /* 1255 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1256 * have the snapshot of its contents in the s/w tlb1[] table, so use 1257 * these values directly to (re)program AP's TLB1 hardware. 1258 */ 1259 for (i = 0; i < tlb1_idx; i ++) { 1260 /* Skip invalid entries */ 1261 if (!(tlb1[i].mas1 & MAS1_VALID)) 1262 continue; 1263 1264 tlb1_write_entry(i); 1265 } 1266 1267 set_mas4_defaults(); 1268 } 1269 1270 /* 1271 * Get the physical page address for the given pmap/virtual address. 1272 */ 1273 static vm_paddr_t 1274 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1275 { 1276 vm_paddr_t pa; 1277 1278 PMAP_LOCK(pmap); 1279 pa = pte_vatopa(mmu, pmap, va); 1280 PMAP_UNLOCK(pmap); 1281 1282 return (pa); 1283 } 1284 1285 /* 1286 * Extract the physical page address associated with the given 1287 * kernel virtual address. 1288 */ 1289 static vm_paddr_t 1290 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1291 { 1292 1293 return (pte_vatopa(mmu, kernel_pmap, va)); 1294 } 1295 1296 /* 1297 * Initialize the pmap module. 1298 * Called by vm_init, to initialize any structures that the pmap 1299 * system needs to map virtual memory. 1300 */ 1301 static void 1302 mmu_booke_init(mmu_t mmu) 1303 { 1304 int shpgperproc = PMAP_SHPGPERPROC; 1305 1306 /* 1307 * Initialize the address space (zone) for the pv entries. Set a 1308 * high water mark so that the system can recover from excessive 1309 * numbers of pv entries. 1310 */ 1311 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1312 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1313 1314 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1315 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1316 1317 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1318 pv_entry_high_water = 9 * (pv_entry_max / 10); 1319 1320 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1321 1322 /* Pre-fill pvzone with initial number of pv entries. */ 1323 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1324 1325 /* Initialize ptbl allocation. */ 1326 ptbl_init(); 1327 } 1328 1329 /* 1330 * Map a list of wired pages into kernel virtual address space. This is 1331 * intended for temporary mappings which do not need page modification or 1332 * references recorded. Existing mappings in the region are overwritten. 1333 */ 1334 static void 1335 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1336 { 1337 vm_offset_t va; 1338 1339 va = sva; 1340 while (count-- > 0) { 1341 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1342 va += PAGE_SIZE; 1343 m++; 1344 } 1345 } 1346 1347 /* 1348 * Remove page mappings from kernel virtual address space. Intended for 1349 * temporary mappings entered by mmu_booke_qenter. 1350 */ 1351 static void 1352 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1353 { 1354 vm_offset_t va; 1355 1356 va = sva; 1357 while (count-- > 0) { 1358 mmu_booke_kremove(mmu, va); 1359 va += PAGE_SIZE; 1360 } 1361 } 1362 1363 /* 1364 * Map a wired page into kernel virtual address space. 1365 */ 1366 static void 1367 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1368 { 1369 unsigned int pdir_idx = PDIR_IDX(va); 1370 unsigned int ptbl_idx = PTBL_IDX(va); 1371 uint32_t flags; 1372 pte_t *pte; 1373 1374 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1375 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1376 1377 flags = 0; 1378 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1379 flags |= PTE_M; 1380 1381 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1382 1383 mtx_lock_spin(&tlbivax_mutex); 1384 tlb_miss_lock(); 1385 1386 if (PTE_ISVALID(pte)) { 1387 1388 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1389 1390 /* Flush entry from TLB0 */ 1391 tlb0_flush_entry(va); 1392 } 1393 1394 pte->rpn = pa & ~PTE_PA_MASK; 1395 pte->flags = flags; 1396 1397 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1398 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1399 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1400 1401 /* Flush the real memory from the instruction cache. */ 1402 if ((flags & (PTE_I | PTE_G)) == 0) { 1403 __syncicache((void *)va, PAGE_SIZE); 1404 } 1405 1406 tlb_miss_unlock(); 1407 mtx_unlock_spin(&tlbivax_mutex); 1408 } 1409 1410 /* 1411 * Remove a page from kernel page table. 1412 */ 1413 static void 1414 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1415 { 1416 unsigned int pdir_idx = PDIR_IDX(va); 1417 unsigned int ptbl_idx = PTBL_IDX(va); 1418 pte_t *pte; 1419 1420 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1421 1422 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1423 (va <= VM_MAX_KERNEL_ADDRESS)), 1424 ("mmu_booke_kremove: invalid va")); 1425 1426 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1427 1428 if (!PTE_ISVALID(pte)) { 1429 1430 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1431 1432 return; 1433 } 1434 1435 mtx_lock_spin(&tlbivax_mutex); 1436 tlb_miss_lock(); 1437 1438 /* Invalidate entry in TLB0, update PTE. */ 1439 tlb0_flush_entry(va); 1440 pte->flags = 0; 1441 pte->rpn = 0; 1442 1443 tlb_miss_unlock(); 1444 mtx_unlock_spin(&tlbivax_mutex); 1445 } 1446 1447 /* 1448 * Initialize pmap associated with process 0. 1449 */ 1450 static void 1451 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1452 { 1453 1454 mmu_booke_pinit(mmu, pmap); 1455 PCPU_SET(curpmap, pmap); 1456 } 1457 1458 /* 1459 * Initialize a preallocated and zeroed pmap structure, 1460 * such as one in a vmspace structure. 1461 */ 1462 static void 1463 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1464 { 1465 int i; 1466 1467 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1468 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1469 1470 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1471 1472 PMAP_LOCK_INIT(pmap); 1473 for (i = 0; i < MAXCPU; i++) 1474 pmap->pm_tid[i] = TID_NONE; 1475 pmap->pm_active = 0; 1476 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1477 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1478 TAILQ_INIT(&pmap->pm_ptbl_list); 1479 } 1480 1481 /* 1482 * Release any resources held by the given physical map. 1483 * Called when a pmap initialized by mmu_booke_pinit is being released. 1484 * Should only be called if the map contains no valid mappings. 1485 */ 1486 static void 1487 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1488 { 1489 1490 printf("mmu_booke_release: s\n"); 1491 1492 KASSERT(pmap->pm_stats.resident_count == 0, 1493 ("pmap_release: pmap resident count %ld != 0", 1494 pmap->pm_stats.resident_count)); 1495 1496 PMAP_LOCK_DESTROY(pmap); 1497 } 1498 1499 /* 1500 * Insert the given physical page at the specified virtual address in the 1501 * target physical map with the protection requested. If specified the page 1502 * will be wired down. 1503 */ 1504 static void 1505 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1506 vm_prot_t prot, boolean_t wired) 1507 { 1508 1509 vm_page_lock_queues(); 1510 PMAP_LOCK(pmap); 1511 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1512 vm_page_unlock_queues(); 1513 PMAP_UNLOCK(pmap); 1514 } 1515 1516 static void 1517 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1518 vm_prot_t prot, boolean_t wired) 1519 { 1520 pte_t *pte; 1521 vm_paddr_t pa; 1522 uint32_t flags; 1523 int su, sync; 1524 1525 pa = VM_PAGE_TO_PHYS(m); 1526 su = (pmap == kernel_pmap); 1527 sync = 0; 1528 1529 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1530 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1531 // (u_int32_t)pmap, su, pmap->pm_tid, 1532 // (u_int32_t)m, va, pa, prot, wired); 1533 1534 if (su) { 1535 KASSERT(((va >= virtual_avail) && 1536 (va <= VM_MAX_KERNEL_ADDRESS)), 1537 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1538 } else { 1539 KASSERT((va <= VM_MAXUSER_ADDRESS), 1540 ("mmu_booke_enter_locked: user pmap, non user va")); 1541 } 1542 1543 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1544 1545 /* 1546 * If there is an existing mapping, and the physical address has not 1547 * changed, must be protection or wiring change. 1548 */ 1549 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1550 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1551 1552 /* 1553 * Before actually updating pte->flags we calculate and 1554 * prepare its new value in a helper var. 1555 */ 1556 flags = pte->flags; 1557 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1558 1559 /* Wiring change, just update stats. */ 1560 if (wired) { 1561 if (!PTE_ISWIRED(pte)) { 1562 flags |= PTE_WIRED; 1563 pmap->pm_stats.wired_count++; 1564 } 1565 } else { 1566 if (PTE_ISWIRED(pte)) { 1567 flags &= ~PTE_WIRED; 1568 pmap->pm_stats.wired_count--; 1569 } 1570 } 1571 1572 if (prot & VM_PROT_WRITE) { 1573 /* Add write permissions. */ 1574 flags |= PTE_SW; 1575 if (!su) 1576 flags |= PTE_UW; 1577 1578 vm_page_flag_set(m, PG_WRITEABLE); 1579 } else { 1580 /* Handle modified pages, sense modify status. */ 1581 1582 /* 1583 * The PTE_MODIFIED flag could be set by underlying 1584 * TLB misses since we last read it (above), possibly 1585 * other CPUs could update it so we check in the PTE 1586 * directly rather than rely on that saved local flags 1587 * copy. 1588 */ 1589 if (PTE_ISMODIFIED(pte)) 1590 vm_page_dirty(m); 1591 } 1592 1593 if (prot & VM_PROT_EXECUTE) { 1594 flags |= PTE_SX; 1595 if (!su) 1596 flags |= PTE_UX; 1597 1598 /* 1599 * Check existing flags for execute permissions: if we 1600 * are turning execute permissions on, icache should 1601 * be flushed. 1602 */ 1603 if ((flags & (PTE_UX | PTE_SX)) == 0) 1604 sync++; 1605 } 1606 1607 flags &= ~PTE_REFERENCED; 1608 1609 /* 1610 * The new flags value is all calculated -- only now actually 1611 * update the PTE. 1612 */ 1613 mtx_lock_spin(&tlbivax_mutex); 1614 tlb_miss_lock(); 1615 1616 tlb0_flush_entry(va); 1617 pte->flags = flags; 1618 1619 tlb_miss_unlock(); 1620 mtx_unlock_spin(&tlbivax_mutex); 1621 1622 } else { 1623 /* 1624 * If there is an existing mapping, but it's for a different 1625 * physical address, pte_enter() will delete the old mapping. 1626 */ 1627 //if ((pte != NULL) && PTE_ISVALID(pte)) 1628 // debugf("mmu_booke_enter_locked: replace\n"); 1629 //else 1630 // debugf("mmu_booke_enter_locked: new\n"); 1631 1632 /* Now set up the flags and install the new mapping. */ 1633 flags = (PTE_SR | PTE_VALID); 1634 flags |= PTE_M; 1635 1636 if (!su) 1637 flags |= PTE_UR; 1638 1639 if (prot & VM_PROT_WRITE) { 1640 flags |= PTE_SW; 1641 if (!su) 1642 flags |= PTE_UW; 1643 1644 vm_page_flag_set(m, PG_WRITEABLE); 1645 } 1646 1647 if (prot & VM_PROT_EXECUTE) { 1648 flags |= PTE_SX; 1649 if (!su) 1650 flags |= PTE_UX; 1651 } 1652 1653 /* If its wired update stats. */ 1654 if (wired) { 1655 pmap->pm_stats.wired_count++; 1656 flags |= PTE_WIRED; 1657 } 1658 1659 pte_enter(mmu, pmap, m, va, flags); 1660 1661 /* Flush the real memory from the instruction cache. */ 1662 if (prot & VM_PROT_EXECUTE) 1663 sync++; 1664 } 1665 1666 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1667 __syncicache((void *)va, PAGE_SIZE); 1668 sync = 0; 1669 } 1670 1671 if (sync) { 1672 /* Create a temporary mapping. */ 1673 pmap = PCPU_GET(curpmap); 1674 1675 va = 0; 1676 pte = pte_find(mmu, pmap, va); 1677 KASSERT(pte == NULL, ("%s:%d", __func__, __LINE__)); 1678 1679 flags = PTE_SR | PTE_VALID | PTE_UR | PTE_M; 1680 1681 pte_enter(mmu, pmap, m, va, flags); 1682 __syncicache((void *)va, PAGE_SIZE); 1683 pte_remove(mmu, pmap, va, PTBL_UNHOLD); 1684 } 1685 } 1686 1687 /* 1688 * Maps a sequence of resident pages belonging to the same object. 1689 * The sequence begins with the given page m_start. This page is 1690 * mapped at the given virtual address start. Each subsequent page is 1691 * mapped at a virtual address that is offset from start by the same 1692 * amount as the page is offset from m_start within the object. The 1693 * last page in the sequence is the page with the largest offset from 1694 * m_start that can be mapped at a virtual address less than the given 1695 * virtual address end. Not every virtual page between start and end 1696 * is mapped; only those for which a resident page exists with the 1697 * corresponding offset from m_start are mapped. 1698 */ 1699 static void 1700 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1701 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1702 { 1703 vm_page_t m; 1704 vm_pindex_t diff, psize; 1705 1706 psize = atop(end - start); 1707 m = m_start; 1708 PMAP_LOCK(pmap); 1709 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1710 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1711 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1712 m = TAILQ_NEXT(m, listq); 1713 } 1714 PMAP_UNLOCK(pmap); 1715 } 1716 1717 static void 1718 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1719 vm_prot_t prot) 1720 { 1721 1722 PMAP_LOCK(pmap); 1723 mmu_booke_enter_locked(mmu, pmap, va, m, 1724 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1725 PMAP_UNLOCK(pmap); 1726 } 1727 1728 /* 1729 * Remove the given range of addresses from the specified map. 1730 * 1731 * It is assumed that the start and end are properly rounded to the page size. 1732 */ 1733 static void 1734 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1735 { 1736 pte_t *pte; 1737 uint8_t hold_flag; 1738 1739 int su = (pmap == kernel_pmap); 1740 1741 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1742 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1743 1744 if (su) { 1745 KASSERT(((va >= virtual_avail) && 1746 (va <= VM_MAX_KERNEL_ADDRESS)), 1747 ("mmu_booke_remove: kernel pmap, non kernel va")); 1748 } else { 1749 KASSERT((va <= VM_MAXUSER_ADDRESS), 1750 ("mmu_booke_remove: user pmap, non user va")); 1751 } 1752 1753 if (PMAP_REMOVE_DONE(pmap)) { 1754 //debugf("mmu_booke_remove: e (empty)\n"); 1755 return; 1756 } 1757 1758 hold_flag = PTBL_HOLD_FLAG(pmap); 1759 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1760 1761 vm_page_lock_queues(); 1762 PMAP_LOCK(pmap); 1763 for (; va < endva; va += PAGE_SIZE) { 1764 pte = pte_find(mmu, pmap, va); 1765 if ((pte != NULL) && PTE_ISVALID(pte)) 1766 pte_remove(mmu, pmap, va, hold_flag); 1767 } 1768 PMAP_UNLOCK(pmap); 1769 vm_page_unlock_queues(); 1770 1771 //debugf("mmu_booke_remove: e\n"); 1772 } 1773 1774 /* 1775 * Remove physical page from all pmaps in which it resides. 1776 */ 1777 static void 1778 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1779 { 1780 pv_entry_t pv, pvn; 1781 uint8_t hold_flag; 1782 1783 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1784 1785 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1786 pvn = TAILQ_NEXT(pv, pv_link); 1787 1788 PMAP_LOCK(pv->pv_pmap); 1789 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1790 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1791 PMAP_UNLOCK(pv->pv_pmap); 1792 } 1793 vm_page_flag_clear(m, PG_WRITEABLE); 1794 } 1795 1796 /* 1797 * Map a range of physical addresses into kernel virtual address space. 1798 */ 1799 static vm_offset_t 1800 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1801 vm_offset_t pa_end, int prot) 1802 { 1803 vm_offset_t sva = *virt; 1804 vm_offset_t va = sva; 1805 1806 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1807 // sva, pa_start, pa_end); 1808 1809 while (pa_start < pa_end) { 1810 mmu_booke_kenter(mmu, va, pa_start); 1811 va += PAGE_SIZE; 1812 pa_start += PAGE_SIZE; 1813 } 1814 *virt = va; 1815 1816 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1817 return (sva); 1818 } 1819 1820 /* 1821 * The pmap must be activated before it's address space can be accessed in any 1822 * way. 1823 */ 1824 static void 1825 mmu_booke_activate(mmu_t mmu, struct thread *td) 1826 { 1827 pmap_t pmap; 1828 1829 pmap = &td->td_proc->p_vmspace->vm_pmap; 1830 1831 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1832 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1833 1834 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1835 1836 mtx_lock_spin(&sched_lock); 1837 1838 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1839 PCPU_SET(curpmap, pmap); 1840 1841 if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1842 tid_alloc(pmap); 1843 1844 /* Load PID0 register with pmap tid value. */ 1845 mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1846 __asm __volatile("isync"); 1847 1848 mtx_unlock_spin(&sched_lock); 1849 1850 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1851 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1852 } 1853 1854 /* 1855 * Deactivate the specified process's address space. 1856 */ 1857 static void 1858 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1859 { 1860 pmap_t pmap; 1861 1862 pmap = &td->td_proc->p_vmspace->vm_pmap; 1863 1864 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1865 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1866 1867 atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1868 PCPU_SET(curpmap, NULL); 1869 } 1870 1871 /* 1872 * Copy the range specified by src_addr/len 1873 * from the source map to the range dst_addr/len 1874 * in the destination map. 1875 * 1876 * This routine is only advisory and need not do anything. 1877 */ 1878 static void 1879 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1880 vm_size_t len, vm_offset_t src_addr) 1881 { 1882 1883 } 1884 1885 /* 1886 * Set the physical protection on the specified range of this map as requested. 1887 */ 1888 static void 1889 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1890 vm_prot_t prot) 1891 { 1892 vm_offset_t va; 1893 vm_page_t m; 1894 pte_t *pte; 1895 1896 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1897 mmu_booke_remove(mmu, pmap, sva, eva); 1898 return; 1899 } 1900 1901 if (prot & VM_PROT_WRITE) 1902 return; 1903 1904 vm_page_lock_queues(); 1905 PMAP_LOCK(pmap); 1906 for (va = sva; va < eva; va += PAGE_SIZE) { 1907 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1908 if (PTE_ISVALID(pte)) { 1909 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1910 1911 mtx_lock_spin(&tlbivax_mutex); 1912 tlb_miss_lock(); 1913 1914 /* Handle modified pages. */ 1915 if (PTE_ISMODIFIED(pte)) 1916 vm_page_dirty(m); 1917 1918 /* Referenced pages. */ 1919 if (PTE_ISREFERENCED(pte)) 1920 vm_page_flag_set(m, PG_REFERENCED); 1921 1922 tlb0_flush_entry(va); 1923 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1924 PTE_REFERENCED); 1925 1926 tlb_miss_unlock(); 1927 mtx_unlock_spin(&tlbivax_mutex); 1928 } 1929 } 1930 } 1931 PMAP_UNLOCK(pmap); 1932 vm_page_unlock_queues(); 1933 } 1934 1935 /* 1936 * Clear the write and modified bits in each of the given page's mappings. 1937 */ 1938 static void 1939 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1940 { 1941 pv_entry_t pv; 1942 pte_t *pte; 1943 1944 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1945 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1946 (m->flags & PG_WRITEABLE) == 0) 1947 return; 1948 1949 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1950 PMAP_LOCK(pv->pv_pmap); 1951 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1952 if (PTE_ISVALID(pte)) { 1953 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1954 1955 mtx_lock_spin(&tlbivax_mutex); 1956 tlb_miss_lock(); 1957 1958 /* Handle modified pages. */ 1959 if (PTE_ISMODIFIED(pte)) 1960 vm_page_dirty(m); 1961 1962 /* Referenced pages. */ 1963 if (PTE_ISREFERENCED(pte)) 1964 vm_page_flag_set(m, PG_REFERENCED); 1965 1966 /* Flush mapping from TLB0. */ 1967 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1968 PTE_REFERENCED); 1969 1970 tlb_miss_unlock(); 1971 mtx_unlock_spin(&tlbivax_mutex); 1972 } 1973 } 1974 PMAP_UNLOCK(pv->pv_pmap); 1975 } 1976 vm_page_flag_clear(m, PG_WRITEABLE); 1977 } 1978 1979 static boolean_t 1980 mmu_booke_page_executable(mmu_t mmu, vm_page_t m) 1981 { 1982 pv_entry_t pv; 1983 pte_t *pte; 1984 boolean_t executable; 1985 1986 executable = FALSE; 1987 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1988 PMAP_LOCK(pv->pv_pmap); 1989 pte = pte_find(mmu, pv->pv_pmap, pv->pv_va); 1990 if (pte != NULL && PTE_ISVALID(pte) && (pte->flags & PTE_UX)) 1991 executable = TRUE; 1992 PMAP_UNLOCK(pv->pv_pmap); 1993 if (executable) 1994 break; 1995 } 1996 1997 return (executable); 1998 } 1999 2000 /* 2001 * Atomically extract and hold the physical page with the given 2002 * pmap and virtual address pair if that mapping permits the given 2003 * protection. 2004 */ 2005 static vm_page_t 2006 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2007 vm_prot_t prot) 2008 { 2009 pte_t *pte; 2010 vm_page_t m; 2011 uint32_t pte_wbit; 2012 2013 m = NULL; 2014 vm_page_lock_queues(); 2015 PMAP_LOCK(pmap); 2016 2017 pte = pte_find(mmu, pmap, va); 2018 if ((pte != NULL) && PTE_ISVALID(pte)) { 2019 if (pmap == kernel_pmap) 2020 pte_wbit = PTE_SW; 2021 else 2022 pte_wbit = PTE_UW; 2023 2024 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2025 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2026 vm_page_hold(m); 2027 } 2028 } 2029 2030 vm_page_unlock_queues(); 2031 PMAP_UNLOCK(pmap); 2032 return (m); 2033 } 2034 2035 /* 2036 * Initialize a vm_page's machine-dependent fields. 2037 */ 2038 static void 2039 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2040 { 2041 2042 TAILQ_INIT(&m->md.pv_list); 2043 } 2044 2045 /* 2046 * mmu_booke_zero_page_area zeros the specified hardware page by 2047 * mapping it into virtual memory and using bzero to clear 2048 * its contents. 2049 * 2050 * off and size must reside within a single page. 2051 */ 2052 static void 2053 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2054 { 2055 vm_offset_t va; 2056 2057 /* XXX KASSERT off and size are within a single page? */ 2058 2059 mtx_lock(&zero_page_mutex); 2060 va = zero_page_va; 2061 2062 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2063 bzero((caddr_t)va + off, size); 2064 mmu_booke_kremove(mmu, va); 2065 2066 mtx_unlock(&zero_page_mutex); 2067 } 2068 2069 /* 2070 * mmu_booke_zero_page zeros the specified hardware page. 2071 */ 2072 static void 2073 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2074 { 2075 2076 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2077 } 2078 2079 /* 2080 * mmu_booke_copy_page copies the specified (machine independent) page by 2081 * mapping the page into virtual memory and using memcopy to copy the page, 2082 * one machine dependent page at a time. 2083 */ 2084 static void 2085 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2086 { 2087 vm_offset_t sva, dva; 2088 2089 sva = copy_page_src_va; 2090 dva = copy_page_dst_va; 2091 2092 mtx_lock(©_page_mutex); 2093 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2094 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2095 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2096 mmu_booke_kremove(mmu, dva); 2097 mmu_booke_kremove(mmu, sva); 2098 mtx_unlock(©_page_mutex); 2099 } 2100 2101 /* 2102 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2103 * into virtual memory and using bzero to clear its contents. This is intended 2104 * to be called from the vm_pagezero process only and outside of Giant. No 2105 * lock is required. 2106 */ 2107 static void 2108 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2109 { 2110 vm_offset_t va; 2111 2112 va = zero_page_idle_va; 2113 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2114 bzero((caddr_t)va, PAGE_SIZE); 2115 mmu_booke_kremove(mmu, va); 2116 } 2117 2118 /* 2119 * Return whether or not the specified physical page was modified 2120 * in any of physical maps. 2121 */ 2122 static boolean_t 2123 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2124 { 2125 pte_t *pte; 2126 pv_entry_t pv; 2127 2128 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2129 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2130 return (FALSE); 2131 2132 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2133 PMAP_LOCK(pv->pv_pmap); 2134 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2135 if (!PTE_ISVALID(pte)) 2136 goto make_sure_to_unlock; 2137 2138 if (PTE_ISMODIFIED(pte)) { 2139 PMAP_UNLOCK(pv->pv_pmap); 2140 return (TRUE); 2141 } 2142 } 2143 make_sure_to_unlock: 2144 PMAP_UNLOCK(pv->pv_pmap); 2145 } 2146 return (FALSE); 2147 } 2148 2149 /* 2150 * Return whether or not the specified virtual address is eligible 2151 * for prefault. 2152 */ 2153 static boolean_t 2154 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2155 { 2156 2157 return (FALSE); 2158 } 2159 2160 /* 2161 * Clear the modify bits on the specified physical page. 2162 */ 2163 static void 2164 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2165 { 2166 pte_t *pte; 2167 pv_entry_t pv; 2168 2169 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2170 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2171 return; 2172 2173 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2174 PMAP_LOCK(pv->pv_pmap); 2175 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2176 if (!PTE_ISVALID(pte)) 2177 goto make_sure_to_unlock; 2178 2179 mtx_lock_spin(&tlbivax_mutex); 2180 tlb_miss_lock(); 2181 2182 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2183 tlb0_flush_entry(pv->pv_va); 2184 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2185 PTE_REFERENCED); 2186 } 2187 2188 tlb_miss_unlock(); 2189 mtx_unlock_spin(&tlbivax_mutex); 2190 } 2191 make_sure_to_unlock: 2192 PMAP_UNLOCK(pv->pv_pmap); 2193 } 2194 } 2195 2196 /* 2197 * Return a count of reference bits for a page, clearing those bits. 2198 * It is not necessary for every reference bit to be cleared, but it 2199 * is necessary that 0 only be returned when there are truly no 2200 * reference bits set. 2201 * 2202 * XXX: The exact number of bits to check and clear is a matter that 2203 * should be tested and standardized at some point in the future for 2204 * optimal aging of shared pages. 2205 */ 2206 static int 2207 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2208 { 2209 pte_t *pte; 2210 pv_entry_t pv; 2211 int count; 2212 2213 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2214 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2215 return (0); 2216 2217 count = 0; 2218 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2219 PMAP_LOCK(pv->pv_pmap); 2220 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2221 if (!PTE_ISVALID(pte)) 2222 goto make_sure_to_unlock; 2223 2224 if (PTE_ISREFERENCED(pte)) { 2225 mtx_lock_spin(&tlbivax_mutex); 2226 tlb_miss_lock(); 2227 2228 tlb0_flush_entry(pv->pv_va); 2229 pte->flags &= ~PTE_REFERENCED; 2230 2231 tlb_miss_unlock(); 2232 mtx_unlock_spin(&tlbivax_mutex); 2233 2234 if (++count > 4) { 2235 PMAP_UNLOCK(pv->pv_pmap); 2236 break; 2237 } 2238 } 2239 } 2240 make_sure_to_unlock: 2241 PMAP_UNLOCK(pv->pv_pmap); 2242 } 2243 return (count); 2244 } 2245 2246 /* 2247 * Clear the reference bit on the specified physical page. 2248 */ 2249 static void 2250 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2251 { 2252 pte_t *pte; 2253 pv_entry_t pv; 2254 2255 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2256 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2257 return; 2258 2259 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2260 PMAP_LOCK(pv->pv_pmap); 2261 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2262 if (!PTE_ISVALID(pte)) 2263 goto make_sure_to_unlock; 2264 2265 if (PTE_ISREFERENCED(pte)) { 2266 mtx_lock_spin(&tlbivax_mutex); 2267 tlb_miss_lock(); 2268 2269 tlb0_flush_entry(pv->pv_va); 2270 pte->flags &= ~PTE_REFERENCED; 2271 2272 tlb_miss_unlock(); 2273 mtx_unlock_spin(&tlbivax_mutex); 2274 } 2275 } 2276 make_sure_to_unlock: 2277 PMAP_UNLOCK(pv->pv_pmap); 2278 } 2279 } 2280 2281 /* 2282 * Change wiring attribute for a map/virtual-address pair. 2283 */ 2284 static void 2285 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2286 { 2287 pte_t *pte;; 2288 2289 PMAP_LOCK(pmap); 2290 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2291 if (wired) { 2292 if (!PTE_ISWIRED(pte)) { 2293 pte->flags |= PTE_WIRED; 2294 pmap->pm_stats.wired_count++; 2295 } 2296 } else { 2297 if (PTE_ISWIRED(pte)) { 2298 pte->flags &= ~PTE_WIRED; 2299 pmap->pm_stats.wired_count--; 2300 } 2301 } 2302 } 2303 PMAP_UNLOCK(pmap); 2304 } 2305 2306 /* 2307 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2308 * page. This count may be changed upwards or downwards in the future; it is 2309 * only necessary that true be returned for a small subset of pmaps for proper 2310 * page aging. 2311 */ 2312 static boolean_t 2313 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2314 { 2315 pv_entry_t pv; 2316 int loops; 2317 2318 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2319 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2320 return (FALSE); 2321 2322 loops = 0; 2323 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2324 if (pv->pv_pmap == pmap) 2325 return (TRUE); 2326 2327 if (++loops >= 16) 2328 break; 2329 } 2330 return (FALSE); 2331 } 2332 2333 /* 2334 * Return the number of managed mappings to the given physical page that are 2335 * wired. 2336 */ 2337 static int 2338 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2339 { 2340 pv_entry_t pv; 2341 pte_t *pte; 2342 int count = 0; 2343 2344 if ((m->flags & PG_FICTITIOUS) != 0) 2345 return (count); 2346 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2347 2348 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2349 PMAP_LOCK(pv->pv_pmap); 2350 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2351 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2352 count++; 2353 PMAP_UNLOCK(pv->pv_pmap); 2354 } 2355 2356 return (count); 2357 } 2358 2359 static int 2360 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2361 { 2362 int i; 2363 vm_offset_t va; 2364 2365 /* 2366 * This currently does not work for entries that 2367 * overlap TLB1 entries. 2368 */ 2369 for (i = 0; i < tlb1_idx; i ++) { 2370 if (tlb1_iomapped(i, pa, size, &va) == 0) 2371 return (0); 2372 } 2373 2374 return (EFAULT); 2375 } 2376 2377 vm_offset_t 2378 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2379 vm_size_t *sz) 2380 { 2381 vm_paddr_t pa, ppa; 2382 vm_offset_t va; 2383 vm_size_t gran; 2384 2385 /* Raw physical memory dumps don't have a virtual address. */ 2386 if (md->md_vaddr == ~0UL) { 2387 /* We always map a 256MB page at 256M. */ 2388 gran = 256 * 1024 * 1024; 2389 pa = md->md_paddr + ofs; 2390 ppa = pa & ~(gran - 1); 2391 ofs = pa - ppa; 2392 va = gran; 2393 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2394 if (*sz > (gran - ofs)) 2395 *sz = gran - ofs; 2396 return (va + ofs); 2397 } 2398 2399 /* Minidumps are based on virtual memory addresses. */ 2400 va = md->md_vaddr + ofs; 2401 if (va >= kernstart + kernsize) { 2402 gran = PAGE_SIZE - (va & PAGE_MASK); 2403 if (*sz > gran) 2404 *sz = gran; 2405 } 2406 return (va); 2407 } 2408 2409 void 2410 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2411 vm_offset_t va) 2412 { 2413 2414 /* Raw physical memory dumps don't have a virtual address. */ 2415 if (md->md_vaddr == ~0UL) { 2416 tlb1_idx--; 2417 tlb1[tlb1_idx].mas1 = 0; 2418 tlb1[tlb1_idx].mas2 = 0; 2419 tlb1[tlb1_idx].mas3 = 0; 2420 tlb1_write_entry(tlb1_idx); 2421 return; 2422 } 2423 2424 /* Minidumps are based on virtual memory addresses. */ 2425 /* Nothing to do... */ 2426 } 2427 2428 struct pmap_md * 2429 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2430 { 2431 static struct pmap_md md; 2432 struct bi_mem_region *mr; 2433 pte_t *pte; 2434 vm_offset_t va; 2435 2436 if (dumpsys_minidump) { 2437 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2438 if (prev == NULL) { 2439 /* 1st: kernel .data and .bss. */ 2440 md.md_index = 1; 2441 md.md_vaddr = trunc_page((uintptr_t)_etext); 2442 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2443 return (&md); 2444 } 2445 switch (prev->md_index) { 2446 case 1: 2447 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2448 md.md_index = 2; 2449 md.md_vaddr = data_start; 2450 md.md_size = data_end - data_start; 2451 break; 2452 case 2: 2453 /* 3rd: kernel VM. */ 2454 va = prev->md_vaddr + prev->md_size; 2455 /* Find start of next chunk (from va). */ 2456 while (va < virtual_end) { 2457 /* Don't dump the buffer cache. */ 2458 if (va >= kmi.buffer_sva && 2459 va < kmi.buffer_eva) { 2460 va = kmi.buffer_eva; 2461 continue; 2462 } 2463 pte = pte_find(mmu, kernel_pmap, va); 2464 if (pte != NULL && PTE_ISVALID(pte)) 2465 break; 2466 va += PAGE_SIZE; 2467 } 2468 if (va < virtual_end) { 2469 md.md_vaddr = va; 2470 va += PAGE_SIZE; 2471 /* Find last page in chunk. */ 2472 while (va < virtual_end) { 2473 /* Don't run into the buffer cache. */ 2474 if (va == kmi.buffer_sva) 2475 break; 2476 pte = pte_find(mmu, kernel_pmap, va); 2477 if (pte == NULL || !PTE_ISVALID(pte)) 2478 break; 2479 va += PAGE_SIZE; 2480 } 2481 md.md_size = va - md.md_vaddr; 2482 break; 2483 } 2484 md.md_index = 3; 2485 /* FALLTHROUGH */ 2486 default: 2487 return (NULL); 2488 } 2489 } else { /* minidumps */ 2490 mr = bootinfo_mr(); 2491 if (prev == NULL) { 2492 /* first physical chunk. */ 2493 md.md_paddr = mr->mem_base; 2494 md.md_size = mr->mem_size; 2495 md.md_vaddr = ~0UL; 2496 md.md_index = 1; 2497 } else if (md.md_index < bootinfo->bi_mem_reg_no) { 2498 md.md_paddr = mr[md.md_index].mem_base; 2499 md.md_size = mr[md.md_index].mem_size; 2500 md.md_vaddr = ~0UL; 2501 md.md_index++; 2502 } else { 2503 /* There's no next physical chunk. */ 2504 return (NULL); 2505 } 2506 } 2507 2508 return (&md); 2509 } 2510 2511 /* 2512 * Map a set of physical memory pages into the kernel virtual address space. 2513 * Return a pointer to where it is mapped. This routine is intended to be used 2514 * for mapping device memory, NOT real memory. 2515 */ 2516 static void * 2517 mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2518 { 2519 void *res; 2520 uintptr_t va; 2521 vm_size_t sz; 2522 2523 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2524 res = (void *)va; 2525 2526 do { 2527 sz = 1 << (ilog2(size) & ~1); 2528 if (bootverbose) 2529 printf("Wiring VA=%x to PA=%x (size=%x), " 2530 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2531 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2532 size -= sz; 2533 pa += sz; 2534 va += sz; 2535 } while (size > 0); 2536 2537 return (res); 2538 } 2539 2540 /* 2541 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2542 */ 2543 static void 2544 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2545 { 2546 vm_offset_t base, offset; 2547 2548 /* 2549 * Unmap only if this is inside kernel virtual space. 2550 */ 2551 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2552 base = trunc_page(va); 2553 offset = va & PAGE_MASK; 2554 size = roundup(offset + size, PAGE_SIZE); 2555 kmem_free(kernel_map, base, size); 2556 } 2557 } 2558 2559 /* 2560 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2561 * specified pmap. This eliminates the blast of soft faults on process startup 2562 * and immediately after an mmap. 2563 */ 2564 static void 2565 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2566 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2567 { 2568 2569 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2570 KASSERT(object->type == OBJT_DEVICE, 2571 ("mmu_booke_object_init_pt: non-device object")); 2572 } 2573 2574 /* 2575 * Perform the pmap work for mincore. 2576 */ 2577 static int 2578 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2579 { 2580 2581 TODO; 2582 return (0); 2583 } 2584 2585 /**************************************************************************/ 2586 /* TID handling */ 2587 /**************************************************************************/ 2588 2589 /* 2590 * Allocate a TID. If necessary, steal one from someone else. 2591 * The new TID is flushed from the TLB before returning. 2592 */ 2593 static tlbtid_t 2594 tid_alloc(pmap_t pmap) 2595 { 2596 tlbtid_t tid; 2597 int thiscpu; 2598 2599 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2600 2601 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2602 2603 thiscpu = PCPU_GET(cpuid); 2604 2605 tid = PCPU_GET(tid_next); 2606 if (tid > TID_MAX) 2607 tid = TID_MIN; 2608 PCPU_SET(tid_next, tid + 1); 2609 2610 /* If we are stealing TID then clear the relevant pmap's field */ 2611 if (tidbusy[thiscpu][tid] != NULL) { 2612 2613 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2614 2615 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2616 2617 /* Flush all entries from TLB0 matching this TID. */ 2618 tid_flush(tid); 2619 } 2620 2621 tidbusy[thiscpu][tid] = pmap; 2622 pmap->pm_tid[thiscpu] = tid; 2623 __asm __volatile("msync; isync"); 2624 2625 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2626 PCPU_GET(tid_next)); 2627 2628 return (tid); 2629 } 2630 2631 /**************************************************************************/ 2632 /* TLB0 handling */ 2633 /**************************************************************************/ 2634 2635 static void 2636 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2637 uint32_t mas7) 2638 { 2639 int as; 2640 char desc[3]; 2641 tlbtid_t tid; 2642 vm_size_t size; 2643 unsigned int tsize; 2644 2645 desc[2] = '\0'; 2646 if (mas1 & MAS1_VALID) 2647 desc[0] = 'V'; 2648 else 2649 desc[0] = ' '; 2650 2651 if (mas1 & MAS1_IPROT) 2652 desc[1] = 'P'; 2653 else 2654 desc[1] = ' '; 2655 2656 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2657 tid = MAS1_GETTID(mas1); 2658 2659 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2660 size = 0; 2661 if (tsize) 2662 size = tsize2size(tsize); 2663 2664 debugf("%3d: (%s) [AS=%d] " 2665 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2666 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2667 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2668 } 2669 2670 /* Convert TLB0 va and way number to tlb0[] table index. */ 2671 static inline unsigned int 2672 tlb0_tableidx(vm_offset_t va, unsigned int way) 2673 { 2674 unsigned int idx; 2675 2676 idx = (way * TLB0_ENTRIES_PER_WAY); 2677 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2678 return (idx); 2679 } 2680 2681 /* 2682 * Invalidate TLB0 entry. 2683 */ 2684 static inline void 2685 tlb0_flush_entry(vm_offset_t va) 2686 { 2687 2688 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2689 2690 mtx_assert(&tlbivax_mutex, MA_OWNED); 2691 2692 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2693 __asm __volatile("isync; msync"); 2694 __asm __volatile("tlbsync; msync"); 2695 2696 CTR1(KTR_PMAP, "%s: e", __func__); 2697 } 2698 2699 /* Print out contents of the MAS registers for each TLB0 entry */ 2700 void 2701 tlb0_print_tlbentries(void) 2702 { 2703 uint32_t mas0, mas1, mas2, mas3, mas7; 2704 int entryidx, way, idx; 2705 2706 debugf("TLB0 entries:\n"); 2707 for (way = 0; way < TLB0_WAYS; way ++) 2708 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2709 2710 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2711 mtspr(SPR_MAS0, mas0); 2712 __asm __volatile("isync"); 2713 2714 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2715 mtspr(SPR_MAS2, mas2); 2716 2717 __asm __volatile("isync; tlbre"); 2718 2719 mas1 = mfspr(SPR_MAS1); 2720 mas2 = mfspr(SPR_MAS2); 2721 mas3 = mfspr(SPR_MAS3); 2722 mas7 = mfspr(SPR_MAS7); 2723 2724 idx = tlb0_tableidx(mas2, way); 2725 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2726 } 2727 } 2728 2729 /**************************************************************************/ 2730 /* TLB1 handling */ 2731 /**************************************************************************/ 2732 2733 /* 2734 * TLB1 mapping notes: 2735 * 2736 * TLB1[0] CCSRBAR 2737 * TLB1[1] Kernel text and data. 2738 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2739 * windows, other devices mappings. 2740 */ 2741 2742 /* 2743 * Write given entry to TLB1 hardware. 2744 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2745 */ 2746 static void 2747 tlb1_write_entry(unsigned int idx) 2748 { 2749 uint32_t mas0, mas7; 2750 2751 //debugf("tlb1_write_entry: s\n"); 2752 2753 /* Clear high order RPN bits */ 2754 mas7 = 0; 2755 2756 /* Select entry */ 2757 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2758 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2759 2760 mtspr(SPR_MAS0, mas0); 2761 __asm __volatile("isync"); 2762 mtspr(SPR_MAS1, tlb1[idx].mas1); 2763 __asm __volatile("isync"); 2764 mtspr(SPR_MAS2, tlb1[idx].mas2); 2765 __asm __volatile("isync"); 2766 mtspr(SPR_MAS3, tlb1[idx].mas3); 2767 __asm __volatile("isync"); 2768 mtspr(SPR_MAS7, mas7); 2769 __asm __volatile("isync; tlbwe; isync; msync"); 2770 2771 //debugf("tlb1_write_entry: e\n");; 2772 } 2773 2774 /* 2775 * Return the largest uint value log such that 2^log <= num. 2776 */ 2777 static unsigned int 2778 ilog2(unsigned int num) 2779 { 2780 int lz; 2781 2782 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2783 return (31 - lz); 2784 } 2785 2786 /* 2787 * Convert TLB TSIZE value to mapped region size. 2788 */ 2789 static vm_size_t 2790 tsize2size(unsigned int tsize) 2791 { 2792 2793 /* 2794 * size = 4^tsize KB 2795 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2796 */ 2797 2798 return ((1 << (2 * tsize)) * 1024); 2799 } 2800 2801 /* 2802 * Convert region size (must be power of 4) to TLB TSIZE value. 2803 */ 2804 static unsigned int 2805 size2tsize(vm_size_t size) 2806 { 2807 2808 return (ilog2(size) / 2 - 5); 2809 } 2810 2811 /* 2812 * Register permanent kernel mapping in TLB1. 2813 * 2814 * Entries are created starting from index 0 (current free entry is 2815 * kept in tlb1_idx) and are not supposed to be invalidated. 2816 */ 2817 static int 2818 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2819 uint32_t flags) 2820 { 2821 uint32_t ts, tid; 2822 int tsize; 2823 2824 if (tlb1_idx >= TLB1_ENTRIES) { 2825 printf("tlb1_set_entry: TLB1 full!\n"); 2826 return (-1); 2827 } 2828 2829 /* Convert size to TSIZE */ 2830 tsize = size2tsize(size); 2831 2832 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2833 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2834 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2835 2836 /* XXX LOCK tlb1[] */ 2837 2838 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2839 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2840 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2841 2842 /* Set supervisor RWX permission bits */ 2843 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2844 2845 tlb1_write_entry(tlb1_idx++); 2846 2847 /* XXX UNLOCK tlb1[] */ 2848 2849 /* 2850 * XXX in general TLB1 updates should be propagated between CPUs, 2851 * since current design assumes to have the same TLB1 set-up on all 2852 * cores. 2853 */ 2854 return (0); 2855 } 2856 2857 static int 2858 tlb1_entry_size_cmp(const void *a, const void *b) 2859 { 2860 const vm_size_t *sza; 2861 const vm_size_t *szb; 2862 2863 sza = a; 2864 szb = b; 2865 if (*sza > *szb) 2866 return (-1); 2867 else if (*sza < *szb) 2868 return (1); 2869 else 2870 return (0); 2871 } 2872 2873 /* 2874 * Map in contiguous RAM region into the TLB1 using maximum of 2875 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2876 * 2877 * If necessary round up last entry size and return total size 2878 * used by all allocated entries. 2879 */ 2880 vm_size_t 2881 tlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2882 { 2883 vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2884 vm_size_t mapped_size, sz, esz; 2885 unsigned int log; 2886 int i; 2887 2888 CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2889 __func__, size, va, pa); 2890 2891 mapped_size = 0; 2892 sz = size; 2893 memset(entry_size, 0, sizeof(entry_size)); 2894 2895 /* Calculate entry sizes. */ 2896 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2897 2898 /* Largest region that is power of 4 and fits within size */ 2899 log = ilog2(sz) / 2; 2900 esz = 1 << (2 * log); 2901 2902 /* If this is last entry cover remaining size. */ 2903 if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2904 while (esz < sz) 2905 esz = esz << 2; 2906 } 2907 2908 entry_size[i] = esz; 2909 mapped_size += esz; 2910 if (esz < sz) 2911 sz -= esz; 2912 else 2913 sz = 0; 2914 } 2915 2916 /* Sort entry sizes, required to get proper entry address alignment. */ 2917 qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2918 sizeof(vm_size_t), tlb1_entry_size_cmp); 2919 2920 /* Load TLB1 entries. */ 2921 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2922 esz = entry_size[i]; 2923 if (!esz) 2924 break; 2925 2926 CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 2927 "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 2928 2929 tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2930 2931 va += esz; 2932 pa += esz; 2933 } 2934 2935 CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 2936 __func__, mapped_size, mapped_size - size); 2937 2938 return (mapped_size); 2939 } 2940 2941 /* 2942 * TLB1 initialization routine, to be called after the very first 2943 * assembler level setup done in locore.S. 2944 */ 2945 void 2946 tlb1_init(vm_offset_t ccsrbar) 2947 { 2948 uint32_t mas0; 2949 2950 /* TLB1[1] is used to map the kernel. Save that entry. */ 2951 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 2952 mtspr(SPR_MAS0, mas0); 2953 __asm __volatile("isync; tlbre"); 2954 2955 tlb1[1].mas1 = mfspr(SPR_MAS1); 2956 tlb1[1].mas2 = mfspr(SPR_MAS2); 2957 tlb1[1].mas3 = mfspr(SPR_MAS3); 2958 2959 /* Map in CCSRBAR in TLB1[0] */ 2960 tlb1_idx = 0; 2961 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 2962 /* 2963 * Set the next available TLB1 entry index. Note TLB[1] is reserved 2964 * for initial mapping of kernel text+data, which was set early in 2965 * locore, we need to skip this [busy] entry. 2966 */ 2967 tlb1_idx = 2; 2968 2969 /* Setup TLB miss defaults */ 2970 set_mas4_defaults(); 2971 } 2972 2973 /* 2974 * Setup MAS4 defaults. 2975 * These values are loaded to MAS0-2 on a TLB miss. 2976 */ 2977 static void 2978 set_mas4_defaults(void) 2979 { 2980 uint32_t mas4; 2981 2982 /* Defaults: TLB0, PID0, TSIZED=4K */ 2983 mas4 = MAS4_TLBSELD0; 2984 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 2985 #ifdef SMP 2986 mas4 |= MAS4_MD; 2987 #endif 2988 mtspr(SPR_MAS4, mas4); 2989 __asm __volatile("isync"); 2990 } 2991 2992 /* 2993 * Print out contents of the MAS registers for each TLB1 entry 2994 */ 2995 void 2996 tlb1_print_tlbentries(void) 2997 { 2998 uint32_t mas0, mas1, mas2, mas3, mas7; 2999 int i; 3000 3001 debugf("TLB1 entries:\n"); 3002 for (i = 0; i < TLB1_ENTRIES; i++) { 3003 3004 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3005 mtspr(SPR_MAS0, mas0); 3006 3007 __asm __volatile("isync; tlbre"); 3008 3009 mas1 = mfspr(SPR_MAS1); 3010 mas2 = mfspr(SPR_MAS2); 3011 mas3 = mfspr(SPR_MAS3); 3012 mas7 = mfspr(SPR_MAS7); 3013 3014 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3015 } 3016 } 3017 3018 /* 3019 * Print out contents of the in-ram tlb1 table. 3020 */ 3021 void 3022 tlb1_print_entries(void) 3023 { 3024 int i; 3025 3026 debugf("tlb1[] table entries:\n"); 3027 for (i = 0; i < TLB1_ENTRIES; i++) 3028 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3029 } 3030 3031 /* 3032 * Return 0 if the physical IO range is encompassed by one of the 3033 * the TLB1 entries, otherwise return related error code. 3034 */ 3035 static int 3036 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3037 { 3038 uint32_t prot; 3039 vm_paddr_t pa_start; 3040 vm_paddr_t pa_end; 3041 unsigned int entry_tsize; 3042 vm_size_t entry_size; 3043 3044 *va = (vm_offset_t)NULL; 3045 3046 /* Skip invalid entries */ 3047 if (!(tlb1[i].mas1 & MAS1_VALID)) 3048 return (EINVAL); 3049 3050 /* 3051 * The entry must be cache-inhibited, guarded, and r/w 3052 * so it can function as an i/o page 3053 */ 3054 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3055 if (prot != (MAS2_I | MAS2_G)) 3056 return (EPERM); 3057 3058 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3059 if (prot != (MAS3_SR | MAS3_SW)) 3060 return (EPERM); 3061 3062 /* The address should be within the entry range. */ 3063 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3064 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3065 3066 entry_size = tsize2size(entry_tsize); 3067 pa_start = tlb1[i].mas3 & MAS3_RPN; 3068 pa_end = pa_start + entry_size - 1; 3069 3070 if ((pa < pa_start) || ((pa + size) > pa_end)) 3071 return (ERANGE); 3072 3073 /* Return virtual address of this mapping. */ 3074 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3075 return (0); 3076 } 3077