1 /*- 2 * Copyright (c) 2008-2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/platform.h> 42 #include <machine/platformvar.h> 43 #include <machine/smp.h> 44 #include <machine/spr.h> 45 #include <machine/vmparam.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/openfirm.h> 51 52 #include <powerpc/mpc85xx/mpc85xx.h> 53 54 #include "platform_if.h" 55 56 #ifdef SMP 57 extern void *ap_pcpu; 58 extern vm_paddr_t kernload; /* Kernel physical load address */ 59 extern uint8_t __boot_page[]; /* Boot page body */ 60 extern uint32_t bp_ntlb1s; 61 extern uint32_t bp_tlb1[]; 62 extern uint32_t bp_tlb1_end[]; 63 #endif 64 65 extern uint32_t *bootinfo; 66 67 static int cpu, maxcpu; 68 69 static int bare_probe(platform_t); 70 static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 71 struct mem_region **avail, int *availsz); 72 static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 73 static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 74 static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 75 static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 76 static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 77 78 static void booke_reset(platform_t); 79 80 static platform_method_t bare_methods[] = { 81 PLATFORMMETHOD(platform_probe, bare_probe), 82 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 83 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 84 85 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 86 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 87 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 88 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 89 90 PLATFORMMETHOD(platform_reset, booke_reset), 91 92 { 0, 0 } 93 }; 94 95 static platform_def_t bare_platform = { 96 "bare metal", 97 bare_methods, 98 0 99 }; 100 101 PLATFORM_DEF(bare_platform); 102 103 static int 104 bare_probe(platform_t plat) 105 { 106 phandle_t cpus, child; 107 uint32_t sr; 108 int i, law_max, tgt; 109 110 if ((cpus = OF_finddevice("/cpus")) != 0) { 111 for (maxcpu = 0, child = OF_child(cpus); child != 0; 112 child = OF_peer(child), maxcpu++) 113 ; 114 } else 115 maxcpu = 1; 116 117 /* 118 * Clear local access windows. Skip DRAM entries, so we don't shoot 119 * ourselves in the foot. 120 */ 121 law_max = law_getmax(); 122 for (i = 0; i < law_max; i++) { 123 sr = ccsr_read4(OCP85XX_LAWSR(i)); 124 if ((sr & 0x80000000) == 0) 125 continue; 126 tgt = (sr & 0x01f00000) >> 20; 127 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 128 tgt == OCP85XX_TGTIF_RAM_INTL) 129 continue; 130 131 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 132 } 133 134 return (BUS_PROBE_GENERIC); 135 } 136 137 #define MEM_REGIONS 8 138 static struct mem_region avail_regions[MEM_REGIONS]; 139 140 void 141 bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 142 struct mem_region **avail, int *availsz) 143 { 144 uint32_t memsize; 145 int i, rv; 146 147 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 148 if (rv != 0) 149 panic("%s: could not retrieve mem regions from the 'memory' " 150 "node, error: %d", __func__, rv); 151 152 for (i = 0; i < *availsz; i++) { 153 if (avail_regions[i].mr_start < 1048576) { 154 avail_regions[i].mr_size = 155 avail_regions[i].mr_size - 156 (1048576 - avail_regions[i].mr_start); 157 avail_regions[i].mr_start = 1048576; 158 } 159 } 160 *avail = avail_regions; 161 162 /* On the bare metal platform phys == avail memory */ 163 *physsz = *availsz; 164 *phys = *avail; 165 } 166 167 static u_long 168 bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 169 { 170 u_long ticks; 171 phandle_t cpus, child; 172 pcell_t freq; 173 174 if (bootinfo != NULL) { 175 if (bootinfo[0] == 1) { 176 /* Backward compatibility. See 8-STABLE. */ 177 ticks = bootinfo[3] >> 3; 178 } else { 179 /* Compatibility with Juniper's loader. */ 180 ticks = bootinfo[5] >> 3; 181 } 182 } else 183 ticks = 0; 184 185 if ((cpus = OF_finddevice("/cpus")) == -1) 186 goto out; 187 188 if ((child = OF_child(cpus)) == 0) 189 goto out; 190 191 freq = 0; 192 if (OF_getprop(child, "bus-frequency", (void *)&freq, 193 sizeof(freq)) <= 0) 194 goto out; 195 196 /* 197 * Time Base and Decrementer are updated every 8 CCB bus clocks. 198 * HID0[SEL_TBCLK] = 0 199 */ 200 if (freq != 0) 201 ticks = freq / 8; 202 203 out: 204 if (ticks <= 0) 205 panic("Unable to determine timebase frequency!"); 206 207 return (ticks); 208 } 209 210 static int 211 bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 212 { 213 214 cpu = 0; 215 cpuref->cr_cpuid = cpu; 216 cpuref->cr_hwref = cpuref->cr_cpuid; 217 if (bootverbose) 218 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 219 cpu++; 220 221 return (0); 222 } 223 224 static int 225 bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 226 { 227 228 if (cpu >= maxcpu) 229 return (ENOENT); 230 231 cpuref->cr_cpuid = cpu++; 232 cpuref->cr_hwref = cpuref->cr_cpuid; 233 if (bootverbose) 234 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 235 236 return (0); 237 } 238 239 static int 240 bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 241 { 242 243 cpuref->cr_cpuid = mfspr(SPR_PIR); 244 cpuref->cr_hwref = cpuref->cr_cpuid; 245 246 return (0); 247 } 248 249 static int 250 bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 251 { 252 #ifdef SMP 253 uint32_t *tlb1; 254 uint32_t bptr, eebpcr; 255 int i, timeout; 256 257 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 258 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) { 259 printf("SMP: CPU %d already out of hold-off state!\n", 260 pc->pc_cpuid); 261 return (ENXIO); 262 } 263 264 ap_pcpu = pc; 265 266 i = 0; 267 tlb1 = bp_tlb1; 268 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) { 269 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i)); 270 __asm __volatile("isync; tlbre"); 271 tlb1[0] = mfspr(SPR_MAS1); 272 tlb1[1] = mfspr(SPR_MAS2); 273 tlb1[2] = mfspr(SPR_MAS3); 274 i++; 275 tlb1 += 3; 276 } 277 if (i < bp_ntlb1s) 278 bp_ntlb1s = i; 279 280 /* 281 * Set BPTR to the physical address of the boot page 282 */ 283 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 284 KASSERT((bptr & 0xfff) == 0, 285 ("%s: boot page is not aligned (%#x)", __func__, bptr)); 286 bptr = (bptr >> 12) | 0x80000000u; 287 ccsr_write4(OCP85XX_BPTR, bptr); 288 __asm __volatile("isync; msync"); 289 290 /* Flush caches to have our changes hit DRAM. */ 291 cpu_flush_dcache(__boot_page, 4096); 292 293 /* 294 * Release AP from hold-off state 295 */ 296 eebpcr |= (1 << (pc->pc_cpuid + 24)); 297 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 298 __asm __volatile("isync; msync"); 299 300 timeout = 500; 301 while (!pc->pc_awake && timeout--) 302 DELAY(1000); /* wait 1ms */ 303 304 /* 305 * Disable boot page translation so that the 4K page at the default 306 * address (= 0xfffff000) isn't permanently remapped and thus not 307 * usable otherwise. 308 */ 309 ccsr_write4(OCP85XX_BPTR, 0); 310 __asm __volatile("isync; msync"); 311 312 if (!pc->pc_awake) 313 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid); 314 return ((pc->pc_awake) ? 0 : EBUSY); 315 #else 316 /* No SMP support */ 317 return (ENXIO); 318 #endif 319 } 320 321 static void 322 booke_reset(platform_t plat) 323 { 324 325 /* 326 * Try the dedicated reset register first. 327 * If the SoC doesn't have one, we'll fall 328 * back to using the debug control register. 329 */ 330 ccsr_write4(OCP85XX_RSTCR, 2); 331 332 /* Clear DBCR0, disables debug interrupts and events. */ 333 mtspr(SPR_DBCR0, 0); 334 __asm __volatile("isync"); 335 336 /* Enable Debug Interrupts in MSR. */ 337 mtmsr(mfmsr() | PSL_DE); 338 339 /* Enable debug interrupts and issue reset. */ 340 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 341 342 printf("Reset failed...\n"); 343 while (1) 344 ; 345 } 346 347