1 /*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/platform.h> 42 #include <machine/platformvar.h> 43 #include <machine/smp.h> 44 #include <machine/spr.h> 45 #include <machine/vmparam.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/openfirm.h> 51 52 #include <powerpc/mpc85xx/mpc85xx.h> 53 54 #include "platform_if.h" 55 56 #ifdef SMP 57 extern void *ap_pcpu; 58 extern uint8_t __boot_page[]; /* Boot page body */ 59 extern uint32_t kernload; /* Kernel physical load address */ 60 #endif 61 62 static int cpu, maxcpu; 63 64 static int bare_probe(platform_t); 65 static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 66 struct mem_region **avail, int *availsz); 67 static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 68 static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 69 static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 70 static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 71 static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 72 73 static void e500_reset(platform_t); 74 75 static platform_method_t bare_methods[] = { 76 PLATFORMMETHOD(platform_probe, bare_probe), 77 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 78 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 79 80 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 81 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 82 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 83 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 84 85 PLATFORMMETHOD(platform_reset, e500_reset), 86 87 { 0, 0 } 88 }; 89 90 static platform_def_t bare_platform = { 91 "bare metal", 92 bare_methods, 93 0 94 }; 95 96 PLATFORM_DEF(bare_platform); 97 98 static int 99 bare_probe(platform_t plat) 100 { 101 uint32_t ver, sr; 102 int i, law_max, tgt; 103 104 ver = SVR_VER(mfspr(SPR_SVR)); 105 if (ver == SVR_MPC8572E || ver == SVR_MPC8572) 106 maxcpu = 2; 107 else 108 maxcpu = 1; 109 110 /* 111 * Clear local access windows. Skip DRAM entries, so we don't shoot 112 * ourselves in the foot. 113 */ 114 law_max = law_getmax(); 115 for (i = 0; i < law_max; i++) { 116 sr = ccsr_read4(OCP85XX_LAWSR(i)); 117 if ((sr & 0x80000000) == 0) 118 continue; 119 tgt = (sr & 0x01f00000) >> 20; 120 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 121 tgt == OCP85XX_TGTIF_RAM_INTL) 122 continue; 123 124 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 125 } 126 127 return (BUS_PROBE_GENERIC); 128 } 129 130 #define MEM_REGIONS 8 131 static struct mem_region avail_regions[MEM_REGIONS]; 132 133 void 134 bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 135 struct mem_region **avail, int *availsz) 136 { 137 uint32_t memsize; 138 int i, rv; 139 140 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 141 142 if (rv != 0) 143 return; 144 145 for (i = 0; i < *availsz; i++) { 146 if (avail_regions[i].mr_start < 1048576) { 147 avail_regions[i].mr_size = 148 avail_regions[i].mr_size - 149 (1048576 - avail_regions[i].mr_start); 150 avail_regions[i].mr_start = 1048576; 151 } 152 } 153 *avail = avail_regions; 154 155 /* On the bare metal platform phys == avail memory */ 156 *physsz = *availsz; 157 *phys = *avail; 158 } 159 160 static u_long 161 bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 162 { 163 u_long ticks = -1; 164 phandle_t cpus, child; 165 pcell_t freq; 166 167 if ((cpus = OF_finddevice("/cpus")) == 0) 168 goto out; 169 170 if ((child = OF_child(cpus)) == 0) 171 goto out; 172 173 if (OF_getprop(child, "bus-frequency", (void *)&freq, 174 sizeof(freq)) <= 0) 175 goto out; 176 /* 177 * Time Base and Decrementer are updated every 8 CCB bus clocks. 178 * HID0[SEL_TBCLK] = 0 179 */ 180 ticks = freq / 8; 181 out: 182 if (ticks <= 0) 183 panic("Unable to determine timebase frequency!"); 184 185 return (ticks); 186 } 187 188 static int 189 bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 190 { 191 192 cpu = 0; 193 cpuref->cr_cpuid = cpu; 194 cpuref->cr_hwref = cpuref->cr_cpuid; 195 if (bootverbose) 196 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 197 cpu++; 198 199 return (0); 200 } 201 202 static int 203 bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 204 { 205 206 if (cpu >= maxcpu) 207 return (ENOENT); 208 209 cpuref->cr_cpuid = cpu++; 210 cpuref->cr_hwref = cpuref->cr_cpuid; 211 if (bootverbose) 212 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 213 214 return (0); 215 } 216 217 static int 218 bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 219 { 220 221 cpuref->cr_cpuid = mfspr(SPR_PIR); 222 cpuref->cr_hwref = cpuref->cr_cpuid; 223 224 return (0); 225 } 226 227 static int 228 bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 229 { 230 #ifdef SMP 231 uint32_t bptr, eebpcr; 232 int timeout; 233 234 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 235 if ((eebpcr & (pc->pc_cpumask << 24)) != 0) { 236 printf("%s: CPU=%d already out of hold-off state!\n", 237 __func__, pc->pc_cpuid); 238 return (ENXIO); 239 } 240 241 ap_pcpu = pc; 242 __asm __volatile("msync; isync"); 243 244 /* 245 * Set BPTR to the physical address of the boot page 246 */ 247 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 248 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 249 250 /* 251 * Release AP from hold-off state 252 */ 253 eebpcr |= (pc->pc_cpumask << 24); 254 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 255 __asm __volatile("isync; msync"); 256 257 timeout = 500; 258 while (!pc->pc_awake && timeout--) 259 DELAY(1000); /* wait 1ms */ 260 261 return ((pc->pc_awake) ? 0 : EBUSY); 262 #else 263 /* No SMP support */ 264 return (ENXIO); 265 #endif 266 } 267 268 static void 269 e500_reset(platform_t plat) 270 { 271 uint32_t ver = SVR_VER(mfspr(SPR_SVR)); 272 273 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 || 274 ver == SVR_MPC8548E || ver == SVR_MPC8548) 275 /* Systems with dedicated reset register */ 276 ccsr_write4(OCP85XX_RSTCR, 2); 277 else { 278 /* Clear DBCR0, disables debug interrupts and events. */ 279 mtspr(SPR_DBCR0, 0); 280 __asm __volatile("isync"); 281 282 /* Enable Debug Interrupts in MSR. */ 283 mtmsr(mfmsr() | PSL_DE); 284 285 /* Enable debug interrupts and issue reset. */ 286 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | 287 DBCR0_RST_SYSTEM); 288 } 289 290 printf("Reset failed...\n"); 291 while (1); 292 } 293 294