1 /*- 2 * Copyright (c) 2008-2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/platform.h> 42 #include <machine/platformvar.h> 43 #include <machine/smp.h> 44 #include <machine/spr.h> 45 #include <machine/vmparam.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/openfirm.h> 51 52 #include <powerpc/mpc85xx/mpc85xx.h> 53 54 #include "platform_if.h" 55 56 #ifdef SMP 57 extern void *ap_pcpu; 58 extern uint8_t __boot_page[]; /* Boot page body */ 59 extern uint32_t bp_kernload; /* Kernel physical load address */ 60 extern uint32_t bp_trace; /* AP boot trace field */ 61 #endif 62 63 extern uint32_t *bootinfo; 64 65 static int cpu, maxcpu; 66 67 static int bare_probe(platform_t); 68 static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 69 struct mem_region **avail, int *availsz); 70 static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 71 static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 72 static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 73 static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 74 static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 75 76 static void booke_reset(platform_t); 77 78 static platform_method_t bare_methods[] = { 79 PLATFORMMETHOD(platform_probe, bare_probe), 80 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 81 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 82 83 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 84 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 85 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 86 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 87 88 PLATFORMMETHOD(platform_reset, booke_reset), 89 90 { 0, 0 } 91 }; 92 93 static platform_def_t bare_platform = { 94 "bare metal", 95 bare_methods, 96 0 97 }; 98 99 PLATFORM_DEF(bare_platform); 100 101 static int 102 bare_probe(platform_t plat) 103 { 104 phandle_t cpus, child; 105 uint32_t sr; 106 int i, law_max, tgt; 107 108 if ((cpus = OF_finddevice("/cpus")) != 0) { 109 for (maxcpu = 0, child = OF_child(cpus); child != 0; 110 child = OF_peer(child), maxcpu++) 111 ; 112 } else 113 maxcpu = 1; 114 115 /* 116 * Clear local access windows. Skip DRAM entries, so we don't shoot 117 * ourselves in the foot. 118 */ 119 law_max = law_getmax(); 120 for (i = 0; i < law_max; i++) { 121 sr = ccsr_read4(OCP85XX_LAWSR(i)); 122 if ((sr & 0x80000000) == 0) 123 continue; 124 tgt = (sr & 0x01f00000) >> 20; 125 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 126 tgt == OCP85XX_TGTIF_RAM_INTL) 127 continue; 128 129 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 130 } 131 132 return (BUS_PROBE_GENERIC); 133 } 134 135 #define MEM_REGIONS 8 136 static struct mem_region avail_regions[MEM_REGIONS]; 137 138 void 139 bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 140 struct mem_region **avail, int *availsz) 141 { 142 uint32_t memsize; 143 int i, rv; 144 145 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 146 if (rv != 0) 147 panic("%s: could not retrieve mem regions from the 'memory' " 148 "node, error: %d", __func__, rv); 149 150 for (i = 0; i < *availsz; i++) { 151 if (avail_regions[i].mr_start < 1048576) { 152 avail_regions[i].mr_size = 153 avail_regions[i].mr_size - 154 (1048576 - avail_regions[i].mr_start); 155 avail_regions[i].mr_start = 1048576; 156 } 157 } 158 *avail = avail_regions; 159 160 /* On the bare metal platform phys == avail memory */ 161 *physsz = *availsz; 162 *phys = *avail; 163 } 164 165 static u_long 166 bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 167 { 168 u_long ticks; 169 phandle_t cpus, child; 170 pcell_t freq; 171 172 if (bootinfo != NULL) { 173 if (bootinfo[0] == 1) { 174 /* Backward compatibility. See 8-STABLE. */ 175 ticks = bootinfo[3] >> 3; 176 } else { 177 /* Compatibility with Juniper's loader. */ 178 ticks = bootinfo[5] >> 3; 179 } 180 } else 181 ticks = 0; 182 183 if ((cpus = OF_finddevice("/cpus")) == -1) 184 goto out; 185 186 if ((child = OF_child(cpus)) == 0) 187 goto out; 188 189 freq = 0; 190 if (OF_getprop(child, "bus-frequency", (void *)&freq, 191 sizeof(freq)) <= 0) 192 goto out; 193 194 /* 195 * Time Base and Decrementer are updated every 8 CCB bus clocks. 196 * HID0[SEL_TBCLK] = 0 197 */ 198 if (freq != 0) 199 ticks = freq / 8; 200 201 out: 202 if (ticks <= 0) 203 panic("Unable to determine timebase frequency!"); 204 205 return (ticks); 206 } 207 208 static int 209 bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 210 { 211 212 cpu = 0; 213 cpuref->cr_cpuid = cpu; 214 cpuref->cr_hwref = cpuref->cr_cpuid; 215 if (bootverbose) 216 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 217 cpu++; 218 219 return (0); 220 } 221 222 static int 223 bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 224 { 225 226 if (cpu >= maxcpu) 227 return (ENOENT); 228 229 cpuref->cr_cpuid = cpu++; 230 cpuref->cr_hwref = cpuref->cr_cpuid; 231 if (bootverbose) 232 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 233 234 return (0); 235 } 236 237 static int 238 bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 239 { 240 241 cpuref->cr_cpuid = mfspr(SPR_PIR); 242 cpuref->cr_hwref = cpuref->cr_cpuid; 243 244 return (0); 245 } 246 247 static int 248 bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 249 { 250 #ifdef SMP 251 uint32_t bptr, eebpcr; 252 int timeout; 253 254 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 255 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) { 256 printf("SMP: CPU %d already out of hold-off state!\n", 257 pc->pc_cpuid); 258 return (ENXIO); 259 } 260 261 ap_pcpu = pc; 262 __asm __volatile("msync; isync"); 263 264 /* 265 * Set BPTR to the physical address of the boot page 266 */ 267 bptr = ((uint32_t)__boot_page - KERNBASE) + bp_kernload; 268 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 269 270 /* 271 * Release AP from hold-off state 272 */ 273 bp_trace = 0; 274 eebpcr |= (1 << (pc->pc_cpuid + 24)); 275 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 276 __asm __volatile("isync; msync"); 277 278 timeout = 500; 279 while (!pc->pc_awake && timeout--) 280 DELAY(1000); /* wait 1ms */ 281 282 /* 283 * Disable boot page translation so that the 4K page at the default 284 * address (= 0xfffff000) isn't permanently remapped and thus not 285 * usable otherwise. 286 */ 287 ccsr_write4(OCP85XX_BPTR, 0); 288 289 if (!pc->pc_awake) 290 printf("SMP: CPU %d didn't wake up (trace code %#x).\n", 291 pc->pc_awake, bp_trace); 292 return ((pc->pc_awake) ? 0 : EBUSY); 293 #else 294 /* No SMP support */ 295 return (ENXIO); 296 #endif 297 } 298 299 static void 300 booke_reset(platform_t plat) 301 { 302 303 /* 304 * Try the dedicated reset register first. 305 * If the SoC doesn't have one, we'll fall 306 * back to using the debug control register. 307 */ 308 ccsr_write4(OCP85XX_RSTCR, 2); 309 310 /* Clear DBCR0, disables debug interrupts and events. */ 311 mtspr(SPR_DBCR0, 0); 312 __asm __volatile("isync"); 313 314 /* Enable Debug Interrupts in MSR. */ 315 mtmsr(mfmsr() | PSL_DE); 316 317 /* Enable debug interrupts and issue reset. */ 318 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 319 320 printf("Reset failed...\n"); 321 while (1) 322 ; 323 } 324 325