1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/pcpu.h> 37 #include <sys/proc.h> 38 #include <sys/smp.h> 39 40 #include <machine/pcb.h> 41 #include <machine/psl.h> 42 #include <machine/smp.h> 43 #include <machine/spr.h> 44 45 extern void dcache_enable(void); 46 extern void dcache_inval(void); 47 extern void icache_enable(void); 48 extern void icache_inval(void); 49 50 volatile void *ap_pcpu; 51 52 uintptr_t 53 cpudep_ap_bootstrap() 54 { 55 uint32_t msr, csr; 56 uintptr_t sp; 57 58 /* Enable L1 caches */ 59 csr = mfspr(SPR_L1CSR0); 60 if ((csr & L1CSR0_DCE) == 0) { 61 dcache_inval(); 62 dcache_enable(); 63 } 64 65 csr = mfspr(SPR_L1CSR1); 66 if ((csr & L1CSR1_ICE) == 0) { 67 icache_inval(); 68 icache_enable(); 69 } 70 71 /* Set MSR */ 72 #ifdef __powerpc64__ 73 msr = PSL_CM | PSL_ME; 74 #else 75 msr = PSL_ME; 76 #endif 77 mtmsr(msr); 78 79 /* Assign pcpu fields, return ptr to this AP's idle thread kstack */ 80 pcpup->pc_curthread = pcpup->pc_idlethread; 81 #ifdef __powerpc64__ 82 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread)); 83 #else 84 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread)); 85 #endif 86 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 87 sp = pcpup->pc_curpcb->pcb_sp; 88 89 /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */ 90 91 return (sp); 92 } 93 94 void 95 cpudep_ap_setup() 96 { 97 } 98