1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/pcpu.h> 34 #include <sys/proc.h> 35 #include <sys/sched.h> 36 #include <sys/smp.h> 37 38 #include <machine/pcb.h> 39 #include <machine/psl.h> 40 #include <machine/smp.h> 41 #include <machine/spr.h> 42 43 extern void dcache_enable(void); 44 extern void dcache_inval(void); 45 extern void icache_enable(void); 46 extern void icache_inval(void); 47 48 volatile void *ap_pcpu; 49 50 uintptr_t 51 cpudep_ap_bootstrap(void) 52 { 53 uint32_t msr, csr; 54 uintptr_t sp; 55 56 /* Enable L1 caches */ 57 csr = mfspr(SPR_L1CSR0); 58 if ((csr & L1CSR0_DCE) == 0) { 59 dcache_inval(); 60 dcache_enable(); 61 } 62 63 csr = mfspr(SPR_L1CSR1); 64 if ((csr & L1CSR1_ICE) == 0) { 65 icache_inval(); 66 icache_enable(); 67 } 68 69 /* Set MSR */ 70 #ifdef __powerpc64__ 71 msr = PSL_CM | PSL_ME; 72 #else 73 msr = PSL_ME; 74 #endif 75 mtmsr(msr); 76 77 /* Assign pcpu fields, return ptr to this AP's idle thread kstack */ 78 pcpup->pc_curthread = pcpup->pc_idlethread; 79 #ifdef __powerpc64__ 80 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread)); 81 #else 82 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread)); 83 #endif 84 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 85 sp = pcpup->pc_curpcb->pcb_sp; 86 schedinit_ap(); 87 88 /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */ 89 90 return (sp); 91 } 92 93 void 94 cpudep_ap_setup(void) 95 { 96 } 97