1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/sched.h> 37 #include <sys/smp.h> 38 39 #include <machine/pcb.h> 40 #include <machine/psl.h> 41 #include <machine/smp.h> 42 #include <machine/spr.h> 43 44 extern void dcache_enable(void); 45 extern void dcache_inval(void); 46 extern void icache_enable(void); 47 extern void icache_inval(void); 48 49 volatile void *ap_pcpu; 50 51 uintptr_t 52 cpudep_ap_bootstrap(void) 53 { 54 uint32_t msr, csr; 55 uintptr_t sp; 56 57 /* Enable L1 caches */ 58 csr = mfspr(SPR_L1CSR0); 59 if ((csr & L1CSR0_DCE) == 0) { 60 dcache_inval(); 61 dcache_enable(); 62 } 63 64 csr = mfspr(SPR_L1CSR1); 65 if ((csr & L1CSR1_ICE) == 0) { 66 icache_inval(); 67 icache_enable(); 68 } 69 70 /* Set MSR */ 71 #ifdef __powerpc64__ 72 msr = PSL_CM | PSL_ME; 73 #else 74 msr = PSL_ME; 75 #endif 76 mtmsr(msr); 77 78 /* Assign pcpu fields, return ptr to this AP's idle thread kstack */ 79 pcpup->pc_curthread = pcpup->pc_idlethread; 80 #ifdef __powerpc64__ 81 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread)); 82 #else 83 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread)); 84 #endif 85 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 86 sp = pcpup->pc_curpcb->pcb_sp; 87 schedinit_ap(); 88 89 /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */ 90 91 return (sp); 92 } 93 94 void 95 cpudep_ap_setup(void) 96 { 97 } 98