1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/cdefs.h> 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/proc.h> 36 #include <sys/reboot.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/machdep.h> 42 43 #include <dev/fdt/fdt_common.h> 44 45 #include <powerpc/mpc85xx/mpc85xx.h> 46 47 extern void dcache_enable(void); 48 extern void dcache_inval(void); 49 extern void icache_enable(void); 50 extern void icache_inval(void); 51 extern void l2cache_enable(void); 52 extern void l2cache_inval(void); 53 extern void bpred_enable(void); 54 55 void 56 booke_enable_l1_cache(void) 57 { 58 uint32_t csr; 59 60 /* Enable D-cache if applicable */ 61 csr = mfspr(SPR_L1CSR0); 62 if ((csr & L1CSR0_DCE) == 0) { 63 dcache_inval(); 64 dcache_enable(); 65 } 66 67 csr = mfspr(SPR_L1CSR0); 68 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) 69 printf("L1 D-cache %sabled\n", 70 (csr & L1CSR0_DCE) ? "en" : "dis"); 71 72 /* Enable L1 I-cache if applicable. */ 73 csr = mfspr(SPR_L1CSR1); 74 if ((csr & L1CSR1_ICE) == 0) { 75 icache_inval(); 76 icache_enable(); 77 } 78 79 csr = mfspr(SPR_L1CSR1); 80 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) 81 printf("L1 I-cache %sabled\n", 82 (csr & L1CSR1_ICE) ? "en" : "dis"); 83 } 84 85 void 86 booke_enable_l2_cache(void) 87 { 88 uint32_t csr; 89 90 /* Enable L2 cache on E500mc */ 91 if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || 92 (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { 93 csr = mfspr(SPR_L2CSR0); 94 /* 95 * Don't actually attempt to manipulate the L2 cache if 96 * L2CFG0 is zero. 97 * 98 * Any chip with a working L2 cache will have a nonzero 99 * L2CFG0, as it will have a nonzero L2CSIZE field. 100 * 101 * This fixes waiting forever for cache enable in qemu, 102 * which does not implement the L2 cache. 103 */ 104 if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) { 105 l2cache_inval(); 106 l2cache_enable(); 107 } 108 109 csr = mfspr(SPR_L2CSR0); 110 if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) 111 printf("L2 cache %sabled\n", 112 (csr & L2CSR0_L2E) ? "en" : "dis"); 113 } 114 } 115 116 void 117 booke_enable_bpred(void) 118 { 119 uint32_t csr; 120 121 bpred_enable(); 122 csr = mfspr(SPR_BUCSR); 123 if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0) 124 printf("Branch Predictor %sabled\n", 125 (csr & BUCSR_BPEN) ? "en" : "dis"); 126 } 127 128 void 129 booke_disable_l2_cache(void) 130 { 131 } 132 133 /* Return 0 on handled success, otherwise signal number. */ 134 int 135 cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode) 136 { 137 register_t mcsr; 138 139 mcsr = mfspr(SPR_MCSR); 140 141 *ucode = BUS_OBJERR; 142 return (SIGBUS); 143 } 144