1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/cdefs.h> 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/proc.h> 36 #include <sys/reboot.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/machdep.h> 42 43 #include <dev/fdt/fdt_common.h> 44 45 #include <powerpc/mpc85xx/mpc85xx.h> 46 47 extern void dcache_enable(void); 48 extern void dcache_inval(void); 49 extern void icache_enable(void); 50 extern void icache_inval(void); 51 extern void l2cache_enable(void); 52 extern void l2cache_inval(void); 53 extern void bpred_enable(void); 54 55 void 56 booke_init_tlb(vm_paddr_t fdt_immr_pa) 57 { 58 59 } 60 61 void 62 booke_enable_l1_cache(void) 63 { 64 uint32_t csr; 65 66 /* Enable D-cache if applicable */ 67 csr = mfspr(SPR_L1CSR0); 68 if ((csr & L1CSR0_DCE) == 0) { 69 dcache_inval(); 70 dcache_enable(); 71 } 72 73 csr = mfspr(SPR_L1CSR0); 74 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) 75 printf("L1 D-cache %sabled\n", 76 (csr & L1CSR0_DCE) ? "en" : "dis"); 77 78 /* Enable L1 I-cache if applicable. */ 79 csr = mfspr(SPR_L1CSR1); 80 if ((csr & L1CSR1_ICE) == 0) { 81 icache_inval(); 82 icache_enable(); 83 } 84 85 csr = mfspr(SPR_L1CSR1); 86 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) 87 printf("L1 I-cache %sabled\n", 88 (csr & L1CSR1_ICE) ? "en" : "dis"); 89 } 90 91 void 92 booke_enable_l2_cache(void) 93 { 94 uint32_t csr; 95 96 /* Enable L2 cache on E500mc */ 97 if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || 98 (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { 99 csr = mfspr(SPR_L2CSR0); 100 if ((csr & L2CSR0_L2E) == 0) { 101 l2cache_inval(); 102 l2cache_enable(); 103 } 104 105 csr = mfspr(SPR_L2CSR0); 106 if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) 107 printf("L2 cache %sabled\n", 108 (csr & L2CSR0_L2E) ? "en" : "dis"); 109 } 110 } 111 112 void 113 booke_enable_bpred(void) 114 { 115 uint32_t csr; 116 117 bpred_enable(); 118 csr = mfspr(SPR_BUCSR); 119 if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0) 120 printf("Branch Predictor %sabled\n", 121 (csr & BUCSR_BPEN) ? "en" : "dis"); 122 } 123 124 void 125 booke_disable_l2_cache(void) 126 { 127 } 128