1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30 31#include "opt_hwpmc_hooks.h" 32 33#include <machine/asm.h> 34#include <machine/hid.h> 35#include <machine/param.h> 36#include <machine/spr.h> 37#include <machine/pte.h> 38#include <machine/trap.h> 39#include <machine/vmparam.h> 40#include <machine/tlb.h> 41 42#define TMPSTACKSZ 16384 43 44#ifdef __powerpc64__ 45#define GET_TOCBASE(r) \ 46 mfspr r, SPR_SPRG8 47#define TOC_RESTORE nop 48#define CMPI cmpdi 49#define CMPL cmpld 50#define LOAD ld 51#define LOADX ldarx 52#define STORE std 53#define STOREX stdcx. 54#define STU stdu 55#define CALLSIZE 48 56#define REDZONE 288 57#define THREAD_REG %r13 58#define ADDR(x) \ 59 .llong x 60#define WORD_SIZE 8 61#else 62#define GET_TOCBASE(r) 63#define TOC_RESTORE 64#define CMPI cmpwi 65#define CMPL cmplw 66#define LOAD lwz 67#define LOADX lwarx 68#define STOREX stwcx. 69#define STORE stw 70#define STU stwu 71#define CALLSIZE 8 72#define REDZONE 0 73#define THREAD_REG %r2 74#define ADDR(x) \ 75 .long x 76#define WORD_SIZE 4 77#endif 78 79 .text 80 .globl btext 81btext: 82 83/* 84 * This symbol is here for the benefit of kvm_mkdb, and is supposed to 85 * mark the start of kernel text. 86 */ 87 .globl kernel_text 88kernel_text: 89 90/* 91 * Startup entry. Note, this must be the first thing in the text segment! 92 */ 93 .text 94 .globl __start 95__start: 96 97/* 98 * Assumptions on the boot loader: 99 * - System memory starts from physical address 0 100 * - It's mapped by a single TLB1 entry 101 * - TLB1 mapping is 1:1 pa to va 102 * - Kernel is loaded at 64MB boundary 103 * - All PID registers are set to the same value 104 * - CPU is running in AS=0 105 * 106 * Registers contents provided by the loader(8): 107 * r1 : stack pointer 108 * r3 : metadata pointer 109 * 110 * We rearrange the TLB1 layout as follows: 111 * - Find TLB1 entry we started in 112 * - Make sure it's protected, invalidate other entries 113 * - Create temp entry in the second AS (make sure it's not TLB[1]) 114 * - Switch to temp mapping 115 * - Map 64MB of RAM in TLB1[1] 116 * - Use AS=0, set EPN to VM_MIN_KERNEL_ADDRESS and RPN to kernel load address 117 * - Switch to TLB1[1] mapping 118 * - Invalidate temp mapping 119 * 120 * locore registers use: 121 * r1 : stack pointer 122 * r2 : trace pointer (AP only, for early diagnostics) 123 * r3-r27 : scratch registers 124 * r28 : temp TLB1 entry 125 * r29 : initial TLB1 entry we started in 126 * r30-r31 : arguments (metadata pointer) 127 */ 128 129/* 130 * Keep arguments in r30 & r31 for later use. 131 */ 132 mr %r30, %r3 133 mr %r31, %r4 134 135/* 136 * Initial cleanup 137 */ 138 li %r3, PSL_DE /* Keep debug exceptions for CodeWarrior. */ 139#ifdef __powerpc64__ 140 oris %r3, %r3, PSL_CM@h 141#endif 142 mtmsr %r3 143 isync 144 145/* 146 * Initial HIDs configuration 147 */ 1481: 149 mfpvr %r3 150 rlwinm %r3, %r3, 16, 16, 31 151 152 lis %r4, HID0_E500_DEFAULT_SET@h 153 ori %r4, %r4, HID0_E500_DEFAULT_SET@l 154 155 /* Check for e500mc and e5500 */ 156 cmpli 0, 0, %r3, FSL_E500mc 157 bne 2f 158 159 lis %r4, HID0_E500MC_DEFAULT_SET@h 160 ori %r4, %r4, HID0_E500MC_DEFAULT_SET@l 161 b 3f 1622: 163 cmpli 0, 0, %r3, FSL_E5500 164 bne 3f 165 166 lis %r4, HID0_E5500_DEFAULT_SET@h 167 ori %r4, %r4, HID0_E5500_DEFAULT_SET@l 168 1693: 170 mtspr SPR_HID0, %r4 171 isync 172 173/* 174 * E500mc and E5500 do not have HID1 register, so skip HID1 setup on 175 * this core. 176 */ 177 cmpli 0, 0, %r3, FSL_E500mc 178 beq 1f 179 cmpli 0, 0, %r3, FSL_E5500 180 beq 1f 181 cmpli 0, 0, %r3, FSL_E6500 182 beq 1f 183 184 lis %r3, HID1_E500_DEFAULT_SET@h 185 ori %r3, %r3, HID1_E500_DEFAULT_SET@l 186 mtspr SPR_HID1, %r3 187 isync 1881: 189 /* Invalidate all entries in TLB0 */ 190 li %r3, 0 191 bl tlb_inval_all 192 193 cmpwi %r30, 0 194 beq done_mapping 195 196/* 197 * Locate the TLB1 entry that maps this code 198 */ 199 bl 1f 2001: mflr %r3 201 bl tlb1_find_current /* the entry found is returned in r29 */ 202 203 bl tlb1_inval_all_but_current 204 205/* 206 * Create temporary mapping in AS=1 and switch to it 207 */ 208 bl tlb1_temp_mapping_as1 209 210 mfmsr %r3 211 ori %r3, %r3, (PSL_IS | PSL_DS) 212 bl 2f 2132: mflr %r4 214 addi %r4, %r4, (3f - 2b) 215 mtspr SPR_SRR0, %r4 216 mtspr SPR_SRR1, %r3 217 rfi /* Switch context */ 218 219/* 220 * Invalidate initial entry 221 */ 2223: 223 mr %r3, %r29 224 bl tlb1_inval_entry 225 226/* 227 * Setup final mapping in TLB1[1] and switch to it 228 */ 229 /* Final kernel mapping, map in 64 MB of RAM */ 230 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 231 li %r4, 0 /* Entry 0 */ 232 rlwimi %r3, %r4, 16, 10, 15 233 mtspr SPR_MAS0, %r3 234 isync 235 236 li %r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l 237 oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h 238 mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */ 239 isync 240 241 LOAD_ADDR(%r3, VM_MIN_KERNEL_ADDRESS) 242 ori %r3, %r3, (_TLB_ENTRY_SHARED | MAS2_M)@l /* WIMGE = 0b00100 */ 243 mtspr SPR_MAS2, %r3 244 isync 245 246 /* Discover phys load address */ 247 bl 3f 2483: mflr %r4 /* Use current address */ 249 rlwinm %r4, %r4, 0, 0, 5 /* 64MB alignment mask */ 250 ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l 251 mtspr SPR_MAS3, %r4 /* Set RPN and protection */ 252 isync 253 bl zero_mas7 254 bl zero_mas8 255 isync 256 tlbwe 257 isync 258 msync 259 260 /* Switch to the above TLB1[1] mapping */ 261 bl 4f 2624: mflr %r4 263#ifdef __powerpc64__ 264 clrldi %r4, %r4, 38 265 clrrdi %r3, %r3, 12 266#else 267 rlwinm %r4, %r4, 0, 6, 31 /* Current offset from kernel load address */ 268 rlwinm %r3, %r3, 0, 0, 19 269#endif 270 add %r4, %r4, %r3 /* Convert to kernel virtual address */ 271 addi %r4, %r4, (5f - 4b) 272 li %r3, PSL_DE /* Note AS=0 */ 273#ifdef __powerpc64__ 274 oris %r3, %r3, PSL_CM@h 275#endif 276 mtspr SPR_SRR0, %r4 277 mtspr SPR_SRR1, %r3 278 rfi 279 280/* 281 * Invalidate temp mapping 282 */ 2835: 284 mr %r3, %r28 285 bl tlb1_inval_entry 286 287done_mapping: 288 289#ifdef __powerpc64__ 290 /* Set up the TOC pointer */ 291 b 0f 292 .align 3 2930: nop 294 bl 1f 295 .llong __tocbase + 0x8000 - . 2961: mflr %r2 297 ld %r1,0(%r2) 298 add %r2,%r1,%r2 299 mtspr SPR_SPRG8, %r2 300 301 /* Get load offset */ 302 ld %r31,-0x8000(%r2) /* First TOC entry is TOC base */ 303 subf %r31,%r31,%r2 /* Subtract from real TOC base to get base */ 304 305 /* Set up the stack pointer */ 306 addis %r1,%r2,TOC_REF(tmpstack)@ha 307 ld %r1,TOC_REF(tmpstack)@l(%r1) 308 addi %r1,%r1,TMPSTACKSZ-96 309 add %r1,%r1,%r31 310 bl 1f 311 .llong _DYNAMIC-. 3121: mflr %r3 313 ld %r4,0(%r3) 314 add %r3,%r4,%r3 315 mr %r4,%r31 316#else 317/* 318 * Setup a temporary stack 319 */ 320 bl 1f 321 .long tmpstack-. 3221: mflr %r1 323 lwz %r2,0(%r1) 324 add %r1,%r1,%r2 325 addi %r1, %r1, (TMPSTACKSZ - 16) 326 327/* 328 * Relocate kernel 329 */ 330 bl 1f 331 .long _DYNAMIC-. 332 .long _GLOBAL_OFFSET_TABLE_-. 3331: mflr %r5 334 lwz %r3,0(%r5) /* _DYNAMIC in %r3 */ 335 add %r3,%r3,%r5 336 lwz %r4,4(%r5) /* GOT pointer */ 337 add %r4,%r4,%r5 338 lwz %r4,4(%r4) /* got[0] is _DYNAMIC link addr */ 339 subf %r4,%r4,%r3 /* subtract to calculate relocbase */ 340#endif 341 bl CNAME(elf_reloc_self) 342 TOC_RESTORE 343 344/* 345 * Initialise exception vector offsets 346 */ 347 bl CNAME(ivor_setup) 348 TOC_RESTORE 349 350/* 351 * Set up arguments and jump to system initialization code 352 */ 353 mr %r3, %r30 354 mr %r4, %r31 355 356 /* Prepare core */ 357 bl CNAME(booke_init) 358 TOC_RESTORE 359 360 /* Switch to thread0.td_kstack now */ 361 mr %r1, %r3 362 li %r3, 0 363 STORE %r3, 0(%r1) 364 365 /* Machine independet part, does not return */ 366 bl CNAME(mi_startup) 367 TOC_RESTORE 368 /* NOT REACHED */ 3695: b 5b 370 371 372#ifdef SMP 373/************************************************************************/ 374/* AP Boot page */ 375/************************************************************************/ 376 .text 377 .globl __boot_page 378 .align 12 379__boot_page: 380 bl 1f 381 382 .globl bp_trace 383bp_trace: 384 .long 0 385 386 .globl bp_kernload 387bp_kernload: 388 .long 0 389 390/* 391 * Initial configuration 392 */ 3931: 394 mflr %r31 /* r31 hold the address of bp_trace */ 395 396 /* Set HIDs */ 397 mfpvr %r3 398 rlwinm %r3, %r3, 16, 16, 31 399 400 /* HID0 for E500 is default */ 401 lis %r4, HID0_E500_DEFAULT_SET@h 402 ori %r4, %r4, HID0_E500_DEFAULT_SET@l 403 404 cmpli 0, 0, %r3, FSL_E500mc 405 bne 2f 406 lis %r4, HID0_E500MC_DEFAULT_SET@h 407 ori %r4, %r4, HID0_E500MC_DEFAULT_SET@l 408 b 3f 4092: 410 cmpli 0, 0, %r3, FSL_E5500 411 bne 3f 412 lis %r4, HID0_E5500_DEFAULT_SET@h 413 ori %r4, %r4, HID0_E5500_DEFAULT_SET@l 4143: 415 mtspr SPR_HID0, %r4 416 isync 417 418 /* Enable branch prediction */ 419 li %r3, BUCSR_BPEN 420 mtspr SPR_BUCSR, %r3 421 isync 422 423 /* Invalidate all entries in TLB0 */ 424 li %r3, 0 425 bl tlb_inval_all 426 427/* 428 * Find TLB1 entry which is translating us now 429 */ 430 bl 2f 4312: mflr %r3 432 bl tlb1_find_current /* the entry number found is in r29 */ 433 434 bl tlb1_inval_all_but_current 435 436/* 437 * Create temporary translation in AS=1 and switch to it 438 */ 439 440 bl tlb1_temp_mapping_as1 441 442 mfmsr %r3 443 ori %r3, %r3, (PSL_IS | PSL_DS) 444#ifdef __powerpc64__ 445 oris %r3, %r3, PSL_CM@h 446#endif 447 bl 3f 4483: mflr %r4 449 addi %r4, %r4, (4f - 3b) 450 mtspr SPR_SRR0, %r4 451 mtspr SPR_SRR1, %r3 452 rfi /* Switch context */ 453 454/* 455 * Invalidate initial entry 456 */ 4574: 458 mr %r3, %r29 459 bl tlb1_inval_entry 460 461/* 462 * Setup final mapping in TLB1[1] and switch to it 463 */ 464 /* Final kernel mapping, map in 64 MB of RAM */ 465 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 466 li %r4, 0 /* Entry 0 */ 467 rlwimi %r3, %r4, 16, 4, 15 468 mtspr SPR_MAS0, %r3 469 isync 470 471 li %r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l 472 oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h 473 mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */ 474 isync 475 476 LOAD_ADDR(%r3, VM_MIN_KERNEL_ADDRESS) 477 ori %r3, %r3, (_TLB_ENTRY_SHARED | MAS2_M)@l /* WIMGE = 0b00100 */ 478 mtspr SPR_MAS2, %r3 479 isync 480 481 /* Retrieve kernel load [physical] address from bp_kernload */ 482#ifdef __powerpc64__ 483 b 0f 484 .align 3 4850: 486 nop 487#endif 488 bl 5f 489 ADDR(bp_kernload) 490 ADDR(__boot_page) 4915: mflr %r3 492#ifdef __powerpc64__ 493 ld %r4, 0(%r3) 494 ld %r5, 8(%r3) 495 clrrdi %r3, %r3, 12 496#else 497 lwz %r4, 0(%r3) 498 lwz %r5, 4(%r3) 499 rlwinm %r3, %r3, 0, 0, 19 500#endif 501 sub %r4, %r4, %r5 /* offset of bp_kernload within __boot_page */ 502 lwzx %r3, %r4, %r3 503 504 /* Set RPN and protection */ 505 ori %r3, %r3, (MAS3_SX | MAS3_SW | MAS3_SR)@l 506 mtspr SPR_MAS3, %r3 507 isync 508 bl zero_mas7 509 bl zero_mas8 510 isync 511 tlbwe 512 isync 513 msync 514 515 /* Switch to the final mapping */ 516 bl 6f 5176: mflr %r3 518 rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */ 519 add %r3, %r3, %r5 /* Make this virtual address */ 520 addi %r3, %r3, (7f - 6b) 521#ifdef __powerpc64__ 522 lis %r4, PSL_CM@h /* Note AS=0 */ 523#else 524 li %r4, 0 /* Note AS=0 */ 525#endif 526 mtspr SPR_SRR0, %r3 527 mtspr SPR_SRR1, %r4 528 rfi 5297: 530 531/* 532 * At this point we're running at virtual addresses VM_MIN_KERNEL_ADDRESS and 533 * beyond so it's allowed to directly access all locations the kernel was linked 534 * against. 535 */ 536 537/* 538 * Invalidate temp mapping 539 */ 540 mr %r3, %r28 541 bl tlb1_inval_entry 542 543#ifdef __powerpc64__ 544 /* Set up the TOC pointer */ 545 b 0f 546 .align 3 5470: nop 548 bl 1f 549 .llong __tocbase + 0x8000 - . 5501: mflr %r2 551 ld %r1,0(%r2) 552 add %r2,%r1,%r2 553 mtspr SPR_SPRG8, %r2 554 555 /* Set up the stack pointer */ 556 addis %r1,%r2,TOC_REF(tmpstack)@ha 557 ld %r1,TOC_REF(tmpstack)@l(%r1) 558 addi %r1,%r1,TMPSTACKSZ-96 559#else 560/* 561 * Setup a temporary stack 562 */ 563 bl 1f 564 .long tmpstack-. 5651: mflr %r1 566 lwz %r2,0(%r1) 567 add %r1,%r1,%r2 568 stw %r1, 0(%r1) 569 addi %r1, %r1, (TMPSTACKSZ - 16) 570#endif 571 572/* 573 * Initialise exception vector offsets 574 */ 575 bl CNAME(ivor_setup) 576 TOC_RESTORE 577 578 /* 579 * Assign our pcpu instance 580 */ 581 bl 1f 582 .long ap_pcpu-. 5831: mflr %r4 584 lwz %r3, 0(%r4) 585 add %r3, %r3, %r4 586 LOAD %r3, 0(%r3) 587 mtsprg0 %r3 588 589 bl CNAME(pmap_bootstrap_ap) 590 TOC_RESTORE 591 592 bl CNAME(cpudep_ap_bootstrap) 593 TOC_RESTORE 594 /* Switch to the idle thread's kstack */ 595 mr %r1, %r3 596 597 bl CNAME(machdep_ap_bootstrap) 598 TOC_RESTORE 599 600 /* NOT REACHED */ 6016: b 6b 602#endif /* SMP */ 603 604#if defined (BOOKE_E500) 605/* 606 * Invalidate all entries in the given TLB. 607 * 608 * r3 TLBSEL 609 */ 610tlb_inval_all: 611 rlwinm %r3, %r3, 3, (1 << 3) /* TLBSEL */ 612 ori %r3, %r3, (1 << 2) /* INVALL */ 613 tlbivax 0, %r3 614 isync 615 msync 616 617 tlbsync 618 msync 619 blr 620 621/* 622 * expects address to look up in r3, returns entry number in r29 623 * 624 * FIXME: the hidden assumption is we are now running in AS=0, but we should 625 * retrieve actual AS from MSR[IS|DS] and put it in MAS6[SAS] 626 */ 627tlb1_find_current: 628 mfspr %r17, SPR_PID0 629 slwi %r17, %r17, MAS6_SPID0_SHIFT 630 mtspr SPR_MAS6, %r17 631 isync 632 tlbsx 0, %r3 633 mfspr %r17, SPR_MAS0 634 rlwinm %r29, %r17, 16, 26, 31 /* MAS0[ESEL] -> r29 */ 635 636 /* Make sure we have IPROT set on the entry */ 637 mfspr %r17, SPR_MAS1 638 oris %r17, %r17, MAS1_IPROT@h 639 mtspr SPR_MAS1, %r17 640 isync 641 tlbwe 642 isync 643 msync 644 blr 645 646/* 647 * Invalidates a single entry in TLB1. 648 * 649 * r3 ESEL 650 * r4-r5 scratched 651 */ 652tlb1_inval_entry: 653 lis %r4, MAS0_TLBSEL1@h /* Select TLB1 */ 654 rlwimi %r4, %r3, 16, 10, 15 /* Select our entry */ 655 mtspr SPR_MAS0, %r4 656 isync 657 tlbre 658 li %r5, 0 /* MAS1[V] = 0 */ 659 mtspr SPR_MAS1, %r5 660 isync 661 tlbwe 662 isync 663 msync 664 blr 665 666/* 667 * r29 current entry number 668 * r28 returned temp entry 669 * r3-r5 scratched 670 */ 671tlb1_temp_mapping_as1: 672 /* Read our current translation */ 673 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 674 rlwimi %r3, %r29, 16, 10, 15 /* Select our current entry */ 675 mtspr SPR_MAS0, %r3 676 isync 677 tlbre 678 679 /* 680 * Prepare and write temp entry 681 * 682 * FIXME this is not robust against overflow i.e. when the current 683 * entry is the last in TLB1 684 */ 685 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 686 addi %r28, %r29, 1 /* Use next entry. */ 687 rlwimi %r3, %r28, 16, 10, 15 /* Select temp entry */ 688 mtspr SPR_MAS0, %r3 689 isync 690 mfspr %r5, SPR_MAS1 691 li %r4, 1 /* AS=1 */ 692 rlwimi %r5, %r4, 12, 19, 19 693 li %r4, 0 /* Global mapping, TID=0 */ 694 rlwimi %r5, %r4, 16, 8, 15 695 oris %r5, %r5, (MAS1_VALID | MAS1_IPROT)@h 696 mtspr SPR_MAS1, %r5 697 isync 698 mflr %r3 699 bl zero_mas7 700 bl zero_mas8 701 mtlr %r3 702 isync 703 tlbwe 704 isync 705 msync 706 blr 707 708/* 709 * Loops over TLB1, invalidates all entries skipping the one which currently 710 * maps this code. 711 * 712 * r29 current entry 713 * r3-r5 scratched 714 */ 715tlb1_inval_all_but_current: 716 mfspr %r3, SPR_TLB1CFG /* Get number of entries */ 717 andi. %r3, %r3, TLBCFG_NENTRY_MASK@l 718 li %r4, 0 /* Start from Entry 0 */ 7191: lis %r5, MAS0_TLBSEL1@h 720 rlwimi %r5, %r4, 16, 10, 15 721 mtspr SPR_MAS0, %r5 722 isync 723 tlbre 724 mfspr %r5, SPR_MAS1 725 cmpw %r4, %r29 /* our current entry? */ 726 beq 2f 727 rlwinm %r5, %r5, 0, 2, 31 /* clear VALID and IPROT bits */ 728 mtspr SPR_MAS1, %r5 729 isync 730 tlbwe 731 isync 732 msync 7332: addi %r4, %r4, 1 734 cmpw %r4, %r3 /* Check if this is the last entry */ 735 bne 1b 736 blr 737 738/* 739 * MAS7 and MAS8 conditional zeroing. 740 */ 741.globl zero_mas7 742zero_mas7: 743 mfpvr %r20 744 rlwinm %r20, %r20, 16, 16, 31 745 cmpli 0, 0, %r20, FSL_E500v1 746 beq 1f 747 748 li %r20, 0 749 mtspr SPR_MAS7, %r20 7501: 751 blr 752 753.globl zero_mas8 754zero_mas8: 755 mfpvr %r20 756 rlwinm %r20, %r20, 16, 16, 31 757 cmpli 0, 0, %r20, FSL_E500mc 758 beq 1f 759 cmpli 0, 0, %r20, FSL_E5500 760 beq 1f 761 762 blr 7631: 764 li %r20, 0 765 mtspr SPR_MAS8, %r20 766 blr 767#endif 768 769#ifdef SMP 770.globl __boot_tlb1 771 /* 772 * The __boot_tlb1 table is used to hold BSP TLB1 entries 773 * marked with _TLB_ENTRY_SHARED flag during AP bootstrap. 774 * The BSP fills in the table in tlb_ap_prep() function. Next, 775 * AP loads its contents to TLB1 hardware in pmap_bootstrap_ap(). 776 */ 777__boot_tlb1: 778 .space TLB1_MAX_ENTRIES * TLB_ENTRY_SIZE 779 780__boot_page_padding: 781 /* 782 * Boot page needs to be exactly 4K, with the last word of this page 783 * acting as the reset vector, so we need to stuff the remainder. 784 * Upon release from holdoff CPU fetches the last word of the boot 785 * page. 786 */ 787 .space 4092 - (__boot_page_padding - __boot_page) 788 b __boot_page 789#endif /* SMP */ 790 791/************************************************************************/ 792/* locore subroutines */ 793/************************************************************************/ 794 795/* 796 * Cache disable/enable/inval sequences according 797 * to section 2.16 of E500CORE RM. 798 */ 799ENTRY(dcache_inval) 800 /* Invalidate d-cache */ 801 mfspr %r3, SPR_L1CSR0 802 ori %r3, %r3, (L1CSR0_DCFI | L1CSR0_DCLFR)@l 803 msync 804 isync 805 mtspr SPR_L1CSR0, %r3 806 isync 8071: mfspr %r3, SPR_L1CSR0 808 andi. %r3, %r3, L1CSR0_DCFI 809 bne 1b 810 blr 811 812ENTRY(dcache_disable) 813 /* Disable d-cache */ 814 mfspr %r3, SPR_L1CSR0 815 li %r4, L1CSR0_DCE@l 816 not %r4, %r4 817 and %r3, %r3, %r4 818 msync 819 isync 820 mtspr SPR_L1CSR0, %r3 821 isync 822 blr 823 824ENTRY(dcache_enable) 825 /* Enable d-cache */ 826 mfspr %r3, SPR_L1CSR0 827 oris %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@h 828 ori %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@l 829 msync 830 isync 831 mtspr SPR_L1CSR0, %r3 832 isync 833 blr 834 835ENTRY(icache_inval) 836 /* Invalidate i-cache */ 837 mfspr %r3, SPR_L1CSR1 838 ori %r3, %r3, (L1CSR1_ICFI | L1CSR1_ICLFR)@l 839 isync 840 mtspr SPR_L1CSR1, %r3 841 isync 8421: mfspr %r3, SPR_L1CSR1 843 andi. %r3, %r3, L1CSR1_ICFI 844 bne 1b 845 blr 846 847ENTRY(icache_disable) 848 /* Disable i-cache */ 849 mfspr %r3, SPR_L1CSR1 850 li %r4, L1CSR1_ICE@l 851 not %r4, %r4 852 and %r3, %r3, %r4 853 isync 854 mtspr SPR_L1CSR1, %r3 855 isync 856 blr 857 858ENTRY(icache_enable) 859 /* Enable i-cache */ 860 mfspr %r3, SPR_L1CSR1 861 oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h 862 ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l 863 isync 864 mtspr SPR_L1CSR1, %r3 865 isync 866 blr 867 868/* 869 * L2 cache disable/enable/inval sequences for E500mc. 870 */ 871 872ENTRY(l2cache_inval) 873 mfspr %r3, SPR_L2CSR0 874 oris %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@h 875 ori %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@l 876 isync 877 mtspr SPR_L2CSR0, %r3 878 isync 8791: mfspr %r3, SPR_L2CSR0 880 andis. %r3, %r3, L2CSR0_L2FI@h 881 bne 1b 882 blr 883 884ENTRY(l2cache_enable) 885 mfspr %r3, SPR_L2CSR0 886 oris %r3, %r3, (L2CSR0_L2E | L2CSR0_L2PE)@h 887 isync 888 mtspr SPR_L2CSR0, %r3 889 isync 890 blr 891 892/* 893 * Branch predictor setup. 894 */ 895ENTRY(bpred_enable) 896 mfspr %r3, SPR_BUCSR 897 ori %r3, %r3, BUCSR_BBFI 898 isync 899 mtspr SPR_BUCSR, %r3 900 isync 901 ori %r3, %r3, BUCSR_BPEN 902 isync 903 mtspr SPR_BUCSR, %r3 904 isync 905 blr 906 907/* 908 * XXX: This should be moved to a shared AIM/booke asm file, if one ever is 909 * created. 910 */ 911ENTRY(get_spr) 912 mfspr %r3, 0 913 blr 914 915/************************************************************************/ 916/* Data section */ 917/************************************************************************/ 918 .data 919 .align 3 920GLOBAL(__startkernel) 921 ADDR(begin) 922GLOBAL(__endkernel) 923 ADDR(end) 924 .align 4 925tmpstack: 926 .space TMPSTACKSZ 927tmpstackbound: 928 .space 10240 /* XXX: this really should not be necessary */ 929#ifdef __powerpc64__ 930TOC_ENTRY(tmpstack) 931TOC_ENTRY(bp_kernload) 932#endif 933 934/* 935 * Compiled KERNBASE locations 936 */ 937 .globl kernbase 938 .set kernbase, KERNBASE 939 940#include <powerpc/booke/trap_subr.S> 941