1/* $FreeBSD$ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* Locate the per-CPU data structure */ 43#define GET_CPUINFO(r) \ 44 mfsprg0 r 45#define GET_TOCBASE(r) \ 46 li r,TRAP_TOCBASE; /* Magic address for TOC */ \ 47 ld r,0(r) 48 49/* 50 * Restore SRs for a pmap 51 * 52 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache 53 */ 54 55/* 56 * User SRs are loaded through a pointer to the current pmap. 57 */ 58restore_usersrs: 59 GET_CPUINFO(%r28) 60 ld %r28,PC_USERSLB(%r28) 61 cmpdi %r28, 0 /* If user SLB pointer NULL, exit */ 62 beqlr 63 64 li %r29, 0 /* Set the counter to zero */ 65 66 slbia 67 slbmfee %r31,%r29 68 clrrdi %r31,%r31,28 69 slbie %r31 701: ld %r31, 0(%r28) /* Load SLB entry pointer */ 71 cmpdi %r31, 0 /* If NULL, stop */ 72 beqlr 73 74 ld %r30, 0(%r31) /* Load SLBV */ 75 ld %r31, 8(%r31) /* Load SLBE */ 76 or %r31, %r31, %r29 /* Set SLBE slot */ 77 slbmte %r30, %r31 /* Install SLB entry */ 78 79 addi %r28, %r28, 8 /* Advance pointer */ 80 addi %r29, %r29, 1 81 b 1b /* Repeat */ 82 83/* 84 * Kernel SRs are loaded directly from the PCPU fields 85 */ 86restore_kernsrs: 87 GET_CPUINFO(%r28) 88 addi %r28,%r28,PC_KERNSLB 89 ld %r29,16(%r28) /* One past USER_SLB_SLOT */ 90 cmpdi %r28,0 91 beqlr /* If first kernel entry is invalid, 92 * SLBs not in use, so exit early */ 93 94 /* Otherwise, set up SLBs */ 95 li %r29, 0 /* Set the counter to zero */ 96 97 slbia 98 slbmfee %r31,%r29 99 clrrdi %r31,%r31,28 100 slbie %r31 1011: cmpdi %r29, USER_SLB_SLOT /* Skip the user slot */ 102 beq- 2f 103 104 ld %r31, 8(%r28) /* Load SLBE */ 105 cmpdi %r31, 0 /* If SLBE is not valid, stop */ 106 beqlr 107 ld %r30, 0(%r28) /* Load SLBV */ 108 slbmte %r30, %r31 /* Install SLB entry */ 109 1102: addi %r28, %r28, 16 /* Advance pointer */ 111 addi %r29, %r29, 1 112 cmpdi %r29, 64 /* Repeat if we are not at the end */ 113 blt 1b 114 blr 115 116/* 117 * FRAME_SETUP assumes: 118 * SPRG1 SP (1) 119 * SPRG3 trap type 120 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 121 * r28 LR 122 * r29 CR 123 * r30 scratch 124 * r31 scratch 125 * r1 kernel stack 126 * SRR0/1 as at start of trap 127 * 128 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse 129 * in any real-mode fault handler, including those handling double faults. 130 */ 131#define FRAME_SETUP(savearea) \ 132/* Have to enable translation to allow access of kernel stack: */ \ 133 GET_CPUINFO(%r31); \ 134 mfsrr0 %r30; \ 135 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 136 mfsrr1 %r30; \ 137 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 138 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \ 139 mfmsr %r30; \ 140 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 141 mtmsr %r30; /* stack can now be accessed */ \ 142 isync; \ 143 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \ 144 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \ 145 std %r31,FRAME_1+48(%r1); /* save SP " " */ \ 146 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \ 147 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \ 148 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \ 149 GET_CPUINFO(%r2); \ 150 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \ 151 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 152 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 153 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 154 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 155 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \ 156 std %r4, FRAME_4+48(%r1); \ 157 std %r5, FRAME_5+48(%r1); \ 158 std %r6, FRAME_6+48(%r1); \ 159 std %r7, FRAME_7+48(%r1); \ 160 std %r8, FRAME_8+48(%r1); \ 161 std %r9, FRAME_9+48(%r1); \ 162 std %r10, FRAME_10+48(%r1); \ 163 std %r11, FRAME_11+48(%r1); \ 164 std %r12, FRAME_12+48(%r1); \ 165 std %r13, FRAME_13+48(%r1); \ 166 std %r14, FRAME_14+48(%r1); \ 167 std %r15, FRAME_15+48(%r1); \ 168 std %r16, FRAME_16+48(%r1); \ 169 std %r17, FRAME_17+48(%r1); \ 170 std %r18, FRAME_18+48(%r1); \ 171 std %r19, FRAME_19+48(%r1); \ 172 std %r20, FRAME_20+48(%r1); \ 173 std %r21, FRAME_21+48(%r1); \ 174 std %r22, FRAME_22+48(%r1); \ 175 std %r23, FRAME_23+48(%r1); \ 176 std %r24, FRAME_24+48(%r1); \ 177 std %r25, FRAME_25+48(%r1); \ 178 std %r26, FRAME_26+48(%r1); \ 179 std %r27, FRAME_27+48(%r1); \ 180 std %r28, FRAME_28+48(%r1); \ 181 std %r29, FRAME_29+48(%r1); \ 182 std %r30, FRAME_30+48(%r1); \ 183 std %r31, FRAME_31+48(%r1); \ 184 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 185 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 186 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 187 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 188 mfxer %r3; \ 189 mfctr %r4; \ 190 mfsprg3 %r5; \ 191 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \ 192 std %r4, FRAME_CTR+48(1); \ 193 std %r5, FRAME_EXC+48(1); \ 194 std %r28,FRAME_AIM_DAR+48(1); \ 195 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \ 196 std %r30,FRAME_SRR0+48(1); \ 197 std %r31,FRAME_SRR1+48(1); \ 198 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */ 199 200#define FRAME_LEAVE(savearea) \ 201/* Disable exceptions: */ \ 202 mfmsr %r2; \ 203 andi. %r2,%r2,~PSL_EE@l; \ 204 mtmsr %r2; \ 205 isync; \ 206/* Now restore regs: */ \ 207 ld %r2,FRAME_SRR0+48(%r1); \ 208 ld %r3,FRAME_SRR1+48(%r1); \ 209 ld %r4,FRAME_CTR+48(%r1); \ 210 ld %r5,FRAME_XER+48(%r1); \ 211 ld %r6,FRAME_LR+48(%r1); \ 212 GET_CPUINFO(%r7); \ 213 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 214 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 215 ld %r7,FRAME_CR+48(%r1); \ 216 mtctr %r4; \ 217 mtxer %r5; \ 218 mtlr %r6; \ 219 mtsprg2 %r7; /* save cr */ \ 220 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \ 221 ld %r30,FRAME_30+48(%r1); \ 222 ld %r29,FRAME_29+48(%r1); \ 223 ld %r28,FRAME_28+48(%r1); \ 224 ld %r27,FRAME_27+48(%r1); \ 225 ld %r26,FRAME_26+48(%r1); \ 226 ld %r25,FRAME_25+48(%r1); \ 227 ld %r24,FRAME_24+48(%r1); \ 228 ld %r23,FRAME_23+48(%r1); \ 229 ld %r22,FRAME_22+48(%r1); \ 230 ld %r21,FRAME_21+48(%r1); \ 231 ld %r20,FRAME_20+48(%r1); \ 232 ld %r19,FRAME_19+48(%r1); \ 233 ld %r18,FRAME_18+48(%r1); \ 234 ld %r17,FRAME_17+48(%r1); \ 235 ld %r16,FRAME_16+48(%r1); \ 236 ld %r15,FRAME_15+48(%r1); \ 237 ld %r14,FRAME_14+48(%r1); \ 238 ld %r13,FRAME_13+48(%r1); \ 239 ld %r12,FRAME_12+48(%r1); \ 240 ld %r11,FRAME_11+48(%r1); \ 241 ld %r10,FRAME_10+48(%r1); \ 242 ld %r9, FRAME_9+48(%r1); \ 243 ld %r8, FRAME_8+48(%r1); \ 244 ld %r7, FRAME_7+48(%r1); \ 245 ld %r6, FRAME_6+48(%r1); \ 246 ld %r5, FRAME_5+48(%r1); \ 247 ld %r4, FRAME_4+48(%r1); \ 248 ld %r3, FRAME_3+48(%r1); \ 249 ld %r2, FRAME_2+48(%r1); \ 250 ld %r0, FRAME_0+48(%r1); \ 251 ld %r1, FRAME_1+48(%r1); \ 252/* Can't touch %r1 from here on */ \ 253 mtsprg3 %r3; /* save r3 */ \ 254/* Disable translation, machine check and recoverability: */ \ 255 mfmsr %r3; \ 256 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 257 mtmsr %r3; \ 258 isync; \ 259/* Decide whether we return to user mode: */ \ 260 GET_CPUINFO(%r3); \ 261 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \ 262 mtcr %r3; \ 263 bf 17,1f; /* branch if PSL_PR is false */ \ 264/* Restore user SRs */ \ 265 GET_CPUINFO(%r3); \ 266 std %r27,(savearea+CPUSAVE_R27)(%r3); \ 267 std %r28,(savearea+CPUSAVE_R28)(%r3); \ 268 std %r29,(savearea+CPUSAVE_R29)(%r3); \ 269 std %r30,(savearea+CPUSAVE_R30)(%r3); \ 270 std %r31,(savearea+CPUSAVE_R31)(%r3); \ 271 mflr %r27; /* preserve LR */ \ 272 bl restore_usersrs; /* uses r28-r31 */ \ 273 mtlr %r27; \ 274 ld %r31,(savearea+CPUSAVE_R31)(%r3); \ 275 ld %r30,(savearea+CPUSAVE_R30)(%r3); \ 276 ld %r29,(savearea+CPUSAVE_R29)(%r3); \ 277 ld %r28,(savearea+CPUSAVE_R28)(%r3); \ 278 ld %r27,(savearea+CPUSAVE_R27)(%r3); \ 2791: mfsprg2 %r3; /* restore cr */ \ 280 mtcr %r3; \ 281 GET_CPUINFO(%r3); \ 282 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \ 283 mtsrr0 %r3; \ 284 GET_CPUINFO(%r3); \ 285 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \ 286 mtsrr1 %r3; \ 287 mfsprg3 %r3 /* restore r3 */ 288 289#ifdef KDTRACE_HOOKS 290 .data 291 .globl dtrace_invop_calltrap_addr 292 .align 8 293 .type dtrace_invop_calltrap_addr, @object 294 .size dtrace_invop_calltrap_addr, 8 295dtrace_invop_calltrap_addr: 296 .word 0 297 .word 0 298 299 .text 300#endif 301 302/* 303 * Processor reset exception handler. These are typically 304 * the first instructions the processor executes after a 305 * software reset. We do this in two bits so that we are 306 * not still hanging around in the trap handling region 307 * once the MMU is turned on. 308 */ 309 .globl CNAME(rstcode), CNAME(rstcodeend), CNAME(cpu_reset_handler) 310 .globl CNAME(cpu_wakeup_handler) 311 .p2align 3 312CNAME(rstcode): 313 /* 314 * Check if this is software reset or 315 * processor is waking up from power saving mode 316 * It is software reset when 46:47 = 0b00 317 */ 318 mfsrr1 %r9 /* Load SRR1 into r9 */ 319 andis. %r9,%r9,0x3 /* Logic AND with 46:47 bits */ 320 beq 2f /* Branch if software reset */ 321 bl 1f 322 .llong cpu_wakeup_handler 323 324 /* It is software reset */ 325 326 /* Explicitly set MSR[SF] */ 3272: mfmsr %r9 328 li %r8,1 329 insrdi %r9,%r8,1,0 330 mtmsrd %r9 331 isync 332 333 bl 1f 334 .llong cpu_reset_handler /* Make sure to maintain 8-byte alignment */ 335 3361: mflr %r9 337 ld %r9,0(%r9) 338 mtlr %r9 339 340 blr 341CNAME(rstcodeend): 342 343cpu_reset_handler: 344 GET_TOCBASE(%r2) 345 346 ld %r1,TOC_REF(tmpstk)(%r2) /* get new SP */ 347 addi %r1,%r1,(TMPSTKSZ-48) 348 349 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */ 350 nop 351 lis %r3,1@l 352 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */ 353 nop 354 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */ 355 nop 356 mr %r1,%r3 /* Use new stack */ 357 bl CNAME(cpudep_ap_setup) 358 nop 359 GET_CPUINFO(%r5) 360 ld %r3,(PC_RESTORE)(%r5) 361 cmpldi %cr0,%r3,0 362 beq %cr0,2f 363 nop 364 li %r4,1 365 bl CNAME(longjmp) 366 nop 3672: 368#ifdef SMP 369 bl CNAME(machdep_ap_bootstrap) /* And away! */ 370 nop 371#endif 372 373 /* Should not be reached */ 3749: 375 b 9b 376 377cpu_wakeup_handler: 378 GET_TOCBASE(%r2) 379 380 /* Check for false wake up due to badly SRR1 set (eg. by OPAL) */ 381 ld %r3,TOC_REF(can_wakeup)(%r2) 382 ld %r3,0(%r3) 383 cmpdi %r3,0 384 beq cpu_reset_handler 385 386 /* Turn on MMU after return from interrupt */ 387 mfsrr1 %r3 388 ori %r3,%r3,(PSL_IR | PSL_DR) 389 mtsrr1 %r3 390 391 /* Turn on MMU (needed to access PCB) */ 392 mfmsr %r3 393 ori %r3,%r3,(PSL_IR | PSL_DR) 394 mtmsr %r3 395 isync 396 397 mfsprg0 %r3 398 399 ld %r3,PC_CURTHREAD(%r3) /* Get current thread */ 400 ld %r3,TD_PCB(%r3) /* Get PCB of current thread */ 401 ld %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs. */ 402 ld %r13,PCB_CONTEXT+1*8(%r3) 403 ld %r14,PCB_CONTEXT+2*8(%r3) 404 ld %r15,PCB_CONTEXT+3*8(%r3) 405 ld %r16,PCB_CONTEXT+4*8(%r3) 406 ld %r17,PCB_CONTEXT+5*8(%r3) 407 ld %r18,PCB_CONTEXT+6*8(%r3) 408 ld %r19,PCB_CONTEXT+7*8(%r3) 409 ld %r20,PCB_CONTEXT+8*8(%r3) 410 ld %r21,PCB_CONTEXT+9*8(%r3) 411 ld %r22,PCB_CONTEXT+10*8(%r3) 412 ld %r23,PCB_CONTEXT+11*8(%r3) 413 ld %r24,PCB_CONTEXT+12*8(%r3) 414 ld %r25,PCB_CONTEXT+13*8(%r3) 415 ld %r26,PCB_CONTEXT+14*8(%r3) 416 ld %r27,PCB_CONTEXT+15*8(%r3) 417 ld %r28,PCB_CONTEXT+16*8(%r3) 418 ld %r29,PCB_CONTEXT+17*8(%r3) 419 ld %r30,PCB_CONTEXT+18*8(%r3) 420 ld %r31,PCB_CONTEXT+19*8(%r3) 421 ld %r5,PCB_CR(%r3) /* Load the condition register */ 422 mtcr %r5 423 ld %r5,PCB_LR(%r3) /* Load the link register */ 424 mtsrr0 %r5 425 ld %r1,PCB_SP(%r3) /* Load the stack pointer */ 426 ld %r2,PCB_TOC(%r3) /* Load the TOC pointer */ 427 428 rfid 429 430/* 431 * This code gets copied to all the trap vectors 432 * (except ISI/DSI, ALI, and the interrupts). Has to fit in 8 instructions! 433 */ 434 435 .globl CNAME(trapcode),CNAME(trapcodeend) 436 .p2align 3 437CNAME(trapcode): 438 mtsprg1 %r1 /* save SP */ 439 mflr %r1 /* Save the old LR in r1 */ 440 mtsprg2 %r1 /* And then in SPRG2 */ 441 ld %r1,TRAP_GENTRAP(0) 442 mtlr %r1 443 li %r1, 0xe0 /* How to get the vector from LR */ 444 blrl /* Branch to generictrap */ 445CNAME(trapcodeend): 446 447/* 448 * For SLB misses: do special things for the kernel 449 * 450 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is 451 * the only time this can be called. 452 */ 453 .globl CNAME(slbtrap),CNAME(slbtrapend) 454 .p2align 3 455CNAME(slbtrap): 456 mtsprg1 %r1 /* save SP */ 457 GET_CPUINFO(%r1) 458 std %r2,(PC_SLBSAVE+16)(%r1) 459 mfcr %r2 /* save CR */ 460 std %r2,(PC_SLBSAVE+104)(%r1) 461 mfsrr1 %r2 /* test kernel mode */ 462 mtcr %r2 463 bf 17,2f /* branch if PSL_PR is false */ 464 /* User mode */ 465 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 466 mtcr %r2 467 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */ 468 mflr %r1 /* Save the old LR in r1 */ 469 mtsprg2 %r1 /* And then in SPRG2 */ 470 /* 52 bytes so far */ 471 bl 1f 472 .llong generictrap 4731: mflr %r1 474 ld %r1,0(%r1) 475 mtlr %r1 476 li %r1, 0x80 /* How to get the vector from LR */ 477 blrl /* Branch to generictrap */ 478 /* 84 bytes */ 4792: mflr %r2 /* Save the old LR in r2 */ 480 nop 481 bl 3f /* Begin dance to jump to kern_slbtrap*/ 482 .llong kern_slbtrap 4833: mflr %r1 484 ld %r1,0(%r1) 485 mtlr %r1 486 GET_CPUINFO(%r1) 487 blrl /* 124 bytes -- 4 to spare */ 488CNAME(slbtrapend): 489 490kern_slbtrap: 491 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */ 492 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */ 493 494 /* Check if this needs to be handled as a regular trap (userseg miss) */ 495 mflr %r2 496 andi. %r2,%r2,0xff80 497 cmpwi %r2,0x380 498 bne 1f 499 mfdar %r2 500 b 2f 5011: mfsrr0 %r2 5022: /* r2 now contains the fault address */ 503 lis %r3,SEGMENT_MASK@highesta 504 ori %r3,%r3,SEGMENT_MASK@highera 505 sldi %r3,%r3,32 506 oris %r3,%r3,SEGMENT_MASK@ha 507 ori %r3,%r3,SEGMENT_MASK@l 508 and %r2,%r2,%r3 /* R2 = segment base address */ 509 lis %r3,USER_ADDR@highesta 510 ori %r3,%r3,USER_ADDR@highera 511 sldi %r3,%r3,32 512 oris %r3,%r3,USER_ADDR@ha 513 ori %r3,%r3,USER_ADDR@l 514 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */ 515 bne 3f 516 517 /* User seg miss, handle as a regular trap */ 518 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */ 519 mtcr %r2 520 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */ 521 ld %r3,(PC_SLBSAVE+24)(%r1) 522 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */ 523 mtsprg2 %r1 /* And then in SPRG2 */ 524 li %r1, 0x80 /* How to get the vector from LR */ 525 b generictrap /* Retain old LR using b */ 526 5273: /* Real kernel SLB miss */ 528 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */ 529 mfsprg1 %r2 /* Old R1 */ 530 std %r2,(PC_SLBSAVE+8)(%r1) 531 /* R2,R3 already saved */ 532 std %r4,(PC_SLBSAVE+32)(%r1) 533 std %r5,(PC_SLBSAVE+40)(%r1) 534 std %r6,(PC_SLBSAVE+48)(%r1) 535 std %r7,(PC_SLBSAVE+56)(%r1) 536 std %r8,(PC_SLBSAVE+64)(%r1) 537 std %r9,(PC_SLBSAVE+72)(%r1) 538 std %r10,(PC_SLBSAVE+80)(%r1) 539 std %r11,(PC_SLBSAVE+88)(%r1) 540 std %r12,(PC_SLBSAVE+96)(%r1) 541 /* CR already saved */ 542 mfxer %r2 /* save XER */ 543 std %r2,(PC_SLBSAVE+112)(%r1) 544 mflr %r2 /* save LR (SP already saved) */ 545 std %r2,(PC_SLBSAVE+120)(%r1) 546 mfctr %r2 /* save CTR */ 547 std %r2,(PC_SLBSAVE+128)(%r1) 548 549 /* Call handler */ 550 addi %r1,%r1,PC_SLBSTACK-48+1024 551 li %r2,~15 552 and %r1,%r1,%r2 553 GET_TOCBASE(%r2) 554 mflr %r3 555 andi. %r3,%r3,0xff80 556 mfdar %r4 557 mfsrr0 %r5 558 bl handle_kernel_slb_spill 559 nop 560 561 /* Save r28-31, restore r4-r12 */ 562 GET_CPUINFO(%r1) 563 ld %r4,(PC_SLBSAVE+32)(%r1) 564 ld %r5,(PC_SLBSAVE+40)(%r1) 565 ld %r6,(PC_SLBSAVE+48)(%r1) 566 ld %r7,(PC_SLBSAVE+56)(%r1) 567 ld %r8,(PC_SLBSAVE+64)(%r1) 568 ld %r9,(PC_SLBSAVE+72)(%r1) 569 ld %r10,(PC_SLBSAVE+80)(%r1) 570 ld %r11,(PC_SLBSAVE+88)(%r1) 571 ld %r12,(PC_SLBSAVE+96)(%r1) 572 std %r28,(PC_SLBSAVE+64)(%r1) 573 std %r29,(PC_SLBSAVE+72)(%r1) 574 std %r30,(PC_SLBSAVE+80)(%r1) 575 std %r31,(PC_SLBSAVE+88)(%r1) 576 577 /* Restore kernel mapping */ 578 bl restore_kernsrs 579 580 /* Restore remaining registers */ 581 ld %r28,(PC_SLBSAVE+64)(%r1) 582 ld %r29,(PC_SLBSAVE+72)(%r1) 583 ld %r30,(PC_SLBSAVE+80)(%r1) 584 ld %r31,(PC_SLBSAVE+88)(%r1) 585 586 ld %r2,(PC_SLBSAVE+104)(%r1) 587 mtcr %r2 588 ld %r2,(PC_SLBSAVE+112)(%r1) 589 mtxer %r2 590 ld %r2,(PC_SLBSAVE+120)(%r1) 591 mtlr %r2 592 ld %r2,(PC_SLBSAVE+128)(%r1) 593 mtctr %r2 594 ld %r2,(PC_SLBSAVE+136)(%r1) 595 mtlr %r2 596 597 /* Restore r0-r3 */ 598 ld %r0,(PC_SLBSAVE+0)(%r1) 599 ld %r2,(PC_SLBSAVE+16)(%r1) 600 ld %r3,(PC_SLBSAVE+24)(%r1) 601 mfsprg1 %r1 602 603 /* Back to whatever we were doing */ 604 rfid 605 606/* 607 * For ALI: has to save DSISR and DAR 608 */ 609 .globl CNAME(alitrap),CNAME(aliend) 610CNAME(alitrap): 611 mtsprg1 %r1 /* save SP */ 612 GET_CPUINFO(%r1) 613 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 614 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 615 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 616 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 617 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 618 mfdar %r30 619 mfdsisr %r31 620 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 621 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 622 mfsprg1 %r1 /* restore SP, in case of branch */ 623 mflr %r28 /* save LR */ 624 mfcr %r29 /* save CR */ 625 626 /* Begin dance to branch to s_trap in a bit */ 627 b 1f 628 .p2align 3 6291: nop 630 bl 1f 631 .llong s_trap 6321: mflr %r31 633 ld %r31,0(%r31) 634 mtlr %r31 635 636 /* Put our exception vector in SPRG3 */ 637 li %r31, EXC_ALI 638 mtsprg3 %r31 639 640 /* Test whether we already had PR set */ 641 mfsrr1 %r31 642 mtcr %r31 643 blrl 644CNAME(aliend): 645 646/* 647 * Similar to the above for DSI 648 * Has to handle standard pagetable spills 649 */ 650 .globl CNAME(dsitrap),CNAME(dsiend) 651 .p2align 3 652CNAME(dsitrap): 653 mtsprg1 %r1 /* save SP */ 654 GET_CPUINFO(%r1) 655 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 656 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) 657 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 658 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 659 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 660 mfcr %r29 /* save CR */ 661 mfxer %r30 /* save XER */ 662 mtsprg2 %r30 /* in SPRG2 */ 663 mfsrr1 %r31 /* test kernel mode */ 664 mtcr %r31 665 mflr %r28 /* save LR (SP already saved) */ 666 bl 1f /* Begin branching to disitrap */ 667 .llong disitrap 6681: mflr %r1 669 ld %r1,0(%r1) 670 mtlr %r1 671 blrl /* Branch to generictrap */ 672CNAME(dsiend): 673 674/* 675 * Preamble code for DSI/ISI traps 676 */ 677disitrap: 678 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 679 mflr %r1 680 andi. %r1,%r1,0xff00 681 mtsprg3 %r1 682 683 GET_CPUINFO(%r1) 684 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) 685 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 686 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 687 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 688 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 689 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 690 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 691 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 692 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 693 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 694 mfdar %r30 695 mfdsisr %r31 696 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 697 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 698 699#ifdef KDB 700 /* Try to detect a kernel stack overflow */ 701 mfsrr1 %r31 702 mtcr %r31 703 bt 17,realtrap /* branch is user mode */ 704 mfsprg1 %r31 /* get old SP */ 705 clrrdi %r31,%r31,12 /* Round SP down to nearest page */ 706 sub. %r30,%r31,%r30 /* SP - DAR */ 707 bge 1f 708 neg %r30,%r30 /* modulo value */ 7091: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */ 710 bge %cr0,realtrap /* no, too far away. */ 711 712 /* Now convert this DSI into a DDB trap. */ 713 GET_CPUINFO(%r1) 714 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 715 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 716 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 717 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 718 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */ 719 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */ 720 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 721 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 722 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 723 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 724 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 725 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 726 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 727 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 728 b dbtrap 729#endif 730 731 /* XXX need stack probe here */ 732realtrap: 733/* Test whether we already had PR set */ 734 mfsrr1 %r1 735 mtcr %r1 736 mfsprg1 %r1 /* restore SP (might have been 737 overwritten) */ 738 bf 17,k_trap /* branch if PSL_PR is false */ 739 GET_CPUINFO(%r1) 740 ld %r1,PC_CURPCB(%r1) 741 mr %r27,%r28 /* Save LR, r29 */ 742 mtsprg2 %r29 743 bl restore_kernsrs /* enable kernel mapping */ 744 mfsprg2 %r29 745 mr %r28,%r27 746 b s_trap 747 748/* 749 * generictrap does some standard setup for trap handling to minimize 750 * the code that need be installed in the actual vectors. It expects 751 * the following conditions. 752 * 753 * R1 - Trap vector = LR & (0xff00 | R1) 754 * SPRG1 - Original R1 contents 755 * SPRG2 - Original LR 756 */ 757 758 .globl CNAME(generictrap) 759generictrap: 760 /* Save R1 for computing the exception vector */ 761 mtsprg3 %r1 762 763 /* Save interesting registers */ 764 GET_CPUINFO(%r1) 765 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 766 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 767 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 768 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 769 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 770 mfdar %r30 771 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 772 mfsprg1 %r1 /* restore SP, in case of branch */ 773 mfsprg2 %r28 /* save LR */ 774 mfcr %r29 /* save CR */ 775 776 /* Compute the exception vector from the link register */ 777 mfsprg3 %r31 778 ori %r31,%r31,0xff00 779 mflr %r30 780 addi %r30,%r30,-4 /* The branch instruction, not the next */ 781 and %r30,%r30,%r31 782 mtsprg3 %r30 783 784 /* Test whether we already had PR set */ 785 mfsrr1 %r31 786 mtcr %r31 787 788s_trap: 789 bf 17,k_trap /* branch if PSL_PR is false */ 790 GET_CPUINFO(%r1) 791u_trap: 792 ld %r1,PC_CURPCB(%r1) 793 mr %r27,%r28 /* Save LR, r29 */ 794 mtsprg2 %r29 795 bl restore_kernsrs /* enable kernel mapping */ 796 mfsprg2 %r29 797 mr %r28,%r27 798 799/* 800 * Now the common trap catching code. 801 */ 802k_trap: 803 FRAME_SETUP(PC_TEMPSAVE) 804/* Call C interrupt dispatcher: */ 805trapagain: 806 GET_TOCBASE(%r2) 807 addi %r3,%r1,48 808 bl CNAME(powerpc_interrupt) 809 nop 810 811 .globl CNAME(trapexit) /* backtrace code sentinel */ 812CNAME(trapexit): 813/* Disable interrupts: */ 814 mfmsr %r3 815 andi. %r3,%r3,~PSL_EE@l 816 mtmsr %r3 817 isync 818/* Test AST pending: */ 819 ld %r5,FRAME_SRR1+48(%r1) 820 mtcr %r5 821 bf 17,1f /* branch if PSL_PR is false */ 822 823 GET_CPUINFO(%r3) /* get per-CPU pointer */ 824 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */ 825 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 826 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 827 and. %r4,%r4,%r5 828 beq 1f 829 mfmsr %r3 /* re-enable interrupts */ 830 ori %r3,%r3,PSL_EE@l 831 mtmsr %r3 832 isync 833 GET_TOCBASE(%r2) 834 addi %r3,%r1,48 835 bl CNAME(ast) 836 nop 837 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 838CNAME(asttrapexit): 839 b trapexit /* test ast ret value ? */ 8401: 841 FRAME_LEAVE(PC_TEMPSAVE) 842 rfid 843 844#if defined(KDB) 845/* 846 * Deliberate entry to dbtrap 847 */ 848ASENTRY_NOPROF(breakpoint) 849 mtsprg1 %r1 850 mfmsr %r3 851 mtsrr1 %r3 852 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 853 mtmsr %r3 /* disable interrupts */ 854 isync 855 GET_CPUINFO(%r3) 856 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3) 857 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 858 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 859 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 860 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 861 mflr %r28 862 li %r29,EXC_BPT 863 mtlr %r29 864 mfcr %r29 865 mtsrr0 %r28 866 867/* 868 * Now the kdb trap catching code. 869 */ 870dbtrap: 871 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 872 mflr %r1 873 andi. %r1,%r1,0xff00 874 mtsprg3 %r1 875 876 ld %r1,TRAP_TOCBASE(0) /* get new SP */ 877 ld %r1,TOC_REF(tmpstk)(%r1) 878 addi %r1,%r1,(TMPSTKSZ-48) 879 880 FRAME_SETUP(PC_DBSAVE) 881/* Call C trap code: */ 882 GET_TOCBASE(%r2) 883 addi %r3,%r1,48 884 bl CNAME(db_trap_glue) 885 nop 886 or. %r3,%r3,%r3 887 bne dbleave 888/* This wasn't for KDB, so switch to real trap: */ 889 ld %r3,FRAME_EXC+48(%r1) /* save exception */ 890 GET_CPUINFO(%r4) 891 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 892 FRAME_LEAVE(PC_DBSAVE) 893 mtsprg1 %r1 /* prepare for entrance to realtrap */ 894 GET_CPUINFO(%r1) 895 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 896 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 897 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 898 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 899 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 900 mflr %r28 901 mfcr %r29 902 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 903 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 904 mfsprg1 %r1 905 b realtrap 906dbleave: 907 FRAME_LEAVE(PC_DBSAVE) 908 rfid 909 910/* 911 * In case of KDB we want a separate trap catcher for it 912 */ 913 .globl CNAME(dblow),CNAME(dbend) 914 .p2align 3 915CNAME(dblow): 916 mtsprg1 %r1 /* save SP */ 917 mtsprg2 %r29 /* save r29 */ 918 mfcr %r29 /* save CR in r29 */ 919 mfsrr1 %r1 920 mtcr %r1 921 bf 17,1f /* branch if privileged */ 922 923 /* Unprivileged case */ 924 mtcr %r29 /* put the condition register back */ 925 mfsprg2 %r29 /* ... and r29 */ 926 mflr %r1 /* save LR */ 927 mtsprg2 %r1 /* And then in SPRG2 */ 928 929 ld %r1, TRAP_GENTRAP(0) /* Get branch address */ 930 mtlr %r1 931 li %r1, 0 /* How to get the vector from LR */ 932 blrl /* Branch to generictrap */ 933 9341: 935 GET_CPUINFO(%r1) 936 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ 937 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 938 mfsprg2 %r28 /* r29 holds cr... */ 939 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 940 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 941 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 942 mflr %r28 /* save LR */ 943 nop /* alignment */ 944 bl 9f /* Begin branch */ 945 .llong dbtrap 9469: mflr %r1 947 ld %r1,0(%r1) 948 mtlr %r1 949 blrl /* Branch to generictrap */ 950CNAME(dbend): 951#endif /* KDB */ 952