1/* $FreeBSD$ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 lwz sr,12*4(pmap); mtsr 12,sr; \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62/* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65#define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) 70 71/* 72 * Kernel SRs are loaded directly from kernel_pmap_ 73 */ 74#define RESTORE_KERN_SRS(pmap,sr) \ 75 lis pmap,CNAME(kernel_pmap_store)@ha; \ 76 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 77 RESTORE_SRS(pmap,sr) 78 79/* 80 * FRAME_SETUP assumes: 81 * SPRG1 SP (1) 82 * SPRG3 trap type 83 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 84 * r28 LR 85 * r29 CR 86 * r30 scratch 87 * r31 scratch 88 * r1 kernel stack 89 * SRR0/1 as at start of trap 90 */ 91#define FRAME_SETUP(savearea) \ 92/* Have to enable translation to allow access of kernel stack: */ \ 93 GET_CPUINFO(%r31); \ 94 mfsrr0 %r30; \ 95 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 96 mfsrr1 %r30; \ 97 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 98 mfmsr %r30; \ 99 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 100 mtmsr %r30; /* stack can now be accessed */ \ 101 isync; \ 102 mfsprg1 %r31; /* get saved SP */ \ 103 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 104 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 105 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 106 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 107 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 108 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 109 GET_CPUINFO(%r2); \ 110 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 111 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 112 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 113 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 114 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 115 stw %r4, FRAME_4+8(%r1); \ 116 stw %r5, FRAME_5+8(%r1); \ 117 stw %r6, FRAME_6+8(%r1); \ 118 stw %r7, FRAME_7+8(%r1); \ 119 stw %r8, FRAME_8+8(%r1); \ 120 stw %r9, FRAME_9+8(%r1); \ 121 stw %r10, FRAME_10+8(%r1); \ 122 stw %r11, FRAME_11+8(%r1); \ 123 stw %r12, FRAME_12+8(%r1); \ 124 stw %r13, FRAME_13+8(%r1); \ 125 stw %r14, FRAME_14+8(%r1); \ 126 stw %r15, FRAME_15+8(%r1); \ 127 stw %r16, FRAME_16+8(%r1); \ 128 stw %r17, FRAME_17+8(%r1); \ 129 stw %r18, FRAME_18+8(%r1); \ 130 stw %r19, FRAME_19+8(%r1); \ 131 stw %r20, FRAME_20+8(%r1); \ 132 stw %r21, FRAME_21+8(%r1); \ 133 stw %r22, FRAME_22+8(%r1); \ 134 stw %r23, FRAME_23+8(%r1); \ 135 stw %r24, FRAME_24+8(%r1); \ 136 stw %r25, FRAME_25+8(%r1); \ 137 stw %r26, FRAME_26+8(%r1); \ 138 stw %r27, FRAME_27+8(%r1); \ 139 stw %r28, FRAME_28+8(%r1); \ 140 stw %r29, FRAME_29+8(%r1); \ 141 stw %r30, FRAME_30+8(%r1); \ 142 stw %r31, FRAME_31+8(%r1); \ 143 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 144 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 145 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 146 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 147 mfxer %r3; \ 148 mfctr %r4; \ 149 mfsprg3 %r5; \ 150 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 151 stw %r4, FRAME_CTR+8(1); \ 152 stw %r5, FRAME_EXC+8(1); \ 153 stw %r28,FRAME_AIM_DAR+8(1); \ 154 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 155 stw %r30,FRAME_SRR0+8(1); \ 156 stw %r31,FRAME_SRR1+8(1) 157 158#define FRAME_LEAVE(savearea) \ 159/* Now restore regs: */ \ 160 lwz %r2,FRAME_SRR0+8(%r1); \ 161 lwz %r3,FRAME_SRR1+8(%r1); \ 162 lwz %r4,FRAME_CTR+8(%r1); \ 163 lwz %r5,FRAME_XER+8(%r1); \ 164 lwz %r6,FRAME_LR+8(%r1); \ 165 GET_CPUINFO(%r7); \ 166 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 167 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 168 lwz %r7,FRAME_CR+8(%r1); \ 169 mtctr %r4; \ 170 mtxer %r5; \ 171 mtlr %r6; \ 172 mtsprg1 %r7; /* save cr */ \ 173 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 174 lwz %r30,FRAME_30+8(%r1); \ 175 lwz %r29,FRAME_29+8(%r1); \ 176 lwz %r28,FRAME_28+8(%r1); \ 177 lwz %r27,FRAME_27+8(%r1); \ 178 lwz %r26,FRAME_26+8(%r1); \ 179 lwz %r25,FRAME_25+8(%r1); \ 180 lwz %r24,FRAME_24+8(%r1); \ 181 lwz %r23,FRAME_23+8(%r1); \ 182 lwz %r22,FRAME_22+8(%r1); \ 183 lwz %r21,FRAME_21+8(%r1); \ 184 lwz %r20,FRAME_20+8(%r1); \ 185 lwz %r19,FRAME_19+8(%r1); \ 186 lwz %r18,FRAME_18+8(%r1); \ 187 lwz %r17,FRAME_17+8(%r1); \ 188 lwz %r16,FRAME_16+8(%r1); \ 189 lwz %r15,FRAME_15+8(%r1); \ 190 lwz %r14,FRAME_14+8(%r1); \ 191 lwz %r13,FRAME_13+8(%r1); \ 192 lwz %r12,FRAME_12+8(%r1); \ 193 lwz %r11,FRAME_11+8(%r1); \ 194 lwz %r10,FRAME_10+8(%r1); \ 195 lwz %r9, FRAME_9+8(%r1); \ 196 lwz %r8, FRAME_8+8(%r1); \ 197 lwz %r7, FRAME_7+8(%r1); \ 198 lwz %r6, FRAME_6+8(%r1); \ 199 lwz %r5, FRAME_5+8(%r1); \ 200 lwz %r4, FRAME_4+8(%r1); \ 201 lwz %r3, FRAME_3+8(%r1); \ 202 lwz %r2, FRAME_2+8(%r1); \ 203 lwz %r0, FRAME_0+8(%r1); \ 204 lwz %r1, FRAME_1+8(%r1); \ 205/* Can't touch %r1 from here on */ \ 206 mtsprg2 %r2; /* save r2 & r3 */ \ 207 mtsprg3 %r3; \ 208/* Disable translation, machine check and recoverability: */ \ 209 mfmsr %r2; \ 210 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \ 211 mtmsr %r2; \ 212 isync; \ 213/* Decide whether we return to user mode: */ \ 214 GET_CPUINFO(%r2); \ 215 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 216 mtcr %r3; \ 217 bf 17,1f; /* branch if PSL_PR is false */ \ 218/* Restore user SRs */ \ 219 RESTORE_USER_SRS(%r2,%r3); \ 2201: mfsprg1 %r2; /* restore cr */ \ 221 mtcr %r2; \ 222 GET_CPUINFO(%r2); \ 223 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 224 mtsrr0 %r3; \ 225 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 226 \ 227 /* Make sure HV bit of MSR propagated to SRR1 */ \ 228 mfmsr %r2; \ 229 or %r3,%r2,%r3; \ 230 \ 231 mtsrr1 %r3; \ 232 mfsprg2 %r2; /* restore r2 & r3 */ \ 233 mfsprg3 %r3 234 235/* 236 * The next two routines are 64-bit glue code. The first is used to test if 237 * we are on a 64-bit system. By copying it to the illegal instruction 238 * handler, we can test for 64-bit mode by trying to execute a 64-bit 239 * instruction and seeing what happens. The second gets copied in front 240 * of all the other handlers to restore 32-bit bridge mode when traps 241 * are taken. 242 */ 243 244/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 245 246 .globl CNAME(testppc64),CNAME(testppc64size) 247CNAME(testppc64): 248 mtsprg1 %r31 249 mfsrr0 %r31 250 addi %r31, %r31, 4 251 mtsrr0 %r31 252 253 li %r31, 0 254 mtsprg2 %r31 255 mfsprg1 %r31 256 257 rfi 258CNAME(testppc64size) = .-CNAME(testppc64) 259 260 261/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 262 * on 64-bit systems. */ 263 264 .globl CNAME(restorebridge),CNAME(restorebridgesize) 265CNAME(restorebridge): 266 mtsprg1 %r31 267 mfmsr %r31 268 clrldi %r31,%r31,1 269 mtmsrd %r31 270 mfsprg1 %r31 271 isync 272CNAME(restorebridgesize) = .-CNAME(restorebridge) 273 274#ifdef SMP 275/* 276 * Processor reset exception handler. These are typically 277 * the first instructions the processor executes after a 278 * software reset. We do this in two bits so that we are 279 * not still hanging around in the trap handling region 280 * once the MMU is turned on. 281 */ 282 .globl CNAME(rstcode), CNAME(rstsize) 283CNAME(rstcode): 284 ba cpu_reset 285CNAME(rstsize) = . - CNAME(rstcode) 286 287cpu_reset: 288 bl 1f 289 290 .space 124 291 2921: 293 mflr %r1 294 addi %r1,%r1,(124-16)@l 295 296 lis %r3,1@l 297 bla CNAME(cpudep_ap_early_bootstrap) 298 bla CNAME(pmap_cpu_bootstrap) 299 bla CNAME(cpudep_ap_bootstrap) 300 mr %r1,%r3 301 bla CNAME(machdep_ap_bootstrap) 302 303 /* Should not be reached */ 3049: 305 b 9b 306#endif 307 308/* 309 * This code gets copied to all the trap vectors 310 * (except ISI/DSI, ALI, and the interrupts) 311 */ 312 313 .globl CNAME(trapcode),CNAME(trapsize) 314CNAME(trapcode): 315 mtsprg1 %r1 /* save SP */ 316 mflr %r1 /* Save the old LR in r1 */ 317 mtsprg2 %r1 /* And then in SPRG2 */ 318 li %r1, 0x20 /* How to get the vector from LR */ 319 bla generictrap /* LR & SPRG3 is exception # */ 320CNAME(trapsize) = .-CNAME(trapcode) 321 322/* 323 * 64-bit version of trapcode. Identical, except it calls generictrap64. 324 */ 325 .globl CNAME(trapcode64) 326CNAME(trapcode64): 327 mtsprg1 %r1 /* save SP */ 328 mflr %r1 /* Save the old LR in r1 */ 329 mtsprg2 %r1 /* And then in SPRG2 */ 330 li %r1, 0x20 /* How to get the vector from LR */ 331 bla generictrap64 /* LR & SPRG3 is exception # */ 332 333/* 334 * For ALI: has to save DSISR and DAR 335 */ 336 .globl CNAME(alitrap),CNAME(alisize) 337CNAME(alitrap): 338 mtsprg1 %r1 /* save SP */ 339 GET_CPUINFO(%r1) 340 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 341 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 342 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 343 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 344 mfdar %r30 345 mfdsisr %r31 346 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 347 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 348 mfsprg1 %r1 /* restore SP, in case of branch */ 349 mflr %r28 /* save LR */ 350 mfcr %r29 /* save CR */ 351 352 /* Put our exception vector in SPRG3 */ 353 li %r31, EXC_ALI 354 mtsprg3 %r31 355 356 /* Test whether we already had PR set */ 357 mfsrr1 %r31 358 mtcr %r31 359 bla s_trap 360CNAME(alisize) = .-CNAME(alitrap) 361 362/* 363 * Similar to the above for DSI 364 * Has to handle BAT spills 365 * and standard pagetable spills 366 */ 367 .globl CNAME(dsitrap),CNAME(dsisize) 368CNAME(dsitrap): 369 mtsprg1 %r1 /* save SP */ 370 GET_CPUINFO(%r1) 371 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 372 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 373 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 374 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 375 mfsprg1 %r1 /* restore SP */ 376 mfcr %r29 /* save CR */ 377 mfxer %r30 /* save XER */ 378 mtsprg2 %r30 /* in SPRG2 */ 379 mfsrr1 %r31 /* test kernel mode */ 380 mtcr %r31 381 bt 17,1f /* branch if PSL_PR is set */ 382 mfdar %r31 /* get fault address */ 383 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 384 385 /* get batu */ 386 addis %r31,%r31,CNAME(battable)@ha 387 lwz %r30,CNAME(battable)@l(31) 388 mtcr %r30 389 bf 30,1f /* branch if supervisor valid is 390 false */ 391 /* get batl */ 392 lwz %r31,CNAME(battable)+4@l(31) 393/* We randomly use the highest two bat registers here */ 394 mftb %r28 395 andi. %r28,%r28,1 396 bne 2f 397 mtdbatu 2,%r30 398 mtdbatl 2,%r31 399 b 3f 4002: 401 mtdbatu 3,%r30 402 mtdbatl 3,%r31 4033: 404 mfsprg2 %r30 /* restore XER */ 405 mtxer %r30 406 mtcr %r29 /* restore CR */ 407 mtsprg1 %r1 408 GET_CPUINFO(%r1) 409 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 410 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 411 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 412 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 413 mfsprg1 %r1 414 rfi /* return to trapped code */ 4151: 416 mflr %r28 /* save LR (SP already saved) */ 417 bla disitrap 418CNAME(dsisize) = .-CNAME(dsitrap) 419 420/* 421 * Preamble code for DSI/ISI traps 422 */ 423disitrap: 424 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 425 mflr %r1 426 andi. %r1,%r1,0xff00 427 mtsprg3 %r1 428 429 GET_CPUINFO(%r1) 430 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 431 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 432 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 433 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 434 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 435 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 436 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 437 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 438 mfdar %r30 439 mfdsisr %r31 440 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 441 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 442 443#ifdef KDB 444 /* Try and detect a kernel stack overflow */ 445 mfsrr1 %r31 446 mtcr %r31 447 bt 17,realtrap /* branch is user mode */ 448 mfsprg1 %r31 /* get old SP */ 449 sub. %r30,%r31,%r30 /* SP - DAR */ 450 bge 1f 451 neg %r30,%r30 /* modulo value */ 4521: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 453 bge %cr0,realtrap /* no, too far away. */ 454 455 /* Now convert this DSI into a DDB trap. */ 456 GET_CPUINFO(%r1) 457 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 458 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 459 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 460 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 461 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 462 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 463 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 464 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 465 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 466 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 467 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 468 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 469 b dbtrap 470#endif 471 472 /* XXX need stack probe here */ 473realtrap: 474/* Test whether we already had PR set */ 475 mfsrr1 %r1 476 mtcr %r1 477 mfsprg1 %r1 /* restore SP (might have been 478 overwritten) */ 479 bf 17,k_trap /* branch if PSL_PR is false */ 480 GET_CPUINFO(%r1) 481 lwz %r1,PC_CURPCB(%r1) 482 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 483 ba s_trap 484 485/* 486 * generictrap does some standard setup for trap handling to minimize 487 * the code that need be installed in the actual vectors. It expects 488 * the following conditions. 489 * 490 * R1 - Trap vector = LR & (0xff00 | R1) 491 * SPRG1 - Original R1 contents 492 * SPRG2 - Original LR 493 */ 494 495generictrap64: 496 mtsprg3 %r31 497 mfmsr %r31 498 clrldi %r31,%r31,1 499 mtmsrd %r31 500 mfsprg3 %r31 501 isync 502 503generictrap: 504 /* Save R1 for computing the exception vector */ 505 mtsprg3 %r1 506 507 /* Save interesting registers */ 508 GET_CPUINFO(%r1) 509 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 510 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 511 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 512 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 513 mfsprg1 %r1 /* restore SP, in case of branch */ 514 mfsprg2 %r28 /* save LR */ 515 mfcr %r29 /* save CR */ 516 517 /* Compute the exception vector from the link register */ 518 mfsprg3 %r31 519 ori %r31,%r31,0xff00 520 mflr %r30 521 and %r30,%r30,%r31 522 mtsprg3 %r30 523 524 /* Test whether we already had PR set */ 525 mfsrr1 %r31 526 mtcr %r31 527 528s_trap: 529 bf 17,k_trap /* branch if PSL_PR is false */ 530 GET_CPUINFO(%r1) 531u_trap: 532 lwz %r1,PC_CURPCB(%r1) 533 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 534 535/* 536 * Now the common trap catching code. 537 */ 538k_trap: 539 FRAME_SETUP(PC_TEMPSAVE) 540/* Call C interrupt dispatcher: */ 541trapagain: 542 addi %r3,%r1,8 543 bl CNAME(powerpc_interrupt) 544 .globl CNAME(trapexit) /* backtrace code sentinel */ 545CNAME(trapexit): 546 547/* Disable interrupts: */ 548 mfmsr %r3 549 andi. %r3,%r3,~PSL_EE@l 550 mtmsr %r3 551/* Test AST pending: */ 552 lwz %r5,FRAME_SRR1+8(%r1) 553 mtcr %r5 554 bf 17,1f /* branch if PSL_PR is false */ 555 556 GET_CPUINFO(%r3) /* get per-CPU pointer */ 557 lwz %r4, PC_CURTHREAD(%r3) /* deref to get curthread */ 558 lwz %r4, TD_FLAGS(%r4) /* get thread flags value */ 559 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 560 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 561 and. %r4,%r4,%r5 562 beq 1f 563 mfmsr %r3 /* re-enable interrupts */ 564 ori %r3,%r3,PSL_EE@l 565 mtmsr %r3 566 isync 567 addi %r3,%r1,8 568 bl CNAME(ast) 569 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 570CNAME(asttrapexit): 571 b trapexit /* test ast ret value ? */ 5721: 573 FRAME_LEAVE(PC_TEMPSAVE) 574 575 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 576CNAME(rfi_patch1): 577 rfi 578 579 .globl CNAME(rfid_patch) 580CNAME(rfid_patch): 581 rfid 582 583#if defined(KDB) 584/* 585 * Deliberate entry to dbtrap 586 */ 587 .globl CNAME(breakpoint) 588CNAME(breakpoint): 589 mtsprg1 %r1 590 mfmsr %r3 591 mtsrr1 %r3 592 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 593 mtmsr %r3 /* disable interrupts */ 594 isync 595 GET_CPUINFO(%r3) 596 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 597 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 598 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 599 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 600 mflr %r28 601 li %r29,EXC_BPT 602 mtlr %r29 603 mfcr %r29 604 mtsrr0 %r28 605 606/* 607 * Now the kdb trap catching code. 608 */ 609dbtrap: 610 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 611 mflr %r1 612 andi. %r1,%r1,0xff00 613 mtsprg3 %r1 614 615 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 616 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 617 618 FRAME_SETUP(PC_DBSAVE) 619/* Call C trap code: */ 620 addi %r3,%r1,8 621 bl CNAME(db_trap_glue) 622 or. %r3,%r3,%r3 623 bne dbleave 624/* This wasn't for KDB, so switch to real trap: */ 625 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 626 GET_CPUINFO(%r4) 627 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 628 FRAME_LEAVE(PC_DBSAVE) 629 mtsprg1 %r1 /* prepare for entrance to realtrap */ 630 GET_CPUINFO(%r1) 631 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 632 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 633 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 634 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 635 mflr %r28 636 mfcr %r29 637 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 638 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 639 mfsprg1 %r1 640 b realtrap 641dbleave: 642 FRAME_LEAVE(PC_DBSAVE) 643 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 644CNAME(rfi_patch2): 645 rfi 646 647/* 648 * In case of KDB we want a separate trap catcher for it 649 */ 650 .globl CNAME(dblow),CNAME(dbsize) 651CNAME(dblow): 652 mtsprg1 %r1 /* save SP */ 653 mtsprg2 %r29 /* save r29 */ 654 mfcr %r29 /* save CR in r29 */ 655 mfsrr1 %r1 656 mtcr %r1 657 bf 17,1f /* branch if privileged */ 658 659 /* Unprivileged case */ 660 mtcr %r29 /* put the condition register back */ 661 mfsprg2 %r29 /* ... and r29 */ 662 mflr %r1 /* save LR */ 663 mtsprg2 %r1 /* And then in SPRG2 */ 664 li %r1, 0 /* How to get the vector from LR */ 665 666 bla generictrap /* and we look like a generic trap */ 6671: 668 /* Privileged, so drop to KDB */ 669 GET_CPUINFO(%r1) 670 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 671 mfsprg2 %r28 /* r29 holds cr... */ 672 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 673 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 674 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 675 mflr %r28 /* save LR */ 676 bla dbtrap 677CNAME(dbsize) = .-CNAME(dblow) 678#endif /* KDB */ 679