1/* $FreeBSD$ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62/* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65#define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr 72 73/* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76#define RESTORE_KERN_SRS(pmap,sr) \ 77 lis pmap,CNAME(kernel_pmap_store)@ha; \ 78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 79 RESTORE_SRS(pmap,sr) 80 81/* 82 * FRAME_SETUP assumes: 83 * SPRG1 SP (1) 84 * SPRG3 trap type 85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 86 * r28 LR 87 * r29 CR 88 * r30 scratch 89 * r31 scratch 90 * r1 kernel stack 91 * SRR0/1 as at start of trap 92 */ 93#define FRAME_SETUP(savearea) \ 94/* Have to enable translation to allow access of kernel stack: */ \ 95 GET_CPUINFO(%r31); \ 96 mfsrr0 %r30; \ 97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 98 mfsrr1 %r30; \ 99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 100 mfmsr %r30; \ 101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 102 mtmsr %r30; /* stack can now be accessed */ \ 103 isync; \ 104 mfsprg1 %r31; /* get saved SP */ \ 105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 111 GET_CPUINFO(%r2); \ 112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 117 stw %r4, FRAME_4+8(%r1); \ 118 stw %r5, FRAME_5+8(%r1); \ 119 stw %r6, FRAME_6+8(%r1); \ 120 stw %r7, FRAME_7+8(%r1); \ 121 stw %r8, FRAME_8+8(%r1); \ 122 stw %r9, FRAME_9+8(%r1); \ 123 stw %r10, FRAME_10+8(%r1); \ 124 stw %r11, FRAME_11+8(%r1); \ 125 stw %r12, FRAME_12+8(%r1); \ 126 stw %r13, FRAME_13+8(%r1); \ 127 stw %r14, FRAME_14+8(%r1); \ 128 stw %r15, FRAME_15+8(%r1); \ 129 stw %r16, FRAME_16+8(%r1); \ 130 stw %r17, FRAME_17+8(%r1); \ 131 stw %r18, FRAME_18+8(%r1); \ 132 stw %r19, FRAME_19+8(%r1); \ 133 stw %r20, FRAME_20+8(%r1); \ 134 stw %r21, FRAME_21+8(%r1); \ 135 stw %r22, FRAME_22+8(%r1); \ 136 stw %r23, FRAME_23+8(%r1); \ 137 stw %r24, FRAME_24+8(%r1); \ 138 stw %r25, FRAME_25+8(%r1); \ 139 stw %r26, FRAME_26+8(%r1); \ 140 stw %r27, FRAME_27+8(%r1); \ 141 stw %r28, FRAME_28+8(%r1); \ 142 stw %r29, FRAME_29+8(%r1); \ 143 stw %r30, FRAME_30+8(%r1); \ 144 stw %r31, FRAME_31+8(%r1); \ 145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 149 mfxer %r3; \ 150 mfctr %r4; \ 151 mfsprg3 %r5; \ 152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 153 stw %r4, FRAME_CTR+8(1); \ 154 stw %r5, FRAME_EXC+8(1); \ 155 stw %r28,FRAME_AIM_DAR+8(1); \ 156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 157 stw %r30,FRAME_SRR0+8(1); \ 158 stw %r31,FRAME_SRR1+8(1) 159 160#define FRAME_LEAVE(savearea) \ 161/* Now restore regs: */ \ 162 lwz %r2,FRAME_SRR0+8(%r1); \ 163 lwz %r3,FRAME_SRR1+8(%r1); \ 164 lwz %r4,FRAME_CTR+8(%r1); \ 165 lwz %r5,FRAME_XER+8(%r1); \ 166 lwz %r6,FRAME_LR+8(%r1); \ 167 GET_CPUINFO(%r7); \ 168 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 169 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 170 lwz %r7,FRAME_CR+8(%r1); \ 171 mtctr %r4; \ 172 mtxer %r5; \ 173 mtlr %r6; \ 174 mtsprg1 %r7; /* save cr */ \ 175 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 176 lwz %r30,FRAME_30+8(%r1); \ 177 lwz %r29,FRAME_29+8(%r1); \ 178 lwz %r28,FRAME_28+8(%r1); \ 179 lwz %r27,FRAME_27+8(%r1); \ 180 lwz %r26,FRAME_26+8(%r1); \ 181 lwz %r25,FRAME_25+8(%r1); \ 182 lwz %r24,FRAME_24+8(%r1); \ 183 lwz %r23,FRAME_23+8(%r1); \ 184 lwz %r22,FRAME_22+8(%r1); \ 185 lwz %r21,FRAME_21+8(%r1); \ 186 lwz %r20,FRAME_20+8(%r1); \ 187 lwz %r19,FRAME_19+8(%r1); \ 188 lwz %r18,FRAME_18+8(%r1); \ 189 lwz %r17,FRAME_17+8(%r1); \ 190 lwz %r16,FRAME_16+8(%r1); \ 191 lwz %r15,FRAME_15+8(%r1); \ 192 lwz %r14,FRAME_14+8(%r1); \ 193 lwz %r13,FRAME_13+8(%r1); \ 194 lwz %r12,FRAME_12+8(%r1); \ 195 lwz %r11,FRAME_11+8(%r1); \ 196 lwz %r10,FRAME_10+8(%r1); \ 197 lwz %r9, FRAME_9+8(%r1); \ 198 lwz %r8, FRAME_8+8(%r1); \ 199 lwz %r7, FRAME_7+8(%r1); \ 200 lwz %r6, FRAME_6+8(%r1); \ 201 lwz %r5, FRAME_5+8(%r1); \ 202 lwz %r4, FRAME_4+8(%r1); \ 203 lwz %r3, FRAME_3+8(%r1); \ 204 lwz %r2, FRAME_2+8(%r1); \ 205 lwz %r0, FRAME_0+8(%r1); \ 206 lwz %r1, FRAME_1+8(%r1); \ 207/* Can't touch %r1 from here on */ \ 208 mtsprg2 %r2; /* save r2 & r3 */ \ 209 mtsprg3 %r3; \ 210/* Disable translation, machine check and recoverability: */ \ 211 mfmsr %r2; \ 212 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \ 213 mtmsr %r2; \ 214 isync; \ 215/* Decide whether we return to user mode: */ \ 216 GET_CPUINFO(%r2); \ 217 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 218 mtcr %r3; \ 219 bf 17,1f; /* branch if PSL_PR is false */ \ 220/* Restore user SRs */ \ 221 RESTORE_USER_SRS(%r2,%r3); \ 2221: mfsprg1 %r2; /* restore cr */ \ 223 mtcr %r2; \ 224 GET_CPUINFO(%r2); \ 225 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 226 mtsrr0 %r3; \ 227 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 228 \ 229 /* Make sure HV bit of MSR propagated to SRR1 */ \ 230 mfmsr %r2; \ 231 or %r3,%r2,%r3; \ 232 \ 233 mtsrr1 %r3; \ 234 mfsprg2 %r2; /* restore r2 & r3 */ \ 235 mfsprg3 %r3 236 237/* 238 * The next two routines are 64-bit glue code. The first is used to test if 239 * we are on a 64-bit system. By copying it to the illegal instruction 240 * handler, we can test for 64-bit mode by trying to execute a 64-bit 241 * instruction and seeing what happens. The second gets copied in front 242 * of all the other handlers to restore 32-bit bridge mode when traps 243 * are taken. 244 */ 245 246/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 247 248 .globl CNAME(testppc64),CNAME(testppc64size) 249CNAME(testppc64): 250 mtsprg1 %r31 251 mfsrr0 %r31 252 addi %r31, %r31, 4 253 mtsrr0 %r31 254 255 li %r31, 0 256 mtsprg2 %r31 257 mfsprg1 %r31 258 259 rfi 260CNAME(testppc64size) = .-CNAME(testppc64) 261 262 263/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 264 * on 64-bit systems. */ 265 266 .globl CNAME(restorebridge),CNAME(restorebridgesize) 267CNAME(restorebridge): 268 mtsprg1 %r31 269 mfmsr %r31 270 clrldi %r31,%r31,1 271 mtmsrd %r31 272 mfsprg1 %r31 273 isync 274CNAME(restorebridgesize) = .-CNAME(restorebridge) 275 276#ifdef SMP 277/* 278 * Processor reset exception handler. These are typically 279 * the first instructions the processor executes after a 280 * software reset. We do this in two bits so that we are 281 * not still hanging around in the trap handling region 282 * once the MMU is turned on. 283 */ 284 .globl CNAME(rstcode), CNAME(rstsize) 285CNAME(rstcode): 286 ba cpu_reset 287CNAME(rstsize) = . - CNAME(rstcode) 288 289cpu_reset: 290 bl 1f 291 292 .space 124 293 2941: 295 mflr %r1 296 addi %r1,%r1,(124-16)@l 297 298 lis %r3,1@l 299 bla CNAME(cpudep_ap_early_bootstrap) 300 bla CNAME(pmap_cpu_bootstrap) 301 bla CNAME(cpudep_ap_bootstrap) 302 mr %r1,%r3 303 bla CNAME(machdep_ap_bootstrap) 304 305 /* Should not be reached */ 3069: 307 b 9b 308#endif 309 310/* 311 * This code gets copied to all the trap vectors 312 * (except ISI/DSI, ALI, and the interrupts) 313 */ 314 315 .globl CNAME(trapcode),CNAME(trapsize) 316CNAME(trapcode): 317 mtsprg1 %r1 /* save SP */ 318 mflr %r1 /* Save the old LR in r1 */ 319 mtsprg2 %r1 /* And then in SPRG2 */ 320 li %r1, 0x20 /* How to get the vector from LR */ 321 bla generictrap /* LR & SPRG3 is exception # */ 322CNAME(trapsize) = .-CNAME(trapcode) 323 324/* 325 * 64-bit version of trapcode. Identical, except it calls generictrap64. 326 */ 327 .globl CNAME(trapcode64) 328CNAME(trapcode64): 329 mtsprg1 %r1 /* save SP */ 330 mflr %r1 /* Save the old LR in r1 */ 331 mtsprg2 %r1 /* And then in SPRG2 */ 332 li %r1, 0x20 /* How to get the vector from LR */ 333 bla generictrap64 /* LR & SPRG3 is exception # */ 334 335/* 336 * For ALI: has to save DSISR and DAR 337 */ 338 .globl CNAME(alitrap),CNAME(alisize) 339CNAME(alitrap): 340 mtsprg1 %r1 /* save SP */ 341 GET_CPUINFO(%r1) 342 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 343 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 344 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 345 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 346 mfdar %r30 347 mfdsisr %r31 348 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 349 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 350 mfsprg1 %r1 /* restore SP, in case of branch */ 351 mflr %r28 /* save LR */ 352 mfcr %r29 /* save CR */ 353 354 /* Put our exception vector in SPRG3 */ 355 li %r31, EXC_ALI 356 mtsprg3 %r31 357 358 /* Test whether we already had PR set */ 359 mfsrr1 %r31 360 mtcr %r31 361 bla s_trap 362CNAME(alisize) = .-CNAME(alitrap) 363 364/* 365 * G2 specific: instuction TLB miss. 366 */ 367 .globl CNAME(imisstrap),CNAME(imisssize) 368CNAME(imisstrap): 369 mfspr %r2, SPR_HASH1 /* get first pointer */ 370 addi %r1, 0, 8 /* load 8 for counter */ 371 mfctr %r0 /* save counter */ 372 mfspr %r3, SPR_ICMP /* get first compare value */ 373 addi %r2, %r2, -8 /* pre dec the pointer */ 374im0: 375 mtctr %r1 /* load counter */ 376im1: 377 lwzu %r1, 8(%r2) /* get next pte */ 378 cmp 0, %r1, %r3 /* see if found pte */ 379 bdnzf 2, im1 /* dec count br if cmp ne and if 380 * count not zero */ 381 bne instr_sec_hash /* if not found set up second hash 382 * or exit */ 383 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 384 andi. %r3, %r1, 8 /* check G bit */ 385 bne do_isi_prot /* if guarded, take an ISI */ 386 mtctr %r0 /* restore counter */ 387 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 388 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 389 mtcrf 0x80, %r3 /* restore CR0 */ 390 mtspr SPR_RPA, %r1 /* set the pte */ 391 ori %r1, %r1, 0x100 /* set reference bit */ 392 srwi %r1, %r1, 8 /* get byte 7 of pte */ 393 tlbli %r0 /* load the itlb */ 394 stb %r1, +6(%r2) /* update page table */ 395 rfi /* return to executing program */ 396 397instr_sec_hash: 398 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 399 bne do_isi /* if so, go to ISI interrupt */ 400 mfspr %r2, SPR_HASH2 /* get the second pointer */ 401 ori %r3, %r3, 0x0040 /* change the compare value */ 402 addi %r1, %r0, 8 /* load 8 for counter */ 403 addi %r2, %r2, -8 /* pre dec for update on load */ 404 b im0 /* try second hash */ 405 406/* Create a faked ISI interrupt as the address was not found */ 407do_isi_prot: 408 mfspr %r3, SPR_SRR1 /* get srr1 */ 409 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 410 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 411 * violation */ 412 b isi1 413do_isi: 414 mfspr %r3, SPR_SRR1 /* get srr1 */ 415 andi. %r2, %r3, 0xffff /* clean srr1 */ 416 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 417 * not found */ 418isi1: 419 mtctr %r0 /* restore counter */ 420 mtspr SPR_SRR1, %r2 /* set srr1 */ 421 mfmsr %r0 /* get msr */ 422 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 423 mtcrf 0x80, %r3 /* restore CR0 */ 424 mtmsr %r0 /* flip back to the native gprs */ 425 ba EXC_ISI /* go to instr. access interrupt */ 426 427CNAME(imisssize) = .-CNAME(imisstrap) 428 429/* 430 * G2 specific: data load TLB miss. 431 */ 432 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 433CNAME(dlmisstrap): 434 mfspr %r2, SPR_HASH1 /* get first pointer */ 435 addi %r1, 0, 8 /* load 8 for counter */ 436 mfctr %r0 /* save counter */ 437 mfspr %r3, SPR_DCMP /* get first compare value */ 438 addi %r2, %r2, -8 /* pre dec the pointer */ 439dm0: 440 mtctr %r1 /* load counter */ 441dm1: 442 lwzu %r1, 8(%r2) /* get next pte */ 443 cmp 0, 0, %r1, %r3 /* see if found pte */ 444 bdnzf 2, dm1 /* dec count br if cmp ne and if 445 * count not zero */ 446 bne data_sec_hash /* if not found set up second hash 447 * or exit */ 448 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 449 mtctr %r0 /* restore counter */ 450 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 451 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 452 mtcrf 0x80, %r3 /* restore CR0 */ 453 mtspr SPR_RPA, %r1 /* set the pte */ 454 ori %r1, %r1, 0x100 /* set reference bit */ 455 srwi %r1, %r1, 8 /* get byte 7 of pte */ 456 tlbld %r0 /* load the dtlb */ 457 stb %r1, +6(%r2) /* update page table */ 458 rfi /* return to executing program */ 459 460data_sec_hash: 461 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 462 bne do_dsi /* if so, go to DSI interrupt */ 463 mfspr %r2, SPR_HASH2 /* get the second pointer */ 464 ori %r3, %r3, 0x0040 /* change the compare value */ 465 addi %r1, 0, 8 /* load 8 for counter */ 466 addi %r2, %r2, -8 /* pre dec for update on load */ 467 b dm0 /* try second hash */ 468 469CNAME(dlmisssize) = .-CNAME(dlmisstrap) 470 471/* 472 * G2 specific: data store TLB miss. 473 */ 474 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 475CNAME(dsmisstrap): 476 mfspr %r2, SPR_HASH1 /* get first pointer */ 477 addi %r1, 0, 8 /* load 8 for counter */ 478 mfctr %r0 /* save counter */ 479 mfspr %r3, SPR_DCMP /* get first compare value */ 480 addi %r2, %r2, -8 /* pre dec the pointer */ 481ds0: 482 mtctr %r1 /* load counter */ 483ds1: 484 lwzu %r1, 8(%r2) /* get next pte */ 485 cmp 0, 0, %r1, %r3 /* see if found pte */ 486 bdnzf 2, ds1 /* dec count br if cmp ne and if 487 * count not zero */ 488 bne data_store_sec_hash /* if not found set up second hash 489 * or exit */ 490 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 491 andi. %r3, %r1, 0x80 /* check the C-bit */ 492 beq data_store_chk_prot /* if (C==0) 493 * go check protection modes */ 494ds2: 495 mtctr %r0 /* restore counter */ 496 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 497 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 498 mtcrf 0x80, %r3 /* restore CR0 */ 499 mtspr SPR_RPA, %r1 /* set the pte */ 500 tlbld %r0 /* load the dtlb */ 501 rfi /* return to executing program */ 502 503data_store_sec_hash: 504 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 505 bne do_dsi /* if so, go to DSI interrupt */ 506 mfspr %r2, SPR_HASH2 /* get the second pointer */ 507 ori %r3, %r3, 0x0040 /* change the compare value */ 508 addi %r1, 0, 8 /* load 8 for counter */ 509 addi %r2, %r2, -8 /* pre dec for update on load */ 510 b ds0 /* try second hash */ 511 512/* Check the protection before setting PTE(c-bit) */ 513data_store_chk_prot: 514 rlwinm. %r3,%r1,30,0,1 /* test PP */ 515 bge- chk0 /* if (PP == 00 or PP == 01) 516 * goto chk0: */ 517 andi. %r3, %r1, 1 /* test PP[0] */ 518 beq+ chk2 /* return if PP[0] == 0 */ 519 b do_dsi_prot /* else DSIp */ 520chk0: 521 mfspr %r3,SPR_SRR1 /* get old msr */ 522 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 523 beq chk2 /* if (KEY==0) goto chk2: */ 524 b do_dsi_prot /* else do_dsi_prot */ 525chk2: 526 ori %r1, %r1, 0x180 /* set reference and change bit */ 527 sth %r1, 6(%r2) /* update page table */ 528 b ds2 /* and back we go */ 529 530/* Create a faked DSI interrupt as the address was not found */ 531do_dsi: 532 mfspr %r3, SPR_SRR1 /* get srr1 */ 533 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 534 * load/store, zero rest */ 535 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 536 * not found */ 537 b dsi1 538 539do_dsi_prot: 540 mfspr %r3, SPR_SRR1 /* get srr1 */ 541 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 542 *load/store, zero rest */ 543 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 544 * violation */ 545 546dsi1: 547 mtctr %r0 /* restore counter */ 548 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 549 mtspr SPR_SRR1, %r2 /* set srr1 */ 550 mtspr SPR_DSISR, %r1 /* load the dsisr */ 551 mfspr %r1, SPR_DMISS /* get miss address */ 552 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 553 beq dsi2 /* if little endian then: */ 554 xor %r1, %r1, 0x07 /* de-mung the data address */ 555dsi2: 556 mtspr SPR_DAR, %r1 /* put in dar */ 557 mfmsr %r0 /* get msr */ 558 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 559 mtcrf 0x80, %r3 /* restore CR0 */ 560 mtmsr %r0 /* flip back to the native gprs */ 561 ba EXC_DSI /* branch to DSI interrupt */ 562 563CNAME(dsmisssize) = .-CNAME(dsmisstrap) 564 565/* 566 * Similar to the above for DSI 567 * Has to handle BAT spills 568 * and standard pagetable spills 569 */ 570 .globl CNAME(dsitrap),CNAME(dsisize) 571CNAME(dsitrap): 572 mtsprg1 %r1 /* save SP */ 573 GET_CPUINFO(%r1) 574 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 575 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 576 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 577 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 578 mfsprg1 %r1 /* restore SP */ 579 mfcr %r29 /* save CR */ 580 mfxer %r30 /* save XER */ 581 mtsprg2 %r30 /* in SPRG2 */ 582 mfsrr1 %r31 /* test kernel mode */ 583 mtcr %r31 584 bt 17,1f /* branch if PSL_PR is set */ 585 mfdar %r31 /* get fault address */ 586 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 587 588 /* get batu */ 589 addis %r31,%r31,CNAME(battable)@ha 590 lwz %r30,CNAME(battable)@l(31) 591 mtcr %r30 592 bf 30,1f /* branch if supervisor valid is 593 false */ 594 /* get batl */ 595 lwz %r31,CNAME(battable)+4@l(31) 596/* We randomly use the highest two bat registers here */ 597 mftb %r28 598 andi. %r28,%r28,1 599 bne 2f 600 mtdbatu 2,%r30 601 mtdbatl 2,%r31 602 b 3f 6032: 604 mtdbatu 3,%r30 605 mtdbatl 3,%r31 6063: 607 mfsprg2 %r30 /* restore XER */ 608 mtxer %r30 609 mtcr %r29 /* restore CR */ 610 mtsprg1 %r1 611 GET_CPUINFO(%r1) 612 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 613 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 614 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 615 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 616 mfsprg1 %r1 617 rfi /* return to trapped code */ 6181: 619 mflr %r28 /* save LR (SP already saved) */ 620 bla disitrap 621CNAME(dsisize) = .-CNAME(dsitrap) 622 623/* 624 * Preamble code for DSI/ISI traps 625 */ 626disitrap: 627 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 628 mflr %r1 629 andi. %r1,%r1,0xff00 630 mtsprg3 %r1 631 632 GET_CPUINFO(%r1) 633 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 634 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 635 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 636 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 637 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 638 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 639 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 640 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 641 mfdar %r30 642 mfdsisr %r31 643 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 644 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 645 646#ifdef KDB 647 /* Try and detect a kernel stack overflow */ 648 mfsrr1 %r31 649 mtcr %r31 650 bt 17,realtrap /* branch is user mode */ 651 mfsprg1 %r31 /* get old SP */ 652 sub. %r30,%r31,%r30 /* SP - DAR */ 653 bge 1f 654 neg %r30,%r30 /* modulo value */ 6551: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 656 bge %cr0,realtrap /* no, too far away. */ 657 658 /* Now convert this DSI into a DDB trap. */ 659 GET_CPUINFO(%r1) 660 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 661 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 662 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 663 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 664 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 665 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 666 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 667 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 668 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 669 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 670 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 671 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 672 b dbtrap 673#endif 674 675 /* XXX need stack probe here */ 676realtrap: 677/* Test whether we already had PR set */ 678 mfsrr1 %r1 679 mtcr %r1 680 mfsprg1 %r1 /* restore SP (might have been 681 overwritten) */ 682 bf 17,k_trap /* branch if PSL_PR is false */ 683 GET_CPUINFO(%r1) 684 lwz %r1,PC_CURPCB(%r1) 685 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 686 ba s_trap 687 688/* 689 * generictrap does some standard setup for trap handling to minimize 690 * the code that need be installed in the actual vectors. It expects 691 * the following conditions. 692 * 693 * R1 - Trap vector = LR & (0xff00 | R1) 694 * SPRG1 - Original R1 contents 695 * SPRG2 - Original LR 696 */ 697 698generictrap64: 699 mtsprg3 %r31 700 mfmsr %r31 701 clrldi %r31,%r31,1 702 mtmsrd %r31 703 mfsprg3 %r31 704 isync 705 706generictrap: 707 /* Save R1 for computing the exception vector */ 708 mtsprg3 %r1 709 710 /* Save interesting registers */ 711 GET_CPUINFO(%r1) 712 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 713 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 714 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 715 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 716 mfsprg1 %r1 /* restore SP, in case of branch */ 717 mfsprg2 %r28 /* save LR */ 718 mfcr %r29 /* save CR */ 719 720 /* Compute the exception vector from the link register */ 721 mfsprg3 %r31 722 ori %r31,%r31,0xff00 723 mflr %r30 724 and %r30,%r30,%r31 725 mtsprg3 %r30 726 727 /* Test whether we already had PR set */ 728 mfsrr1 %r31 729 mtcr %r31 730 731s_trap: 732 bf 17,k_trap /* branch if PSL_PR is false */ 733 GET_CPUINFO(%r1) 734u_trap: 735 lwz %r1,PC_CURPCB(%r1) 736 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 737 738/* 739 * Now the common trap catching code. 740 */ 741k_trap: 742 FRAME_SETUP(PC_TEMPSAVE) 743 /* Restore USER_SR */ 744 GET_CPUINFO(%r30) 745 lwz %r30,PC_CURPCB(%r30) 746 lwz %r30,PCB_AIM_USR_VSID(%r30) 747 mtsr USER_SR,%r30; sync; isync 748/* Call C interrupt dispatcher: */ 749trapagain: 750 addi %r3,%r1,8 751 bl CNAME(powerpc_interrupt) 752 .globl CNAME(trapexit) /* backtrace code sentinel */ 753CNAME(trapexit): 754 755/* Disable interrupts: */ 756 mfmsr %r3 757 andi. %r3,%r3,~PSL_EE@l 758 mtmsr %r3 759/* Test AST pending: */ 760 lwz %r5,FRAME_SRR1+8(%r1) 761 mtcr %r5 762 bf 17,1f /* branch if PSL_PR is false */ 763 764 GET_CPUINFO(%r3) /* get per-CPU pointer */ 765 lwz %r4, PC_CURTHREAD(%r3) /* deref to get curthread */ 766 lwz %r4, TD_FLAGS(%r4) /* get thread flags value */ 767 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 768 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 769 and. %r4,%r4,%r5 770 beq 1f 771 mfmsr %r3 /* re-enable interrupts */ 772 ori %r3,%r3,PSL_EE@l 773 mtmsr %r3 774 isync 775 addi %r3,%r1,8 776 bl CNAME(ast) 777 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 778CNAME(asttrapexit): 779 b trapexit /* test ast ret value ? */ 7801: 781 FRAME_LEAVE(PC_TEMPSAVE) 782 783 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 784CNAME(rfi_patch1): 785 rfi 786 787 .globl CNAME(rfid_patch) 788CNAME(rfid_patch): 789 rfid 790 791#if defined(KDB) 792/* 793 * Deliberate entry to dbtrap 794 */ 795 .globl CNAME(breakpoint) 796CNAME(breakpoint): 797 mtsprg1 %r1 798 mfmsr %r3 799 mtsrr1 %r3 800 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 801 mtmsr %r3 /* disable interrupts */ 802 isync 803 GET_CPUINFO(%r3) 804 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 805 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 806 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 807 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 808 mflr %r28 809 li %r29,EXC_BPT 810 mtlr %r29 811 mfcr %r29 812 mtsrr0 %r28 813 814/* 815 * Now the kdb trap catching code. 816 */ 817dbtrap: 818 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 819 mflr %r1 820 andi. %r1,%r1,0xff00 821 mtsprg3 %r1 822 823 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 824 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 825 826 FRAME_SETUP(PC_DBSAVE) 827/* Call C trap code: */ 828 addi %r3,%r1,8 829 bl CNAME(db_trap_glue) 830 or. %r3,%r3,%r3 831 bne dbleave 832/* This wasn't for KDB, so switch to real trap: */ 833 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 834 GET_CPUINFO(%r4) 835 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 836 FRAME_LEAVE(PC_DBSAVE) 837 mtsprg1 %r1 /* prepare for entrance to realtrap */ 838 GET_CPUINFO(%r1) 839 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 840 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 841 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 842 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 843 mflr %r28 844 mfcr %r29 845 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 846 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 847 mfsprg1 %r1 848 b realtrap 849dbleave: 850 FRAME_LEAVE(PC_DBSAVE) 851 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 852CNAME(rfi_patch2): 853 rfi 854 855/* 856 * In case of KDB we want a separate trap catcher for it 857 */ 858 .globl CNAME(dblow),CNAME(dbsize) 859CNAME(dblow): 860 mtsprg1 %r1 /* save SP */ 861 mtsprg2 %r29 /* save r29 */ 862 mfcr %r29 /* save CR in r29 */ 863 mfsrr1 %r1 864 mtcr %r1 865 bf 17,1f /* branch if privileged */ 866 867 /* Unprivileged case */ 868 mtcr %r29 /* put the condition register back */ 869 mfsprg2 %r29 /* ... and r29 */ 870 mflr %r1 /* save LR */ 871 mtsprg2 %r1 /* And then in SPRG2 */ 872 li %r1, 0 /* How to get the vector from LR */ 873 874 bla generictrap /* and we look like a generic trap */ 8751: 876 /* Privileged, so drop to KDB */ 877 GET_CPUINFO(%r1) 878 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 879 mfsprg2 %r28 /* r29 holds cr... */ 880 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 881 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 882 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 883 mflr %r28 /* save LR */ 884 bla dbtrap 885CNAME(dbsize) = .-CNAME(dblow) 886#endif /* KDB */ 887