1/* $FreeBSD$ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \ 46 lwz sr,1*4(pmap); mtsr 1,sr; \ 47 lwz sr,2*4(pmap); mtsr 2,sr; \ 48 lwz sr,3*4(pmap); mtsr 3,sr; \ 49 lwz sr,4*4(pmap); mtsr 4,sr; \ 50 lwz sr,5*4(pmap); mtsr 5,sr; \ 51 lwz sr,6*4(pmap); mtsr 6,sr; \ 52 lwz sr,7*4(pmap); mtsr 7,sr; \ 53 lwz sr,8*4(pmap); mtsr 8,sr; \ 54 lwz sr,9*4(pmap); mtsr 9,sr; \ 55 lwz sr,10*4(pmap); mtsr 10,sr; \ 56 lwz sr,11*4(pmap); mtsr 11,sr; \ 57 /* Skip segment 12 (USER_SR), which is restored differently */ \ 58 lwz sr,13*4(pmap); mtsr 13,sr; \ 59 lwz sr,14*4(pmap); mtsr 14,sr; \ 60 lwz sr,15*4(pmap); mtsr 15,sr; isync; 61 62/* 63 * User SRs are loaded through a pointer to the current pmap. 64 */ 65#define RESTORE_USER_SRS(pmap,sr) \ 66 GET_CPUINFO(pmap); \ 67 lwz pmap,PC_CURPMAP(pmap); \ 68 lwzu sr,PM_SR(pmap); \ 69 RESTORE_SRS(pmap,sr) \ 70 /* Restore SR 12 */ \ 71 lwz sr,12*4(pmap); mtsr 12,sr 72 73/* 74 * Kernel SRs are loaded directly from kernel_pmap_ 75 */ 76#define RESTORE_KERN_SRS(pmap,sr) \ 77 lis pmap,CNAME(kernel_pmap_store)@ha; \ 78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \ 79 RESTORE_SRS(pmap,sr) 80 81/* 82 * FRAME_SETUP assumes: 83 * SPRG1 SP (1) 84 * SPRG3 trap type 85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 86 * r28 LR 87 * r29 CR 88 * r30 scratch 89 * r31 scratch 90 * r1 kernel stack 91 * SRR0/1 as at start of trap 92 */ 93#define FRAME_SETUP(savearea) \ 94/* Have to enable translation to allow access of kernel stack: */ \ 95 GET_CPUINFO(%r31); \ 96 mfsrr0 %r30; \ 97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 98 mfsrr1 %r30; \ 99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 100 mfmsr %r30; \ 101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 102 mtmsr %r30; /* stack can now be accessed */ \ 103 isync; \ 104 mfsprg1 %r31; /* get saved SP */ \ 105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \ 106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \ 108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \ 110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \ 111 GET_CPUINFO(%r2); \ 112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \ 117 stw %r4, FRAME_4+8(%r1); \ 118 stw %r5, FRAME_5+8(%r1); \ 119 stw %r6, FRAME_6+8(%r1); \ 120 stw %r7, FRAME_7+8(%r1); \ 121 stw %r8, FRAME_8+8(%r1); \ 122 stw %r9, FRAME_9+8(%r1); \ 123 stw %r10, FRAME_10+8(%r1); \ 124 stw %r11, FRAME_11+8(%r1); \ 125 stw %r12, FRAME_12+8(%r1); \ 126 stw %r13, FRAME_13+8(%r1); \ 127 stw %r14, FRAME_14+8(%r1); \ 128 stw %r15, FRAME_15+8(%r1); \ 129 stw %r16, FRAME_16+8(%r1); \ 130 stw %r17, FRAME_17+8(%r1); \ 131 stw %r18, FRAME_18+8(%r1); \ 132 stw %r19, FRAME_19+8(%r1); \ 133 stw %r20, FRAME_20+8(%r1); \ 134 stw %r21, FRAME_21+8(%r1); \ 135 stw %r22, FRAME_22+8(%r1); \ 136 stw %r23, FRAME_23+8(%r1); \ 137 stw %r24, FRAME_24+8(%r1); \ 138 stw %r25, FRAME_25+8(%r1); \ 139 stw %r26, FRAME_26+8(%r1); \ 140 stw %r27, FRAME_27+8(%r1); \ 141 stw %r28, FRAME_28+8(%r1); \ 142 stw %r29, FRAME_29+8(%r1); \ 143 stw %r30, FRAME_30+8(%r1); \ 144 stw %r31, FRAME_31+8(%r1); \ 145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 149 mfxer %r3; \ 150 mfctr %r4; \ 151 mfsprg3 %r5; \ 152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \ 153 stw %r4, FRAME_CTR+8(1); \ 154 stw %r5, FRAME_EXC+8(1); \ 155 stw %r28,FRAME_AIM_DAR+8(1); \ 156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \ 157 stw %r30,FRAME_SRR0+8(1); \ 158 stw %r31,FRAME_SRR1+8(1); \ 159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */ 160 161#define FRAME_LEAVE(savearea) \ 162/* Disable exceptions: */ \ 163 mfmsr %r2; \ 164 andi. %r2,%r2,~PSL_EE@l; \ 165 mtmsr %r2; \ 166 isync; \ 167/* Now restore regs: */ \ 168 lwz %r2,FRAME_SRR0+8(%r1); \ 169 lwz %r3,FRAME_SRR1+8(%r1); \ 170 lwz %r4,FRAME_CTR+8(%r1); \ 171 lwz %r5,FRAME_XER+8(%r1); \ 172 lwz %r6,FRAME_LR+8(%r1); \ 173 GET_CPUINFO(%r7); \ 174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 176 lwz %r7,FRAME_CR+8(%r1); \ 177 mtctr %r4; \ 178 mtxer %r5; \ 179 mtlr %r6; \ 180 mtsprg1 %r7; /* save cr */ \ 181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \ 182 lwz %r30,FRAME_30+8(%r1); \ 183 lwz %r29,FRAME_29+8(%r1); \ 184 lwz %r28,FRAME_28+8(%r1); \ 185 lwz %r27,FRAME_27+8(%r1); \ 186 lwz %r26,FRAME_26+8(%r1); \ 187 lwz %r25,FRAME_25+8(%r1); \ 188 lwz %r24,FRAME_24+8(%r1); \ 189 lwz %r23,FRAME_23+8(%r1); \ 190 lwz %r22,FRAME_22+8(%r1); \ 191 lwz %r21,FRAME_21+8(%r1); \ 192 lwz %r20,FRAME_20+8(%r1); \ 193 lwz %r19,FRAME_19+8(%r1); \ 194 lwz %r18,FRAME_18+8(%r1); \ 195 lwz %r17,FRAME_17+8(%r1); \ 196 lwz %r16,FRAME_16+8(%r1); \ 197 lwz %r15,FRAME_15+8(%r1); \ 198 lwz %r14,FRAME_14+8(%r1); \ 199 lwz %r13,FRAME_13+8(%r1); \ 200 lwz %r12,FRAME_12+8(%r1); \ 201 lwz %r11,FRAME_11+8(%r1); \ 202 lwz %r10,FRAME_10+8(%r1); \ 203 lwz %r9, FRAME_9+8(%r1); \ 204 lwz %r8, FRAME_8+8(%r1); \ 205 lwz %r7, FRAME_7+8(%r1); \ 206 lwz %r6, FRAME_6+8(%r1); \ 207 lwz %r5, FRAME_5+8(%r1); \ 208 lwz %r4, FRAME_4+8(%r1); \ 209 lwz %r3, FRAME_3+8(%r1); \ 210 lwz %r2, FRAME_2+8(%r1); \ 211 lwz %r0, FRAME_0+8(%r1); \ 212 lwz %r1, FRAME_1+8(%r1); \ 213/* Can't touch %r1 from here on */ \ 214 mtsprg2 %r2; /* save r2 & r3 */ \ 215 mtsprg3 %r3; \ 216/* Disable translation, machine check and recoverability: */ \ 217 mfmsr %r2; \ 218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 219 mtmsr %r2; \ 220 isync; \ 221/* Decide whether we return to user mode: */ \ 222 GET_CPUINFO(%r2); \ 223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 224 mtcr %r3; \ 225 bf 17,1f; /* branch if PSL_PR is false */ \ 226/* Restore user SRs */ \ 227 RESTORE_USER_SRS(%r2,%r3); \ 2281: mfsprg1 %r2; /* restore cr */ \ 229 mtcr %r2; \ 230 GET_CPUINFO(%r2); \ 231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 232 mtsrr0 %r3; \ 233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 234 \ 235 /* Make sure HV bit of MSR propagated to SRR1 */ \ 236 mfmsr %r2; \ 237 or %r3,%r2,%r3; \ 238 \ 239 mtsrr1 %r3; \ 240 mfsprg2 %r2; /* restore r2 & r3 */ \ 241 mfsprg3 %r3 242 243/* 244 * The next two routines are 64-bit glue code. The first is used to test if 245 * we are on a 64-bit system. By copying it to the illegal instruction 246 * handler, we can test for 64-bit mode by trying to execute a 64-bit 247 * instruction and seeing what happens. The second gets copied in front 248 * of all the other handlers to restore 32-bit bridge mode when traps 249 * are taken. 250 */ 251 252/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */ 253 254 .globl CNAME(testppc64),CNAME(testppc64size) 255CNAME(testppc64): 256 mtsprg1 %r31 257 mfsrr0 %r31 258 addi %r31, %r31, 4 259 mtsrr0 %r31 260 261 li %r31, 0 262 mtsprg2 %r31 263 mfsprg1 %r31 264 265 rfi 266CNAME(testppc64size) = .-CNAME(testppc64) 267 268 269/* 64-bit bridge mode restore snippet. Gets copied in front of everything else 270 * on 64-bit systems. */ 271 272 .globl CNAME(restorebridge),CNAME(restorebridgesize) 273CNAME(restorebridge): 274 mtsprg1 %r31 275 mfmsr %r31 276 clrldi %r31,%r31,1 277 mtmsrd %r31 278 mfsprg1 %r31 279 isync 280CNAME(restorebridgesize) = .-CNAME(restorebridge) 281 282#ifdef SMP 283/* 284 * Processor reset exception handler. These are typically 285 * the first instructions the processor executes after a 286 * software reset. We do this in two bits so that we are 287 * not still hanging around in the trap handling region 288 * once the MMU is turned on. 289 */ 290 .globl CNAME(rstcode), CNAME(rstsize) 291CNAME(rstcode): 292 ba cpu_reset 293CNAME(rstsize) = . - CNAME(rstcode) 294 295cpu_reset: 296 bl 1f 297 298 .space 124 299 3001: 301 mflr %r1 302 addi %r1,%r1,(124-16)@l 303 304 lis %r3,1@l 305 bla CNAME(cpudep_ap_early_bootstrap) 306 lis %r3,1@l 307 bla CNAME(pmap_cpu_bootstrap) 308 bla CNAME(cpudep_ap_bootstrap) 309 mr %r1,%r3 310 bla CNAME(machdep_ap_bootstrap) 311 312 /* Should not be reached */ 3139: 314 b 9b 315#endif 316 317/* 318 * This code gets copied to all the trap vectors 319 * (except ISI/DSI, ALI, and the interrupts) 320 */ 321 322 .globl CNAME(trapcode),CNAME(trapsize) 323CNAME(trapcode): 324 mtsprg1 %r1 /* save SP */ 325 mflr %r1 /* Save the old LR in r1 */ 326 mtsprg2 %r1 /* And then in SPRG2 */ 327 li %r1, 0x20 /* How to get the vector from LR */ 328 bla generictrap /* LR & SPRG3 is exception # */ 329CNAME(trapsize) = .-CNAME(trapcode) 330 331/* 332 * 64-bit version of trapcode. Identical, except it calls generictrap64. 333 */ 334 .globl CNAME(trapcode64) 335CNAME(trapcode64): 336 mtsprg1 %r1 /* save SP */ 337 mflr %r1 /* Save the old LR in r1 */ 338 mtsprg2 %r1 /* And then in SPRG2 */ 339 li %r1, 0x20 /* How to get the vector from LR */ 340 bla generictrap64 /* LR & SPRG3 is exception # */ 341 342/* 343 * For ALI: has to save DSISR and DAR 344 */ 345 .globl CNAME(alitrap),CNAME(alisize) 346CNAME(alitrap): 347 mtsprg1 %r1 /* save SP */ 348 GET_CPUINFO(%r1) 349 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 350 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 351 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 352 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 353 mfdar %r30 354 mfdsisr %r31 355 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 356 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 357 mfsprg1 %r1 /* restore SP, in case of branch */ 358 mflr %r28 /* save LR */ 359 mfcr %r29 /* save CR */ 360 361 /* Put our exception vector in SPRG3 */ 362 li %r31, EXC_ALI 363 mtsprg3 %r31 364 365 /* Test whether we already had PR set */ 366 mfsrr1 %r31 367 mtcr %r31 368 bla s_trap 369CNAME(alisize) = .-CNAME(alitrap) 370 371/* 372 * G2 specific: instuction TLB miss. 373 */ 374 .globl CNAME(imisstrap),CNAME(imisssize) 375CNAME(imisstrap): 376 mfspr %r2, SPR_HASH1 /* get first pointer */ 377 addi %r1, 0, 8 /* load 8 for counter */ 378 mfctr %r0 /* save counter */ 379 mfspr %r3, SPR_ICMP /* get first compare value */ 380 addi %r2, %r2, -8 /* pre dec the pointer */ 381im0: 382 mtctr %r1 /* load counter */ 383im1: 384 lwzu %r1, 8(%r2) /* get next pte */ 385 cmp 0, %r1, %r3 /* see if found pte */ 386 bdnzf 2, im1 /* dec count br if cmp ne and if 387 * count not zero */ 388 bne instr_sec_hash /* if not found set up second hash 389 * or exit */ 390 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 391 andi. %r3, %r1, 8 /* check G bit */ 392 bne do_isi_prot /* if guarded, take an ISI */ 393 mtctr %r0 /* restore counter */ 394 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ 395 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 396 mtcrf 0x80, %r3 /* restore CR0 */ 397 mtspr SPR_RPA, %r1 /* set the pte */ 398 ori %r1, %r1, 0x100 /* set reference bit */ 399 srwi %r1, %r1, 8 /* get byte 7 of pte */ 400 tlbli %r0 /* load the itlb */ 401 stb %r1, +6(%r2) /* update page table */ 402 rfi /* return to executing program */ 403 404instr_sec_hash: 405 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 406 bne do_isi /* if so, go to ISI interrupt */ 407 mfspr %r2, SPR_HASH2 /* get the second pointer */ 408 ori %r3, %r3, 0x0040 /* change the compare value */ 409 addi %r1, %r0, 8 /* load 8 for counter */ 410 addi %r2, %r2, -8 /* pre dec for update on load */ 411 b im0 /* try second hash */ 412 413/* Create a faked ISI interrupt as the address was not found */ 414do_isi_prot: 415 mfspr %r3, SPR_SRR1 /* get srr1 */ 416 andi. %r2, %r3, 0xffff /* clean upper srr1 */ 417 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot 418 * violation */ 419 b isi1 420do_isi: 421 mfspr %r3, SPR_SRR1 /* get srr1 */ 422 andi. %r2, %r3, 0xffff /* clean srr1 */ 423 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte 424 * not found */ 425isi1: 426 mtctr %r0 /* restore counter */ 427 mtspr SPR_SRR1, %r2 /* set srr1 */ 428 mfmsr %r0 /* get msr */ 429 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 430 mtcrf 0x80, %r3 /* restore CR0 */ 431 mtmsr %r0 /* flip back to the native gprs */ 432 ba EXC_ISI /* go to instr. access interrupt */ 433 434CNAME(imisssize) = .-CNAME(imisstrap) 435 436/* 437 * G2 specific: data load TLB miss. 438 */ 439 .globl CNAME(dlmisstrap),CNAME(dlmisssize) 440CNAME(dlmisstrap): 441 mfspr %r2, SPR_HASH1 /* get first pointer */ 442 addi %r1, 0, 8 /* load 8 for counter */ 443 mfctr %r0 /* save counter */ 444 mfspr %r3, SPR_DCMP /* get first compare value */ 445 addi %r2, %r2, -8 /* pre dec the pointer */ 446dm0: 447 mtctr %r1 /* load counter */ 448dm1: 449 lwzu %r1, 8(%r2) /* get next pte */ 450 cmp 0, 0, %r1, %r3 /* see if found pte */ 451 bdnzf 2, dm1 /* dec count br if cmp ne and if 452 * count not zero */ 453 bne data_sec_hash /* if not found set up second hash 454 * or exit */ 455 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 456 mtctr %r0 /* restore counter */ 457 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 458 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 459 mtcrf 0x80, %r3 /* restore CR0 */ 460 mtspr SPR_RPA, %r1 /* set the pte */ 461 ori %r1, %r1, 0x100 /* set reference bit */ 462 srwi %r1, %r1, 8 /* get byte 7 of pte */ 463 tlbld %r0 /* load the dtlb */ 464 stb %r1, +6(%r2) /* update page table */ 465 rfi /* return to executing program */ 466 467data_sec_hash: 468 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 469 bne do_dsi /* if so, go to DSI interrupt */ 470 mfspr %r2, SPR_HASH2 /* get the second pointer */ 471 ori %r3, %r3, 0x0040 /* change the compare value */ 472 addi %r1, 0, 8 /* load 8 for counter */ 473 addi %r2, %r2, -8 /* pre dec for update on load */ 474 b dm0 /* try second hash */ 475 476CNAME(dlmisssize) = .-CNAME(dlmisstrap) 477 478/* 479 * G2 specific: data store TLB miss. 480 */ 481 .globl CNAME(dsmisstrap),CNAME(dsmisssize) 482CNAME(dsmisstrap): 483 mfspr %r2, SPR_HASH1 /* get first pointer */ 484 addi %r1, 0, 8 /* load 8 for counter */ 485 mfctr %r0 /* save counter */ 486 mfspr %r3, SPR_DCMP /* get first compare value */ 487 addi %r2, %r2, -8 /* pre dec the pointer */ 488ds0: 489 mtctr %r1 /* load counter */ 490ds1: 491 lwzu %r1, 8(%r2) /* get next pte */ 492 cmp 0, 0, %r1, %r3 /* see if found pte */ 493 bdnzf 2, ds1 /* dec count br if cmp ne and if 494 * count not zero */ 495 bne data_store_sec_hash /* if not found set up second hash 496 * or exit */ 497 lwz %r1, +4(%r2) /* load tlb entry lower-word */ 498 andi. %r3, %r1, 0x80 /* check the C-bit */ 499 beq data_store_chk_prot /* if (C==0) 500 * go check protection modes */ 501ds2: 502 mtctr %r0 /* restore counter */ 503 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ 504 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ 505 mtcrf 0x80, %r3 /* restore CR0 */ 506 mtspr SPR_RPA, %r1 /* set the pte */ 507 tlbld %r0 /* load the dtlb */ 508 rfi /* return to executing program */ 509 510data_store_sec_hash: 511 andi. %r1, %r3, 0x0040 /* see if we have done second hash */ 512 bne do_dsi /* if so, go to DSI interrupt */ 513 mfspr %r2, SPR_HASH2 /* get the second pointer */ 514 ori %r3, %r3, 0x0040 /* change the compare value */ 515 addi %r1, 0, 8 /* load 8 for counter */ 516 addi %r2, %r2, -8 /* pre dec for update on load */ 517 b ds0 /* try second hash */ 518 519/* Check the protection before setting PTE(c-bit) */ 520data_store_chk_prot: 521 rlwinm. %r3,%r1,30,0,1 /* test PP */ 522 bge- chk0 /* if (PP == 00 or PP == 01) 523 * goto chk0: */ 524 andi. %r3, %r1, 1 /* test PP[0] */ 525 beq+ chk2 /* return if PP[0] == 0 */ 526 b do_dsi_prot /* else DSIp */ 527chk0: 528 mfspr %r3,SPR_SRR1 /* get old msr */ 529 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ 530 beq chk2 /* if (KEY==0) goto chk2: */ 531 b do_dsi_prot /* else do_dsi_prot */ 532chk2: 533 ori %r1, %r1, 0x180 /* set reference and change bit */ 534 sth %r1, 6(%r2) /* update page table */ 535 b ds2 /* and back we go */ 536 537/* Create a faked DSI interrupt as the address was not found */ 538do_dsi: 539 mfspr %r3, SPR_SRR1 /* get srr1 */ 540 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 541 * load/store, zero rest */ 542 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte 543 * not found */ 544 b dsi1 545 546do_dsi_prot: 547 mfspr %r3, SPR_SRR1 /* get srr1 */ 548 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for 549 *load/store, zero rest */ 550 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot 551 * violation */ 552 553dsi1: 554 mtctr %r0 /* restore counter */ 555 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ 556 mtspr SPR_SRR1, %r2 /* set srr1 */ 557 mtspr SPR_DSISR, %r1 /* load the dsisr */ 558 mfspr %r1, SPR_DMISS /* get miss address */ 559 rlwinm. %r2,%r2,0,31,31 /* test LE bit */ 560 beq dsi2 /* if little endian then: */ 561 xor %r1, %r1, 0x07 /* de-mung the data address */ 562dsi2: 563 mtspr SPR_DAR, %r1 /* put in dar */ 564 mfmsr %r0 /* get msr */ 565 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ 566 mtcrf 0x80, %r3 /* restore CR0 */ 567 mtmsr %r0 /* flip back to the native gprs */ 568 ba EXC_DSI /* branch to DSI interrupt */ 569 570CNAME(dsmisssize) = .-CNAME(dsmisstrap) 571 572/* 573 * Similar to the above for DSI 574 * Has to handle BAT spills 575 * and standard pagetable spills 576 */ 577 .globl CNAME(dsitrap),CNAME(dsisize) 578CNAME(dsitrap): 579 mtsprg1 %r1 /* save SP */ 580 GET_CPUINFO(%r1) 581 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 582 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 583 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 584 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 585 mfsprg1 %r1 /* restore SP */ 586 mfcr %r29 /* save CR */ 587 mfxer %r30 /* save XER */ 588 mtsprg2 %r30 /* in SPRG2 */ 589 mfsrr1 %r31 /* test kernel mode */ 590 mtcr %r31 591 bt 17,1f /* branch if PSL_PR is set */ 592 mfdar %r31 /* get fault address */ 593 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */ 594 595 /* get batu */ 596 addis %r31,%r31,CNAME(battable)@ha 597 lwz %r30,CNAME(battable)@l(31) 598 mtcr %r30 599 bf 30,1f /* branch if supervisor valid is 600 false */ 601 /* get batl */ 602 lwz %r31,CNAME(battable)+4@l(31) 603/* We randomly use the highest two bat registers here */ 604 mftb %r28 605 andi. %r28,%r28,1 606 bne 2f 607 mtdbatu 2,%r30 608 mtdbatl 2,%r31 609 b 3f 6102: 611 mtdbatu 3,%r30 612 mtdbatl 3,%r31 6133: 614 mfsprg2 %r30 /* restore XER */ 615 mtxer %r30 616 mtcr %r29 /* restore CR */ 617 mtsprg1 %r1 618 GET_CPUINFO(%r1) 619 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */ 620 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 621 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 622 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 623 mfsprg1 %r1 624 rfi /* return to trapped code */ 6251: 626 mflr %r28 /* save LR (SP already saved) */ 627 bla disitrap 628CNAME(dsisize) = .-CNAME(dsitrap) 629 630/* 631 * Preamble code for DSI/ISI traps 632 */ 633disitrap: 634 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 635 mflr %r1 636 andi. %r1,%r1,0xff00 637 mtsprg3 %r1 638 639 GET_CPUINFO(%r1) 640 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 641 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 642 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 643 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 644 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 645 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 646 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 647 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 648 mfdar %r30 649 mfdsisr %r31 650 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 651 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 652 653#ifdef KDB 654 /* Try and detect a kernel stack overflow */ 655 mfsrr1 %r31 656 mtcr %r31 657 bt 17,realtrap /* branch is user mode */ 658 mfsprg1 %r31 /* get old SP */ 659 sub. %r30,%r31,%r30 /* SP - DAR */ 660 bge 1f 661 neg %r30,%r30 /* modulo value */ 6621: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */ 663 bge %cr0,realtrap /* no, too far away. */ 664 665 /* Now convert this DSI into a DDB trap. */ 666 GET_CPUINFO(%r1) 667 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 668 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 669 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 670 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 671 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 672 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 673 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 674 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 675 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 676 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 677 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 678 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 679 b dbtrap 680#endif 681 682 /* XXX need stack probe here */ 683realtrap: 684/* Test whether we already had PR set */ 685 mfsrr1 %r1 686 mtcr %r1 687 mfsprg1 %r1 /* restore SP (might have been 688 overwritten) */ 689 bf 17,k_trap /* branch if PSL_PR is false */ 690 GET_CPUINFO(%r1) 691 lwz %r1,PC_CURPCB(%r1) 692 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 693 ba s_trap 694 695/* 696 * generictrap does some standard setup for trap handling to minimize 697 * the code that need be installed in the actual vectors. It expects 698 * the following conditions. 699 * 700 * R1 - Trap vector = LR & (0xff00 | R1) 701 * SPRG1 - Original R1 contents 702 * SPRG2 - Original LR 703 */ 704 705generictrap64: 706 mtsprg3 %r31 707 mfmsr %r31 708 clrldi %r31,%r31,1 709 mtmsrd %r31 710 mfsprg3 %r31 711 isync 712 713generictrap: 714 /* Save R1 for computing the exception vector */ 715 mtsprg3 %r1 716 717 /* Save interesting registers */ 718 GET_CPUINFO(%r1) 719 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */ 720 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 721 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 722 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 723 mfsprg1 %r1 /* restore SP, in case of branch */ 724 mfsprg2 %r28 /* save LR */ 725 mfcr %r29 /* save CR */ 726 727 /* Compute the exception vector from the link register */ 728 mfsprg3 %r31 729 ori %r31,%r31,0xff00 730 mflr %r30 731 and %r30,%r30,%r31 732 mtsprg3 %r30 733 734 /* Test whether we already had PR set */ 735 mfsrr1 %r31 736 mtcr %r31 737 738s_trap: 739 bf 17,k_trap /* branch if PSL_PR is false */ 740 GET_CPUINFO(%r1) 741u_trap: 742 lwz %r1,PC_CURPCB(%r1) 743 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */ 744 745/* 746 * Now the common trap catching code. 747 */ 748k_trap: 749 FRAME_SETUP(PC_TEMPSAVE) 750 /* Restore USER_SR */ 751 GET_CPUINFO(%r30) 752 lwz %r30,PC_CURPCB(%r30) 753 lwz %r30,PCB_AIM_USR_VSID(%r30) 754 mtsr USER_SR,%r30; sync; isync 755/* Call C interrupt dispatcher: */ 756trapagain: 757 addi %r3,%r1,8 758 bl CNAME(powerpc_interrupt) 759 .globl CNAME(trapexit) /* backtrace code sentinel */ 760CNAME(trapexit): 761 762/* Disable interrupts: */ 763 mfmsr %r3 764 andi. %r3,%r3,~PSL_EE@l 765 mtmsr %r3 766/* Test AST pending: */ 767 lwz %r5,FRAME_SRR1+8(%r1) 768 mtcr %r5 769 bf 17,1f /* branch if PSL_PR is false */ 770 771 GET_CPUINFO(%r3) /* get per-CPU pointer */ 772 lwz %r4, TD_FLAGS(%r2) /* get thread flags value 773 * (r2 is curthread) */ 774 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 775 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 776 and. %r4,%r4,%r5 777 beq 1f 778 mfmsr %r3 /* re-enable interrupts */ 779 ori %r3,%r3,PSL_EE@l 780 mtmsr %r3 781 isync 782 addi %r3,%r1,8 783 bl CNAME(ast) 784 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 785CNAME(asttrapexit): 786 b trapexit /* test ast ret value ? */ 7871: 788 FRAME_LEAVE(PC_TEMPSAVE) 789 790 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */ 791CNAME(rfi_patch1): 792 rfi 793 794 .globl CNAME(rfid_patch) 795CNAME(rfid_patch): 796 rfid 797 798#if defined(KDB) 799/* 800 * Deliberate entry to dbtrap 801 */ 802 .globl CNAME(breakpoint) 803CNAME(breakpoint): 804 mtsprg1 %r1 805 mfmsr %r3 806 mtsrr1 %r3 807 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 808 mtmsr %r3 /* disable interrupts */ 809 isync 810 GET_CPUINFO(%r3) 811 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 812 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 813 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 814 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 815 mflr %r28 816 li %r29,EXC_BPT 817 mtlr %r29 818 mfcr %r29 819 mtsrr0 %r28 820 821/* 822 * Now the kdb trap catching code. 823 */ 824dbtrap: 825 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 826 mflr %r1 827 andi. %r1,%r1,0xff00 828 mtsprg3 %r1 829 830 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */ 831 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l 832 833 FRAME_SETUP(PC_DBSAVE) 834/* Call C trap code: */ 835 addi %r3,%r1,8 836 bl CNAME(db_trap_glue) 837 or. %r3,%r3,%r3 838 bne dbleave 839/* This wasn't for KDB, so switch to real trap: */ 840 lwz %r3,FRAME_EXC+8(%r1) /* save exception */ 841 GET_CPUINFO(%r4) 842 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 843 FRAME_LEAVE(PC_DBSAVE) 844 mtsprg1 %r1 /* prepare for entrance to realtrap */ 845 GET_CPUINFO(%r1) 846 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 847 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 848 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 849 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 850 mflr %r28 851 mfcr %r29 852 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 853 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 854 mfsprg1 %r1 855 b realtrap 856dbleave: 857 FRAME_LEAVE(PC_DBSAVE) 858 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */ 859CNAME(rfi_patch2): 860 rfi 861 862/* 863 * In case of KDB we want a separate trap catcher for it 864 */ 865 .globl CNAME(dblow),CNAME(dbsize) 866CNAME(dblow): 867 mtsprg1 %r1 /* save SP */ 868 mtsprg2 %r29 /* save r29 */ 869 mfcr %r29 /* save CR in r29 */ 870 mfsrr1 %r1 871 mtcr %r1 872 bf 17,1f /* branch if privileged */ 873 874 /* Unprivileged case */ 875 mtcr %r29 /* put the condition register back */ 876 mfsprg2 %r29 /* ... and r29 */ 877 mflr %r1 /* save LR */ 878 mtsprg2 %r1 /* And then in SPRG2 */ 879 li %r1, 0 /* How to get the vector from LR */ 880 881 bla generictrap /* and we look like a generic trap */ 8821: 883 /* Privileged, so drop to KDB */ 884 GET_CPUINFO(%r1) 885 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 886 mfsprg2 %r28 /* r29 holds cr... */ 887 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 888 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 889 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 890 mflr %r28 /* save LR */ 891 bla dbtrap 892CNAME(dbsize) = .-CNAME(dblow) 893#endif /* KDB */ 894