xref: /freebsd/sys/powerpc/aim/mmu_oea64.c (revision fab66680b3df4792fb0d3d13b2c9cdd88538d3d2)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2008-2015 Nathan Whitehorn
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 /*
33  * Manages physical address maps.
34  *
35  * Since the information managed by this module is also stored by the
36  * logical address mapping module, this module may throw away valid virtual
37  * to physical mappings at almost any time.  However, invalidations of
38  * mappings must be done as requested.
39  *
40  * In order to cope with hardware architectures which make virtual to
41  * physical map invalidates expensive, this module may delay invalidate
42  * reduced protection operations until such time as they are actually
43  * necessary.  This module is given full information as to which processors
44  * are currently using which maps, and to when physical maps must be made
45  * correct.
46  */
47 
48 #include "opt_kstack_pages.h"
49 
50 #include <sys/param.h>
51 #include <sys/kernel.h>
52 #include <sys/conf.h>
53 #include <sys/queue.h>
54 #include <sys/cpuset.h>
55 #include <sys/kerneldump.h>
56 #include <sys/ktr.h>
57 #include <sys/lock.h>
58 #include <sys/msgbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/mutex.h>
61 #include <sys/proc.h>
62 #include <sys/rwlock.h>
63 #include <sys/sched.h>
64 #include <sys/sysctl.h>
65 #include <sys/systm.h>
66 #include <sys/vmmeter.h>
67 #include <sys/smp.h>
68 
69 #include <sys/kdb.h>
70 
71 #include <dev/ofw/openfirm.h>
72 
73 #include <vm/vm.h>
74 #include <vm/vm_param.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_page.h>
77 #include <vm/vm_map.h>
78 #include <vm/vm_object.h>
79 #include <vm/vm_extern.h>
80 #include <vm/vm_pageout.h>
81 #include <vm/uma.h>
82 
83 #include <machine/_inttypes.h>
84 #include <machine/cpu.h>
85 #include <machine/platform.h>
86 #include <machine/frame.h>
87 #include <machine/md_var.h>
88 #include <machine/psl.h>
89 #include <machine/bat.h>
90 #include <machine/hid.h>
91 #include <machine/pte.h>
92 #include <machine/sr.h>
93 #include <machine/trap.h>
94 #include <machine/mmuvar.h>
95 
96 #include "mmu_oea64.h"
97 #include "mmu_if.h"
98 #include "moea64_if.h"
99 
100 void moea64_release_vsid(uint64_t vsid);
101 uintptr_t moea64_get_unique_vsid(void);
102 
103 #define DISABLE_TRANS(msr)	msr = mfmsr(); mtmsr(msr & ~PSL_DR)
104 #define ENABLE_TRANS(msr)	mtmsr(msr)
105 
106 #define	VSID_MAKE(sr, hash)	((sr) | (((hash) & 0xfffff) << 4))
107 #define	VSID_TO_HASH(vsid)	(((vsid) >> 4) & 0xfffff)
108 #define	VSID_HASH_MASK		0x0000007fffffffffULL
109 
110 /*
111  * Locking semantics:
112  *
113  * There are two locks of interest: the page locks and the pmap locks, which
114  * protect their individual PVO lists and are locked in that order. The contents
115  * of all PVO entries are protected by the locks of their respective pmaps.
116  * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
117  * into any list.
118  *
119  */
120 
121 #define PV_LOCK_PER_DOM	PA_LOCK_COUNT*3
122 #define PV_LOCK_COUNT	PV_LOCK_PER_DOM*MAXMEMDOM
123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
124 
125 /*
126  * Cheap NUMA-izing of the pv locks, to reduce contention across domains.
127  * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the
128  * index at (N << 45).
129  */
130 #ifdef __powerpc64__
131 #define PV_LOCK_IDX(pa)	(pa_index(pa) % PV_LOCK_PER_DOM + \
132 			(((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM)
133 #else
134 #define PV_LOCK_IDX(pa)	(pa_index(pa) % PV_LOCK_COUNT)
135 #endif
136 #define PV_LOCKPTR(pa)	((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)]))
137 #define PV_LOCK(pa)		mtx_lock(PV_LOCKPTR(pa))
138 #define PV_UNLOCK(pa)		mtx_unlock(PV_LOCKPTR(pa))
139 #define PV_LOCKASSERT(pa) 	mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
140 #define PV_PAGE_LOCK(m)		PV_LOCK(VM_PAGE_TO_PHYS(m))
141 #define PV_PAGE_UNLOCK(m)	PV_UNLOCK(VM_PAGE_TO_PHYS(m))
142 #define PV_PAGE_LOCKASSERT(m)	PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
143 
144 struct ofw_map {
145 	cell_t	om_va;
146 	cell_t	om_len;
147 	uint64_t om_pa;
148 	cell_t	om_mode;
149 };
150 
151 extern unsigned char _etext[];
152 extern unsigned char _end[];
153 
154 extern void *slbtrap, *slbtrapend;
155 
156 /*
157  * Map of physical memory regions.
158  */
159 static struct	mem_region *regions;
160 static struct	mem_region *pregions;
161 static struct	numa_mem_region *numa_pregions;
162 static u_int	phys_avail_count;
163 static int	regions_sz, pregions_sz, numapregions_sz;
164 
165 extern void bs_remap_earlyboot(void);
166 
167 /*
168  * Lock for the SLB tables.
169  */
170 struct mtx	moea64_slb_mutex;
171 
172 /*
173  * PTEG data.
174  */
175 u_long		moea64_pteg_count;
176 u_long		moea64_pteg_mask;
177 
178 /*
179  * PVO data.
180  */
181 
182 uma_zone_t	moea64_pvo_zone; /* zone for pvo entries */
183 
184 static struct	pvo_entry *moea64_bpvo_pool;
185 static int	moea64_bpvo_pool_index = 0;
186 static int	moea64_bpvo_pool_size = 327680;
187 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
188 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
189     &moea64_bpvo_pool_index, 0, "");
190 
191 #define	VSID_NBPW	(sizeof(u_int32_t) * 8)
192 #ifdef __powerpc64__
193 #define	NVSIDS		(NPMAPS * 16)
194 #define VSID_HASHMASK	0xffffffffUL
195 #else
196 #define NVSIDS		NPMAPS
197 #define VSID_HASHMASK	0xfffffUL
198 #endif
199 static u_int	moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
200 
201 static boolean_t moea64_initialized = FALSE;
202 
203 /*
204  * Statistics.
205  */
206 u_int	moea64_pte_valid = 0;
207 u_int	moea64_pte_overflow = 0;
208 u_int	moea64_pvo_entries = 0;
209 u_int	moea64_pvo_enter_calls = 0;
210 u_int	moea64_pvo_remove_calls = 0;
211 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
212     &moea64_pte_valid, 0, "");
213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
214     &moea64_pte_overflow, 0, "");
215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
216     &moea64_pvo_entries, 0, "");
217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
218     &moea64_pvo_enter_calls, 0, "");
219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
220     &moea64_pvo_remove_calls, 0, "");
221 
222 vm_offset_t	moea64_scratchpage_va[2];
223 struct pvo_entry *moea64_scratchpage_pvo[2];
224 struct	mtx	moea64_scratchpage_mtx;
225 
226 uint64_t 	moea64_large_page_mask = 0;
227 uint64_t	moea64_large_page_size = 0;
228 int		moea64_large_page_shift = 0;
229 
230 /*
231  * PVO calls.
232  */
233 static int	moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo,
234 		    struct pvo_head *pvo_head);
235 static void	moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo);
236 static void	moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo);
237 static struct	pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
238 
239 /*
240  * Utility routines.
241  */
242 static boolean_t	moea64_query_bit(mmu_t, vm_page_t, uint64_t);
243 static u_int		moea64_clear_bit(mmu_t, vm_page_t, uint64_t);
244 static void		moea64_kremove(mmu_t, vm_offset_t);
245 static void		moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
246 			    vm_paddr_t pa, vm_size_t sz);
247 static void		moea64_pmap_init_qpages(void);
248 
249 /*
250  * Kernel MMU interface
251  */
252 void moea64_clear_modify(mmu_t, vm_page_t);
253 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
254 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
255     vm_page_t *mb, vm_offset_t b_offset, int xfersize);
256 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
257     u_int flags, int8_t psind);
258 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
259     vm_prot_t);
260 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
261 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
262 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
263 void moea64_init(mmu_t);
264 boolean_t moea64_is_modified(mmu_t, vm_page_t);
265 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
266 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
267 int moea64_ts_referenced(mmu_t, vm_page_t);
268 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
269 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
270 void moea64_page_init(mmu_t, vm_page_t);
271 int moea64_page_wired_mappings(mmu_t, vm_page_t);
272 void moea64_pinit(mmu_t, pmap_t);
273 void moea64_pinit0(mmu_t, pmap_t);
274 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
275 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
276 void moea64_qremove(mmu_t, vm_offset_t, int);
277 void moea64_release(mmu_t, pmap_t);
278 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
279 void moea64_remove_pages(mmu_t, pmap_t);
280 void moea64_remove_all(mmu_t, vm_page_t);
281 void moea64_remove_write(mmu_t, vm_page_t);
282 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
283 void moea64_zero_page(mmu_t, vm_page_t);
284 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
285 void moea64_activate(mmu_t, struct thread *);
286 void moea64_deactivate(mmu_t, struct thread *);
287 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
288 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
289 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
290 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
291 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
292 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma);
293 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
294 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
295 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
296 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz,
297     void **va);
298 void moea64_scan_init(mmu_t mmu);
299 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m);
300 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr);
301 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm,
302     volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
303 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
304     int *is_user, vm_offset_t *decoded_addr);
305 
306 
307 static mmu_method_t moea64_methods[] = {
308 	MMUMETHOD(mmu_clear_modify,	moea64_clear_modify),
309 	MMUMETHOD(mmu_copy_page,	moea64_copy_page),
310 	MMUMETHOD(mmu_copy_pages,	moea64_copy_pages),
311 	MMUMETHOD(mmu_enter,		moea64_enter),
312 	MMUMETHOD(mmu_enter_object,	moea64_enter_object),
313 	MMUMETHOD(mmu_enter_quick,	moea64_enter_quick),
314 	MMUMETHOD(mmu_extract,		moea64_extract),
315 	MMUMETHOD(mmu_extract_and_hold,	moea64_extract_and_hold),
316 	MMUMETHOD(mmu_init,		moea64_init),
317 	MMUMETHOD(mmu_is_modified,	moea64_is_modified),
318 	MMUMETHOD(mmu_is_prefaultable,	moea64_is_prefaultable),
319 	MMUMETHOD(mmu_is_referenced,	moea64_is_referenced),
320 	MMUMETHOD(mmu_ts_referenced,	moea64_ts_referenced),
321 	MMUMETHOD(mmu_map,     		moea64_map),
322 	MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
323 	MMUMETHOD(mmu_page_init,	moea64_page_init),
324 	MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
325 	MMUMETHOD(mmu_pinit,		moea64_pinit),
326 	MMUMETHOD(mmu_pinit0,		moea64_pinit0),
327 	MMUMETHOD(mmu_protect,		moea64_protect),
328 	MMUMETHOD(mmu_qenter,		moea64_qenter),
329 	MMUMETHOD(mmu_qremove,		moea64_qremove),
330 	MMUMETHOD(mmu_release,		moea64_release),
331 	MMUMETHOD(mmu_remove,		moea64_remove),
332 	MMUMETHOD(mmu_remove_pages,	moea64_remove_pages),
333 	MMUMETHOD(mmu_remove_all,      	moea64_remove_all),
334 	MMUMETHOD(mmu_remove_write,	moea64_remove_write),
335 	MMUMETHOD(mmu_sync_icache,	moea64_sync_icache),
336 	MMUMETHOD(mmu_unwire,		moea64_unwire),
337 	MMUMETHOD(mmu_zero_page,       	moea64_zero_page),
338 	MMUMETHOD(mmu_zero_page_area,	moea64_zero_page_area),
339 	MMUMETHOD(mmu_activate,		moea64_activate),
340 	MMUMETHOD(mmu_deactivate,      	moea64_deactivate),
341 	MMUMETHOD(mmu_page_set_memattr,	moea64_page_set_memattr),
342 	MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page),
343 	MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page),
344 
345 	/* Internal interfaces */
346 	MMUMETHOD(mmu_mapdev,		moea64_mapdev),
347 	MMUMETHOD(mmu_mapdev_attr,	moea64_mapdev_attr),
348 	MMUMETHOD(mmu_unmapdev,		moea64_unmapdev),
349 	MMUMETHOD(mmu_kextract,		moea64_kextract),
350 	MMUMETHOD(mmu_kenter,		moea64_kenter),
351 	MMUMETHOD(mmu_kenter_attr,	moea64_kenter_attr),
352 	MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
353 	MMUMETHOD(mmu_scan_init,	moea64_scan_init),
354 	MMUMETHOD(mmu_dumpsys_map,	moea64_dumpsys_map),
355 	MMUMETHOD(mmu_map_user_ptr,	moea64_map_user_ptr),
356 	MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr),
357 
358 	{ 0, 0 }
359 };
360 
361 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
362 
363 static struct pvo_head *
364 vm_page_to_pvoh(vm_page_t m)
365 {
366 
367 	mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
368 	return (&m->md.mdpg_pvoh);
369 }
370 
371 static struct pvo_entry *
372 alloc_pvo_entry(int bootstrap)
373 {
374 	struct pvo_entry *pvo;
375 
376 	if (!moea64_initialized || bootstrap) {
377 		if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
378 			panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
379 			      moea64_bpvo_pool_index, moea64_bpvo_pool_size,
380 			      moea64_bpvo_pool_size * sizeof(struct pvo_entry));
381 		}
382 		pvo = &moea64_bpvo_pool[
383 		    atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
384 		bzero(pvo, sizeof(*pvo));
385 		pvo->pvo_vaddr = PVO_BOOTSTRAP;
386 	} else {
387 		pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT);
388 		bzero(pvo, sizeof(*pvo));
389 	}
390 
391 	return (pvo);
392 }
393 
394 
395 static void
396 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
397 {
398 	uint64_t vsid;
399 	uint64_t hash;
400 	int shift;
401 
402 	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
403 
404 	pvo->pvo_pmap = pmap;
405 	va &= ~ADDR_POFF;
406 	pvo->pvo_vaddr |= va;
407 	vsid = va_to_vsid(pmap, va);
408 	pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
409 	    | (vsid << 16);
410 
411 	shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift :
412 	    ADDR_PIDX_SHFT;
413 	hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
414 	pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
415 }
416 
417 static void
418 free_pvo_entry(struct pvo_entry *pvo)
419 {
420 
421 	if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
422 		uma_zfree(moea64_pvo_zone, pvo);
423 }
424 
425 void
426 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
427 {
428 
429 	lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) &
430 	    LPTE_AVPN_MASK;
431 	lpte->pte_hi |= LPTE_VALID;
432 
433 	if (pvo->pvo_vaddr & PVO_LARGE)
434 		lpte->pte_hi |= LPTE_BIG;
435 	if (pvo->pvo_vaddr & PVO_WIRED)
436 		lpte->pte_hi |= LPTE_WIRED;
437 	if (pvo->pvo_vaddr & PVO_HID)
438 		lpte->pte_hi |= LPTE_HID;
439 
440 	lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
441 	if (pvo->pvo_pte.prot & VM_PROT_WRITE)
442 		lpte->pte_lo |= LPTE_BW;
443 	else
444 		lpte->pte_lo |= LPTE_BR;
445 
446 	if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
447 		lpte->pte_lo |= LPTE_NOEXEC;
448 }
449 
450 static __inline uint64_t
451 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
452 {
453 	uint64_t pte_lo;
454 	int i;
455 
456 	if (ma != VM_MEMATTR_DEFAULT) {
457 		switch (ma) {
458 		case VM_MEMATTR_UNCACHEABLE:
459 			return (LPTE_I | LPTE_G);
460 		case VM_MEMATTR_CACHEABLE:
461 			return (LPTE_M);
462 		case VM_MEMATTR_WRITE_COMBINING:
463 		case VM_MEMATTR_WRITE_BACK:
464 		case VM_MEMATTR_PREFETCHABLE:
465 			return (LPTE_I);
466 		case VM_MEMATTR_WRITE_THROUGH:
467 			return (LPTE_W | LPTE_M);
468 		}
469 	}
470 
471 	/*
472 	 * Assume the page is cache inhibited and access is guarded unless
473 	 * it's in our available memory array.
474 	 */
475 	pte_lo = LPTE_I | LPTE_G;
476 	for (i = 0; i < pregions_sz; i++) {
477 		if ((pa >= pregions[i].mr_start) &&
478 		    (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
479 			pte_lo &= ~(LPTE_I | LPTE_G);
480 			pte_lo |= LPTE_M;
481 			break;
482 		}
483 	}
484 
485 	return pte_lo;
486 }
487 
488 /*
489  * Quick sort callout for comparing memory regions.
490  */
491 static int	om_cmp(const void *a, const void *b);
492 
493 static int
494 om_cmp(const void *a, const void *b)
495 {
496 	const struct	ofw_map *mapa;
497 	const struct	ofw_map *mapb;
498 
499 	mapa = a;
500 	mapb = b;
501 	if (mapa->om_pa < mapb->om_pa)
502 		return (-1);
503 	else if (mapa->om_pa > mapb->om_pa)
504 		return (1);
505 	else
506 		return (0);
507 }
508 
509 static void
510 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
511 {
512 	struct ofw_map	translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
513 	pcell_t		acells, trans_cells[sz/sizeof(cell_t)];
514 	struct pvo_entry *pvo;
515 	register_t	msr;
516 	vm_offset_t	off;
517 	vm_paddr_t	pa_base;
518 	int		i, j;
519 
520 	bzero(translations, sz);
521 	OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
522 	    sizeof(acells));
523 	if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
524 		panic("moea64_bootstrap: can't get ofw translations");
525 
526 	CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
527 	sz /= sizeof(cell_t);
528 	for (i = 0, j = 0; i < sz; j++) {
529 		translations[j].om_va = trans_cells[i++];
530 		translations[j].om_len = trans_cells[i++];
531 		translations[j].om_pa = trans_cells[i++];
532 		if (acells == 2) {
533 			translations[j].om_pa <<= 32;
534 			translations[j].om_pa |= trans_cells[i++];
535 		}
536 		translations[j].om_mode = trans_cells[i++];
537 	}
538 	KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
539 	    i, sz));
540 
541 	sz = j;
542 	qsort(translations, sz, sizeof (*translations), om_cmp);
543 
544 	for (i = 0; i < sz; i++) {
545 		pa_base = translations[i].om_pa;
546 	      #ifndef __powerpc64__
547 		if ((translations[i].om_pa >> 32) != 0)
548 			panic("OFW translations above 32-bit boundary!");
549 	      #endif
550 
551 		if (pa_base % PAGE_SIZE)
552 			panic("OFW translation not page-aligned (phys)!");
553 		if (translations[i].om_va % PAGE_SIZE)
554 			panic("OFW translation not page-aligned (virt)!");
555 
556 		CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
557 		    pa_base, translations[i].om_va, translations[i].om_len);
558 
559 		/* Now enter the pages for this mapping */
560 
561 		DISABLE_TRANS(msr);
562 		for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
563 			/* If this address is direct-mapped, skip remapping */
564 			if (hw_direct_map &&
565 			    translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
566 			    moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT)
567  			    == LPTE_M)
568 				continue;
569 
570 			PMAP_LOCK(kernel_pmap);
571 			pvo = moea64_pvo_find_va(kernel_pmap,
572 			    translations[i].om_va + off);
573 			PMAP_UNLOCK(kernel_pmap);
574 			if (pvo != NULL)
575 				continue;
576 
577 			moea64_kenter(mmup, translations[i].om_va + off,
578 			    pa_base + off);
579 		}
580 		ENABLE_TRANS(msr);
581 	}
582 }
583 
584 #ifdef __powerpc64__
585 static void
586 moea64_probe_large_page(void)
587 {
588 	uint16_t pvr = mfpvr() >> 16;
589 
590 	switch (pvr) {
591 	case IBM970:
592 	case IBM970FX:
593 	case IBM970MP:
594 		powerpc_sync(); isync();
595 		mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
596 		powerpc_sync(); isync();
597 
598 		/* FALLTHROUGH */
599 	default:
600 		if (moea64_large_page_size == 0) {
601 			moea64_large_page_size = 0x1000000; /* 16 MB */
602 			moea64_large_page_shift = 24;
603 		}
604 	}
605 
606 	moea64_large_page_mask = moea64_large_page_size - 1;
607 }
608 
609 static void
610 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
611 {
612 	struct slb *cache;
613 	struct slb entry;
614 	uint64_t esid, slbe;
615 	uint64_t i;
616 
617 	cache = PCPU_GET(aim.slb);
618 	esid = va >> ADDR_SR_SHFT;
619 	slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
620 
621 	for (i = 0; i < 64; i++) {
622 		if (cache[i].slbe == (slbe | i))
623 			return;
624 	}
625 
626 	entry.slbe = slbe;
627 	entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
628 	if (large)
629 		entry.slbv |= SLBV_L;
630 
631 	slb_insert_kernel(entry.slbe, entry.slbv);
632 }
633 #endif
634 
635 static void
636 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
637     vm_offset_t kernelend)
638 {
639 	struct pvo_entry *pvo;
640 	register_t msr;
641 	vm_paddr_t pa, pkernelstart, pkernelend;
642 	vm_offset_t size, off;
643 	uint64_t pte_lo;
644 	int i;
645 
646 	if (moea64_large_page_size == 0)
647 		hw_direct_map = 0;
648 
649 	DISABLE_TRANS(msr);
650 	if (hw_direct_map) {
651 		PMAP_LOCK(kernel_pmap);
652 		for (i = 0; i < pregions_sz; i++) {
653 		  for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
654 		     pregions[i].mr_size; pa += moea64_large_page_size) {
655 			pte_lo = LPTE_M;
656 
657 			pvo = alloc_pvo_entry(1 /* bootstrap */);
658 			pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
659 			init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa));
660 
661 			/*
662 			 * Set memory access as guarded if prefetch within
663 			 * the page could exit the available physmem area.
664 			 */
665 			if (pa & moea64_large_page_mask) {
666 				pa &= moea64_large_page_mask;
667 				pte_lo |= LPTE_G;
668 			}
669 			if (pa + moea64_large_page_size >
670 			    pregions[i].mr_start + pregions[i].mr_size)
671 				pte_lo |= LPTE_G;
672 
673 			pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
674 			    VM_PROT_EXECUTE;
675 			pvo->pvo_pte.pa = pa | pte_lo;
676 			moea64_pvo_enter(mmup, pvo, NULL);
677 		  }
678 		}
679 		PMAP_UNLOCK(kernel_pmap);
680 	}
681 
682 	/*
683 	 * Make sure the kernel and BPVO pool stay mapped on systems either
684 	 * without a direct map or on which the kernel is not already executing
685 	 * out of the direct-mapped region.
686 	 */
687 	if (kernelstart < DMAP_BASE_ADDRESS) {
688 		/*
689 		 * For pre-dmap execution, we need to use identity mapping
690 		 * because we will be operating with the mmu on but in the
691 		 * wrong address configuration until we __restartkernel().
692 		 */
693 		for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
694 		    pa += PAGE_SIZE)
695 			moea64_kenter(mmup, pa, pa);
696 	} else if (!hw_direct_map) {
697 		pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS;
698 		pkernelend = kernelend & ~DMAP_BASE_ADDRESS;
699 		for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend;
700 		    pa += PAGE_SIZE)
701 			moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa);
702 	}
703 
704 	if (!hw_direct_map) {
705 		size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
706 		off = (vm_offset_t)(moea64_bpvo_pool);
707 		for (pa = off; pa < off + size; pa += PAGE_SIZE)
708 			moea64_kenter(mmup, pa, pa);
709 
710 		/* Map exception vectors */
711 		for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE)
712 			moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa);
713 	}
714 	ENABLE_TRANS(msr);
715 
716 	/*
717 	 * Allow user to override unmapped_buf_allowed for testing.
718 	 * XXXKIB Only direct map implementation was tested.
719 	 */
720 	if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
721 	    &unmapped_buf_allowed))
722 		unmapped_buf_allowed = hw_direct_map;
723 }
724 
725 /* Quick sort callout for comparing physical addresses. */
726 static int
727 pa_cmp(const void *a, const void *b)
728 {
729 	const vm_paddr_t *pa = a, *pb = b;
730 
731 	if (*pa < *pb)
732 		return (-1);
733 	else if (*pa > *pb)
734 		return (1);
735 	else
736 		return (0);
737 }
738 
739 void
740 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
741 {
742 	int		i, j;
743 	vm_size_t	physsz, hwphyssz;
744 	vm_paddr_t	kernelphysstart, kernelphysend;
745 	int		rm_pavail;
746 
747 #ifndef __powerpc64__
748 	/* We don't have a direct map since there is no BAT */
749 	hw_direct_map = 0;
750 
751 	/* Make sure battable is zero, since we have no BAT */
752 	for (i = 0; i < 16; i++) {
753 		battable[i].batu = 0;
754 		battable[i].batl = 0;
755 	}
756 #else
757 	moea64_probe_large_page();
758 
759 	/* Use a direct map if we have large page support */
760 	if (moea64_large_page_size > 0)
761 		hw_direct_map = 1;
762 	else
763 		hw_direct_map = 0;
764 
765 	/* Install trap handlers for SLBs */
766 	bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
767 	bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
768 	__syncicache((void *)EXC_DSE, 0x80);
769 	__syncicache((void *)EXC_ISE, 0x80);
770 #endif
771 
772 	kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS;
773 	kernelphysend = kernelend & ~DMAP_BASE_ADDRESS;
774 
775 	/* Get physical memory regions from firmware */
776 	mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
777 	CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
778 
779 	if (nitems(phys_avail) < regions_sz)
780 		panic("moea64_bootstrap: phys_avail too small");
781 
782 	phys_avail_count = 0;
783 	physsz = 0;
784 	hwphyssz = 0;
785 	TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
786 	for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
787 		CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
788 		    regions[i].mr_start, regions[i].mr_start +
789 		    regions[i].mr_size, regions[i].mr_size);
790 		if (hwphyssz != 0 &&
791 		    (physsz + regions[i].mr_size) >= hwphyssz) {
792 			if (physsz < hwphyssz) {
793 				phys_avail[j] = regions[i].mr_start;
794 				phys_avail[j + 1] = regions[i].mr_start +
795 				    hwphyssz - physsz;
796 				physsz = hwphyssz;
797 				phys_avail_count++;
798 			}
799 			break;
800 		}
801 		phys_avail[j] = regions[i].mr_start;
802 		phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
803 		phys_avail_count++;
804 		physsz += regions[i].mr_size;
805 	}
806 
807 	/* Check for overlap with the kernel and exception vectors */
808 	rm_pavail = 0;
809 	for (j = 0; j < 2*phys_avail_count; j+=2) {
810 		if (phys_avail[j] < EXC_LAST)
811 			phys_avail[j] += EXC_LAST;
812 
813 		if (phys_avail[j] >= kernelphysstart &&
814 		    phys_avail[j+1] <= kernelphysend) {
815 			phys_avail[j] = phys_avail[j+1] = ~0;
816 			rm_pavail++;
817 			continue;
818 		}
819 
820 		if (kernelphysstart >= phys_avail[j] &&
821 		    kernelphysstart < phys_avail[j+1]) {
822 			if (kernelphysend < phys_avail[j+1]) {
823 				phys_avail[2*phys_avail_count] =
824 				    (kernelphysend & ~PAGE_MASK) + PAGE_SIZE;
825 				phys_avail[2*phys_avail_count + 1] =
826 				    phys_avail[j+1];
827 				phys_avail_count++;
828 			}
829 
830 			phys_avail[j+1] = kernelphysstart & ~PAGE_MASK;
831 		}
832 
833 		if (kernelphysend >= phys_avail[j] &&
834 		    kernelphysend < phys_avail[j+1]) {
835 			if (kernelphysstart > phys_avail[j]) {
836 				phys_avail[2*phys_avail_count] = phys_avail[j];
837 				phys_avail[2*phys_avail_count + 1] =
838 				    kernelphysstart & ~PAGE_MASK;
839 				phys_avail_count++;
840 			}
841 
842 			phys_avail[j] = (kernelphysend & ~PAGE_MASK) +
843 			    PAGE_SIZE;
844 		}
845 	}
846 
847 	/* Remove physical available regions marked for removal (~0) */
848 	if (rm_pavail) {
849 		qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]),
850 			pa_cmp);
851 		phys_avail_count -= rm_pavail;
852 		for (i = 2*phys_avail_count;
853 		     i < 2*(phys_avail_count + rm_pavail); i+=2)
854 			phys_avail[i] = phys_avail[i+1] = 0;
855 	}
856 
857 	physmem = btoc(physsz);
858 
859 #ifdef PTEGCOUNT
860 	moea64_pteg_count = PTEGCOUNT;
861 #else
862 	moea64_pteg_count = 0x1000;
863 
864 	while (moea64_pteg_count < physmem)
865 		moea64_pteg_count <<= 1;
866 
867 	moea64_pteg_count >>= 1;
868 #endif /* PTEGCOUNT */
869 }
870 
871 void
872 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
873 {
874 	int		i;
875 
876 	/*
877 	 * Set PTEG mask
878 	 */
879 	moea64_pteg_mask = moea64_pteg_count - 1;
880 
881 	/*
882 	 * Initialize SLB table lock and page locks
883 	 */
884 	mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
885 	for (i = 0; i < PV_LOCK_COUNT; i++)
886 		mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
887 
888 	/*
889 	 * Initialise the bootstrap pvo pool.
890 	 */
891 	moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
892 		moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE);
893 	moea64_bpvo_pool_index = 0;
894 
895 	/* Place at address usable through the direct map */
896 	if (hw_direct_map)
897 		moea64_bpvo_pool = (struct pvo_entry *)
898 		    PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool);
899 
900 	/*
901 	 * Make sure kernel vsid is allocated as well as VSID 0.
902 	 */
903 	#ifndef __powerpc64__
904 	moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
905 		|= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
906 	moea64_vsid_bitmap[0] |= 1;
907 	#endif
908 
909 	/*
910 	 * Initialize the kernel pmap (which is statically allocated).
911 	 */
912 	#ifdef __powerpc64__
913 	for (i = 0; i < 64; i++) {
914 		pcpup->pc_aim.slb[i].slbv = 0;
915 		pcpup->pc_aim.slb[i].slbe = 0;
916 	}
917 	#else
918 	for (i = 0; i < 16; i++)
919 		kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
920 	#endif
921 
922 	kernel_pmap->pmap_phys = kernel_pmap;
923 	CPU_FILL(&kernel_pmap->pm_active);
924 	RB_INIT(&kernel_pmap->pmap_pvo);
925 
926 	PMAP_LOCK_INIT(kernel_pmap);
927 
928 	/*
929 	 * Now map in all the other buffers we allocated earlier
930 	 */
931 
932 	moea64_setup_direct_map(mmup, kernelstart, kernelend);
933 }
934 
935 void
936 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
937 {
938 	ihandle_t	mmui;
939 	phandle_t	chosen;
940 	phandle_t	mmu;
941 	ssize_t		sz;
942 	int		i;
943 	vm_offset_t	pa, va;
944 	void		*dpcpu;
945 
946 	/*
947 	 * Set up the Open Firmware pmap and add its mappings if not in real
948 	 * mode.
949 	 */
950 
951 	chosen = OF_finddevice("/chosen");
952 	if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
953 		mmu = OF_instance_to_package(mmui);
954 		if (mmu == -1 ||
955 		    (sz = OF_getproplen(mmu, "translations")) == -1)
956 			sz = 0;
957 		if (sz > 6144 /* tmpstksz - 2 KB headroom */)
958 			panic("moea64_bootstrap: too many ofw translations");
959 
960 		if (sz > 0)
961 			moea64_add_ofw_mappings(mmup, mmu, sz);
962 	}
963 
964 	/*
965 	 * Calculate the last available physical address.
966 	 */
967 	Maxmem = 0;
968 	for (i = 0; phys_avail[i + 2] != 0; i += 2)
969 		Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1]));
970 
971 	/*
972 	 * Initialize MMU.
973 	 */
974 	MMU_CPU_BOOTSTRAP(mmup,0);
975 	mtmsr(mfmsr() | PSL_DR | PSL_IR);
976 	pmap_bootstrapped++;
977 
978 	/*
979 	 * Set the start and end of kva.
980 	 */
981 	virtual_avail = VM_MIN_KERNEL_ADDRESS;
982 	virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
983 
984 	/*
985 	 * Map the entire KVA range into the SLB. We must not fault there.
986 	 */
987 	#ifdef __powerpc64__
988 	for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
989 		moea64_bootstrap_slb_prefault(va, 0);
990 	#endif
991 
992 	/*
993 	 * Remap any early IO mappings (console framebuffer, etc.)
994 	 */
995 	bs_remap_earlyboot();
996 
997 	/*
998 	 * Figure out how far we can extend virtual_end into segment 16
999 	 * without running into existing mappings. Segment 16 is guaranteed
1000 	 * to contain neither RAM nor devices (at least on Apple hardware),
1001 	 * but will generally contain some OFW mappings we should not
1002 	 * step on.
1003 	 */
1004 
1005 	#ifndef __powerpc64__	/* KVA is in high memory on PPC64 */
1006 	PMAP_LOCK(kernel_pmap);
1007 	while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
1008 	    moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
1009 		virtual_end += PAGE_SIZE;
1010 	PMAP_UNLOCK(kernel_pmap);
1011 	#endif
1012 
1013 	/*
1014 	 * Allocate a kernel stack with a guard page for thread0 and map it
1015 	 * into the kernel page map.
1016 	 */
1017 	pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
1018 	va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1019 	virtual_avail = va + kstack_pages * PAGE_SIZE;
1020 	CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
1021 	thread0.td_kstack = va;
1022 	thread0.td_kstack_pages = kstack_pages;
1023 	for (i = 0; i < kstack_pages; i++) {
1024 		moea64_kenter(mmup, va, pa);
1025 		pa += PAGE_SIZE;
1026 		va += PAGE_SIZE;
1027 	}
1028 
1029 	/*
1030 	 * Allocate virtual address space for the message buffer.
1031 	 */
1032 	pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
1033 	msgbufp = (struct msgbuf *)virtual_avail;
1034 	va = virtual_avail;
1035 	virtual_avail += round_page(msgbufsize);
1036 	while (va < virtual_avail) {
1037 		moea64_kenter(mmup, va, pa);
1038 		pa += PAGE_SIZE;
1039 		va += PAGE_SIZE;
1040 	}
1041 
1042 	/*
1043 	 * Allocate virtual address space for the dynamic percpu area.
1044 	 */
1045 	pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
1046 	dpcpu = (void *)virtual_avail;
1047 	va = virtual_avail;
1048 	virtual_avail += DPCPU_SIZE;
1049 	while (va < virtual_avail) {
1050 		moea64_kenter(mmup, va, pa);
1051 		pa += PAGE_SIZE;
1052 		va += PAGE_SIZE;
1053 	}
1054 	dpcpu_init(dpcpu, curcpu);
1055 
1056 	/*
1057 	 * Allocate some things for page zeroing. We put this directly
1058 	 * in the page table and use MOEA64_PTE_REPLACE to avoid any
1059 	 * of the PVO book-keeping or other parts of the VM system
1060 	 * from even knowing that this hack exists.
1061 	 */
1062 
1063 	if (!hw_direct_map) {
1064 		mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
1065 		    MTX_DEF);
1066 		for (i = 0; i < 2; i++) {
1067 			moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
1068 			virtual_end -= PAGE_SIZE;
1069 
1070 			moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
1071 
1072 			PMAP_LOCK(kernel_pmap);
1073 			moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
1074 			    kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
1075 			PMAP_UNLOCK(kernel_pmap);
1076 		}
1077 	}
1078 
1079 	numa_mem_regions(&numa_pregions, &numapregions_sz);
1080 }
1081 
1082 static void
1083 moea64_pmap_init_qpages(void)
1084 {
1085 	struct pcpu *pc;
1086 	int i;
1087 
1088 	if (hw_direct_map)
1089 		return;
1090 
1091 	CPU_FOREACH(i) {
1092 		pc = pcpu_find(i);
1093 		pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1094 		if (pc->pc_qmap_addr == 0)
1095 			panic("pmap_init_qpages: unable to allocate KVA");
1096 		PMAP_LOCK(kernel_pmap);
1097 		pc->pc_aim.qmap_pvo =
1098 		    moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1099 		PMAP_UNLOCK(kernel_pmap);
1100 		mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF);
1101 	}
1102 }
1103 
1104 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1105 
1106 /*
1107  * Activate a user pmap.  This mostly involves setting some non-CPU
1108  * state.
1109  */
1110 void
1111 moea64_activate(mmu_t mmu, struct thread *td)
1112 {
1113 	pmap_t	pm;
1114 
1115 	pm = &td->td_proc->p_vmspace->vm_pmap;
1116 	CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1117 
1118 	#ifdef __powerpc64__
1119 	PCPU_SET(aim.userslb, pm->pm_slb);
1120 	__asm __volatile("slbmte %0, %1; isync" ::
1121 	    "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1122 	#else
1123 	PCPU_SET(curpmap, pm->pmap_phys);
1124 	mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1125 	#endif
1126 }
1127 
1128 void
1129 moea64_deactivate(mmu_t mmu, struct thread *td)
1130 {
1131 	pmap_t	pm;
1132 
1133 	__asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1134 
1135 	pm = &td->td_proc->p_vmspace->vm_pmap;
1136 	CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1137 	#ifdef __powerpc64__
1138 	PCPU_SET(aim.userslb, NULL);
1139 	#else
1140 	PCPU_SET(curpmap, NULL);
1141 	#endif
1142 }
1143 
1144 void
1145 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1146 {
1147 	struct	pvo_entry key, *pvo;
1148 	vm_page_t m;
1149 	int64_t	refchg;
1150 
1151 	key.pvo_vaddr = sva;
1152 	PMAP_LOCK(pm);
1153 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1154 	    pvo != NULL && PVO_VADDR(pvo) < eva;
1155 	    pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1156 		if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1157 			panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1158 			    pvo);
1159 		pvo->pvo_vaddr &= ~PVO_WIRED;
1160 		refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */);
1161 		if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1162 		    (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1163 			if (refchg < 0)
1164 				refchg = LPTE_CHG;
1165 			m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1166 
1167 			refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1168 			if (refchg & LPTE_CHG)
1169 				vm_page_dirty(m);
1170 			if (refchg & LPTE_REF)
1171 				vm_page_aflag_set(m, PGA_REFERENCED);
1172 		}
1173 		pm->pm_stats.wired_count--;
1174 	}
1175 	PMAP_UNLOCK(pm);
1176 }
1177 
1178 /*
1179  * This goes through and sets the physical address of our
1180  * special scratch PTE to the PA we want to zero or copy. Because
1181  * of locking issues (this can get called in pvo_enter() by
1182  * the UMA allocator), we can't use most other utility functions here
1183  */
1184 
1185 static __inline
1186 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa)
1187 {
1188 	struct pvo_entry *pvo;
1189 
1190 	KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1191 	mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1192 
1193 	pvo = moea64_scratchpage_pvo[which];
1194 	PMAP_LOCK(pvo->pvo_pmap);
1195 	pvo->pvo_pte.pa =
1196 	    moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1197 	MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE);
1198 	PMAP_UNLOCK(pvo->pvo_pmap);
1199 	isync();
1200 }
1201 
1202 void
1203 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1204 {
1205 	vm_offset_t	dst;
1206 	vm_offset_t	src;
1207 
1208 	dst = VM_PAGE_TO_PHYS(mdst);
1209 	src = VM_PAGE_TO_PHYS(msrc);
1210 
1211 	if (hw_direct_map) {
1212 		bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1213 		    PAGE_SIZE);
1214 	} else {
1215 		mtx_lock(&moea64_scratchpage_mtx);
1216 
1217 		moea64_set_scratchpage_pa(mmu, 0, src);
1218 		moea64_set_scratchpage_pa(mmu, 1, dst);
1219 
1220 		bcopy((void *)moea64_scratchpage_va[0],
1221 		    (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1222 
1223 		mtx_unlock(&moea64_scratchpage_mtx);
1224 	}
1225 }
1226 
1227 static inline void
1228 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1229     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1230 {
1231 	void *a_cp, *b_cp;
1232 	vm_offset_t a_pg_offset, b_pg_offset;
1233 	int cnt;
1234 
1235 	while (xfersize > 0) {
1236 		a_pg_offset = a_offset & PAGE_MASK;
1237 		cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1238 		a_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1239 		    VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1240 		    a_pg_offset;
1241 		b_pg_offset = b_offset & PAGE_MASK;
1242 		cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1243 		b_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1244 		    VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1245 		    b_pg_offset;
1246 		bcopy(a_cp, b_cp, cnt);
1247 		a_offset += cnt;
1248 		b_offset += cnt;
1249 		xfersize -= cnt;
1250 	}
1251 }
1252 
1253 static inline void
1254 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1255     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1256 {
1257 	void *a_cp, *b_cp;
1258 	vm_offset_t a_pg_offset, b_pg_offset;
1259 	int cnt;
1260 
1261 	mtx_lock(&moea64_scratchpage_mtx);
1262 	while (xfersize > 0) {
1263 		a_pg_offset = a_offset & PAGE_MASK;
1264 		cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1265 		moea64_set_scratchpage_pa(mmu, 0,
1266 		    VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1267 		a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1268 		b_pg_offset = b_offset & PAGE_MASK;
1269 		cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1270 		moea64_set_scratchpage_pa(mmu, 1,
1271 		    VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1272 		b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1273 		bcopy(a_cp, b_cp, cnt);
1274 		a_offset += cnt;
1275 		b_offset += cnt;
1276 		xfersize -= cnt;
1277 	}
1278 	mtx_unlock(&moea64_scratchpage_mtx);
1279 }
1280 
1281 void
1282 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1283     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1284 {
1285 
1286 	if (hw_direct_map) {
1287 		moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1288 		    xfersize);
1289 	} else {
1290 		moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1291 		    xfersize);
1292 	}
1293 }
1294 
1295 void
1296 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1297 {
1298 	vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1299 
1300 	if (size + off > PAGE_SIZE)
1301 		panic("moea64_zero_page: size + off > PAGE_SIZE");
1302 
1303 	if (hw_direct_map) {
1304 		bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size);
1305 	} else {
1306 		mtx_lock(&moea64_scratchpage_mtx);
1307 		moea64_set_scratchpage_pa(mmu, 0, pa);
1308 		bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1309 		mtx_unlock(&moea64_scratchpage_mtx);
1310 	}
1311 }
1312 
1313 /*
1314  * Zero a page of physical memory by temporarily mapping it
1315  */
1316 void
1317 moea64_zero_page(mmu_t mmu, vm_page_t m)
1318 {
1319 	vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1320 	vm_offset_t va, off;
1321 
1322 	if (!hw_direct_map) {
1323 		mtx_lock(&moea64_scratchpage_mtx);
1324 
1325 		moea64_set_scratchpage_pa(mmu, 0, pa);
1326 		va = moea64_scratchpage_va[0];
1327 	} else {
1328 		va = PHYS_TO_DMAP(pa);
1329 	}
1330 
1331 	for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1332 		__asm __volatile("dcbz 0,%0" :: "r"(va + off));
1333 
1334 	if (!hw_direct_map)
1335 		mtx_unlock(&moea64_scratchpage_mtx);
1336 }
1337 
1338 vm_offset_t
1339 moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
1340 {
1341 	struct pvo_entry *pvo;
1342 	vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1343 
1344 	if (hw_direct_map)
1345 		return (PHYS_TO_DMAP(pa));
1346 
1347 	/*
1348  	 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1349 	 * a critical section and access the PCPU data like on i386.
1350 	 * Instead, pin the thread and grab the PCPU lock to prevent
1351 	 * a preempting thread from using the same PCPU data.
1352 	 */
1353 	sched_pin();
1354 
1355 	mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED);
1356 	pvo = PCPU_GET(aim.qmap_pvo);
1357 
1358 	mtx_lock(PCPU_PTR(aim.qmap_lock));
1359 	pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1360 	    (uint64_t)pa;
1361 	MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
1362 	isync();
1363 
1364 	return (PCPU_GET(qmap_addr));
1365 }
1366 
1367 void
1368 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1369 {
1370 	if (hw_direct_map)
1371 		return;
1372 
1373 	mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED);
1374 	KASSERT(PCPU_GET(qmap_addr) == addr,
1375 	    ("moea64_quick_remove_page: invalid address"));
1376 	mtx_unlock(PCPU_PTR(aim.qmap_lock));
1377 	sched_unpin();
1378 }
1379 
1380 /*
1381  * Map the given physical page at the specified virtual address in the
1382  * target pmap with the protection requested.  If specified the page
1383  * will be wired down.
1384  */
1385 
1386 int
1387 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1388     vm_prot_t prot, u_int flags, int8_t psind)
1389 {
1390 	struct		pvo_entry *pvo, *oldpvo;
1391 	struct		pvo_head *pvo_head;
1392 	uint64_t	pte_lo;
1393 	int		error;
1394 
1395 	if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1396 		VM_OBJECT_ASSERT_LOCKED(m->object);
1397 
1398 	pvo = alloc_pvo_entry(0);
1399 	pvo->pvo_pmap = NULL; /* to be filled in later */
1400 	pvo->pvo_pte.prot = prot;
1401 
1402 	pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1403 	pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo;
1404 
1405 	if ((flags & PMAP_ENTER_WIRED) != 0)
1406 		pvo->pvo_vaddr |= PVO_WIRED;
1407 
1408 	if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1409 		pvo_head = NULL;
1410 	} else {
1411 		pvo_head = &m->md.mdpg_pvoh;
1412 		pvo->pvo_vaddr |= PVO_MANAGED;
1413 	}
1414 
1415 	for (;;) {
1416 		PV_PAGE_LOCK(m);
1417 		PMAP_LOCK(pmap);
1418 		if (pvo->pvo_pmap == NULL)
1419 			init_pvo_entry(pvo, pmap, va);
1420 		if (prot & VM_PROT_WRITE)
1421 			if (pmap_bootstrapped &&
1422 			    (m->oflags & VPO_UNMANAGED) == 0)
1423 				vm_page_aflag_set(m, PGA_WRITEABLE);
1424 
1425 		oldpvo = moea64_pvo_find_va(pmap, va);
1426 		if (oldpvo != NULL) {
1427 			if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1428 			    oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1429 			    oldpvo->pvo_pte.prot == prot) {
1430 				/* Identical mapping already exists */
1431 				error = 0;
1432 
1433 				/* If not in page table, reinsert it */
1434 				if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) {
1435 					moea64_pte_overflow--;
1436 					MOEA64_PTE_INSERT(mmu, oldpvo);
1437 				}
1438 
1439 				/* Then just clean up and go home */
1440 				PV_PAGE_UNLOCK(m);
1441 				PMAP_UNLOCK(pmap);
1442 				free_pvo_entry(pvo);
1443 				break;
1444 			}
1445 
1446 			/* Otherwise, need to kill it first */
1447 			KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1448 			    "mapping does not match new mapping"));
1449 			moea64_pvo_remove_from_pmap(mmu, oldpvo);
1450 		}
1451 		error = moea64_pvo_enter(mmu, pvo, pvo_head);
1452 		PV_PAGE_UNLOCK(m);
1453 		PMAP_UNLOCK(pmap);
1454 
1455 		/* Free any dead pages */
1456 		if (oldpvo != NULL) {
1457 			PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1458 			moea64_pvo_remove_from_page(mmu, oldpvo);
1459 			PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1460 			free_pvo_entry(oldpvo);
1461 		}
1462 
1463 		if (error != ENOMEM)
1464 			break;
1465 		if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1466 			return (KERN_RESOURCE_SHORTAGE);
1467 		VM_OBJECT_ASSERT_UNLOCKED(m->object);
1468 		vm_wait(NULL);
1469 	}
1470 
1471 	/*
1472 	 * Flush the page from the instruction cache if this page is
1473 	 * mapped executable and cacheable.
1474 	 */
1475 	if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1476 	    (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1477 		vm_page_aflag_set(m, PGA_EXECUTABLE);
1478 		moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1479 	}
1480 	return (KERN_SUCCESS);
1481 }
1482 
1483 static void
1484 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1485     vm_size_t sz)
1486 {
1487 
1488 	/*
1489 	 * This is much trickier than on older systems because
1490 	 * we can't sync the icache on physical addresses directly
1491 	 * without a direct map. Instead we check a couple of cases
1492 	 * where the memory is already mapped in and, failing that,
1493 	 * use the same trick we use for page zeroing to create
1494 	 * a temporary mapping for this physical address.
1495 	 */
1496 
1497 	if (!pmap_bootstrapped) {
1498 		/*
1499 		 * If PMAP is not bootstrapped, we are likely to be
1500 		 * in real mode.
1501 		 */
1502 		__syncicache((void *)(uintptr_t)pa, sz);
1503 	} else if (pmap == kernel_pmap) {
1504 		__syncicache((void *)va, sz);
1505 	} else if (hw_direct_map) {
1506 		__syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz);
1507 	} else {
1508 		/* Use the scratch page to set up a temp mapping */
1509 
1510 		mtx_lock(&moea64_scratchpage_mtx);
1511 
1512 		moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1513 		__syncicache((void *)(moea64_scratchpage_va[1] +
1514 		    (va & ADDR_POFF)), sz);
1515 
1516 		mtx_unlock(&moea64_scratchpage_mtx);
1517 	}
1518 }
1519 
1520 /*
1521  * Maps a sequence of resident pages belonging to the same object.
1522  * The sequence begins with the given page m_start.  This page is
1523  * mapped at the given virtual address start.  Each subsequent page is
1524  * mapped at a virtual address that is offset from start by the same
1525  * amount as the page is offset from m_start within the object.  The
1526  * last page in the sequence is the page with the largest offset from
1527  * m_start that can be mapped at a virtual address less than the given
1528  * virtual address end.  Not every virtual page between start and end
1529  * is mapped; only those for which a resident page exists with the
1530  * corresponding offset from m_start are mapped.
1531  */
1532 void
1533 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1534     vm_page_t m_start, vm_prot_t prot)
1535 {
1536 	vm_page_t m;
1537 	vm_pindex_t diff, psize;
1538 
1539 	VM_OBJECT_ASSERT_LOCKED(m_start->object);
1540 
1541 	psize = atop(end - start);
1542 	m = m_start;
1543 	while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1544 		moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1545 		    (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0);
1546 		m = TAILQ_NEXT(m, listq);
1547 	}
1548 }
1549 
1550 void
1551 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1552     vm_prot_t prot)
1553 {
1554 
1555 	moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1556 	    PMAP_ENTER_NOSLEEP, 0);
1557 }
1558 
1559 vm_paddr_t
1560 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1561 {
1562 	struct	pvo_entry *pvo;
1563 	vm_paddr_t pa;
1564 
1565 	PMAP_LOCK(pm);
1566 	pvo = moea64_pvo_find_va(pm, va);
1567 	if (pvo == NULL)
1568 		pa = 0;
1569 	else
1570 		pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1571 	PMAP_UNLOCK(pm);
1572 
1573 	return (pa);
1574 }
1575 
1576 /*
1577  * Atomically extract and hold the physical page with the given
1578  * pmap and virtual address pair if that mapping permits the given
1579  * protection.
1580  */
1581 vm_page_t
1582 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1583 {
1584 	struct	pvo_entry *pvo;
1585 	vm_page_t m;
1586         vm_paddr_t pa;
1587 
1588 	m = NULL;
1589 	pa = 0;
1590 	PMAP_LOCK(pmap);
1591 retry:
1592 	pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1593 	if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1594 		if (vm_page_pa_tryrelock(pmap,
1595 		    pvo->pvo_pte.pa & LPTE_RPGN, &pa))
1596 			goto retry;
1597 		m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1598 		vm_page_hold(m);
1599 	}
1600 	PA_UNLOCK_COND(pa);
1601 	PMAP_UNLOCK(pmap);
1602 	return (m);
1603 }
1604 
1605 static mmu_t installed_mmu;
1606 
1607 static void *
1608 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1609     uint8_t *flags, int wait)
1610 {
1611 	struct pvo_entry *pvo;
1612         vm_offset_t va;
1613         vm_page_t m;
1614         int needed_lock;
1615 
1616 	/*
1617 	 * This entire routine is a horrible hack to avoid bothering kmem
1618 	 * for new KVA addresses. Because this can get called from inside
1619 	 * kmem allocation routines, calling kmem for a new address here
1620 	 * can lead to multiply locking non-recursive mutexes.
1621 	 */
1622 
1623 	*flags = UMA_SLAB_PRIV;
1624 	needed_lock = !PMAP_LOCKED(kernel_pmap);
1625 
1626 	m = vm_page_alloc_domain(NULL, 0, domain,
1627 	    malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ);
1628 	if (m == NULL)
1629 		return (NULL);
1630 
1631 	va = VM_PAGE_TO_PHYS(m);
1632 
1633 	pvo = alloc_pvo_entry(1 /* bootstrap */);
1634 
1635 	pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1636 	pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1637 
1638 	if (needed_lock)
1639 		PMAP_LOCK(kernel_pmap);
1640 
1641 	init_pvo_entry(pvo, kernel_pmap, va);
1642 	pvo->pvo_vaddr |= PVO_WIRED;
1643 
1644 	moea64_pvo_enter(installed_mmu, pvo, NULL);
1645 
1646 	if (needed_lock)
1647 		PMAP_UNLOCK(kernel_pmap);
1648 
1649 	if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1650                 bzero((void *)va, PAGE_SIZE);
1651 
1652 	return (void *)va;
1653 }
1654 
1655 extern int elf32_nxstack;
1656 
1657 void
1658 moea64_init(mmu_t mmu)
1659 {
1660 
1661 	CTR0(KTR_PMAP, "moea64_init");
1662 
1663 	moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1664 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1665 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1666 
1667 	if (!hw_direct_map) {
1668 		installed_mmu = mmu;
1669 		uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1670 	}
1671 
1672 #ifdef COMPAT_FREEBSD32
1673 	elf32_nxstack = 1;
1674 #endif
1675 
1676 	moea64_initialized = TRUE;
1677 }
1678 
1679 boolean_t
1680 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1681 {
1682 
1683 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1684 	    ("moea64_is_referenced: page %p is not managed", m));
1685 
1686 	return (moea64_query_bit(mmu, m, LPTE_REF));
1687 }
1688 
1689 boolean_t
1690 moea64_is_modified(mmu_t mmu, vm_page_t m)
1691 {
1692 
1693 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1694 	    ("moea64_is_modified: page %p is not managed", m));
1695 
1696 	/*
1697 	 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1698 	 * concurrently set while the object is locked.  Thus, if PGA_WRITEABLE
1699 	 * is clear, no PTEs can have LPTE_CHG set.
1700 	 */
1701 	VM_OBJECT_ASSERT_LOCKED(m->object);
1702 	if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1703 		return (FALSE);
1704 	return (moea64_query_bit(mmu, m, LPTE_CHG));
1705 }
1706 
1707 boolean_t
1708 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1709 {
1710 	struct pvo_entry *pvo;
1711 	boolean_t rv = TRUE;
1712 
1713 	PMAP_LOCK(pmap);
1714 	pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1715 	if (pvo != NULL)
1716 		rv = FALSE;
1717 	PMAP_UNLOCK(pmap);
1718 	return (rv);
1719 }
1720 
1721 void
1722 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1723 {
1724 
1725 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1726 	    ("moea64_clear_modify: page %p is not managed", m));
1727 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1728 	KASSERT(!vm_page_xbusied(m),
1729 	    ("moea64_clear_modify: page %p is exclusive busied", m));
1730 
1731 	/*
1732 	 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1733 	 * set.  If the object containing the page is locked and the page is
1734 	 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1735 	 */
1736 	if ((m->aflags & PGA_WRITEABLE) == 0)
1737 		return;
1738 	moea64_clear_bit(mmu, m, LPTE_CHG);
1739 }
1740 
1741 /*
1742  * Clear the write and modified bits in each of the given page's mappings.
1743  */
1744 void
1745 moea64_remove_write(mmu_t mmu, vm_page_t m)
1746 {
1747 	struct	pvo_entry *pvo;
1748 	int64_t	refchg, ret;
1749 	pmap_t	pmap;
1750 
1751 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1752 	    ("moea64_remove_write: page %p is not managed", m));
1753 
1754 	/*
1755 	 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1756 	 * set by another thread while the object is locked.  Thus,
1757 	 * if PGA_WRITEABLE is clear, no page table entries need updating.
1758 	 */
1759 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1760 	if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1761 		return;
1762 	powerpc_sync();
1763 	PV_PAGE_LOCK(m);
1764 	refchg = 0;
1765 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1766 		pmap = pvo->pvo_pmap;
1767 		PMAP_LOCK(pmap);
1768 		if (!(pvo->pvo_vaddr & PVO_DEAD) &&
1769 		    (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1770 			pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
1771 			ret = MOEA64_PTE_REPLACE(mmu, pvo,
1772 			    MOEA64_PTE_PROT_UPDATE);
1773 			if (ret < 0)
1774 				ret = LPTE_CHG;
1775 			refchg |= ret;
1776 			if (pvo->pvo_pmap == kernel_pmap)
1777 				isync();
1778 		}
1779 		PMAP_UNLOCK(pmap);
1780 	}
1781 	if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
1782 		vm_page_dirty(m);
1783 	vm_page_aflag_clear(m, PGA_WRITEABLE);
1784 	PV_PAGE_UNLOCK(m);
1785 }
1786 
1787 /*
1788  *	moea64_ts_referenced:
1789  *
1790  *	Return a count of reference bits for a page, clearing those bits.
1791  *	It is not necessary for every reference bit to be cleared, but it
1792  *	is necessary that 0 only be returned when there are truly no
1793  *	reference bits set.
1794  *
1795  *	XXX: The exact number of bits to check and clear is a matter that
1796  *	should be tested and standardized at some point in the future for
1797  *	optimal aging of shared pages.
1798  */
1799 int
1800 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1801 {
1802 
1803 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1804 	    ("moea64_ts_referenced: page %p is not managed", m));
1805 	return (moea64_clear_bit(mmu, m, LPTE_REF));
1806 }
1807 
1808 /*
1809  * Modify the WIMG settings of all mappings for a page.
1810  */
1811 void
1812 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1813 {
1814 	struct	pvo_entry *pvo;
1815 	int64_t	refchg;
1816 	pmap_t	pmap;
1817 	uint64_t lo;
1818 
1819 	if ((m->oflags & VPO_UNMANAGED) != 0) {
1820 		m->md.mdpg_cache_attrs = ma;
1821 		return;
1822 	}
1823 
1824 	lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1825 
1826 	PV_PAGE_LOCK(m);
1827 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1828 		pmap = pvo->pvo_pmap;
1829 		PMAP_LOCK(pmap);
1830 		if (!(pvo->pvo_vaddr & PVO_DEAD)) {
1831 			pvo->pvo_pte.pa &= ~LPTE_WIMG;
1832 			pvo->pvo_pte.pa |= lo;
1833 			refchg = MOEA64_PTE_REPLACE(mmu, pvo,
1834 			    MOEA64_PTE_INVALIDATE);
1835 			if (refchg < 0)
1836 				refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
1837 				    LPTE_CHG : 0;
1838 			if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1839 			    (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1840 				refchg |=
1841 				    atomic_readandclear_32(&m->md.mdpg_attrs);
1842 				if (refchg & LPTE_CHG)
1843 					vm_page_dirty(m);
1844 				if (refchg & LPTE_REF)
1845 					vm_page_aflag_set(m, PGA_REFERENCED);
1846 			}
1847 			if (pvo->pvo_pmap == kernel_pmap)
1848 				isync();
1849 		}
1850 		PMAP_UNLOCK(pmap);
1851 	}
1852 	m->md.mdpg_cache_attrs = ma;
1853 	PV_PAGE_UNLOCK(m);
1854 }
1855 
1856 /*
1857  * Map a wired page into kernel virtual address space.
1858  */
1859 void
1860 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1861 {
1862 	int		error;
1863 	struct pvo_entry *pvo, *oldpvo;
1864 
1865 	pvo = alloc_pvo_entry(0);
1866 	pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
1867 	pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
1868 	pvo->pvo_vaddr |= PVO_WIRED;
1869 
1870 	PMAP_LOCK(kernel_pmap);
1871 	oldpvo = moea64_pvo_find_va(kernel_pmap, va);
1872 	if (oldpvo != NULL)
1873 		moea64_pvo_remove_from_pmap(mmu, oldpvo);
1874 	init_pvo_entry(pvo, kernel_pmap, va);
1875 	error = moea64_pvo_enter(mmu, pvo, NULL);
1876 	PMAP_UNLOCK(kernel_pmap);
1877 
1878 	/* Free any dead pages */
1879 	if (oldpvo != NULL) {
1880 		PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1881 		moea64_pvo_remove_from_page(mmu, oldpvo);
1882 		PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1883 		free_pvo_entry(oldpvo);
1884 	}
1885 
1886 	if (error != 0 && error != ENOENT)
1887 		panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va,
1888 		    (uintmax_t)pa, error);
1889 }
1890 
1891 void
1892 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1893 {
1894 
1895 	moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1896 }
1897 
1898 /*
1899  * Extract the physical page address associated with the given kernel virtual
1900  * address.
1901  */
1902 vm_paddr_t
1903 moea64_kextract(mmu_t mmu, vm_offset_t va)
1904 {
1905 	struct		pvo_entry *pvo;
1906 	vm_paddr_t pa;
1907 
1908 	/*
1909 	 * Shortcut the direct-mapped case when applicable.  We never put
1910 	 * anything but 1:1 (or 62-bit aliased) mappings below
1911 	 * VM_MIN_KERNEL_ADDRESS.
1912 	 */
1913 	if (va < VM_MIN_KERNEL_ADDRESS)
1914 		return (va & ~DMAP_BASE_ADDRESS);
1915 
1916 	PMAP_LOCK(kernel_pmap);
1917 	pvo = moea64_pvo_find_va(kernel_pmap, va);
1918 	KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1919 	    va));
1920 	pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1921 	PMAP_UNLOCK(kernel_pmap);
1922 	return (pa);
1923 }
1924 
1925 /*
1926  * Remove a wired page from kernel virtual address space.
1927  */
1928 void
1929 moea64_kremove(mmu_t mmu, vm_offset_t va)
1930 {
1931 	moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1932 }
1933 
1934 /*
1935  * Provide a kernel pointer corresponding to a given userland pointer.
1936  * The returned pointer is valid until the next time this function is
1937  * called in this thread. This is used internally in copyin/copyout.
1938  */
1939 static int
1940 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1941     void **kaddr, size_t ulen, size_t *klen)
1942 {
1943 	size_t l;
1944 #ifdef __powerpc64__
1945 	struct slb *slb;
1946 #endif
1947 	register_t slbv;
1948 
1949 	*kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1950 	l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1951 	if (l > ulen)
1952 		l = ulen;
1953 	if (klen)
1954 		*klen = l;
1955 	else if (l != ulen)
1956 		return (EFAULT);
1957 
1958 #ifdef __powerpc64__
1959 	/* Try lockless look-up first */
1960 	slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
1961 
1962 	if (slb == NULL) {
1963 		/* If it isn't there, we need to pre-fault the VSID */
1964 		PMAP_LOCK(pm);
1965 		slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
1966 		PMAP_UNLOCK(pm);
1967 	} else {
1968 		slbv = slb->slbv;
1969 	}
1970 
1971 	/* Mark segment no-execute */
1972 	slbv |= SLBV_N;
1973 #else
1974 	slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
1975 
1976 	/* Mark segment no-execute */
1977 	slbv |= SR_N;
1978 #endif
1979 
1980 	/* If we have already set this VSID, we can just return */
1981 	if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
1982 		return (0);
1983 
1984 	__asm __volatile("isync");
1985 	curthread->td_pcb->pcb_cpu.aim.usr_segm =
1986 	    (uintptr_t)uaddr >> ADDR_SR_SHFT;
1987 	curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
1988 #ifdef __powerpc64__
1989 	__asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
1990 	    "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
1991 #else
1992 	__asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
1993 #endif
1994 
1995 	return (0);
1996 }
1997 
1998 /*
1999  * Figure out where a given kernel pointer (usually in a fault) points
2000  * to from the VM's perspective, potentially remapping into userland's
2001  * address space.
2002  */
2003 static int
2004 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
2005     vm_offset_t *decoded_addr)
2006 {
2007 	vm_offset_t user_sr;
2008 
2009 	if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
2010 		user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm;
2011 		addr &= ADDR_PIDX | ADDR_POFF;
2012 		addr |= user_sr << ADDR_SR_SHFT;
2013 		*decoded_addr = addr;
2014 		*is_user = 1;
2015 	} else {
2016 		*decoded_addr = addr;
2017 		*is_user = 0;
2018 	}
2019 
2020 	return (0);
2021 }
2022 
2023 /*
2024  * Map a range of physical addresses into kernel virtual address space.
2025  *
2026  * The value passed in *virt is a suggested virtual address for the mapping.
2027  * Architectures which can support a direct-mapped physical to virtual region
2028  * can return the appropriate address within that region, leaving '*virt'
2029  * unchanged.  Other architectures should map the pages starting at '*virt' and
2030  * update '*virt' with the first usable address after the mapped region.
2031  */
2032 vm_offset_t
2033 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2034     vm_paddr_t pa_end, int prot)
2035 {
2036 	vm_offset_t	sva, va;
2037 
2038 	if (hw_direct_map) {
2039 		/*
2040 		 * Check if every page in the region is covered by the direct
2041 		 * map. The direct map covers all of physical memory. Use
2042 		 * moea64_calc_wimg() as a shortcut to see if the page is in
2043 		 * physical memory as a way to see if the direct map covers it.
2044 		 */
2045 		for (va = pa_start; va < pa_end; va += PAGE_SIZE)
2046 			if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
2047 				break;
2048 		if (va == pa_end)
2049 			return (PHYS_TO_DMAP(pa_start));
2050 	}
2051 	sva = *virt;
2052 	va = sva;
2053 	/* XXX respect prot argument */
2054 	for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
2055 		moea64_kenter(mmu, va, pa_start);
2056 	*virt = va;
2057 
2058 	return (sva);
2059 }
2060 
2061 /*
2062  * Returns true if the pmap's pv is one of the first
2063  * 16 pvs linked to from this page.  This count may
2064  * be changed upwards or downwards in the future; it
2065  * is only necessary that true be returned for a small
2066  * subset of pmaps for proper page aging.
2067  */
2068 boolean_t
2069 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2070 {
2071         int loops;
2072 	struct pvo_entry *pvo;
2073 	boolean_t rv;
2074 
2075 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2076 	    ("moea64_page_exists_quick: page %p is not managed", m));
2077 	loops = 0;
2078 	rv = FALSE;
2079 	PV_PAGE_LOCK(m);
2080 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2081 		if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
2082 			rv = TRUE;
2083 			break;
2084 		}
2085 		if (++loops >= 16)
2086 			break;
2087 	}
2088 	PV_PAGE_UNLOCK(m);
2089 	return (rv);
2090 }
2091 
2092 void
2093 moea64_page_init(mmu_t mmu __unused, vm_page_t m)
2094 {
2095 
2096 	m->md.mdpg_attrs = 0;
2097 	m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
2098 	LIST_INIT(&m->md.mdpg_pvoh);
2099 }
2100 
2101 /*
2102  * Return the number of managed mappings to the given physical page
2103  * that are wired.
2104  */
2105 int
2106 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
2107 {
2108 	struct pvo_entry *pvo;
2109 	int count;
2110 
2111 	count = 0;
2112 	if ((m->oflags & VPO_UNMANAGED) != 0)
2113 		return (count);
2114 	PV_PAGE_LOCK(m);
2115 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
2116 		if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2117 			count++;
2118 	PV_PAGE_UNLOCK(m);
2119 	return (count);
2120 }
2121 
2122 static uintptr_t	moea64_vsidcontext;
2123 
2124 uintptr_t
2125 moea64_get_unique_vsid(void) {
2126 	u_int entropy;
2127 	register_t hash;
2128 	uint32_t mask;
2129 	int i;
2130 
2131 	entropy = 0;
2132 	__asm __volatile("mftb %0" : "=r"(entropy));
2133 
2134 	mtx_lock(&moea64_slb_mutex);
2135 	for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2136 		u_int	n;
2137 
2138 		/*
2139 		 * Create a new value by mutiplying by a prime and adding in
2140 		 * entropy from the timebase register.  This is to make the
2141 		 * VSID more random so that the PT hash function collides
2142 		 * less often.  (Note that the prime casues gcc to do shifts
2143 		 * instead of a multiply.)
2144 		 */
2145 		moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2146 		hash = moea64_vsidcontext & (NVSIDS - 1);
2147 		if (hash == 0)		/* 0 is special, avoid it */
2148 			continue;
2149 		n = hash >> 5;
2150 		mask = 1 << (hash & (VSID_NBPW - 1));
2151 		hash = (moea64_vsidcontext & VSID_HASHMASK);
2152 		if (moea64_vsid_bitmap[n] & mask) {	/* collision? */
2153 			/* anything free in this bucket? */
2154 			if (moea64_vsid_bitmap[n] == 0xffffffff) {
2155 				entropy = (moea64_vsidcontext >> 20);
2156 				continue;
2157 			}
2158 			i = ffs(~moea64_vsid_bitmap[n]) - 1;
2159 			mask = 1 << i;
2160 			hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2161 			hash |= i;
2162 		}
2163 		if (hash == VSID_VRMA)	/* also special, avoid this too */
2164 			continue;
2165 		KASSERT(!(moea64_vsid_bitmap[n] & mask),
2166 		    ("Allocating in-use VSID %#zx\n", hash));
2167 		moea64_vsid_bitmap[n] |= mask;
2168 		mtx_unlock(&moea64_slb_mutex);
2169 		return (hash);
2170 	}
2171 
2172 	mtx_unlock(&moea64_slb_mutex);
2173 	panic("%s: out of segments",__func__);
2174 }
2175 
2176 #ifdef __powerpc64__
2177 void
2178 moea64_pinit(mmu_t mmu, pmap_t pmap)
2179 {
2180 
2181 	RB_INIT(&pmap->pmap_pvo);
2182 
2183 	pmap->pm_slb_tree_root = slb_alloc_tree();
2184 	pmap->pm_slb = slb_alloc_user_cache();
2185 	pmap->pm_slb_len = 0;
2186 }
2187 #else
2188 void
2189 moea64_pinit(mmu_t mmu, pmap_t pmap)
2190 {
2191 	int	i;
2192 	uint32_t hash;
2193 
2194 	RB_INIT(&pmap->pmap_pvo);
2195 
2196 	if (pmap_bootstrapped)
2197 		pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
2198 		    (vm_offset_t)pmap);
2199 	else
2200 		pmap->pmap_phys = pmap;
2201 
2202 	/*
2203 	 * Allocate some segment registers for this pmap.
2204 	 */
2205 	hash = moea64_get_unique_vsid();
2206 
2207 	for (i = 0; i < 16; i++)
2208 		pmap->pm_sr[i] = VSID_MAKE(i, hash);
2209 
2210 	KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2211 }
2212 #endif
2213 
2214 /*
2215  * Initialize the pmap associated with process 0.
2216  */
2217 void
2218 moea64_pinit0(mmu_t mmu, pmap_t pm)
2219 {
2220 
2221 	PMAP_LOCK_INIT(pm);
2222 	moea64_pinit(mmu, pm);
2223 	bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2224 }
2225 
2226 /*
2227  * Set the physical protection on the specified range of this map as requested.
2228  */
2229 static void
2230 moea64_pvo_protect(mmu_t mmu,  pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2231 {
2232 	struct vm_page *pg;
2233 	vm_prot_t oldprot;
2234 	int32_t refchg;
2235 
2236 	PMAP_LOCK_ASSERT(pm, MA_OWNED);
2237 
2238 	/*
2239 	 * Change the protection of the page.
2240 	 */
2241 	oldprot = pvo->pvo_pte.prot;
2242 	pvo->pvo_pte.prot = prot;
2243 	pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2244 
2245 	/*
2246 	 * If the PVO is in the page table, update mapping
2247 	 */
2248 	refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE);
2249 	if (refchg < 0)
2250 		refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2251 
2252 	if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2253 	    (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2254 		if ((pg->oflags & VPO_UNMANAGED) == 0)
2255 			vm_page_aflag_set(pg, PGA_EXECUTABLE);
2256 		moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2257 		    pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE);
2258 	}
2259 
2260 	/*
2261 	 * Update vm about the REF/CHG bits if the page is managed and we have
2262 	 * removed write access.
2263 	 */
2264 	if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2265 	    (oldprot & VM_PROT_WRITE)) {
2266 		refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2267 		if (refchg & LPTE_CHG)
2268 			vm_page_dirty(pg);
2269 		if (refchg & LPTE_REF)
2270 			vm_page_aflag_set(pg, PGA_REFERENCED);
2271 	}
2272 }
2273 
2274 void
2275 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2276     vm_prot_t prot)
2277 {
2278 	struct	pvo_entry *pvo, *tpvo, key;
2279 
2280 	CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2281 	    sva, eva, prot);
2282 
2283 	KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2284 	    ("moea64_protect: non current pmap"));
2285 
2286 	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2287 		moea64_remove(mmu, pm, sva, eva);
2288 		return;
2289 	}
2290 
2291 	PMAP_LOCK(pm);
2292 	key.pvo_vaddr = sva;
2293 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2294 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2295 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2296 		moea64_pvo_protect(mmu, pm, pvo, prot);
2297 	}
2298 	PMAP_UNLOCK(pm);
2299 }
2300 
2301 /*
2302  * Map a list of wired pages into kernel virtual address space.  This is
2303  * intended for temporary mappings which do not need page modification or
2304  * references recorded.  Existing mappings in the region are overwritten.
2305  */
2306 void
2307 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2308 {
2309 	while (count-- > 0) {
2310 		moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2311 		va += PAGE_SIZE;
2312 		m++;
2313 	}
2314 }
2315 
2316 /*
2317  * Remove page mappings from kernel virtual address space.  Intended for
2318  * temporary mappings entered by moea64_qenter.
2319  */
2320 void
2321 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2322 {
2323 	while (count-- > 0) {
2324 		moea64_kremove(mmu, va);
2325 		va += PAGE_SIZE;
2326 	}
2327 }
2328 
2329 void
2330 moea64_release_vsid(uint64_t vsid)
2331 {
2332 	int idx, mask;
2333 
2334 	mtx_lock(&moea64_slb_mutex);
2335 	idx = vsid & (NVSIDS-1);
2336 	mask = 1 << (idx % VSID_NBPW);
2337 	idx /= VSID_NBPW;
2338 	KASSERT(moea64_vsid_bitmap[idx] & mask,
2339 	    ("Freeing unallocated VSID %#jx", vsid));
2340 	moea64_vsid_bitmap[idx] &= ~mask;
2341 	mtx_unlock(&moea64_slb_mutex);
2342 }
2343 
2344 
2345 void
2346 moea64_release(mmu_t mmu, pmap_t pmap)
2347 {
2348 
2349 	/*
2350 	 * Free segment registers' VSIDs
2351 	 */
2352     #ifdef __powerpc64__
2353 	slb_free_tree(pmap);
2354 	slb_free_user_cache(pmap->pm_slb);
2355     #else
2356 	KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2357 
2358 	moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2359     #endif
2360 }
2361 
2362 /*
2363  * Remove all pages mapped by the specified pmap
2364  */
2365 void
2366 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2367 {
2368 	struct pvo_entry *pvo, *tpvo;
2369 	struct pvo_tree tofree;
2370 
2371 	RB_INIT(&tofree);
2372 
2373 	PMAP_LOCK(pm);
2374 	RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2375 		if (pvo->pvo_vaddr & PVO_WIRED)
2376 			continue;
2377 
2378 		/*
2379 		 * For locking reasons, remove this from the page table and
2380 		 * pmap, but save delinking from the vm_page for a second
2381 		 * pass
2382 		 */
2383 		moea64_pvo_remove_from_pmap(mmu, pvo);
2384 		RB_INSERT(pvo_tree, &tofree, pvo);
2385 	}
2386 	PMAP_UNLOCK(pm);
2387 
2388 	RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2389 		PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2390 		moea64_pvo_remove_from_page(mmu, pvo);
2391 		PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2392 		RB_REMOVE(pvo_tree, &tofree, pvo);
2393 		free_pvo_entry(pvo);
2394 	}
2395 }
2396 
2397 /*
2398  * Remove the given range of addresses from the specified map.
2399  */
2400 void
2401 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2402 {
2403 	struct  pvo_entry *pvo, *tpvo, key;
2404 	struct pvo_tree tofree;
2405 
2406 	/*
2407 	 * Perform an unsynchronized read.  This is, however, safe.
2408 	 */
2409 	if (pm->pm_stats.resident_count == 0)
2410 		return;
2411 
2412 	key.pvo_vaddr = sva;
2413 
2414 	RB_INIT(&tofree);
2415 
2416 	PMAP_LOCK(pm);
2417 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2418 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2419 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2420 
2421 		/*
2422 		 * For locking reasons, remove this from the page table and
2423 		 * pmap, but save delinking from the vm_page for a second
2424 		 * pass
2425 		 */
2426 		moea64_pvo_remove_from_pmap(mmu, pvo);
2427 		RB_INSERT(pvo_tree, &tofree, pvo);
2428 	}
2429 	PMAP_UNLOCK(pm);
2430 
2431 	RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2432 		PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2433 		moea64_pvo_remove_from_page(mmu, pvo);
2434 		PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2435 		RB_REMOVE(pvo_tree, &tofree, pvo);
2436 		free_pvo_entry(pvo);
2437 	}
2438 }
2439 
2440 /*
2441  * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2442  * will reflect changes in pte's back to the vm_page.
2443  */
2444 void
2445 moea64_remove_all(mmu_t mmu, vm_page_t m)
2446 {
2447 	struct	pvo_entry *pvo, *next_pvo;
2448 	struct	pvo_head freequeue;
2449 	int	wasdead;
2450 	pmap_t	pmap;
2451 
2452 	LIST_INIT(&freequeue);
2453 
2454 	PV_PAGE_LOCK(m);
2455 	LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2456 		pmap = pvo->pvo_pmap;
2457 		PMAP_LOCK(pmap);
2458 		wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2459 		if (!wasdead)
2460 			moea64_pvo_remove_from_pmap(mmu, pvo);
2461 		moea64_pvo_remove_from_page(mmu, pvo);
2462 		if (!wasdead)
2463 			LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2464 		PMAP_UNLOCK(pmap);
2465 
2466 	}
2467 	KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2468 	KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable"));
2469 	PV_PAGE_UNLOCK(m);
2470 
2471 	/* Clean up UMA allocations */
2472 	LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2473 		free_pvo_entry(pvo);
2474 }
2475 
2476 /*
2477  * Allocate a physical page of memory directly from the phys_avail map.
2478  * Can only be called from moea64_bootstrap before avail start and end are
2479  * calculated.
2480  */
2481 vm_offset_t
2482 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align)
2483 {
2484 	vm_offset_t	s, e;
2485 	int		i, j;
2486 
2487 	size = round_page(size);
2488 	for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2489 		if (align != 0)
2490 			s = roundup2(phys_avail[i], align);
2491 		else
2492 			s = phys_avail[i];
2493 		e = s + size;
2494 
2495 		if (s < phys_avail[i] || e > phys_avail[i + 1])
2496 			continue;
2497 
2498 		if (s + size > platform_real_maxaddr())
2499 			continue;
2500 
2501 		if (s == phys_avail[i]) {
2502 			phys_avail[i] += size;
2503 		} else if (e == phys_avail[i + 1]) {
2504 			phys_avail[i + 1] -= size;
2505 		} else {
2506 			for (j = phys_avail_count * 2; j > i; j -= 2) {
2507 				phys_avail[j] = phys_avail[j - 2];
2508 				phys_avail[j + 1] = phys_avail[j - 1];
2509 			}
2510 
2511 			phys_avail[i + 3] = phys_avail[i + 1];
2512 			phys_avail[i + 1] = s;
2513 			phys_avail[i + 2] = e;
2514 			phys_avail_count++;
2515 		}
2516 
2517 		return (s);
2518 	}
2519 	panic("moea64_bootstrap_alloc: could not allocate memory");
2520 }
2521 
2522 static int
2523 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head)
2524 {
2525 	int first, err;
2526 
2527 	PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2528 	KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL,
2529 	    ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo)));
2530 
2531 	moea64_pvo_enter_calls++;
2532 
2533 	/*
2534 	 * Add to pmap list
2535 	 */
2536 	RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2537 
2538 	/*
2539 	 * Remember if the list was empty and therefore will be the first
2540 	 * item.
2541 	 */
2542 	if (pvo_head != NULL) {
2543 		if (LIST_FIRST(pvo_head) == NULL)
2544 			first = 1;
2545 		LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2546 	}
2547 
2548 	if (pvo->pvo_vaddr & PVO_WIRED)
2549 		pvo->pvo_pmap->pm_stats.wired_count++;
2550 	pvo->pvo_pmap->pm_stats.resident_count++;
2551 
2552 	/*
2553 	 * Insert it into the hardware page table
2554 	 */
2555 	err = MOEA64_PTE_INSERT(mmu, pvo);
2556 	if (err != 0) {
2557 		panic("moea64_pvo_enter: overflow");
2558 	}
2559 
2560 	moea64_pvo_entries++;
2561 
2562 	if (pvo->pvo_pmap == kernel_pmap)
2563 		isync();
2564 
2565 #ifdef __powerpc64__
2566 	/*
2567 	 * Make sure all our bootstrap mappings are in the SLB as soon
2568 	 * as virtual memory is switched on.
2569 	 */
2570 	if (!pmap_bootstrapped)
2571 		moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2572 		    pvo->pvo_vaddr & PVO_LARGE);
2573 #endif
2574 
2575 	return (first ? ENOENT : 0);
2576 }
2577 
2578 static void
2579 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo)
2580 {
2581 	struct	vm_page *pg;
2582 	int32_t refchg;
2583 
2584 	KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2585 	PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2586 	KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2587 
2588 	/*
2589 	 * If there is an active pte entry, we need to deactivate it
2590 	 */
2591 	refchg = MOEA64_PTE_UNSET(mmu, pvo);
2592 	if (refchg < 0) {
2593 		/*
2594 		 * If it was evicted from the page table, be pessimistic and
2595 		 * dirty the page.
2596 		 */
2597 		if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2598 			refchg = LPTE_CHG;
2599 		else
2600 			refchg = 0;
2601 	}
2602 
2603 	/*
2604 	 * Update our statistics.
2605 	 */
2606 	pvo->pvo_pmap->pm_stats.resident_count--;
2607 	if (pvo->pvo_vaddr & PVO_WIRED)
2608 		pvo->pvo_pmap->pm_stats.wired_count--;
2609 
2610 	/*
2611 	 * Remove this PVO from the pmap list.
2612 	 */
2613 	RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2614 
2615 	/*
2616 	 * Mark this for the next sweep
2617 	 */
2618 	pvo->pvo_vaddr |= PVO_DEAD;
2619 
2620 	/* Send RC bits to VM */
2621 	if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2622 	    (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2623 		pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2624 		if (pg != NULL) {
2625 			refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2626 			if (refchg & LPTE_CHG)
2627 				vm_page_dirty(pg);
2628 			if (refchg & LPTE_REF)
2629 				vm_page_aflag_set(pg, PGA_REFERENCED);
2630 		}
2631 	}
2632 }
2633 
2634 static void
2635 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo)
2636 {
2637 	struct	vm_page *pg;
2638 
2639 	KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
2640 
2641 	/* Use NULL pmaps as a sentinel for races in page deletion */
2642 	if (pvo->pvo_pmap == NULL)
2643 		return;
2644 	pvo->pvo_pmap = NULL;
2645 
2646 	/*
2647 	 * Update vm about page writeability/executability if managed
2648 	 */
2649 	PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN);
2650 	if (pvo->pvo_vaddr & PVO_MANAGED) {
2651 		pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2652 
2653 		if (pg != NULL) {
2654 			LIST_REMOVE(pvo, pvo_vlink);
2655 			if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2656 				vm_page_aflag_clear(pg,
2657 				    PGA_WRITEABLE | PGA_EXECUTABLE);
2658 		}
2659 	}
2660 
2661 	moea64_pvo_entries--;
2662 	moea64_pvo_remove_calls++;
2663 }
2664 
2665 static struct pvo_entry *
2666 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2667 {
2668 	struct pvo_entry key;
2669 
2670 	PMAP_LOCK_ASSERT(pm, MA_OWNED);
2671 
2672 	key.pvo_vaddr = va & ~ADDR_POFF;
2673 	return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2674 }
2675 
2676 static boolean_t
2677 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit)
2678 {
2679 	struct	pvo_entry *pvo;
2680 	int64_t ret;
2681 	boolean_t rv;
2682 
2683 	/*
2684 	 * See if this bit is stored in the page already.
2685 	 */
2686 	if (m->md.mdpg_attrs & ptebit)
2687 		return (TRUE);
2688 
2689 	/*
2690 	 * Examine each PTE.  Sync so that any pending REF/CHG bits are
2691 	 * flushed to the PTEs.
2692 	 */
2693 	rv = FALSE;
2694 	powerpc_sync();
2695 	PV_PAGE_LOCK(m);
2696 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2697 		ret = 0;
2698 
2699 		/*
2700 		 * See if this pvo has a valid PTE.  if so, fetch the
2701 		 * REF/CHG bits from the valid PTE.  If the appropriate
2702 		 * ptebit is set, return success.
2703 		 */
2704 		PMAP_LOCK(pvo->pvo_pmap);
2705 		if (!(pvo->pvo_vaddr & PVO_DEAD))
2706 			ret = MOEA64_PTE_SYNCH(mmu, pvo);
2707 		PMAP_UNLOCK(pvo->pvo_pmap);
2708 
2709 		if (ret > 0) {
2710 			atomic_set_32(&m->md.mdpg_attrs,
2711 			    ret & (LPTE_CHG | LPTE_REF));
2712 			if (ret & ptebit) {
2713 				rv = TRUE;
2714 				break;
2715 			}
2716 		}
2717 	}
2718 	PV_PAGE_UNLOCK(m);
2719 
2720 	return (rv);
2721 }
2722 
2723 static u_int
2724 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2725 {
2726 	u_int	count;
2727 	struct	pvo_entry *pvo;
2728 	int64_t ret;
2729 
2730 	/*
2731 	 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2732 	 * we can reset the right ones).
2733 	 */
2734 	powerpc_sync();
2735 
2736 	/*
2737 	 * For each pvo entry, clear the pte's ptebit.
2738 	 */
2739 	count = 0;
2740 	PV_PAGE_LOCK(m);
2741 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2742 		ret = 0;
2743 
2744 		PMAP_LOCK(pvo->pvo_pmap);
2745 		if (!(pvo->pvo_vaddr & PVO_DEAD))
2746 			ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit);
2747 		PMAP_UNLOCK(pvo->pvo_pmap);
2748 
2749 		if (ret > 0 && (ret & ptebit))
2750 			count++;
2751 	}
2752 	atomic_clear_32(&m->md.mdpg_attrs, ptebit);
2753 	PV_PAGE_UNLOCK(m);
2754 
2755 	return (count);
2756 }
2757 
2758 boolean_t
2759 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2760 {
2761 	struct pvo_entry *pvo, key;
2762 	vm_offset_t ppa;
2763 	int error = 0;
2764 
2765 	if (hw_direct_map && mem_valid(pa, size) == 0)
2766 		return (0);
2767 
2768 	PMAP_LOCK(kernel_pmap);
2769 	ppa = pa & ~ADDR_POFF;
2770 	key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa;
2771 	for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2772 	    ppa < pa + size; ppa += PAGE_SIZE,
2773 	    pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2774 		if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) {
2775 			error = EFAULT;
2776 			break;
2777 		}
2778 	}
2779 	PMAP_UNLOCK(kernel_pmap);
2780 
2781 	return (error);
2782 }
2783 
2784 /*
2785  * Map a set of physical memory pages into the kernel virtual
2786  * address space. Return a pointer to where it is mapped. This
2787  * routine is intended to be used for mapping device memory,
2788  * NOT real memory.
2789  */
2790 void *
2791 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2792 {
2793 	vm_offset_t va, tmpva, ppa, offset;
2794 
2795 	ppa = trunc_page(pa);
2796 	offset = pa & PAGE_MASK;
2797 	size = roundup2(offset + size, PAGE_SIZE);
2798 
2799 	va = kva_alloc(size);
2800 
2801 	if (!va)
2802 		panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2803 
2804 	for (tmpva = va; size > 0;) {
2805 		moea64_kenter_attr(mmu, tmpva, ppa, ma);
2806 		size -= PAGE_SIZE;
2807 		tmpva += PAGE_SIZE;
2808 		ppa += PAGE_SIZE;
2809 	}
2810 
2811 	return ((void *)(va + offset));
2812 }
2813 
2814 void *
2815 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2816 {
2817 
2818 	return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2819 }
2820 
2821 void
2822 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2823 {
2824 	vm_offset_t base, offset;
2825 
2826 	base = trunc_page(va);
2827 	offset = va & PAGE_MASK;
2828 	size = roundup2(offset + size, PAGE_SIZE);
2829 
2830 	kva_free(base, size);
2831 }
2832 
2833 void
2834 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2835 {
2836 	struct pvo_entry *pvo;
2837 	vm_offset_t lim;
2838 	vm_paddr_t pa;
2839 	vm_size_t len;
2840 
2841 	PMAP_LOCK(pm);
2842 	while (sz > 0) {
2843 		lim = round_page(va+1);
2844 		len = MIN(lim - va, sz);
2845 		pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2846 		if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
2847 			pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF);
2848 			moea64_syncicache(mmu, pm, va, pa, len);
2849 		}
2850 		va += len;
2851 		sz -= len;
2852 	}
2853 	PMAP_UNLOCK(pm);
2854 }
2855 
2856 void
2857 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2858 {
2859 
2860 	*va = (void *)(uintptr_t)pa;
2861 }
2862 
2863 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2864 
2865 void
2866 moea64_scan_init(mmu_t mmu)
2867 {
2868 	struct pvo_entry *pvo;
2869 	vm_offset_t va;
2870 	int i;
2871 
2872 	if (!do_minidump) {
2873 		/* Initialize phys. segments for dumpsys(). */
2874 		memset(&dump_map, 0, sizeof(dump_map));
2875 		mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
2876 		for (i = 0; i < pregions_sz; i++) {
2877 			dump_map[i].pa_start = pregions[i].mr_start;
2878 			dump_map[i].pa_size = pregions[i].mr_size;
2879 		}
2880 		return;
2881 	}
2882 
2883 	/* Virtual segments for minidumps: */
2884 	memset(&dump_map, 0, sizeof(dump_map));
2885 
2886 	/* 1st: kernel .data and .bss. */
2887 	dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2888 	dump_map[0].pa_size = round_page((uintptr_t)_end) -
2889 	    dump_map[0].pa_start;
2890 
2891 	/* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2892 	dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr;
2893 	dump_map[1].pa_size = round_page(msgbufp->msg_size);
2894 
2895 	/* 3rd: kernel VM. */
2896 	va = dump_map[1].pa_start + dump_map[1].pa_size;
2897 	/* Find start of next chunk (from va). */
2898 	while (va < virtual_end) {
2899 		/* Don't dump the buffer cache. */
2900 		if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2901 			va = kmi.buffer_eva;
2902 			continue;
2903 		}
2904 		pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2905 		if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2906 			break;
2907 		va += PAGE_SIZE;
2908 	}
2909 	if (va < virtual_end) {
2910 		dump_map[2].pa_start = va;
2911 		va += PAGE_SIZE;
2912 		/* Find last page in chunk. */
2913 		while (va < virtual_end) {
2914 			/* Don't run into the buffer cache. */
2915 			if (va == kmi.buffer_sva)
2916 				break;
2917 			pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2918 			if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD))
2919 				break;
2920 			va += PAGE_SIZE;
2921 		}
2922 		dump_map[2].pa_size = va - dump_map[2].pa_start;
2923 	}
2924 }
2925 
2926