1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_map.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_pageout.h> 81 #include <vm/uma.h> 82 83 #include <machine/_inttypes.h> 84 #include <machine/cpu.h> 85 #include <machine/platform.h> 86 #include <machine/frame.h> 87 #include <machine/md_var.h> 88 #include <machine/psl.h> 89 #include <machine/bat.h> 90 #include <machine/hid.h> 91 #include <machine/pte.h> 92 #include <machine/sr.h> 93 #include <machine/trap.h> 94 #include <machine/mmuvar.h> 95 96 #include "mmu_oea64.h" 97 #include "mmu_if.h" 98 #include "moea64_if.h" 99 100 void moea64_release_vsid(uint64_t vsid); 101 uintptr_t moea64_get_unique_vsid(void); 102 103 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 104 #define ENABLE_TRANS(msr) mtmsr(msr) 105 106 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 107 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 108 #define VSID_HASH_MASK 0x0000007fffffffffULL 109 110 /* 111 * Locking semantics: 112 * 113 * There are two locks of interest: the page locks and the pmap locks, which 114 * protect their individual PVO lists and are locked in that order. The contents 115 * of all PVO entries are protected by the locks of their respective pmaps. 116 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 117 * into any list. 118 * 119 */ 120 121 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 122 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 123 124 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 125 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 126 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 127 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 128 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 129 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 130 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 131 132 struct ofw_map { 133 cell_t om_va; 134 cell_t om_len; 135 uint64_t om_pa; 136 cell_t om_mode; 137 }; 138 139 extern unsigned char _etext[]; 140 extern unsigned char _end[]; 141 142 extern void *slbtrap, *slbtrapend; 143 144 /* 145 * Map of physical memory regions. 146 */ 147 static struct mem_region *regions; 148 static struct mem_region *pregions; 149 static u_int phys_avail_count; 150 static int regions_sz, pregions_sz; 151 152 extern void bs_remap_earlyboot(void); 153 154 /* 155 * Lock for the SLB tables. 156 */ 157 struct mtx moea64_slb_mutex; 158 159 /* 160 * PTEG data. 161 */ 162 u_int moea64_pteg_count; 163 u_int moea64_pteg_mask; 164 165 /* 166 * PVO data. 167 */ 168 169 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 170 171 static struct pvo_entry *moea64_bpvo_pool; 172 static int moea64_bpvo_pool_index = 0; 173 static int moea64_bpvo_pool_size = 327680; 174 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 175 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 176 &moea64_bpvo_pool_index, 0, ""); 177 178 #define VSID_NBPW (sizeof(u_int32_t) * 8) 179 #ifdef __powerpc64__ 180 #define NVSIDS (NPMAPS * 16) 181 #define VSID_HASHMASK 0xffffffffUL 182 #else 183 #define NVSIDS NPMAPS 184 #define VSID_HASHMASK 0xfffffUL 185 #endif 186 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 187 188 static boolean_t moea64_initialized = FALSE; 189 190 /* 191 * Statistics. 192 */ 193 u_int moea64_pte_valid = 0; 194 u_int moea64_pte_overflow = 0; 195 u_int moea64_pvo_entries = 0; 196 u_int moea64_pvo_enter_calls = 0; 197 u_int moea64_pvo_remove_calls = 0; 198 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 199 &moea64_pte_valid, 0, ""); 200 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 201 &moea64_pte_overflow, 0, ""); 202 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 203 &moea64_pvo_entries, 0, ""); 204 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 205 &moea64_pvo_enter_calls, 0, ""); 206 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 207 &moea64_pvo_remove_calls, 0, ""); 208 209 vm_offset_t moea64_scratchpage_va[2]; 210 struct pvo_entry *moea64_scratchpage_pvo[2]; 211 struct mtx moea64_scratchpage_mtx; 212 213 uint64_t moea64_large_page_mask = 0; 214 uint64_t moea64_large_page_size = 0; 215 int moea64_large_page_shift = 0; 216 217 /* 218 * PVO calls. 219 */ 220 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 221 struct pvo_head *pvo_head); 222 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 223 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 224 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 225 226 /* 227 * Utility routines. 228 */ 229 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 230 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 231 static void moea64_kremove(mmu_t, vm_offset_t); 232 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 233 vm_paddr_t pa, vm_size_t sz); 234 static void moea64_pmap_init_qpages(void); 235 236 /* 237 * Kernel MMU interface 238 */ 239 void moea64_clear_modify(mmu_t, vm_page_t); 240 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 241 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 242 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 243 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 244 u_int flags, int8_t psind); 245 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 246 vm_prot_t); 247 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 248 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 249 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 250 void moea64_init(mmu_t); 251 boolean_t moea64_is_modified(mmu_t, vm_page_t); 252 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 253 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 254 int moea64_ts_referenced(mmu_t, vm_page_t); 255 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 256 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 257 void moea64_page_init(mmu_t, vm_page_t); 258 int moea64_page_wired_mappings(mmu_t, vm_page_t); 259 void moea64_pinit(mmu_t, pmap_t); 260 void moea64_pinit0(mmu_t, pmap_t); 261 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 262 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 263 void moea64_qremove(mmu_t, vm_offset_t, int); 264 void moea64_release(mmu_t, pmap_t); 265 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 266 void moea64_remove_pages(mmu_t, pmap_t); 267 void moea64_remove_all(mmu_t, vm_page_t); 268 void moea64_remove_write(mmu_t, vm_page_t); 269 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 270 void moea64_zero_page(mmu_t, vm_page_t); 271 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 272 void moea64_activate(mmu_t, struct thread *); 273 void moea64_deactivate(mmu_t, struct thread *); 274 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 275 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 276 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 277 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 278 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 279 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 280 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 281 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 282 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 283 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 284 void **va); 285 void moea64_scan_init(mmu_t mmu); 286 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 287 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 288 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 289 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 290 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 291 int *is_user, vm_offset_t *decoded_addr); 292 293 294 static mmu_method_t moea64_methods[] = { 295 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 296 MMUMETHOD(mmu_copy_page, moea64_copy_page), 297 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 298 MMUMETHOD(mmu_enter, moea64_enter), 299 MMUMETHOD(mmu_enter_object, moea64_enter_object), 300 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 301 MMUMETHOD(mmu_extract, moea64_extract), 302 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 303 MMUMETHOD(mmu_init, moea64_init), 304 MMUMETHOD(mmu_is_modified, moea64_is_modified), 305 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 306 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 307 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 308 MMUMETHOD(mmu_map, moea64_map), 309 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 310 MMUMETHOD(mmu_page_init, moea64_page_init), 311 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 312 MMUMETHOD(mmu_pinit, moea64_pinit), 313 MMUMETHOD(mmu_pinit0, moea64_pinit0), 314 MMUMETHOD(mmu_protect, moea64_protect), 315 MMUMETHOD(mmu_qenter, moea64_qenter), 316 MMUMETHOD(mmu_qremove, moea64_qremove), 317 MMUMETHOD(mmu_release, moea64_release), 318 MMUMETHOD(mmu_remove, moea64_remove), 319 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 320 MMUMETHOD(mmu_remove_all, moea64_remove_all), 321 MMUMETHOD(mmu_remove_write, moea64_remove_write), 322 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 323 MMUMETHOD(mmu_unwire, moea64_unwire), 324 MMUMETHOD(mmu_zero_page, moea64_zero_page), 325 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 326 MMUMETHOD(mmu_activate, moea64_activate), 327 MMUMETHOD(mmu_deactivate, moea64_deactivate), 328 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 329 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 330 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 331 332 /* Internal interfaces */ 333 MMUMETHOD(mmu_mapdev, moea64_mapdev), 334 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 335 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 336 MMUMETHOD(mmu_kextract, moea64_kextract), 337 MMUMETHOD(mmu_kenter, moea64_kenter), 338 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 339 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 340 MMUMETHOD(mmu_scan_init, moea64_scan_init), 341 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 342 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 343 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 344 345 { 0, 0 } 346 }; 347 348 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 349 350 static struct pvo_head * 351 vm_page_to_pvoh(vm_page_t m) 352 { 353 354 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 355 return (&m->md.mdpg_pvoh); 356 } 357 358 static struct pvo_entry * 359 alloc_pvo_entry(int bootstrap) 360 { 361 struct pvo_entry *pvo; 362 363 if (!moea64_initialized || bootstrap) { 364 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 365 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 366 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 367 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 368 } 369 pvo = &moea64_bpvo_pool[ 370 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 371 bzero(pvo, sizeof(*pvo)); 372 pvo->pvo_vaddr = PVO_BOOTSTRAP; 373 } else { 374 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 375 bzero(pvo, sizeof(*pvo)); 376 } 377 378 return (pvo); 379 } 380 381 382 static void 383 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 384 { 385 uint64_t vsid; 386 uint64_t hash; 387 int shift; 388 389 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 390 391 pvo->pvo_pmap = pmap; 392 va &= ~ADDR_POFF; 393 pvo->pvo_vaddr |= va; 394 vsid = va_to_vsid(pmap, va); 395 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 396 | (vsid << 16); 397 398 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 399 ADDR_PIDX_SHFT; 400 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 401 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 402 } 403 404 static void 405 free_pvo_entry(struct pvo_entry *pvo) 406 { 407 408 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 409 uma_zfree(moea64_pvo_zone, pvo); 410 } 411 412 void 413 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 414 { 415 416 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 417 LPTE_AVPN_MASK; 418 lpte->pte_hi |= LPTE_VALID; 419 420 if (pvo->pvo_vaddr & PVO_LARGE) 421 lpte->pte_hi |= LPTE_BIG; 422 if (pvo->pvo_vaddr & PVO_WIRED) 423 lpte->pte_hi |= LPTE_WIRED; 424 if (pvo->pvo_vaddr & PVO_HID) 425 lpte->pte_hi |= LPTE_HID; 426 427 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 428 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 429 lpte->pte_lo |= LPTE_BW; 430 else 431 lpte->pte_lo |= LPTE_BR; 432 433 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 434 lpte->pte_lo |= LPTE_NOEXEC; 435 } 436 437 static __inline uint64_t 438 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 439 { 440 uint64_t pte_lo; 441 int i; 442 443 if (ma != VM_MEMATTR_DEFAULT) { 444 switch (ma) { 445 case VM_MEMATTR_UNCACHEABLE: 446 return (LPTE_I | LPTE_G); 447 case VM_MEMATTR_CACHEABLE: 448 return (LPTE_M); 449 case VM_MEMATTR_WRITE_COMBINING: 450 case VM_MEMATTR_WRITE_BACK: 451 case VM_MEMATTR_PREFETCHABLE: 452 return (LPTE_I); 453 case VM_MEMATTR_WRITE_THROUGH: 454 return (LPTE_W | LPTE_M); 455 } 456 } 457 458 /* 459 * Assume the page is cache inhibited and access is guarded unless 460 * it's in our available memory array. 461 */ 462 pte_lo = LPTE_I | LPTE_G; 463 for (i = 0; i < pregions_sz; i++) { 464 if ((pa >= pregions[i].mr_start) && 465 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 466 pte_lo &= ~(LPTE_I | LPTE_G); 467 pte_lo |= LPTE_M; 468 break; 469 } 470 } 471 472 return pte_lo; 473 } 474 475 /* 476 * Quick sort callout for comparing memory regions. 477 */ 478 static int om_cmp(const void *a, const void *b); 479 480 static int 481 om_cmp(const void *a, const void *b) 482 { 483 const struct ofw_map *mapa; 484 const struct ofw_map *mapb; 485 486 mapa = a; 487 mapb = b; 488 if (mapa->om_pa < mapb->om_pa) 489 return (-1); 490 else if (mapa->om_pa > mapb->om_pa) 491 return (1); 492 else 493 return (0); 494 } 495 496 static void 497 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 498 { 499 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 500 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 501 struct pvo_entry *pvo; 502 register_t msr; 503 vm_offset_t off; 504 vm_paddr_t pa_base; 505 int i, j; 506 507 bzero(translations, sz); 508 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 509 sizeof(acells)); 510 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 511 panic("moea64_bootstrap: can't get ofw translations"); 512 513 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 514 sz /= sizeof(cell_t); 515 for (i = 0, j = 0; i < sz; j++) { 516 translations[j].om_va = trans_cells[i++]; 517 translations[j].om_len = trans_cells[i++]; 518 translations[j].om_pa = trans_cells[i++]; 519 if (acells == 2) { 520 translations[j].om_pa <<= 32; 521 translations[j].om_pa |= trans_cells[i++]; 522 } 523 translations[j].om_mode = trans_cells[i++]; 524 } 525 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 526 i, sz)); 527 528 sz = j; 529 qsort(translations, sz, sizeof (*translations), om_cmp); 530 531 for (i = 0; i < sz; i++) { 532 pa_base = translations[i].om_pa; 533 #ifndef __powerpc64__ 534 if ((translations[i].om_pa >> 32) != 0) 535 panic("OFW translations above 32-bit boundary!"); 536 #endif 537 538 if (pa_base % PAGE_SIZE) 539 panic("OFW translation not page-aligned (phys)!"); 540 if (translations[i].om_va % PAGE_SIZE) 541 panic("OFW translation not page-aligned (virt)!"); 542 543 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 544 pa_base, translations[i].om_va, translations[i].om_len); 545 546 /* Now enter the pages for this mapping */ 547 548 DISABLE_TRANS(msr); 549 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 550 /* If this address is direct-mapped, skip remapping */ 551 if (hw_direct_map && 552 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 553 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 554 == LPTE_M) 555 continue; 556 557 PMAP_LOCK(kernel_pmap); 558 pvo = moea64_pvo_find_va(kernel_pmap, 559 translations[i].om_va + off); 560 PMAP_UNLOCK(kernel_pmap); 561 if (pvo != NULL) 562 continue; 563 564 moea64_kenter(mmup, translations[i].om_va + off, 565 pa_base + off); 566 } 567 ENABLE_TRANS(msr); 568 } 569 } 570 571 #ifdef __powerpc64__ 572 static void 573 moea64_probe_large_page(void) 574 { 575 uint16_t pvr = mfpvr() >> 16; 576 577 switch (pvr) { 578 case IBM970: 579 case IBM970FX: 580 case IBM970MP: 581 powerpc_sync(); isync(); 582 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 583 powerpc_sync(); isync(); 584 585 /* FALLTHROUGH */ 586 default: 587 if (moea64_large_page_size == 0) { 588 moea64_large_page_size = 0x1000000; /* 16 MB */ 589 moea64_large_page_shift = 24; 590 } 591 } 592 593 moea64_large_page_mask = moea64_large_page_size - 1; 594 } 595 596 static void 597 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 598 { 599 struct slb *cache; 600 struct slb entry; 601 uint64_t esid, slbe; 602 uint64_t i; 603 604 cache = PCPU_GET(aim.slb); 605 esid = va >> ADDR_SR_SHFT; 606 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 607 608 for (i = 0; i < 64; i++) { 609 if (cache[i].slbe == (slbe | i)) 610 return; 611 } 612 613 entry.slbe = slbe; 614 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 615 if (large) 616 entry.slbv |= SLBV_L; 617 618 slb_insert_kernel(entry.slbe, entry.slbv); 619 } 620 #endif 621 622 static void 623 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 624 vm_offset_t kernelend) 625 { 626 struct pvo_entry *pvo; 627 register_t msr; 628 vm_paddr_t pa; 629 vm_offset_t size, off; 630 uint64_t pte_lo; 631 int i; 632 633 if (moea64_large_page_size == 0) 634 hw_direct_map = 0; 635 636 DISABLE_TRANS(msr); 637 if (hw_direct_map) { 638 PMAP_LOCK(kernel_pmap); 639 for (i = 0; i < pregions_sz; i++) { 640 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 641 pregions[i].mr_size; pa += moea64_large_page_size) { 642 pte_lo = LPTE_M; 643 644 pvo = alloc_pvo_entry(1 /* bootstrap */); 645 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 646 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 647 648 /* 649 * Set memory access as guarded if prefetch within 650 * the page could exit the available physmem area. 651 */ 652 if (pa & moea64_large_page_mask) { 653 pa &= moea64_large_page_mask; 654 pte_lo |= LPTE_G; 655 } 656 if (pa + moea64_large_page_size > 657 pregions[i].mr_start + pregions[i].mr_size) 658 pte_lo |= LPTE_G; 659 660 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 661 VM_PROT_EXECUTE; 662 pvo->pvo_pte.pa = pa | pte_lo; 663 moea64_pvo_enter(mmup, pvo, NULL); 664 } 665 } 666 PMAP_UNLOCK(kernel_pmap); 667 } 668 669 /* 670 * Make sure the kernel and BPVO pool stay mapped on systems either 671 * without a direct map or on which the kernel is not already executing 672 * out of the direct-mapped region. 673 */ 674 675 if (!hw_direct_map || kernelstart < DMAP_BASE_ADDRESS) { 676 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 677 pa += PAGE_SIZE) 678 moea64_kenter(mmup, pa, pa); 679 } 680 681 if (!hw_direct_map) { 682 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 683 off = (vm_offset_t)(moea64_bpvo_pool); 684 for (pa = off; pa < off + size; pa += PAGE_SIZE) 685 moea64_kenter(mmup, pa, pa); 686 } 687 ENABLE_TRANS(msr); 688 689 /* 690 * Allow user to override unmapped_buf_allowed for testing. 691 * XXXKIB Only direct map implementation was tested. 692 */ 693 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 694 &unmapped_buf_allowed)) 695 unmapped_buf_allowed = hw_direct_map; 696 } 697 698 void 699 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 700 { 701 int i, j; 702 vm_size_t physsz, hwphyssz; 703 vm_paddr_t kernelphysstart, kernelphysend; 704 705 #ifndef __powerpc64__ 706 /* We don't have a direct map since there is no BAT */ 707 hw_direct_map = 0; 708 709 /* Make sure battable is zero, since we have no BAT */ 710 for (i = 0; i < 16; i++) { 711 battable[i].batu = 0; 712 battable[i].batl = 0; 713 } 714 #else 715 moea64_probe_large_page(); 716 717 /* Use a direct map if we have large page support */ 718 if (moea64_large_page_size > 0) 719 hw_direct_map = 1; 720 else 721 hw_direct_map = 0; 722 723 /* Install trap handlers for SLBs */ 724 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 725 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 726 __syncicache((void *)EXC_DSE, 0x80); 727 __syncicache((void *)EXC_ISE, 0x80); 728 #endif 729 730 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 731 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 732 733 /* Get physical memory regions from firmware */ 734 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 735 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 736 737 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 738 panic("moea64_bootstrap: phys_avail too small"); 739 740 phys_avail_count = 0; 741 physsz = 0; 742 hwphyssz = 0; 743 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 744 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 745 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 746 regions[i].mr_start, regions[i].mr_start + 747 regions[i].mr_size, regions[i].mr_size); 748 if (hwphyssz != 0 && 749 (physsz + regions[i].mr_size) >= hwphyssz) { 750 if (physsz < hwphyssz) { 751 phys_avail[j] = regions[i].mr_start; 752 phys_avail[j + 1] = regions[i].mr_start + 753 hwphyssz - physsz; 754 physsz = hwphyssz; 755 phys_avail_count++; 756 } 757 break; 758 } 759 phys_avail[j] = regions[i].mr_start; 760 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 761 phys_avail_count++; 762 physsz += regions[i].mr_size; 763 } 764 765 /* Check for overlap with the kernel and exception vectors */ 766 for (j = 0; j < 2*phys_avail_count; j+=2) { 767 if (phys_avail[j] < EXC_LAST) 768 phys_avail[j] += EXC_LAST; 769 770 if (kernelphysstart >= phys_avail[j] && 771 kernelphysstart < phys_avail[j+1]) { 772 if (kernelphysend < phys_avail[j+1]) { 773 phys_avail[2*phys_avail_count] = 774 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 775 phys_avail[2*phys_avail_count + 1] = 776 phys_avail[j+1]; 777 phys_avail_count++; 778 } 779 780 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 781 } 782 783 if (kernelphysend >= phys_avail[j] && 784 kernelphysend < phys_avail[j+1]) { 785 if (kernelphysstart > phys_avail[j]) { 786 phys_avail[2*phys_avail_count] = phys_avail[j]; 787 phys_avail[2*phys_avail_count + 1] = 788 kernelphysstart & ~PAGE_MASK; 789 phys_avail_count++; 790 } 791 792 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 793 PAGE_SIZE; 794 } 795 } 796 797 physmem = btoc(physsz); 798 799 #ifdef PTEGCOUNT 800 moea64_pteg_count = PTEGCOUNT; 801 #else 802 moea64_pteg_count = 0x1000; 803 804 while (moea64_pteg_count < physmem) 805 moea64_pteg_count <<= 1; 806 807 moea64_pteg_count >>= 1; 808 #endif /* PTEGCOUNT */ 809 } 810 811 void 812 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 813 { 814 int i; 815 816 /* 817 * Set PTEG mask 818 */ 819 moea64_pteg_mask = moea64_pteg_count - 1; 820 821 /* 822 * Initialize SLB table lock and page locks 823 */ 824 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 825 for (i = 0; i < PV_LOCK_COUNT; i++) 826 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 827 828 /* 829 * Initialise the bootstrap pvo pool. 830 */ 831 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 832 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 833 moea64_bpvo_pool_index = 0; 834 835 /* Place at address usable through the direct map */ 836 if (hw_direct_map) 837 moea64_bpvo_pool = (struct pvo_entry *) 838 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 839 840 /* 841 * Make sure kernel vsid is allocated as well as VSID 0. 842 */ 843 #ifndef __powerpc64__ 844 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 845 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 846 moea64_vsid_bitmap[0] |= 1; 847 #endif 848 849 /* 850 * Initialize the kernel pmap (which is statically allocated). 851 */ 852 #ifdef __powerpc64__ 853 for (i = 0; i < 64; i++) { 854 pcpup->pc_aim.slb[i].slbv = 0; 855 pcpup->pc_aim.slb[i].slbe = 0; 856 } 857 #else 858 for (i = 0; i < 16; i++) 859 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 860 #endif 861 862 kernel_pmap->pmap_phys = kernel_pmap; 863 CPU_FILL(&kernel_pmap->pm_active); 864 RB_INIT(&kernel_pmap->pmap_pvo); 865 866 PMAP_LOCK_INIT(kernel_pmap); 867 868 /* 869 * Now map in all the other buffers we allocated earlier 870 */ 871 872 moea64_setup_direct_map(mmup, kernelstart, kernelend); 873 } 874 875 void 876 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 877 { 878 ihandle_t mmui; 879 phandle_t chosen; 880 phandle_t mmu; 881 ssize_t sz; 882 int i; 883 vm_offset_t pa, va; 884 void *dpcpu; 885 886 /* 887 * Set up the Open Firmware pmap and add its mappings if not in real 888 * mode. 889 */ 890 891 chosen = OF_finddevice("/chosen"); 892 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 893 mmu = OF_instance_to_package(mmui); 894 if (mmu == -1 || 895 (sz = OF_getproplen(mmu, "translations")) == -1) 896 sz = 0; 897 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 898 panic("moea64_bootstrap: too many ofw translations"); 899 900 if (sz > 0) 901 moea64_add_ofw_mappings(mmup, mmu, sz); 902 } 903 904 /* 905 * Calculate the last available physical address. 906 */ 907 Maxmem = 0; 908 for (i = 0; phys_avail[i + 2] != 0; i += 2) 909 Maxmem = max(Maxmem, powerpc_btop(phys_avail[i + 1])); 910 911 /* 912 * Initialize MMU. 913 */ 914 MMU_CPU_BOOTSTRAP(mmup,0); 915 mtmsr(mfmsr() | PSL_DR | PSL_IR); 916 pmap_bootstrapped++; 917 918 /* 919 * Set the start and end of kva. 920 */ 921 virtual_avail = VM_MIN_KERNEL_ADDRESS; 922 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 923 924 /* 925 * Map the entire KVA range into the SLB. We must not fault there. 926 */ 927 #ifdef __powerpc64__ 928 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 929 moea64_bootstrap_slb_prefault(va, 0); 930 #endif 931 932 /* 933 * Remap any early IO mappings (console framebuffer, etc.) 934 */ 935 bs_remap_earlyboot(); 936 937 /* 938 * Figure out how far we can extend virtual_end into segment 16 939 * without running into existing mappings. Segment 16 is guaranteed 940 * to contain neither RAM nor devices (at least on Apple hardware), 941 * but will generally contain some OFW mappings we should not 942 * step on. 943 */ 944 945 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 946 PMAP_LOCK(kernel_pmap); 947 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 948 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 949 virtual_end += PAGE_SIZE; 950 PMAP_UNLOCK(kernel_pmap); 951 #endif 952 953 /* 954 * Allocate a kernel stack with a guard page for thread0 and map it 955 * into the kernel page map. 956 */ 957 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 958 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 959 virtual_avail = va + kstack_pages * PAGE_SIZE; 960 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 961 thread0.td_kstack = va; 962 thread0.td_kstack_pages = kstack_pages; 963 for (i = 0; i < kstack_pages; i++) { 964 moea64_kenter(mmup, va, pa); 965 pa += PAGE_SIZE; 966 va += PAGE_SIZE; 967 } 968 969 /* 970 * Allocate virtual address space for the message buffer. 971 */ 972 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 973 msgbufp = (struct msgbuf *)virtual_avail; 974 va = virtual_avail; 975 virtual_avail += round_page(msgbufsize); 976 while (va < virtual_avail) { 977 moea64_kenter(mmup, va, pa); 978 pa += PAGE_SIZE; 979 va += PAGE_SIZE; 980 } 981 982 /* 983 * Allocate virtual address space for the dynamic percpu area. 984 */ 985 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 986 dpcpu = (void *)virtual_avail; 987 va = virtual_avail; 988 virtual_avail += DPCPU_SIZE; 989 while (va < virtual_avail) { 990 moea64_kenter(mmup, va, pa); 991 pa += PAGE_SIZE; 992 va += PAGE_SIZE; 993 } 994 dpcpu_init(dpcpu, curcpu); 995 996 /* 997 * Allocate some things for page zeroing. We put this directly 998 * in the page table and use MOEA64_PTE_REPLACE to avoid any 999 * of the PVO book-keeping or other parts of the VM system 1000 * from even knowing that this hack exists. 1001 */ 1002 1003 if (!hw_direct_map) { 1004 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1005 MTX_DEF); 1006 for (i = 0; i < 2; i++) { 1007 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1008 virtual_end -= PAGE_SIZE; 1009 1010 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1011 1012 PMAP_LOCK(kernel_pmap); 1013 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1014 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1015 PMAP_UNLOCK(kernel_pmap); 1016 } 1017 } 1018 } 1019 1020 static void 1021 moea64_pmap_init_qpages(void) 1022 { 1023 struct pcpu *pc; 1024 int i; 1025 1026 if (hw_direct_map) 1027 return; 1028 1029 CPU_FOREACH(i) { 1030 pc = pcpu_find(i); 1031 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1032 if (pc->pc_qmap_addr == 0) 1033 panic("pmap_init_qpages: unable to allocate KVA"); 1034 PMAP_LOCK(kernel_pmap); 1035 pc->pc_aim.qmap_pvo = 1036 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1037 PMAP_UNLOCK(kernel_pmap); 1038 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1039 } 1040 } 1041 1042 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1043 1044 /* 1045 * Activate a user pmap. This mostly involves setting some non-CPU 1046 * state. 1047 */ 1048 void 1049 moea64_activate(mmu_t mmu, struct thread *td) 1050 { 1051 pmap_t pm; 1052 1053 pm = &td->td_proc->p_vmspace->vm_pmap; 1054 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1055 1056 #ifdef __powerpc64__ 1057 PCPU_SET(aim.userslb, pm->pm_slb); 1058 __asm __volatile("slbmte %0, %1; isync" :: 1059 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1060 #else 1061 PCPU_SET(curpmap, pm->pmap_phys); 1062 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1063 #endif 1064 } 1065 1066 void 1067 moea64_deactivate(mmu_t mmu, struct thread *td) 1068 { 1069 pmap_t pm; 1070 1071 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1072 1073 pm = &td->td_proc->p_vmspace->vm_pmap; 1074 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1075 #ifdef __powerpc64__ 1076 PCPU_SET(aim.userslb, NULL); 1077 #else 1078 PCPU_SET(curpmap, NULL); 1079 #endif 1080 } 1081 1082 void 1083 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1084 { 1085 struct pvo_entry key, *pvo; 1086 vm_page_t m; 1087 int64_t refchg; 1088 1089 key.pvo_vaddr = sva; 1090 PMAP_LOCK(pm); 1091 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1092 pvo != NULL && PVO_VADDR(pvo) < eva; 1093 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1094 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1095 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1096 pvo); 1097 pvo->pvo_vaddr &= ~PVO_WIRED; 1098 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1099 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1100 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1101 if (refchg < 0) 1102 refchg = LPTE_CHG; 1103 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1104 1105 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1106 if (refchg & LPTE_CHG) 1107 vm_page_dirty(m); 1108 if (refchg & LPTE_REF) 1109 vm_page_aflag_set(m, PGA_REFERENCED); 1110 } 1111 pm->pm_stats.wired_count--; 1112 } 1113 PMAP_UNLOCK(pm); 1114 } 1115 1116 /* 1117 * This goes through and sets the physical address of our 1118 * special scratch PTE to the PA we want to zero or copy. Because 1119 * of locking issues (this can get called in pvo_enter() by 1120 * the UMA allocator), we can't use most other utility functions here 1121 */ 1122 1123 static __inline 1124 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1125 1126 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1127 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1128 1129 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1130 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1131 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1132 MOEA64_PTE_INVALIDATE); 1133 isync(); 1134 } 1135 1136 void 1137 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1138 { 1139 vm_offset_t dst; 1140 vm_offset_t src; 1141 1142 dst = VM_PAGE_TO_PHYS(mdst); 1143 src = VM_PAGE_TO_PHYS(msrc); 1144 1145 if (hw_direct_map) { 1146 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1147 PAGE_SIZE); 1148 } else { 1149 mtx_lock(&moea64_scratchpage_mtx); 1150 1151 moea64_set_scratchpage_pa(mmu, 0, src); 1152 moea64_set_scratchpage_pa(mmu, 1, dst); 1153 1154 bcopy((void *)moea64_scratchpage_va[0], 1155 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1156 1157 mtx_unlock(&moea64_scratchpage_mtx); 1158 } 1159 } 1160 1161 static inline void 1162 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1163 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1164 { 1165 void *a_cp, *b_cp; 1166 vm_offset_t a_pg_offset, b_pg_offset; 1167 int cnt; 1168 1169 while (xfersize > 0) { 1170 a_pg_offset = a_offset & PAGE_MASK; 1171 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1172 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1173 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1174 a_pg_offset; 1175 b_pg_offset = b_offset & PAGE_MASK; 1176 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1177 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1178 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1179 b_pg_offset; 1180 bcopy(a_cp, b_cp, cnt); 1181 a_offset += cnt; 1182 b_offset += cnt; 1183 xfersize -= cnt; 1184 } 1185 } 1186 1187 static inline void 1188 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1189 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1190 { 1191 void *a_cp, *b_cp; 1192 vm_offset_t a_pg_offset, b_pg_offset; 1193 int cnt; 1194 1195 mtx_lock(&moea64_scratchpage_mtx); 1196 while (xfersize > 0) { 1197 a_pg_offset = a_offset & PAGE_MASK; 1198 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1199 moea64_set_scratchpage_pa(mmu, 0, 1200 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1201 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1202 b_pg_offset = b_offset & PAGE_MASK; 1203 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1204 moea64_set_scratchpage_pa(mmu, 1, 1205 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1206 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1207 bcopy(a_cp, b_cp, cnt); 1208 a_offset += cnt; 1209 b_offset += cnt; 1210 xfersize -= cnt; 1211 } 1212 mtx_unlock(&moea64_scratchpage_mtx); 1213 } 1214 1215 void 1216 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1217 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1218 { 1219 1220 if (hw_direct_map) { 1221 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1222 xfersize); 1223 } else { 1224 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1225 xfersize); 1226 } 1227 } 1228 1229 void 1230 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1231 { 1232 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1233 1234 if (size + off > PAGE_SIZE) 1235 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1236 1237 if (hw_direct_map) { 1238 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1239 } else { 1240 mtx_lock(&moea64_scratchpage_mtx); 1241 moea64_set_scratchpage_pa(mmu, 0, pa); 1242 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1243 mtx_unlock(&moea64_scratchpage_mtx); 1244 } 1245 } 1246 1247 /* 1248 * Zero a page of physical memory by temporarily mapping it 1249 */ 1250 void 1251 moea64_zero_page(mmu_t mmu, vm_page_t m) 1252 { 1253 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1254 vm_offset_t va, off; 1255 1256 if (!hw_direct_map) { 1257 mtx_lock(&moea64_scratchpage_mtx); 1258 1259 moea64_set_scratchpage_pa(mmu, 0, pa); 1260 va = moea64_scratchpage_va[0]; 1261 } else { 1262 va = PHYS_TO_DMAP(pa); 1263 } 1264 1265 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1266 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1267 1268 if (!hw_direct_map) 1269 mtx_unlock(&moea64_scratchpage_mtx); 1270 } 1271 1272 vm_offset_t 1273 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1274 { 1275 struct pvo_entry *pvo; 1276 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1277 1278 if (hw_direct_map) 1279 return (PHYS_TO_DMAP(pa)); 1280 1281 /* 1282 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1283 * a critical section and access the PCPU data like on i386. 1284 * Instead, pin the thread and grab the PCPU lock to prevent 1285 * a preempting thread from using the same PCPU data. 1286 */ 1287 sched_pin(); 1288 1289 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1290 pvo = PCPU_GET(aim.qmap_pvo); 1291 1292 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1293 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1294 (uint64_t)pa; 1295 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1296 isync(); 1297 1298 return (PCPU_GET(qmap_addr)); 1299 } 1300 1301 void 1302 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1303 { 1304 if (hw_direct_map) 1305 return; 1306 1307 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1308 KASSERT(PCPU_GET(qmap_addr) == addr, 1309 ("moea64_quick_remove_page: invalid address")); 1310 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1311 sched_unpin(); 1312 } 1313 1314 /* 1315 * Map the given physical page at the specified virtual address in the 1316 * target pmap with the protection requested. If specified the page 1317 * will be wired down. 1318 */ 1319 1320 int 1321 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1322 vm_prot_t prot, u_int flags, int8_t psind) 1323 { 1324 struct pvo_entry *pvo, *oldpvo; 1325 struct pvo_head *pvo_head; 1326 uint64_t pte_lo; 1327 int error; 1328 1329 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1330 VM_OBJECT_ASSERT_LOCKED(m->object); 1331 1332 pvo = alloc_pvo_entry(0); 1333 pvo->pvo_pmap = NULL; /* to be filled in later */ 1334 pvo->pvo_pte.prot = prot; 1335 1336 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1337 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1338 1339 if ((flags & PMAP_ENTER_WIRED) != 0) 1340 pvo->pvo_vaddr |= PVO_WIRED; 1341 1342 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1343 pvo_head = NULL; 1344 } else { 1345 pvo_head = &m->md.mdpg_pvoh; 1346 pvo->pvo_vaddr |= PVO_MANAGED; 1347 } 1348 1349 for (;;) { 1350 PV_PAGE_LOCK(m); 1351 PMAP_LOCK(pmap); 1352 if (pvo->pvo_pmap == NULL) 1353 init_pvo_entry(pvo, pmap, va); 1354 if (prot & VM_PROT_WRITE) 1355 if (pmap_bootstrapped && 1356 (m->oflags & VPO_UNMANAGED) == 0) 1357 vm_page_aflag_set(m, PGA_WRITEABLE); 1358 1359 oldpvo = moea64_pvo_find_va(pmap, va); 1360 if (oldpvo != NULL) { 1361 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1362 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1363 oldpvo->pvo_pte.prot == prot) { 1364 /* Identical mapping already exists */ 1365 error = 0; 1366 1367 /* If not in page table, reinsert it */ 1368 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1369 moea64_pte_overflow--; 1370 MOEA64_PTE_INSERT(mmu, oldpvo); 1371 } 1372 1373 /* Then just clean up and go home */ 1374 PV_PAGE_UNLOCK(m); 1375 PMAP_UNLOCK(pmap); 1376 free_pvo_entry(pvo); 1377 break; 1378 } 1379 1380 /* Otherwise, need to kill it first */ 1381 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1382 "mapping does not match new mapping")); 1383 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1384 } 1385 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1386 PV_PAGE_UNLOCK(m); 1387 PMAP_UNLOCK(pmap); 1388 1389 /* Free any dead pages */ 1390 if (oldpvo != NULL) { 1391 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1392 moea64_pvo_remove_from_page(mmu, oldpvo); 1393 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1394 free_pvo_entry(oldpvo); 1395 } 1396 1397 if (error != ENOMEM) 1398 break; 1399 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1400 return (KERN_RESOURCE_SHORTAGE); 1401 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1402 vm_wait(NULL); 1403 } 1404 1405 /* 1406 * Flush the page from the instruction cache if this page is 1407 * mapped executable and cacheable. 1408 */ 1409 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1410 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1411 vm_page_aflag_set(m, PGA_EXECUTABLE); 1412 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1413 } 1414 return (KERN_SUCCESS); 1415 } 1416 1417 static void 1418 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1419 vm_size_t sz) 1420 { 1421 1422 /* 1423 * This is much trickier than on older systems because 1424 * we can't sync the icache on physical addresses directly 1425 * without a direct map. Instead we check a couple of cases 1426 * where the memory is already mapped in and, failing that, 1427 * use the same trick we use for page zeroing to create 1428 * a temporary mapping for this physical address. 1429 */ 1430 1431 if (!pmap_bootstrapped) { 1432 /* 1433 * If PMAP is not bootstrapped, we are likely to be 1434 * in real mode. 1435 */ 1436 __syncicache((void *)(uintptr_t)pa, sz); 1437 } else if (pmap == kernel_pmap) { 1438 __syncicache((void *)va, sz); 1439 } else if (hw_direct_map) { 1440 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1441 } else { 1442 /* Use the scratch page to set up a temp mapping */ 1443 1444 mtx_lock(&moea64_scratchpage_mtx); 1445 1446 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1447 __syncicache((void *)(moea64_scratchpage_va[1] + 1448 (va & ADDR_POFF)), sz); 1449 1450 mtx_unlock(&moea64_scratchpage_mtx); 1451 } 1452 } 1453 1454 /* 1455 * Maps a sequence of resident pages belonging to the same object. 1456 * The sequence begins with the given page m_start. This page is 1457 * mapped at the given virtual address start. Each subsequent page is 1458 * mapped at a virtual address that is offset from start by the same 1459 * amount as the page is offset from m_start within the object. The 1460 * last page in the sequence is the page with the largest offset from 1461 * m_start that can be mapped at a virtual address less than the given 1462 * virtual address end. Not every virtual page between start and end 1463 * is mapped; only those for which a resident page exists with the 1464 * corresponding offset from m_start are mapped. 1465 */ 1466 void 1467 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1468 vm_page_t m_start, vm_prot_t prot) 1469 { 1470 vm_page_t m; 1471 vm_pindex_t diff, psize; 1472 1473 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1474 1475 psize = atop(end - start); 1476 m = m_start; 1477 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1478 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1479 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1480 m = TAILQ_NEXT(m, listq); 1481 } 1482 } 1483 1484 void 1485 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1486 vm_prot_t prot) 1487 { 1488 1489 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1490 PMAP_ENTER_NOSLEEP, 0); 1491 } 1492 1493 vm_paddr_t 1494 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1495 { 1496 struct pvo_entry *pvo; 1497 vm_paddr_t pa; 1498 1499 PMAP_LOCK(pm); 1500 pvo = moea64_pvo_find_va(pm, va); 1501 if (pvo == NULL) 1502 pa = 0; 1503 else 1504 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1505 PMAP_UNLOCK(pm); 1506 1507 return (pa); 1508 } 1509 1510 /* 1511 * Atomically extract and hold the physical page with the given 1512 * pmap and virtual address pair if that mapping permits the given 1513 * protection. 1514 */ 1515 vm_page_t 1516 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1517 { 1518 struct pvo_entry *pvo; 1519 vm_page_t m; 1520 vm_paddr_t pa; 1521 1522 m = NULL; 1523 pa = 0; 1524 PMAP_LOCK(pmap); 1525 retry: 1526 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1527 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1528 if (vm_page_pa_tryrelock(pmap, 1529 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1530 goto retry; 1531 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1532 vm_page_hold(m); 1533 } 1534 PA_UNLOCK_COND(pa); 1535 PMAP_UNLOCK(pmap); 1536 return (m); 1537 } 1538 1539 static mmu_t installed_mmu; 1540 1541 static void * 1542 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1543 uint8_t *flags, int wait) 1544 { 1545 struct pvo_entry *pvo; 1546 vm_offset_t va; 1547 vm_page_t m; 1548 int needed_lock; 1549 1550 /* 1551 * This entire routine is a horrible hack to avoid bothering kmem 1552 * for new KVA addresses. Because this can get called from inside 1553 * kmem allocation routines, calling kmem for a new address here 1554 * can lead to multiply locking non-recursive mutexes. 1555 */ 1556 1557 *flags = UMA_SLAB_PRIV; 1558 needed_lock = !PMAP_LOCKED(kernel_pmap); 1559 1560 m = vm_page_alloc_domain(NULL, 0, domain, 1561 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1562 if (m == NULL) 1563 return (NULL); 1564 1565 va = VM_PAGE_TO_PHYS(m); 1566 1567 pvo = alloc_pvo_entry(1 /* bootstrap */); 1568 1569 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1570 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1571 1572 if (needed_lock) 1573 PMAP_LOCK(kernel_pmap); 1574 1575 init_pvo_entry(pvo, kernel_pmap, va); 1576 pvo->pvo_vaddr |= PVO_WIRED; 1577 1578 moea64_pvo_enter(installed_mmu, pvo, NULL); 1579 1580 if (needed_lock) 1581 PMAP_UNLOCK(kernel_pmap); 1582 1583 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1584 bzero((void *)va, PAGE_SIZE); 1585 1586 return (void *)va; 1587 } 1588 1589 extern int elf32_nxstack; 1590 1591 void 1592 moea64_init(mmu_t mmu) 1593 { 1594 1595 CTR0(KTR_PMAP, "moea64_init"); 1596 1597 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1598 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1599 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1600 1601 if (!hw_direct_map) { 1602 installed_mmu = mmu; 1603 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1604 } 1605 1606 #ifdef COMPAT_FREEBSD32 1607 elf32_nxstack = 1; 1608 #endif 1609 1610 moea64_initialized = TRUE; 1611 } 1612 1613 boolean_t 1614 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1615 { 1616 1617 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1618 ("moea64_is_referenced: page %p is not managed", m)); 1619 1620 return (moea64_query_bit(mmu, m, LPTE_REF)); 1621 } 1622 1623 boolean_t 1624 moea64_is_modified(mmu_t mmu, vm_page_t m) 1625 { 1626 1627 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1628 ("moea64_is_modified: page %p is not managed", m)); 1629 1630 /* 1631 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1632 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1633 * is clear, no PTEs can have LPTE_CHG set. 1634 */ 1635 VM_OBJECT_ASSERT_LOCKED(m->object); 1636 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1637 return (FALSE); 1638 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1639 } 1640 1641 boolean_t 1642 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1643 { 1644 struct pvo_entry *pvo; 1645 boolean_t rv = TRUE; 1646 1647 PMAP_LOCK(pmap); 1648 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1649 if (pvo != NULL) 1650 rv = FALSE; 1651 PMAP_UNLOCK(pmap); 1652 return (rv); 1653 } 1654 1655 void 1656 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1657 { 1658 1659 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1660 ("moea64_clear_modify: page %p is not managed", m)); 1661 VM_OBJECT_ASSERT_WLOCKED(m->object); 1662 KASSERT(!vm_page_xbusied(m), 1663 ("moea64_clear_modify: page %p is exclusive busied", m)); 1664 1665 /* 1666 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1667 * set. If the object containing the page is locked and the page is 1668 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1669 */ 1670 if ((m->aflags & PGA_WRITEABLE) == 0) 1671 return; 1672 moea64_clear_bit(mmu, m, LPTE_CHG); 1673 } 1674 1675 /* 1676 * Clear the write and modified bits in each of the given page's mappings. 1677 */ 1678 void 1679 moea64_remove_write(mmu_t mmu, vm_page_t m) 1680 { 1681 struct pvo_entry *pvo; 1682 int64_t refchg, ret; 1683 pmap_t pmap; 1684 1685 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1686 ("moea64_remove_write: page %p is not managed", m)); 1687 1688 /* 1689 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1690 * set by another thread while the object is locked. Thus, 1691 * if PGA_WRITEABLE is clear, no page table entries need updating. 1692 */ 1693 VM_OBJECT_ASSERT_WLOCKED(m->object); 1694 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1695 return; 1696 powerpc_sync(); 1697 PV_PAGE_LOCK(m); 1698 refchg = 0; 1699 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1700 pmap = pvo->pvo_pmap; 1701 PMAP_LOCK(pmap); 1702 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1703 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1704 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1705 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1706 MOEA64_PTE_PROT_UPDATE); 1707 if (ret < 0) 1708 ret = LPTE_CHG; 1709 refchg |= ret; 1710 if (pvo->pvo_pmap == kernel_pmap) 1711 isync(); 1712 } 1713 PMAP_UNLOCK(pmap); 1714 } 1715 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1716 vm_page_dirty(m); 1717 vm_page_aflag_clear(m, PGA_WRITEABLE); 1718 PV_PAGE_UNLOCK(m); 1719 } 1720 1721 /* 1722 * moea64_ts_referenced: 1723 * 1724 * Return a count of reference bits for a page, clearing those bits. 1725 * It is not necessary for every reference bit to be cleared, but it 1726 * is necessary that 0 only be returned when there are truly no 1727 * reference bits set. 1728 * 1729 * XXX: The exact number of bits to check and clear is a matter that 1730 * should be tested and standardized at some point in the future for 1731 * optimal aging of shared pages. 1732 */ 1733 int 1734 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1735 { 1736 1737 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1738 ("moea64_ts_referenced: page %p is not managed", m)); 1739 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1740 } 1741 1742 /* 1743 * Modify the WIMG settings of all mappings for a page. 1744 */ 1745 void 1746 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1747 { 1748 struct pvo_entry *pvo; 1749 int64_t refchg; 1750 pmap_t pmap; 1751 uint64_t lo; 1752 1753 if ((m->oflags & VPO_UNMANAGED) != 0) { 1754 m->md.mdpg_cache_attrs = ma; 1755 return; 1756 } 1757 1758 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1759 1760 PV_PAGE_LOCK(m); 1761 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1762 pmap = pvo->pvo_pmap; 1763 PMAP_LOCK(pmap); 1764 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1765 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1766 pvo->pvo_pte.pa |= lo; 1767 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1768 MOEA64_PTE_INVALIDATE); 1769 if (refchg < 0) 1770 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1771 LPTE_CHG : 0; 1772 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1773 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1774 refchg |= 1775 atomic_readandclear_32(&m->md.mdpg_attrs); 1776 if (refchg & LPTE_CHG) 1777 vm_page_dirty(m); 1778 if (refchg & LPTE_REF) 1779 vm_page_aflag_set(m, PGA_REFERENCED); 1780 } 1781 if (pvo->pvo_pmap == kernel_pmap) 1782 isync(); 1783 } 1784 PMAP_UNLOCK(pmap); 1785 } 1786 m->md.mdpg_cache_attrs = ma; 1787 PV_PAGE_UNLOCK(m); 1788 } 1789 1790 /* 1791 * Map a wired page into kernel virtual address space. 1792 */ 1793 void 1794 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1795 { 1796 int error; 1797 struct pvo_entry *pvo, *oldpvo; 1798 1799 pvo = alloc_pvo_entry(0); 1800 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1801 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1802 pvo->pvo_vaddr |= PVO_WIRED; 1803 1804 PMAP_LOCK(kernel_pmap); 1805 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1806 if (oldpvo != NULL) 1807 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1808 init_pvo_entry(pvo, kernel_pmap, va); 1809 error = moea64_pvo_enter(mmu, pvo, NULL); 1810 PMAP_UNLOCK(kernel_pmap); 1811 1812 /* Free any dead pages */ 1813 if (oldpvo != NULL) { 1814 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1815 moea64_pvo_remove_from_page(mmu, oldpvo); 1816 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1817 free_pvo_entry(oldpvo); 1818 } 1819 1820 if (error != 0 && error != ENOENT) 1821 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1822 (uintmax_t)pa, error); 1823 } 1824 1825 void 1826 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1827 { 1828 1829 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1830 } 1831 1832 /* 1833 * Extract the physical page address associated with the given kernel virtual 1834 * address. 1835 */ 1836 vm_paddr_t 1837 moea64_kextract(mmu_t mmu, vm_offset_t va) 1838 { 1839 struct pvo_entry *pvo; 1840 vm_paddr_t pa; 1841 1842 /* 1843 * Shortcut the direct-mapped case when applicable. We never put 1844 * anything but 1:1 (or 62-bit aliased) mappings below 1845 * VM_MIN_KERNEL_ADDRESS. 1846 */ 1847 if (va < VM_MIN_KERNEL_ADDRESS) 1848 return (va & ~DMAP_BASE_ADDRESS); 1849 1850 PMAP_LOCK(kernel_pmap); 1851 pvo = moea64_pvo_find_va(kernel_pmap, va); 1852 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1853 va)); 1854 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1855 PMAP_UNLOCK(kernel_pmap); 1856 return (pa); 1857 } 1858 1859 /* 1860 * Remove a wired page from kernel virtual address space. 1861 */ 1862 void 1863 moea64_kremove(mmu_t mmu, vm_offset_t va) 1864 { 1865 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1866 } 1867 1868 /* 1869 * Provide a kernel pointer corresponding to a given userland pointer. 1870 * The returned pointer is valid until the next time this function is 1871 * called in this thread. This is used internally in copyin/copyout. 1872 */ 1873 static int 1874 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1875 void **kaddr, size_t ulen, size_t *klen) 1876 { 1877 size_t l; 1878 #ifdef __powerpc64__ 1879 struct slb *slb; 1880 #endif 1881 register_t slbv; 1882 1883 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1884 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1885 if (l > ulen) 1886 l = ulen; 1887 if (klen) 1888 *klen = l; 1889 else if (l != ulen) 1890 return (EFAULT); 1891 1892 #ifdef __powerpc64__ 1893 /* Try lockless look-up first */ 1894 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1895 1896 if (slb == NULL) { 1897 /* If it isn't there, we need to pre-fault the VSID */ 1898 PMAP_LOCK(pm); 1899 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1900 PMAP_UNLOCK(pm); 1901 } else { 1902 slbv = slb->slbv; 1903 } 1904 1905 /* Mark segment no-execute */ 1906 slbv |= SLBV_N; 1907 #else 1908 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1909 1910 /* Mark segment no-execute */ 1911 slbv |= SR_N; 1912 #endif 1913 1914 /* If we have already set this VSID, we can just return */ 1915 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1916 return (0); 1917 1918 __asm __volatile("isync"); 1919 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1920 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1921 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1922 #ifdef __powerpc64__ 1923 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1924 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1925 #else 1926 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1927 #endif 1928 1929 return (0); 1930 } 1931 1932 /* 1933 * Figure out where a given kernel pointer (usually in a fault) points 1934 * to from the VM's perspective, potentially remapping into userland's 1935 * address space. 1936 */ 1937 static int 1938 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1939 vm_offset_t *decoded_addr) 1940 { 1941 vm_offset_t user_sr; 1942 1943 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1944 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1945 addr &= ADDR_PIDX | ADDR_POFF; 1946 addr |= user_sr << ADDR_SR_SHFT; 1947 *decoded_addr = addr; 1948 *is_user = 1; 1949 } else { 1950 *decoded_addr = addr; 1951 *is_user = 0; 1952 } 1953 1954 return (0); 1955 } 1956 1957 /* 1958 * Map a range of physical addresses into kernel virtual address space. 1959 * 1960 * The value passed in *virt is a suggested virtual address for the mapping. 1961 * Architectures which can support a direct-mapped physical to virtual region 1962 * can return the appropriate address within that region, leaving '*virt' 1963 * unchanged. Other architectures should map the pages starting at '*virt' and 1964 * update '*virt' with the first usable address after the mapped region. 1965 */ 1966 vm_offset_t 1967 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1968 vm_paddr_t pa_end, int prot) 1969 { 1970 vm_offset_t sva, va; 1971 1972 if (hw_direct_map) { 1973 /* 1974 * Check if every page in the region is covered by the direct 1975 * map. The direct map covers all of physical memory. Use 1976 * moea64_calc_wimg() as a shortcut to see if the page is in 1977 * physical memory as a way to see if the direct map covers it. 1978 */ 1979 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1980 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1981 break; 1982 if (va == pa_end) 1983 return (PHYS_TO_DMAP(pa_start)); 1984 } 1985 sva = *virt; 1986 va = sva; 1987 /* XXX respect prot argument */ 1988 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1989 moea64_kenter(mmu, va, pa_start); 1990 *virt = va; 1991 1992 return (sva); 1993 } 1994 1995 /* 1996 * Returns true if the pmap's pv is one of the first 1997 * 16 pvs linked to from this page. This count may 1998 * be changed upwards or downwards in the future; it 1999 * is only necessary that true be returned for a small 2000 * subset of pmaps for proper page aging. 2001 */ 2002 boolean_t 2003 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2004 { 2005 int loops; 2006 struct pvo_entry *pvo; 2007 boolean_t rv; 2008 2009 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2010 ("moea64_page_exists_quick: page %p is not managed", m)); 2011 loops = 0; 2012 rv = FALSE; 2013 PV_PAGE_LOCK(m); 2014 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2015 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2016 rv = TRUE; 2017 break; 2018 } 2019 if (++loops >= 16) 2020 break; 2021 } 2022 PV_PAGE_UNLOCK(m); 2023 return (rv); 2024 } 2025 2026 void 2027 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2028 { 2029 2030 m->md.mdpg_attrs = 0; 2031 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2032 LIST_INIT(&m->md.mdpg_pvoh); 2033 } 2034 2035 /* 2036 * Return the number of managed mappings to the given physical page 2037 * that are wired. 2038 */ 2039 int 2040 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2041 { 2042 struct pvo_entry *pvo; 2043 int count; 2044 2045 count = 0; 2046 if ((m->oflags & VPO_UNMANAGED) != 0) 2047 return (count); 2048 PV_PAGE_LOCK(m); 2049 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2050 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2051 count++; 2052 PV_PAGE_UNLOCK(m); 2053 return (count); 2054 } 2055 2056 static uintptr_t moea64_vsidcontext; 2057 2058 uintptr_t 2059 moea64_get_unique_vsid(void) { 2060 u_int entropy; 2061 register_t hash; 2062 uint32_t mask; 2063 int i; 2064 2065 entropy = 0; 2066 __asm __volatile("mftb %0" : "=r"(entropy)); 2067 2068 mtx_lock(&moea64_slb_mutex); 2069 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2070 u_int n; 2071 2072 /* 2073 * Create a new value by mutiplying by a prime and adding in 2074 * entropy from the timebase register. This is to make the 2075 * VSID more random so that the PT hash function collides 2076 * less often. (Note that the prime casues gcc to do shifts 2077 * instead of a multiply.) 2078 */ 2079 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2080 hash = moea64_vsidcontext & (NVSIDS - 1); 2081 if (hash == 0) /* 0 is special, avoid it */ 2082 continue; 2083 n = hash >> 5; 2084 mask = 1 << (hash & (VSID_NBPW - 1)); 2085 hash = (moea64_vsidcontext & VSID_HASHMASK); 2086 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2087 /* anything free in this bucket? */ 2088 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2089 entropy = (moea64_vsidcontext >> 20); 2090 continue; 2091 } 2092 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2093 mask = 1 << i; 2094 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2095 hash |= i; 2096 } 2097 if (hash == VSID_VRMA) /* also special, avoid this too */ 2098 continue; 2099 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2100 ("Allocating in-use VSID %#zx\n", hash)); 2101 moea64_vsid_bitmap[n] |= mask; 2102 mtx_unlock(&moea64_slb_mutex); 2103 return (hash); 2104 } 2105 2106 mtx_unlock(&moea64_slb_mutex); 2107 panic("%s: out of segments",__func__); 2108 } 2109 2110 #ifdef __powerpc64__ 2111 void 2112 moea64_pinit(mmu_t mmu, pmap_t pmap) 2113 { 2114 2115 RB_INIT(&pmap->pmap_pvo); 2116 2117 pmap->pm_slb_tree_root = slb_alloc_tree(); 2118 pmap->pm_slb = slb_alloc_user_cache(); 2119 pmap->pm_slb_len = 0; 2120 } 2121 #else 2122 void 2123 moea64_pinit(mmu_t mmu, pmap_t pmap) 2124 { 2125 int i; 2126 uint32_t hash; 2127 2128 RB_INIT(&pmap->pmap_pvo); 2129 2130 if (pmap_bootstrapped) 2131 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2132 (vm_offset_t)pmap); 2133 else 2134 pmap->pmap_phys = pmap; 2135 2136 /* 2137 * Allocate some segment registers for this pmap. 2138 */ 2139 hash = moea64_get_unique_vsid(); 2140 2141 for (i = 0; i < 16; i++) 2142 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2143 2144 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2145 } 2146 #endif 2147 2148 /* 2149 * Initialize the pmap associated with process 0. 2150 */ 2151 void 2152 moea64_pinit0(mmu_t mmu, pmap_t pm) 2153 { 2154 2155 PMAP_LOCK_INIT(pm); 2156 moea64_pinit(mmu, pm); 2157 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2158 } 2159 2160 /* 2161 * Set the physical protection on the specified range of this map as requested. 2162 */ 2163 static void 2164 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2165 { 2166 struct vm_page *pg; 2167 vm_prot_t oldprot; 2168 int32_t refchg; 2169 2170 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2171 2172 /* 2173 * Change the protection of the page. 2174 */ 2175 oldprot = pvo->pvo_pte.prot; 2176 pvo->pvo_pte.prot = prot; 2177 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2178 2179 /* 2180 * If the PVO is in the page table, update mapping 2181 */ 2182 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2183 if (refchg < 0) 2184 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2185 2186 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2187 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2188 if ((pg->oflags & VPO_UNMANAGED) == 0) 2189 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2190 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2191 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2192 } 2193 2194 /* 2195 * Update vm about the REF/CHG bits if the page is managed and we have 2196 * removed write access. 2197 */ 2198 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2199 (oldprot & VM_PROT_WRITE)) { 2200 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2201 if (refchg & LPTE_CHG) 2202 vm_page_dirty(pg); 2203 if (refchg & LPTE_REF) 2204 vm_page_aflag_set(pg, PGA_REFERENCED); 2205 } 2206 } 2207 2208 void 2209 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2210 vm_prot_t prot) 2211 { 2212 struct pvo_entry *pvo, *tpvo, key; 2213 2214 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2215 sva, eva, prot); 2216 2217 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2218 ("moea64_protect: non current pmap")); 2219 2220 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2221 moea64_remove(mmu, pm, sva, eva); 2222 return; 2223 } 2224 2225 PMAP_LOCK(pm); 2226 key.pvo_vaddr = sva; 2227 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2228 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2229 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2230 moea64_pvo_protect(mmu, pm, pvo, prot); 2231 } 2232 PMAP_UNLOCK(pm); 2233 } 2234 2235 /* 2236 * Map a list of wired pages into kernel virtual address space. This is 2237 * intended for temporary mappings which do not need page modification or 2238 * references recorded. Existing mappings in the region are overwritten. 2239 */ 2240 void 2241 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2242 { 2243 while (count-- > 0) { 2244 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2245 va += PAGE_SIZE; 2246 m++; 2247 } 2248 } 2249 2250 /* 2251 * Remove page mappings from kernel virtual address space. Intended for 2252 * temporary mappings entered by moea64_qenter. 2253 */ 2254 void 2255 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2256 { 2257 while (count-- > 0) { 2258 moea64_kremove(mmu, va); 2259 va += PAGE_SIZE; 2260 } 2261 } 2262 2263 void 2264 moea64_release_vsid(uint64_t vsid) 2265 { 2266 int idx, mask; 2267 2268 mtx_lock(&moea64_slb_mutex); 2269 idx = vsid & (NVSIDS-1); 2270 mask = 1 << (idx % VSID_NBPW); 2271 idx /= VSID_NBPW; 2272 KASSERT(moea64_vsid_bitmap[idx] & mask, 2273 ("Freeing unallocated VSID %#jx", vsid)); 2274 moea64_vsid_bitmap[idx] &= ~mask; 2275 mtx_unlock(&moea64_slb_mutex); 2276 } 2277 2278 2279 void 2280 moea64_release(mmu_t mmu, pmap_t pmap) 2281 { 2282 2283 /* 2284 * Free segment registers' VSIDs 2285 */ 2286 #ifdef __powerpc64__ 2287 slb_free_tree(pmap); 2288 slb_free_user_cache(pmap->pm_slb); 2289 #else 2290 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2291 2292 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2293 #endif 2294 } 2295 2296 /* 2297 * Remove all pages mapped by the specified pmap 2298 */ 2299 void 2300 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2301 { 2302 struct pvo_entry *pvo, *tpvo; 2303 struct pvo_tree tofree; 2304 2305 RB_INIT(&tofree); 2306 2307 PMAP_LOCK(pm); 2308 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2309 if (pvo->pvo_vaddr & PVO_WIRED) 2310 continue; 2311 2312 /* 2313 * For locking reasons, remove this from the page table and 2314 * pmap, but save delinking from the vm_page for a second 2315 * pass 2316 */ 2317 moea64_pvo_remove_from_pmap(mmu, pvo); 2318 RB_INSERT(pvo_tree, &tofree, pvo); 2319 } 2320 PMAP_UNLOCK(pm); 2321 2322 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2323 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2324 moea64_pvo_remove_from_page(mmu, pvo); 2325 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2326 RB_REMOVE(pvo_tree, &tofree, pvo); 2327 free_pvo_entry(pvo); 2328 } 2329 } 2330 2331 /* 2332 * Remove the given range of addresses from the specified map. 2333 */ 2334 void 2335 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2336 { 2337 struct pvo_entry *pvo, *tpvo, key; 2338 struct pvo_tree tofree; 2339 2340 /* 2341 * Perform an unsynchronized read. This is, however, safe. 2342 */ 2343 if (pm->pm_stats.resident_count == 0) 2344 return; 2345 2346 key.pvo_vaddr = sva; 2347 2348 RB_INIT(&tofree); 2349 2350 PMAP_LOCK(pm); 2351 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2352 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2353 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2354 2355 /* 2356 * For locking reasons, remove this from the page table and 2357 * pmap, but save delinking from the vm_page for a second 2358 * pass 2359 */ 2360 moea64_pvo_remove_from_pmap(mmu, pvo); 2361 RB_INSERT(pvo_tree, &tofree, pvo); 2362 } 2363 PMAP_UNLOCK(pm); 2364 2365 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2366 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2367 moea64_pvo_remove_from_page(mmu, pvo); 2368 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2369 RB_REMOVE(pvo_tree, &tofree, pvo); 2370 free_pvo_entry(pvo); 2371 } 2372 } 2373 2374 /* 2375 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2376 * will reflect changes in pte's back to the vm_page. 2377 */ 2378 void 2379 moea64_remove_all(mmu_t mmu, vm_page_t m) 2380 { 2381 struct pvo_entry *pvo, *next_pvo; 2382 struct pvo_head freequeue; 2383 int wasdead; 2384 pmap_t pmap; 2385 2386 LIST_INIT(&freequeue); 2387 2388 PV_PAGE_LOCK(m); 2389 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2390 pmap = pvo->pvo_pmap; 2391 PMAP_LOCK(pmap); 2392 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2393 if (!wasdead) 2394 moea64_pvo_remove_from_pmap(mmu, pvo); 2395 moea64_pvo_remove_from_page(mmu, pvo); 2396 if (!wasdead) 2397 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2398 PMAP_UNLOCK(pmap); 2399 2400 } 2401 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2402 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2403 PV_PAGE_UNLOCK(m); 2404 2405 /* Clean up UMA allocations */ 2406 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2407 free_pvo_entry(pvo); 2408 } 2409 2410 /* 2411 * Allocate a physical page of memory directly from the phys_avail map. 2412 * Can only be called from moea64_bootstrap before avail start and end are 2413 * calculated. 2414 */ 2415 vm_offset_t 2416 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2417 { 2418 vm_offset_t s, e; 2419 int i, j; 2420 2421 size = round_page(size); 2422 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2423 if (align != 0) 2424 s = roundup2(phys_avail[i], align); 2425 else 2426 s = phys_avail[i]; 2427 e = s + size; 2428 2429 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2430 continue; 2431 2432 if (s + size > platform_real_maxaddr()) 2433 continue; 2434 2435 if (s == phys_avail[i]) { 2436 phys_avail[i] += size; 2437 } else if (e == phys_avail[i + 1]) { 2438 phys_avail[i + 1] -= size; 2439 } else { 2440 for (j = phys_avail_count * 2; j > i; j -= 2) { 2441 phys_avail[j] = phys_avail[j - 2]; 2442 phys_avail[j + 1] = phys_avail[j - 1]; 2443 } 2444 2445 phys_avail[i + 3] = phys_avail[i + 1]; 2446 phys_avail[i + 1] = s; 2447 phys_avail[i + 2] = e; 2448 phys_avail_count++; 2449 } 2450 2451 return (s); 2452 } 2453 panic("moea64_bootstrap_alloc: could not allocate memory"); 2454 } 2455 2456 static int 2457 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2458 { 2459 int first, err; 2460 2461 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2462 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2463 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2464 2465 moea64_pvo_enter_calls++; 2466 2467 /* 2468 * Add to pmap list 2469 */ 2470 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2471 2472 /* 2473 * Remember if the list was empty and therefore will be the first 2474 * item. 2475 */ 2476 if (pvo_head != NULL) { 2477 if (LIST_FIRST(pvo_head) == NULL) 2478 first = 1; 2479 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2480 } 2481 2482 if (pvo->pvo_vaddr & PVO_WIRED) 2483 pvo->pvo_pmap->pm_stats.wired_count++; 2484 pvo->pvo_pmap->pm_stats.resident_count++; 2485 2486 /* 2487 * Insert it into the hardware page table 2488 */ 2489 err = MOEA64_PTE_INSERT(mmu, pvo); 2490 if (err != 0) { 2491 panic("moea64_pvo_enter: overflow"); 2492 } 2493 2494 moea64_pvo_entries++; 2495 2496 if (pvo->pvo_pmap == kernel_pmap) 2497 isync(); 2498 2499 #ifdef __powerpc64__ 2500 /* 2501 * Make sure all our bootstrap mappings are in the SLB as soon 2502 * as virtual memory is switched on. 2503 */ 2504 if (!pmap_bootstrapped) 2505 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2506 pvo->pvo_vaddr & PVO_LARGE); 2507 #endif 2508 2509 return (first ? ENOENT : 0); 2510 } 2511 2512 static void 2513 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2514 { 2515 struct vm_page *pg; 2516 int32_t refchg; 2517 2518 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2519 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2520 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2521 2522 /* 2523 * If there is an active pte entry, we need to deactivate it 2524 */ 2525 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2526 if (refchg < 0) { 2527 /* 2528 * If it was evicted from the page table, be pessimistic and 2529 * dirty the page. 2530 */ 2531 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2532 refchg = LPTE_CHG; 2533 else 2534 refchg = 0; 2535 } 2536 2537 /* 2538 * Update our statistics. 2539 */ 2540 pvo->pvo_pmap->pm_stats.resident_count--; 2541 if (pvo->pvo_vaddr & PVO_WIRED) 2542 pvo->pvo_pmap->pm_stats.wired_count--; 2543 2544 /* 2545 * Remove this PVO from the pmap list. 2546 */ 2547 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2548 2549 /* 2550 * Mark this for the next sweep 2551 */ 2552 pvo->pvo_vaddr |= PVO_DEAD; 2553 2554 /* Send RC bits to VM */ 2555 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2556 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2557 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2558 if (pg != NULL) { 2559 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2560 if (refchg & LPTE_CHG) 2561 vm_page_dirty(pg); 2562 if (refchg & LPTE_REF) 2563 vm_page_aflag_set(pg, PGA_REFERENCED); 2564 } 2565 } 2566 } 2567 2568 static void 2569 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2570 { 2571 struct vm_page *pg; 2572 2573 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2574 2575 /* Use NULL pmaps as a sentinel for races in page deletion */ 2576 if (pvo->pvo_pmap == NULL) 2577 return; 2578 pvo->pvo_pmap = NULL; 2579 2580 /* 2581 * Update vm about page writeability/executability if managed 2582 */ 2583 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2584 if (pvo->pvo_vaddr & PVO_MANAGED) { 2585 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2586 2587 if (pg != NULL) { 2588 LIST_REMOVE(pvo, pvo_vlink); 2589 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2590 vm_page_aflag_clear(pg, 2591 PGA_WRITEABLE | PGA_EXECUTABLE); 2592 } 2593 } 2594 2595 moea64_pvo_entries--; 2596 moea64_pvo_remove_calls++; 2597 } 2598 2599 static struct pvo_entry * 2600 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2601 { 2602 struct pvo_entry key; 2603 2604 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2605 2606 key.pvo_vaddr = va & ~ADDR_POFF; 2607 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2608 } 2609 2610 static boolean_t 2611 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2612 { 2613 struct pvo_entry *pvo; 2614 int64_t ret; 2615 boolean_t rv; 2616 2617 /* 2618 * See if this bit is stored in the page already. 2619 */ 2620 if (m->md.mdpg_attrs & ptebit) 2621 return (TRUE); 2622 2623 /* 2624 * Examine each PTE. Sync so that any pending REF/CHG bits are 2625 * flushed to the PTEs. 2626 */ 2627 rv = FALSE; 2628 powerpc_sync(); 2629 PV_PAGE_LOCK(m); 2630 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2631 ret = 0; 2632 2633 /* 2634 * See if this pvo has a valid PTE. if so, fetch the 2635 * REF/CHG bits from the valid PTE. If the appropriate 2636 * ptebit is set, return success. 2637 */ 2638 PMAP_LOCK(pvo->pvo_pmap); 2639 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2640 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2641 PMAP_UNLOCK(pvo->pvo_pmap); 2642 2643 if (ret > 0) { 2644 atomic_set_32(&m->md.mdpg_attrs, 2645 ret & (LPTE_CHG | LPTE_REF)); 2646 if (ret & ptebit) { 2647 rv = TRUE; 2648 break; 2649 } 2650 } 2651 } 2652 PV_PAGE_UNLOCK(m); 2653 2654 return (rv); 2655 } 2656 2657 static u_int 2658 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2659 { 2660 u_int count; 2661 struct pvo_entry *pvo; 2662 int64_t ret; 2663 2664 /* 2665 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2666 * we can reset the right ones). 2667 */ 2668 powerpc_sync(); 2669 2670 /* 2671 * For each pvo entry, clear the pte's ptebit. 2672 */ 2673 count = 0; 2674 PV_PAGE_LOCK(m); 2675 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2676 ret = 0; 2677 2678 PMAP_LOCK(pvo->pvo_pmap); 2679 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2680 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2681 PMAP_UNLOCK(pvo->pvo_pmap); 2682 2683 if (ret > 0 && (ret & ptebit)) 2684 count++; 2685 } 2686 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2687 PV_PAGE_UNLOCK(m); 2688 2689 return (count); 2690 } 2691 2692 boolean_t 2693 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2694 { 2695 struct pvo_entry *pvo, key; 2696 vm_offset_t ppa; 2697 int error = 0; 2698 2699 if (hw_direct_map && mem_valid(pa, size) == 0) 2700 return (0); 2701 2702 PMAP_LOCK(kernel_pmap); 2703 ppa = pa & ~ADDR_POFF; 2704 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2705 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2706 ppa < pa + size; ppa += PAGE_SIZE, 2707 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2708 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2709 error = EFAULT; 2710 break; 2711 } 2712 } 2713 PMAP_UNLOCK(kernel_pmap); 2714 2715 return (error); 2716 } 2717 2718 /* 2719 * Map a set of physical memory pages into the kernel virtual 2720 * address space. Return a pointer to where it is mapped. This 2721 * routine is intended to be used for mapping device memory, 2722 * NOT real memory. 2723 */ 2724 void * 2725 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2726 { 2727 vm_offset_t va, tmpva, ppa, offset; 2728 2729 ppa = trunc_page(pa); 2730 offset = pa & PAGE_MASK; 2731 size = roundup2(offset + size, PAGE_SIZE); 2732 2733 va = kva_alloc(size); 2734 2735 if (!va) 2736 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2737 2738 for (tmpva = va; size > 0;) { 2739 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2740 size -= PAGE_SIZE; 2741 tmpva += PAGE_SIZE; 2742 ppa += PAGE_SIZE; 2743 } 2744 2745 return ((void *)(va + offset)); 2746 } 2747 2748 void * 2749 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2750 { 2751 2752 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2753 } 2754 2755 void 2756 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2757 { 2758 vm_offset_t base, offset; 2759 2760 base = trunc_page(va); 2761 offset = va & PAGE_MASK; 2762 size = roundup2(offset + size, PAGE_SIZE); 2763 2764 kva_free(base, size); 2765 } 2766 2767 void 2768 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2769 { 2770 struct pvo_entry *pvo; 2771 vm_offset_t lim; 2772 vm_paddr_t pa; 2773 vm_size_t len; 2774 2775 PMAP_LOCK(pm); 2776 while (sz > 0) { 2777 lim = round_page(va); 2778 len = MIN(lim - va, sz); 2779 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2780 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2781 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2782 moea64_syncicache(mmu, pm, va, pa, len); 2783 } 2784 va += len; 2785 sz -= len; 2786 } 2787 PMAP_UNLOCK(pm); 2788 } 2789 2790 void 2791 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2792 { 2793 2794 *va = (void *)(uintptr_t)pa; 2795 } 2796 2797 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2798 2799 void 2800 moea64_scan_init(mmu_t mmu) 2801 { 2802 struct pvo_entry *pvo; 2803 vm_offset_t va; 2804 int i; 2805 2806 if (!do_minidump) { 2807 /* Initialize phys. segments for dumpsys(). */ 2808 memset(&dump_map, 0, sizeof(dump_map)); 2809 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2810 for (i = 0; i < pregions_sz; i++) { 2811 dump_map[i].pa_start = pregions[i].mr_start; 2812 dump_map[i].pa_size = pregions[i].mr_size; 2813 } 2814 return; 2815 } 2816 2817 /* Virtual segments for minidumps: */ 2818 memset(&dump_map, 0, sizeof(dump_map)); 2819 2820 /* 1st: kernel .data and .bss. */ 2821 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2822 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2823 dump_map[0].pa_start; 2824 2825 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2826 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2827 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2828 2829 /* 3rd: kernel VM. */ 2830 va = dump_map[1].pa_start + dump_map[1].pa_size; 2831 /* Find start of next chunk (from va). */ 2832 while (va < virtual_end) { 2833 /* Don't dump the buffer cache. */ 2834 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2835 va = kmi.buffer_eva; 2836 continue; 2837 } 2838 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2839 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2840 break; 2841 va += PAGE_SIZE; 2842 } 2843 if (va < virtual_end) { 2844 dump_map[2].pa_start = va; 2845 va += PAGE_SIZE; 2846 /* Find last page in chunk. */ 2847 while (va < virtual_end) { 2848 /* Don't run into the buffer cache. */ 2849 if (va == kmi.buffer_sva) 2850 break; 2851 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2852 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2853 break; 2854 va += PAGE_SIZE; 2855 } 2856 dump_map[2].pa_size = va - dump_map[2].pa_start; 2857 } 2858 } 2859 2860