1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_phys.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_PER_DOM PA_LOCK_COUNT*3 123 #define PV_LOCK_COUNT PV_LOCK_PER_DOM*MAXMEMDOM 124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 125 126 /* 127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 129 * index at (N << 45). 130 */ 131 #ifdef __powerpc64__ 132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 134 #else 135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 136 #endif 137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 144 145 struct ofw_map { 146 cell_t om_va; 147 cell_t om_len; 148 uint64_t om_pa; 149 cell_t om_mode; 150 }; 151 152 extern unsigned char _etext[]; 153 extern unsigned char _end[]; 154 155 extern void *slbtrap, *slbtrapend; 156 157 /* 158 * Map of physical memory regions. 159 */ 160 static struct mem_region *regions; 161 static struct mem_region *pregions; 162 static struct numa_mem_region *numa_pregions; 163 static u_int phys_avail_count; 164 static int regions_sz, pregions_sz, numapregions_sz; 165 166 extern void bs_remap_earlyboot(void); 167 168 /* 169 * Lock for the SLB tables. 170 */ 171 struct mtx moea64_slb_mutex; 172 173 /* 174 * PTEG data. 175 */ 176 u_long moea64_pteg_count; 177 u_long moea64_pteg_mask; 178 179 /* 180 * PVO data. 181 */ 182 183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 184 185 static struct pvo_entry *moea64_bpvo_pool; 186 static int moea64_bpvo_pool_index = 0; 187 static int moea64_bpvo_pool_size = 327680; 188 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 190 &moea64_bpvo_pool_index, 0, ""); 191 192 #define VSID_NBPW (sizeof(u_int32_t) * 8) 193 #ifdef __powerpc64__ 194 #define NVSIDS (NPMAPS * 16) 195 #define VSID_HASHMASK 0xffffffffUL 196 #else 197 #define NVSIDS NPMAPS 198 #define VSID_HASHMASK 0xfffffUL 199 #endif 200 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 201 202 static boolean_t moea64_initialized = FALSE; 203 204 #ifdef MOEA64_STATS 205 /* 206 * Statistics. 207 */ 208 u_int moea64_pte_valid = 0; 209 u_int moea64_pte_overflow = 0; 210 u_int moea64_pvo_entries = 0; 211 u_int moea64_pvo_enter_calls = 0; 212 u_int moea64_pvo_remove_calls = 0; 213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 214 &moea64_pte_valid, 0, ""); 215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 216 &moea64_pte_overflow, 0, ""); 217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 218 &moea64_pvo_entries, 0, ""); 219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 220 &moea64_pvo_enter_calls, 0, ""); 221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 222 &moea64_pvo_remove_calls, 0, ""); 223 #endif 224 225 vm_offset_t moea64_scratchpage_va[2]; 226 struct pvo_entry *moea64_scratchpage_pvo[2]; 227 struct mtx moea64_scratchpage_mtx; 228 229 uint64_t moea64_large_page_mask = 0; 230 uint64_t moea64_large_page_size = 0; 231 int moea64_large_page_shift = 0; 232 233 /* 234 * PVO calls. 235 */ 236 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 237 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 238 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 240 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 241 struct pvo_entry *pvo, vm_page_t m); 242 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 243 244 /* 245 * Utility routines. 246 */ 247 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 248 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 249 static void moea64_kremove(mmu_t, vm_offset_t); 250 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 251 vm_paddr_t pa, vm_size_t sz); 252 static void moea64_pmap_init_qpages(void); 253 254 /* 255 * Kernel MMU interface 256 */ 257 void moea64_clear_modify(mmu_t, vm_page_t); 258 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 259 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 260 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 261 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 262 u_int flags, int8_t psind); 263 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 264 vm_prot_t); 265 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 266 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 267 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 268 void moea64_init(mmu_t); 269 boolean_t moea64_is_modified(mmu_t, vm_page_t); 270 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 271 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 272 int moea64_ts_referenced(mmu_t, vm_page_t); 273 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 274 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 275 void moea64_page_init(mmu_t, vm_page_t); 276 int moea64_page_wired_mappings(mmu_t, vm_page_t); 277 void moea64_pinit(mmu_t, pmap_t); 278 void moea64_pinit0(mmu_t, pmap_t); 279 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 280 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 281 void moea64_qremove(mmu_t, vm_offset_t, int); 282 void moea64_release(mmu_t, pmap_t); 283 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 284 void moea64_remove_pages(mmu_t, pmap_t); 285 void moea64_remove_all(mmu_t, vm_page_t); 286 void moea64_remove_write(mmu_t, vm_page_t); 287 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 288 void moea64_zero_page(mmu_t, vm_page_t); 289 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 290 void moea64_activate(mmu_t, struct thread *); 291 void moea64_deactivate(mmu_t, struct thread *); 292 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 293 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 294 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 295 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 296 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 297 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 298 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 299 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 300 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 301 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 302 void **va); 303 void moea64_scan_init(mmu_t mmu); 304 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 305 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 306 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 308 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 309 int *is_user, vm_offset_t *decoded_addr); 310 311 312 static mmu_method_t moea64_methods[] = { 313 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 314 MMUMETHOD(mmu_copy_page, moea64_copy_page), 315 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 316 MMUMETHOD(mmu_enter, moea64_enter), 317 MMUMETHOD(mmu_enter_object, moea64_enter_object), 318 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 319 MMUMETHOD(mmu_extract, moea64_extract), 320 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 321 MMUMETHOD(mmu_init, moea64_init), 322 MMUMETHOD(mmu_is_modified, moea64_is_modified), 323 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 324 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 325 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 326 MMUMETHOD(mmu_map, moea64_map), 327 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 328 MMUMETHOD(mmu_page_init, moea64_page_init), 329 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 330 MMUMETHOD(mmu_pinit, moea64_pinit), 331 MMUMETHOD(mmu_pinit0, moea64_pinit0), 332 MMUMETHOD(mmu_protect, moea64_protect), 333 MMUMETHOD(mmu_qenter, moea64_qenter), 334 MMUMETHOD(mmu_qremove, moea64_qremove), 335 MMUMETHOD(mmu_release, moea64_release), 336 MMUMETHOD(mmu_remove, moea64_remove), 337 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 338 MMUMETHOD(mmu_remove_all, moea64_remove_all), 339 MMUMETHOD(mmu_remove_write, moea64_remove_write), 340 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 341 MMUMETHOD(mmu_unwire, moea64_unwire), 342 MMUMETHOD(mmu_zero_page, moea64_zero_page), 343 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 344 MMUMETHOD(mmu_activate, moea64_activate), 345 MMUMETHOD(mmu_deactivate, moea64_deactivate), 346 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 347 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 348 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 349 350 /* Internal interfaces */ 351 MMUMETHOD(mmu_mapdev, moea64_mapdev), 352 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 353 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 354 MMUMETHOD(mmu_kextract, moea64_kextract), 355 MMUMETHOD(mmu_kenter, moea64_kenter), 356 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 357 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 358 MMUMETHOD(mmu_scan_init, moea64_scan_init), 359 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 360 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 361 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 362 363 { 0, 0 } 364 }; 365 366 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 367 368 static struct pvo_head * 369 vm_page_to_pvoh(vm_page_t m) 370 { 371 372 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 373 return (&m->md.mdpg_pvoh); 374 } 375 376 static struct pvo_entry * 377 alloc_pvo_entry(int bootstrap, int flags) 378 { 379 struct pvo_entry *pvo; 380 381 KASSERT(bootstrap || (flags & M_WAITOK) || (flags & M_NOWAIT), 382 ("Either M_WAITOK or M_NOWAIT flag must be specified " 383 "when bootstrap is 0")); 384 KASSERT(!bootstrap || !(flags & M_WAITOK), 385 ("M_WAITOK can't be used with bootstrap")); 386 387 if (!moea64_initialized || bootstrap) { 388 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 389 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 390 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 391 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 392 } 393 pvo = &moea64_bpvo_pool[ 394 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 395 bzero(pvo, sizeof(*pvo)); 396 pvo->pvo_vaddr = PVO_BOOTSTRAP; 397 } else 398 pvo = uma_zalloc(moea64_pvo_zone, flags | M_ZERO); 399 400 return (pvo); 401 } 402 403 404 static void 405 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 406 { 407 uint64_t vsid; 408 uint64_t hash; 409 int shift; 410 411 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 412 413 pvo->pvo_pmap = pmap; 414 va &= ~ADDR_POFF; 415 pvo->pvo_vaddr |= va; 416 vsid = va_to_vsid(pmap, va); 417 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 418 | (vsid << 16); 419 420 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 421 ADDR_PIDX_SHFT; 422 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 423 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 424 } 425 426 static void 427 free_pvo_entry(struct pvo_entry *pvo) 428 { 429 430 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 431 uma_zfree(moea64_pvo_zone, pvo); 432 } 433 434 void 435 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 436 { 437 438 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 439 LPTE_AVPN_MASK; 440 lpte->pte_hi |= LPTE_VALID; 441 442 if (pvo->pvo_vaddr & PVO_LARGE) 443 lpte->pte_hi |= LPTE_BIG; 444 if (pvo->pvo_vaddr & PVO_WIRED) 445 lpte->pte_hi |= LPTE_WIRED; 446 if (pvo->pvo_vaddr & PVO_HID) 447 lpte->pte_hi |= LPTE_HID; 448 449 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 450 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 451 lpte->pte_lo |= LPTE_BW; 452 else 453 lpte->pte_lo |= LPTE_BR; 454 455 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 456 lpte->pte_lo |= LPTE_NOEXEC; 457 } 458 459 static __inline uint64_t 460 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 461 { 462 uint64_t pte_lo; 463 int i; 464 465 if (ma != VM_MEMATTR_DEFAULT) { 466 switch (ma) { 467 case VM_MEMATTR_UNCACHEABLE: 468 return (LPTE_I | LPTE_G); 469 case VM_MEMATTR_CACHEABLE: 470 return (LPTE_M); 471 case VM_MEMATTR_WRITE_COMBINING: 472 case VM_MEMATTR_WRITE_BACK: 473 case VM_MEMATTR_PREFETCHABLE: 474 return (LPTE_I); 475 case VM_MEMATTR_WRITE_THROUGH: 476 return (LPTE_W | LPTE_M); 477 } 478 } 479 480 /* 481 * Assume the page is cache inhibited and access is guarded unless 482 * it's in our available memory array. 483 */ 484 pte_lo = LPTE_I | LPTE_G; 485 for (i = 0; i < pregions_sz; i++) { 486 if ((pa >= pregions[i].mr_start) && 487 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 488 pte_lo &= ~(LPTE_I | LPTE_G); 489 pte_lo |= LPTE_M; 490 break; 491 } 492 } 493 494 return pte_lo; 495 } 496 497 /* 498 * Quick sort callout for comparing memory regions. 499 */ 500 static int om_cmp(const void *a, const void *b); 501 502 static int 503 om_cmp(const void *a, const void *b) 504 { 505 const struct ofw_map *mapa; 506 const struct ofw_map *mapb; 507 508 mapa = a; 509 mapb = b; 510 if (mapa->om_pa < mapb->om_pa) 511 return (-1); 512 else if (mapa->om_pa > mapb->om_pa) 513 return (1); 514 else 515 return (0); 516 } 517 518 static void 519 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 520 { 521 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 522 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 523 struct pvo_entry *pvo; 524 register_t msr; 525 vm_offset_t off; 526 vm_paddr_t pa_base; 527 int i, j; 528 529 bzero(translations, sz); 530 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 531 sizeof(acells)); 532 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 533 panic("moea64_bootstrap: can't get ofw translations"); 534 535 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 536 sz /= sizeof(cell_t); 537 for (i = 0, j = 0; i < sz; j++) { 538 translations[j].om_va = trans_cells[i++]; 539 translations[j].om_len = trans_cells[i++]; 540 translations[j].om_pa = trans_cells[i++]; 541 if (acells == 2) { 542 translations[j].om_pa <<= 32; 543 translations[j].om_pa |= trans_cells[i++]; 544 } 545 translations[j].om_mode = trans_cells[i++]; 546 } 547 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 548 i, sz)); 549 550 sz = j; 551 qsort(translations, sz, sizeof (*translations), om_cmp); 552 553 for (i = 0; i < sz; i++) { 554 pa_base = translations[i].om_pa; 555 #ifndef __powerpc64__ 556 if ((translations[i].om_pa >> 32) != 0) 557 panic("OFW translations above 32-bit boundary!"); 558 #endif 559 560 if (pa_base % PAGE_SIZE) 561 panic("OFW translation not page-aligned (phys)!"); 562 if (translations[i].om_va % PAGE_SIZE) 563 panic("OFW translation not page-aligned (virt)!"); 564 565 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 566 pa_base, translations[i].om_va, translations[i].om_len); 567 568 /* Now enter the pages for this mapping */ 569 570 DISABLE_TRANS(msr); 571 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 572 /* If this address is direct-mapped, skip remapping */ 573 if (hw_direct_map && 574 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 575 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 576 == LPTE_M) 577 continue; 578 579 PMAP_LOCK(kernel_pmap); 580 pvo = moea64_pvo_find_va(kernel_pmap, 581 translations[i].om_va + off); 582 PMAP_UNLOCK(kernel_pmap); 583 if (pvo != NULL) 584 continue; 585 586 moea64_kenter(mmup, translations[i].om_va + off, 587 pa_base + off); 588 } 589 ENABLE_TRANS(msr); 590 } 591 } 592 593 #ifdef __powerpc64__ 594 static void 595 moea64_probe_large_page(void) 596 { 597 uint16_t pvr = mfpvr() >> 16; 598 599 switch (pvr) { 600 case IBM970: 601 case IBM970FX: 602 case IBM970MP: 603 powerpc_sync(); isync(); 604 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 605 powerpc_sync(); isync(); 606 607 /* FALLTHROUGH */ 608 default: 609 if (moea64_large_page_size == 0) { 610 moea64_large_page_size = 0x1000000; /* 16 MB */ 611 moea64_large_page_shift = 24; 612 } 613 } 614 615 moea64_large_page_mask = moea64_large_page_size - 1; 616 } 617 618 static void 619 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 620 { 621 struct slb *cache; 622 struct slb entry; 623 uint64_t esid, slbe; 624 uint64_t i; 625 626 cache = PCPU_GET(aim.slb); 627 esid = va >> ADDR_SR_SHFT; 628 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 629 630 for (i = 0; i < 64; i++) { 631 if (cache[i].slbe == (slbe | i)) 632 return; 633 } 634 635 entry.slbe = slbe; 636 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 637 if (large) 638 entry.slbv |= SLBV_L; 639 640 slb_insert_kernel(entry.slbe, entry.slbv); 641 } 642 #endif 643 644 static void 645 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 646 vm_offset_t kernelend) 647 { 648 struct pvo_entry *pvo; 649 register_t msr; 650 vm_paddr_t pa, pkernelstart, pkernelend; 651 vm_offset_t size, off; 652 uint64_t pte_lo; 653 int i; 654 655 if (moea64_large_page_size == 0) 656 hw_direct_map = 0; 657 658 DISABLE_TRANS(msr); 659 if (hw_direct_map) { 660 PMAP_LOCK(kernel_pmap); 661 for (i = 0; i < pregions_sz; i++) { 662 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 663 pregions[i].mr_size; pa += moea64_large_page_size) { 664 pte_lo = LPTE_M; 665 666 pvo = alloc_pvo_entry(1 /* bootstrap */, 0); 667 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 668 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 669 670 /* 671 * Set memory access as guarded if prefetch within 672 * the page could exit the available physmem area. 673 */ 674 if (pa & moea64_large_page_mask) { 675 pa &= moea64_large_page_mask; 676 pte_lo |= LPTE_G; 677 } 678 if (pa + moea64_large_page_size > 679 pregions[i].mr_start + pregions[i].mr_size) 680 pte_lo |= LPTE_G; 681 682 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 683 VM_PROT_EXECUTE; 684 pvo->pvo_pte.pa = pa | pte_lo; 685 moea64_pvo_enter(mmup, pvo, NULL, NULL); 686 } 687 } 688 PMAP_UNLOCK(kernel_pmap); 689 } 690 691 /* 692 * Make sure the kernel and BPVO pool stay mapped on systems either 693 * without a direct map or on which the kernel is not already executing 694 * out of the direct-mapped region. 695 */ 696 if (kernelstart < DMAP_BASE_ADDRESS) { 697 /* 698 * For pre-dmap execution, we need to use identity mapping 699 * because we will be operating with the mmu on but in the 700 * wrong address configuration until we __restartkernel(). 701 */ 702 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 703 pa += PAGE_SIZE) 704 moea64_kenter(mmup, pa, pa); 705 } else if (!hw_direct_map) { 706 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 707 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 708 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 709 pa += PAGE_SIZE) 710 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 711 } 712 713 if (!hw_direct_map) { 714 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 715 off = (vm_offset_t)(moea64_bpvo_pool); 716 for (pa = off; pa < off + size; pa += PAGE_SIZE) 717 moea64_kenter(mmup, pa, pa); 718 719 /* Map exception vectors */ 720 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 721 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 722 } 723 ENABLE_TRANS(msr); 724 725 /* 726 * Allow user to override unmapped_buf_allowed for testing. 727 * XXXKIB Only direct map implementation was tested. 728 */ 729 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 730 &unmapped_buf_allowed)) 731 unmapped_buf_allowed = hw_direct_map; 732 } 733 734 /* Quick sort callout for comparing physical addresses. */ 735 static int 736 pa_cmp(const void *a, const void *b) 737 { 738 const vm_paddr_t *pa = a, *pb = b; 739 740 if (*pa < *pb) 741 return (-1); 742 else if (*pa > *pb) 743 return (1); 744 else 745 return (0); 746 } 747 748 void 749 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 750 { 751 int i, j; 752 vm_size_t physsz, hwphyssz; 753 vm_paddr_t kernelphysstart, kernelphysend; 754 int rm_pavail; 755 756 #ifndef __powerpc64__ 757 /* We don't have a direct map since there is no BAT */ 758 hw_direct_map = 0; 759 760 /* Make sure battable is zero, since we have no BAT */ 761 for (i = 0; i < 16; i++) { 762 battable[i].batu = 0; 763 battable[i].batl = 0; 764 } 765 #else 766 moea64_probe_large_page(); 767 768 /* Use a direct map if we have large page support */ 769 if (moea64_large_page_size > 0) 770 hw_direct_map = 1; 771 else 772 hw_direct_map = 0; 773 774 /* Install trap handlers for SLBs */ 775 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 776 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 777 __syncicache((void *)EXC_DSE, 0x80); 778 __syncicache((void *)EXC_ISE, 0x80); 779 #endif 780 781 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 782 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 783 784 /* Get physical memory regions from firmware */ 785 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 786 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 787 788 if (PHYS_AVAIL_ENTRIES < regions_sz) 789 panic("moea64_bootstrap: phys_avail too small"); 790 791 phys_avail_count = 0; 792 physsz = 0; 793 hwphyssz = 0; 794 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 795 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 796 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 797 regions[i].mr_start, regions[i].mr_start + 798 regions[i].mr_size, regions[i].mr_size); 799 if (hwphyssz != 0 && 800 (physsz + regions[i].mr_size) >= hwphyssz) { 801 if (physsz < hwphyssz) { 802 phys_avail[j] = regions[i].mr_start; 803 phys_avail[j + 1] = regions[i].mr_start + 804 hwphyssz - physsz; 805 physsz = hwphyssz; 806 phys_avail_count++; 807 } 808 break; 809 } 810 phys_avail[j] = regions[i].mr_start; 811 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 812 phys_avail_count++; 813 physsz += regions[i].mr_size; 814 } 815 816 /* Check for overlap with the kernel and exception vectors */ 817 rm_pavail = 0; 818 for (j = 0; j < 2*phys_avail_count; j+=2) { 819 if (phys_avail[j] < EXC_LAST) 820 phys_avail[j] += EXC_LAST; 821 822 if (phys_avail[j] >= kernelphysstart && 823 phys_avail[j+1] <= kernelphysend) { 824 phys_avail[j] = phys_avail[j+1] = ~0; 825 rm_pavail++; 826 continue; 827 } 828 829 if (kernelphysstart >= phys_avail[j] && 830 kernelphysstart < phys_avail[j+1]) { 831 if (kernelphysend < phys_avail[j+1]) { 832 phys_avail[2*phys_avail_count] = 833 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 834 phys_avail[2*phys_avail_count + 1] = 835 phys_avail[j+1]; 836 phys_avail_count++; 837 } 838 839 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 840 } 841 842 if (kernelphysend >= phys_avail[j] && 843 kernelphysend < phys_avail[j+1]) { 844 if (kernelphysstart > phys_avail[j]) { 845 phys_avail[2*phys_avail_count] = phys_avail[j]; 846 phys_avail[2*phys_avail_count + 1] = 847 kernelphysstart & ~PAGE_MASK; 848 phys_avail_count++; 849 } 850 851 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 852 PAGE_SIZE; 853 } 854 } 855 856 /* Remove physical available regions marked for removal (~0) */ 857 if (rm_pavail) { 858 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 859 pa_cmp); 860 phys_avail_count -= rm_pavail; 861 for (i = 2*phys_avail_count; 862 i < 2*(phys_avail_count + rm_pavail); i+=2) 863 phys_avail[i] = phys_avail[i+1] = 0; 864 } 865 866 physmem = btoc(physsz); 867 868 #ifdef PTEGCOUNT 869 moea64_pteg_count = PTEGCOUNT; 870 #else 871 moea64_pteg_count = 0x1000; 872 873 while (moea64_pteg_count < physmem) 874 moea64_pteg_count <<= 1; 875 876 moea64_pteg_count >>= 1; 877 #endif /* PTEGCOUNT */ 878 } 879 880 void 881 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 882 { 883 int i; 884 885 /* 886 * Set PTEG mask 887 */ 888 moea64_pteg_mask = moea64_pteg_count - 1; 889 890 /* 891 * Initialize SLB table lock and page locks 892 */ 893 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 894 for (i = 0; i < PV_LOCK_COUNT; i++) 895 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 896 897 /* 898 * Initialise the bootstrap pvo pool. 899 */ 900 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 901 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 902 moea64_bpvo_pool_index = 0; 903 904 /* Place at address usable through the direct map */ 905 if (hw_direct_map) 906 moea64_bpvo_pool = (struct pvo_entry *) 907 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 908 909 /* 910 * Make sure kernel vsid is allocated as well as VSID 0. 911 */ 912 #ifndef __powerpc64__ 913 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 914 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 915 moea64_vsid_bitmap[0] |= 1; 916 #endif 917 918 /* 919 * Initialize the kernel pmap (which is statically allocated). 920 */ 921 #ifdef __powerpc64__ 922 for (i = 0; i < 64; i++) { 923 pcpup->pc_aim.slb[i].slbv = 0; 924 pcpup->pc_aim.slb[i].slbe = 0; 925 } 926 #else 927 for (i = 0; i < 16; i++) 928 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 929 #endif 930 931 kernel_pmap->pmap_phys = kernel_pmap; 932 CPU_FILL(&kernel_pmap->pm_active); 933 RB_INIT(&kernel_pmap->pmap_pvo); 934 935 PMAP_LOCK_INIT(kernel_pmap); 936 937 /* 938 * Now map in all the other buffers we allocated earlier 939 */ 940 941 moea64_setup_direct_map(mmup, kernelstart, kernelend); 942 } 943 944 void 945 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 946 { 947 ihandle_t mmui; 948 phandle_t chosen; 949 phandle_t mmu; 950 ssize_t sz; 951 int i; 952 vm_offset_t pa, va; 953 void *dpcpu; 954 955 /* 956 * Set up the Open Firmware pmap and add its mappings if not in real 957 * mode. 958 */ 959 960 chosen = OF_finddevice("/chosen"); 961 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 962 mmu = OF_instance_to_package(mmui); 963 if (mmu == -1 || 964 (sz = OF_getproplen(mmu, "translations")) == -1) 965 sz = 0; 966 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 967 panic("moea64_bootstrap: too many ofw translations"); 968 969 if (sz > 0) 970 moea64_add_ofw_mappings(mmup, mmu, sz); 971 } 972 973 /* 974 * Calculate the last available physical address. 975 */ 976 Maxmem = 0; 977 for (i = 0; phys_avail[i + 2] != 0; i += 2) 978 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 979 980 /* 981 * Initialize MMU. 982 */ 983 MMU_CPU_BOOTSTRAP(mmup,0); 984 mtmsr(mfmsr() | PSL_DR | PSL_IR); 985 pmap_bootstrapped++; 986 987 /* 988 * Set the start and end of kva. 989 */ 990 virtual_avail = VM_MIN_KERNEL_ADDRESS; 991 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 992 993 /* 994 * Map the entire KVA range into the SLB. We must not fault there. 995 */ 996 #ifdef __powerpc64__ 997 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 998 moea64_bootstrap_slb_prefault(va, 0); 999 #endif 1000 1001 /* 1002 * Remap any early IO mappings (console framebuffer, etc.) 1003 */ 1004 bs_remap_earlyboot(); 1005 1006 /* 1007 * Figure out how far we can extend virtual_end into segment 16 1008 * without running into existing mappings. Segment 16 is guaranteed 1009 * to contain neither RAM nor devices (at least on Apple hardware), 1010 * but will generally contain some OFW mappings we should not 1011 * step on. 1012 */ 1013 1014 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1015 PMAP_LOCK(kernel_pmap); 1016 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1017 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1018 virtual_end += PAGE_SIZE; 1019 PMAP_UNLOCK(kernel_pmap); 1020 #endif 1021 1022 /* 1023 * Allocate a kernel stack with a guard page for thread0 and map it 1024 * into the kernel page map. 1025 */ 1026 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1027 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1028 virtual_avail = va + kstack_pages * PAGE_SIZE; 1029 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1030 thread0.td_kstack = va; 1031 thread0.td_kstack_pages = kstack_pages; 1032 for (i = 0; i < kstack_pages; i++) { 1033 moea64_kenter(mmup, va, pa); 1034 pa += PAGE_SIZE; 1035 va += PAGE_SIZE; 1036 } 1037 1038 /* 1039 * Allocate virtual address space for the message buffer. 1040 */ 1041 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1042 msgbufp = (struct msgbuf *)virtual_avail; 1043 va = virtual_avail; 1044 virtual_avail += round_page(msgbufsize); 1045 while (va < virtual_avail) { 1046 moea64_kenter(mmup, va, pa); 1047 pa += PAGE_SIZE; 1048 va += PAGE_SIZE; 1049 } 1050 1051 /* 1052 * Allocate virtual address space for the dynamic percpu area. 1053 */ 1054 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1055 dpcpu = (void *)virtual_avail; 1056 va = virtual_avail; 1057 virtual_avail += DPCPU_SIZE; 1058 while (va < virtual_avail) { 1059 moea64_kenter(mmup, va, pa); 1060 pa += PAGE_SIZE; 1061 va += PAGE_SIZE; 1062 } 1063 dpcpu_init(dpcpu, curcpu); 1064 1065 /* 1066 * Allocate some things for page zeroing. We put this directly 1067 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1068 * of the PVO book-keeping or other parts of the VM system 1069 * from even knowing that this hack exists. 1070 */ 1071 1072 if (!hw_direct_map) { 1073 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1074 MTX_DEF); 1075 for (i = 0; i < 2; i++) { 1076 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1077 virtual_end -= PAGE_SIZE; 1078 1079 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1080 1081 PMAP_LOCK(kernel_pmap); 1082 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1083 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1084 PMAP_UNLOCK(kernel_pmap); 1085 } 1086 } 1087 1088 numa_mem_regions(&numa_pregions, &numapregions_sz); 1089 } 1090 1091 static void 1092 moea64_pmap_init_qpages(void) 1093 { 1094 struct pcpu *pc; 1095 int i; 1096 1097 if (hw_direct_map) 1098 return; 1099 1100 CPU_FOREACH(i) { 1101 pc = pcpu_find(i); 1102 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1103 if (pc->pc_qmap_addr == 0) 1104 panic("pmap_init_qpages: unable to allocate KVA"); 1105 PMAP_LOCK(kernel_pmap); 1106 pc->pc_aim.qmap_pvo = 1107 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1108 PMAP_UNLOCK(kernel_pmap); 1109 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1110 } 1111 } 1112 1113 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1114 1115 /* 1116 * Activate a user pmap. This mostly involves setting some non-CPU 1117 * state. 1118 */ 1119 void 1120 moea64_activate(mmu_t mmu, struct thread *td) 1121 { 1122 pmap_t pm; 1123 1124 pm = &td->td_proc->p_vmspace->vm_pmap; 1125 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1126 1127 #ifdef __powerpc64__ 1128 PCPU_SET(aim.userslb, pm->pm_slb); 1129 __asm __volatile("slbmte %0, %1; isync" :: 1130 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1131 #else 1132 PCPU_SET(curpmap, pm->pmap_phys); 1133 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1134 #endif 1135 } 1136 1137 void 1138 moea64_deactivate(mmu_t mmu, struct thread *td) 1139 { 1140 pmap_t pm; 1141 1142 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1143 1144 pm = &td->td_proc->p_vmspace->vm_pmap; 1145 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1146 #ifdef __powerpc64__ 1147 PCPU_SET(aim.userslb, NULL); 1148 #else 1149 PCPU_SET(curpmap, NULL); 1150 #endif 1151 } 1152 1153 void 1154 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1155 { 1156 struct pvo_entry key, *pvo; 1157 vm_page_t m; 1158 int64_t refchg; 1159 1160 key.pvo_vaddr = sva; 1161 PMAP_LOCK(pm); 1162 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1163 pvo != NULL && PVO_VADDR(pvo) < eva; 1164 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1165 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1166 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1167 pvo); 1168 pvo->pvo_vaddr &= ~PVO_WIRED; 1169 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1170 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1171 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1172 if (refchg < 0) 1173 refchg = LPTE_CHG; 1174 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1175 1176 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1177 if (refchg & LPTE_CHG) 1178 vm_page_dirty(m); 1179 if (refchg & LPTE_REF) 1180 vm_page_aflag_set(m, PGA_REFERENCED); 1181 } 1182 pm->pm_stats.wired_count--; 1183 } 1184 PMAP_UNLOCK(pm); 1185 } 1186 1187 /* 1188 * This goes through and sets the physical address of our 1189 * special scratch PTE to the PA we want to zero or copy. Because 1190 * of locking issues (this can get called in pvo_enter() by 1191 * the UMA allocator), we can't use most other utility functions here 1192 */ 1193 1194 static __inline 1195 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1196 { 1197 struct pvo_entry *pvo; 1198 1199 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1200 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1201 1202 pvo = moea64_scratchpage_pvo[which]; 1203 PMAP_LOCK(pvo->pvo_pmap); 1204 pvo->pvo_pte.pa = 1205 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1206 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1207 PMAP_UNLOCK(pvo->pvo_pmap); 1208 isync(); 1209 } 1210 1211 void 1212 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1213 { 1214 vm_offset_t dst; 1215 vm_offset_t src; 1216 1217 dst = VM_PAGE_TO_PHYS(mdst); 1218 src = VM_PAGE_TO_PHYS(msrc); 1219 1220 if (hw_direct_map) { 1221 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1222 PAGE_SIZE); 1223 } else { 1224 mtx_lock(&moea64_scratchpage_mtx); 1225 1226 moea64_set_scratchpage_pa(mmu, 0, src); 1227 moea64_set_scratchpage_pa(mmu, 1, dst); 1228 1229 bcopy((void *)moea64_scratchpage_va[0], 1230 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1231 1232 mtx_unlock(&moea64_scratchpage_mtx); 1233 } 1234 } 1235 1236 static inline void 1237 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1238 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1239 { 1240 void *a_cp, *b_cp; 1241 vm_offset_t a_pg_offset, b_pg_offset; 1242 int cnt; 1243 1244 while (xfersize > 0) { 1245 a_pg_offset = a_offset & PAGE_MASK; 1246 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1247 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1248 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1249 a_pg_offset; 1250 b_pg_offset = b_offset & PAGE_MASK; 1251 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1252 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1253 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1254 b_pg_offset; 1255 bcopy(a_cp, b_cp, cnt); 1256 a_offset += cnt; 1257 b_offset += cnt; 1258 xfersize -= cnt; 1259 } 1260 } 1261 1262 static inline void 1263 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1264 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1265 { 1266 void *a_cp, *b_cp; 1267 vm_offset_t a_pg_offset, b_pg_offset; 1268 int cnt; 1269 1270 mtx_lock(&moea64_scratchpage_mtx); 1271 while (xfersize > 0) { 1272 a_pg_offset = a_offset & PAGE_MASK; 1273 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1274 moea64_set_scratchpage_pa(mmu, 0, 1275 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1276 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1277 b_pg_offset = b_offset & PAGE_MASK; 1278 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1279 moea64_set_scratchpage_pa(mmu, 1, 1280 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1281 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1282 bcopy(a_cp, b_cp, cnt); 1283 a_offset += cnt; 1284 b_offset += cnt; 1285 xfersize -= cnt; 1286 } 1287 mtx_unlock(&moea64_scratchpage_mtx); 1288 } 1289 1290 void 1291 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1292 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1293 { 1294 1295 if (hw_direct_map) { 1296 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1297 xfersize); 1298 } else { 1299 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1300 xfersize); 1301 } 1302 } 1303 1304 void 1305 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1306 { 1307 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1308 1309 if (size + off > PAGE_SIZE) 1310 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1311 1312 if (hw_direct_map) { 1313 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1314 } else { 1315 mtx_lock(&moea64_scratchpage_mtx); 1316 moea64_set_scratchpage_pa(mmu, 0, pa); 1317 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1318 mtx_unlock(&moea64_scratchpage_mtx); 1319 } 1320 } 1321 1322 /* 1323 * Zero a page of physical memory by temporarily mapping it 1324 */ 1325 void 1326 moea64_zero_page(mmu_t mmu, vm_page_t m) 1327 { 1328 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1329 vm_offset_t va, off; 1330 1331 if (!hw_direct_map) { 1332 mtx_lock(&moea64_scratchpage_mtx); 1333 1334 moea64_set_scratchpage_pa(mmu, 0, pa); 1335 va = moea64_scratchpage_va[0]; 1336 } else { 1337 va = PHYS_TO_DMAP(pa); 1338 } 1339 1340 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1341 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1342 1343 if (!hw_direct_map) 1344 mtx_unlock(&moea64_scratchpage_mtx); 1345 } 1346 1347 vm_offset_t 1348 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1349 { 1350 struct pvo_entry *pvo; 1351 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1352 1353 if (hw_direct_map) 1354 return (PHYS_TO_DMAP(pa)); 1355 1356 /* 1357 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1358 * a critical section and access the PCPU data like on i386. 1359 * Instead, pin the thread and grab the PCPU lock to prevent 1360 * a preempting thread from using the same PCPU data. 1361 */ 1362 sched_pin(); 1363 1364 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1365 pvo = PCPU_GET(aim.qmap_pvo); 1366 1367 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1368 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1369 (uint64_t)pa; 1370 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1371 isync(); 1372 1373 return (PCPU_GET(qmap_addr)); 1374 } 1375 1376 void 1377 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1378 { 1379 if (hw_direct_map) 1380 return; 1381 1382 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1383 KASSERT(PCPU_GET(qmap_addr) == addr, 1384 ("moea64_quick_remove_page: invalid address")); 1385 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1386 sched_unpin(); 1387 } 1388 1389 /* 1390 * Map the given physical page at the specified virtual address in the 1391 * target pmap with the protection requested. If specified the page 1392 * will be wired down. 1393 */ 1394 1395 int 1396 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1397 vm_prot_t prot, u_int flags, int8_t psind) 1398 { 1399 struct pvo_entry *pvo, *oldpvo; 1400 struct pvo_head *pvo_head; 1401 uint64_t pte_lo; 1402 int error; 1403 1404 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1405 VM_OBJECT_ASSERT_LOCKED(m->object); 1406 1407 pvo = alloc_pvo_entry(0, M_NOWAIT); 1408 if (pvo == NULL) 1409 return (KERN_RESOURCE_SHORTAGE); 1410 pvo->pvo_pmap = NULL; /* to be filled in later */ 1411 pvo->pvo_pte.prot = prot; 1412 1413 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1414 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1415 1416 if ((flags & PMAP_ENTER_WIRED) != 0) 1417 pvo->pvo_vaddr |= PVO_WIRED; 1418 1419 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1420 pvo_head = NULL; 1421 } else { 1422 pvo_head = &m->md.mdpg_pvoh; 1423 pvo->pvo_vaddr |= PVO_MANAGED; 1424 } 1425 1426 PV_PAGE_LOCK(m); 1427 PMAP_LOCK(pmap); 1428 if (pvo->pvo_pmap == NULL) 1429 init_pvo_entry(pvo, pmap, va); 1430 if (prot & VM_PROT_WRITE) 1431 if (pmap_bootstrapped && 1432 (m->oflags & VPO_UNMANAGED) == 0) 1433 vm_page_aflag_set(m, PGA_WRITEABLE); 1434 1435 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1436 if (error == EEXIST) { 1437 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1438 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1439 oldpvo->pvo_pte.prot == prot) { 1440 /* Identical mapping already exists */ 1441 error = 0; 1442 1443 /* If not in page table, reinsert it */ 1444 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1445 STAT_MOEA64(moea64_pte_overflow--); 1446 MOEA64_PTE_INSERT(mmu, oldpvo); 1447 } 1448 1449 /* Then just clean up and go home */ 1450 PV_PAGE_UNLOCK(m); 1451 PMAP_UNLOCK(pmap); 1452 free_pvo_entry(pvo); 1453 goto out; 1454 } else { 1455 /* Otherwise, need to kill it first */ 1456 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1457 "mapping does not match new mapping")); 1458 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1459 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1460 } 1461 } 1462 PV_PAGE_UNLOCK(m); 1463 PMAP_UNLOCK(pmap); 1464 1465 /* Free any dead pages */ 1466 if (error == EEXIST) { 1467 moea64_pvo_remove_from_page(mmu, oldpvo); 1468 free_pvo_entry(oldpvo); 1469 } 1470 1471 out: 1472 /* 1473 * Flush the page from the instruction cache if this page is 1474 * mapped executable and cacheable. 1475 */ 1476 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1477 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1478 vm_page_aflag_set(m, PGA_EXECUTABLE); 1479 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1480 } 1481 return (KERN_SUCCESS); 1482 } 1483 1484 static void 1485 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1486 vm_size_t sz) 1487 { 1488 1489 /* 1490 * This is much trickier than on older systems because 1491 * we can't sync the icache on physical addresses directly 1492 * without a direct map. Instead we check a couple of cases 1493 * where the memory is already mapped in and, failing that, 1494 * use the same trick we use for page zeroing to create 1495 * a temporary mapping for this physical address. 1496 */ 1497 1498 if (!pmap_bootstrapped) { 1499 /* 1500 * If PMAP is not bootstrapped, we are likely to be 1501 * in real mode. 1502 */ 1503 __syncicache((void *)(uintptr_t)pa, sz); 1504 } else if (pmap == kernel_pmap) { 1505 __syncicache((void *)va, sz); 1506 } else if (hw_direct_map) { 1507 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1508 } else { 1509 /* Use the scratch page to set up a temp mapping */ 1510 1511 mtx_lock(&moea64_scratchpage_mtx); 1512 1513 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1514 __syncicache((void *)(moea64_scratchpage_va[1] + 1515 (va & ADDR_POFF)), sz); 1516 1517 mtx_unlock(&moea64_scratchpage_mtx); 1518 } 1519 } 1520 1521 /* 1522 * Maps a sequence of resident pages belonging to the same object. 1523 * The sequence begins with the given page m_start. This page is 1524 * mapped at the given virtual address start. Each subsequent page is 1525 * mapped at a virtual address that is offset from start by the same 1526 * amount as the page is offset from m_start within the object. The 1527 * last page in the sequence is the page with the largest offset from 1528 * m_start that can be mapped at a virtual address less than the given 1529 * virtual address end. Not every virtual page between start and end 1530 * is mapped; only those for which a resident page exists with the 1531 * corresponding offset from m_start are mapped. 1532 */ 1533 void 1534 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1535 vm_page_t m_start, vm_prot_t prot) 1536 { 1537 vm_page_t m; 1538 vm_pindex_t diff, psize; 1539 1540 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1541 1542 psize = atop(end - start); 1543 m = m_start; 1544 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1545 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1546 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1547 m = TAILQ_NEXT(m, listq); 1548 } 1549 } 1550 1551 void 1552 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1553 vm_prot_t prot) 1554 { 1555 1556 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1557 PMAP_ENTER_NOSLEEP, 0); 1558 } 1559 1560 vm_paddr_t 1561 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1562 { 1563 struct pvo_entry *pvo; 1564 vm_paddr_t pa; 1565 1566 PMAP_LOCK(pm); 1567 pvo = moea64_pvo_find_va(pm, va); 1568 if (pvo == NULL) 1569 pa = 0; 1570 else 1571 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1572 PMAP_UNLOCK(pm); 1573 1574 return (pa); 1575 } 1576 1577 /* 1578 * Atomically extract and hold the physical page with the given 1579 * pmap and virtual address pair if that mapping permits the given 1580 * protection. 1581 */ 1582 vm_page_t 1583 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1584 { 1585 struct pvo_entry *pvo; 1586 vm_page_t m; 1587 vm_paddr_t pa; 1588 1589 m = NULL; 1590 pa = 0; 1591 PMAP_LOCK(pmap); 1592 retry: 1593 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1594 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1595 if (vm_page_pa_tryrelock(pmap, 1596 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1597 goto retry; 1598 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1599 vm_page_wire(m); 1600 } 1601 PA_UNLOCK_COND(pa); 1602 PMAP_UNLOCK(pmap); 1603 return (m); 1604 } 1605 1606 static mmu_t installed_mmu; 1607 1608 static void * 1609 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1610 uint8_t *flags, int wait) 1611 { 1612 struct pvo_entry *pvo; 1613 vm_offset_t va; 1614 vm_page_t m; 1615 int needed_lock; 1616 1617 /* 1618 * This entire routine is a horrible hack to avoid bothering kmem 1619 * for new KVA addresses. Because this can get called from inside 1620 * kmem allocation routines, calling kmem for a new address here 1621 * can lead to multiply locking non-recursive mutexes. 1622 */ 1623 1624 *flags = UMA_SLAB_PRIV; 1625 needed_lock = !PMAP_LOCKED(kernel_pmap); 1626 1627 m = vm_page_alloc_domain(NULL, 0, domain, 1628 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1629 if (m == NULL) 1630 return (NULL); 1631 1632 va = VM_PAGE_TO_PHYS(m); 1633 1634 pvo = alloc_pvo_entry(1 /* bootstrap */, 0); 1635 1636 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1637 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1638 1639 if (needed_lock) 1640 PMAP_LOCK(kernel_pmap); 1641 1642 init_pvo_entry(pvo, kernel_pmap, va); 1643 pvo->pvo_vaddr |= PVO_WIRED; 1644 1645 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1646 1647 if (needed_lock) 1648 PMAP_UNLOCK(kernel_pmap); 1649 1650 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1651 bzero((void *)va, PAGE_SIZE); 1652 1653 return (void *)va; 1654 } 1655 1656 extern int elf32_nxstack; 1657 1658 void 1659 moea64_init(mmu_t mmu) 1660 { 1661 1662 CTR0(KTR_PMAP, "moea64_init"); 1663 1664 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1665 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1666 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1667 1668 if (!hw_direct_map) { 1669 installed_mmu = mmu; 1670 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1671 } 1672 1673 #ifdef COMPAT_FREEBSD32 1674 elf32_nxstack = 1; 1675 #endif 1676 1677 moea64_initialized = TRUE; 1678 } 1679 1680 boolean_t 1681 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1682 { 1683 1684 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1685 ("moea64_is_referenced: page %p is not managed", m)); 1686 1687 return (moea64_query_bit(mmu, m, LPTE_REF)); 1688 } 1689 1690 boolean_t 1691 moea64_is_modified(mmu_t mmu, vm_page_t m) 1692 { 1693 1694 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1695 ("moea64_is_modified: page %p is not managed", m)); 1696 1697 /* 1698 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1699 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1700 * is clear, no PTEs can have LPTE_CHG set. 1701 */ 1702 VM_OBJECT_ASSERT_LOCKED(m->object); 1703 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1704 return (FALSE); 1705 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1706 } 1707 1708 boolean_t 1709 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1710 { 1711 struct pvo_entry *pvo; 1712 boolean_t rv = TRUE; 1713 1714 PMAP_LOCK(pmap); 1715 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1716 if (pvo != NULL) 1717 rv = FALSE; 1718 PMAP_UNLOCK(pmap); 1719 return (rv); 1720 } 1721 1722 void 1723 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1724 { 1725 1726 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1727 ("moea64_clear_modify: page %p is not managed", m)); 1728 VM_OBJECT_ASSERT_WLOCKED(m->object); 1729 KASSERT(!vm_page_xbusied(m), 1730 ("moea64_clear_modify: page %p is exclusive busied", m)); 1731 1732 /* 1733 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1734 * set. If the object containing the page is locked and the page is 1735 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1736 */ 1737 if ((m->aflags & PGA_WRITEABLE) == 0) 1738 return; 1739 moea64_clear_bit(mmu, m, LPTE_CHG); 1740 } 1741 1742 /* 1743 * Clear the write and modified bits in each of the given page's mappings. 1744 */ 1745 void 1746 moea64_remove_write(mmu_t mmu, vm_page_t m) 1747 { 1748 struct pvo_entry *pvo; 1749 int64_t refchg, ret; 1750 pmap_t pmap; 1751 1752 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1753 ("moea64_remove_write: page %p is not managed", m)); 1754 1755 /* 1756 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1757 * set by another thread while the object is locked. Thus, 1758 * if PGA_WRITEABLE is clear, no page table entries need updating. 1759 */ 1760 VM_OBJECT_ASSERT_WLOCKED(m->object); 1761 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1762 return; 1763 powerpc_sync(); 1764 PV_PAGE_LOCK(m); 1765 refchg = 0; 1766 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1767 pmap = pvo->pvo_pmap; 1768 PMAP_LOCK(pmap); 1769 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1770 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1771 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1772 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1773 MOEA64_PTE_PROT_UPDATE); 1774 if (ret < 0) 1775 ret = LPTE_CHG; 1776 refchg |= ret; 1777 if (pvo->pvo_pmap == kernel_pmap) 1778 isync(); 1779 } 1780 PMAP_UNLOCK(pmap); 1781 } 1782 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1783 vm_page_dirty(m); 1784 vm_page_aflag_clear(m, PGA_WRITEABLE); 1785 PV_PAGE_UNLOCK(m); 1786 } 1787 1788 /* 1789 * moea64_ts_referenced: 1790 * 1791 * Return a count of reference bits for a page, clearing those bits. 1792 * It is not necessary for every reference bit to be cleared, but it 1793 * is necessary that 0 only be returned when there are truly no 1794 * reference bits set. 1795 * 1796 * XXX: The exact number of bits to check and clear is a matter that 1797 * should be tested and standardized at some point in the future for 1798 * optimal aging of shared pages. 1799 */ 1800 int 1801 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1802 { 1803 1804 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1805 ("moea64_ts_referenced: page %p is not managed", m)); 1806 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1807 } 1808 1809 /* 1810 * Modify the WIMG settings of all mappings for a page. 1811 */ 1812 void 1813 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1814 { 1815 struct pvo_entry *pvo; 1816 int64_t refchg; 1817 pmap_t pmap; 1818 uint64_t lo; 1819 1820 if ((m->oflags & VPO_UNMANAGED) != 0) { 1821 m->md.mdpg_cache_attrs = ma; 1822 return; 1823 } 1824 1825 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1826 1827 PV_PAGE_LOCK(m); 1828 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1829 pmap = pvo->pvo_pmap; 1830 PMAP_LOCK(pmap); 1831 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1832 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1833 pvo->pvo_pte.pa |= lo; 1834 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1835 MOEA64_PTE_INVALIDATE); 1836 if (refchg < 0) 1837 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1838 LPTE_CHG : 0; 1839 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1840 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1841 refchg |= 1842 atomic_readandclear_32(&m->md.mdpg_attrs); 1843 if (refchg & LPTE_CHG) 1844 vm_page_dirty(m); 1845 if (refchg & LPTE_REF) 1846 vm_page_aflag_set(m, PGA_REFERENCED); 1847 } 1848 if (pvo->pvo_pmap == kernel_pmap) 1849 isync(); 1850 } 1851 PMAP_UNLOCK(pmap); 1852 } 1853 m->md.mdpg_cache_attrs = ma; 1854 PV_PAGE_UNLOCK(m); 1855 } 1856 1857 /* 1858 * Map a wired page into kernel virtual address space. 1859 */ 1860 void 1861 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1862 { 1863 int error; 1864 struct pvo_entry *pvo, *oldpvo; 1865 1866 pvo = alloc_pvo_entry(0, M_WAITOK); 1867 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1868 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1869 pvo->pvo_vaddr |= PVO_WIRED; 1870 1871 PMAP_LOCK(kernel_pmap); 1872 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1873 if (oldpvo != NULL) 1874 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1875 init_pvo_entry(pvo, kernel_pmap, va); 1876 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1877 PMAP_UNLOCK(kernel_pmap); 1878 1879 /* Free any dead pages */ 1880 if (oldpvo != NULL) { 1881 moea64_pvo_remove_from_page(mmu, oldpvo); 1882 free_pvo_entry(oldpvo); 1883 } 1884 1885 if (error != 0 && error != ENOENT) 1886 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1887 (uintmax_t)pa, error); 1888 } 1889 1890 void 1891 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1892 { 1893 1894 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1895 } 1896 1897 /* 1898 * Extract the physical page address associated with the given kernel virtual 1899 * address. 1900 */ 1901 vm_paddr_t 1902 moea64_kextract(mmu_t mmu, vm_offset_t va) 1903 { 1904 struct pvo_entry *pvo; 1905 vm_paddr_t pa; 1906 1907 /* 1908 * Shortcut the direct-mapped case when applicable. We never put 1909 * anything but 1:1 (or 62-bit aliased) mappings below 1910 * VM_MIN_KERNEL_ADDRESS. 1911 */ 1912 if (va < VM_MIN_KERNEL_ADDRESS) 1913 return (va & ~DMAP_BASE_ADDRESS); 1914 1915 PMAP_LOCK(kernel_pmap); 1916 pvo = moea64_pvo_find_va(kernel_pmap, va); 1917 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1918 va)); 1919 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1920 PMAP_UNLOCK(kernel_pmap); 1921 return (pa); 1922 } 1923 1924 /* 1925 * Remove a wired page from kernel virtual address space. 1926 */ 1927 void 1928 moea64_kremove(mmu_t mmu, vm_offset_t va) 1929 { 1930 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1931 } 1932 1933 /* 1934 * Provide a kernel pointer corresponding to a given userland pointer. 1935 * The returned pointer is valid until the next time this function is 1936 * called in this thread. This is used internally in copyin/copyout. 1937 */ 1938 static int 1939 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1940 void **kaddr, size_t ulen, size_t *klen) 1941 { 1942 size_t l; 1943 #ifdef __powerpc64__ 1944 struct slb *slb; 1945 #endif 1946 register_t slbv; 1947 1948 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1949 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1950 if (l > ulen) 1951 l = ulen; 1952 if (klen) 1953 *klen = l; 1954 else if (l != ulen) 1955 return (EFAULT); 1956 1957 #ifdef __powerpc64__ 1958 /* Try lockless look-up first */ 1959 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1960 1961 if (slb == NULL) { 1962 /* If it isn't there, we need to pre-fault the VSID */ 1963 PMAP_LOCK(pm); 1964 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1965 PMAP_UNLOCK(pm); 1966 } else { 1967 slbv = slb->slbv; 1968 } 1969 1970 /* Mark segment no-execute */ 1971 slbv |= SLBV_N; 1972 #else 1973 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1974 1975 /* Mark segment no-execute */ 1976 slbv |= SR_N; 1977 #endif 1978 1979 /* If we have already set this VSID, we can just return */ 1980 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1981 return (0); 1982 1983 __asm __volatile("isync"); 1984 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1985 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1986 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1987 #ifdef __powerpc64__ 1988 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1989 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1990 #else 1991 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1992 #endif 1993 1994 return (0); 1995 } 1996 1997 /* 1998 * Figure out where a given kernel pointer (usually in a fault) points 1999 * to from the VM's perspective, potentially remapping into userland's 2000 * address space. 2001 */ 2002 static int 2003 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2004 vm_offset_t *decoded_addr) 2005 { 2006 vm_offset_t user_sr; 2007 2008 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2009 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2010 addr &= ADDR_PIDX | ADDR_POFF; 2011 addr |= user_sr << ADDR_SR_SHFT; 2012 *decoded_addr = addr; 2013 *is_user = 1; 2014 } else { 2015 *decoded_addr = addr; 2016 *is_user = 0; 2017 } 2018 2019 return (0); 2020 } 2021 2022 /* 2023 * Map a range of physical addresses into kernel virtual address space. 2024 * 2025 * The value passed in *virt is a suggested virtual address for the mapping. 2026 * Architectures which can support a direct-mapped physical to virtual region 2027 * can return the appropriate address within that region, leaving '*virt' 2028 * unchanged. Other architectures should map the pages starting at '*virt' and 2029 * update '*virt' with the first usable address after the mapped region. 2030 */ 2031 vm_offset_t 2032 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2033 vm_paddr_t pa_end, int prot) 2034 { 2035 vm_offset_t sva, va; 2036 2037 if (hw_direct_map) { 2038 /* 2039 * Check if every page in the region is covered by the direct 2040 * map. The direct map covers all of physical memory. Use 2041 * moea64_calc_wimg() as a shortcut to see if the page is in 2042 * physical memory as a way to see if the direct map covers it. 2043 */ 2044 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2045 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2046 break; 2047 if (va == pa_end) 2048 return (PHYS_TO_DMAP(pa_start)); 2049 } 2050 sva = *virt; 2051 va = sva; 2052 /* XXX respect prot argument */ 2053 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2054 moea64_kenter(mmu, va, pa_start); 2055 *virt = va; 2056 2057 return (sva); 2058 } 2059 2060 /* 2061 * Returns true if the pmap's pv is one of the first 2062 * 16 pvs linked to from this page. This count may 2063 * be changed upwards or downwards in the future; it 2064 * is only necessary that true be returned for a small 2065 * subset of pmaps for proper page aging. 2066 */ 2067 boolean_t 2068 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2069 { 2070 int loops; 2071 struct pvo_entry *pvo; 2072 boolean_t rv; 2073 2074 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2075 ("moea64_page_exists_quick: page %p is not managed", m)); 2076 loops = 0; 2077 rv = FALSE; 2078 PV_PAGE_LOCK(m); 2079 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2080 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2081 rv = TRUE; 2082 break; 2083 } 2084 if (++loops >= 16) 2085 break; 2086 } 2087 PV_PAGE_UNLOCK(m); 2088 return (rv); 2089 } 2090 2091 void 2092 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2093 { 2094 2095 m->md.mdpg_attrs = 0; 2096 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2097 LIST_INIT(&m->md.mdpg_pvoh); 2098 } 2099 2100 /* 2101 * Return the number of managed mappings to the given physical page 2102 * that are wired. 2103 */ 2104 int 2105 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2106 { 2107 struct pvo_entry *pvo; 2108 int count; 2109 2110 count = 0; 2111 if ((m->oflags & VPO_UNMANAGED) != 0) 2112 return (count); 2113 PV_PAGE_LOCK(m); 2114 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2115 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2116 count++; 2117 PV_PAGE_UNLOCK(m); 2118 return (count); 2119 } 2120 2121 static uintptr_t moea64_vsidcontext; 2122 2123 uintptr_t 2124 moea64_get_unique_vsid(void) { 2125 u_int entropy; 2126 register_t hash; 2127 uint32_t mask; 2128 int i; 2129 2130 entropy = 0; 2131 __asm __volatile("mftb %0" : "=r"(entropy)); 2132 2133 mtx_lock(&moea64_slb_mutex); 2134 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2135 u_int n; 2136 2137 /* 2138 * Create a new value by mutiplying by a prime and adding in 2139 * entropy from the timebase register. This is to make the 2140 * VSID more random so that the PT hash function collides 2141 * less often. (Note that the prime casues gcc to do shifts 2142 * instead of a multiply.) 2143 */ 2144 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2145 hash = moea64_vsidcontext & (NVSIDS - 1); 2146 if (hash == 0) /* 0 is special, avoid it */ 2147 continue; 2148 n = hash >> 5; 2149 mask = 1 << (hash & (VSID_NBPW - 1)); 2150 hash = (moea64_vsidcontext & VSID_HASHMASK); 2151 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2152 /* anything free in this bucket? */ 2153 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2154 entropy = (moea64_vsidcontext >> 20); 2155 continue; 2156 } 2157 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2158 mask = 1 << i; 2159 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2160 hash |= i; 2161 } 2162 if (hash == VSID_VRMA) /* also special, avoid this too */ 2163 continue; 2164 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2165 ("Allocating in-use VSID %#zx\n", hash)); 2166 moea64_vsid_bitmap[n] |= mask; 2167 mtx_unlock(&moea64_slb_mutex); 2168 return (hash); 2169 } 2170 2171 mtx_unlock(&moea64_slb_mutex); 2172 panic("%s: out of segments",__func__); 2173 } 2174 2175 #ifdef __powerpc64__ 2176 void 2177 moea64_pinit(mmu_t mmu, pmap_t pmap) 2178 { 2179 2180 RB_INIT(&pmap->pmap_pvo); 2181 2182 pmap->pm_slb_tree_root = slb_alloc_tree(); 2183 pmap->pm_slb = slb_alloc_user_cache(); 2184 pmap->pm_slb_len = 0; 2185 } 2186 #else 2187 void 2188 moea64_pinit(mmu_t mmu, pmap_t pmap) 2189 { 2190 int i; 2191 uint32_t hash; 2192 2193 RB_INIT(&pmap->pmap_pvo); 2194 2195 if (pmap_bootstrapped) 2196 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2197 (vm_offset_t)pmap); 2198 else 2199 pmap->pmap_phys = pmap; 2200 2201 /* 2202 * Allocate some segment registers for this pmap. 2203 */ 2204 hash = moea64_get_unique_vsid(); 2205 2206 for (i = 0; i < 16; i++) 2207 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2208 2209 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2210 } 2211 #endif 2212 2213 /* 2214 * Initialize the pmap associated with process 0. 2215 */ 2216 void 2217 moea64_pinit0(mmu_t mmu, pmap_t pm) 2218 { 2219 2220 PMAP_LOCK_INIT(pm); 2221 moea64_pinit(mmu, pm); 2222 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2223 } 2224 2225 /* 2226 * Set the physical protection on the specified range of this map as requested. 2227 */ 2228 static void 2229 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2230 { 2231 struct vm_page *pg; 2232 vm_prot_t oldprot; 2233 int32_t refchg; 2234 2235 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2236 2237 /* 2238 * Change the protection of the page. 2239 */ 2240 oldprot = pvo->pvo_pte.prot; 2241 pvo->pvo_pte.prot = prot; 2242 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2243 2244 /* 2245 * If the PVO is in the page table, update mapping 2246 */ 2247 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2248 if (refchg < 0) 2249 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2250 2251 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2252 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2253 if ((pg->oflags & VPO_UNMANAGED) == 0) 2254 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2255 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2256 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2257 } 2258 2259 /* 2260 * Update vm about the REF/CHG bits if the page is managed and we have 2261 * removed write access. 2262 */ 2263 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2264 (oldprot & VM_PROT_WRITE)) { 2265 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2266 if (refchg & LPTE_CHG) 2267 vm_page_dirty(pg); 2268 if (refchg & LPTE_REF) 2269 vm_page_aflag_set(pg, PGA_REFERENCED); 2270 } 2271 } 2272 2273 void 2274 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2275 vm_prot_t prot) 2276 { 2277 struct pvo_entry *pvo, *tpvo, key; 2278 2279 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2280 sva, eva, prot); 2281 2282 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2283 ("moea64_protect: non current pmap")); 2284 2285 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2286 moea64_remove(mmu, pm, sva, eva); 2287 return; 2288 } 2289 2290 PMAP_LOCK(pm); 2291 key.pvo_vaddr = sva; 2292 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2293 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2294 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2295 moea64_pvo_protect(mmu, pm, pvo, prot); 2296 } 2297 PMAP_UNLOCK(pm); 2298 } 2299 2300 /* 2301 * Map a list of wired pages into kernel virtual address space. This is 2302 * intended for temporary mappings which do not need page modification or 2303 * references recorded. Existing mappings in the region are overwritten. 2304 */ 2305 void 2306 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2307 { 2308 while (count-- > 0) { 2309 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2310 va += PAGE_SIZE; 2311 m++; 2312 } 2313 } 2314 2315 /* 2316 * Remove page mappings from kernel virtual address space. Intended for 2317 * temporary mappings entered by moea64_qenter. 2318 */ 2319 void 2320 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2321 { 2322 while (count-- > 0) { 2323 moea64_kremove(mmu, va); 2324 va += PAGE_SIZE; 2325 } 2326 } 2327 2328 void 2329 moea64_release_vsid(uint64_t vsid) 2330 { 2331 int idx, mask; 2332 2333 mtx_lock(&moea64_slb_mutex); 2334 idx = vsid & (NVSIDS-1); 2335 mask = 1 << (idx % VSID_NBPW); 2336 idx /= VSID_NBPW; 2337 KASSERT(moea64_vsid_bitmap[idx] & mask, 2338 ("Freeing unallocated VSID %#jx", vsid)); 2339 moea64_vsid_bitmap[idx] &= ~mask; 2340 mtx_unlock(&moea64_slb_mutex); 2341 } 2342 2343 2344 void 2345 moea64_release(mmu_t mmu, pmap_t pmap) 2346 { 2347 2348 /* 2349 * Free segment registers' VSIDs 2350 */ 2351 #ifdef __powerpc64__ 2352 slb_free_tree(pmap); 2353 slb_free_user_cache(pmap->pm_slb); 2354 #else 2355 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2356 2357 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2358 #endif 2359 } 2360 2361 /* 2362 * Remove all pages mapped by the specified pmap 2363 */ 2364 void 2365 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2366 { 2367 struct pvo_entry *pvo, *tpvo; 2368 struct pvo_dlist tofree; 2369 2370 SLIST_INIT(&tofree); 2371 2372 PMAP_LOCK(pm); 2373 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2374 if (pvo->pvo_vaddr & PVO_WIRED) 2375 continue; 2376 2377 /* 2378 * For locking reasons, remove this from the page table and 2379 * pmap, but save delinking from the vm_page for a second 2380 * pass 2381 */ 2382 moea64_pvo_remove_from_pmap(mmu, pvo); 2383 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2384 } 2385 PMAP_UNLOCK(pm); 2386 2387 while (!SLIST_EMPTY(&tofree)) { 2388 pvo = SLIST_FIRST(&tofree); 2389 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2390 moea64_pvo_remove_from_page(mmu, pvo); 2391 free_pvo_entry(pvo); 2392 } 2393 } 2394 2395 /* 2396 * Remove the given range of addresses from the specified map. 2397 */ 2398 void 2399 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2400 { 2401 struct pvo_entry *pvo, *tpvo, key; 2402 struct pvo_dlist tofree; 2403 2404 /* 2405 * Perform an unsynchronized read. This is, however, safe. 2406 */ 2407 if (pm->pm_stats.resident_count == 0) 2408 return; 2409 2410 key.pvo_vaddr = sva; 2411 2412 SLIST_INIT(&tofree); 2413 2414 PMAP_LOCK(pm); 2415 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2416 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2417 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2418 2419 /* 2420 * For locking reasons, remove this from the page table and 2421 * pmap, but save delinking from the vm_page for a second 2422 * pass 2423 */ 2424 moea64_pvo_remove_from_pmap(mmu, pvo); 2425 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2426 } 2427 PMAP_UNLOCK(pm); 2428 2429 while (!SLIST_EMPTY(&tofree)) { 2430 pvo = SLIST_FIRST(&tofree); 2431 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2432 moea64_pvo_remove_from_page(mmu, pvo); 2433 free_pvo_entry(pvo); 2434 } 2435 } 2436 2437 /* 2438 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2439 * will reflect changes in pte's back to the vm_page. 2440 */ 2441 void 2442 moea64_remove_all(mmu_t mmu, vm_page_t m) 2443 { 2444 struct pvo_entry *pvo, *next_pvo; 2445 struct pvo_head freequeue; 2446 int wasdead; 2447 pmap_t pmap; 2448 2449 LIST_INIT(&freequeue); 2450 2451 PV_PAGE_LOCK(m); 2452 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2453 pmap = pvo->pvo_pmap; 2454 PMAP_LOCK(pmap); 2455 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2456 if (!wasdead) 2457 moea64_pvo_remove_from_pmap(mmu, pvo); 2458 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2459 if (!wasdead) 2460 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2461 PMAP_UNLOCK(pmap); 2462 2463 } 2464 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2465 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2466 PV_PAGE_UNLOCK(m); 2467 2468 /* Clean up UMA allocations */ 2469 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2470 free_pvo_entry(pvo); 2471 } 2472 2473 /* 2474 * Allocate a physical page of memory directly from the phys_avail map. 2475 * Can only be called from moea64_bootstrap before avail start and end are 2476 * calculated. 2477 */ 2478 vm_offset_t 2479 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2480 { 2481 vm_offset_t s, e; 2482 int i, j; 2483 2484 size = round_page(size); 2485 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2486 if (align != 0) 2487 s = roundup2(phys_avail[i], align); 2488 else 2489 s = phys_avail[i]; 2490 e = s + size; 2491 2492 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2493 continue; 2494 2495 if (s + size > platform_real_maxaddr()) 2496 continue; 2497 2498 if (s == phys_avail[i]) { 2499 phys_avail[i] += size; 2500 } else if (e == phys_avail[i + 1]) { 2501 phys_avail[i + 1] -= size; 2502 } else { 2503 for (j = phys_avail_count * 2; j > i; j -= 2) { 2504 phys_avail[j] = phys_avail[j - 2]; 2505 phys_avail[j + 1] = phys_avail[j - 1]; 2506 } 2507 2508 phys_avail[i + 3] = phys_avail[i + 1]; 2509 phys_avail[i + 1] = s; 2510 phys_avail[i + 2] = e; 2511 phys_avail_count++; 2512 } 2513 2514 return (s); 2515 } 2516 panic("moea64_bootstrap_alloc: could not allocate memory"); 2517 } 2518 2519 static int 2520 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2521 struct pvo_entry **oldpvop) 2522 { 2523 int first, err; 2524 struct pvo_entry *old_pvo; 2525 2526 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2527 2528 STAT_MOEA64(moea64_pvo_enter_calls++); 2529 2530 /* 2531 * Add to pmap list 2532 */ 2533 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2534 2535 if (old_pvo != NULL) { 2536 if (oldpvop != NULL) 2537 *oldpvop = old_pvo; 2538 return (EEXIST); 2539 } 2540 2541 /* 2542 * Remember if the list was empty and therefore will be the first 2543 * item. 2544 */ 2545 if (pvo_head != NULL) { 2546 if (LIST_FIRST(pvo_head) == NULL) 2547 first = 1; 2548 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2549 } 2550 2551 if (pvo->pvo_vaddr & PVO_WIRED) 2552 pvo->pvo_pmap->pm_stats.wired_count++; 2553 pvo->pvo_pmap->pm_stats.resident_count++; 2554 2555 /* 2556 * Insert it into the hardware page table 2557 */ 2558 err = MOEA64_PTE_INSERT(mmu, pvo); 2559 if (err != 0) { 2560 panic("moea64_pvo_enter: overflow"); 2561 } 2562 2563 STAT_MOEA64(moea64_pvo_entries++); 2564 2565 if (pvo->pvo_pmap == kernel_pmap) 2566 isync(); 2567 2568 #ifdef __powerpc64__ 2569 /* 2570 * Make sure all our bootstrap mappings are in the SLB as soon 2571 * as virtual memory is switched on. 2572 */ 2573 if (!pmap_bootstrapped) 2574 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2575 pvo->pvo_vaddr & PVO_LARGE); 2576 #endif 2577 2578 return (first ? ENOENT : 0); 2579 } 2580 2581 static void 2582 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2583 { 2584 struct vm_page *pg; 2585 int32_t refchg; 2586 2587 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2588 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2589 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2590 2591 /* 2592 * If there is an active pte entry, we need to deactivate it 2593 */ 2594 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2595 if (refchg < 0) { 2596 /* 2597 * If it was evicted from the page table, be pessimistic and 2598 * dirty the page. 2599 */ 2600 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2601 refchg = LPTE_CHG; 2602 else 2603 refchg = 0; 2604 } 2605 2606 /* 2607 * Update our statistics. 2608 */ 2609 pvo->pvo_pmap->pm_stats.resident_count--; 2610 if (pvo->pvo_vaddr & PVO_WIRED) 2611 pvo->pvo_pmap->pm_stats.wired_count--; 2612 2613 /* 2614 * Remove this PVO from the pmap list. 2615 */ 2616 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2617 2618 /* 2619 * Mark this for the next sweep 2620 */ 2621 pvo->pvo_vaddr |= PVO_DEAD; 2622 2623 /* Send RC bits to VM */ 2624 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2625 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2626 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2627 if (pg != NULL) { 2628 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2629 if (refchg & LPTE_CHG) 2630 vm_page_dirty(pg); 2631 if (refchg & LPTE_REF) 2632 vm_page_aflag_set(pg, PGA_REFERENCED); 2633 } 2634 } 2635 } 2636 2637 static inline void 2638 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2639 vm_page_t m) 2640 { 2641 2642 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2643 2644 /* Use NULL pmaps as a sentinel for races in page deletion */ 2645 if (pvo->pvo_pmap == NULL) 2646 return; 2647 pvo->pvo_pmap = NULL; 2648 2649 /* 2650 * Update vm about page writeability/executability if managed 2651 */ 2652 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2653 if (pvo->pvo_vaddr & PVO_MANAGED) { 2654 if (m != NULL) { 2655 LIST_REMOVE(pvo, pvo_vlink); 2656 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2657 vm_page_aflag_clear(m, 2658 PGA_WRITEABLE | PGA_EXECUTABLE); 2659 } 2660 } 2661 2662 STAT_MOEA64(moea64_pvo_entries--); 2663 STAT_MOEA64(moea64_pvo_remove_calls++); 2664 } 2665 2666 static void 2667 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2668 { 2669 vm_page_t pg = NULL; 2670 2671 if (pvo->pvo_vaddr & PVO_MANAGED) 2672 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2673 2674 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2675 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2676 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2677 } 2678 2679 static struct pvo_entry * 2680 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2681 { 2682 struct pvo_entry key; 2683 2684 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2685 2686 key.pvo_vaddr = va & ~ADDR_POFF; 2687 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2688 } 2689 2690 static boolean_t 2691 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2692 { 2693 struct pvo_entry *pvo; 2694 int64_t ret; 2695 boolean_t rv; 2696 2697 /* 2698 * See if this bit is stored in the page already. 2699 */ 2700 if (m->md.mdpg_attrs & ptebit) 2701 return (TRUE); 2702 2703 /* 2704 * Examine each PTE. Sync so that any pending REF/CHG bits are 2705 * flushed to the PTEs. 2706 */ 2707 rv = FALSE; 2708 powerpc_sync(); 2709 PV_PAGE_LOCK(m); 2710 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2711 ret = 0; 2712 2713 /* 2714 * See if this pvo has a valid PTE. if so, fetch the 2715 * REF/CHG bits from the valid PTE. If the appropriate 2716 * ptebit is set, return success. 2717 */ 2718 PMAP_LOCK(pvo->pvo_pmap); 2719 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2720 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2721 PMAP_UNLOCK(pvo->pvo_pmap); 2722 2723 if (ret > 0) { 2724 atomic_set_32(&m->md.mdpg_attrs, 2725 ret & (LPTE_CHG | LPTE_REF)); 2726 if (ret & ptebit) { 2727 rv = TRUE; 2728 break; 2729 } 2730 } 2731 } 2732 PV_PAGE_UNLOCK(m); 2733 2734 return (rv); 2735 } 2736 2737 static u_int 2738 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2739 { 2740 u_int count; 2741 struct pvo_entry *pvo; 2742 int64_t ret; 2743 2744 /* 2745 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2746 * we can reset the right ones). 2747 */ 2748 powerpc_sync(); 2749 2750 /* 2751 * For each pvo entry, clear the pte's ptebit. 2752 */ 2753 count = 0; 2754 PV_PAGE_LOCK(m); 2755 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2756 ret = 0; 2757 2758 PMAP_LOCK(pvo->pvo_pmap); 2759 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2760 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2761 PMAP_UNLOCK(pvo->pvo_pmap); 2762 2763 if (ret > 0 && (ret & ptebit)) 2764 count++; 2765 } 2766 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2767 PV_PAGE_UNLOCK(m); 2768 2769 return (count); 2770 } 2771 2772 boolean_t 2773 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2774 { 2775 struct pvo_entry *pvo, key; 2776 vm_offset_t ppa; 2777 int error = 0; 2778 2779 if (hw_direct_map && mem_valid(pa, size) == 0) 2780 return (0); 2781 2782 PMAP_LOCK(kernel_pmap); 2783 ppa = pa & ~ADDR_POFF; 2784 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2785 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2786 ppa < pa + size; ppa += PAGE_SIZE, 2787 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2788 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2789 error = EFAULT; 2790 break; 2791 } 2792 } 2793 PMAP_UNLOCK(kernel_pmap); 2794 2795 return (error); 2796 } 2797 2798 /* 2799 * Map a set of physical memory pages into the kernel virtual 2800 * address space. Return a pointer to where it is mapped. This 2801 * routine is intended to be used for mapping device memory, 2802 * NOT real memory. 2803 */ 2804 void * 2805 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2806 { 2807 vm_offset_t va, tmpva, ppa, offset; 2808 2809 ppa = trunc_page(pa); 2810 offset = pa & PAGE_MASK; 2811 size = roundup2(offset + size, PAGE_SIZE); 2812 2813 va = kva_alloc(size); 2814 2815 if (!va) 2816 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2817 2818 for (tmpva = va; size > 0;) { 2819 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2820 size -= PAGE_SIZE; 2821 tmpva += PAGE_SIZE; 2822 ppa += PAGE_SIZE; 2823 } 2824 2825 return ((void *)(va + offset)); 2826 } 2827 2828 void * 2829 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2830 { 2831 2832 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2833 } 2834 2835 void 2836 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2837 { 2838 vm_offset_t base, offset; 2839 2840 base = trunc_page(va); 2841 offset = va & PAGE_MASK; 2842 size = roundup2(offset + size, PAGE_SIZE); 2843 2844 kva_free(base, size); 2845 } 2846 2847 void 2848 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2849 { 2850 struct pvo_entry *pvo; 2851 vm_offset_t lim; 2852 vm_paddr_t pa; 2853 vm_size_t len; 2854 2855 if (__predict_false(pm == NULL)) 2856 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2857 2858 PMAP_LOCK(pm); 2859 while (sz > 0) { 2860 lim = round_page(va+1); 2861 len = MIN(lim - va, sz); 2862 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2863 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2864 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2865 moea64_syncicache(mmu, pm, va, pa, len); 2866 } 2867 va += len; 2868 sz -= len; 2869 } 2870 PMAP_UNLOCK(pm); 2871 } 2872 2873 void 2874 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2875 { 2876 2877 *va = (void *)(uintptr_t)pa; 2878 } 2879 2880 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2881 2882 void 2883 moea64_scan_init(mmu_t mmu) 2884 { 2885 struct pvo_entry *pvo; 2886 vm_offset_t va; 2887 int i; 2888 2889 if (!do_minidump) { 2890 /* Initialize phys. segments for dumpsys(). */ 2891 memset(&dump_map, 0, sizeof(dump_map)); 2892 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2893 for (i = 0; i < pregions_sz; i++) { 2894 dump_map[i].pa_start = pregions[i].mr_start; 2895 dump_map[i].pa_size = pregions[i].mr_size; 2896 } 2897 return; 2898 } 2899 2900 /* Virtual segments for minidumps: */ 2901 memset(&dump_map, 0, sizeof(dump_map)); 2902 2903 /* 1st: kernel .data and .bss. */ 2904 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2905 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2906 dump_map[0].pa_start; 2907 2908 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2909 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2910 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2911 2912 /* 3rd: kernel VM. */ 2913 va = dump_map[1].pa_start + dump_map[1].pa_size; 2914 /* Find start of next chunk (from va). */ 2915 while (va < virtual_end) { 2916 /* Don't dump the buffer cache. */ 2917 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2918 va = kmi.buffer_eva; 2919 continue; 2920 } 2921 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2922 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2923 break; 2924 va += PAGE_SIZE; 2925 } 2926 if (va < virtual_end) { 2927 dump_map[2].pa_start = va; 2928 va += PAGE_SIZE; 2929 /* Find last page in chunk. */ 2930 while (va < virtual_end) { 2931 /* Don't run into the buffer cache. */ 2932 if (va == kmi.buffer_sva) 2933 break; 2934 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2935 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2936 break; 2937 va += PAGE_SIZE; 2938 } 2939 dump_map[2].pa_size = va - dump_map[2].pa_start; 2940 } 2941 } 2942 2943