1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/cpu.h> 146 #include <machine/platform.h> 147 #include <machine/frame.h> 148 #include <machine/md_var.h> 149 #include <machine/psl.h> 150 #include <machine/bat.h> 151 #include <machine/pte.h> 152 #include <machine/sr.h> 153 #include <machine/trap.h> 154 #include <machine/mmuvar.h> 155 156 #include "mmu_if.h" 157 158 #define MOEA_DEBUG 159 160 #define TODO panic("%s: not implemented", __func__); 161 162 static __inline u_int32_t 163 cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167 } 168 169 static __inline uint64_t 170 va_to_vsid(pmap_t pm, vm_offset_t va) 171 { 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173 } 174 175 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 176 #define SYNC() __asm __volatile("sync"); 177 #define EIEIO() __asm __volatile("eieio"); 178 179 /* 180 * The tlbie instruction must be executed in 64-bit mode 181 * so we have to twiddle MSR[SF] around every invocation. 182 * Just to add to the fun, exceptions must be off as well 183 * so that we can't trap in 64-bit mode. What a pain. 184 */ 185 struct mtx tlbie_mutex; 186 187 static __inline void 188 TLBIE(pmap_t pmap, vm_offset_t va) { 189 uint64_t vpn; 190 register_t vpn_hi, vpn_lo; 191 register_t msr; 192 register_t scratch; 193 194 vpn = (uint64_t)(va & ADDR_PIDX); 195 if (pmap != NULL) 196 vpn |= (va_to_vsid(pmap,va) << 28); 197 198 vpn_hi = (uint32_t)(vpn >> 32); 199 vpn_lo = (uint32_t)vpn; 200 201 mtx_lock_spin(&tlbie_mutex); 202 __asm __volatile("\ 203 mfmsr %0; \ 204 clrldi %1,%0,49; \ 205 mtmsr %1; \ 206 insrdi %1,%5,1,0; \ 207 mtmsrd %1; \ 208 ptesync; \ 209 \ 210 sld %1,%2,%4; \ 211 or %1,%1,%3; \ 212 tlbie %1; \ 213 \ 214 mtmsrd %0; \ 215 eieio; \ 216 tlbsync; \ 217 ptesync;" 218 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1)); 219 mtx_unlock_spin(&tlbie_mutex); 220 } 221 222 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 223 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 224 225 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 226 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 227 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 228 229 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 230 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 231 #define PVO_WIRED 0x010 /* PVO entry is wired */ 232 #define PVO_MANAGED 0x020 /* PVO entry is managed */ 233 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 234 bootstrap */ 235 #define PVO_FAKE 0x100 /* fictitious phys page */ 236 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 237 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 238 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 239 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 240 #define PVO_PTEGIDX_CLR(pvo) \ 241 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 242 #define PVO_PTEGIDX_SET(pvo, i) \ 243 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 244 245 #define MOEA_PVO_CHECK(pvo) 246 247 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 248 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 249 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 250 251 struct ofw_map { 252 vm_offset_t om_va; 253 vm_size_t om_len; 254 vm_offset_t om_pa_hi; 255 vm_offset_t om_pa_lo; 256 u_int om_mode; 257 }; 258 259 /* 260 * Map of physical memory regions. 261 */ 262 static struct mem_region *regions; 263 static struct mem_region *pregions; 264 extern u_int phys_avail_count; 265 extern int regions_sz, pregions_sz; 266 extern int ofw_real_mode; 267 268 extern struct pmap ofw_pmap; 269 270 extern void bs_remap_earlyboot(void); 271 272 273 /* 274 * Lock for the pteg and pvo tables. 275 */ 276 struct mtx moea64_table_mutex; 277 278 /* 279 * PTEG data. 280 */ 281 static struct lpteg *moea64_pteg_table; 282 u_int moea64_pteg_count; 283 u_int moea64_pteg_mask; 284 285 /* 286 * PVO data. 287 */ 288 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 289 /* lists of unmanaged pages */ 290 struct pvo_head moea64_pvo_kunmanaged = 291 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 292 struct pvo_head moea64_pvo_unmanaged = 293 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 294 295 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 296 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 297 298 vm_offset_t pvo_allocator_start; 299 vm_offset_t pvo_allocator_end; 300 301 #define BPVO_POOL_SIZE 327680 302 static struct pvo_entry *moea64_bpvo_pool; 303 static int moea64_bpvo_pool_index = 0; 304 305 #define VSID_NBPW (sizeof(u_int32_t) * 8) 306 static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 307 308 static boolean_t moea64_initialized = FALSE; 309 310 /* 311 * Statistics. 312 */ 313 u_int moea64_pte_valid = 0; 314 u_int moea64_pte_overflow = 0; 315 u_int moea64_pvo_entries = 0; 316 u_int moea64_pvo_enter_calls = 0; 317 u_int moea64_pvo_remove_calls = 0; 318 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 319 &moea64_pte_valid, 0, ""); 320 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 321 &moea64_pte_overflow, 0, ""); 322 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 323 &moea64_pvo_entries, 0, ""); 324 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 325 &moea64_pvo_enter_calls, 0, ""); 326 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 327 &moea64_pvo_remove_calls, 0, ""); 328 329 vm_offset_t moea64_scratchpage_va[2]; 330 struct pvo_entry *moea64_scratchpage_pvo[2]; 331 struct lpte *moea64_scratchpage_pte[2]; 332 struct mtx moea64_scratchpage_mtx; 333 334 /* 335 * Allocate physical memory for use in moea64_bootstrap. 336 */ 337 static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 338 339 /* 340 * PTE calls. 341 */ 342 static int moea64_pte_insert(u_int, struct lpte *); 343 344 /* 345 * PVO calls. 346 */ 347 static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 348 vm_offset_t, vm_offset_t, uint64_t, int); 349 static void moea64_pvo_remove(struct pvo_entry *, int); 350 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 351 static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 352 353 /* 354 * Utility routines. 355 */ 356 static void moea64_bridge_bootstrap(mmu_t mmup, 357 vm_offset_t kernelstart, vm_offset_t kernelend); 358 static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 359 static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 360 vm_prot_t, boolean_t); 361 static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 362 static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *); 363 static void moea64_kremove(mmu_t, vm_offset_t); 364 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 365 vm_offset_t pa, vm_size_t sz); 366 static void tlbia(void); 367 368 /* 369 * Kernel MMU interface 370 */ 371 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 372 void moea64_clear_modify(mmu_t, vm_page_t); 373 void moea64_clear_reference(mmu_t, vm_page_t); 374 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 375 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 376 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 377 vm_prot_t); 378 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 379 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 380 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 381 void moea64_init(mmu_t); 382 boolean_t moea64_is_modified(mmu_t, vm_page_t); 383 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 384 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 385 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 386 int moea64_page_wired_mappings(mmu_t, vm_page_t); 387 void moea64_pinit(mmu_t, pmap_t); 388 void moea64_pinit0(mmu_t, pmap_t); 389 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 390 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 391 void moea64_qremove(mmu_t, vm_offset_t, int); 392 void moea64_release(mmu_t, pmap_t); 393 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 394 void moea64_remove_all(mmu_t, vm_page_t); 395 void moea64_remove_write(mmu_t, vm_page_t); 396 void moea64_zero_page(mmu_t, vm_page_t); 397 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 398 void moea64_zero_page_idle(mmu_t, vm_page_t); 399 void moea64_activate(mmu_t, struct thread *); 400 void moea64_deactivate(mmu_t, struct thread *); 401 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 402 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 403 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 404 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 405 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 406 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 407 408 static mmu_method_t moea64_bridge_methods[] = { 409 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 410 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 411 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 412 MMUMETHOD(mmu_copy_page, moea64_copy_page), 413 MMUMETHOD(mmu_enter, moea64_enter), 414 MMUMETHOD(mmu_enter_object, moea64_enter_object), 415 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 416 MMUMETHOD(mmu_extract, moea64_extract), 417 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 418 MMUMETHOD(mmu_init, moea64_init), 419 MMUMETHOD(mmu_is_modified, moea64_is_modified), 420 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 421 MMUMETHOD(mmu_map, moea64_map), 422 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 423 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 424 MMUMETHOD(mmu_pinit, moea64_pinit), 425 MMUMETHOD(mmu_pinit0, moea64_pinit0), 426 MMUMETHOD(mmu_protect, moea64_protect), 427 MMUMETHOD(mmu_qenter, moea64_qenter), 428 MMUMETHOD(mmu_qremove, moea64_qremove), 429 MMUMETHOD(mmu_release, moea64_release), 430 MMUMETHOD(mmu_remove, moea64_remove), 431 MMUMETHOD(mmu_remove_all, moea64_remove_all), 432 MMUMETHOD(mmu_remove_write, moea64_remove_write), 433 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 434 MMUMETHOD(mmu_zero_page, moea64_zero_page), 435 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 436 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 437 MMUMETHOD(mmu_activate, moea64_activate), 438 MMUMETHOD(mmu_deactivate, moea64_deactivate), 439 440 /* Internal interfaces */ 441 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 442 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 443 MMUMETHOD(mmu_mapdev, moea64_mapdev), 444 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 445 MMUMETHOD(mmu_kextract, moea64_kextract), 446 MMUMETHOD(mmu_kenter, moea64_kenter), 447 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 448 449 { 0, 0 } 450 }; 451 452 static mmu_def_t oea64_bridge_mmu = { 453 MMU_TYPE_G5, 454 moea64_bridge_methods, 455 0 456 }; 457 MMU_DEF(oea64_bridge_mmu); 458 459 static __inline u_int 460 va_to_pteg(uint64_t vsid, vm_offset_t addr) 461 { 462 u_int hash; 463 464 hash = vsid ^ (((uint64_t)addr & ADDR_PIDX) >> 465 ADDR_PIDX_SHFT); 466 return (hash & moea64_pteg_mask); 467 } 468 469 static __inline struct pvo_head * 470 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 471 { 472 struct vm_page *pg; 473 474 pg = PHYS_TO_VM_PAGE(pa); 475 476 if (pg_p != NULL) 477 *pg_p = pg; 478 479 if (pg == NULL) 480 return (&moea64_pvo_unmanaged); 481 482 return (&pg->md.mdpg_pvoh); 483 } 484 485 static __inline struct pvo_head * 486 vm_page_to_pvoh(vm_page_t m) 487 { 488 489 return (&m->md.mdpg_pvoh); 490 } 491 492 static __inline void 493 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 494 { 495 496 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 497 m->md.mdpg_attrs &= ~ptebit; 498 } 499 500 static __inline u_int64_t 501 moea64_attr_fetch(vm_page_t m) 502 { 503 504 return (m->md.mdpg_attrs); 505 } 506 507 static __inline void 508 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 509 { 510 511 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 512 m->md.mdpg_attrs |= ptebit; 513 } 514 515 static __inline int 516 moea64_pte_compare(const struct lpte *pt, const struct lpte *pvo_pt) 517 { 518 if (pt->pte_hi == pvo_pt->pte_hi) 519 return (1); 520 521 return (0); 522 } 523 524 static __inline int 525 moea64_pte_match(struct lpte *pt, uint64_t vsid, vm_offset_t va, int which) 526 { 527 return (pt->pte_hi & ~LPTE_VALID) == 528 ((vsid << LPTE_VSID_SHIFT) | 529 ((uint64_t)(va >> ADDR_API_SHFT64) & LPTE_API) | which); 530 } 531 532 static __inline void 533 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 534 uint64_t pte_lo) 535 { 536 ASSERT_TABLE_LOCK(); 537 538 /* 539 * Construct a PTE. Default to IMB initially. Valid bit only gets 540 * set when the real pte is set in memory. 541 * 542 * Note: Don't set the valid bit for correct operation of tlb update. 543 */ 544 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 545 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 546 547 pt->pte_lo = pte_lo; 548 } 549 550 static __inline void 551 moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 552 { 553 554 ASSERT_TABLE_LOCK(); 555 556 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 557 } 558 559 static __inline void 560 moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 561 { 562 ASSERT_TABLE_LOCK(); 563 564 /* 565 * As shown in Section 7.6.3.2.3 566 */ 567 pt->pte_lo &= ~ptebit; 568 TLBIE(pmap,va); 569 } 570 571 static __inline void 572 moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 573 { 574 575 ASSERT_TABLE_LOCK(); 576 pvo_pt->pte_hi |= LPTE_VALID; 577 578 /* 579 * Update the PTE as defined in section 7.6.3.1. 580 * Note that the REF/CHG bits are from pvo_pt and thus should have 581 * been saved so this routine can restore them (if desired). 582 */ 583 pt->pte_lo = pvo_pt->pte_lo; 584 EIEIO(); 585 pt->pte_hi = pvo_pt->pte_hi; 586 SYNC(); 587 moea64_pte_valid++; 588 } 589 590 static __inline void 591 moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 592 { 593 ASSERT_TABLE_LOCK(); 594 pvo_pt->pte_hi &= ~LPTE_VALID; 595 596 /* 597 * Force the reg & chg bits back into the PTEs. 598 */ 599 SYNC(); 600 601 /* 602 * Invalidate the pte. 603 */ 604 pt->pte_hi &= ~LPTE_VALID; 605 606 TLBIE(pmap,va); 607 608 /* 609 * Save the reg & chg bits. 610 */ 611 moea64_pte_synch(pt, pvo_pt); 612 moea64_pte_valid--; 613 } 614 615 static __inline void 616 moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 617 { 618 619 /* 620 * Invalidate the PTE 621 */ 622 moea64_pte_unset(pt, pvo_pt, pmap, va); 623 moea64_pte_set(pt, pvo_pt); 624 } 625 626 static __inline uint64_t 627 moea64_calc_wimg(vm_offset_t pa) 628 { 629 uint64_t pte_lo; 630 int i; 631 632 /* 633 * Assume the page is cache inhibited and access is guarded unless 634 * it's in our available memory array. 635 */ 636 pte_lo = LPTE_I | LPTE_G; 637 for (i = 0; i < pregions_sz; i++) { 638 if ((pa >= pregions[i].mr_start) && 639 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 640 pte_lo &= ~(LPTE_I | LPTE_G); 641 pte_lo |= LPTE_M; 642 break; 643 } 644 } 645 646 return pte_lo; 647 } 648 649 /* 650 * Quick sort callout for comparing memory regions. 651 */ 652 static int mr_cmp(const void *a, const void *b); 653 static int om_cmp(const void *a, const void *b); 654 655 static int 656 mr_cmp(const void *a, const void *b) 657 { 658 const struct mem_region *regiona; 659 const struct mem_region *regionb; 660 661 regiona = a; 662 regionb = b; 663 if (regiona->mr_start < regionb->mr_start) 664 return (-1); 665 else if (regiona->mr_start > regionb->mr_start) 666 return (1); 667 else 668 return (0); 669 } 670 671 static int 672 om_cmp(const void *a, const void *b) 673 { 674 const struct ofw_map *mapa; 675 const struct ofw_map *mapb; 676 677 mapa = a; 678 mapb = b; 679 if (mapa->om_pa_hi < mapb->om_pa_hi) 680 return (-1); 681 else if (mapa->om_pa_hi > mapb->om_pa_hi) 682 return (1); 683 else if (mapa->om_pa_lo < mapb->om_pa_lo) 684 return (-1); 685 else if (mapa->om_pa_lo > mapb->om_pa_lo) 686 return (1); 687 else 688 return (0); 689 } 690 691 static void 692 moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 693 { 694 int i = 0; 695 696 /* 697 * Initialize segment registers and MMU 698 */ 699 700 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 701 for (i = 0; i < 16; i++) { 702 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 703 } 704 __asm __volatile ("sync; mtsdr1 %0; isync" 705 :: "r"((u_int)moea64_pteg_table 706 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 707 tlbia(); 708 } 709 710 static void 711 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 712 { 713 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 714 register_t msr; 715 vm_offset_t off; 716 int i, ofw_mappings; 717 718 bzero(translations, sz); 719 if (OF_getprop(mmu, "translations", translations, sz) == -1) 720 panic("moea64_bootstrap: can't get ofw translations"); 721 722 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 723 sz /= sizeof(*translations); 724 qsort(translations, sz, sizeof (*translations), om_cmp); 725 726 for (i = 0, ofw_mappings = 0; i < sz; i++) { 727 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 728 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 729 translations[i].om_len); 730 731 if (translations[i].om_pa_lo % PAGE_SIZE) 732 panic("OFW translation not page-aligned!"); 733 734 if (translations[i].om_pa_hi) 735 panic("OFW translations above 32-bit boundary!"); 736 737 /* Now enter the pages for this mapping */ 738 739 /* 740 * Lock the ofw pmap. pmap_kenter(), which we use for the 741 * pages the kernel also needs, does its own locking. 742 */ 743 PMAP_LOCK(&ofw_pmap); 744 DISABLE_TRANS(msr); 745 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 746 struct vm_page m; 747 748 /* Map low memory mappings into the kernel pmap, too. 749 * These are typically mappings made by the loader, 750 * so we need them if we want to keep executing. */ 751 752 if (translations[i].om_va + off < SEGMENT_LENGTH) 753 moea64_kenter(mmup, translations[i].om_va + off, 754 translations[i].om_va + off); 755 756 m.phys_addr = translations[i].om_pa_lo + off; 757 moea64_enter_locked(&ofw_pmap, 758 translations[i].om_va + off, &m, VM_PROT_ALL, 1); 759 760 ofw_mappings++; 761 } 762 ENABLE_TRANS(msr); 763 PMAP_UNLOCK(&ofw_pmap); 764 } 765 } 766 767 static void 768 moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 769 { 770 ihandle_t mmui; 771 phandle_t chosen; 772 phandle_t mmu; 773 size_t sz; 774 int i, j; 775 vm_size_t size, physsz, hwphyssz; 776 vm_offset_t pa, va, off; 777 register_t msr; 778 void *dpcpu; 779 780 /* We don't have a direct map since there is no BAT */ 781 hw_direct_map = 0; 782 783 /* Make sure battable is zero, since we have no BAT */ 784 for (i = 0; i < 16; i++) { 785 battable[i].batu = 0; 786 battable[i].batl = 0; 787 } 788 789 /* Get physical memory regions from firmware */ 790 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 791 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 792 793 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 794 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 795 panic("moea64_bootstrap: phys_avail too small"); 796 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 797 phys_avail_count = 0; 798 physsz = 0; 799 hwphyssz = 0; 800 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 801 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 802 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 803 regions[i].mr_start + regions[i].mr_size, 804 regions[i].mr_size); 805 if (hwphyssz != 0 && 806 (physsz + regions[i].mr_size) >= hwphyssz) { 807 if (physsz < hwphyssz) { 808 phys_avail[j] = regions[i].mr_start; 809 phys_avail[j + 1] = regions[i].mr_start + 810 hwphyssz - physsz; 811 physsz = hwphyssz; 812 phys_avail_count++; 813 } 814 break; 815 } 816 phys_avail[j] = regions[i].mr_start; 817 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 818 phys_avail_count++; 819 physsz += regions[i].mr_size; 820 } 821 physmem = btoc(physsz); 822 823 /* 824 * Allocate PTEG table. 825 */ 826 #ifdef PTEGCOUNT 827 moea64_pteg_count = PTEGCOUNT; 828 #else 829 moea64_pteg_count = 0x1000; 830 831 while (moea64_pteg_count < physmem) 832 moea64_pteg_count <<= 1; 833 #endif /* PTEGCOUNT */ 834 835 size = moea64_pteg_count * sizeof(struct lpteg); 836 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 837 moea64_pteg_count, size); 838 839 /* 840 * We now need to allocate memory. This memory, to be allocated, 841 * has to reside in a page table. The page table we are about to 842 * allocate. We don't have BAT. So drop to data real mode for a minute 843 * as a measure of last resort. We do this a couple times. 844 */ 845 846 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 847 DISABLE_TRANS(msr); 848 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 849 ENABLE_TRANS(msr); 850 851 moea64_pteg_mask = moea64_pteg_count - 1; 852 853 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 854 855 /* 856 * Allocate pv/overflow lists. 857 */ 858 size = sizeof(struct pvo_head) * moea64_pteg_count; 859 860 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 861 PAGE_SIZE); 862 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 863 864 DISABLE_TRANS(msr); 865 for (i = 0; i < moea64_pteg_count; i++) 866 LIST_INIT(&moea64_pvo_table[i]); 867 ENABLE_TRANS(msr); 868 869 /* 870 * Initialize the lock that synchronizes access to the pteg and pvo 871 * tables. 872 */ 873 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 874 MTX_RECURSE); 875 876 /* 877 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 878 */ 879 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 880 881 /* 882 * Initialise the unmanaged pvo pool. 883 */ 884 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 885 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 886 moea64_bpvo_pool_index = 0; 887 888 /* 889 * Make sure kernel vsid is allocated as well as VSID 0. 890 */ 891 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 892 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 893 moea64_vsid_bitmap[0] |= 1; 894 895 /* 896 * Initialize the kernel pmap (which is statically allocated). 897 */ 898 for (i = 0; i < 16; i++) 899 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 900 901 kernel_pmap->pmap_phys = kernel_pmap; 902 kernel_pmap->pm_active = ~0; 903 904 PMAP_LOCK_INIT(kernel_pmap); 905 906 /* 907 * Now map in all the other buffers we allocated earlier 908 */ 909 910 DISABLE_TRANS(msr); 911 size = moea64_pteg_count * sizeof(struct lpteg); 912 off = (vm_offset_t)(moea64_pteg_table); 913 for (pa = off; pa < off + size; pa += PAGE_SIZE) 914 moea64_kenter(mmup, pa, pa); 915 size = sizeof(struct pvo_head) * moea64_pteg_count; 916 off = (vm_offset_t)(moea64_pvo_table); 917 for (pa = off; pa < off + size; pa += PAGE_SIZE) 918 moea64_kenter(mmup, pa, pa); 919 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 920 off = (vm_offset_t)(moea64_bpvo_pool); 921 for (pa = off; pa < off + size; pa += PAGE_SIZE) 922 moea64_kenter(mmup, pa, pa); 923 924 /* 925 * Map certain important things, like ourselves. 926 * 927 * NOTE: We do not map the exception vector space. That code is 928 * used only in real mode, and leaving it unmapped allows us to 929 * catch NULL pointer deferences, instead of making NULL a valid 930 * address. 931 */ 932 933 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 934 moea64_kenter(mmup, pa, pa); 935 ENABLE_TRANS(msr); 936 937 if (!ofw_real_mode) { 938 /* 939 * Set up the Open Firmware pmap and add its mappings. 940 */ 941 942 moea64_pinit(mmup, &ofw_pmap); 943 ofw_pmap.pm_sr[KERNEL_SR] = kernel_pmap->pm_sr[KERNEL_SR]; 944 ofw_pmap.pm_sr[KERNEL2_SR] = kernel_pmap->pm_sr[KERNEL2_SR]; 945 946 if ((chosen = OF_finddevice("/chosen")) == -1) 947 panic("moea64_bootstrap: can't find /chosen"); 948 OF_getprop(chosen, "mmu", &mmui, 4); 949 if ((mmu = OF_instance_to_package(mmui)) == -1) 950 panic("moea64_bootstrap: can't get mmu package"); 951 if ((sz = OF_getproplen(mmu, "translations")) == -1) 952 panic("moea64_bootstrap: can't get ofw translation count"); 953 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 954 panic("moea64_bootstrap: too many ofw translations"); 955 956 moea64_add_ofw_mappings(mmup, mmu, sz); 957 } 958 959 #ifdef SMP 960 TLBSYNC(); 961 #endif 962 963 /* 964 * Calculate the last available physical address. 965 */ 966 for (i = 0; phys_avail[i + 2] != 0; i += 2) 967 ; 968 Maxmem = powerpc_btop(phys_avail[i + 1]); 969 970 /* 971 * Initialize MMU and remap early physical mappings 972 */ 973 moea64_bridge_cpu_bootstrap(mmup,0); 974 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 975 pmap_bootstrapped++; 976 bs_remap_earlyboot(); 977 978 /* 979 * Set the start and end of kva. 980 */ 981 virtual_avail = VM_MIN_KERNEL_ADDRESS; 982 virtual_end = VM_MAX_KERNEL_ADDRESS; 983 984 /* 985 * Allocate some stupid buffer regions. 986 */ 987 988 pvo_allocator_start = virtual_avail; 989 virtual_avail += SEGMENT_LENGTH/4; 990 pvo_allocator_end = virtual_avail; 991 992 /* 993 * Allocate some things for page zeroing 994 */ 995 996 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 997 for (i = 0; i < 2; i++) { 998 moea64_scratchpage_va[i] = virtual_avail; 999 virtual_avail += PAGE_SIZE; 1000 1001 moea64_kenter(mmup,moea64_scratchpage_va[i],kernelstart); 1002 1003 LOCK_TABLE(); 1004 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(kernel_pmap, 1005 moea64_scratchpage_va[i],&j); 1006 moea64_scratchpage_pte[i] = moea64_pvo_to_pte( 1007 moea64_scratchpage_pvo[i],j); 1008 UNLOCK_TABLE(); 1009 } 1010 1011 /* 1012 * Allocate a kernel stack with a guard page for thread0 and map it 1013 * into the kernel page map. 1014 */ 1015 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1016 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1017 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1018 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1019 thread0.td_kstack = va; 1020 thread0.td_kstack_pages = KSTACK_PAGES; 1021 for (i = 0; i < KSTACK_PAGES; i++) { 1022 moea64_kenter(mmup, va, pa);; 1023 pa += PAGE_SIZE; 1024 va += PAGE_SIZE; 1025 } 1026 1027 /* 1028 * Allocate virtual address space for the message buffer. 1029 */ 1030 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1031 msgbufp = (struct msgbuf *)virtual_avail; 1032 va = virtual_avail; 1033 virtual_avail += round_page(MSGBUF_SIZE); 1034 while (va < virtual_avail) { 1035 moea64_kenter(mmup, va, pa);; 1036 pa += PAGE_SIZE; 1037 va += PAGE_SIZE; 1038 } 1039 1040 /* 1041 * Allocate virtual address space for the dynamic percpu area. 1042 */ 1043 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1044 dpcpu = (void *)virtual_avail; 1045 va = virtual_avail; 1046 virtual_avail += DPCPU_SIZE; 1047 while (va < virtual_avail) { 1048 moea64_kenter(mmup, va, pa);; 1049 pa += PAGE_SIZE; 1050 va += PAGE_SIZE; 1051 } 1052 dpcpu_init(dpcpu, 0); 1053 } 1054 1055 /* 1056 * Activate a user pmap. The pmap must be activated before it's address 1057 * space can be accessed in any way. 1058 */ 1059 void 1060 moea64_activate(mmu_t mmu, struct thread *td) 1061 { 1062 pmap_t pm, pmr; 1063 1064 /* 1065 * Load all the data we need up front to encourage the compiler to 1066 * not issue any loads while we have interrupts disabled below. 1067 */ 1068 pm = &td->td_proc->p_vmspace->vm_pmap; 1069 pmr = pm->pmap_phys; 1070 1071 pm->pm_active |= PCPU_GET(cpumask); 1072 PCPU_SET(curpmap, pmr); 1073 } 1074 1075 void 1076 moea64_deactivate(mmu_t mmu, struct thread *td) 1077 { 1078 pmap_t pm; 1079 1080 pm = &td->td_proc->p_vmspace->vm_pmap; 1081 pm->pm_active &= ~(PCPU_GET(cpumask)); 1082 PCPU_SET(curpmap, NULL); 1083 } 1084 1085 void 1086 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1087 { 1088 struct pvo_entry *pvo; 1089 1090 PMAP_LOCK(pm); 1091 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1092 1093 if (pvo != NULL) { 1094 if (wired) { 1095 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1096 pm->pm_stats.wired_count++; 1097 pvo->pvo_vaddr |= PVO_WIRED; 1098 } else { 1099 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1100 pm->pm_stats.wired_count--; 1101 pvo->pvo_vaddr &= ~PVO_WIRED; 1102 } 1103 } 1104 PMAP_UNLOCK(pm); 1105 } 1106 1107 /* 1108 * Zero a page of physical memory by temporarily mapping it into the tlb. 1109 */ 1110 void 1111 moea64_zero_page(mmu_t mmu, vm_page_t m) 1112 { 1113 moea64_zero_page_area(mmu,m,0,PAGE_SIZE); 1114 } 1115 1116 /* 1117 * This goes through and sets the physical address of our 1118 * special scratch PTE to the PA we want to zero or copy. Because 1119 * of locking issues (this can get called in pvo_enter() by 1120 * the UMA allocator), we can't use most other utility functions here 1121 */ 1122 1123 static __inline 1124 void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1125 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1126 (~LPTE_WIMG & ~LPTE_RPGN); 1127 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1128 moea64_calc_wimg(pa) | (uint64_t)pa; 1129 1130 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1131 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1132 1133 moea64_scratchpage_pte[which]->pte_lo = 1134 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo; 1135 EIEIO(); 1136 1137 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1138 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1139 } 1140 1141 void 1142 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1143 { 1144 vm_offset_t dst; 1145 vm_offset_t src; 1146 1147 dst = VM_PAGE_TO_PHYS(mdst); 1148 src = VM_PAGE_TO_PHYS(msrc); 1149 1150 mtx_lock(&moea64_scratchpage_mtx); 1151 1152 moea64_set_scratchpage_pa(0,src); 1153 moea64_set_scratchpage_pa(1,dst); 1154 1155 kcopy((void *)moea64_scratchpage_va[0], 1156 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1157 1158 __syncicache((void *)moea64_scratchpage_va[1],PAGE_SIZE); 1159 1160 mtx_unlock(&moea64_scratchpage_mtx); 1161 } 1162 1163 void 1164 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1165 { 1166 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1167 1168 if (!moea64_initialized) 1169 panic("moea64_zero_page: can't zero pa %#x", pa); 1170 if (size + off > PAGE_SIZE) 1171 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1172 1173 mtx_lock(&moea64_scratchpage_mtx); 1174 1175 moea64_set_scratchpage_pa(0,pa); 1176 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1177 __syncicache((void *)moea64_scratchpage_va[0],PAGE_SIZE); 1178 1179 mtx_unlock(&moea64_scratchpage_mtx); 1180 } 1181 1182 void 1183 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1184 { 1185 1186 moea64_zero_page(mmu, m); 1187 } 1188 1189 /* 1190 * Map the given physical page at the specified virtual address in the 1191 * target pmap with the protection requested. If specified the page 1192 * will be wired down. 1193 */ 1194 void 1195 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1196 vm_prot_t prot, boolean_t wired) 1197 { 1198 1199 vm_page_lock_queues(); 1200 PMAP_LOCK(pmap); 1201 moea64_enter_locked(pmap, va, m, prot, wired); 1202 vm_page_unlock_queues(); 1203 PMAP_UNLOCK(pmap); 1204 } 1205 1206 /* 1207 * Map the given physical page at the specified virtual address in the 1208 * target pmap with the protection requested. If specified the page 1209 * will be wired down. 1210 * 1211 * The page queues and pmap must be locked. 1212 */ 1213 1214 static void 1215 moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1216 boolean_t wired) 1217 { 1218 struct pvo_head *pvo_head; 1219 uma_zone_t zone; 1220 vm_page_t pg; 1221 uint64_t pte_lo; 1222 u_int pvo_flags; 1223 int error; 1224 1225 if (!moea64_initialized) { 1226 pvo_head = &moea64_pvo_kunmanaged; 1227 pg = NULL; 1228 zone = moea64_upvo_zone; 1229 pvo_flags = 0; 1230 } else { 1231 pvo_head = vm_page_to_pvoh(m); 1232 pg = m; 1233 zone = moea64_mpvo_zone; 1234 pvo_flags = PVO_MANAGED; 1235 } 1236 1237 if (pmap_bootstrapped) 1238 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1239 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1240 1241 /* XXX change the pvo head for fake pages */ 1242 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1243 pvo_flags &= ~PVO_MANAGED; 1244 pvo_head = &moea64_pvo_kunmanaged; 1245 zone = moea64_upvo_zone; 1246 } 1247 1248 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1249 1250 if (prot & VM_PROT_WRITE) { 1251 pte_lo |= LPTE_BW; 1252 if (pmap_bootstrapped) 1253 vm_page_flag_set(m, PG_WRITEABLE); 1254 } else 1255 pte_lo |= LPTE_BR; 1256 1257 if (prot & VM_PROT_EXECUTE) 1258 pvo_flags |= VM_PROT_EXECUTE; 1259 1260 if (wired) 1261 pvo_flags |= PVO_WIRED; 1262 1263 if ((m->flags & PG_FICTITIOUS) != 0) 1264 pvo_flags |= PVO_FAKE; 1265 1266 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1267 pte_lo, pvo_flags); 1268 1269 if (pmap == kernel_pmap) 1270 TLBIE(pmap, va); 1271 1272 /* 1273 * Flush the page from the instruction cache if this page is 1274 * mapped executable and cacheable. 1275 */ 1276 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1277 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1278 } 1279 } 1280 1281 static void 1282 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1283 { 1284 /* 1285 * This is much trickier than on older systems because 1286 * we can't sync the icache on physical addresses directly 1287 * without a direct map. Instead we check a couple of cases 1288 * where the memory is already mapped in and, failing that, 1289 * use the same trick we use for page zeroing to create 1290 * a temporary mapping for this physical address. 1291 */ 1292 1293 if (!pmap_bootstrapped) { 1294 /* 1295 * If PMAP is not bootstrapped, we are likely to be 1296 * in real mode. 1297 */ 1298 __syncicache((void *)pa, sz); 1299 } else if (pmap == kernel_pmap) { 1300 __syncicache((void *)va, sz); 1301 } else { 1302 /* Use the scratch page to set up a temp mapping */ 1303 1304 mtx_lock(&moea64_scratchpage_mtx); 1305 1306 moea64_set_scratchpage_pa(1,pa); 1307 __syncicache((void *)moea64_scratchpage_va[1], sz); 1308 1309 mtx_unlock(&moea64_scratchpage_mtx); 1310 } 1311 } 1312 1313 /* 1314 * Maps a sequence of resident pages belonging to the same object. 1315 * The sequence begins with the given page m_start. This page is 1316 * mapped at the given virtual address start. Each subsequent page is 1317 * mapped at a virtual address that is offset from start by the same 1318 * amount as the page is offset from m_start within the object. The 1319 * last page in the sequence is the page with the largest offset from 1320 * m_start that can be mapped at a virtual address less than the given 1321 * virtual address end. Not every virtual page between start and end 1322 * is mapped; only those for which a resident page exists with the 1323 * corresponding offset from m_start are mapped. 1324 */ 1325 void 1326 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1327 vm_page_t m_start, vm_prot_t prot) 1328 { 1329 vm_page_t m; 1330 vm_pindex_t diff, psize; 1331 1332 psize = atop(end - start); 1333 m = m_start; 1334 PMAP_LOCK(pm); 1335 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1336 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1337 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1338 m = TAILQ_NEXT(m, listq); 1339 } 1340 PMAP_UNLOCK(pm); 1341 } 1342 1343 void 1344 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1345 vm_prot_t prot) 1346 { 1347 PMAP_LOCK(pm); 1348 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1349 FALSE); 1350 PMAP_UNLOCK(pm); 1351 1352 } 1353 1354 vm_paddr_t 1355 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1356 { 1357 struct pvo_entry *pvo; 1358 vm_paddr_t pa; 1359 1360 PMAP_LOCK(pm); 1361 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1362 if (pvo == NULL) 1363 pa = 0; 1364 else 1365 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1366 PMAP_UNLOCK(pm); 1367 return (pa); 1368 } 1369 1370 /* 1371 * Atomically extract and hold the physical page with the given 1372 * pmap and virtual address pair if that mapping permits the given 1373 * protection. 1374 */ 1375 vm_page_t 1376 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1377 { 1378 struct pvo_entry *pvo; 1379 vm_page_t m; 1380 1381 m = NULL; 1382 vm_page_lock_queues(); 1383 PMAP_LOCK(pmap); 1384 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1385 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1386 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1387 (prot & VM_PROT_WRITE) == 0)) { 1388 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1389 vm_page_hold(m); 1390 } 1391 vm_page_unlock_queues(); 1392 PMAP_UNLOCK(pmap); 1393 return (m); 1394 } 1395 1396 static void * 1397 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1398 { 1399 /* 1400 * This entire routine is a horrible hack to avoid bothering kmem 1401 * for new KVA addresses. Because this can get called from inside 1402 * kmem allocation routines, calling kmem for a new address here 1403 * can lead to multiply locking non-recursive mutexes. 1404 */ 1405 static vm_pindex_t color; 1406 vm_offset_t va; 1407 1408 vm_page_t m; 1409 int pflags, needed_lock; 1410 1411 *flags = UMA_SLAB_PRIV; 1412 needed_lock = !PMAP_LOCKED(kernel_pmap); 1413 1414 if (needed_lock) 1415 PMAP_LOCK(kernel_pmap); 1416 1417 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1418 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1419 else 1420 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1421 if (wait & M_ZERO) 1422 pflags |= VM_ALLOC_ZERO; 1423 1424 for (;;) { 1425 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1426 if (m == NULL) { 1427 if (wait & M_NOWAIT) 1428 return (NULL); 1429 VM_WAIT; 1430 } else 1431 break; 1432 } 1433 1434 va = pvo_allocator_start; 1435 pvo_allocator_start += PAGE_SIZE; 1436 1437 if (pvo_allocator_start >= pvo_allocator_end) 1438 panic("Ran out of PVO allocator buffer space!"); 1439 1440 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1441 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1442 PVO_WIRED | PVO_BOOTSTRAP); 1443 1444 TLBIE(kernel_pmap, va); 1445 1446 if (needed_lock) 1447 PMAP_UNLOCK(kernel_pmap); 1448 1449 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1450 bzero((void *)va, PAGE_SIZE); 1451 1452 return (void *)va; 1453 } 1454 1455 void 1456 moea64_init(mmu_t mmu) 1457 { 1458 1459 CTR0(KTR_PMAP, "moea64_init"); 1460 1461 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1462 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1463 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1464 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1465 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1466 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1467 1468 if (!hw_direct_map) { 1469 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1470 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1471 } 1472 1473 moea64_initialized = TRUE; 1474 } 1475 1476 boolean_t 1477 moea64_is_modified(mmu_t mmu, vm_page_t m) 1478 { 1479 1480 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1481 return (FALSE); 1482 1483 return (moea64_query_bit(m, LPTE_CHG)); 1484 } 1485 1486 void 1487 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1488 { 1489 1490 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1491 return; 1492 moea64_clear_bit(m, LPTE_REF, NULL); 1493 } 1494 1495 void 1496 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1497 { 1498 1499 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1500 return; 1501 moea64_clear_bit(m, LPTE_CHG, NULL); 1502 } 1503 1504 /* 1505 * Clear the write and modified bits in each of the given page's mappings. 1506 */ 1507 void 1508 moea64_remove_write(mmu_t mmu, vm_page_t m) 1509 { 1510 struct pvo_entry *pvo; 1511 struct lpte *pt; 1512 pmap_t pmap; 1513 uint64_t lo; 1514 1515 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1516 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1517 (m->flags & PG_WRITEABLE) == 0) 1518 return; 1519 lo = moea64_attr_fetch(m); 1520 SYNC(); 1521 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1522 pmap = pvo->pvo_pmap; 1523 PMAP_LOCK(pmap); 1524 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1525 LOCK_TABLE(); 1526 pt = moea64_pvo_to_pte(pvo, -1); 1527 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1528 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1529 if (pt != NULL) { 1530 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1531 lo |= pvo->pvo_pte.lpte.pte_lo; 1532 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1533 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1534 pvo->pvo_pmap, pvo->pvo_vaddr); 1535 } 1536 UNLOCK_TABLE(); 1537 } 1538 PMAP_UNLOCK(pmap); 1539 } 1540 if ((lo & LPTE_CHG) != 0) { 1541 moea64_attr_clear(m, LPTE_CHG); 1542 vm_page_dirty(m); 1543 } 1544 vm_page_flag_clear(m, PG_WRITEABLE); 1545 } 1546 1547 /* 1548 * moea64_ts_referenced: 1549 * 1550 * Return a count of reference bits for a page, clearing those bits. 1551 * It is not necessary for every reference bit to be cleared, but it 1552 * is necessary that 0 only be returned when there are truly no 1553 * reference bits set. 1554 * 1555 * XXX: The exact number of bits to check and clear is a matter that 1556 * should be tested and standardized at some point in the future for 1557 * optimal aging of shared pages. 1558 */ 1559 boolean_t 1560 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1561 { 1562 int count; 1563 1564 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1565 return (0); 1566 1567 count = moea64_clear_bit(m, LPTE_REF, NULL); 1568 1569 return (count); 1570 } 1571 1572 /* 1573 * Map a wired page into kernel virtual address space. 1574 */ 1575 void 1576 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1577 { 1578 uint64_t pte_lo; 1579 int error; 1580 1581 if (!pmap_bootstrapped) { 1582 if (va >= VM_MIN_KERNEL_ADDRESS && va < VM_MAX_KERNEL_ADDRESS) 1583 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1584 } 1585 1586 pte_lo = moea64_calc_wimg(pa); 1587 1588 PMAP_LOCK(kernel_pmap); 1589 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1590 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1591 PVO_WIRED | VM_PROT_EXECUTE); 1592 1593 TLBIE(kernel_pmap, va); 1594 1595 if (error != 0 && error != ENOENT) 1596 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1597 pa, error); 1598 1599 /* 1600 * Flush the memory from the instruction cache. 1601 */ 1602 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1603 __syncicache((void *)va, PAGE_SIZE); 1604 } 1605 PMAP_UNLOCK(kernel_pmap); 1606 } 1607 1608 /* 1609 * Extract the physical page address associated with the given kernel virtual 1610 * address. 1611 */ 1612 vm_offset_t 1613 moea64_kextract(mmu_t mmu, vm_offset_t va) 1614 { 1615 struct pvo_entry *pvo; 1616 vm_paddr_t pa; 1617 1618 PMAP_LOCK(kernel_pmap); 1619 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1620 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1621 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1622 PMAP_UNLOCK(kernel_pmap); 1623 return (pa); 1624 } 1625 1626 /* 1627 * Remove a wired page from kernel virtual address space. 1628 */ 1629 void 1630 moea64_kremove(mmu_t mmu, vm_offset_t va) 1631 { 1632 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1633 } 1634 1635 /* 1636 * Map a range of physical addresses into kernel virtual address space. 1637 * 1638 * The value passed in *virt is a suggested virtual address for the mapping. 1639 * Architectures which can support a direct-mapped physical to virtual region 1640 * can return the appropriate address within that region, leaving '*virt' 1641 * unchanged. We cannot and therefore do not; *virt is updated with the 1642 * first usable address after the mapped region. 1643 */ 1644 vm_offset_t 1645 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1646 vm_offset_t pa_end, int prot) 1647 { 1648 vm_offset_t sva, va; 1649 1650 sva = *virt; 1651 va = sva; 1652 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1653 moea64_kenter(mmu, va, pa_start); 1654 *virt = va; 1655 1656 return (sva); 1657 } 1658 1659 /* 1660 * Returns true if the pmap's pv is one of the first 1661 * 16 pvs linked to from this page. This count may 1662 * be changed upwards or downwards in the future; it 1663 * is only necessary that true be returned for a small 1664 * subset of pmaps for proper page aging. 1665 */ 1666 boolean_t 1667 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1668 { 1669 int loops; 1670 struct pvo_entry *pvo; 1671 1672 if (!moea64_initialized || (m->flags & PG_FICTITIOUS)) 1673 return FALSE; 1674 1675 loops = 0; 1676 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1677 if (pvo->pvo_pmap == pmap) 1678 return (TRUE); 1679 if (++loops >= 16) 1680 break; 1681 } 1682 1683 return (FALSE); 1684 } 1685 1686 /* 1687 * Return the number of managed mappings to the given physical page 1688 * that are wired. 1689 */ 1690 int 1691 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1692 { 1693 struct pvo_entry *pvo; 1694 int count; 1695 1696 count = 0; 1697 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0) 1698 return (count); 1699 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1700 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1701 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1702 count++; 1703 return (count); 1704 } 1705 1706 static u_int moea64_vsidcontext; 1707 1708 void 1709 moea64_pinit(mmu_t mmu, pmap_t pmap) 1710 { 1711 int i, mask; 1712 u_int entropy; 1713 1714 PMAP_LOCK_INIT(pmap); 1715 1716 entropy = 0; 1717 __asm __volatile("mftb %0" : "=r"(entropy)); 1718 1719 if (pmap_bootstrapped) 1720 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1721 else 1722 pmap->pmap_phys = pmap; 1723 1724 /* 1725 * Allocate some segment registers for this pmap. 1726 */ 1727 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1728 u_int hash, n; 1729 1730 /* 1731 * Create a new value by mutiplying by a prime and adding in 1732 * entropy from the timebase register. This is to make the 1733 * VSID more random so that the PT hash function collides 1734 * less often. (Note that the prime casues gcc to do shifts 1735 * instead of a multiply.) 1736 */ 1737 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1738 hash = moea64_vsidcontext & (NPMAPS - 1); 1739 if (hash == 0) /* 0 is special, avoid it */ 1740 continue; 1741 n = hash >> 5; 1742 mask = 1 << (hash & (VSID_NBPW - 1)); 1743 hash = (moea64_vsidcontext & 0xfffff); 1744 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1745 /* anything free in this bucket? */ 1746 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1747 entropy = (moea64_vsidcontext >> 20); 1748 continue; 1749 } 1750 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1751 mask = 1 << i; 1752 hash &= 0xfffff & ~(VSID_NBPW - 1); 1753 hash |= i; 1754 } 1755 moea64_vsid_bitmap[n] |= mask; 1756 for (i = 0; i < 16; i++) { 1757 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1758 } 1759 return; 1760 } 1761 1762 panic("moea64_pinit: out of segments"); 1763 } 1764 1765 /* 1766 * Initialize the pmap associated with process 0. 1767 */ 1768 void 1769 moea64_pinit0(mmu_t mmu, pmap_t pm) 1770 { 1771 moea64_pinit(mmu, pm); 1772 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1773 } 1774 1775 /* 1776 * Set the physical protection on the specified range of this map as requested. 1777 */ 1778 void 1779 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1780 vm_prot_t prot) 1781 { 1782 struct pvo_entry *pvo; 1783 struct lpte *pt; 1784 int pteidx; 1785 1786 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1787 eva, prot); 1788 1789 1790 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1791 ("moea64_protect: non current pmap")); 1792 1793 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1794 moea64_remove(mmu, pm, sva, eva); 1795 return; 1796 } 1797 1798 vm_page_lock_queues(); 1799 PMAP_LOCK(pm); 1800 for (; sva < eva; sva += PAGE_SIZE) { 1801 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1802 if (pvo == NULL) 1803 continue; 1804 1805 /* 1806 * Grab the PTE pointer before we diddle with the cached PTE 1807 * copy. 1808 */ 1809 LOCK_TABLE(); 1810 pt = moea64_pvo_to_pte(pvo, pteidx); 1811 1812 /* 1813 * Change the protection of the page. 1814 */ 1815 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1816 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1817 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1818 if ((prot & VM_PROT_EXECUTE) == 0) 1819 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1820 1821 /* 1822 * If the PVO is in the page table, update that pte as well. 1823 */ 1824 if (pt != NULL) { 1825 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1826 pvo->pvo_pmap, pvo->pvo_vaddr); 1827 if ((pvo->pvo_pte.lpte.pte_lo & 1828 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1829 moea64_syncicache(pm, sva, 1830 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1831 PAGE_SIZE); 1832 } 1833 } 1834 UNLOCK_TABLE(); 1835 } 1836 vm_page_unlock_queues(); 1837 PMAP_UNLOCK(pm); 1838 } 1839 1840 /* 1841 * Map a list of wired pages into kernel virtual address space. This is 1842 * intended for temporary mappings which do not need page modification or 1843 * references recorded. Existing mappings in the region are overwritten. 1844 */ 1845 void 1846 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1847 { 1848 while (count-- > 0) { 1849 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1850 va += PAGE_SIZE; 1851 m++; 1852 } 1853 } 1854 1855 /* 1856 * Remove page mappings from kernel virtual address space. Intended for 1857 * temporary mappings entered by moea64_qenter. 1858 */ 1859 void 1860 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1861 { 1862 while (count-- > 0) { 1863 moea64_kremove(mmu, va); 1864 va += PAGE_SIZE; 1865 } 1866 } 1867 1868 void 1869 moea64_release(mmu_t mmu, pmap_t pmap) 1870 { 1871 int idx, mask; 1872 1873 /* 1874 * Free segment register's VSID 1875 */ 1876 if (pmap->pm_sr[0] == 0) 1877 panic("moea64_release"); 1878 1879 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1880 mask = 1 << (idx % VSID_NBPW); 1881 idx /= VSID_NBPW; 1882 moea64_vsid_bitmap[idx] &= ~mask; 1883 PMAP_LOCK_DESTROY(pmap); 1884 } 1885 1886 /* 1887 * Remove the given range of addresses from the specified map. 1888 */ 1889 void 1890 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1891 { 1892 struct pvo_entry *pvo; 1893 int pteidx; 1894 1895 vm_page_lock_queues(); 1896 PMAP_LOCK(pm); 1897 for (; sva < eva; sva += PAGE_SIZE) { 1898 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1899 if (pvo != NULL) { 1900 moea64_pvo_remove(pvo, pteidx); 1901 } 1902 } 1903 vm_page_unlock_queues(); 1904 PMAP_UNLOCK(pm); 1905 } 1906 1907 /* 1908 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1909 * will reflect changes in pte's back to the vm_page. 1910 */ 1911 void 1912 moea64_remove_all(mmu_t mmu, vm_page_t m) 1913 { 1914 struct pvo_head *pvo_head; 1915 struct pvo_entry *pvo, *next_pvo; 1916 pmap_t pmap; 1917 1918 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1919 1920 pvo_head = vm_page_to_pvoh(m); 1921 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1922 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1923 1924 MOEA_PVO_CHECK(pvo); /* sanity check */ 1925 pmap = pvo->pvo_pmap; 1926 PMAP_LOCK(pmap); 1927 moea64_pvo_remove(pvo, -1); 1928 PMAP_UNLOCK(pmap); 1929 } 1930 vm_page_flag_clear(m, PG_WRITEABLE); 1931 } 1932 1933 /* 1934 * Allocate a physical page of memory directly from the phys_avail map. 1935 * Can only be called from moea64_bootstrap before avail start and end are 1936 * calculated. 1937 */ 1938 static vm_offset_t 1939 moea64_bootstrap_alloc(vm_size_t size, u_int align) 1940 { 1941 vm_offset_t s, e; 1942 int i, j; 1943 1944 size = round_page(size); 1945 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1946 if (align != 0) 1947 s = (phys_avail[i] + align - 1) & ~(align - 1); 1948 else 1949 s = phys_avail[i]; 1950 e = s + size; 1951 1952 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1953 continue; 1954 1955 if (s == phys_avail[i]) { 1956 phys_avail[i] += size; 1957 } else if (e == phys_avail[i + 1]) { 1958 phys_avail[i + 1] -= size; 1959 } else { 1960 for (j = phys_avail_count * 2; j > i; j -= 2) { 1961 phys_avail[j] = phys_avail[j - 2]; 1962 phys_avail[j + 1] = phys_avail[j - 1]; 1963 } 1964 1965 phys_avail[i + 3] = phys_avail[i + 1]; 1966 phys_avail[i + 1] = s; 1967 phys_avail[i + 2] = e; 1968 phys_avail_count++; 1969 } 1970 1971 return (s); 1972 } 1973 panic("moea64_bootstrap_alloc: could not allocate memory"); 1974 } 1975 1976 static void 1977 tlbia(void) 1978 { 1979 vm_offset_t i; 1980 register_t msr, scratch; 1981 1982 for (i = 0; i < 0xFF000; i += 0x00001000) { 1983 __asm __volatile("\ 1984 mfmsr %0; \ 1985 mr %1, %0; \ 1986 insrdi %1,%3,1,0; \ 1987 mtmsrd %1; \ 1988 ptesync; \ 1989 \ 1990 tlbiel %2; \ 1991 \ 1992 mtmsrd %0; \ 1993 eieio; \ 1994 tlbsync; \ 1995 ptesync;" 1996 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 1997 } 1998 } 1999 2000 static int 2001 moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2002 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 2003 { 2004 struct pvo_entry *pvo; 2005 uint64_t vsid; 2006 int first; 2007 u_int ptegidx; 2008 int i; 2009 int bootstrap; 2010 2011 /* 2012 * One nasty thing that can happen here is that the UMA calls to 2013 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2014 * which calls UMA... 2015 * 2016 * We break the loop by detecting recursion and allocating out of 2017 * the bootstrap pool. 2018 */ 2019 2020 moea64_pvo_enter_calls++; 2021 first = 0; 2022 bootstrap = (flags & PVO_BOOTSTRAP); 2023 2024 if (!moea64_initialized) 2025 bootstrap = 1; 2026 2027 /* 2028 * Compute the PTE Group index. 2029 */ 2030 va &= ~ADDR_POFF; 2031 vsid = va_to_vsid(pm, va); 2032 ptegidx = va_to_pteg(vsid, va); 2033 2034 /* 2035 * Remove any existing mapping for this page. Reuse the pvo entry if 2036 * there is a mapping. 2037 */ 2038 LOCK_TABLE(); 2039 2040 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2041 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2042 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2043 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2044 (pte_lo & LPTE_PP)) { 2045 UNLOCK_TABLE(); 2046 return (0); 2047 } 2048 moea64_pvo_remove(pvo, -1); 2049 break; 2050 } 2051 } 2052 2053 /* 2054 * If we aren't overwriting a mapping, try to allocate. 2055 */ 2056 if (bootstrap) { 2057 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2058 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2059 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2060 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2061 } 2062 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2063 moea64_bpvo_pool_index++; 2064 bootstrap = 1; 2065 } else { 2066 /* 2067 * Note: drop the table around the UMA allocation in 2068 * case the UMA allocator needs to manipulate the page 2069 * table. The mapping we are working with is already 2070 * protected by the PMAP lock. 2071 */ 2072 UNLOCK_TABLE(); 2073 pvo = uma_zalloc(zone, M_NOWAIT); 2074 LOCK_TABLE(); 2075 } 2076 2077 if (pvo == NULL) { 2078 UNLOCK_TABLE(); 2079 return (ENOMEM); 2080 } 2081 2082 moea64_pvo_entries++; 2083 pvo->pvo_vaddr = va; 2084 pvo->pvo_pmap = pm; 2085 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2086 pvo->pvo_vaddr &= ~ADDR_POFF; 2087 2088 if (!(flags & VM_PROT_EXECUTE)) 2089 pte_lo |= LPTE_NOEXEC; 2090 if (flags & PVO_WIRED) 2091 pvo->pvo_vaddr |= PVO_WIRED; 2092 if (pvo_head != &moea64_pvo_kunmanaged) 2093 pvo->pvo_vaddr |= PVO_MANAGED; 2094 if (bootstrap) 2095 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2096 if (flags & PVO_FAKE) 2097 pvo->pvo_vaddr |= PVO_FAKE; 2098 2099 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2100 (uint64_t)(pa) | pte_lo); 2101 2102 /* 2103 * Remember if the list was empty and therefore will be the first 2104 * item. 2105 */ 2106 if (LIST_FIRST(pvo_head) == NULL) 2107 first = 1; 2108 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2109 2110 if (pvo->pvo_pte.lpte.pte_lo & PVO_WIRED) 2111 pm->pm_stats.wired_count++; 2112 pm->pm_stats.resident_count++; 2113 2114 /* 2115 * We hope this succeeds but it isn't required. 2116 */ 2117 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2118 if (i >= 0) { 2119 PVO_PTEGIDX_SET(pvo, i); 2120 } else { 2121 panic("moea64_pvo_enter: overflow"); 2122 moea64_pte_overflow++; 2123 } 2124 2125 UNLOCK_TABLE(); 2126 2127 return (first ? ENOENT : 0); 2128 } 2129 2130 static void 2131 moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2132 { 2133 struct lpte *pt; 2134 2135 /* 2136 * If there is an active pte entry, we need to deactivate it (and 2137 * save the ref & cfg bits). 2138 */ 2139 LOCK_TABLE(); 2140 pt = moea64_pvo_to_pte(pvo, pteidx); 2141 if (pt != NULL) { 2142 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2143 pvo->pvo_vaddr); 2144 PVO_PTEGIDX_CLR(pvo); 2145 } else { 2146 moea64_pte_overflow--; 2147 } 2148 UNLOCK_TABLE(); 2149 2150 /* 2151 * Update our statistics. 2152 */ 2153 pvo->pvo_pmap->pm_stats.resident_count--; 2154 if (pvo->pvo_pte.lpte.pte_lo & PVO_WIRED) 2155 pvo->pvo_pmap->pm_stats.wired_count--; 2156 2157 /* 2158 * Save the REF/CHG bits into their cache if the page is managed. 2159 */ 2160 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2161 struct vm_page *pg; 2162 2163 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2164 if (pg != NULL) { 2165 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2166 (LPTE_REF | LPTE_CHG)); 2167 } 2168 } 2169 2170 /* 2171 * Remove this PVO from the PV list. 2172 */ 2173 LIST_REMOVE(pvo, pvo_vlink); 2174 2175 /* 2176 * Remove this from the overflow list and return it to the pool 2177 * if we aren't going to reuse it. 2178 */ 2179 LIST_REMOVE(pvo, pvo_olink); 2180 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2181 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea64_mpvo_zone : 2182 moea64_upvo_zone, pvo); 2183 moea64_pvo_entries--; 2184 moea64_pvo_remove_calls++; 2185 } 2186 2187 static __inline int 2188 moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2189 { 2190 int pteidx; 2191 2192 /* 2193 * We can find the actual pte entry without searching by grabbing 2194 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2195 * noticing the HID bit. 2196 */ 2197 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2198 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2199 pteidx ^= moea64_pteg_mask * 8; 2200 2201 return (pteidx); 2202 } 2203 2204 static struct pvo_entry * 2205 moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2206 { 2207 struct pvo_entry *pvo; 2208 int ptegidx; 2209 uint64_t vsid; 2210 2211 va &= ~ADDR_POFF; 2212 vsid = va_to_vsid(pm, va); 2213 ptegidx = va_to_pteg(vsid, va); 2214 2215 LOCK_TABLE(); 2216 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2217 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2218 if (pteidx_p) 2219 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2220 break; 2221 } 2222 } 2223 UNLOCK_TABLE(); 2224 2225 return (pvo); 2226 } 2227 2228 static struct lpte * 2229 moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2230 { 2231 struct lpte *pt; 2232 2233 /* 2234 * If we haven't been supplied the ptegidx, calculate it. 2235 */ 2236 if (pteidx == -1) { 2237 int ptegidx; 2238 uint64_t vsid; 2239 2240 vsid = va_to_vsid(pvo->pvo_pmap, pvo->pvo_vaddr); 2241 ptegidx = va_to_pteg(vsid, pvo->pvo_vaddr); 2242 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2243 } 2244 2245 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2246 2247 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2248 !PVO_PTEGIDX_ISSET(pvo)) { 2249 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2250 "valid pte index", pvo); 2251 } 2252 2253 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2254 PVO_PTEGIDX_ISSET(pvo)) { 2255 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2256 "pvo but no valid pte", pvo); 2257 } 2258 2259 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2260 LPTE_VALID) { 2261 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2262 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2263 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2264 } 2265 2266 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2267 ~(LPTE_CHG|LPTE_REF)) != 0) { 2268 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2269 "pte %p in moea64_pteg_table difference is %#x", 2270 pvo, pt, 2271 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2272 } 2273 2274 ASSERT_TABLE_LOCK(); 2275 return (pt); 2276 } 2277 2278 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2279 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2280 "moea64_pteg_table but valid in pvo", pvo, pt); 2281 } 2282 2283 return (NULL); 2284 } 2285 2286 static int 2287 moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2288 { 2289 struct lpte *pt; 2290 int i; 2291 2292 ASSERT_TABLE_LOCK(); 2293 2294 /* 2295 * First try primary hash. 2296 */ 2297 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2298 if ((pt->pte_hi & LPTE_VALID) == 0) { 2299 pvo_pt->pte_hi &= ~LPTE_HID; 2300 moea64_pte_set(pt, pvo_pt); 2301 return (i); 2302 } 2303 } 2304 2305 /* 2306 * Now try secondary hash. 2307 */ 2308 ptegidx ^= moea64_pteg_mask; 2309 2310 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2311 if ((pt->pte_hi & LPTE_VALID) == 0) { 2312 pvo_pt->pte_hi |= LPTE_HID; 2313 moea64_pte_set(pt, pvo_pt); 2314 return (i); 2315 } 2316 } 2317 2318 panic("moea64_pte_insert: overflow"); 2319 return (-1); 2320 } 2321 2322 static boolean_t 2323 moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2324 { 2325 struct pvo_entry *pvo; 2326 struct lpte *pt; 2327 2328 #if 0 2329 if (moea64_attr_fetch(m) & ptebit) 2330 return (TRUE); 2331 #endif 2332 2333 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2334 MOEA_PVO_CHECK(pvo); /* sanity check */ 2335 2336 /* 2337 * See if we saved the bit off. If so, cache it and return 2338 * success. 2339 */ 2340 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2341 moea64_attr_save(m, ptebit); 2342 MOEA_PVO_CHECK(pvo); /* sanity check */ 2343 return (TRUE); 2344 } 2345 } 2346 2347 /* 2348 * No luck, now go through the hard part of looking at the PTEs 2349 * themselves. Sync so that any pending REF/CHG bits are flushed to 2350 * the PTEs. 2351 */ 2352 SYNC(); 2353 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2354 MOEA_PVO_CHECK(pvo); /* sanity check */ 2355 2356 /* 2357 * See if this pvo has a valid PTE. if so, fetch the 2358 * REF/CHG bits from the valid PTE. If the appropriate 2359 * ptebit is set, cache it and return success. 2360 */ 2361 LOCK_TABLE(); 2362 pt = moea64_pvo_to_pte(pvo, -1); 2363 if (pt != NULL) { 2364 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2365 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2366 UNLOCK_TABLE(); 2367 2368 moea64_attr_save(m, ptebit); 2369 MOEA_PVO_CHECK(pvo); /* sanity check */ 2370 return (TRUE); 2371 } 2372 } 2373 UNLOCK_TABLE(); 2374 } 2375 2376 return (FALSE); 2377 } 2378 2379 static u_int 2380 moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit) 2381 { 2382 u_int count; 2383 struct pvo_entry *pvo; 2384 struct lpte *pt; 2385 uint64_t rv; 2386 2387 /* 2388 * Clear the cached value. 2389 */ 2390 rv = moea64_attr_fetch(m); 2391 moea64_attr_clear(m, ptebit); 2392 2393 /* 2394 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2395 * we can reset the right ones). note that since the pvo entries and 2396 * list heads are accessed via BAT0 and are never placed in the page 2397 * table, we don't have to worry about further accesses setting the 2398 * REF/CHG bits. 2399 */ 2400 SYNC(); 2401 2402 /* 2403 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2404 * valid pte clear the ptebit from the valid pte. 2405 */ 2406 count = 0; 2407 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2408 MOEA_PVO_CHECK(pvo); /* sanity check */ 2409 2410 LOCK_TABLE(); 2411 pt = moea64_pvo_to_pte(pvo, -1); 2412 if (pt != NULL) { 2413 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2414 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2415 count++; 2416 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2417 } 2418 } 2419 UNLOCK_TABLE(); 2420 rv |= pvo->pvo_pte.lpte.pte_lo; 2421 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2422 MOEA_PVO_CHECK(pvo); /* sanity check */ 2423 } 2424 2425 if (origbit != NULL) { 2426 *origbit = rv; 2427 } 2428 2429 return (count); 2430 } 2431 2432 boolean_t 2433 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2434 { 2435 return (EFAULT); 2436 } 2437 2438 /* 2439 * Map a set of physical memory pages into the kernel virtual 2440 * address space. Return a pointer to where it is mapped. This 2441 * routine is intended to be used for mapping device memory, 2442 * NOT real memory. 2443 */ 2444 void * 2445 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2446 { 2447 vm_offset_t va, tmpva, ppa, offset; 2448 2449 ppa = trunc_page(pa); 2450 offset = pa & PAGE_MASK; 2451 size = roundup(offset + size, PAGE_SIZE); 2452 2453 va = kmem_alloc_nofault(kernel_map, size); 2454 2455 if (!va) 2456 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2457 2458 for (tmpva = va; size > 0;) { 2459 moea64_kenter(mmu, tmpva, ppa); 2460 size -= PAGE_SIZE; 2461 tmpva += PAGE_SIZE; 2462 ppa += PAGE_SIZE; 2463 } 2464 2465 return ((void *)(va + offset)); 2466 } 2467 2468 void 2469 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2470 { 2471 vm_offset_t base, offset; 2472 2473 base = trunc_page(va); 2474 offset = va & PAGE_MASK; 2475 size = roundup(offset + size, PAGE_SIZE); 2476 2477 kmem_free(kernel_map, base, size); 2478 } 2479 2480 static void 2481 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2482 { 2483 struct pvo_entry *pvo; 2484 vm_offset_t lim; 2485 vm_paddr_t pa; 2486 vm_size_t len; 2487 2488 PMAP_LOCK(pm); 2489 while (sz > 0) { 2490 lim = round_page(va); 2491 len = MIN(lim - va, sz); 2492 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2493 if (pvo != NULL) { 2494 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2495 (va & ADDR_POFF); 2496 moea64_syncicache(pm, va, pa, len); 2497 } 2498 va += len; 2499 sz -= len; 2500 } 2501 PMAP_UNLOCK(pm); 2502 } 2503