1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_map.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_pageout.h> 81 #include <vm/uma.h> 82 83 #include <machine/_inttypes.h> 84 #include <machine/cpu.h> 85 #include <machine/platform.h> 86 #include <machine/frame.h> 87 #include <machine/md_var.h> 88 #include <machine/psl.h> 89 #include <machine/bat.h> 90 #include <machine/hid.h> 91 #include <machine/pte.h> 92 #include <machine/sr.h> 93 #include <machine/trap.h> 94 #include <machine/mmuvar.h> 95 96 #include "mmu_oea64.h" 97 #include "mmu_if.h" 98 #include "moea64_if.h" 99 100 void moea64_release_vsid(uint64_t vsid); 101 uintptr_t moea64_get_unique_vsid(void); 102 103 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 104 #define ENABLE_TRANS(msr) mtmsr(msr) 105 106 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 107 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 108 #define VSID_HASH_MASK 0x0000007fffffffffULL 109 110 /* 111 * Locking semantics: 112 * 113 * There are two locks of interest: the page locks and the pmap locks, which 114 * protect their individual PVO lists and are locked in that order. The contents 115 * of all PVO entries are protected by the locks of their respective pmaps. 116 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 117 * into any list. 118 * 119 */ 120 121 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 122 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 123 124 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 125 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 126 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 127 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 128 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 129 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 130 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 131 132 struct ofw_map { 133 cell_t om_va; 134 cell_t om_len; 135 uint64_t om_pa; 136 cell_t om_mode; 137 }; 138 139 extern unsigned char _etext[]; 140 extern unsigned char _end[]; 141 142 extern void *slbtrap, *slbtrapend; 143 144 /* 145 * Map of physical memory regions. 146 */ 147 static struct mem_region *regions; 148 static struct mem_region *pregions; 149 static struct numa_mem_region *numa_pregions; 150 static u_int phys_avail_count; 151 static int regions_sz, pregions_sz, numapregions_sz; 152 153 extern void bs_remap_earlyboot(void); 154 155 /* 156 * Lock for the SLB tables. 157 */ 158 struct mtx moea64_slb_mutex; 159 160 /* 161 * PTEG data. 162 */ 163 u_long moea64_pteg_count; 164 u_long moea64_pteg_mask; 165 166 /* 167 * PVO data. 168 */ 169 170 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 171 172 static struct pvo_entry *moea64_bpvo_pool; 173 static int moea64_bpvo_pool_index = 0; 174 static int moea64_bpvo_pool_size = 327680; 175 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 176 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 177 &moea64_bpvo_pool_index, 0, ""); 178 179 #define VSID_NBPW (sizeof(u_int32_t) * 8) 180 #ifdef __powerpc64__ 181 #define NVSIDS (NPMAPS * 16) 182 #define VSID_HASHMASK 0xffffffffUL 183 #else 184 #define NVSIDS NPMAPS 185 #define VSID_HASHMASK 0xfffffUL 186 #endif 187 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 188 189 static boolean_t moea64_initialized = FALSE; 190 191 /* 192 * Statistics. 193 */ 194 u_int moea64_pte_valid = 0; 195 u_int moea64_pte_overflow = 0; 196 u_int moea64_pvo_entries = 0; 197 u_int moea64_pvo_enter_calls = 0; 198 u_int moea64_pvo_remove_calls = 0; 199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 200 &moea64_pte_valid, 0, ""); 201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 202 &moea64_pte_overflow, 0, ""); 203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 204 &moea64_pvo_entries, 0, ""); 205 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 206 &moea64_pvo_enter_calls, 0, ""); 207 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 208 &moea64_pvo_remove_calls, 0, ""); 209 210 vm_offset_t moea64_scratchpage_va[2]; 211 struct pvo_entry *moea64_scratchpage_pvo[2]; 212 struct mtx moea64_scratchpage_mtx; 213 214 uint64_t moea64_large_page_mask = 0; 215 uint64_t moea64_large_page_size = 0; 216 int moea64_large_page_shift = 0; 217 218 /* 219 * PVO calls. 220 */ 221 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 222 struct pvo_head *pvo_head); 223 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 224 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 225 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 226 227 /* 228 * Utility routines. 229 */ 230 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 231 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 232 static void moea64_kremove(mmu_t, vm_offset_t); 233 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 234 vm_paddr_t pa, vm_size_t sz); 235 static void moea64_pmap_init_qpages(void); 236 237 /* 238 * Kernel MMU interface 239 */ 240 void moea64_clear_modify(mmu_t, vm_page_t); 241 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 242 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 243 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 244 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 245 u_int flags, int8_t psind); 246 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 247 vm_prot_t); 248 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 249 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 250 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 251 void moea64_init(mmu_t); 252 boolean_t moea64_is_modified(mmu_t, vm_page_t); 253 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 254 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 255 int moea64_ts_referenced(mmu_t, vm_page_t); 256 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 257 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 258 void moea64_page_init(mmu_t, vm_page_t); 259 int moea64_page_wired_mappings(mmu_t, vm_page_t); 260 void moea64_pinit(mmu_t, pmap_t); 261 void moea64_pinit0(mmu_t, pmap_t); 262 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 263 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 264 void moea64_qremove(mmu_t, vm_offset_t, int); 265 void moea64_release(mmu_t, pmap_t); 266 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 267 void moea64_remove_pages(mmu_t, pmap_t); 268 void moea64_remove_all(mmu_t, vm_page_t); 269 void moea64_remove_write(mmu_t, vm_page_t); 270 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 271 void moea64_zero_page(mmu_t, vm_page_t); 272 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 273 void moea64_activate(mmu_t, struct thread *); 274 void moea64_deactivate(mmu_t, struct thread *); 275 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 276 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 277 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 278 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 279 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 280 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 281 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 282 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 283 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 284 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 285 void **va); 286 void moea64_scan_init(mmu_t mmu); 287 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 288 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 289 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 290 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 291 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 292 int *is_user, vm_offset_t *decoded_addr); 293 294 295 static mmu_method_t moea64_methods[] = { 296 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 297 MMUMETHOD(mmu_copy_page, moea64_copy_page), 298 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 299 MMUMETHOD(mmu_enter, moea64_enter), 300 MMUMETHOD(mmu_enter_object, moea64_enter_object), 301 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 302 MMUMETHOD(mmu_extract, moea64_extract), 303 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 304 MMUMETHOD(mmu_init, moea64_init), 305 MMUMETHOD(mmu_is_modified, moea64_is_modified), 306 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 307 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 308 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 309 MMUMETHOD(mmu_map, moea64_map), 310 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 311 MMUMETHOD(mmu_page_init, moea64_page_init), 312 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 313 MMUMETHOD(mmu_pinit, moea64_pinit), 314 MMUMETHOD(mmu_pinit0, moea64_pinit0), 315 MMUMETHOD(mmu_protect, moea64_protect), 316 MMUMETHOD(mmu_qenter, moea64_qenter), 317 MMUMETHOD(mmu_qremove, moea64_qremove), 318 MMUMETHOD(mmu_release, moea64_release), 319 MMUMETHOD(mmu_remove, moea64_remove), 320 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 321 MMUMETHOD(mmu_remove_all, moea64_remove_all), 322 MMUMETHOD(mmu_remove_write, moea64_remove_write), 323 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 324 MMUMETHOD(mmu_unwire, moea64_unwire), 325 MMUMETHOD(mmu_zero_page, moea64_zero_page), 326 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 327 MMUMETHOD(mmu_activate, moea64_activate), 328 MMUMETHOD(mmu_deactivate, moea64_deactivate), 329 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 330 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 331 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 332 333 /* Internal interfaces */ 334 MMUMETHOD(mmu_mapdev, moea64_mapdev), 335 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 336 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 337 MMUMETHOD(mmu_kextract, moea64_kextract), 338 MMUMETHOD(mmu_kenter, moea64_kenter), 339 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 340 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 341 MMUMETHOD(mmu_scan_init, moea64_scan_init), 342 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 343 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 344 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 345 346 { 0, 0 } 347 }; 348 349 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 350 351 static struct pvo_head * 352 vm_page_to_pvoh(vm_page_t m) 353 { 354 355 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 356 return (&m->md.mdpg_pvoh); 357 } 358 359 static struct pvo_entry * 360 alloc_pvo_entry(int bootstrap) 361 { 362 struct pvo_entry *pvo; 363 364 if (!moea64_initialized || bootstrap) { 365 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 366 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 367 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 368 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 369 } 370 pvo = &moea64_bpvo_pool[ 371 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 372 bzero(pvo, sizeof(*pvo)); 373 pvo->pvo_vaddr = PVO_BOOTSTRAP; 374 } else { 375 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 376 bzero(pvo, sizeof(*pvo)); 377 } 378 379 return (pvo); 380 } 381 382 383 static void 384 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 385 { 386 uint64_t vsid; 387 uint64_t hash; 388 int shift; 389 390 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 391 392 pvo->pvo_pmap = pmap; 393 va &= ~ADDR_POFF; 394 pvo->pvo_vaddr |= va; 395 vsid = va_to_vsid(pmap, va); 396 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 397 | (vsid << 16); 398 399 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 400 ADDR_PIDX_SHFT; 401 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 402 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 403 } 404 405 static void 406 free_pvo_entry(struct pvo_entry *pvo) 407 { 408 409 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 410 uma_zfree(moea64_pvo_zone, pvo); 411 } 412 413 void 414 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 415 { 416 417 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 418 LPTE_AVPN_MASK; 419 lpte->pte_hi |= LPTE_VALID; 420 421 if (pvo->pvo_vaddr & PVO_LARGE) 422 lpte->pte_hi |= LPTE_BIG; 423 if (pvo->pvo_vaddr & PVO_WIRED) 424 lpte->pte_hi |= LPTE_WIRED; 425 if (pvo->pvo_vaddr & PVO_HID) 426 lpte->pte_hi |= LPTE_HID; 427 428 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 429 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 430 lpte->pte_lo |= LPTE_BW; 431 else 432 lpte->pte_lo |= LPTE_BR; 433 434 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 435 lpte->pte_lo |= LPTE_NOEXEC; 436 } 437 438 static __inline uint64_t 439 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 440 { 441 uint64_t pte_lo; 442 int i; 443 444 if (ma != VM_MEMATTR_DEFAULT) { 445 switch (ma) { 446 case VM_MEMATTR_UNCACHEABLE: 447 return (LPTE_I | LPTE_G); 448 case VM_MEMATTR_CACHEABLE: 449 return (LPTE_M); 450 case VM_MEMATTR_WRITE_COMBINING: 451 case VM_MEMATTR_WRITE_BACK: 452 case VM_MEMATTR_PREFETCHABLE: 453 return (LPTE_I); 454 case VM_MEMATTR_WRITE_THROUGH: 455 return (LPTE_W | LPTE_M); 456 } 457 } 458 459 /* 460 * Assume the page is cache inhibited and access is guarded unless 461 * it's in our available memory array. 462 */ 463 pte_lo = LPTE_I | LPTE_G; 464 for (i = 0; i < pregions_sz; i++) { 465 if ((pa >= pregions[i].mr_start) && 466 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 467 pte_lo &= ~(LPTE_I | LPTE_G); 468 pte_lo |= LPTE_M; 469 break; 470 } 471 } 472 473 return pte_lo; 474 } 475 476 /* 477 * Quick sort callout for comparing memory regions. 478 */ 479 static int om_cmp(const void *a, const void *b); 480 481 static int 482 om_cmp(const void *a, const void *b) 483 { 484 const struct ofw_map *mapa; 485 const struct ofw_map *mapb; 486 487 mapa = a; 488 mapb = b; 489 if (mapa->om_pa < mapb->om_pa) 490 return (-1); 491 else if (mapa->om_pa > mapb->om_pa) 492 return (1); 493 else 494 return (0); 495 } 496 497 static void 498 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 499 { 500 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 501 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 502 struct pvo_entry *pvo; 503 register_t msr; 504 vm_offset_t off; 505 vm_paddr_t pa_base; 506 int i, j; 507 508 bzero(translations, sz); 509 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 510 sizeof(acells)); 511 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 512 panic("moea64_bootstrap: can't get ofw translations"); 513 514 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 515 sz /= sizeof(cell_t); 516 for (i = 0, j = 0; i < sz; j++) { 517 translations[j].om_va = trans_cells[i++]; 518 translations[j].om_len = trans_cells[i++]; 519 translations[j].om_pa = trans_cells[i++]; 520 if (acells == 2) { 521 translations[j].om_pa <<= 32; 522 translations[j].om_pa |= trans_cells[i++]; 523 } 524 translations[j].om_mode = trans_cells[i++]; 525 } 526 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 527 i, sz)); 528 529 sz = j; 530 qsort(translations, sz, sizeof (*translations), om_cmp); 531 532 for (i = 0; i < sz; i++) { 533 pa_base = translations[i].om_pa; 534 #ifndef __powerpc64__ 535 if ((translations[i].om_pa >> 32) != 0) 536 panic("OFW translations above 32-bit boundary!"); 537 #endif 538 539 if (pa_base % PAGE_SIZE) 540 panic("OFW translation not page-aligned (phys)!"); 541 if (translations[i].om_va % PAGE_SIZE) 542 panic("OFW translation not page-aligned (virt)!"); 543 544 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 545 pa_base, translations[i].om_va, translations[i].om_len); 546 547 /* Now enter the pages for this mapping */ 548 549 DISABLE_TRANS(msr); 550 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 551 /* If this address is direct-mapped, skip remapping */ 552 if (hw_direct_map && 553 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 554 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 555 == LPTE_M) 556 continue; 557 558 PMAP_LOCK(kernel_pmap); 559 pvo = moea64_pvo_find_va(kernel_pmap, 560 translations[i].om_va + off); 561 PMAP_UNLOCK(kernel_pmap); 562 if (pvo != NULL) 563 continue; 564 565 moea64_kenter(mmup, translations[i].om_va + off, 566 pa_base + off); 567 } 568 ENABLE_TRANS(msr); 569 } 570 } 571 572 #ifdef __powerpc64__ 573 static void 574 moea64_probe_large_page(void) 575 { 576 uint16_t pvr = mfpvr() >> 16; 577 578 switch (pvr) { 579 case IBM970: 580 case IBM970FX: 581 case IBM970MP: 582 powerpc_sync(); isync(); 583 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 584 powerpc_sync(); isync(); 585 586 /* FALLTHROUGH */ 587 default: 588 if (moea64_large_page_size == 0) { 589 moea64_large_page_size = 0x1000000; /* 16 MB */ 590 moea64_large_page_shift = 24; 591 } 592 } 593 594 moea64_large_page_mask = moea64_large_page_size - 1; 595 } 596 597 static void 598 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 599 { 600 struct slb *cache; 601 struct slb entry; 602 uint64_t esid, slbe; 603 uint64_t i; 604 605 cache = PCPU_GET(aim.slb); 606 esid = va >> ADDR_SR_SHFT; 607 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 608 609 for (i = 0; i < 64; i++) { 610 if (cache[i].slbe == (slbe | i)) 611 return; 612 } 613 614 entry.slbe = slbe; 615 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 616 if (large) 617 entry.slbv |= SLBV_L; 618 619 slb_insert_kernel(entry.slbe, entry.slbv); 620 } 621 #endif 622 623 static void 624 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 625 vm_offset_t kernelend) 626 { 627 struct pvo_entry *pvo; 628 register_t msr; 629 vm_paddr_t pa; 630 vm_offset_t size, off; 631 uint64_t pte_lo; 632 int i; 633 634 if (moea64_large_page_size == 0) 635 hw_direct_map = 0; 636 637 DISABLE_TRANS(msr); 638 if (hw_direct_map) { 639 PMAP_LOCK(kernel_pmap); 640 for (i = 0; i < pregions_sz; i++) { 641 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 642 pregions[i].mr_size; pa += moea64_large_page_size) { 643 pte_lo = LPTE_M; 644 645 pvo = alloc_pvo_entry(1 /* bootstrap */); 646 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 647 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 648 649 /* 650 * Set memory access as guarded if prefetch within 651 * the page could exit the available physmem area. 652 */ 653 if (pa & moea64_large_page_mask) { 654 pa &= moea64_large_page_mask; 655 pte_lo |= LPTE_G; 656 } 657 if (pa + moea64_large_page_size > 658 pregions[i].mr_start + pregions[i].mr_size) 659 pte_lo |= LPTE_G; 660 661 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 662 VM_PROT_EXECUTE; 663 pvo->pvo_pte.pa = pa | pte_lo; 664 moea64_pvo_enter(mmup, pvo, NULL); 665 } 666 } 667 PMAP_UNLOCK(kernel_pmap); 668 } 669 670 /* 671 * Make sure the kernel and BPVO pool stay mapped on systems either 672 * without a direct map or on which the kernel is not already executing 673 * out of the direct-mapped region. 674 */ 675 676 if (!hw_direct_map || kernelstart < DMAP_BASE_ADDRESS) { 677 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 678 pa += PAGE_SIZE) 679 moea64_kenter(mmup, pa, pa); 680 } 681 682 if (!hw_direct_map) { 683 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 684 off = (vm_offset_t)(moea64_bpvo_pool); 685 for (pa = off; pa < off + size; pa += PAGE_SIZE) 686 moea64_kenter(mmup, pa, pa); 687 } 688 ENABLE_TRANS(msr); 689 690 /* 691 * Allow user to override unmapped_buf_allowed for testing. 692 * XXXKIB Only direct map implementation was tested. 693 */ 694 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 695 &unmapped_buf_allowed)) 696 unmapped_buf_allowed = hw_direct_map; 697 } 698 699 /* Quick sort callout for comparing physical addresses. */ 700 static int 701 pa_cmp(const void *a, const void *b) 702 { 703 const vm_paddr_t *pa = a, *pb = b; 704 705 if (*pa < *pb) 706 return (-1); 707 else if (*pa > *pb) 708 return (1); 709 else 710 return (0); 711 } 712 713 void 714 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 715 { 716 int i, j; 717 vm_size_t physsz, hwphyssz; 718 vm_paddr_t kernelphysstart, kernelphysend; 719 int rm_pavail; 720 721 #ifndef __powerpc64__ 722 /* We don't have a direct map since there is no BAT */ 723 hw_direct_map = 0; 724 725 /* Make sure battable is zero, since we have no BAT */ 726 for (i = 0; i < 16; i++) { 727 battable[i].batu = 0; 728 battable[i].batl = 0; 729 } 730 #else 731 moea64_probe_large_page(); 732 733 /* Use a direct map if we have large page support */ 734 if (moea64_large_page_size > 0) 735 hw_direct_map = 1; 736 else 737 hw_direct_map = 0; 738 739 /* Install trap handlers for SLBs */ 740 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 741 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 742 __syncicache((void *)EXC_DSE, 0x80); 743 __syncicache((void *)EXC_ISE, 0x80); 744 #endif 745 746 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 747 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 748 749 /* Get physical memory regions from firmware */ 750 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 751 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 752 753 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 754 panic("moea64_bootstrap: phys_avail too small"); 755 756 phys_avail_count = 0; 757 physsz = 0; 758 hwphyssz = 0; 759 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 760 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 761 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 762 regions[i].mr_start, regions[i].mr_start + 763 regions[i].mr_size, regions[i].mr_size); 764 if (hwphyssz != 0 && 765 (physsz + regions[i].mr_size) >= hwphyssz) { 766 if (physsz < hwphyssz) { 767 phys_avail[j] = regions[i].mr_start; 768 phys_avail[j + 1] = regions[i].mr_start + 769 hwphyssz - physsz; 770 physsz = hwphyssz; 771 phys_avail_count++; 772 } 773 break; 774 } 775 phys_avail[j] = regions[i].mr_start; 776 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 777 phys_avail_count++; 778 physsz += regions[i].mr_size; 779 } 780 781 /* Check for overlap with the kernel and exception vectors */ 782 rm_pavail = 0; 783 for (j = 0; j < 2*phys_avail_count; j+=2) { 784 if (phys_avail[j] < EXC_LAST) 785 phys_avail[j] += EXC_LAST; 786 787 if (phys_avail[j] >= kernelphysstart && 788 phys_avail[j+1] <= kernelphysend) { 789 phys_avail[j] = phys_avail[j+1] = ~0; 790 rm_pavail++; 791 continue; 792 } 793 794 if (kernelphysstart >= phys_avail[j] && 795 kernelphysstart < phys_avail[j+1]) { 796 if (kernelphysend < phys_avail[j+1]) { 797 phys_avail[2*phys_avail_count] = 798 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 799 phys_avail[2*phys_avail_count + 1] = 800 phys_avail[j+1]; 801 phys_avail_count++; 802 } 803 804 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 805 } 806 807 if (kernelphysend >= phys_avail[j] && 808 kernelphysend < phys_avail[j+1]) { 809 if (kernelphysstart > phys_avail[j]) { 810 phys_avail[2*phys_avail_count] = phys_avail[j]; 811 phys_avail[2*phys_avail_count + 1] = 812 kernelphysstart & ~PAGE_MASK; 813 phys_avail_count++; 814 } 815 816 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 817 PAGE_SIZE; 818 } 819 } 820 821 /* Remove physical available regions marked for removal (~0) */ 822 if (rm_pavail) { 823 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 824 pa_cmp); 825 phys_avail_count -= rm_pavail; 826 for (i = 2*phys_avail_count; 827 i < 2*(phys_avail_count + rm_pavail); i+=2) 828 phys_avail[i] = phys_avail[i+1] = 0; 829 } 830 831 physmem = btoc(physsz); 832 833 #ifdef PTEGCOUNT 834 moea64_pteg_count = PTEGCOUNT; 835 #else 836 moea64_pteg_count = 0x1000; 837 838 while (moea64_pteg_count < physmem) 839 moea64_pteg_count <<= 1; 840 841 moea64_pteg_count >>= 1; 842 #endif /* PTEGCOUNT */ 843 } 844 845 void 846 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 847 { 848 int i; 849 850 /* 851 * Set PTEG mask 852 */ 853 moea64_pteg_mask = moea64_pteg_count - 1; 854 855 /* 856 * Initialize SLB table lock and page locks 857 */ 858 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 859 for (i = 0; i < PV_LOCK_COUNT; i++) 860 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 861 862 /* 863 * Initialise the bootstrap pvo pool. 864 */ 865 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 866 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 867 moea64_bpvo_pool_index = 0; 868 869 /* Place at address usable through the direct map */ 870 if (hw_direct_map) 871 moea64_bpvo_pool = (struct pvo_entry *) 872 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 873 874 /* 875 * Make sure kernel vsid is allocated as well as VSID 0. 876 */ 877 #ifndef __powerpc64__ 878 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 879 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 880 moea64_vsid_bitmap[0] |= 1; 881 #endif 882 883 /* 884 * Initialize the kernel pmap (which is statically allocated). 885 */ 886 #ifdef __powerpc64__ 887 for (i = 0; i < 64; i++) { 888 pcpup->pc_aim.slb[i].slbv = 0; 889 pcpup->pc_aim.slb[i].slbe = 0; 890 } 891 #else 892 for (i = 0; i < 16; i++) 893 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 894 #endif 895 896 kernel_pmap->pmap_phys = kernel_pmap; 897 CPU_FILL(&kernel_pmap->pm_active); 898 RB_INIT(&kernel_pmap->pmap_pvo); 899 900 PMAP_LOCK_INIT(kernel_pmap); 901 902 /* 903 * Now map in all the other buffers we allocated earlier 904 */ 905 906 moea64_setup_direct_map(mmup, kernelstart, kernelend); 907 } 908 909 void 910 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 911 { 912 ihandle_t mmui; 913 phandle_t chosen; 914 phandle_t mmu; 915 ssize_t sz; 916 int i; 917 vm_offset_t pa, va; 918 void *dpcpu; 919 920 /* 921 * Set up the Open Firmware pmap and add its mappings if not in real 922 * mode. 923 */ 924 925 chosen = OF_finddevice("/chosen"); 926 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 927 mmu = OF_instance_to_package(mmui); 928 if (mmu == -1 || 929 (sz = OF_getproplen(mmu, "translations")) == -1) 930 sz = 0; 931 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 932 panic("moea64_bootstrap: too many ofw translations"); 933 934 if (sz > 0) 935 moea64_add_ofw_mappings(mmup, mmu, sz); 936 } 937 938 /* 939 * Calculate the last available physical address. 940 */ 941 Maxmem = 0; 942 for (i = 0; phys_avail[i + 2] != 0; i += 2) 943 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 944 945 /* 946 * Initialize MMU. 947 */ 948 MMU_CPU_BOOTSTRAP(mmup,0); 949 mtmsr(mfmsr() | PSL_DR | PSL_IR); 950 pmap_bootstrapped++; 951 952 /* 953 * Set the start and end of kva. 954 */ 955 virtual_avail = VM_MIN_KERNEL_ADDRESS; 956 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 957 958 /* 959 * Map the entire KVA range into the SLB. We must not fault there. 960 */ 961 #ifdef __powerpc64__ 962 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 963 moea64_bootstrap_slb_prefault(va, 0); 964 #endif 965 966 /* 967 * Remap any early IO mappings (console framebuffer, etc.) 968 */ 969 bs_remap_earlyboot(); 970 971 /* 972 * Figure out how far we can extend virtual_end into segment 16 973 * without running into existing mappings. Segment 16 is guaranteed 974 * to contain neither RAM nor devices (at least on Apple hardware), 975 * but will generally contain some OFW mappings we should not 976 * step on. 977 */ 978 979 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 980 PMAP_LOCK(kernel_pmap); 981 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 982 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 983 virtual_end += PAGE_SIZE; 984 PMAP_UNLOCK(kernel_pmap); 985 #endif 986 987 /* 988 * Allocate a kernel stack with a guard page for thread0 and map it 989 * into the kernel page map. 990 */ 991 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 992 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 993 virtual_avail = va + kstack_pages * PAGE_SIZE; 994 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 995 thread0.td_kstack = va; 996 thread0.td_kstack_pages = kstack_pages; 997 for (i = 0; i < kstack_pages; i++) { 998 moea64_kenter(mmup, va, pa); 999 pa += PAGE_SIZE; 1000 va += PAGE_SIZE; 1001 } 1002 1003 /* 1004 * Allocate virtual address space for the message buffer. 1005 */ 1006 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1007 msgbufp = (struct msgbuf *)virtual_avail; 1008 va = virtual_avail; 1009 virtual_avail += round_page(msgbufsize); 1010 while (va < virtual_avail) { 1011 moea64_kenter(mmup, va, pa); 1012 pa += PAGE_SIZE; 1013 va += PAGE_SIZE; 1014 } 1015 1016 /* 1017 * Allocate virtual address space for the dynamic percpu area. 1018 */ 1019 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1020 dpcpu = (void *)virtual_avail; 1021 va = virtual_avail; 1022 virtual_avail += DPCPU_SIZE; 1023 while (va < virtual_avail) { 1024 moea64_kenter(mmup, va, pa); 1025 pa += PAGE_SIZE; 1026 va += PAGE_SIZE; 1027 } 1028 dpcpu_init(dpcpu, curcpu); 1029 1030 /* 1031 * Allocate some things for page zeroing. We put this directly 1032 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1033 * of the PVO book-keeping or other parts of the VM system 1034 * from even knowing that this hack exists. 1035 */ 1036 1037 if (!hw_direct_map) { 1038 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1039 MTX_DEF); 1040 for (i = 0; i < 2; i++) { 1041 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1042 virtual_end -= PAGE_SIZE; 1043 1044 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1045 1046 PMAP_LOCK(kernel_pmap); 1047 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1048 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1049 PMAP_UNLOCK(kernel_pmap); 1050 } 1051 } 1052 1053 numa_mem_regions(&numa_pregions, &numapregions_sz); 1054 } 1055 1056 static void 1057 moea64_pmap_init_qpages(void) 1058 { 1059 struct pcpu *pc; 1060 int i; 1061 1062 if (hw_direct_map) 1063 return; 1064 1065 CPU_FOREACH(i) { 1066 pc = pcpu_find(i); 1067 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1068 if (pc->pc_qmap_addr == 0) 1069 panic("pmap_init_qpages: unable to allocate KVA"); 1070 PMAP_LOCK(kernel_pmap); 1071 pc->pc_aim.qmap_pvo = 1072 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1073 PMAP_UNLOCK(kernel_pmap); 1074 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1075 } 1076 } 1077 1078 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1079 1080 /* 1081 * Activate a user pmap. This mostly involves setting some non-CPU 1082 * state. 1083 */ 1084 void 1085 moea64_activate(mmu_t mmu, struct thread *td) 1086 { 1087 pmap_t pm; 1088 1089 pm = &td->td_proc->p_vmspace->vm_pmap; 1090 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1091 1092 #ifdef __powerpc64__ 1093 PCPU_SET(aim.userslb, pm->pm_slb); 1094 __asm __volatile("slbmte %0, %1; isync" :: 1095 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1096 #else 1097 PCPU_SET(curpmap, pm->pmap_phys); 1098 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1099 #endif 1100 } 1101 1102 void 1103 moea64_deactivate(mmu_t mmu, struct thread *td) 1104 { 1105 pmap_t pm; 1106 1107 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1108 1109 pm = &td->td_proc->p_vmspace->vm_pmap; 1110 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1111 #ifdef __powerpc64__ 1112 PCPU_SET(aim.userslb, NULL); 1113 #else 1114 PCPU_SET(curpmap, NULL); 1115 #endif 1116 } 1117 1118 void 1119 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1120 { 1121 struct pvo_entry key, *pvo; 1122 vm_page_t m; 1123 int64_t refchg; 1124 1125 key.pvo_vaddr = sva; 1126 PMAP_LOCK(pm); 1127 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1128 pvo != NULL && PVO_VADDR(pvo) < eva; 1129 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1130 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1131 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1132 pvo); 1133 pvo->pvo_vaddr &= ~PVO_WIRED; 1134 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1135 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1136 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1137 if (refchg < 0) 1138 refchg = LPTE_CHG; 1139 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1140 1141 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1142 if (refchg & LPTE_CHG) 1143 vm_page_dirty(m); 1144 if (refchg & LPTE_REF) 1145 vm_page_aflag_set(m, PGA_REFERENCED); 1146 } 1147 pm->pm_stats.wired_count--; 1148 } 1149 PMAP_UNLOCK(pm); 1150 } 1151 1152 /* 1153 * This goes through and sets the physical address of our 1154 * special scratch PTE to the PA we want to zero or copy. Because 1155 * of locking issues (this can get called in pvo_enter() by 1156 * the UMA allocator), we can't use most other utility functions here 1157 */ 1158 1159 static __inline 1160 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1161 1162 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1163 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1164 1165 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1166 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1167 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1168 MOEA64_PTE_INVALIDATE); 1169 isync(); 1170 } 1171 1172 void 1173 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1174 { 1175 vm_offset_t dst; 1176 vm_offset_t src; 1177 1178 dst = VM_PAGE_TO_PHYS(mdst); 1179 src = VM_PAGE_TO_PHYS(msrc); 1180 1181 if (hw_direct_map) { 1182 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1183 PAGE_SIZE); 1184 } else { 1185 mtx_lock(&moea64_scratchpage_mtx); 1186 1187 moea64_set_scratchpage_pa(mmu, 0, src); 1188 moea64_set_scratchpage_pa(mmu, 1, dst); 1189 1190 bcopy((void *)moea64_scratchpage_va[0], 1191 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1192 1193 mtx_unlock(&moea64_scratchpage_mtx); 1194 } 1195 } 1196 1197 static inline void 1198 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1199 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1200 { 1201 void *a_cp, *b_cp; 1202 vm_offset_t a_pg_offset, b_pg_offset; 1203 int cnt; 1204 1205 while (xfersize > 0) { 1206 a_pg_offset = a_offset & PAGE_MASK; 1207 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1208 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1209 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1210 a_pg_offset; 1211 b_pg_offset = b_offset & PAGE_MASK; 1212 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1213 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1214 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1215 b_pg_offset; 1216 bcopy(a_cp, b_cp, cnt); 1217 a_offset += cnt; 1218 b_offset += cnt; 1219 xfersize -= cnt; 1220 } 1221 } 1222 1223 static inline void 1224 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1225 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1226 { 1227 void *a_cp, *b_cp; 1228 vm_offset_t a_pg_offset, b_pg_offset; 1229 int cnt; 1230 1231 mtx_lock(&moea64_scratchpage_mtx); 1232 while (xfersize > 0) { 1233 a_pg_offset = a_offset & PAGE_MASK; 1234 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1235 moea64_set_scratchpage_pa(mmu, 0, 1236 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1237 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1238 b_pg_offset = b_offset & PAGE_MASK; 1239 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1240 moea64_set_scratchpage_pa(mmu, 1, 1241 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1242 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1243 bcopy(a_cp, b_cp, cnt); 1244 a_offset += cnt; 1245 b_offset += cnt; 1246 xfersize -= cnt; 1247 } 1248 mtx_unlock(&moea64_scratchpage_mtx); 1249 } 1250 1251 void 1252 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1253 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1254 { 1255 1256 if (hw_direct_map) { 1257 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1258 xfersize); 1259 } else { 1260 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1261 xfersize); 1262 } 1263 } 1264 1265 void 1266 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1267 { 1268 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1269 1270 if (size + off > PAGE_SIZE) 1271 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1272 1273 if (hw_direct_map) { 1274 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1275 } else { 1276 mtx_lock(&moea64_scratchpage_mtx); 1277 moea64_set_scratchpage_pa(mmu, 0, pa); 1278 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1279 mtx_unlock(&moea64_scratchpage_mtx); 1280 } 1281 } 1282 1283 /* 1284 * Zero a page of physical memory by temporarily mapping it 1285 */ 1286 void 1287 moea64_zero_page(mmu_t mmu, vm_page_t m) 1288 { 1289 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1290 vm_offset_t va, off; 1291 1292 if (!hw_direct_map) { 1293 mtx_lock(&moea64_scratchpage_mtx); 1294 1295 moea64_set_scratchpage_pa(mmu, 0, pa); 1296 va = moea64_scratchpage_va[0]; 1297 } else { 1298 va = PHYS_TO_DMAP(pa); 1299 } 1300 1301 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1302 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1303 1304 if (!hw_direct_map) 1305 mtx_unlock(&moea64_scratchpage_mtx); 1306 } 1307 1308 vm_offset_t 1309 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1310 { 1311 struct pvo_entry *pvo; 1312 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1313 1314 if (hw_direct_map) 1315 return (PHYS_TO_DMAP(pa)); 1316 1317 /* 1318 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1319 * a critical section and access the PCPU data like on i386. 1320 * Instead, pin the thread and grab the PCPU lock to prevent 1321 * a preempting thread from using the same PCPU data. 1322 */ 1323 sched_pin(); 1324 1325 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1326 pvo = PCPU_GET(aim.qmap_pvo); 1327 1328 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1329 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1330 (uint64_t)pa; 1331 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1332 isync(); 1333 1334 return (PCPU_GET(qmap_addr)); 1335 } 1336 1337 void 1338 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1339 { 1340 if (hw_direct_map) 1341 return; 1342 1343 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1344 KASSERT(PCPU_GET(qmap_addr) == addr, 1345 ("moea64_quick_remove_page: invalid address")); 1346 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1347 sched_unpin(); 1348 } 1349 1350 /* 1351 * Map the given physical page at the specified virtual address in the 1352 * target pmap with the protection requested. If specified the page 1353 * will be wired down. 1354 */ 1355 1356 int 1357 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1358 vm_prot_t prot, u_int flags, int8_t psind) 1359 { 1360 struct pvo_entry *pvo, *oldpvo; 1361 struct pvo_head *pvo_head; 1362 uint64_t pte_lo; 1363 int error; 1364 1365 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1366 VM_OBJECT_ASSERT_LOCKED(m->object); 1367 1368 pvo = alloc_pvo_entry(0); 1369 pvo->pvo_pmap = NULL; /* to be filled in later */ 1370 pvo->pvo_pte.prot = prot; 1371 1372 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1373 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1374 1375 if ((flags & PMAP_ENTER_WIRED) != 0) 1376 pvo->pvo_vaddr |= PVO_WIRED; 1377 1378 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1379 pvo_head = NULL; 1380 } else { 1381 pvo_head = &m->md.mdpg_pvoh; 1382 pvo->pvo_vaddr |= PVO_MANAGED; 1383 } 1384 1385 for (;;) { 1386 PV_PAGE_LOCK(m); 1387 PMAP_LOCK(pmap); 1388 if (pvo->pvo_pmap == NULL) 1389 init_pvo_entry(pvo, pmap, va); 1390 if (prot & VM_PROT_WRITE) 1391 if (pmap_bootstrapped && 1392 (m->oflags & VPO_UNMANAGED) == 0) 1393 vm_page_aflag_set(m, PGA_WRITEABLE); 1394 1395 oldpvo = moea64_pvo_find_va(pmap, va); 1396 if (oldpvo != NULL) { 1397 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1398 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1399 oldpvo->pvo_pte.prot == prot) { 1400 /* Identical mapping already exists */ 1401 error = 0; 1402 1403 /* If not in page table, reinsert it */ 1404 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1405 moea64_pte_overflow--; 1406 MOEA64_PTE_INSERT(mmu, oldpvo); 1407 } 1408 1409 /* Then just clean up and go home */ 1410 PV_PAGE_UNLOCK(m); 1411 PMAP_UNLOCK(pmap); 1412 free_pvo_entry(pvo); 1413 break; 1414 } 1415 1416 /* Otherwise, need to kill it first */ 1417 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1418 "mapping does not match new mapping")); 1419 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1420 } 1421 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1422 PV_PAGE_UNLOCK(m); 1423 PMAP_UNLOCK(pmap); 1424 1425 /* Free any dead pages */ 1426 if (oldpvo != NULL) { 1427 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1428 moea64_pvo_remove_from_page(mmu, oldpvo); 1429 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1430 free_pvo_entry(oldpvo); 1431 } 1432 1433 if (error != ENOMEM) 1434 break; 1435 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1436 return (KERN_RESOURCE_SHORTAGE); 1437 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1438 vm_wait(NULL); 1439 } 1440 1441 /* 1442 * Flush the page from the instruction cache if this page is 1443 * mapped executable and cacheable. 1444 */ 1445 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1446 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1447 vm_page_aflag_set(m, PGA_EXECUTABLE); 1448 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1449 } 1450 return (KERN_SUCCESS); 1451 } 1452 1453 static void 1454 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1455 vm_size_t sz) 1456 { 1457 1458 /* 1459 * This is much trickier than on older systems because 1460 * we can't sync the icache on physical addresses directly 1461 * without a direct map. Instead we check a couple of cases 1462 * where the memory is already mapped in and, failing that, 1463 * use the same trick we use for page zeroing to create 1464 * a temporary mapping for this physical address. 1465 */ 1466 1467 if (!pmap_bootstrapped) { 1468 /* 1469 * If PMAP is not bootstrapped, we are likely to be 1470 * in real mode. 1471 */ 1472 __syncicache((void *)(uintptr_t)pa, sz); 1473 } else if (pmap == kernel_pmap) { 1474 __syncicache((void *)va, sz); 1475 } else if (hw_direct_map) { 1476 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1477 } else { 1478 /* Use the scratch page to set up a temp mapping */ 1479 1480 mtx_lock(&moea64_scratchpage_mtx); 1481 1482 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1483 __syncicache((void *)(moea64_scratchpage_va[1] + 1484 (va & ADDR_POFF)), sz); 1485 1486 mtx_unlock(&moea64_scratchpage_mtx); 1487 } 1488 } 1489 1490 /* 1491 * Maps a sequence of resident pages belonging to the same object. 1492 * The sequence begins with the given page m_start. This page is 1493 * mapped at the given virtual address start. Each subsequent page is 1494 * mapped at a virtual address that is offset from start by the same 1495 * amount as the page is offset from m_start within the object. The 1496 * last page in the sequence is the page with the largest offset from 1497 * m_start that can be mapped at a virtual address less than the given 1498 * virtual address end. Not every virtual page between start and end 1499 * is mapped; only those for which a resident page exists with the 1500 * corresponding offset from m_start are mapped. 1501 */ 1502 void 1503 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1504 vm_page_t m_start, vm_prot_t prot) 1505 { 1506 vm_page_t m; 1507 vm_pindex_t diff, psize; 1508 1509 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1510 1511 psize = atop(end - start); 1512 m = m_start; 1513 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1514 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1515 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1516 m = TAILQ_NEXT(m, listq); 1517 } 1518 } 1519 1520 void 1521 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1522 vm_prot_t prot) 1523 { 1524 1525 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1526 PMAP_ENTER_NOSLEEP, 0); 1527 } 1528 1529 vm_paddr_t 1530 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1531 { 1532 struct pvo_entry *pvo; 1533 vm_paddr_t pa; 1534 1535 PMAP_LOCK(pm); 1536 pvo = moea64_pvo_find_va(pm, va); 1537 if (pvo == NULL) 1538 pa = 0; 1539 else 1540 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1541 PMAP_UNLOCK(pm); 1542 1543 return (pa); 1544 } 1545 1546 /* 1547 * Atomically extract and hold the physical page with the given 1548 * pmap and virtual address pair if that mapping permits the given 1549 * protection. 1550 */ 1551 vm_page_t 1552 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1553 { 1554 struct pvo_entry *pvo; 1555 vm_page_t m; 1556 vm_paddr_t pa; 1557 1558 m = NULL; 1559 pa = 0; 1560 PMAP_LOCK(pmap); 1561 retry: 1562 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1563 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1564 if (vm_page_pa_tryrelock(pmap, 1565 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1566 goto retry; 1567 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1568 vm_page_hold(m); 1569 } 1570 PA_UNLOCK_COND(pa); 1571 PMAP_UNLOCK(pmap); 1572 return (m); 1573 } 1574 1575 static mmu_t installed_mmu; 1576 1577 static void * 1578 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1579 uint8_t *flags, int wait) 1580 { 1581 struct pvo_entry *pvo; 1582 vm_offset_t va; 1583 vm_page_t m; 1584 int needed_lock; 1585 1586 /* 1587 * This entire routine is a horrible hack to avoid bothering kmem 1588 * for new KVA addresses. Because this can get called from inside 1589 * kmem allocation routines, calling kmem for a new address here 1590 * can lead to multiply locking non-recursive mutexes. 1591 */ 1592 1593 *flags = UMA_SLAB_PRIV; 1594 needed_lock = !PMAP_LOCKED(kernel_pmap); 1595 1596 m = vm_page_alloc_domain(NULL, 0, domain, 1597 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1598 if (m == NULL) 1599 return (NULL); 1600 1601 va = VM_PAGE_TO_PHYS(m); 1602 1603 pvo = alloc_pvo_entry(1 /* bootstrap */); 1604 1605 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1606 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1607 1608 if (needed_lock) 1609 PMAP_LOCK(kernel_pmap); 1610 1611 init_pvo_entry(pvo, kernel_pmap, va); 1612 pvo->pvo_vaddr |= PVO_WIRED; 1613 1614 moea64_pvo_enter(installed_mmu, pvo, NULL); 1615 1616 if (needed_lock) 1617 PMAP_UNLOCK(kernel_pmap); 1618 1619 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1620 bzero((void *)va, PAGE_SIZE); 1621 1622 return (void *)va; 1623 } 1624 1625 extern int elf32_nxstack; 1626 1627 void 1628 moea64_init(mmu_t mmu) 1629 { 1630 1631 CTR0(KTR_PMAP, "moea64_init"); 1632 1633 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1634 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1635 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1636 1637 if (!hw_direct_map) { 1638 installed_mmu = mmu; 1639 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1640 } 1641 1642 #ifdef COMPAT_FREEBSD32 1643 elf32_nxstack = 1; 1644 #endif 1645 1646 moea64_initialized = TRUE; 1647 } 1648 1649 boolean_t 1650 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1651 { 1652 1653 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1654 ("moea64_is_referenced: page %p is not managed", m)); 1655 1656 return (moea64_query_bit(mmu, m, LPTE_REF)); 1657 } 1658 1659 boolean_t 1660 moea64_is_modified(mmu_t mmu, vm_page_t m) 1661 { 1662 1663 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1664 ("moea64_is_modified: page %p is not managed", m)); 1665 1666 /* 1667 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1668 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1669 * is clear, no PTEs can have LPTE_CHG set. 1670 */ 1671 VM_OBJECT_ASSERT_LOCKED(m->object); 1672 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1673 return (FALSE); 1674 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1675 } 1676 1677 boolean_t 1678 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1679 { 1680 struct pvo_entry *pvo; 1681 boolean_t rv = TRUE; 1682 1683 PMAP_LOCK(pmap); 1684 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1685 if (pvo != NULL) 1686 rv = FALSE; 1687 PMAP_UNLOCK(pmap); 1688 return (rv); 1689 } 1690 1691 void 1692 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1693 { 1694 1695 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1696 ("moea64_clear_modify: page %p is not managed", m)); 1697 VM_OBJECT_ASSERT_WLOCKED(m->object); 1698 KASSERT(!vm_page_xbusied(m), 1699 ("moea64_clear_modify: page %p is exclusive busied", m)); 1700 1701 /* 1702 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1703 * set. If the object containing the page is locked and the page is 1704 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1705 */ 1706 if ((m->aflags & PGA_WRITEABLE) == 0) 1707 return; 1708 moea64_clear_bit(mmu, m, LPTE_CHG); 1709 } 1710 1711 /* 1712 * Clear the write and modified bits in each of the given page's mappings. 1713 */ 1714 void 1715 moea64_remove_write(mmu_t mmu, vm_page_t m) 1716 { 1717 struct pvo_entry *pvo; 1718 int64_t refchg, ret; 1719 pmap_t pmap; 1720 1721 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1722 ("moea64_remove_write: page %p is not managed", m)); 1723 1724 /* 1725 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1726 * set by another thread while the object is locked. Thus, 1727 * if PGA_WRITEABLE is clear, no page table entries need updating. 1728 */ 1729 VM_OBJECT_ASSERT_WLOCKED(m->object); 1730 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1731 return; 1732 powerpc_sync(); 1733 PV_PAGE_LOCK(m); 1734 refchg = 0; 1735 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1736 pmap = pvo->pvo_pmap; 1737 PMAP_LOCK(pmap); 1738 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1739 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1740 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1741 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1742 MOEA64_PTE_PROT_UPDATE); 1743 if (ret < 0) 1744 ret = LPTE_CHG; 1745 refchg |= ret; 1746 if (pvo->pvo_pmap == kernel_pmap) 1747 isync(); 1748 } 1749 PMAP_UNLOCK(pmap); 1750 } 1751 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1752 vm_page_dirty(m); 1753 vm_page_aflag_clear(m, PGA_WRITEABLE); 1754 PV_PAGE_UNLOCK(m); 1755 } 1756 1757 /* 1758 * moea64_ts_referenced: 1759 * 1760 * Return a count of reference bits for a page, clearing those bits. 1761 * It is not necessary for every reference bit to be cleared, but it 1762 * is necessary that 0 only be returned when there are truly no 1763 * reference bits set. 1764 * 1765 * XXX: The exact number of bits to check and clear is a matter that 1766 * should be tested and standardized at some point in the future for 1767 * optimal aging of shared pages. 1768 */ 1769 int 1770 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1771 { 1772 1773 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1774 ("moea64_ts_referenced: page %p is not managed", m)); 1775 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1776 } 1777 1778 /* 1779 * Modify the WIMG settings of all mappings for a page. 1780 */ 1781 void 1782 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1783 { 1784 struct pvo_entry *pvo; 1785 int64_t refchg; 1786 pmap_t pmap; 1787 uint64_t lo; 1788 1789 if ((m->oflags & VPO_UNMANAGED) != 0) { 1790 m->md.mdpg_cache_attrs = ma; 1791 return; 1792 } 1793 1794 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1795 1796 PV_PAGE_LOCK(m); 1797 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1798 pmap = pvo->pvo_pmap; 1799 PMAP_LOCK(pmap); 1800 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1801 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1802 pvo->pvo_pte.pa |= lo; 1803 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1804 MOEA64_PTE_INVALIDATE); 1805 if (refchg < 0) 1806 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1807 LPTE_CHG : 0; 1808 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1809 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1810 refchg |= 1811 atomic_readandclear_32(&m->md.mdpg_attrs); 1812 if (refchg & LPTE_CHG) 1813 vm_page_dirty(m); 1814 if (refchg & LPTE_REF) 1815 vm_page_aflag_set(m, PGA_REFERENCED); 1816 } 1817 if (pvo->pvo_pmap == kernel_pmap) 1818 isync(); 1819 } 1820 PMAP_UNLOCK(pmap); 1821 } 1822 m->md.mdpg_cache_attrs = ma; 1823 PV_PAGE_UNLOCK(m); 1824 } 1825 1826 /* 1827 * Map a wired page into kernel virtual address space. 1828 */ 1829 void 1830 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1831 { 1832 int error; 1833 struct pvo_entry *pvo, *oldpvo; 1834 1835 pvo = alloc_pvo_entry(0); 1836 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1837 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1838 pvo->pvo_vaddr |= PVO_WIRED; 1839 1840 PMAP_LOCK(kernel_pmap); 1841 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1842 if (oldpvo != NULL) 1843 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1844 init_pvo_entry(pvo, kernel_pmap, va); 1845 error = moea64_pvo_enter(mmu, pvo, NULL); 1846 PMAP_UNLOCK(kernel_pmap); 1847 1848 /* Free any dead pages */ 1849 if (oldpvo != NULL) { 1850 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1851 moea64_pvo_remove_from_page(mmu, oldpvo); 1852 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1853 free_pvo_entry(oldpvo); 1854 } 1855 1856 if (error != 0 && error != ENOENT) 1857 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1858 (uintmax_t)pa, error); 1859 } 1860 1861 void 1862 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1863 { 1864 1865 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1866 } 1867 1868 /* 1869 * Extract the physical page address associated with the given kernel virtual 1870 * address. 1871 */ 1872 vm_paddr_t 1873 moea64_kextract(mmu_t mmu, vm_offset_t va) 1874 { 1875 struct pvo_entry *pvo; 1876 vm_paddr_t pa; 1877 1878 /* 1879 * Shortcut the direct-mapped case when applicable. We never put 1880 * anything but 1:1 (or 62-bit aliased) mappings below 1881 * VM_MIN_KERNEL_ADDRESS. 1882 */ 1883 if (va < VM_MIN_KERNEL_ADDRESS) 1884 return (va & ~DMAP_BASE_ADDRESS); 1885 1886 PMAP_LOCK(kernel_pmap); 1887 pvo = moea64_pvo_find_va(kernel_pmap, va); 1888 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1889 va)); 1890 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1891 PMAP_UNLOCK(kernel_pmap); 1892 return (pa); 1893 } 1894 1895 /* 1896 * Remove a wired page from kernel virtual address space. 1897 */ 1898 void 1899 moea64_kremove(mmu_t mmu, vm_offset_t va) 1900 { 1901 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1902 } 1903 1904 /* 1905 * Provide a kernel pointer corresponding to a given userland pointer. 1906 * The returned pointer is valid until the next time this function is 1907 * called in this thread. This is used internally in copyin/copyout. 1908 */ 1909 static int 1910 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1911 void **kaddr, size_t ulen, size_t *klen) 1912 { 1913 size_t l; 1914 #ifdef __powerpc64__ 1915 struct slb *slb; 1916 #endif 1917 register_t slbv; 1918 1919 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1920 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1921 if (l > ulen) 1922 l = ulen; 1923 if (klen) 1924 *klen = l; 1925 else if (l != ulen) 1926 return (EFAULT); 1927 1928 #ifdef __powerpc64__ 1929 /* Try lockless look-up first */ 1930 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1931 1932 if (slb == NULL) { 1933 /* If it isn't there, we need to pre-fault the VSID */ 1934 PMAP_LOCK(pm); 1935 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1936 PMAP_UNLOCK(pm); 1937 } else { 1938 slbv = slb->slbv; 1939 } 1940 1941 /* Mark segment no-execute */ 1942 slbv |= SLBV_N; 1943 #else 1944 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1945 1946 /* Mark segment no-execute */ 1947 slbv |= SR_N; 1948 #endif 1949 1950 /* If we have already set this VSID, we can just return */ 1951 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1952 return (0); 1953 1954 __asm __volatile("isync"); 1955 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1956 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1957 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1958 #ifdef __powerpc64__ 1959 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1960 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1961 #else 1962 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1963 #endif 1964 1965 return (0); 1966 } 1967 1968 /* 1969 * Figure out where a given kernel pointer (usually in a fault) points 1970 * to from the VM's perspective, potentially remapping into userland's 1971 * address space. 1972 */ 1973 static int 1974 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1975 vm_offset_t *decoded_addr) 1976 { 1977 vm_offset_t user_sr; 1978 1979 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1980 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1981 addr &= ADDR_PIDX | ADDR_POFF; 1982 addr |= user_sr << ADDR_SR_SHFT; 1983 *decoded_addr = addr; 1984 *is_user = 1; 1985 } else { 1986 *decoded_addr = addr; 1987 *is_user = 0; 1988 } 1989 1990 return (0); 1991 } 1992 1993 /* 1994 * Map a range of physical addresses into kernel virtual address space. 1995 * 1996 * The value passed in *virt is a suggested virtual address for the mapping. 1997 * Architectures which can support a direct-mapped physical to virtual region 1998 * can return the appropriate address within that region, leaving '*virt' 1999 * unchanged. Other architectures should map the pages starting at '*virt' and 2000 * update '*virt' with the first usable address after the mapped region. 2001 */ 2002 vm_offset_t 2003 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2004 vm_paddr_t pa_end, int prot) 2005 { 2006 vm_offset_t sva, va; 2007 2008 if (hw_direct_map) { 2009 /* 2010 * Check if every page in the region is covered by the direct 2011 * map. The direct map covers all of physical memory. Use 2012 * moea64_calc_wimg() as a shortcut to see if the page is in 2013 * physical memory as a way to see if the direct map covers it. 2014 */ 2015 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2016 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2017 break; 2018 if (va == pa_end) 2019 return (PHYS_TO_DMAP(pa_start)); 2020 } 2021 sva = *virt; 2022 va = sva; 2023 /* XXX respect prot argument */ 2024 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2025 moea64_kenter(mmu, va, pa_start); 2026 *virt = va; 2027 2028 return (sva); 2029 } 2030 2031 /* 2032 * Returns true if the pmap's pv is one of the first 2033 * 16 pvs linked to from this page. This count may 2034 * be changed upwards or downwards in the future; it 2035 * is only necessary that true be returned for a small 2036 * subset of pmaps for proper page aging. 2037 */ 2038 boolean_t 2039 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2040 { 2041 int loops; 2042 struct pvo_entry *pvo; 2043 boolean_t rv; 2044 2045 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2046 ("moea64_page_exists_quick: page %p is not managed", m)); 2047 loops = 0; 2048 rv = FALSE; 2049 PV_PAGE_LOCK(m); 2050 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2051 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2052 rv = TRUE; 2053 break; 2054 } 2055 if (++loops >= 16) 2056 break; 2057 } 2058 PV_PAGE_UNLOCK(m); 2059 return (rv); 2060 } 2061 2062 void 2063 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2064 { 2065 2066 m->md.mdpg_attrs = 0; 2067 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2068 LIST_INIT(&m->md.mdpg_pvoh); 2069 } 2070 2071 /* 2072 * Return the number of managed mappings to the given physical page 2073 * that are wired. 2074 */ 2075 int 2076 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2077 { 2078 struct pvo_entry *pvo; 2079 int count; 2080 2081 count = 0; 2082 if ((m->oflags & VPO_UNMANAGED) != 0) 2083 return (count); 2084 PV_PAGE_LOCK(m); 2085 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2086 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2087 count++; 2088 PV_PAGE_UNLOCK(m); 2089 return (count); 2090 } 2091 2092 static uintptr_t moea64_vsidcontext; 2093 2094 uintptr_t 2095 moea64_get_unique_vsid(void) { 2096 u_int entropy; 2097 register_t hash; 2098 uint32_t mask; 2099 int i; 2100 2101 entropy = 0; 2102 __asm __volatile("mftb %0" : "=r"(entropy)); 2103 2104 mtx_lock(&moea64_slb_mutex); 2105 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2106 u_int n; 2107 2108 /* 2109 * Create a new value by mutiplying by a prime and adding in 2110 * entropy from the timebase register. This is to make the 2111 * VSID more random so that the PT hash function collides 2112 * less often. (Note that the prime casues gcc to do shifts 2113 * instead of a multiply.) 2114 */ 2115 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2116 hash = moea64_vsidcontext & (NVSIDS - 1); 2117 if (hash == 0) /* 0 is special, avoid it */ 2118 continue; 2119 n = hash >> 5; 2120 mask = 1 << (hash & (VSID_NBPW - 1)); 2121 hash = (moea64_vsidcontext & VSID_HASHMASK); 2122 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2123 /* anything free in this bucket? */ 2124 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2125 entropy = (moea64_vsidcontext >> 20); 2126 continue; 2127 } 2128 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2129 mask = 1 << i; 2130 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2131 hash |= i; 2132 } 2133 if (hash == VSID_VRMA) /* also special, avoid this too */ 2134 continue; 2135 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2136 ("Allocating in-use VSID %#zx\n", hash)); 2137 moea64_vsid_bitmap[n] |= mask; 2138 mtx_unlock(&moea64_slb_mutex); 2139 return (hash); 2140 } 2141 2142 mtx_unlock(&moea64_slb_mutex); 2143 panic("%s: out of segments",__func__); 2144 } 2145 2146 #ifdef __powerpc64__ 2147 void 2148 moea64_pinit(mmu_t mmu, pmap_t pmap) 2149 { 2150 2151 RB_INIT(&pmap->pmap_pvo); 2152 2153 pmap->pm_slb_tree_root = slb_alloc_tree(); 2154 pmap->pm_slb = slb_alloc_user_cache(); 2155 pmap->pm_slb_len = 0; 2156 } 2157 #else 2158 void 2159 moea64_pinit(mmu_t mmu, pmap_t pmap) 2160 { 2161 int i; 2162 uint32_t hash; 2163 2164 RB_INIT(&pmap->pmap_pvo); 2165 2166 if (pmap_bootstrapped) 2167 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2168 (vm_offset_t)pmap); 2169 else 2170 pmap->pmap_phys = pmap; 2171 2172 /* 2173 * Allocate some segment registers for this pmap. 2174 */ 2175 hash = moea64_get_unique_vsid(); 2176 2177 for (i = 0; i < 16; i++) 2178 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2179 2180 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2181 } 2182 #endif 2183 2184 /* 2185 * Initialize the pmap associated with process 0. 2186 */ 2187 void 2188 moea64_pinit0(mmu_t mmu, pmap_t pm) 2189 { 2190 2191 PMAP_LOCK_INIT(pm); 2192 moea64_pinit(mmu, pm); 2193 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2194 } 2195 2196 /* 2197 * Set the physical protection on the specified range of this map as requested. 2198 */ 2199 static void 2200 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2201 { 2202 struct vm_page *pg; 2203 vm_prot_t oldprot; 2204 int32_t refchg; 2205 2206 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2207 2208 /* 2209 * Change the protection of the page. 2210 */ 2211 oldprot = pvo->pvo_pte.prot; 2212 pvo->pvo_pte.prot = prot; 2213 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2214 2215 /* 2216 * If the PVO is in the page table, update mapping 2217 */ 2218 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2219 if (refchg < 0) 2220 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2221 2222 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2223 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2224 if ((pg->oflags & VPO_UNMANAGED) == 0) 2225 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2226 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2227 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2228 } 2229 2230 /* 2231 * Update vm about the REF/CHG bits if the page is managed and we have 2232 * removed write access. 2233 */ 2234 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2235 (oldprot & VM_PROT_WRITE)) { 2236 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2237 if (refchg & LPTE_CHG) 2238 vm_page_dirty(pg); 2239 if (refchg & LPTE_REF) 2240 vm_page_aflag_set(pg, PGA_REFERENCED); 2241 } 2242 } 2243 2244 void 2245 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2246 vm_prot_t prot) 2247 { 2248 struct pvo_entry *pvo, *tpvo, key; 2249 2250 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2251 sva, eva, prot); 2252 2253 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2254 ("moea64_protect: non current pmap")); 2255 2256 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2257 moea64_remove(mmu, pm, sva, eva); 2258 return; 2259 } 2260 2261 PMAP_LOCK(pm); 2262 key.pvo_vaddr = sva; 2263 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2264 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2265 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2266 moea64_pvo_protect(mmu, pm, pvo, prot); 2267 } 2268 PMAP_UNLOCK(pm); 2269 } 2270 2271 /* 2272 * Map a list of wired pages into kernel virtual address space. This is 2273 * intended for temporary mappings which do not need page modification or 2274 * references recorded. Existing mappings in the region are overwritten. 2275 */ 2276 void 2277 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2278 { 2279 while (count-- > 0) { 2280 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2281 va += PAGE_SIZE; 2282 m++; 2283 } 2284 } 2285 2286 /* 2287 * Remove page mappings from kernel virtual address space. Intended for 2288 * temporary mappings entered by moea64_qenter. 2289 */ 2290 void 2291 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2292 { 2293 while (count-- > 0) { 2294 moea64_kremove(mmu, va); 2295 va += PAGE_SIZE; 2296 } 2297 } 2298 2299 void 2300 moea64_release_vsid(uint64_t vsid) 2301 { 2302 int idx, mask; 2303 2304 mtx_lock(&moea64_slb_mutex); 2305 idx = vsid & (NVSIDS-1); 2306 mask = 1 << (idx % VSID_NBPW); 2307 idx /= VSID_NBPW; 2308 KASSERT(moea64_vsid_bitmap[idx] & mask, 2309 ("Freeing unallocated VSID %#jx", vsid)); 2310 moea64_vsid_bitmap[idx] &= ~mask; 2311 mtx_unlock(&moea64_slb_mutex); 2312 } 2313 2314 2315 void 2316 moea64_release(mmu_t mmu, pmap_t pmap) 2317 { 2318 2319 /* 2320 * Free segment registers' VSIDs 2321 */ 2322 #ifdef __powerpc64__ 2323 slb_free_tree(pmap); 2324 slb_free_user_cache(pmap->pm_slb); 2325 #else 2326 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2327 2328 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2329 #endif 2330 } 2331 2332 /* 2333 * Remove all pages mapped by the specified pmap 2334 */ 2335 void 2336 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2337 { 2338 struct pvo_entry *pvo, *tpvo; 2339 struct pvo_tree tofree; 2340 2341 RB_INIT(&tofree); 2342 2343 PMAP_LOCK(pm); 2344 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2345 if (pvo->pvo_vaddr & PVO_WIRED) 2346 continue; 2347 2348 /* 2349 * For locking reasons, remove this from the page table and 2350 * pmap, but save delinking from the vm_page for a second 2351 * pass 2352 */ 2353 moea64_pvo_remove_from_pmap(mmu, pvo); 2354 RB_INSERT(pvo_tree, &tofree, pvo); 2355 } 2356 PMAP_UNLOCK(pm); 2357 2358 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2359 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2360 moea64_pvo_remove_from_page(mmu, pvo); 2361 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2362 RB_REMOVE(pvo_tree, &tofree, pvo); 2363 free_pvo_entry(pvo); 2364 } 2365 } 2366 2367 /* 2368 * Remove the given range of addresses from the specified map. 2369 */ 2370 void 2371 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2372 { 2373 struct pvo_entry *pvo, *tpvo, key; 2374 struct pvo_tree tofree; 2375 2376 /* 2377 * Perform an unsynchronized read. This is, however, safe. 2378 */ 2379 if (pm->pm_stats.resident_count == 0) 2380 return; 2381 2382 key.pvo_vaddr = sva; 2383 2384 RB_INIT(&tofree); 2385 2386 PMAP_LOCK(pm); 2387 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2388 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2389 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2390 2391 /* 2392 * For locking reasons, remove this from the page table and 2393 * pmap, but save delinking from the vm_page for a second 2394 * pass 2395 */ 2396 moea64_pvo_remove_from_pmap(mmu, pvo); 2397 RB_INSERT(pvo_tree, &tofree, pvo); 2398 } 2399 PMAP_UNLOCK(pm); 2400 2401 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2402 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2403 moea64_pvo_remove_from_page(mmu, pvo); 2404 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2405 RB_REMOVE(pvo_tree, &tofree, pvo); 2406 free_pvo_entry(pvo); 2407 } 2408 } 2409 2410 /* 2411 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2412 * will reflect changes in pte's back to the vm_page. 2413 */ 2414 void 2415 moea64_remove_all(mmu_t mmu, vm_page_t m) 2416 { 2417 struct pvo_entry *pvo, *next_pvo; 2418 struct pvo_head freequeue; 2419 int wasdead; 2420 pmap_t pmap; 2421 2422 LIST_INIT(&freequeue); 2423 2424 PV_PAGE_LOCK(m); 2425 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2426 pmap = pvo->pvo_pmap; 2427 PMAP_LOCK(pmap); 2428 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2429 if (!wasdead) 2430 moea64_pvo_remove_from_pmap(mmu, pvo); 2431 moea64_pvo_remove_from_page(mmu, pvo); 2432 if (!wasdead) 2433 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2434 PMAP_UNLOCK(pmap); 2435 2436 } 2437 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2438 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2439 PV_PAGE_UNLOCK(m); 2440 2441 /* Clean up UMA allocations */ 2442 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2443 free_pvo_entry(pvo); 2444 } 2445 2446 /* 2447 * Allocate a physical page of memory directly from the phys_avail map. 2448 * Can only be called from moea64_bootstrap before avail start and end are 2449 * calculated. 2450 */ 2451 vm_offset_t 2452 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2453 { 2454 vm_offset_t s, e; 2455 int i, j; 2456 2457 size = round_page(size); 2458 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2459 if (align != 0) 2460 s = roundup2(phys_avail[i], align); 2461 else 2462 s = phys_avail[i]; 2463 e = s + size; 2464 2465 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2466 continue; 2467 2468 if (s + size > platform_real_maxaddr()) 2469 continue; 2470 2471 if (s == phys_avail[i]) { 2472 phys_avail[i] += size; 2473 } else if (e == phys_avail[i + 1]) { 2474 phys_avail[i + 1] -= size; 2475 } else { 2476 for (j = phys_avail_count * 2; j > i; j -= 2) { 2477 phys_avail[j] = phys_avail[j - 2]; 2478 phys_avail[j + 1] = phys_avail[j - 1]; 2479 } 2480 2481 phys_avail[i + 3] = phys_avail[i + 1]; 2482 phys_avail[i + 1] = s; 2483 phys_avail[i + 2] = e; 2484 phys_avail_count++; 2485 } 2486 2487 return (s); 2488 } 2489 panic("moea64_bootstrap_alloc: could not allocate memory"); 2490 } 2491 2492 static int 2493 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2494 { 2495 int first, err; 2496 2497 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2498 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2499 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2500 2501 moea64_pvo_enter_calls++; 2502 2503 /* 2504 * Add to pmap list 2505 */ 2506 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2507 2508 /* 2509 * Remember if the list was empty and therefore will be the first 2510 * item. 2511 */ 2512 if (pvo_head != NULL) { 2513 if (LIST_FIRST(pvo_head) == NULL) 2514 first = 1; 2515 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2516 } 2517 2518 if (pvo->pvo_vaddr & PVO_WIRED) 2519 pvo->pvo_pmap->pm_stats.wired_count++; 2520 pvo->pvo_pmap->pm_stats.resident_count++; 2521 2522 /* 2523 * Insert it into the hardware page table 2524 */ 2525 err = MOEA64_PTE_INSERT(mmu, pvo); 2526 if (err != 0) { 2527 panic("moea64_pvo_enter: overflow"); 2528 } 2529 2530 moea64_pvo_entries++; 2531 2532 if (pvo->pvo_pmap == kernel_pmap) 2533 isync(); 2534 2535 #ifdef __powerpc64__ 2536 /* 2537 * Make sure all our bootstrap mappings are in the SLB as soon 2538 * as virtual memory is switched on. 2539 */ 2540 if (!pmap_bootstrapped) 2541 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2542 pvo->pvo_vaddr & PVO_LARGE); 2543 #endif 2544 2545 return (first ? ENOENT : 0); 2546 } 2547 2548 static void 2549 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2550 { 2551 struct vm_page *pg; 2552 int32_t refchg; 2553 2554 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2555 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2556 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2557 2558 /* 2559 * If there is an active pte entry, we need to deactivate it 2560 */ 2561 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2562 if (refchg < 0) { 2563 /* 2564 * If it was evicted from the page table, be pessimistic and 2565 * dirty the page. 2566 */ 2567 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2568 refchg = LPTE_CHG; 2569 else 2570 refchg = 0; 2571 } 2572 2573 /* 2574 * Update our statistics. 2575 */ 2576 pvo->pvo_pmap->pm_stats.resident_count--; 2577 if (pvo->pvo_vaddr & PVO_WIRED) 2578 pvo->pvo_pmap->pm_stats.wired_count--; 2579 2580 /* 2581 * Remove this PVO from the pmap list. 2582 */ 2583 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2584 2585 /* 2586 * Mark this for the next sweep 2587 */ 2588 pvo->pvo_vaddr |= PVO_DEAD; 2589 2590 /* Send RC bits to VM */ 2591 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2592 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2593 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2594 if (pg != NULL) { 2595 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2596 if (refchg & LPTE_CHG) 2597 vm_page_dirty(pg); 2598 if (refchg & LPTE_REF) 2599 vm_page_aflag_set(pg, PGA_REFERENCED); 2600 } 2601 } 2602 } 2603 2604 static void 2605 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2606 { 2607 struct vm_page *pg; 2608 2609 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2610 2611 /* Use NULL pmaps as a sentinel for races in page deletion */ 2612 if (pvo->pvo_pmap == NULL) 2613 return; 2614 pvo->pvo_pmap = NULL; 2615 2616 /* 2617 * Update vm about page writeability/executability if managed 2618 */ 2619 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2620 if (pvo->pvo_vaddr & PVO_MANAGED) { 2621 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2622 2623 if (pg != NULL) { 2624 LIST_REMOVE(pvo, pvo_vlink); 2625 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2626 vm_page_aflag_clear(pg, 2627 PGA_WRITEABLE | PGA_EXECUTABLE); 2628 } 2629 } 2630 2631 moea64_pvo_entries--; 2632 moea64_pvo_remove_calls++; 2633 } 2634 2635 static struct pvo_entry * 2636 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2637 { 2638 struct pvo_entry key; 2639 2640 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2641 2642 key.pvo_vaddr = va & ~ADDR_POFF; 2643 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2644 } 2645 2646 static boolean_t 2647 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2648 { 2649 struct pvo_entry *pvo; 2650 int64_t ret; 2651 boolean_t rv; 2652 2653 /* 2654 * See if this bit is stored in the page already. 2655 */ 2656 if (m->md.mdpg_attrs & ptebit) 2657 return (TRUE); 2658 2659 /* 2660 * Examine each PTE. Sync so that any pending REF/CHG bits are 2661 * flushed to the PTEs. 2662 */ 2663 rv = FALSE; 2664 powerpc_sync(); 2665 PV_PAGE_LOCK(m); 2666 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2667 ret = 0; 2668 2669 /* 2670 * See if this pvo has a valid PTE. if so, fetch the 2671 * REF/CHG bits from the valid PTE. If the appropriate 2672 * ptebit is set, return success. 2673 */ 2674 PMAP_LOCK(pvo->pvo_pmap); 2675 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2676 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2677 PMAP_UNLOCK(pvo->pvo_pmap); 2678 2679 if (ret > 0) { 2680 atomic_set_32(&m->md.mdpg_attrs, 2681 ret & (LPTE_CHG | LPTE_REF)); 2682 if (ret & ptebit) { 2683 rv = TRUE; 2684 break; 2685 } 2686 } 2687 } 2688 PV_PAGE_UNLOCK(m); 2689 2690 return (rv); 2691 } 2692 2693 static u_int 2694 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2695 { 2696 u_int count; 2697 struct pvo_entry *pvo; 2698 int64_t ret; 2699 2700 /* 2701 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2702 * we can reset the right ones). 2703 */ 2704 powerpc_sync(); 2705 2706 /* 2707 * For each pvo entry, clear the pte's ptebit. 2708 */ 2709 count = 0; 2710 PV_PAGE_LOCK(m); 2711 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2712 ret = 0; 2713 2714 PMAP_LOCK(pvo->pvo_pmap); 2715 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2716 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2717 PMAP_UNLOCK(pvo->pvo_pmap); 2718 2719 if (ret > 0 && (ret & ptebit)) 2720 count++; 2721 } 2722 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2723 PV_PAGE_UNLOCK(m); 2724 2725 return (count); 2726 } 2727 2728 boolean_t 2729 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2730 { 2731 struct pvo_entry *pvo, key; 2732 vm_offset_t ppa; 2733 int error = 0; 2734 2735 if (hw_direct_map && mem_valid(pa, size) == 0) 2736 return (0); 2737 2738 PMAP_LOCK(kernel_pmap); 2739 ppa = pa & ~ADDR_POFF; 2740 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2741 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2742 ppa < pa + size; ppa += PAGE_SIZE, 2743 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2744 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2745 error = EFAULT; 2746 break; 2747 } 2748 } 2749 PMAP_UNLOCK(kernel_pmap); 2750 2751 return (error); 2752 } 2753 2754 /* 2755 * Map a set of physical memory pages into the kernel virtual 2756 * address space. Return a pointer to where it is mapped. This 2757 * routine is intended to be used for mapping device memory, 2758 * NOT real memory. 2759 */ 2760 void * 2761 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2762 { 2763 vm_offset_t va, tmpva, ppa, offset; 2764 2765 ppa = trunc_page(pa); 2766 offset = pa & PAGE_MASK; 2767 size = roundup2(offset + size, PAGE_SIZE); 2768 2769 va = kva_alloc(size); 2770 2771 if (!va) 2772 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2773 2774 for (tmpva = va; size > 0;) { 2775 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2776 size -= PAGE_SIZE; 2777 tmpva += PAGE_SIZE; 2778 ppa += PAGE_SIZE; 2779 } 2780 2781 return ((void *)(va + offset)); 2782 } 2783 2784 void * 2785 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2786 { 2787 2788 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2789 } 2790 2791 void 2792 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2793 { 2794 vm_offset_t base, offset; 2795 2796 base = trunc_page(va); 2797 offset = va & PAGE_MASK; 2798 size = roundup2(offset + size, PAGE_SIZE); 2799 2800 kva_free(base, size); 2801 } 2802 2803 void 2804 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2805 { 2806 struct pvo_entry *pvo; 2807 vm_offset_t lim; 2808 vm_paddr_t pa; 2809 vm_size_t len; 2810 2811 PMAP_LOCK(pm); 2812 while (sz > 0) { 2813 lim = round_page(va+1); 2814 len = MIN(lim - va, sz); 2815 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2816 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2817 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2818 moea64_syncicache(mmu, pm, va, pa, len); 2819 } 2820 va += len; 2821 sz -= len; 2822 } 2823 PMAP_UNLOCK(pm); 2824 } 2825 2826 void 2827 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2828 { 2829 2830 *va = (void *)(uintptr_t)pa; 2831 } 2832 2833 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2834 2835 void 2836 moea64_scan_init(mmu_t mmu) 2837 { 2838 struct pvo_entry *pvo; 2839 vm_offset_t va; 2840 int i; 2841 2842 if (!do_minidump) { 2843 /* Initialize phys. segments for dumpsys(). */ 2844 memset(&dump_map, 0, sizeof(dump_map)); 2845 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2846 for (i = 0; i < pregions_sz; i++) { 2847 dump_map[i].pa_start = pregions[i].mr_start; 2848 dump_map[i].pa_size = pregions[i].mr_size; 2849 } 2850 return; 2851 } 2852 2853 /* Virtual segments for minidumps: */ 2854 memset(&dump_map, 0, sizeof(dump_map)); 2855 2856 /* 1st: kernel .data and .bss. */ 2857 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2858 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2859 dump_map[0].pa_start; 2860 2861 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2862 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2863 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2864 2865 /* 3rd: kernel VM. */ 2866 va = dump_map[1].pa_start + dump_map[1].pa_size; 2867 /* Find start of next chunk (from va). */ 2868 while (va < virtual_end) { 2869 /* Don't dump the buffer cache. */ 2870 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2871 va = kmi.buffer_eva; 2872 continue; 2873 } 2874 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2875 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2876 break; 2877 va += PAGE_SIZE; 2878 } 2879 if (va < virtual_end) { 2880 dump_map[2].pa_start = va; 2881 va += PAGE_SIZE; 2882 /* Find last page in chunk. */ 2883 while (va < virtual_end) { 2884 /* Don't run into the buffer cache. */ 2885 if (va == kmi.buffer_sva) 2886 break; 2887 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2888 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2889 break; 2890 va += PAGE_SIZE; 2891 } 2892 dump_map[2].pa_size = va - dump_map[2].pa_start; 2893 } 2894 } 2895 2896