1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_compat.h" 49 #include "opt_kstack_pages.h" 50 51 #include <sys/param.h> 52 #include <sys/kernel.h> 53 #include <sys/conf.h> 54 #include <sys/queue.h> 55 #include <sys/cpuset.h> 56 #include <sys/kerneldump.h> 57 #include <sys/ktr.h> 58 #include <sys/lock.h> 59 #include <sys/msgbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/proc.h> 63 #include <sys/rwlock.h> 64 #include <sys/sched.h> 65 #include <sys/sysctl.h> 66 #include <sys/systm.h> 67 #include <sys/vmmeter.h> 68 #include <sys/smp.h> 69 70 #include <sys/kdb.h> 71 72 #include <dev/ofw/openfirm.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_kern.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 124 125 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 126 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 127 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 128 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 129 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 130 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 131 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 132 133 struct ofw_map { 134 cell_t om_va; 135 cell_t om_len; 136 uint64_t om_pa; 137 cell_t om_mode; 138 }; 139 140 extern unsigned char _etext[]; 141 extern unsigned char _end[]; 142 143 /* 144 * Map of physical memory regions. 145 */ 146 static struct mem_region *regions; 147 static struct mem_region *pregions; 148 static u_int phys_avail_count; 149 static int regions_sz, pregions_sz; 150 151 extern void bs_remap_earlyboot(void); 152 153 /* 154 * Lock for the SLB tables. 155 */ 156 struct mtx moea64_slb_mutex; 157 158 /* 159 * PTEG data. 160 */ 161 u_int moea64_pteg_count; 162 u_int moea64_pteg_mask; 163 164 /* 165 * PVO data. 166 */ 167 168 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 169 170 static struct pvo_entry *moea64_bpvo_pool; 171 static int moea64_bpvo_pool_index = 0; 172 static int moea64_bpvo_pool_size = 327680; 173 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 174 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 175 &moea64_bpvo_pool_index, 0, ""); 176 177 #define VSID_NBPW (sizeof(u_int32_t) * 8) 178 #ifdef __powerpc64__ 179 #define NVSIDS (NPMAPS * 16) 180 #define VSID_HASHMASK 0xffffffffUL 181 #else 182 #define NVSIDS NPMAPS 183 #define VSID_HASHMASK 0xfffffUL 184 #endif 185 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 186 187 static boolean_t moea64_initialized = FALSE; 188 189 /* 190 * Statistics. 191 */ 192 u_int moea64_pte_valid = 0; 193 u_int moea64_pte_overflow = 0; 194 u_int moea64_pvo_entries = 0; 195 u_int moea64_pvo_enter_calls = 0; 196 u_int moea64_pvo_remove_calls = 0; 197 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 198 &moea64_pte_valid, 0, ""); 199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 200 &moea64_pte_overflow, 0, ""); 201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 202 &moea64_pvo_entries, 0, ""); 203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 204 &moea64_pvo_enter_calls, 0, ""); 205 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 206 &moea64_pvo_remove_calls, 0, ""); 207 208 vm_offset_t moea64_scratchpage_va[2]; 209 struct pvo_entry *moea64_scratchpage_pvo[2]; 210 struct mtx moea64_scratchpage_mtx; 211 212 uint64_t moea64_large_page_mask = 0; 213 uint64_t moea64_large_page_size = 0; 214 int moea64_large_page_shift = 0; 215 216 /* 217 * PVO calls. 218 */ 219 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 220 struct pvo_head *pvo_head); 221 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 222 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 223 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 224 225 /* 226 * Utility routines. 227 */ 228 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 229 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 230 static void moea64_kremove(mmu_t, vm_offset_t); 231 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 232 vm_paddr_t pa, vm_size_t sz); 233 static void moea64_pmap_init_qpages(void); 234 235 /* 236 * Kernel MMU interface 237 */ 238 void moea64_clear_modify(mmu_t, vm_page_t); 239 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 240 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 241 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 242 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 243 u_int flags, int8_t psind); 244 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 245 vm_prot_t); 246 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 247 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 248 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 249 void moea64_init(mmu_t); 250 boolean_t moea64_is_modified(mmu_t, vm_page_t); 251 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 252 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 253 int moea64_ts_referenced(mmu_t, vm_page_t); 254 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 255 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 256 void moea64_page_init(mmu_t, vm_page_t); 257 int moea64_page_wired_mappings(mmu_t, vm_page_t); 258 void moea64_pinit(mmu_t, pmap_t); 259 void moea64_pinit0(mmu_t, pmap_t); 260 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 261 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 262 void moea64_qremove(mmu_t, vm_offset_t, int); 263 void moea64_release(mmu_t, pmap_t); 264 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 265 void moea64_remove_pages(mmu_t, pmap_t); 266 void moea64_remove_all(mmu_t, vm_page_t); 267 void moea64_remove_write(mmu_t, vm_page_t); 268 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 269 void moea64_zero_page(mmu_t, vm_page_t); 270 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 271 void moea64_activate(mmu_t, struct thread *); 272 void moea64_deactivate(mmu_t, struct thread *); 273 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 274 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 275 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 276 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 277 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 278 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 279 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 280 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 281 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 282 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 283 void **va); 284 void moea64_scan_init(mmu_t mmu); 285 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 286 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 287 288 static mmu_method_t moea64_methods[] = { 289 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 290 MMUMETHOD(mmu_copy_page, moea64_copy_page), 291 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 292 MMUMETHOD(mmu_enter, moea64_enter), 293 MMUMETHOD(mmu_enter_object, moea64_enter_object), 294 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 295 MMUMETHOD(mmu_extract, moea64_extract), 296 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 297 MMUMETHOD(mmu_init, moea64_init), 298 MMUMETHOD(mmu_is_modified, moea64_is_modified), 299 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 300 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 301 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 302 MMUMETHOD(mmu_map, moea64_map), 303 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 304 MMUMETHOD(mmu_page_init, moea64_page_init), 305 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 306 MMUMETHOD(mmu_pinit, moea64_pinit), 307 MMUMETHOD(mmu_pinit0, moea64_pinit0), 308 MMUMETHOD(mmu_protect, moea64_protect), 309 MMUMETHOD(mmu_qenter, moea64_qenter), 310 MMUMETHOD(mmu_qremove, moea64_qremove), 311 MMUMETHOD(mmu_release, moea64_release), 312 MMUMETHOD(mmu_remove, moea64_remove), 313 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 314 MMUMETHOD(mmu_remove_all, moea64_remove_all), 315 MMUMETHOD(mmu_remove_write, moea64_remove_write), 316 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 317 MMUMETHOD(mmu_unwire, moea64_unwire), 318 MMUMETHOD(mmu_zero_page, moea64_zero_page), 319 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 320 MMUMETHOD(mmu_activate, moea64_activate), 321 MMUMETHOD(mmu_deactivate, moea64_deactivate), 322 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 323 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 324 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 325 326 /* Internal interfaces */ 327 MMUMETHOD(mmu_mapdev, moea64_mapdev), 328 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 329 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 330 MMUMETHOD(mmu_kextract, moea64_kextract), 331 MMUMETHOD(mmu_kenter, moea64_kenter), 332 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 333 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 334 MMUMETHOD(mmu_scan_init, moea64_scan_init), 335 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 336 337 { 0, 0 } 338 }; 339 340 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 341 342 static struct pvo_head * 343 vm_page_to_pvoh(vm_page_t m) 344 { 345 346 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 347 return (&m->md.mdpg_pvoh); 348 } 349 350 static struct pvo_entry * 351 alloc_pvo_entry(int bootstrap) 352 { 353 struct pvo_entry *pvo; 354 355 if (!moea64_initialized || bootstrap) { 356 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 357 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 358 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 359 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 360 } 361 pvo = &moea64_bpvo_pool[ 362 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 363 bzero(pvo, sizeof(*pvo)); 364 pvo->pvo_vaddr = PVO_BOOTSTRAP; 365 } else { 366 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 367 bzero(pvo, sizeof(*pvo)); 368 } 369 370 return (pvo); 371 } 372 373 374 static void 375 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 376 { 377 uint64_t vsid; 378 uint64_t hash; 379 int shift; 380 381 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 382 383 pvo->pvo_pmap = pmap; 384 va &= ~ADDR_POFF; 385 pvo->pvo_vaddr |= va; 386 vsid = va_to_vsid(pmap, va); 387 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 388 | (vsid << 16); 389 390 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 391 ADDR_PIDX_SHFT; 392 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 393 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 394 } 395 396 static void 397 free_pvo_entry(struct pvo_entry *pvo) 398 { 399 400 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 401 uma_zfree(moea64_pvo_zone, pvo); 402 } 403 404 void 405 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 406 { 407 408 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 409 LPTE_AVPN_MASK; 410 lpte->pte_hi |= LPTE_VALID; 411 412 if (pvo->pvo_vaddr & PVO_LARGE) 413 lpte->pte_hi |= LPTE_BIG; 414 if (pvo->pvo_vaddr & PVO_WIRED) 415 lpte->pte_hi |= LPTE_WIRED; 416 if (pvo->pvo_vaddr & PVO_HID) 417 lpte->pte_hi |= LPTE_HID; 418 419 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 420 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 421 lpte->pte_lo |= LPTE_BW; 422 else 423 lpte->pte_lo |= LPTE_BR; 424 425 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 426 lpte->pte_lo |= LPTE_NOEXEC; 427 } 428 429 static __inline uint64_t 430 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 431 { 432 uint64_t pte_lo; 433 int i; 434 435 if (ma != VM_MEMATTR_DEFAULT) { 436 switch (ma) { 437 case VM_MEMATTR_UNCACHEABLE: 438 return (LPTE_I | LPTE_G); 439 case VM_MEMATTR_CACHEABLE: 440 return (LPTE_M); 441 case VM_MEMATTR_WRITE_COMBINING: 442 case VM_MEMATTR_WRITE_BACK: 443 case VM_MEMATTR_PREFETCHABLE: 444 return (LPTE_I); 445 case VM_MEMATTR_WRITE_THROUGH: 446 return (LPTE_W | LPTE_M); 447 } 448 } 449 450 /* 451 * Assume the page is cache inhibited and access is guarded unless 452 * it's in our available memory array. 453 */ 454 pte_lo = LPTE_I | LPTE_G; 455 for (i = 0; i < pregions_sz; i++) { 456 if ((pa >= pregions[i].mr_start) && 457 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 458 pte_lo &= ~(LPTE_I | LPTE_G); 459 pte_lo |= LPTE_M; 460 break; 461 } 462 } 463 464 return pte_lo; 465 } 466 467 /* 468 * Quick sort callout for comparing memory regions. 469 */ 470 static int om_cmp(const void *a, const void *b); 471 472 static int 473 om_cmp(const void *a, const void *b) 474 { 475 const struct ofw_map *mapa; 476 const struct ofw_map *mapb; 477 478 mapa = a; 479 mapb = b; 480 if (mapa->om_pa < mapb->om_pa) 481 return (-1); 482 else if (mapa->om_pa > mapb->om_pa) 483 return (1); 484 else 485 return (0); 486 } 487 488 static void 489 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 490 { 491 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 492 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 493 struct pvo_entry *pvo; 494 register_t msr; 495 vm_offset_t off; 496 vm_paddr_t pa_base; 497 int i, j; 498 499 bzero(translations, sz); 500 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 501 sizeof(acells)); 502 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 503 panic("moea64_bootstrap: can't get ofw translations"); 504 505 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 506 sz /= sizeof(cell_t); 507 for (i = 0, j = 0; i < sz; j++) { 508 translations[j].om_va = trans_cells[i++]; 509 translations[j].om_len = trans_cells[i++]; 510 translations[j].om_pa = trans_cells[i++]; 511 if (acells == 2) { 512 translations[j].om_pa <<= 32; 513 translations[j].om_pa |= trans_cells[i++]; 514 } 515 translations[j].om_mode = trans_cells[i++]; 516 } 517 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 518 i, sz)); 519 520 sz = j; 521 qsort(translations, sz, sizeof (*translations), om_cmp); 522 523 for (i = 0; i < sz; i++) { 524 pa_base = translations[i].om_pa; 525 #ifndef __powerpc64__ 526 if ((translations[i].om_pa >> 32) != 0) 527 panic("OFW translations above 32-bit boundary!"); 528 #endif 529 530 if (pa_base % PAGE_SIZE) 531 panic("OFW translation not page-aligned (phys)!"); 532 if (translations[i].om_va % PAGE_SIZE) 533 panic("OFW translation not page-aligned (virt)!"); 534 535 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 536 pa_base, translations[i].om_va, translations[i].om_len); 537 538 /* Now enter the pages for this mapping */ 539 540 DISABLE_TRANS(msr); 541 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 542 /* If this address is direct-mapped, skip remapping */ 543 if (hw_direct_map && translations[i].om_va == pa_base && 544 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 545 continue; 546 547 PMAP_LOCK(kernel_pmap); 548 pvo = moea64_pvo_find_va(kernel_pmap, 549 translations[i].om_va + off); 550 PMAP_UNLOCK(kernel_pmap); 551 if (pvo != NULL) 552 continue; 553 554 moea64_kenter(mmup, translations[i].om_va + off, 555 pa_base + off); 556 } 557 ENABLE_TRANS(msr); 558 } 559 } 560 561 #ifdef __powerpc64__ 562 static void 563 moea64_probe_large_page(void) 564 { 565 uint16_t pvr = mfpvr() >> 16; 566 567 switch (pvr) { 568 case IBM970: 569 case IBM970FX: 570 case IBM970MP: 571 powerpc_sync(); isync(); 572 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 573 powerpc_sync(); isync(); 574 575 /* FALLTHROUGH */ 576 default: 577 if (moea64_large_page_size == 0) { 578 moea64_large_page_size = 0x1000000; /* 16 MB */ 579 moea64_large_page_shift = 24; 580 } 581 } 582 583 moea64_large_page_mask = moea64_large_page_size - 1; 584 } 585 586 static void 587 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 588 { 589 struct slb *cache; 590 struct slb entry; 591 uint64_t esid, slbe; 592 uint64_t i; 593 594 cache = PCPU_GET(slb); 595 esid = va >> ADDR_SR_SHFT; 596 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 597 598 for (i = 0; i < 64; i++) { 599 if (cache[i].slbe == (slbe | i)) 600 return; 601 } 602 603 entry.slbe = slbe; 604 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 605 if (large) 606 entry.slbv |= SLBV_L; 607 608 slb_insert_kernel(entry.slbe, entry.slbv); 609 } 610 #endif 611 612 static void 613 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 614 vm_offset_t kernelend) 615 { 616 struct pvo_entry *pvo; 617 register_t msr; 618 vm_paddr_t pa; 619 vm_offset_t size, off; 620 uint64_t pte_lo; 621 int i; 622 623 if (moea64_large_page_size == 0) 624 hw_direct_map = 0; 625 626 DISABLE_TRANS(msr); 627 if (hw_direct_map) { 628 PMAP_LOCK(kernel_pmap); 629 for (i = 0; i < pregions_sz; i++) { 630 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 631 pregions[i].mr_size; pa += moea64_large_page_size) { 632 pte_lo = LPTE_M; 633 634 pvo = alloc_pvo_entry(1 /* bootstrap */); 635 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 636 init_pvo_entry(pvo, kernel_pmap, pa); 637 638 /* 639 * Set memory access as guarded if prefetch within 640 * the page could exit the available physmem area. 641 */ 642 if (pa & moea64_large_page_mask) { 643 pa &= moea64_large_page_mask; 644 pte_lo |= LPTE_G; 645 } 646 if (pa + moea64_large_page_size > 647 pregions[i].mr_start + pregions[i].mr_size) 648 pte_lo |= LPTE_G; 649 650 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 651 VM_PROT_EXECUTE; 652 pvo->pvo_pte.pa = pa | pte_lo; 653 moea64_pvo_enter(mmup, pvo, NULL); 654 } 655 } 656 PMAP_UNLOCK(kernel_pmap); 657 } else { 658 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 659 off = (vm_offset_t)(moea64_bpvo_pool); 660 for (pa = off; pa < off + size; pa += PAGE_SIZE) 661 moea64_kenter(mmup, pa, pa); 662 663 /* 664 * Map certain important things, like ourselves. 665 * 666 * NOTE: We do not map the exception vector space. That code is 667 * used only in real mode, and leaving it unmapped allows us to 668 * catch NULL pointer deferences, instead of making NULL a valid 669 * address. 670 */ 671 672 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 673 pa += PAGE_SIZE) 674 moea64_kenter(mmup, pa, pa); 675 } 676 ENABLE_TRANS(msr); 677 678 /* 679 * Allow user to override unmapped_buf_allowed for testing. 680 * XXXKIB Only direct map implementation was tested. 681 */ 682 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 683 &unmapped_buf_allowed)) 684 unmapped_buf_allowed = hw_direct_map; 685 } 686 687 void 688 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 689 { 690 int i, j; 691 vm_size_t physsz, hwphyssz; 692 693 #ifndef __powerpc64__ 694 /* We don't have a direct map since there is no BAT */ 695 hw_direct_map = 0; 696 697 /* Make sure battable is zero, since we have no BAT */ 698 for (i = 0; i < 16; i++) { 699 battable[i].batu = 0; 700 battable[i].batl = 0; 701 } 702 #else 703 moea64_probe_large_page(); 704 705 /* Use a direct map if we have large page support */ 706 if (moea64_large_page_size > 0) 707 hw_direct_map = 1; 708 else 709 hw_direct_map = 0; 710 #endif 711 712 /* Get physical memory regions from firmware */ 713 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 714 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 715 716 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 717 panic("moea64_bootstrap: phys_avail too small"); 718 719 phys_avail_count = 0; 720 physsz = 0; 721 hwphyssz = 0; 722 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 723 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 724 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 725 regions[i].mr_start, regions[i].mr_start + 726 regions[i].mr_size, regions[i].mr_size); 727 if (hwphyssz != 0 && 728 (physsz + regions[i].mr_size) >= hwphyssz) { 729 if (physsz < hwphyssz) { 730 phys_avail[j] = regions[i].mr_start; 731 phys_avail[j + 1] = regions[i].mr_start + 732 hwphyssz - physsz; 733 physsz = hwphyssz; 734 phys_avail_count++; 735 } 736 break; 737 } 738 phys_avail[j] = regions[i].mr_start; 739 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 740 phys_avail_count++; 741 physsz += regions[i].mr_size; 742 } 743 744 /* Check for overlap with the kernel and exception vectors */ 745 for (j = 0; j < 2*phys_avail_count; j+=2) { 746 if (phys_avail[j] < EXC_LAST) 747 phys_avail[j] += EXC_LAST; 748 749 if (kernelstart >= phys_avail[j] && 750 kernelstart < phys_avail[j+1]) { 751 if (kernelend < phys_avail[j+1]) { 752 phys_avail[2*phys_avail_count] = 753 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 754 phys_avail[2*phys_avail_count + 1] = 755 phys_avail[j+1]; 756 phys_avail_count++; 757 } 758 759 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 760 } 761 762 if (kernelend >= phys_avail[j] && 763 kernelend < phys_avail[j+1]) { 764 if (kernelstart > phys_avail[j]) { 765 phys_avail[2*phys_avail_count] = phys_avail[j]; 766 phys_avail[2*phys_avail_count + 1] = 767 kernelstart & ~PAGE_MASK; 768 phys_avail_count++; 769 } 770 771 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 772 } 773 } 774 775 physmem = btoc(physsz); 776 777 #ifdef PTEGCOUNT 778 moea64_pteg_count = PTEGCOUNT; 779 #else 780 moea64_pteg_count = 0x1000; 781 782 while (moea64_pteg_count < physmem) 783 moea64_pteg_count <<= 1; 784 785 moea64_pteg_count >>= 1; 786 #endif /* PTEGCOUNT */ 787 } 788 789 void 790 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 791 { 792 int i; 793 794 /* 795 * Set PTEG mask 796 */ 797 moea64_pteg_mask = moea64_pteg_count - 1; 798 799 /* 800 * Initialize SLB table lock and page locks 801 */ 802 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 803 for (i = 0; i < PV_LOCK_COUNT; i++) 804 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 805 806 /* 807 * Initialise the bootstrap pvo pool. 808 */ 809 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 810 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 811 moea64_bpvo_pool_index = 0; 812 813 /* 814 * Make sure kernel vsid is allocated as well as VSID 0. 815 */ 816 #ifndef __powerpc64__ 817 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 818 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 819 moea64_vsid_bitmap[0] |= 1; 820 #endif 821 822 /* 823 * Initialize the kernel pmap (which is statically allocated). 824 */ 825 #ifdef __powerpc64__ 826 for (i = 0; i < 64; i++) { 827 pcpup->pc_slb[i].slbv = 0; 828 pcpup->pc_slb[i].slbe = 0; 829 } 830 #else 831 for (i = 0; i < 16; i++) 832 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 833 #endif 834 835 kernel_pmap->pmap_phys = kernel_pmap; 836 CPU_FILL(&kernel_pmap->pm_active); 837 RB_INIT(&kernel_pmap->pmap_pvo); 838 839 PMAP_LOCK_INIT(kernel_pmap); 840 841 /* 842 * Now map in all the other buffers we allocated earlier 843 */ 844 845 moea64_setup_direct_map(mmup, kernelstart, kernelend); 846 } 847 848 void 849 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 850 { 851 ihandle_t mmui; 852 phandle_t chosen; 853 phandle_t mmu; 854 ssize_t sz; 855 int i; 856 vm_offset_t pa, va; 857 void *dpcpu; 858 859 /* 860 * Set up the Open Firmware pmap and add its mappings if not in real 861 * mode. 862 */ 863 864 chosen = OF_finddevice("/chosen"); 865 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 866 mmu = OF_instance_to_package(mmui); 867 if (mmu == -1 || 868 (sz = OF_getproplen(mmu, "translations")) == -1) 869 sz = 0; 870 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 871 panic("moea64_bootstrap: too many ofw translations"); 872 873 if (sz > 0) 874 moea64_add_ofw_mappings(mmup, mmu, sz); 875 } 876 877 /* 878 * Calculate the last available physical address. 879 */ 880 Maxmem = 0; 881 for (i = 0; phys_avail[i + 2] != 0; i += 2) 882 Maxmem = max(Maxmem, powerpc_btop(phys_avail[i + 1])); 883 884 /* 885 * Initialize MMU and remap early physical mappings 886 */ 887 MMU_CPU_BOOTSTRAP(mmup,0); 888 mtmsr(mfmsr() | PSL_DR | PSL_IR); 889 pmap_bootstrapped++; 890 bs_remap_earlyboot(); 891 892 /* 893 * Set the start and end of kva. 894 */ 895 virtual_avail = VM_MIN_KERNEL_ADDRESS; 896 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 897 898 /* 899 * Map the entire KVA range into the SLB. We must not fault there. 900 */ 901 #ifdef __powerpc64__ 902 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 903 moea64_bootstrap_slb_prefault(va, 0); 904 #endif 905 906 /* 907 * Figure out how far we can extend virtual_end into segment 16 908 * without running into existing mappings. Segment 16 is guaranteed 909 * to contain neither RAM nor devices (at least on Apple hardware), 910 * but will generally contain some OFW mappings we should not 911 * step on. 912 */ 913 914 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 915 PMAP_LOCK(kernel_pmap); 916 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 917 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 918 virtual_end += PAGE_SIZE; 919 PMAP_UNLOCK(kernel_pmap); 920 #endif 921 922 /* 923 * Allocate a kernel stack with a guard page for thread0 and map it 924 * into the kernel page map. 925 */ 926 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 927 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 928 virtual_avail = va + kstack_pages * PAGE_SIZE; 929 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 930 thread0.td_kstack = va; 931 thread0.td_kstack_pages = kstack_pages; 932 for (i = 0; i < kstack_pages; i++) { 933 moea64_kenter(mmup, va, pa); 934 pa += PAGE_SIZE; 935 va += PAGE_SIZE; 936 } 937 938 /* 939 * Allocate virtual address space for the message buffer. 940 */ 941 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 942 msgbufp = (struct msgbuf *)virtual_avail; 943 va = virtual_avail; 944 virtual_avail += round_page(msgbufsize); 945 while (va < virtual_avail) { 946 moea64_kenter(mmup, va, pa); 947 pa += PAGE_SIZE; 948 va += PAGE_SIZE; 949 } 950 951 /* 952 * Allocate virtual address space for the dynamic percpu area. 953 */ 954 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 955 dpcpu = (void *)virtual_avail; 956 va = virtual_avail; 957 virtual_avail += DPCPU_SIZE; 958 while (va < virtual_avail) { 959 moea64_kenter(mmup, va, pa); 960 pa += PAGE_SIZE; 961 va += PAGE_SIZE; 962 } 963 dpcpu_init(dpcpu, curcpu); 964 965 /* 966 * Allocate some things for page zeroing. We put this directly 967 * in the page table and use MOEA64_PTE_REPLACE to avoid any 968 * of the PVO book-keeping or other parts of the VM system 969 * from even knowing that this hack exists. 970 */ 971 972 if (!hw_direct_map) { 973 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 974 MTX_DEF); 975 for (i = 0; i < 2; i++) { 976 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 977 virtual_end -= PAGE_SIZE; 978 979 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 980 981 PMAP_LOCK(kernel_pmap); 982 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 983 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 984 PMAP_UNLOCK(kernel_pmap); 985 } 986 } 987 } 988 989 static void 990 moea64_pmap_init_qpages(void) 991 { 992 struct pcpu *pc; 993 int i; 994 995 if (hw_direct_map) 996 return; 997 998 CPU_FOREACH(i) { 999 pc = pcpu_find(i); 1000 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1001 if (pc->pc_qmap_addr == 0) 1002 panic("pmap_init_qpages: unable to allocate KVA"); 1003 PMAP_LOCK(kernel_pmap); 1004 pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1005 PMAP_UNLOCK(kernel_pmap); 1006 mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF); 1007 } 1008 } 1009 1010 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1011 1012 /* 1013 * Activate a user pmap. This mostly involves setting some non-CPU 1014 * state. 1015 */ 1016 void 1017 moea64_activate(mmu_t mmu, struct thread *td) 1018 { 1019 pmap_t pm; 1020 1021 pm = &td->td_proc->p_vmspace->vm_pmap; 1022 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1023 1024 #ifdef __powerpc64__ 1025 PCPU_SET(userslb, pm->pm_slb); 1026 __asm __volatile("slbmte %0, %1; isync" :: 1027 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1028 #else 1029 PCPU_SET(curpmap, pm->pmap_phys); 1030 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1031 #endif 1032 } 1033 1034 void 1035 moea64_deactivate(mmu_t mmu, struct thread *td) 1036 { 1037 pmap_t pm; 1038 1039 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1040 1041 pm = &td->td_proc->p_vmspace->vm_pmap; 1042 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1043 #ifdef __powerpc64__ 1044 PCPU_SET(userslb, NULL); 1045 #else 1046 PCPU_SET(curpmap, NULL); 1047 #endif 1048 } 1049 1050 void 1051 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1052 { 1053 struct pvo_entry key, *pvo; 1054 vm_page_t m; 1055 int64_t refchg; 1056 1057 key.pvo_vaddr = sva; 1058 PMAP_LOCK(pm); 1059 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1060 pvo != NULL && PVO_VADDR(pvo) < eva; 1061 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1062 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1063 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1064 pvo); 1065 pvo->pvo_vaddr &= ~PVO_WIRED; 1066 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1067 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1068 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1069 if (refchg < 0) 1070 refchg = LPTE_CHG; 1071 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1072 1073 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1074 if (refchg & LPTE_CHG) 1075 vm_page_dirty(m); 1076 if (refchg & LPTE_REF) 1077 vm_page_aflag_set(m, PGA_REFERENCED); 1078 } 1079 pm->pm_stats.wired_count--; 1080 } 1081 PMAP_UNLOCK(pm); 1082 } 1083 1084 /* 1085 * This goes through and sets the physical address of our 1086 * special scratch PTE to the PA we want to zero or copy. Because 1087 * of locking issues (this can get called in pvo_enter() by 1088 * the UMA allocator), we can't use most other utility functions here 1089 */ 1090 1091 static __inline 1092 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1093 1094 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1095 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1096 1097 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1098 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1099 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1100 MOEA64_PTE_INVALIDATE); 1101 isync(); 1102 } 1103 1104 void 1105 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1106 { 1107 vm_offset_t dst; 1108 vm_offset_t src; 1109 1110 dst = VM_PAGE_TO_PHYS(mdst); 1111 src = VM_PAGE_TO_PHYS(msrc); 1112 1113 if (hw_direct_map) { 1114 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1115 } else { 1116 mtx_lock(&moea64_scratchpage_mtx); 1117 1118 moea64_set_scratchpage_pa(mmu, 0, src); 1119 moea64_set_scratchpage_pa(mmu, 1, dst); 1120 1121 bcopy((void *)moea64_scratchpage_va[0], 1122 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1123 1124 mtx_unlock(&moea64_scratchpage_mtx); 1125 } 1126 } 1127 1128 static inline void 1129 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1130 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1131 { 1132 void *a_cp, *b_cp; 1133 vm_offset_t a_pg_offset, b_pg_offset; 1134 int cnt; 1135 1136 while (xfersize > 0) { 1137 a_pg_offset = a_offset & PAGE_MASK; 1138 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1139 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1140 a_pg_offset; 1141 b_pg_offset = b_offset & PAGE_MASK; 1142 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1143 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1144 b_pg_offset; 1145 bcopy(a_cp, b_cp, cnt); 1146 a_offset += cnt; 1147 b_offset += cnt; 1148 xfersize -= cnt; 1149 } 1150 } 1151 1152 static inline void 1153 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1154 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1155 { 1156 void *a_cp, *b_cp; 1157 vm_offset_t a_pg_offset, b_pg_offset; 1158 int cnt; 1159 1160 mtx_lock(&moea64_scratchpage_mtx); 1161 while (xfersize > 0) { 1162 a_pg_offset = a_offset & PAGE_MASK; 1163 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1164 moea64_set_scratchpage_pa(mmu, 0, 1165 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1166 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1167 b_pg_offset = b_offset & PAGE_MASK; 1168 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1169 moea64_set_scratchpage_pa(mmu, 1, 1170 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1171 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1172 bcopy(a_cp, b_cp, cnt); 1173 a_offset += cnt; 1174 b_offset += cnt; 1175 xfersize -= cnt; 1176 } 1177 mtx_unlock(&moea64_scratchpage_mtx); 1178 } 1179 1180 void 1181 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1182 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1183 { 1184 1185 if (hw_direct_map) { 1186 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1187 xfersize); 1188 } else { 1189 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1190 xfersize); 1191 } 1192 } 1193 1194 void 1195 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1196 { 1197 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1198 1199 if (size + off > PAGE_SIZE) 1200 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1201 1202 if (hw_direct_map) { 1203 bzero((caddr_t)pa + off, size); 1204 } else { 1205 mtx_lock(&moea64_scratchpage_mtx); 1206 moea64_set_scratchpage_pa(mmu, 0, pa); 1207 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1208 mtx_unlock(&moea64_scratchpage_mtx); 1209 } 1210 } 1211 1212 /* 1213 * Zero a page of physical memory by temporarily mapping it 1214 */ 1215 void 1216 moea64_zero_page(mmu_t mmu, vm_page_t m) 1217 { 1218 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1219 vm_offset_t va, off; 1220 1221 if (!hw_direct_map) { 1222 mtx_lock(&moea64_scratchpage_mtx); 1223 1224 moea64_set_scratchpage_pa(mmu, 0, pa); 1225 va = moea64_scratchpage_va[0]; 1226 } else { 1227 va = pa; 1228 } 1229 1230 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1231 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1232 1233 if (!hw_direct_map) 1234 mtx_unlock(&moea64_scratchpage_mtx); 1235 } 1236 1237 vm_offset_t 1238 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1239 { 1240 struct pvo_entry *pvo; 1241 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1242 1243 if (hw_direct_map) 1244 return (pa); 1245 1246 /* 1247 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1248 * a critical section and access the PCPU data like on i386. 1249 * Instead, pin the thread and grab the PCPU lock to prevent 1250 * a preempting thread from using the same PCPU data. 1251 */ 1252 sched_pin(); 1253 1254 mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED); 1255 pvo = PCPU_GET(qmap_pvo); 1256 1257 mtx_lock(PCPU_PTR(qmap_lock)); 1258 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1259 (uint64_t)pa; 1260 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1261 isync(); 1262 1263 return (PCPU_GET(qmap_addr)); 1264 } 1265 1266 void 1267 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1268 { 1269 if (hw_direct_map) 1270 return; 1271 1272 mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED); 1273 KASSERT(PCPU_GET(qmap_addr) == addr, 1274 ("moea64_quick_remove_page: invalid address")); 1275 mtx_unlock(PCPU_PTR(qmap_lock)); 1276 sched_unpin(); 1277 } 1278 1279 /* 1280 * Map the given physical page at the specified virtual address in the 1281 * target pmap with the protection requested. If specified the page 1282 * will be wired down. 1283 */ 1284 1285 int 1286 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1287 vm_prot_t prot, u_int flags, int8_t psind) 1288 { 1289 struct pvo_entry *pvo, *oldpvo; 1290 struct pvo_head *pvo_head; 1291 uint64_t pte_lo; 1292 int error; 1293 1294 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1295 VM_OBJECT_ASSERT_LOCKED(m->object); 1296 1297 pvo = alloc_pvo_entry(0); 1298 pvo->pvo_pmap = NULL; /* to be filled in later */ 1299 pvo->pvo_pte.prot = prot; 1300 1301 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1302 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1303 1304 if ((flags & PMAP_ENTER_WIRED) != 0) 1305 pvo->pvo_vaddr |= PVO_WIRED; 1306 1307 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1308 pvo_head = NULL; 1309 } else { 1310 pvo_head = &m->md.mdpg_pvoh; 1311 pvo->pvo_vaddr |= PVO_MANAGED; 1312 } 1313 1314 for (;;) { 1315 PV_PAGE_LOCK(m); 1316 PMAP_LOCK(pmap); 1317 if (pvo->pvo_pmap == NULL) 1318 init_pvo_entry(pvo, pmap, va); 1319 if (prot & VM_PROT_WRITE) 1320 if (pmap_bootstrapped && 1321 (m->oflags & VPO_UNMANAGED) == 0) 1322 vm_page_aflag_set(m, PGA_WRITEABLE); 1323 1324 oldpvo = moea64_pvo_find_va(pmap, va); 1325 if (oldpvo != NULL) { 1326 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1327 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1328 oldpvo->pvo_pte.prot == prot) { 1329 /* Identical mapping already exists */ 1330 error = 0; 1331 1332 /* If not in page table, reinsert it */ 1333 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1334 moea64_pte_overflow--; 1335 MOEA64_PTE_INSERT(mmu, oldpvo); 1336 } 1337 1338 /* Then just clean up and go home */ 1339 PV_PAGE_UNLOCK(m); 1340 PMAP_UNLOCK(pmap); 1341 free_pvo_entry(pvo); 1342 break; 1343 } 1344 1345 /* Otherwise, need to kill it first */ 1346 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1347 "mapping does not match new mapping")); 1348 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1349 } 1350 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1351 PV_PAGE_UNLOCK(m); 1352 PMAP_UNLOCK(pmap); 1353 1354 /* Free any dead pages */ 1355 if (oldpvo != NULL) { 1356 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1357 moea64_pvo_remove_from_page(mmu, oldpvo); 1358 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1359 free_pvo_entry(oldpvo); 1360 } 1361 1362 if (error != ENOMEM) 1363 break; 1364 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1365 return (KERN_RESOURCE_SHORTAGE); 1366 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1367 VM_WAIT; 1368 } 1369 1370 /* 1371 * Flush the page from the instruction cache if this page is 1372 * mapped executable and cacheable. 1373 */ 1374 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1375 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1376 vm_page_aflag_set(m, PGA_EXECUTABLE); 1377 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1378 } 1379 return (KERN_SUCCESS); 1380 } 1381 1382 static void 1383 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1384 vm_size_t sz) 1385 { 1386 1387 /* 1388 * This is much trickier than on older systems because 1389 * we can't sync the icache on physical addresses directly 1390 * without a direct map. Instead we check a couple of cases 1391 * where the memory is already mapped in and, failing that, 1392 * use the same trick we use for page zeroing to create 1393 * a temporary mapping for this physical address. 1394 */ 1395 1396 if (!pmap_bootstrapped) { 1397 /* 1398 * If PMAP is not bootstrapped, we are likely to be 1399 * in real mode. 1400 */ 1401 __syncicache((void *)pa, sz); 1402 } else if (pmap == kernel_pmap) { 1403 __syncicache((void *)va, sz); 1404 } else if (hw_direct_map) { 1405 __syncicache((void *)pa, sz); 1406 } else { 1407 /* Use the scratch page to set up a temp mapping */ 1408 1409 mtx_lock(&moea64_scratchpage_mtx); 1410 1411 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1412 __syncicache((void *)(moea64_scratchpage_va[1] + 1413 (va & ADDR_POFF)), sz); 1414 1415 mtx_unlock(&moea64_scratchpage_mtx); 1416 } 1417 } 1418 1419 /* 1420 * Maps a sequence of resident pages belonging to the same object. 1421 * The sequence begins with the given page m_start. This page is 1422 * mapped at the given virtual address start. Each subsequent page is 1423 * mapped at a virtual address that is offset from start by the same 1424 * amount as the page is offset from m_start within the object. The 1425 * last page in the sequence is the page with the largest offset from 1426 * m_start that can be mapped at a virtual address less than the given 1427 * virtual address end. Not every virtual page between start and end 1428 * is mapped; only those for which a resident page exists with the 1429 * corresponding offset from m_start are mapped. 1430 */ 1431 void 1432 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1433 vm_page_t m_start, vm_prot_t prot) 1434 { 1435 vm_page_t m; 1436 vm_pindex_t diff, psize; 1437 1438 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1439 1440 psize = atop(end - start); 1441 m = m_start; 1442 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1443 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1444 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1445 m = TAILQ_NEXT(m, listq); 1446 } 1447 } 1448 1449 void 1450 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1451 vm_prot_t prot) 1452 { 1453 1454 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1455 PMAP_ENTER_NOSLEEP, 0); 1456 } 1457 1458 vm_paddr_t 1459 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1460 { 1461 struct pvo_entry *pvo; 1462 vm_paddr_t pa; 1463 1464 PMAP_LOCK(pm); 1465 pvo = moea64_pvo_find_va(pm, va); 1466 if (pvo == NULL) 1467 pa = 0; 1468 else 1469 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1470 PMAP_UNLOCK(pm); 1471 1472 return (pa); 1473 } 1474 1475 /* 1476 * Atomically extract and hold the physical page with the given 1477 * pmap and virtual address pair if that mapping permits the given 1478 * protection. 1479 */ 1480 vm_page_t 1481 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1482 { 1483 struct pvo_entry *pvo; 1484 vm_page_t m; 1485 vm_paddr_t pa; 1486 1487 m = NULL; 1488 pa = 0; 1489 PMAP_LOCK(pmap); 1490 retry: 1491 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1492 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1493 if (vm_page_pa_tryrelock(pmap, 1494 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1495 goto retry; 1496 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1497 vm_page_hold(m); 1498 } 1499 PA_UNLOCK_COND(pa); 1500 PMAP_UNLOCK(pmap); 1501 return (m); 1502 } 1503 1504 static mmu_t installed_mmu; 1505 1506 static void * 1507 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 1508 int wait) 1509 { 1510 struct pvo_entry *pvo; 1511 vm_offset_t va; 1512 vm_page_t m; 1513 int needed_lock; 1514 1515 /* 1516 * This entire routine is a horrible hack to avoid bothering kmem 1517 * for new KVA addresses. Because this can get called from inside 1518 * kmem allocation routines, calling kmem for a new address here 1519 * can lead to multiply locking non-recursive mutexes. 1520 */ 1521 1522 *flags = UMA_SLAB_PRIV; 1523 needed_lock = !PMAP_LOCKED(kernel_pmap); 1524 1525 m = vm_page_alloc(NULL, 0, 1526 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1527 if (m == NULL) 1528 return (NULL); 1529 1530 va = VM_PAGE_TO_PHYS(m); 1531 1532 pvo = alloc_pvo_entry(1 /* bootstrap */); 1533 1534 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1535 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1536 1537 if (needed_lock) 1538 PMAP_LOCK(kernel_pmap); 1539 1540 init_pvo_entry(pvo, kernel_pmap, va); 1541 pvo->pvo_vaddr |= PVO_WIRED; 1542 1543 moea64_pvo_enter(installed_mmu, pvo, NULL); 1544 1545 if (needed_lock) 1546 PMAP_UNLOCK(kernel_pmap); 1547 1548 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1549 bzero((void *)va, PAGE_SIZE); 1550 1551 return (void *)va; 1552 } 1553 1554 extern int elf32_nxstack; 1555 1556 void 1557 moea64_init(mmu_t mmu) 1558 { 1559 1560 CTR0(KTR_PMAP, "moea64_init"); 1561 1562 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1563 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1564 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1565 1566 if (!hw_direct_map) { 1567 installed_mmu = mmu; 1568 uma_zone_set_allocf(moea64_pvo_zone,moea64_uma_page_alloc); 1569 } 1570 1571 #ifdef COMPAT_FREEBSD32 1572 elf32_nxstack = 1; 1573 #endif 1574 1575 moea64_initialized = TRUE; 1576 } 1577 1578 boolean_t 1579 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1580 { 1581 1582 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1583 ("moea64_is_referenced: page %p is not managed", m)); 1584 1585 return (moea64_query_bit(mmu, m, LPTE_REF)); 1586 } 1587 1588 boolean_t 1589 moea64_is_modified(mmu_t mmu, vm_page_t m) 1590 { 1591 1592 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1593 ("moea64_is_modified: page %p is not managed", m)); 1594 1595 /* 1596 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1597 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1598 * is clear, no PTEs can have LPTE_CHG set. 1599 */ 1600 VM_OBJECT_ASSERT_LOCKED(m->object); 1601 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1602 return (FALSE); 1603 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1604 } 1605 1606 boolean_t 1607 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1608 { 1609 struct pvo_entry *pvo; 1610 boolean_t rv = TRUE; 1611 1612 PMAP_LOCK(pmap); 1613 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1614 if (pvo != NULL) 1615 rv = FALSE; 1616 PMAP_UNLOCK(pmap); 1617 return (rv); 1618 } 1619 1620 void 1621 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1622 { 1623 1624 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1625 ("moea64_clear_modify: page %p is not managed", m)); 1626 VM_OBJECT_ASSERT_WLOCKED(m->object); 1627 KASSERT(!vm_page_xbusied(m), 1628 ("moea64_clear_modify: page %p is exclusive busied", m)); 1629 1630 /* 1631 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1632 * set. If the object containing the page is locked and the page is 1633 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1634 */ 1635 if ((m->aflags & PGA_WRITEABLE) == 0) 1636 return; 1637 moea64_clear_bit(mmu, m, LPTE_CHG); 1638 } 1639 1640 /* 1641 * Clear the write and modified bits in each of the given page's mappings. 1642 */ 1643 void 1644 moea64_remove_write(mmu_t mmu, vm_page_t m) 1645 { 1646 struct pvo_entry *pvo; 1647 int64_t refchg, ret; 1648 pmap_t pmap; 1649 1650 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1651 ("moea64_remove_write: page %p is not managed", m)); 1652 1653 /* 1654 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1655 * set by another thread while the object is locked. Thus, 1656 * if PGA_WRITEABLE is clear, no page table entries need updating. 1657 */ 1658 VM_OBJECT_ASSERT_WLOCKED(m->object); 1659 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1660 return; 1661 powerpc_sync(); 1662 PV_PAGE_LOCK(m); 1663 refchg = 0; 1664 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1665 pmap = pvo->pvo_pmap; 1666 PMAP_LOCK(pmap); 1667 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1668 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1669 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1670 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1671 MOEA64_PTE_PROT_UPDATE); 1672 if (ret < 0) 1673 ret = LPTE_CHG; 1674 refchg |= ret; 1675 if (pvo->pvo_pmap == kernel_pmap) 1676 isync(); 1677 } 1678 PMAP_UNLOCK(pmap); 1679 } 1680 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1681 vm_page_dirty(m); 1682 vm_page_aflag_clear(m, PGA_WRITEABLE); 1683 PV_PAGE_UNLOCK(m); 1684 } 1685 1686 /* 1687 * moea64_ts_referenced: 1688 * 1689 * Return a count of reference bits for a page, clearing those bits. 1690 * It is not necessary for every reference bit to be cleared, but it 1691 * is necessary that 0 only be returned when there are truly no 1692 * reference bits set. 1693 * 1694 * XXX: The exact number of bits to check and clear is a matter that 1695 * should be tested and standardized at some point in the future for 1696 * optimal aging of shared pages. 1697 */ 1698 int 1699 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1700 { 1701 1702 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1703 ("moea64_ts_referenced: page %p is not managed", m)); 1704 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1705 } 1706 1707 /* 1708 * Modify the WIMG settings of all mappings for a page. 1709 */ 1710 void 1711 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1712 { 1713 struct pvo_entry *pvo; 1714 int64_t refchg; 1715 pmap_t pmap; 1716 uint64_t lo; 1717 1718 if ((m->oflags & VPO_UNMANAGED) != 0) { 1719 m->md.mdpg_cache_attrs = ma; 1720 return; 1721 } 1722 1723 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1724 1725 PV_PAGE_LOCK(m); 1726 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1727 pmap = pvo->pvo_pmap; 1728 PMAP_LOCK(pmap); 1729 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1730 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1731 pvo->pvo_pte.pa |= lo; 1732 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1733 MOEA64_PTE_INVALIDATE); 1734 if (refchg < 0) 1735 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1736 LPTE_CHG : 0; 1737 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1738 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1739 refchg |= 1740 atomic_readandclear_32(&m->md.mdpg_attrs); 1741 if (refchg & LPTE_CHG) 1742 vm_page_dirty(m); 1743 if (refchg & LPTE_REF) 1744 vm_page_aflag_set(m, PGA_REFERENCED); 1745 } 1746 if (pvo->pvo_pmap == kernel_pmap) 1747 isync(); 1748 } 1749 PMAP_UNLOCK(pmap); 1750 } 1751 m->md.mdpg_cache_attrs = ma; 1752 PV_PAGE_UNLOCK(m); 1753 } 1754 1755 /* 1756 * Map a wired page into kernel virtual address space. 1757 */ 1758 void 1759 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1760 { 1761 int error; 1762 struct pvo_entry *pvo, *oldpvo; 1763 1764 pvo = alloc_pvo_entry(0); 1765 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1766 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1767 pvo->pvo_vaddr |= PVO_WIRED; 1768 1769 PMAP_LOCK(kernel_pmap); 1770 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1771 if (oldpvo != NULL) 1772 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1773 init_pvo_entry(pvo, kernel_pmap, va); 1774 error = moea64_pvo_enter(mmu, pvo, NULL); 1775 PMAP_UNLOCK(kernel_pmap); 1776 1777 /* Free any dead pages */ 1778 if (oldpvo != NULL) { 1779 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1780 moea64_pvo_remove_from_page(mmu, oldpvo); 1781 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1782 free_pvo_entry(oldpvo); 1783 } 1784 1785 if (error != 0 && error != ENOENT) 1786 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1787 pa, error); 1788 } 1789 1790 void 1791 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1792 { 1793 1794 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1795 } 1796 1797 /* 1798 * Extract the physical page address associated with the given kernel virtual 1799 * address. 1800 */ 1801 vm_paddr_t 1802 moea64_kextract(mmu_t mmu, vm_offset_t va) 1803 { 1804 struct pvo_entry *pvo; 1805 vm_paddr_t pa; 1806 1807 /* 1808 * Shortcut the direct-mapped case when applicable. We never put 1809 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1810 */ 1811 if (va < VM_MIN_KERNEL_ADDRESS) 1812 return (va); 1813 1814 PMAP_LOCK(kernel_pmap); 1815 pvo = moea64_pvo_find_va(kernel_pmap, va); 1816 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1817 va)); 1818 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1819 PMAP_UNLOCK(kernel_pmap); 1820 return (pa); 1821 } 1822 1823 /* 1824 * Remove a wired page from kernel virtual address space. 1825 */ 1826 void 1827 moea64_kremove(mmu_t mmu, vm_offset_t va) 1828 { 1829 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1830 } 1831 1832 /* 1833 * Map a range of physical addresses into kernel virtual address space. 1834 * 1835 * The value passed in *virt is a suggested virtual address for the mapping. 1836 * Architectures which can support a direct-mapped physical to virtual region 1837 * can return the appropriate address within that region, leaving '*virt' 1838 * unchanged. Other architectures should map the pages starting at '*virt' and 1839 * update '*virt' with the first usable address after the mapped region. 1840 */ 1841 vm_offset_t 1842 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1843 vm_paddr_t pa_end, int prot) 1844 { 1845 vm_offset_t sva, va; 1846 1847 if (hw_direct_map) { 1848 /* 1849 * Check if every page in the region is covered by the direct 1850 * map. The direct map covers all of physical memory. Use 1851 * moea64_calc_wimg() as a shortcut to see if the page is in 1852 * physical memory as a way to see if the direct map covers it. 1853 */ 1854 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1855 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1856 break; 1857 if (va == pa_end) 1858 return (pa_start); 1859 } 1860 sva = *virt; 1861 va = sva; 1862 /* XXX respect prot argument */ 1863 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1864 moea64_kenter(mmu, va, pa_start); 1865 *virt = va; 1866 1867 return (sva); 1868 } 1869 1870 /* 1871 * Returns true if the pmap's pv is one of the first 1872 * 16 pvs linked to from this page. This count may 1873 * be changed upwards or downwards in the future; it 1874 * is only necessary that true be returned for a small 1875 * subset of pmaps for proper page aging. 1876 */ 1877 boolean_t 1878 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1879 { 1880 int loops; 1881 struct pvo_entry *pvo; 1882 boolean_t rv; 1883 1884 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1885 ("moea64_page_exists_quick: page %p is not managed", m)); 1886 loops = 0; 1887 rv = FALSE; 1888 PV_PAGE_LOCK(m); 1889 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1890 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 1891 rv = TRUE; 1892 break; 1893 } 1894 if (++loops >= 16) 1895 break; 1896 } 1897 PV_PAGE_UNLOCK(m); 1898 return (rv); 1899 } 1900 1901 void 1902 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 1903 { 1904 1905 m->md.mdpg_attrs = 0; 1906 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1907 LIST_INIT(&m->md.mdpg_pvoh); 1908 } 1909 1910 /* 1911 * Return the number of managed mappings to the given physical page 1912 * that are wired. 1913 */ 1914 int 1915 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1916 { 1917 struct pvo_entry *pvo; 1918 int count; 1919 1920 count = 0; 1921 if ((m->oflags & VPO_UNMANAGED) != 0) 1922 return (count); 1923 PV_PAGE_LOCK(m); 1924 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1925 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 1926 count++; 1927 PV_PAGE_UNLOCK(m); 1928 return (count); 1929 } 1930 1931 static uintptr_t moea64_vsidcontext; 1932 1933 uintptr_t 1934 moea64_get_unique_vsid(void) { 1935 u_int entropy; 1936 register_t hash; 1937 uint32_t mask; 1938 int i; 1939 1940 entropy = 0; 1941 __asm __volatile("mftb %0" : "=r"(entropy)); 1942 1943 mtx_lock(&moea64_slb_mutex); 1944 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1945 u_int n; 1946 1947 /* 1948 * Create a new value by mutiplying by a prime and adding in 1949 * entropy from the timebase register. This is to make the 1950 * VSID more random so that the PT hash function collides 1951 * less often. (Note that the prime casues gcc to do shifts 1952 * instead of a multiply.) 1953 */ 1954 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1955 hash = moea64_vsidcontext & (NVSIDS - 1); 1956 if (hash == 0) /* 0 is special, avoid it */ 1957 continue; 1958 n = hash >> 5; 1959 mask = 1 << (hash & (VSID_NBPW - 1)); 1960 hash = (moea64_vsidcontext & VSID_HASHMASK); 1961 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1962 /* anything free in this bucket? */ 1963 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1964 entropy = (moea64_vsidcontext >> 20); 1965 continue; 1966 } 1967 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1968 mask = 1 << i; 1969 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 1970 hash |= i; 1971 } 1972 if (hash == VSID_VRMA) /* also special, avoid this too */ 1973 continue; 1974 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1975 ("Allocating in-use VSID %#zx\n", hash)); 1976 moea64_vsid_bitmap[n] |= mask; 1977 mtx_unlock(&moea64_slb_mutex); 1978 return (hash); 1979 } 1980 1981 mtx_unlock(&moea64_slb_mutex); 1982 panic("%s: out of segments",__func__); 1983 } 1984 1985 #ifdef __powerpc64__ 1986 void 1987 moea64_pinit(mmu_t mmu, pmap_t pmap) 1988 { 1989 1990 RB_INIT(&pmap->pmap_pvo); 1991 1992 pmap->pm_slb_tree_root = slb_alloc_tree(); 1993 pmap->pm_slb = slb_alloc_user_cache(); 1994 pmap->pm_slb_len = 0; 1995 } 1996 #else 1997 void 1998 moea64_pinit(mmu_t mmu, pmap_t pmap) 1999 { 2000 int i; 2001 uint32_t hash; 2002 2003 RB_INIT(&pmap->pmap_pvo); 2004 2005 if (pmap_bootstrapped) 2006 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2007 (vm_offset_t)pmap); 2008 else 2009 pmap->pmap_phys = pmap; 2010 2011 /* 2012 * Allocate some segment registers for this pmap. 2013 */ 2014 hash = moea64_get_unique_vsid(); 2015 2016 for (i = 0; i < 16; i++) 2017 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2018 2019 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2020 } 2021 #endif 2022 2023 /* 2024 * Initialize the pmap associated with process 0. 2025 */ 2026 void 2027 moea64_pinit0(mmu_t mmu, pmap_t pm) 2028 { 2029 2030 PMAP_LOCK_INIT(pm); 2031 moea64_pinit(mmu, pm); 2032 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2033 } 2034 2035 /* 2036 * Set the physical protection on the specified range of this map as requested. 2037 */ 2038 static void 2039 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2040 { 2041 struct vm_page *pg; 2042 vm_prot_t oldprot; 2043 int32_t refchg; 2044 2045 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2046 2047 /* 2048 * Change the protection of the page. 2049 */ 2050 oldprot = pvo->pvo_pte.prot; 2051 pvo->pvo_pte.prot = prot; 2052 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2053 2054 /* 2055 * If the PVO is in the page table, update mapping 2056 */ 2057 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2058 if (refchg < 0) 2059 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2060 2061 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2062 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2063 if ((pg->oflags & VPO_UNMANAGED) == 0) 2064 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2065 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2066 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2067 } 2068 2069 /* 2070 * Update vm about the REF/CHG bits if the page is managed and we have 2071 * removed write access. 2072 */ 2073 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2074 (oldprot & VM_PROT_WRITE)) { 2075 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2076 if (refchg & LPTE_CHG) 2077 vm_page_dirty(pg); 2078 if (refchg & LPTE_REF) 2079 vm_page_aflag_set(pg, PGA_REFERENCED); 2080 } 2081 } 2082 2083 void 2084 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2085 vm_prot_t prot) 2086 { 2087 struct pvo_entry *pvo, *tpvo, key; 2088 2089 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2090 sva, eva, prot); 2091 2092 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2093 ("moea64_protect: non current pmap")); 2094 2095 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2096 moea64_remove(mmu, pm, sva, eva); 2097 return; 2098 } 2099 2100 PMAP_LOCK(pm); 2101 key.pvo_vaddr = sva; 2102 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2103 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2104 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2105 moea64_pvo_protect(mmu, pm, pvo, prot); 2106 } 2107 PMAP_UNLOCK(pm); 2108 } 2109 2110 /* 2111 * Map a list of wired pages into kernel virtual address space. This is 2112 * intended for temporary mappings which do not need page modification or 2113 * references recorded. Existing mappings in the region are overwritten. 2114 */ 2115 void 2116 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2117 { 2118 while (count-- > 0) { 2119 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2120 va += PAGE_SIZE; 2121 m++; 2122 } 2123 } 2124 2125 /* 2126 * Remove page mappings from kernel virtual address space. Intended for 2127 * temporary mappings entered by moea64_qenter. 2128 */ 2129 void 2130 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2131 { 2132 while (count-- > 0) { 2133 moea64_kremove(mmu, va); 2134 va += PAGE_SIZE; 2135 } 2136 } 2137 2138 void 2139 moea64_release_vsid(uint64_t vsid) 2140 { 2141 int idx, mask; 2142 2143 mtx_lock(&moea64_slb_mutex); 2144 idx = vsid & (NVSIDS-1); 2145 mask = 1 << (idx % VSID_NBPW); 2146 idx /= VSID_NBPW; 2147 KASSERT(moea64_vsid_bitmap[idx] & mask, 2148 ("Freeing unallocated VSID %#jx", vsid)); 2149 moea64_vsid_bitmap[idx] &= ~mask; 2150 mtx_unlock(&moea64_slb_mutex); 2151 } 2152 2153 2154 void 2155 moea64_release(mmu_t mmu, pmap_t pmap) 2156 { 2157 2158 /* 2159 * Free segment registers' VSIDs 2160 */ 2161 #ifdef __powerpc64__ 2162 slb_free_tree(pmap); 2163 slb_free_user_cache(pmap->pm_slb); 2164 #else 2165 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2166 2167 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2168 #endif 2169 } 2170 2171 /* 2172 * Remove all pages mapped by the specified pmap 2173 */ 2174 void 2175 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2176 { 2177 struct pvo_entry *pvo, *tpvo; 2178 struct pvo_tree tofree; 2179 2180 RB_INIT(&tofree); 2181 2182 PMAP_LOCK(pm); 2183 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2184 if (pvo->pvo_vaddr & PVO_WIRED) 2185 continue; 2186 2187 /* 2188 * For locking reasons, remove this from the page table and 2189 * pmap, but save delinking from the vm_page for a second 2190 * pass 2191 */ 2192 moea64_pvo_remove_from_pmap(mmu, pvo); 2193 RB_INSERT(pvo_tree, &tofree, pvo); 2194 } 2195 PMAP_UNLOCK(pm); 2196 2197 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2198 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2199 moea64_pvo_remove_from_page(mmu, pvo); 2200 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2201 RB_REMOVE(pvo_tree, &tofree, pvo); 2202 free_pvo_entry(pvo); 2203 } 2204 } 2205 2206 /* 2207 * Remove the given range of addresses from the specified map. 2208 */ 2209 void 2210 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2211 { 2212 struct pvo_entry *pvo, *tpvo, key; 2213 struct pvo_tree tofree; 2214 2215 /* 2216 * Perform an unsynchronized read. This is, however, safe. 2217 */ 2218 if (pm->pm_stats.resident_count == 0) 2219 return; 2220 2221 key.pvo_vaddr = sva; 2222 2223 RB_INIT(&tofree); 2224 2225 PMAP_LOCK(pm); 2226 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2227 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2228 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2229 2230 /* 2231 * For locking reasons, remove this from the page table and 2232 * pmap, but save delinking from the vm_page for a second 2233 * pass 2234 */ 2235 moea64_pvo_remove_from_pmap(mmu, pvo); 2236 RB_INSERT(pvo_tree, &tofree, pvo); 2237 } 2238 PMAP_UNLOCK(pm); 2239 2240 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2241 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2242 moea64_pvo_remove_from_page(mmu, pvo); 2243 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2244 RB_REMOVE(pvo_tree, &tofree, pvo); 2245 free_pvo_entry(pvo); 2246 } 2247 } 2248 2249 /* 2250 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2251 * will reflect changes in pte's back to the vm_page. 2252 */ 2253 void 2254 moea64_remove_all(mmu_t mmu, vm_page_t m) 2255 { 2256 struct pvo_entry *pvo, *next_pvo; 2257 struct pvo_head freequeue; 2258 int wasdead; 2259 pmap_t pmap; 2260 2261 LIST_INIT(&freequeue); 2262 2263 PV_PAGE_LOCK(m); 2264 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2265 pmap = pvo->pvo_pmap; 2266 PMAP_LOCK(pmap); 2267 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2268 if (!wasdead) 2269 moea64_pvo_remove_from_pmap(mmu, pvo); 2270 moea64_pvo_remove_from_page(mmu, pvo); 2271 if (!wasdead) 2272 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2273 PMAP_UNLOCK(pmap); 2274 2275 } 2276 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2277 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2278 PV_PAGE_UNLOCK(m); 2279 2280 /* Clean up UMA allocations */ 2281 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2282 free_pvo_entry(pvo); 2283 } 2284 2285 /* 2286 * Allocate a physical page of memory directly from the phys_avail map. 2287 * Can only be called from moea64_bootstrap before avail start and end are 2288 * calculated. 2289 */ 2290 vm_offset_t 2291 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2292 { 2293 vm_offset_t s, e; 2294 int i, j; 2295 2296 size = round_page(size); 2297 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2298 if (align != 0) 2299 s = roundup2(phys_avail[i], align); 2300 else 2301 s = phys_avail[i]; 2302 e = s + size; 2303 2304 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2305 continue; 2306 2307 if (s + size > platform_real_maxaddr()) 2308 continue; 2309 2310 if (s == phys_avail[i]) { 2311 phys_avail[i] += size; 2312 } else if (e == phys_avail[i + 1]) { 2313 phys_avail[i + 1] -= size; 2314 } else { 2315 for (j = phys_avail_count * 2; j > i; j -= 2) { 2316 phys_avail[j] = phys_avail[j - 2]; 2317 phys_avail[j + 1] = phys_avail[j - 1]; 2318 } 2319 2320 phys_avail[i + 3] = phys_avail[i + 1]; 2321 phys_avail[i + 1] = s; 2322 phys_avail[i + 2] = e; 2323 phys_avail_count++; 2324 } 2325 2326 return (s); 2327 } 2328 panic("moea64_bootstrap_alloc: could not allocate memory"); 2329 } 2330 2331 static int 2332 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2333 { 2334 int first, err; 2335 2336 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2337 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2338 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2339 2340 moea64_pvo_enter_calls++; 2341 2342 /* 2343 * Add to pmap list 2344 */ 2345 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2346 2347 /* 2348 * Remember if the list was empty and therefore will be the first 2349 * item. 2350 */ 2351 if (pvo_head != NULL) { 2352 if (LIST_FIRST(pvo_head) == NULL) 2353 first = 1; 2354 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2355 } 2356 2357 if (pvo->pvo_vaddr & PVO_WIRED) 2358 pvo->pvo_pmap->pm_stats.wired_count++; 2359 pvo->pvo_pmap->pm_stats.resident_count++; 2360 2361 /* 2362 * Insert it into the hardware page table 2363 */ 2364 err = MOEA64_PTE_INSERT(mmu, pvo); 2365 if (err != 0) { 2366 panic("moea64_pvo_enter: overflow"); 2367 } 2368 2369 moea64_pvo_entries++; 2370 2371 if (pvo->pvo_pmap == kernel_pmap) 2372 isync(); 2373 2374 #ifdef __powerpc64__ 2375 /* 2376 * Make sure all our bootstrap mappings are in the SLB as soon 2377 * as virtual memory is switched on. 2378 */ 2379 if (!pmap_bootstrapped) 2380 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2381 pvo->pvo_vaddr & PVO_LARGE); 2382 #endif 2383 2384 return (first ? ENOENT : 0); 2385 } 2386 2387 static void 2388 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2389 { 2390 struct vm_page *pg; 2391 int32_t refchg; 2392 2393 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2394 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2395 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2396 2397 /* 2398 * If there is an active pte entry, we need to deactivate it 2399 */ 2400 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2401 if (refchg < 0) { 2402 /* 2403 * If it was evicted from the page table, be pessimistic and 2404 * dirty the page. 2405 */ 2406 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2407 refchg = LPTE_CHG; 2408 else 2409 refchg = 0; 2410 } 2411 2412 /* 2413 * Update our statistics. 2414 */ 2415 pvo->pvo_pmap->pm_stats.resident_count--; 2416 if (pvo->pvo_vaddr & PVO_WIRED) 2417 pvo->pvo_pmap->pm_stats.wired_count--; 2418 2419 /* 2420 * Remove this PVO from the pmap list. 2421 */ 2422 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2423 2424 /* 2425 * Mark this for the next sweep 2426 */ 2427 pvo->pvo_vaddr |= PVO_DEAD; 2428 2429 /* Send RC bits to VM */ 2430 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2431 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2432 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2433 if (pg != NULL) { 2434 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2435 if (refchg & LPTE_CHG) 2436 vm_page_dirty(pg); 2437 if (refchg & LPTE_REF) 2438 vm_page_aflag_set(pg, PGA_REFERENCED); 2439 } 2440 } 2441 } 2442 2443 static void 2444 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2445 { 2446 struct vm_page *pg; 2447 2448 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2449 2450 /* Use NULL pmaps as a sentinel for races in page deletion */ 2451 if (pvo->pvo_pmap == NULL) 2452 return; 2453 pvo->pvo_pmap = NULL; 2454 2455 /* 2456 * Update vm about page writeability/executability if managed 2457 */ 2458 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2459 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2460 2461 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) { 2462 LIST_REMOVE(pvo, pvo_vlink); 2463 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2464 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE); 2465 } 2466 2467 moea64_pvo_entries--; 2468 moea64_pvo_remove_calls++; 2469 } 2470 2471 static struct pvo_entry * 2472 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2473 { 2474 struct pvo_entry key; 2475 2476 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2477 2478 key.pvo_vaddr = va & ~ADDR_POFF; 2479 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2480 } 2481 2482 static boolean_t 2483 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2484 { 2485 struct pvo_entry *pvo; 2486 int64_t ret; 2487 boolean_t rv; 2488 2489 /* 2490 * See if this bit is stored in the page already. 2491 */ 2492 if (m->md.mdpg_attrs & ptebit) 2493 return (TRUE); 2494 2495 /* 2496 * Examine each PTE. Sync so that any pending REF/CHG bits are 2497 * flushed to the PTEs. 2498 */ 2499 rv = FALSE; 2500 powerpc_sync(); 2501 PV_PAGE_LOCK(m); 2502 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2503 ret = 0; 2504 2505 /* 2506 * See if this pvo has a valid PTE. if so, fetch the 2507 * REF/CHG bits from the valid PTE. If the appropriate 2508 * ptebit is set, return success. 2509 */ 2510 PMAP_LOCK(pvo->pvo_pmap); 2511 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2512 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2513 PMAP_UNLOCK(pvo->pvo_pmap); 2514 2515 if (ret > 0) { 2516 atomic_set_32(&m->md.mdpg_attrs, 2517 ret & (LPTE_CHG | LPTE_REF)); 2518 if (ret & ptebit) { 2519 rv = TRUE; 2520 break; 2521 } 2522 } 2523 } 2524 PV_PAGE_UNLOCK(m); 2525 2526 return (rv); 2527 } 2528 2529 static u_int 2530 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2531 { 2532 u_int count; 2533 struct pvo_entry *pvo; 2534 int64_t ret; 2535 2536 /* 2537 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2538 * we can reset the right ones). 2539 */ 2540 powerpc_sync(); 2541 2542 /* 2543 * For each pvo entry, clear the pte's ptebit. 2544 */ 2545 count = 0; 2546 PV_PAGE_LOCK(m); 2547 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2548 ret = 0; 2549 2550 PMAP_LOCK(pvo->pvo_pmap); 2551 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2552 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2553 PMAP_UNLOCK(pvo->pvo_pmap); 2554 2555 if (ret > 0 && (ret & ptebit)) 2556 count++; 2557 } 2558 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2559 PV_PAGE_UNLOCK(m); 2560 2561 return (count); 2562 } 2563 2564 boolean_t 2565 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2566 { 2567 struct pvo_entry *pvo, key; 2568 vm_offset_t ppa; 2569 int error = 0; 2570 2571 PMAP_LOCK(kernel_pmap); 2572 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2573 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2574 ppa < pa + size; ppa += PAGE_SIZE, 2575 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2576 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2577 error = EFAULT; 2578 break; 2579 } 2580 } 2581 PMAP_UNLOCK(kernel_pmap); 2582 2583 return (error); 2584 } 2585 2586 /* 2587 * Map a set of physical memory pages into the kernel virtual 2588 * address space. Return a pointer to where it is mapped. This 2589 * routine is intended to be used for mapping device memory, 2590 * NOT real memory. 2591 */ 2592 void * 2593 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2594 { 2595 vm_offset_t va, tmpva, ppa, offset; 2596 2597 ppa = trunc_page(pa); 2598 offset = pa & PAGE_MASK; 2599 size = roundup2(offset + size, PAGE_SIZE); 2600 2601 va = kva_alloc(size); 2602 2603 if (!va) 2604 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2605 2606 for (tmpva = va; size > 0;) { 2607 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2608 size -= PAGE_SIZE; 2609 tmpva += PAGE_SIZE; 2610 ppa += PAGE_SIZE; 2611 } 2612 2613 return ((void *)(va + offset)); 2614 } 2615 2616 void * 2617 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2618 { 2619 2620 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2621 } 2622 2623 void 2624 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2625 { 2626 vm_offset_t base, offset; 2627 2628 base = trunc_page(va); 2629 offset = va & PAGE_MASK; 2630 size = roundup2(offset + size, PAGE_SIZE); 2631 2632 kva_free(base, size); 2633 } 2634 2635 void 2636 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2637 { 2638 struct pvo_entry *pvo; 2639 vm_offset_t lim; 2640 vm_paddr_t pa; 2641 vm_size_t len; 2642 2643 PMAP_LOCK(pm); 2644 while (sz > 0) { 2645 lim = round_page(va); 2646 len = MIN(lim - va, sz); 2647 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2648 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2649 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2650 moea64_syncicache(mmu, pm, va, pa, len); 2651 } 2652 va += len; 2653 sz -= len; 2654 } 2655 PMAP_UNLOCK(pm); 2656 } 2657 2658 void 2659 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2660 { 2661 2662 *va = (void *)pa; 2663 } 2664 2665 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2666 2667 void 2668 moea64_scan_init(mmu_t mmu) 2669 { 2670 struct pvo_entry *pvo; 2671 vm_offset_t va; 2672 int i; 2673 2674 if (!do_minidump) { 2675 /* Initialize phys. segments for dumpsys(). */ 2676 memset(&dump_map, 0, sizeof(dump_map)); 2677 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2678 for (i = 0; i < pregions_sz; i++) { 2679 dump_map[i].pa_start = pregions[i].mr_start; 2680 dump_map[i].pa_size = pregions[i].mr_size; 2681 } 2682 return; 2683 } 2684 2685 /* Virtual segments for minidumps: */ 2686 memset(&dump_map, 0, sizeof(dump_map)); 2687 2688 /* 1st: kernel .data and .bss. */ 2689 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2690 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2691 dump_map[0].pa_start; 2692 2693 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2694 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2695 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2696 2697 /* 3rd: kernel VM. */ 2698 va = dump_map[1].pa_start + dump_map[1].pa_size; 2699 /* Find start of next chunk (from va). */ 2700 while (va < virtual_end) { 2701 /* Don't dump the buffer cache. */ 2702 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2703 va = kmi.buffer_eva; 2704 continue; 2705 } 2706 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2707 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2708 break; 2709 va += PAGE_SIZE; 2710 } 2711 if (va < virtual_end) { 2712 dump_map[2].pa_start = va; 2713 va += PAGE_SIZE; 2714 /* Find last page in chunk. */ 2715 while (va < virtual_end) { 2716 /* Don't run into the buffer cache. */ 2717 if (va == kmi.buffer_sva) 2718 break; 2719 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2720 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2721 break; 2722 va += PAGE_SIZE; 2723 } 2724 dump_map[2].pa_size = va - dump_map[2].pa_start; 2725 } 2726 } 2727 2728