1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_phys.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_PER_DOM (PA_LOCK_COUNT * 3) 123 #define PV_LOCK_COUNT (PV_LOCK_PER_DOM * MAXMEMDOM) 124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 125 126 /* 127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 129 * index at (N << 45). 130 */ 131 #ifdef __powerpc64__ 132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 134 #else 135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 136 #endif 137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 144 145 struct ofw_map { 146 cell_t om_va; 147 cell_t om_len; 148 uint64_t om_pa; 149 cell_t om_mode; 150 }; 151 152 extern unsigned char _etext[]; 153 extern unsigned char _end[]; 154 155 extern void *slbtrap, *slbtrapend; 156 157 /* 158 * Map of physical memory regions. 159 */ 160 static struct mem_region *regions; 161 static struct mem_region *pregions; 162 static struct numa_mem_region *numa_pregions; 163 static u_int phys_avail_count; 164 static int regions_sz, pregions_sz, numapregions_sz; 165 166 extern void bs_remap_earlyboot(void); 167 168 /* 169 * Lock for the SLB tables. 170 */ 171 struct mtx moea64_slb_mutex; 172 173 /* 174 * PTEG data. 175 */ 176 u_long moea64_pteg_count; 177 u_long moea64_pteg_mask; 178 179 /* 180 * PVO data. 181 */ 182 183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 184 185 static struct pvo_entry *moea64_bpvo_pool; 186 static int moea64_bpvo_pool_index = 0; 187 static int moea64_bpvo_pool_size = 327680; 188 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 189 &moea64_bpvo_pool_index, 0, ""); 190 191 #define VSID_NBPW (sizeof(u_int32_t) * 8) 192 #ifdef __powerpc64__ 193 #define NVSIDS (NPMAPS * 16) 194 #define VSID_HASHMASK 0xffffffffUL 195 #else 196 #define NVSIDS NPMAPS 197 #define VSID_HASHMASK 0xfffffUL 198 #endif 199 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 200 201 static boolean_t moea64_initialized = FALSE; 202 203 #ifdef MOEA64_STATS 204 /* 205 * Statistics. 206 */ 207 u_int moea64_pte_valid = 0; 208 u_int moea64_pte_overflow = 0; 209 u_int moea64_pvo_entries = 0; 210 u_int moea64_pvo_enter_calls = 0; 211 u_int moea64_pvo_remove_calls = 0; 212 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 213 &moea64_pte_valid, 0, ""); 214 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 215 &moea64_pte_overflow, 0, ""); 216 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 217 &moea64_pvo_entries, 0, ""); 218 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 219 &moea64_pvo_enter_calls, 0, ""); 220 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 221 &moea64_pvo_remove_calls, 0, ""); 222 #endif 223 224 vm_offset_t moea64_scratchpage_va[2]; 225 struct pvo_entry *moea64_scratchpage_pvo[2]; 226 struct mtx moea64_scratchpage_mtx; 227 228 uint64_t moea64_large_page_mask = 0; 229 uint64_t moea64_large_page_size = 0; 230 int moea64_large_page_shift = 0; 231 232 /* 233 * PVO calls. 234 */ 235 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 236 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 237 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 238 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 240 struct pvo_entry *pvo, vm_page_t m); 241 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 242 243 /* 244 * Utility routines. 245 */ 246 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 247 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 248 static void moea64_kremove(mmu_t, vm_offset_t); 249 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 250 vm_paddr_t pa, vm_size_t sz); 251 static void moea64_pmap_init_qpages(void); 252 253 /* 254 * Kernel MMU interface 255 */ 256 void moea64_clear_modify(mmu_t, vm_page_t); 257 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 258 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 259 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 260 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 261 u_int flags, int8_t psind); 262 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 263 vm_prot_t); 264 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 265 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 266 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 267 void moea64_init(mmu_t); 268 boolean_t moea64_is_modified(mmu_t, vm_page_t); 269 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 270 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 271 int moea64_ts_referenced(mmu_t, vm_page_t); 272 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 273 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 274 void moea64_page_init(mmu_t, vm_page_t); 275 int moea64_page_wired_mappings(mmu_t, vm_page_t); 276 void moea64_pinit(mmu_t, pmap_t); 277 void moea64_pinit0(mmu_t, pmap_t); 278 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 279 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 280 void moea64_qremove(mmu_t, vm_offset_t, int); 281 void moea64_release(mmu_t, pmap_t); 282 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 283 void moea64_remove_pages(mmu_t, pmap_t); 284 void moea64_remove_all(mmu_t, vm_page_t); 285 void moea64_remove_write(mmu_t, vm_page_t); 286 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 287 void moea64_zero_page(mmu_t, vm_page_t); 288 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 289 void moea64_activate(mmu_t, struct thread *); 290 void moea64_deactivate(mmu_t, struct thread *); 291 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 292 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 293 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 294 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 295 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 296 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 297 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 298 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 299 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 300 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 301 void **va); 302 void moea64_scan_init(mmu_t mmu); 303 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 304 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 305 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 306 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 307 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 308 int *is_user, vm_offset_t *decoded_addr); 309 static size_t moea64_scan_pmap(mmu_t mmu); 310 static void *moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs); 311 #ifdef __powerpc64__ 312 static void moea64_page_array_startup(mmu_t, long); 313 #endif 314 315 316 static mmu_method_t moea64_methods[] = { 317 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 318 MMUMETHOD(mmu_copy_page, moea64_copy_page), 319 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 320 MMUMETHOD(mmu_enter, moea64_enter), 321 MMUMETHOD(mmu_enter_object, moea64_enter_object), 322 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 323 MMUMETHOD(mmu_extract, moea64_extract), 324 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 325 MMUMETHOD(mmu_init, moea64_init), 326 MMUMETHOD(mmu_is_modified, moea64_is_modified), 327 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 328 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 329 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 330 MMUMETHOD(mmu_map, moea64_map), 331 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 332 MMUMETHOD(mmu_page_init, moea64_page_init), 333 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 334 MMUMETHOD(mmu_pinit, moea64_pinit), 335 MMUMETHOD(mmu_pinit0, moea64_pinit0), 336 MMUMETHOD(mmu_protect, moea64_protect), 337 MMUMETHOD(mmu_qenter, moea64_qenter), 338 MMUMETHOD(mmu_qremove, moea64_qremove), 339 MMUMETHOD(mmu_release, moea64_release), 340 MMUMETHOD(mmu_remove, moea64_remove), 341 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 342 MMUMETHOD(mmu_remove_all, moea64_remove_all), 343 MMUMETHOD(mmu_remove_write, moea64_remove_write), 344 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 345 MMUMETHOD(mmu_unwire, moea64_unwire), 346 MMUMETHOD(mmu_zero_page, moea64_zero_page), 347 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 348 MMUMETHOD(mmu_activate, moea64_activate), 349 MMUMETHOD(mmu_deactivate, moea64_deactivate), 350 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 351 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 352 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 353 #ifdef __powerpc64__ 354 MMUMETHOD(mmu_page_array_startup, moea64_page_array_startup), 355 #endif 356 357 /* Internal interfaces */ 358 MMUMETHOD(mmu_mapdev, moea64_mapdev), 359 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 360 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 361 MMUMETHOD(mmu_kextract, moea64_kextract), 362 MMUMETHOD(mmu_kenter, moea64_kenter), 363 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 364 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 365 MMUMETHOD(mmu_scan_init, moea64_scan_init), 366 MMUMETHOD(mmu_scan_pmap, moea64_scan_pmap), 367 MMUMETHOD(mmu_dump_pmap_init, moea64_dump_pmap_init), 368 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 369 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 370 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 371 372 { 0, 0 } 373 }; 374 375 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 376 377 static struct pvo_head * 378 vm_page_to_pvoh(vm_page_t m) 379 { 380 381 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 382 return (&m->md.mdpg_pvoh); 383 } 384 385 static struct pvo_entry * 386 alloc_pvo_entry(int bootstrap) 387 { 388 struct pvo_entry *pvo; 389 390 if (!moea64_initialized || bootstrap) { 391 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 392 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 393 "Try setting machdep.moea64_bpvo_pool_size tunable", 394 __func__, moea64_bpvo_pool_index, 395 moea64_bpvo_pool_size, 396 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 397 } 398 pvo = &moea64_bpvo_pool[ 399 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 400 bzero(pvo, sizeof(*pvo)); 401 pvo->pvo_vaddr = PVO_BOOTSTRAP; 402 } else 403 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 404 405 return (pvo); 406 } 407 408 409 static void 410 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 411 { 412 uint64_t vsid; 413 uint64_t hash; 414 int shift; 415 416 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 417 418 pvo->pvo_pmap = pmap; 419 va &= ~ADDR_POFF; 420 pvo->pvo_vaddr |= va; 421 vsid = va_to_vsid(pmap, va); 422 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 423 | (vsid << 16); 424 425 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 426 ADDR_PIDX_SHFT; 427 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 428 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 429 } 430 431 static void 432 free_pvo_entry(struct pvo_entry *pvo) 433 { 434 435 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 436 uma_zfree(moea64_pvo_zone, pvo); 437 } 438 439 void 440 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 441 { 442 443 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 444 lpte->pte_hi |= LPTE_VALID; 445 446 if (pvo->pvo_vaddr & PVO_LARGE) 447 lpte->pte_hi |= LPTE_BIG; 448 if (pvo->pvo_vaddr & PVO_WIRED) 449 lpte->pte_hi |= LPTE_WIRED; 450 if (pvo->pvo_vaddr & PVO_HID) 451 lpte->pte_hi |= LPTE_HID; 452 453 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 454 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 455 lpte->pte_lo |= LPTE_BW; 456 else 457 lpte->pte_lo |= LPTE_BR; 458 459 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 460 lpte->pte_lo |= LPTE_NOEXEC; 461 } 462 463 static __inline uint64_t 464 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 465 { 466 uint64_t pte_lo; 467 int i; 468 469 if (ma != VM_MEMATTR_DEFAULT) { 470 switch (ma) { 471 case VM_MEMATTR_UNCACHEABLE: 472 return (LPTE_I | LPTE_G); 473 case VM_MEMATTR_CACHEABLE: 474 return (LPTE_M); 475 case VM_MEMATTR_WRITE_COMBINING: 476 case VM_MEMATTR_WRITE_BACK: 477 case VM_MEMATTR_PREFETCHABLE: 478 return (LPTE_I); 479 case VM_MEMATTR_WRITE_THROUGH: 480 return (LPTE_W | LPTE_M); 481 } 482 } 483 484 /* 485 * Assume the page is cache inhibited and access is guarded unless 486 * it's in our available memory array. 487 */ 488 pte_lo = LPTE_I | LPTE_G; 489 for (i = 0; i < pregions_sz; i++) { 490 if ((pa >= pregions[i].mr_start) && 491 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 492 pte_lo &= ~(LPTE_I | LPTE_G); 493 pte_lo |= LPTE_M; 494 break; 495 } 496 } 497 498 return pte_lo; 499 } 500 501 /* 502 * Quick sort callout for comparing memory regions. 503 */ 504 static int om_cmp(const void *a, const void *b); 505 506 static int 507 om_cmp(const void *a, const void *b) 508 { 509 const struct ofw_map *mapa; 510 const struct ofw_map *mapb; 511 512 mapa = a; 513 mapb = b; 514 if (mapa->om_pa < mapb->om_pa) 515 return (-1); 516 else if (mapa->om_pa > mapb->om_pa) 517 return (1); 518 else 519 return (0); 520 } 521 522 static void 523 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 524 { 525 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 526 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 527 struct pvo_entry *pvo; 528 register_t msr; 529 vm_offset_t off; 530 vm_paddr_t pa_base; 531 int i, j; 532 533 bzero(translations, sz); 534 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 535 sizeof(acells)); 536 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 537 panic("moea64_bootstrap: can't get ofw translations"); 538 539 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 540 sz /= sizeof(cell_t); 541 for (i = 0, j = 0; i < sz; j++) { 542 translations[j].om_va = trans_cells[i++]; 543 translations[j].om_len = trans_cells[i++]; 544 translations[j].om_pa = trans_cells[i++]; 545 if (acells == 2) { 546 translations[j].om_pa <<= 32; 547 translations[j].om_pa |= trans_cells[i++]; 548 } 549 translations[j].om_mode = trans_cells[i++]; 550 } 551 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 552 i, sz)); 553 554 sz = j; 555 qsort(translations, sz, sizeof (*translations), om_cmp); 556 557 for (i = 0; i < sz; i++) { 558 pa_base = translations[i].om_pa; 559 #ifndef __powerpc64__ 560 if ((translations[i].om_pa >> 32) != 0) 561 panic("OFW translations above 32-bit boundary!"); 562 #endif 563 564 if (pa_base % PAGE_SIZE) 565 panic("OFW translation not page-aligned (phys)!"); 566 if (translations[i].om_va % PAGE_SIZE) 567 panic("OFW translation not page-aligned (virt)!"); 568 569 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 570 pa_base, translations[i].om_va, translations[i].om_len); 571 572 /* Now enter the pages for this mapping */ 573 574 DISABLE_TRANS(msr); 575 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 576 /* If this address is direct-mapped, skip remapping */ 577 if (hw_direct_map && 578 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 579 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 580 == LPTE_M) 581 continue; 582 583 PMAP_LOCK(kernel_pmap); 584 pvo = moea64_pvo_find_va(kernel_pmap, 585 translations[i].om_va + off); 586 PMAP_UNLOCK(kernel_pmap); 587 if (pvo != NULL) 588 continue; 589 590 moea64_kenter(mmup, translations[i].om_va + off, 591 pa_base + off); 592 } 593 ENABLE_TRANS(msr); 594 } 595 } 596 597 #ifdef __powerpc64__ 598 static void 599 moea64_probe_large_page(void) 600 { 601 uint16_t pvr = mfpvr() >> 16; 602 603 switch (pvr) { 604 case IBM970: 605 case IBM970FX: 606 case IBM970MP: 607 powerpc_sync(); isync(); 608 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 609 powerpc_sync(); isync(); 610 611 /* FALLTHROUGH */ 612 default: 613 if (moea64_large_page_size == 0) { 614 moea64_large_page_size = 0x1000000; /* 16 MB */ 615 moea64_large_page_shift = 24; 616 } 617 } 618 619 moea64_large_page_mask = moea64_large_page_size - 1; 620 } 621 622 static void 623 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 624 { 625 struct slb *cache; 626 struct slb entry; 627 uint64_t esid, slbe; 628 uint64_t i; 629 630 cache = PCPU_GET(aim.slb); 631 esid = va >> ADDR_SR_SHFT; 632 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 633 634 for (i = 0; i < 64; i++) { 635 if (cache[i].slbe == (slbe | i)) 636 return; 637 } 638 639 entry.slbe = slbe; 640 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 641 if (large) 642 entry.slbv |= SLBV_L; 643 644 slb_insert_kernel(entry.slbe, entry.slbv); 645 } 646 #endif 647 648 static int 649 moea64_kenter_large(mmu_t mmup, vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 650 { 651 struct pvo_entry *pvo; 652 uint64_t pte_lo; 653 int error; 654 655 pte_lo = LPTE_M; 656 pte_lo |= attr; 657 658 pvo = alloc_pvo_entry(bootstrap); 659 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 660 init_pvo_entry(pvo, kernel_pmap, va); 661 662 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 663 VM_PROT_EXECUTE; 664 pvo->pvo_pte.pa = pa | pte_lo; 665 error = moea64_pvo_enter(mmup, pvo, NULL, NULL); 666 if (error != 0) 667 panic("Error %d inserting large page\n", error); 668 return (0); 669 } 670 671 static void 672 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 673 vm_offset_t kernelend) 674 { 675 register_t msr; 676 vm_paddr_t pa, pkernelstart, pkernelend; 677 vm_offset_t size, off; 678 uint64_t pte_lo; 679 int i; 680 681 if (moea64_large_page_size == 0) 682 hw_direct_map = 0; 683 684 DISABLE_TRANS(msr); 685 if (hw_direct_map) { 686 PMAP_LOCK(kernel_pmap); 687 for (i = 0; i < pregions_sz; i++) { 688 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 689 pregions[i].mr_size; pa += moea64_large_page_size) { 690 pte_lo = LPTE_M; 691 if (pa & moea64_large_page_mask) { 692 pa &= moea64_large_page_mask; 693 pte_lo |= LPTE_G; 694 } 695 if (pa + moea64_large_page_size > 696 pregions[i].mr_start + pregions[i].mr_size) 697 pte_lo |= LPTE_G; 698 699 moea64_kenter_large(mmup, PHYS_TO_DMAP(pa), pa, pte_lo, 1); 700 } 701 } 702 PMAP_UNLOCK(kernel_pmap); 703 } 704 705 /* 706 * Make sure the kernel and BPVO pool stay mapped on systems either 707 * without a direct map or on which the kernel is not already executing 708 * out of the direct-mapped region. 709 */ 710 if (kernelstart < DMAP_BASE_ADDRESS) { 711 /* 712 * For pre-dmap execution, we need to use identity mapping 713 * because we will be operating with the mmu on but in the 714 * wrong address configuration until we __restartkernel(). 715 */ 716 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 717 pa += PAGE_SIZE) 718 moea64_kenter(mmup, pa, pa); 719 } else if (!hw_direct_map) { 720 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 721 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 722 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 723 pa += PAGE_SIZE) 724 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 725 } 726 727 if (!hw_direct_map) { 728 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 729 off = (vm_offset_t)(moea64_bpvo_pool); 730 for (pa = off; pa < off + size; pa += PAGE_SIZE) 731 moea64_kenter(mmup, pa, pa); 732 733 /* Map exception vectors */ 734 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 735 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 736 } 737 ENABLE_TRANS(msr); 738 739 /* 740 * Allow user to override unmapped_buf_allowed for testing. 741 * XXXKIB Only direct map implementation was tested. 742 */ 743 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 744 &unmapped_buf_allowed)) 745 unmapped_buf_allowed = hw_direct_map; 746 } 747 748 /* Quick sort callout for comparing physical addresses. */ 749 static int 750 pa_cmp(const void *a, const void *b) 751 { 752 const vm_paddr_t *pa = a, *pb = b; 753 754 if (*pa < *pb) 755 return (-1); 756 else if (*pa > *pb) 757 return (1); 758 else 759 return (0); 760 } 761 762 void 763 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 764 { 765 int i, j; 766 vm_size_t physsz, hwphyssz; 767 vm_paddr_t kernelphysstart, kernelphysend; 768 int rm_pavail; 769 770 #ifndef __powerpc64__ 771 /* We don't have a direct map since there is no BAT */ 772 hw_direct_map = 0; 773 774 /* Make sure battable is zero, since we have no BAT */ 775 for (i = 0; i < 16; i++) { 776 battable[i].batu = 0; 777 battable[i].batl = 0; 778 } 779 #else 780 moea64_probe_large_page(); 781 782 /* Use a direct map if we have large page support */ 783 if (moea64_large_page_size > 0) 784 hw_direct_map = 1; 785 else 786 hw_direct_map = 0; 787 788 /* Install trap handlers for SLBs */ 789 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 790 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 791 __syncicache((void *)EXC_DSE, 0x80); 792 __syncicache((void *)EXC_ISE, 0x80); 793 #endif 794 795 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 796 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 797 798 /* Get physical memory regions from firmware */ 799 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 800 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 801 802 if (PHYS_AVAIL_ENTRIES < regions_sz) 803 panic("moea64_bootstrap: phys_avail too small"); 804 805 phys_avail_count = 0; 806 physsz = 0; 807 hwphyssz = 0; 808 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 809 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 810 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 811 regions[i].mr_start, regions[i].mr_start + 812 regions[i].mr_size, regions[i].mr_size); 813 if (hwphyssz != 0 && 814 (physsz + regions[i].mr_size) >= hwphyssz) { 815 if (physsz < hwphyssz) { 816 phys_avail[j] = regions[i].mr_start; 817 phys_avail[j + 1] = regions[i].mr_start + 818 hwphyssz - physsz; 819 physsz = hwphyssz; 820 phys_avail_count++; 821 dump_avail[j] = phys_avail[j]; 822 dump_avail[j + 1] = phys_avail[j + 1]; 823 } 824 break; 825 } 826 phys_avail[j] = regions[i].mr_start; 827 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 828 phys_avail_count++; 829 physsz += regions[i].mr_size; 830 dump_avail[j] = phys_avail[j]; 831 dump_avail[j + 1] = phys_avail[j + 1]; 832 } 833 834 /* Check for overlap with the kernel and exception vectors */ 835 rm_pavail = 0; 836 for (j = 0; j < 2*phys_avail_count; j+=2) { 837 if (phys_avail[j] < EXC_LAST) 838 phys_avail[j] += EXC_LAST; 839 840 if (phys_avail[j] >= kernelphysstart && 841 phys_avail[j+1] <= kernelphysend) { 842 phys_avail[j] = phys_avail[j+1] = ~0; 843 rm_pavail++; 844 continue; 845 } 846 847 if (kernelphysstart >= phys_avail[j] && 848 kernelphysstart < phys_avail[j+1]) { 849 if (kernelphysend < phys_avail[j+1]) { 850 phys_avail[2*phys_avail_count] = 851 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 852 phys_avail[2*phys_avail_count + 1] = 853 phys_avail[j+1]; 854 phys_avail_count++; 855 } 856 857 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 858 } 859 860 if (kernelphysend >= phys_avail[j] && 861 kernelphysend < phys_avail[j+1]) { 862 if (kernelphysstart > phys_avail[j]) { 863 phys_avail[2*phys_avail_count] = phys_avail[j]; 864 phys_avail[2*phys_avail_count + 1] = 865 kernelphysstart & ~PAGE_MASK; 866 phys_avail_count++; 867 } 868 869 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 870 PAGE_SIZE; 871 } 872 } 873 874 /* Remove physical available regions marked for removal (~0) */ 875 if (rm_pavail) { 876 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 877 pa_cmp); 878 phys_avail_count -= rm_pavail; 879 for (i = 2*phys_avail_count; 880 i < 2*(phys_avail_count + rm_pavail); i+=2) 881 phys_avail[i] = phys_avail[i+1] = 0; 882 } 883 884 physmem = btoc(physsz); 885 886 #ifdef PTEGCOUNT 887 moea64_pteg_count = PTEGCOUNT; 888 #else 889 moea64_pteg_count = 0x1000; 890 891 while (moea64_pteg_count < physmem) 892 moea64_pteg_count <<= 1; 893 894 moea64_pteg_count >>= 1; 895 #endif /* PTEGCOUNT */ 896 } 897 898 void 899 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 900 { 901 int i; 902 903 /* 904 * Set PTEG mask 905 */ 906 moea64_pteg_mask = moea64_pteg_count - 1; 907 908 /* 909 * Initialize SLB table lock and page locks 910 */ 911 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 912 for (i = 0; i < PV_LOCK_COUNT; i++) 913 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 914 915 /* 916 * Initialise the bootstrap pvo pool. 917 */ 918 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 919 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 920 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 921 moea64_bpvo_pool_index = 0; 922 923 /* Place at address usable through the direct map */ 924 if (hw_direct_map) 925 moea64_bpvo_pool = (struct pvo_entry *) 926 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 927 928 /* 929 * Make sure kernel vsid is allocated as well as VSID 0. 930 */ 931 #ifndef __powerpc64__ 932 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 933 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 934 moea64_vsid_bitmap[0] |= 1; 935 #endif 936 937 /* 938 * Initialize the kernel pmap (which is statically allocated). 939 */ 940 #ifdef __powerpc64__ 941 for (i = 0; i < 64; i++) { 942 pcpup->pc_aim.slb[i].slbv = 0; 943 pcpup->pc_aim.slb[i].slbe = 0; 944 } 945 #else 946 for (i = 0; i < 16; i++) 947 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 948 #endif 949 950 kernel_pmap->pmap_phys = kernel_pmap; 951 CPU_FILL(&kernel_pmap->pm_active); 952 RB_INIT(&kernel_pmap->pmap_pvo); 953 954 PMAP_LOCK_INIT(kernel_pmap); 955 956 /* 957 * Now map in all the other buffers we allocated earlier 958 */ 959 960 moea64_setup_direct_map(mmup, kernelstart, kernelend); 961 } 962 963 void 964 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 965 { 966 ihandle_t mmui; 967 phandle_t chosen; 968 phandle_t mmu; 969 ssize_t sz; 970 int i; 971 vm_offset_t pa, va; 972 void *dpcpu; 973 974 /* 975 * Set up the Open Firmware pmap and add its mappings if not in real 976 * mode. 977 */ 978 979 chosen = OF_finddevice("/chosen"); 980 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 981 mmu = OF_instance_to_package(mmui); 982 if (mmu == -1 || 983 (sz = OF_getproplen(mmu, "translations")) == -1) 984 sz = 0; 985 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 986 panic("moea64_bootstrap: too many ofw translations"); 987 988 if (sz > 0) 989 moea64_add_ofw_mappings(mmup, mmu, sz); 990 } 991 992 /* 993 * Calculate the last available physical address. 994 */ 995 Maxmem = 0; 996 for (i = 0; phys_avail[i + 2] != 0; i += 2) 997 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 998 999 /* 1000 * Initialize MMU. 1001 */ 1002 MMU_CPU_BOOTSTRAP(mmup,0); 1003 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1004 pmap_bootstrapped++; 1005 1006 /* 1007 * Set the start and end of kva. 1008 */ 1009 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1010 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1011 1012 /* 1013 * Map the entire KVA range into the SLB. We must not fault there. 1014 */ 1015 #ifdef __powerpc64__ 1016 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1017 moea64_bootstrap_slb_prefault(va, 0); 1018 #endif 1019 1020 /* 1021 * Remap any early IO mappings (console framebuffer, etc.) 1022 */ 1023 bs_remap_earlyboot(); 1024 1025 /* 1026 * Figure out how far we can extend virtual_end into segment 16 1027 * without running into existing mappings. Segment 16 is guaranteed 1028 * to contain neither RAM nor devices (at least on Apple hardware), 1029 * but will generally contain some OFW mappings we should not 1030 * step on. 1031 */ 1032 1033 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1034 PMAP_LOCK(kernel_pmap); 1035 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1036 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1037 virtual_end += PAGE_SIZE; 1038 PMAP_UNLOCK(kernel_pmap); 1039 #endif 1040 1041 /* 1042 * Allocate a kernel stack with a guard page for thread0 and map it 1043 * into the kernel page map. 1044 */ 1045 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1046 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1047 virtual_avail = va + kstack_pages * PAGE_SIZE; 1048 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1049 thread0.td_kstack = va; 1050 thread0.td_kstack_pages = kstack_pages; 1051 for (i = 0; i < kstack_pages; i++) { 1052 moea64_kenter(mmup, va, pa); 1053 pa += PAGE_SIZE; 1054 va += PAGE_SIZE; 1055 } 1056 1057 /* 1058 * Allocate virtual address space for the message buffer. 1059 */ 1060 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1061 msgbufp = (struct msgbuf *)virtual_avail; 1062 va = virtual_avail; 1063 virtual_avail += round_page(msgbufsize); 1064 while (va < virtual_avail) { 1065 moea64_kenter(mmup, va, pa); 1066 pa += PAGE_SIZE; 1067 va += PAGE_SIZE; 1068 } 1069 1070 /* 1071 * Allocate virtual address space for the dynamic percpu area. 1072 */ 1073 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1074 dpcpu = (void *)virtual_avail; 1075 va = virtual_avail; 1076 virtual_avail += DPCPU_SIZE; 1077 while (va < virtual_avail) { 1078 moea64_kenter(mmup, va, pa); 1079 pa += PAGE_SIZE; 1080 va += PAGE_SIZE; 1081 } 1082 dpcpu_init(dpcpu, curcpu); 1083 1084 crashdumpmap = (caddr_t)virtual_avail; 1085 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1086 1087 /* 1088 * Allocate some things for page zeroing. We put this directly 1089 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1090 * of the PVO book-keeping or other parts of the VM system 1091 * from even knowing that this hack exists. 1092 */ 1093 1094 if (!hw_direct_map) { 1095 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1096 MTX_DEF); 1097 for (i = 0; i < 2; i++) { 1098 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1099 virtual_end -= PAGE_SIZE; 1100 1101 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1102 1103 PMAP_LOCK(kernel_pmap); 1104 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1105 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1106 PMAP_UNLOCK(kernel_pmap); 1107 } 1108 } 1109 1110 numa_mem_regions(&numa_pregions, &numapregions_sz); 1111 } 1112 1113 static void 1114 moea64_pmap_init_qpages(void) 1115 { 1116 struct pcpu *pc; 1117 int i; 1118 1119 if (hw_direct_map) 1120 return; 1121 1122 CPU_FOREACH(i) { 1123 pc = pcpu_find(i); 1124 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1125 if (pc->pc_qmap_addr == 0) 1126 panic("pmap_init_qpages: unable to allocate KVA"); 1127 PMAP_LOCK(kernel_pmap); 1128 pc->pc_aim.qmap_pvo = 1129 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1130 PMAP_UNLOCK(kernel_pmap); 1131 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1132 } 1133 } 1134 1135 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1136 1137 /* 1138 * Activate a user pmap. This mostly involves setting some non-CPU 1139 * state. 1140 */ 1141 void 1142 moea64_activate(mmu_t mmu, struct thread *td) 1143 { 1144 pmap_t pm; 1145 1146 pm = &td->td_proc->p_vmspace->vm_pmap; 1147 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1148 1149 #ifdef __powerpc64__ 1150 PCPU_SET(aim.userslb, pm->pm_slb); 1151 __asm __volatile("slbmte %0, %1; isync" :: 1152 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1153 #else 1154 PCPU_SET(curpmap, pm->pmap_phys); 1155 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1156 #endif 1157 } 1158 1159 void 1160 moea64_deactivate(mmu_t mmu, struct thread *td) 1161 { 1162 pmap_t pm; 1163 1164 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1165 1166 pm = &td->td_proc->p_vmspace->vm_pmap; 1167 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1168 #ifdef __powerpc64__ 1169 PCPU_SET(aim.userslb, NULL); 1170 #else 1171 PCPU_SET(curpmap, NULL); 1172 #endif 1173 } 1174 1175 void 1176 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1177 { 1178 struct pvo_entry key, *pvo; 1179 vm_page_t m; 1180 int64_t refchg; 1181 1182 key.pvo_vaddr = sva; 1183 PMAP_LOCK(pm); 1184 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1185 pvo != NULL && PVO_VADDR(pvo) < eva; 1186 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1187 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1188 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1189 pvo); 1190 pvo->pvo_vaddr &= ~PVO_WIRED; 1191 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1192 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1193 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1194 if (refchg < 0) 1195 refchg = LPTE_CHG; 1196 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1197 1198 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1199 if (refchg & LPTE_CHG) 1200 vm_page_dirty(m); 1201 if (refchg & LPTE_REF) 1202 vm_page_aflag_set(m, PGA_REFERENCED); 1203 } 1204 pm->pm_stats.wired_count--; 1205 } 1206 PMAP_UNLOCK(pm); 1207 } 1208 1209 /* 1210 * This goes through and sets the physical address of our 1211 * special scratch PTE to the PA we want to zero or copy. Because 1212 * of locking issues (this can get called in pvo_enter() by 1213 * the UMA allocator), we can't use most other utility functions here 1214 */ 1215 1216 static __inline 1217 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1218 { 1219 struct pvo_entry *pvo; 1220 1221 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1222 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1223 1224 pvo = moea64_scratchpage_pvo[which]; 1225 PMAP_LOCK(pvo->pvo_pmap); 1226 pvo->pvo_pte.pa = 1227 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1228 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1229 PMAP_UNLOCK(pvo->pvo_pmap); 1230 isync(); 1231 } 1232 1233 void 1234 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1235 { 1236 vm_offset_t dst; 1237 vm_offset_t src; 1238 1239 dst = VM_PAGE_TO_PHYS(mdst); 1240 src = VM_PAGE_TO_PHYS(msrc); 1241 1242 if (hw_direct_map) { 1243 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1244 PAGE_SIZE); 1245 } else { 1246 mtx_lock(&moea64_scratchpage_mtx); 1247 1248 moea64_set_scratchpage_pa(mmu, 0, src); 1249 moea64_set_scratchpage_pa(mmu, 1, dst); 1250 1251 bcopy((void *)moea64_scratchpage_va[0], 1252 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1253 1254 mtx_unlock(&moea64_scratchpage_mtx); 1255 } 1256 } 1257 1258 static inline void 1259 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1260 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1261 { 1262 void *a_cp, *b_cp; 1263 vm_offset_t a_pg_offset, b_pg_offset; 1264 int cnt; 1265 1266 while (xfersize > 0) { 1267 a_pg_offset = a_offset & PAGE_MASK; 1268 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1269 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1270 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1271 a_pg_offset; 1272 b_pg_offset = b_offset & PAGE_MASK; 1273 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1274 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1275 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1276 b_pg_offset; 1277 bcopy(a_cp, b_cp, cnt); 1278 a_offset += cnt; 1279 b_offset += cnt; 1280 xfersize -= cnt; 1281 } 1282 } 1283 1284 static inline void 1285 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1286 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1287 { 1288 void *a_cp, *b_cp; 1289 vm_offset_t a_pg_offset, b_pg_offset; 1290 int cnt; 1291 1292 mtx_lock(&moea64_scratchpage_mtx); 1293 while (xfersize > 0) { 1294 a_pg_offset = a_offset & PAGE_MASK; 1295 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1296 moea64_set_scratchpage_pa(mmu, 0, 1297 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1298 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1299 b_pg_offset = b_offset & PAGE_MASK; 1300 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1301 moea64_set_scratchpage_pa(mmu, 1, 1302 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1303 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1304 bcopy(a_cp, b_cp, cnt); 1305 a_offset += cnt; 1306 b_offset += cnt; 1307 xfersize -= cnt; 1308 } 1309 mtx_unlock(&moea64_scratchpage_mtx); 1310 } 1311 1312 void 1313 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1314 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1315 { 1316 1317 if (hw_direct_map) { 1318 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1319 xfersize); 1320 } else { 1321 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1322 xfersize); 1323 } 1324 } 1325 1326 void 1327 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1328 { 1329 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1330 1331 if (size + off > PAGE_SIZE) 1332 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1333 1334 if (hw_direct_map) { 1335 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1336 } else { 1337 mtx_lock(&moea64_scratchpage_mtx); 1338 moea64_set_scratchpage_pa(mmu, 0, pa); 1339 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1340 mtx_unlock(&moea64_scratchpage_mtx); 1341 } 1342 } 1343 1344 /* 1345 * Zero a page of physical memory by temporarily mapping it 1346 */ 1347 void 1348 moea64_zero_page(mmu_t mmu, vm_page_t m) 1349 { 1350 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1351 vm_offset_t va, off; 1352 1353 if (!hw_direct_map) { 1354 mtx_lock(&moea64_scratchpage_mtx); 1355 1356 moea64_set_scratchpage_pa(mmu, 0, pa); 1357 va = moea64_scratchpage_va[0]; 1358 } else { 1359 va = PHYS_TO_DMAP(pa); 1360 } 1361 1362 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1363 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1364 1365 if (!hw_direct_map) 1366 mtx_unlock(&moea64_scratchpage_mtx); 1367 } 1368 1369 vm_offset_t 1370 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1371 { 1372 struct pvo_entry *pvo; 1373 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1374 1375 if (hw_direct_map) 1376 return (PHYS_TO_DMAP(pa)); 1377 1378 /* 1379 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1380 * a critical section and access the PCPU data like on i386. 1381 * Instead, pin the thread and grab the PCPU lock to prevent 1382 * a preempting thread from using the same PCPU data. 1383 */ 1384 sched_pin(); 1385 1386 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1387 pvo = PCPU_GET(aim.qmap_pvo); 1388 1389 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1390 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1391 (uint64_t)pa; 1392 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1393 isync(); 1394 1395 return (PCPU_GET(qmap_addr)); 1396 } 1397 1398 void 1399 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1400 { 1401 if (hw_direct_map) 1402 return; 1403 1404 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1405 KASSERT(PCPU_GET(qmap_addr) == addr, 1406 ("moea64_quick_remove_page: invalid address")); 1407 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1408 sched_unpin(); 1409 } 1410 1411 /* 1412 * Map the given physical page at the specified virtual address in the 1413 * target pmap with the protection requested. If specified the page 1414 * will be wired down. 1415 */ 1416 1417 int 1418 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1419 vm_prot_t prot, u_int flags, int8_t psind) 1420 { 1421 struct pvo_entry *pvo, *oldpvo; 1422 struct pvo_head *pvo_head; 1423 uint64_t pte_lo; 1424 int error; 1425 1426 if ((m->oflags & VPO_UNMANAGED) == 0) { 1427 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1428 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1429 else 1430 VM_OBJECT_ASSERT_LOCKED(m->object); 1431 } 1432 1433 pvo = alloc_pvo_entry(0); 1434 if (pvo == NULL) 1435 return (KERN_RESOURCE_SHORTAGE); 1436 pvo->pvo_pmap = NULL; /* to be filled in later */ 1437 pvo->pvo_pte.prot = prot; 1438 1439 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1440 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1441 1442 if ((flags & PMAP_ENTER_WIRED) != 0) 1443 pvo->pvo_vaddr |= PVO_WIRED; 1444 1445 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1446 pvo_head = NULL; 1447 } else { 1448 pvo_head = &m->md.mdpg_pvoh; 1449 pvo->pvo_vaddr |= PVO_MANAGED; 1450 } 1451 1452 PV_PAGE_LOCK(m); 1453 PMAP_LOCK(pmap); 1454 if (pvo->pvo_pmap == NULL) 1455 init_pvo_entry(pvo, pmap, va); 1456 if (prot & VM_PROT_WRITE) 1457 if (pmap_bootstrapped && 1458 (m->oflags & VPO_UNMANAGED) == 0) 1459 vm_page_aflag_set(m, PGA_WRITEABLE); 1460 1461 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1462 if (error == EEXIST) { 1463 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1464 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1465 oldpvo->pvo_pte.prot == prot) { 1466 /* Identical mapping already exists */ 1467 error = 0; 1468 1469 /* If not in page table, reinsert it */ 1470 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1471 STAT_MOEA64(moea64_pte_overflow--); 1472 MOEA64_PTE_INSERT(mmu, oldpvo); 1473 } 1474 1475 /* Then just clean up and go home */ 1476 PV_PAGE_UNLOCK(m); 1477 PMAP_UNLOCK(pmap); 1478 free_pvo_entry(pvo); 1479 goto out; 1480 } else { 1481 /* Otherwise, need to kill it first */ 1482 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1483 "mapping does not match new mapping")); 1484 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1485 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1486 } 1487 } 1488 PMAP_UNLOCK(pmap); 1489 PV_PAGE_UNLOCK(m); 1490 1491 /* Free any dead pages */ 1492 if (error == EEXIST) { 1493 moea64_pvo_remove_from_page(mmu, oldpvo); 1494 free_pvo_entry(oldpvo); 1495 } 1496 1497 out: 1498 /* 1499 * Flush the page from the instruction cache if this page is 1500 * mapped executable and cacheable. 1501 */ 1502 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1503 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1504 vm_page_aflag_set(m, PGA_EXECUTABLE); 1505 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1506 } 1507 return (KERN_SUCCESS); 1508 } 1509 1510 static void 1511 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1512 vm_size_t sz) 1513 { 1514 1515 /* 1516 * This is much trickier than on older systems because 1517 * we can't sync the icache on physical addresses directly 1518 * without a direct map. Instead we check a couple of cases 1519 * where the memory is already mapped in and, failing that, 1520 * use the same trick we use for page zeroing to create 1521 * a temporary mapping for this physical address. 1522 */ 1523 1524 if (!pmap_bootstrapped) { 1525 /* 1526 * If PMAP is not bootstrapped, we are likely to be 1527 * in real mode. 1528 */ 1529 __syncicache((void *)(uintptr_t)pa, sz); 1530 } else if (pmap == kernel_pmap) { 1531 __syncicache((void *)va, sz); 1532 } else if (hw_direct_map) { 1533 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1534 } else { 1535 /* Use the scratch page to set up a temp mapping */ 1536 1537 mtx_lock(&moea64_scratchpage_mtx); 1538 1539 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1540 __syncicache((void *)(moea64_scratchpage_va[1] + 1541 (va & ADDR_POFF)), sz); 1542 1543 mtx_unlock(&moea64_scratchpage_mtx); 1544 } 1545 } 1546 1547 /* 1548 * Maps a sequence of resident pages belonging to the same object. 1549 * The sequence begins with the given page m_start. This page is 1550 * mapped at the given virtual address start. Each subsequent page is 1551 * mapped at a virtual address that is offset from start by the same 1552 * amount as the page is offset from m_start within the object. The 1553 * last page in the sequence is the page with the largest offset from 1554 * m_start that can be mapped at a virtual address less than the given 1555 * virtual address end. Not every virtual page between start and end 1556 * is mapped; only those for which a resident page exists with the 1557 * corresponding offset from m_start are mapped. 1558 */ 1559 void 1560 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1561 vm_page_t m_start, vm_prot_t prot) 1562 { 1563 vm_page_t m; 1564 vm_pindex_t diff, psize; 1565 1566 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1567 1568 psize = atop(end - start); 1569 m = m_start; 1570 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1571 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1572 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1573 PMAP_ENTER_QUICK_LOCKED, 0); 1574 m = TAILQ_NEXT(m, listq); 1575 } 1576 } 1577 1578 void 1579 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1580 vm_prot_t prot) 1581 { 1582 1583 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1584 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1585 } 1586 1587 vm_paddr_t 1588 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1589 { 1590 struct pvo_entry *pvo; 1591 vm_paddr_t pa; 1592 1593 PMAP_LOCK(pm); 1594 pvo = moea64_pvo_find_va(pm, va); 1595 if (pvo == NULL) 1596 pa = 0; 1597 else 1598 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1599 PMAP_UNLOCK(pm); 1600 1601 return (pa); 1602 } 1603 1604 /* 1605 * Atomically extract and hold the physical page with the given 1606 * pmap and virtual address pair if that mapping permits the given 1607 * protection. 1608 */ 1609 vm_page_t 1610 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1611 { 1612 struct pvo_entry *pvo; 1613 vm_page_t m; 1614 1615 m = NULL; 1616 PMAP_LOCK(pmap); 1617 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1618 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1619 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1620 if (!vm_page_wire_mapped(m)) 1621 m = NULL; 1622 } 1623 PMAP_UNLOCK(pmap); 1624 return (m); 1625 } 1626 1627 static mmu_t installed_mmu; 1628 1629 static void * 1630 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1631 uint8_t *flags, int wait) 1632 { 1633 struct pvo_entry *pvo; 1634 vm_offset_t va; 1635 vm_page_t m; 1636 int needed_lock; 1637 1638 /* 1639 * This entire routine is a horrible hack to avoid bothering kmem 1640 * for new KVA addresses. Because this can get called from inside 1641 * kmem allocation routines, calling kmem for a new address here 1642 * can lead to multiply locking non-recursive mutexes. 1643 */ 1644 1645 *flags = UMA_SLAB_PRIV; 1646 needed_lock = !PMAP_LOCKED(kernel_pmap); 1647 1648 m = vm_page_alloc_domain(NULL, 0, domain, 1649 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1650 if (m == NULL) 1651 return (NULL); 1652 1653 va = VM_PAGE_TO_PHYS(m); 1654 1655 pvo = alloc_pvo_entry(1 /* bootstrap */); 1656 1657 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1658 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1659 1660 if (needed_lock) 1661 PMAP_LOCK(kernel_pmap); 1662 1663 init_pvo_entry(pvo, kernel_pmap, va); 1664 pvo->pvo_vaddr |= PVO_WIRED; 1665 1666 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1667 1668 if (needed_lock) 1669 PMAP_UNLOCK(kernel_pmap); 1670 1671 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1672 bzero((void *)va, PAGE_SIZE); 1673 1674 return (void *)va; 1675 } 1676 1677 extern int elf32_nxstack; 1678 1679 void 1680 moea64_init(mmu_t mmu) 1681 { 1682 1683 CTR0(KTR_PMAP, "moea64_init"); 1684 1685 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1686 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1687 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1688 1689 if (!hw_direct_map) { 1690 installed_mmu = mmu; 1691 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1692 } 1693 1694 #ifdef COMPAT_FREEBSD32 1695 elf32_nxstack = 1; 1696 #endif 1697 1698 moea64_initialized = TRUE; 1699 } 1700 1701 boolean_t 1702 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1703 { 1704 1705 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1706 ("moea64_is_referenced: page %p is not managed", m)); 1707 1708 return (moea64_query_bit(mmu, m, LPTE_REF)); 1709 } 1710 1711 boolean_t 1712 moea64_is_modified(mmu_t mmu, vm_page_t m) 1713 { 1714 1715 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1716 ("moea64_is_modified: page %p is not managed", m)); 1717 1718 /* 1719 * If the page is not busied then this check is racy. 1720 */ 1721 if (!pmap_page_is_write_mapped(m)) 1722 return (FALSE); 1723 1724 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1725 } 1726 1727 boolean_t 1728 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1729 { 1730 struct pvo_entry *pvo; 1731 boolean_t rv = TRUE; 1732 1733 PMAP_LOCK(pmap); 1734 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1735 if (pvo != NULL) 1736 rv = FALSE; 1737 PMAP_UNLOCK(pmap); 1738 return (rv); 1739 } 1740 1741 void 1742 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1743 { 1744 1745 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1746 ("moea64_clear_modify: page %p is not managed", m)); 1747 vm_page_assert_busied(m); 1748 1749 if (!pmap_page_is_write_mapped(m)) 1750 return; 1751 moea64_clear_bit(mmu, m, LPTE_CHG); 1752 } 1753 1754 /* 1755 * Clear the write and modified bits in each of the given page's mappings. 1756 */ 1757 void 1758 moea64_remove_write(mmu_t mmu, vm_page_t m) 1759 { 1760 struct pvo_entry *pvo; 1761 int64_t refchg, ret; 1762 pmap_t pmap; 1763 1764 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1765 ("moea64_remove_write: page %p is not managed", m)); 1766 vm_page_assert_busied(m); 1767 1768 if (!pmap_page_is_write_mapped(m)) 1769 return 1770 1771 powerpc_sync(); 1772 PV_PAGE_LOCK(m); 1773 refchg = 0; 1774 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1775 pmap = pvo->pvo_pmap; 1776 PMAP_LOCK(pmap); 1777 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1778 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1779 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1780 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1781 MOEA64_PTE_PROT_UPDATE); 1782 if (ret < 0) 1783 ret = LPTE_CHG; 1784 refchg |= ret; 1785 if (pvo->pvo_pmap == kernel_pmap) 1786 isync(); 1787 } 1788 PMAP_UNLOCK(pmap); 1789 } 1790 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1791 vm_page_dirty(m); 1792 vm_page_aflag_clear(m, PGA_WRITEABLE); 1793 PV_PAGE_UNLOCK(m); 1794 } 1795 1796 /* 1797 * moea64_ts_referenced: 1798 * 1799 * Return a count of reference bits for a page, clearing those bits. 1800 * It is not necessary for every reference bit to be cleared, but it 1801 * is necessary that 0 only be returned when there are truly no 1802 * reference bits set. 1803 * 1804 * XXX: The exact number of bits to check and clear is a matter that 1805 * should be tested and standardized at some point in the future for 1806 * optimal aging of shared pages. 1807 */ 1808 int 1809 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1810 { 1811 1812 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1813 ("moea64_ts_referenced: page %p is not managed", m)); 1814 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1815 } 1816 1817 /* 1818 * Modify the WIMG settings of all mappings for a page. 1819 */ 1820 void 1821 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1822 { 1823 struct pvo_entry *pvo; 1824 int64_t refchg; 1825 pmap_t pmap; 1826 uint64_t lo; 1827 1828 if ((m->oflags & VPO_UNMANAGED) != 0) { 1829 m->md.mdpg_cache_attrs = ma; 1830 return; 1831 } 1832 1833 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1834 1835 PV_PAGE_LOCK(m); 1836 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1837 pmap = pvo->pvo_pmap; 1838 PMAP_LOCK(pmap); 1839 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1840 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1841 pvo->pvo_pte.pa |= lo; 1842 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1843 MOEA64_PTE_INVALIDATE); 1844 if (refchg < 0) 1845 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1846 LPTE_CHG : 0; 1847 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1848 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1849 refchg |= 1850 atomic_readandclear_32(&m->md.mdpg_attrs); 1851 if (refchg & LPTE_CHG) 1852 vm_page_dirty(m); 1853 if (refchg & LPTE_REF) 1854 vm_page_aflag_set(m, PGA_REFERENCED); 1855 } 1856 if (pvo->pvo_pmap == kernel_pmap) 1857 isync(); 1858 } 1859 PMAP_UNLOCK(pmap); 1860 } 1861 m->md.mdpg_cache_attrs = ma; 1862 PV_PAGE_UNLOCK(m); 1863 } 1864 1865 /* 1866 * Map a wired page into kernel virtual address space. 1867 */ 1868 void 1869 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1870 { 1871 int error; 1872 struct pvo_entry *pvo, *oldpvo; 1873 1874 do { 1875 pvo = alloc_pvo_entry(0); 1876 if (pvo == NULL) 1877 vm_wait(NULL); 1878 } while (pvo == NULL); 1879 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1880 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1881 pvo->pvo_vaddr |= PVO_WIRED; 1882 1883 PMAP_LOCK(kernel_pmap); 1884 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1885 if (oldpvo != NULL) 1886 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1887 init_pvo_entry(pvo, kernel_pmap, va); 1888 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1889 PMAP_UNLOCK(kernel_pmap); 1890 1891 /* Free any dead pages */ 1892 if (oldpvo != NULL) { 1893 moea64_pvo_remove_from_page(mmu, oldpvo); 1894 free_pvo_entry(oldpvo); 1895 } 1896 1897 if (error != 0) 1898 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1899 (uintmax_t)pa, error); 1900 } 1901 1902 void 1903 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1904 { 1905 1906 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1907 } 1908 1909 /* 1910 * Extract the physical page address associated with the given kernel virtual 1911 * address. 1912 */ 1913 vm_paddr_t 1914 moea64_kextract(mmu_t mmu, vm_offset_t va) 1915 { 1916 struct pvo_entry *pvo; 1917 vm_paddr_t pa; 1918 1919 /* 1920 * Shortcut the direct-mapped case when applicable. We never put 1921 * anything but 1:1 (or 62-bit aliased) mappings below 1922 * VM_MIN_KERNEL_ADDRESS. 1923 */ 1924 if (va < VM_MIN_KERNEL_ADDRESS) 1925 return (va & ~DMAP_BASE_ADDRESS); 1926 1927 PMAP_LOCK(kernel_pmap); 1928 pvo = moea64_pvo_find_va(kernel_pmap, va); 1929 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1930 va)); 1931 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1932 PMAP_UNLOCK(kernel_pmap); 1933 return (pa); 1934 } 1935 1936 /* 1937 * Remove a wired page from kernel virtual address space. 1938 */ 1939 void 1940 moea64_kremove(mmu_t mmu, vm_offset_t va) 1941 { 1942 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1943 } 1944 1945 /* 1946 * Provide a kernel pointer corresponding to a given userland pointer. 1947 * The returned pointer is valid until the next time this function is 1948 * called in this thread. This is used internally in copyin/copyout. 1949 */ 1950 static int 1951 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1952 void **kaddr, size_t ulen, size_t *klen) 1953 { 1954 size_t l; 1955 #ifdef __powerpc64__ 1956 struct slb *slb; 1957 #endif 1958 register_t slbv; 1959 1960 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1961 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1962 if (l > ulen) 1963 l = ulen; 1964 if (klen) 1965 *klen = l; 1966 else if (l != ulen) 1967 return (EFAULT); 1968 1969 #ifdef __powerpc64__ 1970 /* Try lockless look-up first */ 1971 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1972 1973 if (slb == NULL) { 1974 /* If it isn't there, we need to pre-fault the VSID */ 1975 PMAP_LOCK(pm); 1976 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1977 PMAP_UNLOCK(pm); 1978 } else { 1979 slbv = slb->slbv; 1980 } 1981 1982 /* Mark segment no-execute */ 1983 slbv |= SLBV_N; 1984 #else 1985 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1986 1987 /* Mark segment no-execute */ 1988 slbv |= SR_N; 1989 #endif 1990 1991 /* If we have already set this VSID, we can just return */ 1992 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1993 return (0); 1994 1995 __asm __volatile("isync"); 1996 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1997 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1998 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1999 #ifdef __powerpc64__ 2000 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2001 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2002 #else 2003 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2004 #endif 2005 2006 return (0); 2007 } 2008 2009 /* 2010 * Figure out where a given kernel pointer (usually in a fault) points 2011 * to from the VM's perspective, potentially remapping into userland's 2012 * address space. 2013 */ 2014 static int 2015 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2016 vm_offset_t *decoded_addr) 2017 { 2018 vm_offset_t user_sr; 2019 2020 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2021 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2022 addr &= ADDR_PIDX | ADDR_POFF; 2023 addr |= user_sr << ADDR_SR_SHFT; 2024 *decoded_addr = addr; 2025 *is_user = 1; 2026 } else { 2027 *decoded_addr = addr; 2028 *is_user = 0; 2029 } 2030 2031 return (0); 2032 } 2033 2034 /* 2035 * Map a range of physical addresses into kernel virtual address space. 2036 * 2037 * The value passed in *virt is a suggested virtual address for the mapping. 2038 * Architectures which can support a direct-mapped physical to virtual region 2039 * can return the appropriate address within that region, leaving '*virt' 2040 * unchanged. Other architectures should map the pages starting at '*virt' and 2041 * update '*virt' with the first usable address after the mapped region. 2042 */ 2043 vm_offset_t 2044 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2045 vm_paddr_t pa_end, int prot) 2046 { 2047 vm_offset_t sva, va; 2048 2049 if (hw_direct_map) { 2050 /* 2051 * Check if every page in the region is covered by the direct 2052 * map. The direct map covers all of physical memory. Use 2053 * moea64_calc_wimg() as a shortcut to see if the page is in 2054 * physical memory as a way to see if the direct map covers it. 2055 */ 2056 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2057 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2058 break; 2059 if (va == pa_end) 2060 return (PHYS_TO_DMAP(pa_start)); 2061 } 2062 sva = *virt; 2063 va = sva; 2064 /* XXX respect prot argument */ 2065 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2066 moea64_kenter(mmu, va, pa_start); 2067 *virt = va; 2068 2069 return (sva); 2070 } 2071 2072 /* 2073 * Returns true if the pmap's pv is one of the first 2074 * 16 pvs linked to from this page. This count may 2075 * be changed upwards or downwards in the future; it 2076 * is only necessary that true be returned for a small 2077 * subset of pmaps for proper page aging. 2078 */ 2079 boolean_t 2080 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2081 { 2082 int loops; 2083 struct pvo_entry *pvo; 2084 boolean_t rv; 2085 2086 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2087 ("moea64_page_exists_quick: page %p is not managed", m)); 2088 loops = 0; 2089 rv = FALSE; 2090 PV_PAGE_LOCK(m); 2091 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2092 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2093 rv = TRUE; 2094 break; 2095 } 2096 if (++loops >= 16) 2097 break; 2098 } 2099 PV_PAGE_UNLOCK(m); 2100 return (rv); 2101 } 2102 2103 void 2104 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2105 { 2106 2107 m->md.mdpg_attrs = 0; 2108 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2109 LIST_INIT(&m->md.mdpg_pvoh); 2110 } 2111 2112 /* 2113 * Return the number of managed mappings to the given physical page 2114 * that are wired. 2115 */ 2116 int 2117 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2118 { 2119 struct pvo_entry *pvo; 2120 int count; 2121 2122 count = 0; 2123 if ((m->oflags & VPO_UNMANAGED) != 0) 2124 return (count); 2125 PV_PAGE_LOCK(m); 2126 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2127 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2128 count++; 2129 PV_PAGE_UNLOCK(m); 2130 return (count); 2131 } 2132 2133 static uintptr_t moea64_vsidcontext; 2134 2135 uintptr_t 2136 moea64_get_unique_vsid(void) { 2137 u_int entropy; 2138 register_t hash; 2139 uint32_t mask; 2140 int i; 2141 2142 entropy = 0; 2143 __asm __volatile("mftb %0" : "=r"(entropy)); 2144 2145 mtx_lock(&moea64_slb_mutex); 2146 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2147 u_int n; 2148 2149 /* 2150 * Create a new value by mutiplying by a prime and adding in 2151 * entropy from the timebase register. This is to make the 2152 * VSID more random so that the PT hash function collides 2153 * less often. (Note that the prime casues gcc to do shifts 2154 * instead of a multiply.) 2155 */ 2156 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2157 hash = moea64_vsidcontext & (NVSIDS - 1); 2158 if (hash == 0) /* 0 is special, avoid it */ 2159 continue; 2160 n = hash >> 5; 2161 mask = 1 << (hash & (VSID_NBPW - 1)); 2162 hash = (moea64_vsidcontext & VSID_HASHMASK); 2163 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2164 /* anything free in this bucket? */ 2165 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2166 entropy = (moea64_vsidcontext >> 20); 2167 continue; 2168 } 2169 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2170 mask = 1 << i; 2171 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2172 hash |= i; 2173 } 2174 if (hash == VSID_VRMA) /* also special, avoid this too */ 2175 continue; 2176 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2177 ("Allocating in-use VSID %#zx\n", hash)); 2178 moea64_vsid_bitmap[n] |= mask; 2179 mtx_unlock(&moea64_slb_mutex); 2180 return (hash); 2181 } 2182 2183 mtx_unlock(&moea64_slb_mutex); 2184 panic("%s: out of segments",__func__); 2185 } 2186 2187 #ifdef __powerpc64__ 2188 void 2189 moea64_pinit(mmu_t mmu, pmap_t pmap) 2190 { 2191 2192 RB_INIT(&pmap->pmap_pvo); 2193 2194 pmap->pm_slb_tree_root = slb_alloc_tree(); 2195 pmap->pm_slb = slb_alloc_user_cache(); 2196 pmap->pm_slb_len = 0; 2197 } 2198 #else 2199 void 2200 moea64_pinit(mmu_t mmu, pmap_t pmap) 2201 { 2202 int i; 2203 uint32_t hash; 2204 2205 RB_INIT(&pmap->pmap_pvo); 2206 2207 if (pmap_bootstrapped) 2208 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2209 (vm_offset_t)pmap); 2210 else 2211 pmap->pmap_phys = pmap; 2212 2213 /* 2214 * Allocate some segment registers for this pmap. 2215 */ 2216 hash = moea64_get_unique_vsid(); 2217 2218 for (i = 0; i < 16; i++) 2219 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2220 2221 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2222 } 2223 #endif 2224 2225 /* 2226 * Initialize the pmap associated with process 0. 2227 */ 2228 void 2229 moea64_pinit0(mmu_t mmu, pmap_t pm) 2230 { 2231 2232 PMAP_LOCK_INIT(pm); 2233 moea64_pinit(mmu, pm); 2234 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2235 } 2236 2237 /* 2238 * Set the physical protection on the specified range of this map as requested. 2239 */ 2240 static void 2241 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2242 { 2243 struct vm_page *pg; 2244 vm_prot_t oldprot; 2245 int32_t refchg; 2246 2247 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2248 2249 /* 2250 * Change the protection of the page. 2251 */ 2252 oldprot = pvo->pvo_pte.prot; 2253 pvo->pvo_pte.prot = prot; 2254 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2255 2256 /* 2257 * If the PVO is in the page table, update mapping 2258 */ 2259 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2260 if (refchg < 0) 2261 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2262 2263 if (pm != kernel_pmap && pg != NULL && 2264 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2265 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2266 if ((pg->oflags & VPO_UNMANAGED) == 0) 2267 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2268 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2269 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2270 } 2271 2272 /* 2273 * Update vm about the REF/CHG bits if the page is managed and we have 2274 * removed write access. 2275 */ 2276 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2277 (oldprot & VM_PROT_WRITE)) { 2278 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2279 if (refchg & LPTE_CHG) 2280 vm_page_dirty(pg); 2281 if (refchg & LPTE_REF) 2282 vm_page_aflag_set(pg, PGA_REFERENCED); 2283 } 2284 } 2285 2286 void 2287 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2288 vm_prot_t prot) 2289 { 2290 struct pvo_entry *pvo, *tpvo, key; 2291 2292 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2293 sva, eva, prot); 2294 2295 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2296 ("moea64_protect: non current pmap")); 2297 2298 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2299 moea64_remove(mmu, pm, sva, eva); 2300 return; 2301 } 2302 2303 PMAP_LOCK(pm); 2304 key.pvo_vaddr = sva; 2305 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2306 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2307 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2308 moea64_pvo_protect(mmu, pm, pvo, prot); 2309 } 2310 PMAP_UNLOCK(pm); 2311 } 2312 2313 /* 2314 * Map a list of wired pages into kernel virtual address space. This is 2315 * intended for temporary mappings which do not need page modification or 2316 * references recorded. Existing mappings in the region are overwritten. 2317 */ 2318 void 2319 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2320 { 2321 while (count-- > 0) { 2322 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2323 va += PAGE_SIZE; 2324 m++; 2325 } 2326 } 2327 2328 /* 2329 * Remove page mappings from kernel virtual address space. Intended for 2330 * temporary mappings entered by moea64_qenter. 2331 */ 2332 void 2333 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2334 { 2335 while (count-- > 0) { 2336 moea64_kremove(mmu, va); 2337 va += PAGE_SIZE; 2338 } 2339 } 2340 2341 void 2342 moea64_release_vsid(uint64_t vsid) 2343 { 2344 int idx, mask; 2345 2346 mtx_lock(&moea64_slb_mutex); 2347 idx = vsid & (NVSIDS-1); 2348 mask = 1 << (idx % VSID_NBPW); 2349 idx /= VSID_NBPW; 2350 KASSERT(moea64_vsid_bitmap[idx] & mask, 2351 ("Freeing unallocated VSID %#jx", vsid)); 2352 moea64_vsid_bitmap[idx] &= ~mask; 2353 mtx_unlock(&moea64_slb_mutex); 2354 } 2355 2356 2357 void 2358 moea64_release(mmu_t mmu, pmap_t pmap) 2359 { 2360 2361 /* 2362 * Free segment registers' VSIDs 2363 */ 2364 #ifdef __powerpc64__ 2365 slb_free_tree(pmap); 2366 slb_free_user_cache(pmap->pm_slb); 2367 #else 2368 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2369 2370 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2371 #endif 2372 } 2373 2374 /* 2375 * Remove all pages mapped by the specified pmap 2376 */ 2377 void 2378 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2379 { 2380 struct pvo_entry *pvo, *tpvo; 2381 struct pvo_dlist tofree; 2382 2383 SLIST_INIT(&tofree); 2384 2385 PMAP_LOCK(pm); 2386 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2387 if (pvo->pvo_vaddr & PVO_WIRED) 2388 continue; 2389 2390 /* 2391 * For locking reasons, remove this from the page table and 2392 * pmap, but save delinking from the vm_page for a second 2393 * pass 2394 */ 2395 moea64_pvo_remove_from_pmap(mmu, pvo); 2396 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2397 } 2398 PMAP_UNLOCK(pm); 2399 2400 while (!SLIST_EMPTY(&tofree)) { 2401 pvo = SLIST_FIRST(&tofree); 2402 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2403 moea64_pvo_remove_from_page(mmu, pvo); 2404 free_pvo_entry(pvo); 2405 } 2406 } 2407 2408 /* 2409 * Remove the given range of addresses from the specified map. 2410 */ 2411 void 2412 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2413 { 2414 struct pvo_entry *pvo, *tpvo, key; 2415 struct pvo_dlist tofree; 2416 2417 /* 2418 * Perform an unsynchronized read. This is, however, safe. 2419 */ 2420 if (pm->pm_stats.resident_count == 0) 2421 return; 2422 2423 key.pvo_vaddr = sva; 2424 2425 SLIST_INIT(&tofree); 2426 2427 PMAP_LOCK(pm); 2428 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2429 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2430 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2431 2432 /* 2433 * For locking reasons, remove this from the page table and 2434 * pmap, but save delinking from the vm_page for a second 2435 * pass 2436 */ 2437 moea64_pvo_remove_from_pmap(mmu, pvo); 2438 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2439 } 2440 PMAP_UNLOCK(pm); 2441 2442 while (!SLIST_EMPTY(&tofree)) { 2443 pvo = SLIST_FIRST(&tofree); 2444 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2445 moea64_pvo_remove_from_page(mmu, pvo); 2446 free_pvo_entry(pvo); 2447 } 2448 } 2449 2450 /* 2451 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2452 * will reflect changes in pte's back to the vm_page. 2453 */ 2454 void 2455 moea64_remove_all(mmu_t mmu, vm_page_t m) 2456 { 2457 struct pvo_entry *pvo, *next_pvo; 2458 struct pvo_head freequeue; 2459 int wasdead; 2460 pmap_t pmap; 2461 2462 LIST_INIT(&freequeue); 2463 2464 PV_PAGE_LOCK(m); 2465 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2466 pmap = pvo->pvo_pmap; 2467 PMAP_LOCK(pmap); 2468 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2469 if (!wasdead) 2470 moea64_pvo_remove_from_pmap(mmu, pvo); 2471 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2472 if (!wasdead) 2473 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2474 PMAP_UNLOCK(pmap); 2475 2476 } 2477 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2478 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2479 PV_PAGE_UNLOCK(m); 2480 2481 /* Clean up UMA allocations */ 2482 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2483 free_pvo_entry(pvo); 2484 } 2485 2486 /* 2487 * Allocate a physical page of memory directly from the phys_avail map. 2488 * Can only be called from moea64_bootstrap before avail start and end are 2489 * calculated. 2490 */ 2491 vm_offset_t 2492 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2493 { 2494 vm_offset_t s, e; 2495 int i, j; 2496 2497 size = round_page(size); 2498 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2499 if (align != 0) 2500 s = roundup2(phys_avail[i], align); 2501 else 2502 s = phys_avail[i]; 2503 e = s + size; 2504 2505 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2506 continue; 2507 2508 if (s + size > platform_real_maxaddr()) 2509 continue; 2510 2511 if (s == phys_avail[i]) { 2512 phys_avail[i] += size; 2513 } else if (e == phys_avail[i + 1]) { 2514 phys_avail[i + 1] -= size; 2515 } else { 2516 for (j = phys_avail_count * 2; j > i; j -= 2) { 2517 phys_avail[j] = phys_avail[j - 2]; 2518 phys_avail[j + 1] = phys_avail[j - 1]; 2519 } 2520 2521 phys_avail[i + 3] = phys_avail[i + 1]; 2522 phys_avail[i + 1] = s; 2523 phys_avail[i + 2] = e; 2524 phys_avail_count++; 2525 } 2526 2527 return (s); 2528 } 2529 panic("moea64_bootstrap_alloc: could not allocate memory"); 2530 } 2531 2532 static int 2533 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2534 struct pvo_entry **oldpvop) 2535 { 2536 struct pvo_entry *old_pvo; 2537 int err; 2538 2539 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2540 2541 STAT_MOEA64(moea64_pvo_enter_calls++); 2542 2543 /* 2544 * Add to pmap list 2545 */ 2546 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2547 2548 if (old_pvo != NULL) { 2549 if (oldpvop != NULL) 2550 *oldpvop = old_pvo; 2551 return (EEXIST); 2552 } 2553 2554 if (pvo_head != NULL) { 2555 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2556 } 2557 2558 if (pvo->pvo_vaddr & PVO_WIRED) 2559 pvo->pvo_pmap->pm_stats.wired_count++; 2560 pvo->pvo_pmap->pm_stats.resident_count++; 2561 2562 /* 2563 * Insert it into the hardware page table 2564 */ 2565 err = MOEA64_PTE_INSERT(mmu, pvo); 2566 if (err != 0) { 2567 panic("moea64_pvo_enter: overflow"); 2568 } 2569 2570 STAT_MOEA64(moea64_pvo_entries++); 2571 2572 if (pvo->pvo_pmap == kernel_pmap) 2573 isync(); 2574 2575 #ifdef __powerpc64__ 2576 /* 2577 * Make sure all our bootstrap mappings are in the SLB as soon 2578 * as virtual memory is switched on. 2579 */ 2580 if (!pmap_bootstrapped) 2581 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2582 pvo->pvo_vaddr & PVO_LARGE); 2583 #endif 2584 2585 return (0); 2586 } 2587 2588 static void 2589 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2590 { 2591 struct vm_page *pg; 2592 int32_t refchg; 2593 2594 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2595 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2596 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2597 2598 /* 2599 * If there is an active pte entry, we need to deactivate it 2600 */ 2601 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2602 if (refchg < 0) { 2603 /* 2604 * If it was evicted from the page table, be pessimistic and 2605 * dirty the page. 2606 */ 2607 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2608 refchg = LPTE_CHG; 2609 else 2610 refchg = 0; 2611 } 2612 2613 /* 2614 * Update our statistics. 2615 */ 2616 pvo->pvo_pmap->pm_stats.resident_count--; 2617 if (pvo->pvo_vaddr & PVO_WIRED) 2618 pvo->pvo_pmap->pm_stats.wired_count--; 2619 2620 /* 2621 * Remove this PVO from the pmap list. 2622 */ 2623 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2624 2625 /* 2626 * Mark this for the next sweep 2627 */ 2628 pvo->pvo_vaddr |= PVO_DEAD; 2629 2630 /* Send RC bits to VM */ 2631 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2632 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2633 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2634 if (pg != NULL) { 2635 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2636 if (refchg & LPTE_CHG) 2637 vm_page_dirty(pg); 2638 if (refchg & LPTE_REF) 2639 vm_page_aflag_set(pg, PGA_REFERENCED); 2640 } 2641 } 2642 } 2643 2644 static inline void 2645 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2646 vm_page_t m) 2647 { 2648 2649 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2650 2651 /* Use NULL pmaps as a sentinel for races in page deletion */ 2652 if (pvo->pvo_pmap == NULL) 2653 return; 2654 pvo->pvo_pmap = NULL; 2655 2656 /* 2657 * Update vm about page writeability/executability if managed 2658 */ 2659 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2660 if (pvo->pvo_vaddr & PVO_MANAGED) { 2661 if (m != NULL) { 2662 LIST_REMOVE(pvo, pvo_vlink); 2663 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2664 vm_page_aflag_clear(m, 2665 PGA_WRITEABLE | PGA_EXECUTABLE); 2666 } 2667 } 2668 2669 STAT_MOEA64(moea64_pvo_entries--); 2670 STAT_MOEA64(moea64_pvo_remove_calls++); 2671 } 2672 2673 static void 2674 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2675 { 2676 vm_page_t pg = NULL; 2677 2678 if (pvo->pvo_vaddr & PVO_MANAGED) 2679 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2680 2681 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2682 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2683 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2684 } 2685 2686 static struct pvo_entry * 2687 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2688 { 2689 struct pvo_entry key; 2690 2691 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2692 2693 key.pvo_vaddr = va & ~ADDR_POFF; 2694 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2695 } 2696 2697 static boolean_t 2698 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2699 { 2700 struct pvo_entry *pvo; 2701 int64_t ret; 2702 boolean_t rv; 2703 2704 /* 2705 * See if this bit is stored in the page already. 2706 */ 2707 if (m->md.mdpg_attrs & ptebit) 2708 return (TRUE); 2709 2710 /* 2711 * Examine each PTE. Sync so that any pending REF/CHG bits are 2712 * flushed to the PTEs. 2713 */ 2714 rv = FALSE; 2715 powerpc_sync(); 2716 PV_PAGE_LOCK(m); 2717 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2718 ret = 0; 2719 2720 /* 2721 * See if this pvo has a valid PTE. if so, fetch the 2722 * REF/CHG bits from the valid PTE. If the appropriate 2723 * ptebit is set, return success. 2724 */ 2725 PMAP_LOCK(pvo->pvo_pmap); 2726 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2727 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2728 PMAP_UNLOCK(pvo->pvo_pmap); 2729 2730 if (ret > 0) { 2731 atomic_set_32(&m->md.mdpg_attrs, 2732 ret & (LPTE_CHG | LPTE_REF)); 2733 if (ret & ptebit) { 2734 rv = TRUE; 2735 break; 2736 } 2737 } 2738 } 2739 PV_PAGE_UNLOCK(m); 2740 2741 return (rv); 2742 } 2743 2744 static u_int 2745 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2746 { 2747 u_int count; 2748 struct pvo_entry *pvo; 2749 int64_t ret; 2750 2751 /* 2752 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2753 * we can reset the right ones). 2754 */ 2755 powerpc_sync(); 2756 2757 /* 2758 * For each pvo entry, clear the pte's ptebit. 2759 */ 2760 count = 0; 2761 PV_PAGE_LOCK(m); 2762 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2763 ret = 0; 2764 2765 PMAP_LOCK(pvo->pvo_pmap); 2766 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2767 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2768 PMAP_UNLOCK(pvo->pvo_pmap); 2769 2770 if (ret > 0 && (ret & ptebit)) 2771 count++; 2772 } 2773 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2774 PV_PAGE_UNLOCK(m); 2775 2776 return (count); 2777 } 2778 2779 boolean_t 2780 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2781 { 2782 struct pvo_entry *pvo, key; 2783 vm_offset_t ppa; 2784 int error = 0; 2785 2786 if (hw_direct_map && mem_valid(pa, size) == 0) 2787 return (0); 2788 2789 PMAP_LOCK(kernel_pmap); 2790 ppa = pa & ~ADDR_POFF; 2791 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2792 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2793 ppa < pa + size; ppa += PAGE_SIZE, 2794 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2795 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2796 error = EFAULT; 2797 break; 2798 } 2799 } 2800 PMAP_UNLOCK(kernel_pmap); 2801 2802 return (error); 2803 } 2804 2805 /* 2806 * Map a set of physical memory pages into the kernel virtual 2807 * address space. Return a pointer to where it is mapped. This 2808 * routine is intended to be used for mapping device memory, 2809 * NOT real memory. 2810 */ 2811 void * 2812 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2813 { 2814 vm_offset_t va, tmpva, ppa, offset; 2815 2816 ppa = trunc_page(pa); 2817 offset = pa & PAGE_MASK; 2818 size = roundup2(offset + size, PAGE_SIZE); 2819 2820 va = kva_alloc(size); 2821 2822 if (!va) 2823 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2824 2825 for (tmpva = va; size > 0;) { 2826 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2827 size -= PAGE_SIZE; 2828 tmpva += PAGE_SIZE; 2829 ppa += PAGE_SIZE; 2830 } 2831 2832 return ((void *)(va + offset)); 2833 } 2834 2835 void * 2836 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2837 { 2838 2839 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2840 } 2841 2842 void 2843 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2844 { 2845 vm_offset_t base, offset; 2846 2847 base = trunc_page(va); 2848 offset = va & PAGE_MASK; 2849 size = roundup2(offset + size, PAGE_SIZE); 2850 2851 kva_free(base, size); 2852 } 2853 2854 void 2855 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2856 { 2857 struct pvo_entry *pvo; 2858 vm_offset_t lim; 2859 vm_paddr_t pa; 2860 vm_size_t len; 2861 2862 if (__predict_false(pm == NULL)) 2863 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2864 2865 PMAP_LOCK(pm); 2866 while (sz > 0) { 2867 lim = round_page(va+1); 2868 len = MIN(lim - va, sz); 2869 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2870 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2871 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2872 moea64_syncicache(mmu, pm, va, pa, len); 2873 } 2874 va += len; 2875 sz -= len; 2876 } 2877 PMAP_UNLOCK(pm); 2878 } 2879 2880 void 2881 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2882 { 2883 2884 *va = (void *)(uintptr_t)pa; 2885 } 2886 2887 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2888 2889 void 2890 moea64_scan_init(mmu_t mmu) 2891 { 2892 struct pvo_entry *pvo; 2893 vm_offset_t va; 2894 int i; 2895 2896 if (!do_minidump) { 2897 /* Initialize phys. segments for dumpsys(). */ 2898 memset(&dump_map, 0, sizeof(dump_map)); 2899 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2900 for (i = 0; i < pregions_sz; i++) { 2901 dump_map[i].pa_start = pregions[i].mr_start; 2902 dump_map[i].pa_size = pregions[i].mr_size; 2903 } 2904 return; 2905 } 2906 2907 /* Virtual segments for minidumps: */ 2908 memset(&dump_map, 0, sizeof(dump_map)); 2909 2910 /* 1st: kernel .data and .bss. */ 2911 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2912 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2913 dump_map[0].pa_start; 2914 2915 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2916 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2917 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2918 2919 /* 3rd: kernel VM. */ 2920 va = dump_map[1].pa_start + dump_map[1].pa_size; 2921 /* Find start of next chunk (from va). */ 2922 while (va < virtual_end) { 2923 /* Don't dump the buffer cache. */ 2924 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2925 va = kmi.buffer_eva; 2926 continue; 2927 } 2928 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2929 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2930 break; 2931 va += PAGE_SIZE; 2932 } 2933 if (va < virtual_end) { 2934 dump_map[2].pa_start = va; 2935 va += PAGE_SIZE; 2936 /* Find last page in chunk. */ 2937 while (va < virtual_end) { 2938 /* Don't run into the buffer cache. */ 2939 if (va == kmi.buffer_sva) 2940 break; 2941 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2942 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2943 break; 2944 va += PAGE_SIZE; 2945 } 2946 dump_map[2].pa_size = va - dump_map[2].pa_start; 2947 } 2948 } 2949 2950 #ifdef __powerpc64__ 2951 2952 static size_t 2953 moea64_scan_pmap(mmu_t mmu) 2954 { 2955 struct pvo_entry *pvo; 2956 vm_paddr_t pa, pa_end; 2957 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 2958 uint64_t lpsize; 2959 2960 lpsize = moea64_large_page_size; 2961 kstart = trunc_page((vm_offset_t)_etext); 2962 kend = round_page((vm_offset_t)_end); 2963 kstart_lp = kstart & ~moea64_large_page_mask; 2964 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 2965 2966 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 2967 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 2968 kstart, kend, kstart_lp, kend_lp); 2969 2970 PMAP_LOCK(kernel_pmap); 2971 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 2972 va = pvo->pvo_vaddr; 2973 2974 if (va & PVO_DEAD) 2975 continue; 2976 2977 /* Skip DMAP (except kernel area) */ 2978 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 2979 if (va & PVO_LARGE) { 2980 pgva = va & ~moea64_large_page_mask; 2981 if (pgva < kstart_lp || pgva >= kend_lp) 2982 continue; 2983 } else { 2984 pgva = trunc_page(va); 2985 if (pgva < kstart || pgva >= kend) 2986 continue; 2987 } 2988 } 2989 2990 pa = pvo->pvo_pte.pa & LPTE_RPGN; 2991 2992 if (va & PVO_LARGE) { 2993 pa_end = pa + lpsize; 2994 for (; pa < pa_end; pa += PAGE_SIZE) { 2995 if (is_dumpable(pa)) 2996 dump_add_page(pa); 2997 } 2998 } else { 2999 if (is_dumpable(pa)) 3000 dump_add_page(pa); 3001 } 3002 } 3003 PMAP_UNLOCK(kernel_pmap); 3004 3005 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3006 } 3007 3008 static struct dump_context dump_ctx; 3009 3010 static void * 3011 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3012 { 3013 dump_ctx.ptex = 0; 3014 dump_ctx.ptex_end = moea64_pteg_count * 8; 3015 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3016 return (&dump_ctx); 3017 } 3018 3019 #else 3020 3021 static size_t 3022 moea64_scan_pmap(mmu_t mmu) 3023 { 3024 return (0); 3025 } 3026 3027 static void * 3028 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3029 { 3030 return (NULL); 3031 } 3032 3033 #endif 3034 3035 #ifdef __powerpc64__ 3036 static void 3037 moea64_map_range(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3038 { 3039 3040 for (; npages > 0; --npages) { 3041 if (moea64_large_page_size != 0 && 3042 (pa & moea64_large_page_mask) == 0 && 3043 (va & moea64_large_page_mask) == 0 && 3044 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3045 PMAP_LOCK(kernel_pmap); 3046 moea64_kenter_large(mmu, va, pa, 0, 0); 3047 PMAP_UNLOCK(kernel_pmap); 3048 pa += moea64_large_page_size; 3049 va += moea64_large_page_size; 3050 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3051 } else { 3052 moea64_kenter(mmu, va, pa); 3053 pa += PAGE_SIZE; 3054 va += PAGE_SIZE; 3055 } 3056 } 3057 } 3058 3059 static void 3060 moea64_page_array_startup(mmu_t mmu, long pages) 3061 { 3062 long dom_pages[MAXMEMDOM]; 3063 vm_paddr_t pa; 3064 vm_offset_t va, vm_page_base; 3065 vm_size_t needed, size; 3066 long page; 3067 int domain; 3068 int i; 3069 3070 vm_page_base = 0xd000000000000000ULL; 3071 3072 /* Short-circuit single-domain systems. */ 3073 if (vm_ndomains == 1) { 3074 size = round_page(pages * sizeof(struct vm_page)); 3075 pa = vm_phys_early_alloc(0, size); 3076 vm_page_base = moea64_map(mmu, &vm_page_base, 3077 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3078 vm_page_array_size = pages; 3079 vm_page_array = (vm_page_t)vm_page_base; 3080 return; 3081 } 3082 3083 page = 0; 3084 for (i = 0; i < MAXMEMDOM; i++) 3085 dom_pages[i] = 0; 3086 3087 /* Now get the number of pages required per domain. */ 3088 for (i = 0; i < vm_phys_nsegs; i++) { 3089 domain = vm_phys_segs[i].domain; 3090 KASSERT(domain < MAXMEMDOM, 3091 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3092 /* Get size of vm_page_array needed for this segment. */ 3093 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3094 dom_pages[domain] += size; 3095 } 3096 3097 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3098 domain = _vm_phys_domain(phys_avail[i]); 3099 KASSERT(domain < MAXMEMDOM, 3100 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3101 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3102 dom_pages[domain] += size; 3103 } 3104 3105 /* 3106 * Map in chunks that can get us all 16MB pages. There will be some 3107 * overlap between domains, but that's acceptable for now. 3108 */ 3109 vm_page_array_size = 0; 3110 va = vm_page_base; 3111 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3112 if (dom_pages[i] == 0) 3113 continue; 3114 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3115 size = round_page(size * sizeof(struct vm_page)); 3116 needed = size; 3117 size = roundup2(size, moea64_large_page_size); 3118 pa = vm_phys_early_alloc(i, size); 3119 vm_page_array_size += size / sizeof(struct vm_page); 3120 moea64_map_range(mmu, va, pa, size >> PAGE_SHIFT); 3121 /* Scoot up domain 0, to reduce the domain page overlap. */ 3122 if (i == 0) 3123 vm_page_base += size - needed; 3124 va += size; 3125 } 3126 vm_page_array = (vm_page_t)vm_page_base; 3127 vm_page_array_size = pages; 3128 } 3129 #endif 3130