1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mman.h> 61 #include <sys/mutex.h> 62 #include <sys/proc.h> 63 #include <sys/rwlock.h> 64 #include <sys/sched.h> 65 #include <sys/sysctl.h> 66 #include <sys/systm.h> 67 #include <sys/vmmeter.h> 68 #include <sys/smp.h> 69 #include <sys/reboot.h> 70 71 #include <sys/kdb.h> 72 73 #include <dev/ofw/openfirm.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 #include <vm/vm_param.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_page.h> 80 #include <vm/vm_phys.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_object.h> 83 #include <vm/vm_extern.h> 84 #include <vm/vm_pageout.h> 85 #include <vm/vm_dumpset.h> 86 #include <vm/vm_reserv.h> 87 #include <vm/uma.h> 88 89 #include <machine/_inttypes.h> 90 #include <machine/cpu.h> 91 #include <machine/ifunc.h> 92 #include <machine/platform.h> 93 #include <machine/frame.h> 94 #include <machine/md_var.h> 95 #include <machine/psl.h> 96 #include <machine/bat.h> 97 #include <machine/hid.h> 98 #include <machine/pte.h> 99 #include <machine/sr.h> 100 #include <machine/trap.h> 101 #include <machine/mmuvar.h> 102 103 #include "mmu_oea64.h" 104 105 void moea64_release_vsid(uint64_t vsid); 106 uintptr_t moea64_get_unique_vsid(void); 107 108 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 109 #define ENABLE_TRANS(msr) mtmsr(msr) 110 111 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 112 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 113 #define VSID_HASH_MASK 0x0000007fffffffffULL 114 115 /* 116 * Locking semantics: 117 * 118 * There are two locks of interest: the page locks and the pmap locks, which 119 * protect their individual PVO lists and are locked in that order. The contents 120 * of all PVO entries are protected by the locks of their respective pmaps. 121 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 122 * into any list. 123 * 124 */ 125 126 #define PV_LOCK_COUNT PA_LOCK_COUNT 127 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 128 129 /* 130 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 131 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 132 * index at (N << 45). 133 */ 134 #ifdef __powerpc64__ 135 #define PV_LOCK_IDX(pa) ((pa_index(pa) * (((pa) >> 45) + 1)) % PV_LOCK_COUNT) 136 #else 137 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 138 #endif 139 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 140 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 141 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 142 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 143 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 144 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 145 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 146 147 /* Superpage PV lock */ 148 149 #define PV_LOCK_SIZE (1<<PDRSHIFT) 150 151 static __always_inline void 152 moea64_sp_pv_lock(vm_paddr_t pa) 153 { 154 vm_paddr_t pa_end; 155 156 /* Note: breaking when pa_end is reached to avoid overflows */ 157 pa_end = pa + (HPT_SP_SIZE - PV_LOCK_SIZE); 158 for (;;) { 159 mtx_lock_flags(PV_LOCKPTR(pa), MTX_DUPOK); 160 if (pa == pa_end) 161 break; 162 pa += PV_LOCK_SIZE; 163 } 164 } 165 166 static __always_inline void 167 moea64_sp_pv_unlock(vm_paddr_t pa) 168 { 169 vm_paddr_t pa_end; 170 171 /* Note: breaking when pa_end is reached to avoid overflows */ 172 pa_end = pa; 173 pa += HPT_SP_SIZE - PV_LOCK_SIZE; 174 for (;;) { 175 mtx_unlock_flags(PV_LOCKPTR(pa), MTX_DUPOK); 176 if (pa == pa_end) 177 break; 178 pa -= PV_LOCK_SIZE; 179 } 180 } 181 182 #define SP_PV_LOCK_ALIGNED(pa) moea64_sp_pv_lock(pa) 183 #define SP_PV_UNLOCK_ALIGNED(pa) moea64_sp_pv_unlock(pa) 184 #define SP_PV_LOCK(pa) moea64_sp_pv_lock((pa) & ~HPT_SP_MASK) 185 #define SP_PV_UNLOCK(pa) moea64_sp_pv_unlock((pa) & ~HPT_SP_MASK) 186 #define SP_PV_PAGE_LOCK(m) SP_PV_LOCK(VM_PAGE_TO_PHYS(m)) 187 #define SP_PV_PAGE_UNLOCK(m) SP_PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 188 189 struct ofw_map { 190 cell_t om_va; 191 cell_t om_len; 192 uint64_t om_pa; 193 cell_t om_mode; 194 }; 195 196 extern unsigned char _etext[]; 197 extern unsigned char _end[]; 198 199 extern void *slbtrap, *slbtrapend; 200 201 /* 202 * Map of physical memory regions. 203 */ 204 static struct mem_region *regions; 205 static struct mem_region *pregions; 206 static struct numa_mem_region *numa_pregions; 207 static u_int phys_avail_count; 208 static int regions_sz, pregions_sz, numapregions_sz; 209 210 extern void bs_remap_earlyboot(void); 211 212 /* 213 * Lock for the SLB tables. 214 */ 215 struct mtx moea64_slb_mutex; 216 217 /* 218 * PTEG data. 219 */ 220 u_long moea64_pteg_count; 221 u_long moea64_pteg_mask; 222 223 /* 224 * PVO data. 225 */ 226 227 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 228 229 static struct pvo_entry *moea64_bpvo_pool; 230 static int moea64_bpvo_pool_index = 0; 231 static int moea64_bpvo_pool_size = 0; 232 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 233 &moea64_bpvo_pool_index, 0, ""); 234 235 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */ 236 #define BPVO_POOL_EXPANSION_FACTOR 3 237 #define VSID_NBPW (sizeof(u_int32_t) * 8) 238 #ifdef __powerpc64__ 239 #define NVSIDS (NPMAPS * 16) 240 #define VSID_HASHMASK 0xffffffffUL 241 #else 242 #define NVSIDS NPMAPS 243 #define VSID_HASHMASK 0xfffffUL 244 #endif 245 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 246 247 static boolean_t moea64_initialized = FALSE; 248 249 #ifdef MOEA64_STATS 250 /* 251 * Statistics. 252 */ 253 u_int moea64_pte_valid = 0; 254 u_int moea64_pte_overflow = 0; 255 u_int moea64_pvo_entries = 0; 256 u_int moea64_pvo_enter_calls = 0; 257 u_int moea64_pvo_remove_calls = 0; 258 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 259 &moea64_pte_valid, 0, ""); 260 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 261 &moea64_pte_overflow, 0, ""); 262 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 263 &moea64_pvo_entries, 0, ""); 264 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 265 &moea64_pvo_enter_calls, 0, ""); 266 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 267 &moea64_pvo_remove_calls, 0, ""); 268 #endif 269 270 vm_offset_t moea64_scratchpage_va[2]; 271 struct pvo_entry *moea64_scratchpage_pvo[2]; 272 struct mtx moea64_scratchpage_mtx; 273 274 uint64_t moea64_large_page_mask = 0; 275 uint64_t moea64_large_page_size = 0; 276 int moea64_large_page_shift = 0; 277 bool moea64_has_lp_4k_16m = false; 278 279 /* 280 * PVO calls. 281 */ 282 static int moea64_pvo_enter(struct pvo_entry *pvo, 283 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 284 static void moea64_pvo_remove_from_pmap(struct pvo_entry *pvo); 285 static void moea64_pvo_remove_from_page(struct pvo_entry *pvo); 286 static void moea64_pvo_remove_from_page_locked( 287 struct pvo_entry *pvo, vm_page_t m); 288 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 289 290 /* 291 * Utility routines. 292 */ 293 static boolean_t moea64_query_bit(vm_page_t, uint64_t); 294 static u_int moea64_clear_bit(vm_page_t, uint64_t); 295 static void moea64_kremove(vm_offset_t); 296 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 297 vm_paddr_t pa, vm_size_t sz); 298 static void moea64_pmap_init_qpages(void); 299 static void moea64_remove_locked(pmap_t, vm_offset_t, 300 vm_offset_t, struct pvo_dlist *); 301 302 /* 303 * Superpages data and routines. 304 */ 305 306 /* 307 * PVO flags (in vaddr) that must match for promotion to succeed. 308 * Note that protection bits are checked separately, as they reside in 309 * another field. 310 */ 311 #define PVO_FLAGS_PROMOTE (PVO_WIRED | PVO_MANAGED | PVO_PTEGIDX_VALID) 312 313 #define PVO_IS_SP(pvo) (((pvo)->pvo_vaddr & PVO_LARGE) && \ 314 (pvo)->pvo_pmap != kernel_pmap) 315 316 /* Get physical address from PVO. */ 317 #define PVO_PADDR(pvo) moea64_pvo_paddr(pvo) 318 319 /* MD page flag indicating that the page is a superpage. */ 320 #define MDPG_ATTR_SP 0x40000000 321 322 SYSCTL_DECL(_vm_pmap); 323 324 static SYSCTL_NODE(_vm_pmap, OID_AUTO, sp, CTLFLAG_RD, 0, 325 "SP page mapping counters"); 326 327 static u_long sp_demotions; 328 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, demotions, CTLFLAG_RD, 329 &sp_demotions, 0, "SP page demotions"); 330 331 static u_long sp_mappings; 332 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, mappings, CTLFLAG_RD, 333 &sp_mappings, 0, "SP page mappings"); 334 335 static u_long sp_p_failures; 336 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_failures, CTLFLAG_RD, 337 &sp_p_failures, 0, "SP page promotion failures"); 338 339 static u_long sp_p_fail_pa; 340 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_pa, CTLFLAG_RD, 341 &sp_p_fail_pa, 0, "SP page promotion failure: PAs don't match"); 342 343 static u_long sp_p_fail_flags; 344 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_flags, CTLFLAG_RD, 345 &sp_p_fail_flags, 0, "SP page promotion failure: page flags don't match"); 346 347 static u_long sp_p_fail_prot; 348 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_prot, CTLFLAG_RD, 349 &sp_p_fail_prot, 0, 350 "SP page promotion failure: page protections don't match"); 351 352 static u_long sp_p_fail_wimg; 353 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_wimg, CTLFLAG_RD, 354 &sp_p_fail_wimg, 0, "SP page promotion failure: WIMG bits don't match"); 355 356 static u_long sp_promotions; 357 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, promotions, CTLFLAG_RD, 358 &sp_promotions, 0, "SP page promotions"); 359 360 static bool moea64_ps_enabled(pmap_t); 361 static void moea64_align_superpage(vm_object_t, vm_ooffset_t, 362 vm_offset_t *, vm_size_t); 363 364 static int moea64_sp_enter(pmap_t pmap, vm_offset_t va, 365 vm_page_t m, vm_prot_t prot, u_int flags, int8_t psind); 366 static struct pvo_entry *moea64_sp_remove(struct pvo_entry *sp, 367 struct pvo_dlist *tofree); 368 369 static void moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m); 370 static void moea64_sp_demote_aligned(struct pvo_entry *sp); 371 static void moea64_sp_demote(struct pvo_entry *pvo); 372 373 static struct pvo_entry *moea64_sp_unwire(struct pvo_entry *sp); 374 static struct pvo_entry *moea64_sp_protect(struct pvo_entry *sp, 375 vm_prot_t prot); 376 377 static int64_t moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit); 378 static int64_t moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, 379 uint64_t ptebit); 380 381 static __inline bool moea64_sp_pvo_in_range(struct pvo_entry *pvo, 382 vm_offset_t sva, vm_offset_t eva); 383 384 /* 385 * Kernel MMU interface 386 */ 387 void moea64_clear_modify(vm_page_t); 388 void moea64_copy_page(vm_page_t, vm_page_t); 389 void moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 390 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 391 int moea64_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 392 u_int flags, int8_t psind); 393 void moea64_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 394 vm_prot_t); 395 void moea64_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 396 vm_paddr_t moea64_extract(pmap_t, vm_offset_t); 397 vm_page_t moea64_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 398 void moea64_init(void); 399 boolean_t moea64_is_modified(vm_page_t); 400 boolean_t moea64_is_prefaultable(pmap_t, vm_offset_t); 401 boolean_t moea64_is_referenced(vm_page_t); 402 int moea64_ts_referenced(vm_page_t); 403 vm_offset_t moea64_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 404 boolean_t moea64_page_exists_quick(pmap_t, vm_page_t); 405 void moea64_page_init(vm_page_t); 406 int moea64_page_wired_mappings(vm_page_t); 407 int moea64_pinit(pmap_t); 408 void moea64_pinit0(pmap_t); 409 void moea64_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 410 void moea64_qenter(vm_offset_t, vm_page_t *, int); 411 void moea64_qremove(vm_offset_t, int); 412 void moea64_release(pmap_t); 413 void moea64_remove(pmap_t, vm_offset_t, vm_offset_t); 414 void moea64_remove_pages(pmap_t); 415 void moea64_remove_all(vm_page_t); 416 void moea64_remove_write(vm_page_t); 417 void moea64_unwire(pmap_t, vm_offset_t, vm_offset_t); 418 void moea64_zero_page(vm_page_t); 419 void moea64_zero_page_area(vm_page_t, int, int); 420 void moea64_activate(struct thread *); 421 void moea64_deactivate(struct thread *); 422 void *moea64_mapdev(vm_paddr_t, vm_size_t); 423 void *moea64_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 424 void moea64_unmapdev(vm_offset_t, vm_size_t); 425 vm_paddr_t moea64_kextract(vm_offset_t); 426 void moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma); 427 void moea64_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t ma); 428 void moea64_kenter(vm_offset_t, vm_paddr_t); 429 boolean_t moea64_dev_direct_mapped(vm_paddr_t, vm_size_t); 430 static void moea64_sync_icache(pmap_t, vm_offset_t, vm_size_t); 431 void moea64_dumpsys_map(vm_paddr_t pa, size_t sz, 432 void **va); 433 void moea64_scan_init(void); 434 vm_offset_t moea64_quick_enter_page(vm_page_t m); 435 void moea64_quick_remove_page(vm_offset_t addr); 436 boolean_t moea64_page_is_mapped(vm_page_t m); 437 static int moea64_map_user_ptr(pmap_t pm, 438 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 439 static int moea64_decode_kernel_ptr(vm_offset_t addr, 440 int *is_user, vm_offset_t *decoded_addr); 441 static size_t moea64_scan_pmap(void); 442 static void *moea64_dump_pmap_init(unsigned blkpgs); 443 #ifdef __powerpc64__ 444 static void moea64_page_array_startup(long); 445 #endif 446 static int moea64_mincore(pmap_t, vm_offset_t, vm_paddr_t *); 447 448 static struct pmap_funcs moea64_methods = { 449 .clear_modify = moea64_clear_modify, 450 .copy_page = moea64_copy_page, 451 .copy_pages = moea64_copy_pages, 452 .enter = moea64_enter, 453 .enter_object = moea64_enter_object, 454 .enter_quick = moea64_enter_quick, 455 .extract = moea64_extract, 456 .extract_and_hold = moea64_extract_and_hold, 457 .init = moea64_init, 458 .is_modified = moea64_is_modified, 459 .is_prefaultable = moea64_is_prefaultable, 460 .is_referenced = moea64_is_referenced, 461 .ts_referenced = moea64_ts_referenced, 462 .map = moea64_map, 463 .mincore = moea64_mincore, 464 .page_exists_quick = moea64_page_exists_quick, 465 .page_init = moea64_page_init, 466 .page_wired_mappings = moea64_page_wired_mappings, 467 .pinit = moea64_pinit, 468 .pinit0 = moea64_pinit0, 469 .protect = moea64_protect, 470 .qenter = moea64_qenter, 471 .qremove = moea64_qremove, 472 .release = moea64_release, 473 .remove = moea64_remove, 474 .remove_pages = moea64_remove_pages, 475 .remove_all = moea64_remove_all, 476 .remove_write = moea64_remove_write, 477 .sync_icache = moea64_sync_icache, 478 .unwire = moea64_unwire, 479 .zero_page = moea64_zero_page, 480 .zero_page_area = moea64_zero_page_area, 481 .activate = moea64_activate, 482 .deactivate = moea64_deactivate, 483 .page_set_memattr = moea64_page_set_memattr, 484 .quick_enter_page = moea64_quick_enter_page, 485 .quick_remove_page = moea64_quick_remove_page, 486 .page_is_mapped = moea64_page_is_mapped, 487 #ifdef __powerpc64__ 488 .page_array_startup = moea64_page_array_startup, 489 #endif 490 .ps_enabled = moea64_ps_enabled, 491 .align_superpage = moea64_align_superpage, 492 493 /* Internal interfaces */ 494 .mapdev = moea64_mapdev, 495 .mapdev_attr = moea64_mapdev_attr, 496 .unmapdev = moea64_unmapdev, 497 .kextract = moea64_kextract, 498 .kenter = moea64_kenter, 499 .kenter_attr = moea64_kenter_attr, 500 .dev_direct_mapped = moea64_dev_direct_mapped, 501 .dumpsys_pa_init = moea64_scan_init, 502 .dumpsys_scan_pmap = moea64_scan_pmap, 503 .dumpsys_dump_pmap_init = moea64_dump_pmap_init, 504 .dumpsys_map_chunk = moea64_dumpsys_map, 505 .map_user_ptr = moea64_map_user_ptr, 506 .decode_kernel_ptr = moea64_decode_kernel_ptr, 507 }; 508 509 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods); 510 511 /* 512 * Get physical address from PVO. 513 * 514 * For superpages, the lower bits are not stored on pvo_pte.pa and must be 515 * obtained from VA. 516 */ 517 static __always_inline vm_paddr_t 518 moea64_pvo_paddr(struct pvo_entry *pvo) 519 { 520 vm_paddr_t pa; 521 522 pa = (pvo)->pvo_pte.pa & LPTE_RPGN; 523 524 if (PVO_IS_SP(pvo)) { 525 pa &= ~HPT_SP_MASK; /* This is needed to clear LPTE_LP bits. */ 526 pa |= PVO_VADDR(pvo) & HPT_SP_MASK; 527 } 528 return (pa); 529 } 530 531 static struct pvo_head * 532 vm_page_to_pvoh(vm_page_t m) 533 { 534 535 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 536 return (&m->md.mdpg_pvoh); 537 } 538 539 static struct pvo_entry * 540 alloc_pvo_entry(int bootstrap) 541 { 542 struct pvo_entry *pvo; 543 544 if (!moea64_initialized || bootstrap) { 545 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 546 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 547 "Try setting machdep.moea64_bpvo_pool_size tunable", 548 __func__, moea64_bpvo_pool_index, 549 moea64_bpvo_pool_size, 550 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 551 } 552 pvo = &moea64_bpvo_pool[ 553 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 554 bzero(pvo, sizeof(*pvo)); 555 pvo->pvo_vaddr = PVO_BOOTSTRAP; 556 } else 557 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 558 559 return (pvo); 560 } 561 562 static void 563 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 564 { 565 uint64_t vsid; 566 uint64_t hash; 567 int shift; 568 569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 570 571 pvo->pvo_pmap = pmap; 572 va &= ~ADDR_POFF; 573 pvo->pvo_vaddr |= va; 574 vsid = va_to_vsid(pmap, va); 575 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 576 | (vsid << 16); 577 578 if (pmap == kernel_pmap && (pvo->pvo_vaddr & PVO_LARGE) != 0) 579 shift = moea64_large_page_shift; 580 else 581 shift = ADDR_PIDX_SHFT; 582 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 583 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 584 } 585 586 static void 587 free_pvo_entry(struct pvo_entry *pvo) 588 { 589 590 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 591 uma_zfree(moea64_pvo_zone, pvo); 592 } 593 594 void 595 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 596 { 597 598 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 599 lpte->pte_hi |= LPTE_VALID; 600 601 if (pvo->pvo_vaddr & PVO_LARGE) 602 lpte->pte_hi |= LPTE_BIG; 603 if (pvo->pvo_vaddr & PVO_WIRED) 604 lpte->pte_hi |= LPTE_WIRED; 605 if (pvo->pvo_vaddr & PVO_HID) 606 lpte->pte_hi |= LPTE_HID; 607 608 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 609 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 610 lpte->pte_lo |= LPTE_BW; 611 else 612 lpte->pte_lo |= LPTE_BR; 613 614 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 615 lpte->pte_lo |= LPTE_NOEXEC; 616 } 617 618 static __inline uint64_t 619 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 620 { 621 uint64_t pte_lo; 622 int i; 623 624 if (ma != VM_MEMATTR_DEFAULT) { 625 switch (ma) { 626 case VM_MEMATTR_UNCACHEABLE: 627 return (LPTE_I | LPTE_G); 628 case VM_MEMATTR_CACHEABLE: 629 return (LPTE_M); 630 case VM_MEMATTR_WRITE_COMBINING: 631 case VM_MEMATTR_WRITE_BACK: 632 case VM_MEMATTR_PREFETCHABLE: 633 return (LPTE_I); 634 case VM_MEMATTR_WRITE_THROUGH: 635 return (LPTE_W | LPTE_M); 636 } 637 } 638 639 /* 640 * Assume the page is cache inhibited and access is guarded unless 641 * it's in our available memory array. 642 */ 643 pte_lo = LPTE_I | LPTE_G; 644 for (i = 0; i < pregions_sz; i++) { 645 if ((pa >= pregions[i].mr_start) && 646 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 647 pte_lo &= ~(LPTE_I | LPTE_G); 648 pte_lo |= LPTE_M; 649 break; 650 } 651 } 652 653 return pte_lo; 654 } 655 656 /* 657 * Quick sort callout for comparing memory regions. 658 */ 659 static int om_cmp(const void *a, const void *b); 660 661 static int 662 om_cmp(const void *a, const void *b) 663 { 664 const struct ofw_map *mapa; 665 const struct ofw_map *mapb; 666 667 mapa = a; 668 mapb = b; 669 if (mapa->om_pa < mapb->om_pa) 670 return (-1); 671 else if (mapa->om_pa > mapb->om_pa) 672 return (1); 673 else 674 return (0); 675 } 676 677 static void 678 moea64_add_ofw_mappings(phandle_t mmu, size_t sz) 679 { 680 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 681 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 682 struct pvo_entry *pvo; 683 register_t msr; 684 vm_offset_t off; 685 vm_paddr_t pa_base; 686 int i, j; 687 688 bzero(translations, sz); 689 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 690 sizeof(acells)); 691 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 692 panic("moea64_bootstrap: can't get ofw translations"); 693 694 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 695 sz /= sizeof(cell_t); 696 for (i = 0, j = 0; i < sz; j++) { 697 translations[j].om_va = trans_cells[i++]; 698 translations[j].om_len = trans_cells[i++]; 699 translations[j].om_pa = trans_cells[i++]; 700 if (acells == 2) { 701 translations[j].om_pa <<= 32; 702 translations[j].om_pa |= trans_cells[i++]; 703 } 704 translations[j].om_mode = trans_cells[i++]; 705 } 706 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 707 i, sz)); 708 709 sz = j; 710 qsort(translations, sz, sizeof (*translations), om_cmp); 711 712 for (i = 0; i < sz; i++) { 713 pa_base = translations[i].om_pa; 714 #ifndef __powerpc64__ 715 if ((translations[i].om_pa >> 32) != 0) 716 panic("OFW translations above 32-bit boundary!"); 717 #endif 718 719 if (pa_base % PAGE_SIZE) 720 panic("OFW translation not page-aligned (phys)!"); 721 if (translations[i].om_va % PAGE_SIZE) 722 panic("OFW translation not page-aligned (virt)!"); 723 724 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 725 pa_base, translations[i].om_va, translations[i].om_len); 726 727 /* Now enter the pages for this mapping */ 728 729 DISABLE_TRANS(msr); 730 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 731 /* If this address is direct-mapped, skip remapping */ 732 if (hw_direct_map && 733 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 734 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 735 == LPTE_M) 736 continue; 737 738 PMAP_LOCK(kernel_pmap); 739 pvo = moea64_pvo_find_va(kernel_pmap, 740 translations[i].om_va + off); 741 PMAP_UNLOCK(kernel_pmap); 742 if (pvo != NULL) 743 continue; 744 745 moea64_kenter(translations[i].om_va + off, 746 pa_base + off); 747 } 748 ENABLE_TRANS(msr); 749 } 750 } 751 752 #ifdef __powerpc64__ 753 static void 754 moea64_probe_large_page(void) 755 { 756 uint16_t pvr = mfpvr() >> 16; 757 758 switch (pvr) { 759 case IBM970: 760 case IBM970FX: 761 case IBM970MP: 762 powerpc_sync(); isync(); 763 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 764 powerpc_sync(); isync(); 765 766 /* FALLTHROUGH */ 767 default: 768 if (moea64_large_page_size == 0) { 769 moea64_large_page_size = 0x1000000; /* 16 MB */ 770 moea64_large_page_shift = 24; 771 } 772 } 773 774 moea64_large_page_mask = moea64_large_page_size - 1; 775 } 776 777 static void 778 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 779 { 780 struct slb *cache; 781 struct slb entry; 782 uint64_t esid, slbe; 783 uint64_t i; 784 785 cache = PCPU_GET(aim.slb); 786 esid = va >> ADDR_SR_SHFT; 787 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 788 789 for (i = 0; i < 64; i++) { 790 if (cache[i].slbe == (slbe | i)) 791 return; 792 } 793 794 entry.slbe = slbe; 795 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 796 if (large) 797 entry.slbv |= SLBV_L; 798 799 slb_insert_kernel(entry.slbe, entry.slbv); 800 } 801 #endif 802 803 static int 804 moea64_kenter_large(vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 805 { 806 struct pvo_entry *pvo; 807 uint64_t pte_lo; 808 int error; 809 810 pte_lo = LPTE_M; 811 pte_lo |= attr; 812 813 pvo = alloc_pvo_entry(bootstrap); 814 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 815 init_pvo_entry(pvo, kernel_pmap, va); 816 817 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 818 VM_PROT_EXECUTE; 819 pvo->pvo_pte.pa = pa | pte_lo; 820 error = moea64_pvo_enter(pvo, NULL, NULL); 821 if (error != 0) 822 panic("Error %d inserting large page\n", error); 823 return (0); 824 } 825 826 static void 827 moea64_setup_direct_map(vm_offset_t kernelstart, 828 vm_offset_t kernelend) 829 { 830 register_t msr; 831 vm_paddr_t pa, pkernelstart, pkernelend; 832 vm_offset_t size, off; 833 uint64_t pte_lo; 834 int i; 835 836 if (moea64_large_page_size == 0) 837 hw_direct_map = 0; 838 839 DISABLE_TRANS(msr); 840 if (hw_direct_map) { 841 PMAP_LOCK(kernel_pmap); 842 for (i = 0; i < pregions_sz; i++) { 843 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 844 pregions[i].mr_size; pa += moea64_large_page_size) { 845 pte_lo = LPTE_M; 846 if (pa & moea64_large_page_mask) { 847 pa &= moea64_large_page_mask; 848 pte_lo |= LPTE_G; 849 } 850 if (pa + moea64_large_page_size > 851 pregions[i].mr_start + pregions[i].mr_size) 852 pte_lo |= LPTE_G; 853 854 moea64_kenter_large(PHYS_TO_DMAP(pa), pa, pte_lo, 1); 855 } 856 } 857 PMAP_UNLOCK(kernel_pmap); 858 } 859 860 /* 861 * Make sure the kernel and BPVO pool stay mapped on systems either 862 * without a direct map or on which the kernel is not already executing 863 * out of the direct-mapped region. 864 */ 865 if (kernelstart < DMAP_BASE_ADDRESS) { 866 /* 867 * For pre-dmap execution, we need to use identity mapping 868 * because we will be operating with the mmu on but in the 869 * wrong address configuration until we __restartkernel(). 870 */ 871 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 872 pa += PAGE_SIZE) 873 moea64_kenter(pa, pa); 874 } else if (!hw_direct_map) { 875 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 876 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 877 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 878 pa += PAGE_SIZE) 879 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 880 } 881 882 if (!hw_direct_map) { 883 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 884 off = (vm_offset_t)(moea64_bpvo_pool); 885 for (pa = off; pa < off + size; pa += PAGE_SIZE) 886 moea64_kenter(pa, pa); 887 888 /* Map exception vectors */ 889 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 890 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 891 } 892 ENABLE_TRANS(msr); 893 894 /* 895 * Allow user to override unmapped_buf_allowed for testing. 896 * XXXKIB Only direct map implementation was tested. 897 */ 898 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 899 &unmapped_buf_allowed)) 900 unmapped_buf_allowed = hw_direct_map; 901 } 902 903 /* Quick sort callout for comparing physical addresses. */ 904 static int 905 pa_cmp(const void *a, const void *b) 906 { 907 const vm_paddr_t *pa = a, *pb = b; 908 909 if (*pa < *pb) 910 return (-1); 911 else if (*pa > *pb) 912 return (1); 913 else 914 return (0); 915 } 916 917 void 918 moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 919 { 920 int i, j; 921 vm_size_t physsz, hwphyssz; 922 vm_paddr_t kernelphysstart, kernelphysend; 923 int rm_pavail; 924 925 /* Level 0 reservations consist of 4096 pages (16MB superpage). */ 926 vm_level_0_order = 12; 927 928 #ifndef __powerpc64__ 929 /* We don't have a direct map since there is no BAT */ 930 hw_direct_map = 0; 931 932 /* Make sure battable is zero, since we have no BAT */ 933 for (i = 0; i < 16; i++) { 934 battable[i].batu = 0; 935 battable[i].batl = 0; 936 } 937 #else 938 moea64_probe_large_page(); 939 940 /* Use a direct map if we have large page support */ 941 if (moea64_large_page_size > 0) 942 hw_direct_map = 1; 943 else 944 hw_direct_map = 0; 945 946 /* Install trap handlers for SLBs */ 947 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 948 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 949 __syncicache((void *)EXC_DSE, 0x80); 950 __syncicache((void *)EXC_ISE, 0x80); 951 #endif 952 953 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 954 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 955 956 /* Get physical memory regions from firmware */ 957 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 958 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 959 960 if (PHYS_AVAIL_ENTRIES < regions_sz) 961 panic("moea64_bootstrap: phys_avail too small"); 962 963 phys_avail_count = 0; 964 physsz = 0; 965 hwphyssz = 0; 966 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 967 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 968 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 969 regions[i].mr_start, regions[i].mr_start + 970 regions[i].mr_size, regions[i].mr_size); 971 if (hwphyssz != 0 && 972 (physsz + regions[i].mr_size) >= hwphyssz) { 973 if (physsz < hwphyssz) { 974 phys_avail[j] = regions[i].mr_start; 975 phys_avail[j + 1] = regions[i].mr_start + 976 hwphyssz - physsz; 977 physsz = hwphyssz; 978 phys_avail_count++; 979 dump_avail[j] = phys_avail[j]; 980 dump_avail[j + 1] = phys_avail[j + 1]; 981 } 982 break; 983 } 984 phys_avail[j] = regions[i].mr_start; 985 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 986 phys_avail_count++; 987 physsz += regions[i].mr_size; 988 dump_avail[j] = phys_avail[j]; 989 dump_avail[j + 1] = phys_avail[j + 1]; 990 } 991 992 /* Check for overlap with the kernel and exception vectors */ 993 rm_pavail = 0; 994 for (j = 0; j < 2*phys_avail_count; j+=2) { 995 if (phys_avail[j] < EXC_LAST) 996 phys_avail[j] += EXC_LAST; 997 998 if (phys_avail[j] >= kernelphysstart && 999 phys_avail[j+1] <= kernelphysend) { 1000 phys_avail[j] = phys_avail[j+1] = ~0; 1001 rm_pavail++; 1002 continue; 1003 } 1004 1005 if (kernelphysstart >= phys_avail[j] && 1006 kernelphysstart < phys_avail[j+1]) { 1007 if (kernelphysend < phys_avail[j+1]) { 1008 phys_avail[2*phys_avail_count] = 1009 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 1010 phys_avail[2*phys_avail_count + 1] = 1011 phys_avail[j+1]; 1012 phys_avail_count++; 1013 } 1014 1015 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 1016 } 1017 1018 if (kernelphysend >= phys_avail[j] && 1019 kernelphysend < phys_avail[j+1]) { 1020 if (kernelphysstart > phys_avail[j]) { 1021 phys_avail[2*phys_avail_count] = phys_avail[j]; 1022 phys_avail[2*phys_avail_count + 1] = 1023 kernelphysstart & ~PAGE_MASK; 1024 phys_avail_count++; 1025 } 1026 1027 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 1028 PAGE_SIZE; 1029 } 1030 } 1031 1032 /* Remove physical available regions marked for removal (~0) */ 1033 if (rm_pavail) { 1034 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 1035 pa_cmp); 1036 phys_avail_count -= rm_pavail; 1037 for (i = 2*phys_avail_count; 1038 i < 2*(phys_avail_count + rm_pavail); i+=2) 1039 phys_avail[i] = phys_avail[i+1] = 0; 1040 } 1041 1042 physmem = btoc(physsz); 1043 1044 #ifdef PTEGCOUNT 1045 moea64_pteg_count = PTEGCOUNT; 1046 #else 1047 moea64_pteg_count = 0x1000; 1048 1049 while (moea64_pteg_count < physmem) 1050 moea64_pteg_count <<= 1; 1051 1052 moea64_pteg_count >>= 1; 1053 #endif /* PTEGCOUNT */ 1054 } 1055 1056 void 1057 moea64_mid_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 1058 { 1059 int i; 1060 1061 /* 1062 * Set PTEG mask 1063 */ 1064 moea64_pteg_mask = moea64_pteg_count - 1; 1065 1066 /* 1067 * Initialize SLB table lock and page locks 1068 */ 1069 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 1070 for (i = 0; i < PV_LOCK_COUNT; i++) 1071 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 1072 1073 /* 1074 * Initialise the bootstrap pvo pool. 1075 */ 1076 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 1077 if (moea64_bpvo_pool_size == 0) { 1078 if (!hw_direct_map) 1079 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) / 1080 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR; 1081 else 1082 moea64_bpvo_pool_size = BPVO_POOL_SIZE; 1083 } 1084 1085 if (boothowto & RB_VERBOSE) { 1086 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n", 1087 moea64_bpvo_pool_size, 1088 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576); 1089 } 1090 1091 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 1092 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 1093 moea64_bpvo_pool_index = 0; 1094 1095 /* Place at address usable through the direct map */ 1096 if (hw_direct_map) 1097 moea64_bpvo_pool = (struct pvo_entry *) 1098 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 1099 1100 /* 1101 * Make sure kernel vsid is allocated as well as VSID 0. 1102 */ 1103 #ifndef __powerpc64__ 1104 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 1105 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 1106 moea64_vsid_bitmap[0] |= 1; 1107 #endif 1108 1109 /* 1110 * Initialize the kernel pmap (which is statically allocated). 1111 */ 1112 #ifdef __powerpc64__ 1113 for (i = 0; i < 64; i++) { 1114 pcpup->pc_aim.slb[i].slbv = 0; 1115 pcpup->pc_aim.slb[i].slbe = 0; 1116 } 1117 #else 1118 for (i = 0; i < 16; i++) 1119 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 1120 #endif 1121 1122 kernel_pmap->pmap_phys = kernel_pmap; 1123 CPU_FILL(&kernel_pmap->pm_active); 1124 RB_INIT(&kernel_pmap->pmap_pvo); 1125 1126 PMAP_LOCK_INIT(kernel_pmap); 1127 1128 /* 1129 * Now map in all the other buffers we allocated earlier 1130 */ 1131 1132 moea64_setup_direct_map(kernelstart, kernelend); 1133 } 1134 1135 void 1136 moea64_late_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 1137 { 1138 ihandle_t mmui; 1139 phandle_t chosen; 1140 phandle_t mmu; 1141 ssize_t sz; 1142 int i; 1143 vm_offset_t pa, va; 1144 void *dpcpu; 1145 1146 /* 1147 * Set up the Open Firmware pmap and add its mappings if not in real 1148 * mode. 1149 */ 1150 1151 chosen = OF_finddevice("/chosen"); 1152 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 1153 mmu = OF_instance_to_package(mmui); 1154 if (mmu == -1 || 1155 (sz = OF_getproplen(mmu, "translations")) == -1) 1156 sz = 0; 1157 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1158 panic("moea64_bootstrap: too many ofw translations"); 1159 1160 if (sz > 0) 1161 moea64_add_ofw_mappings(mmu, sz); 1162 } 1163 1164 /* 1165 * Calculate the last available physical address. 1166 */ 1167 Maxmem = 0; 1168 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1169 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 1170 1171 /* 1172 * Initialize MMU. 1173 */ 1174 pmap_cpu_bootstrap(0); 1175 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1176 pmap_bootstrapped++; 1177 1178 /* 1179 * Set the start and end of kva. 1180 */ 1181 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1182 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1183 1184 /* 1185 * Map the entire KVA range into the SLB. We must not fault there. 1186 */ 1187 #ifdef __powerpc64__ 1188 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1189 moea64_bootstrap_slb_prefault(va, 0); 1190 #endif 1191 1192 /* 1193 * Remap any early IO mappings (console framebuffer, etc.) 1194 */ 1195 bs_remap_earlyboot(); 1196 1197 /* 1198 * Figure out how far we can extend virtual_end into segment 16 1199 * without running into existing mappings. Segment 16 is guaranteed 1200 * to contain neither RAM nor devices (at least on Apple hardware), 1201 * but will generally contain some OFW mappings we should not 1202 * step on. 1203 */ 1204 1205 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1206 PMAP_LOCK(kernel_pmap); 1207 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1208 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1209 virtual_end += PAGE_SIZE; 1210 PMAP_UNLOCK(kernel_pmap); 1211 #endif 1212 1213 /* 1214 * Allocate a kernel stack with a guard page for thread0 and map it 1215 * into the kernel page map. 1216 */ 1217 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1218 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1219 virtual_avail = va + kstack_pages * PAGE_SIZE; 1220 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1221 thread0.td_kstack = va; 1222 thread0.td_kstack_pages = kstack_pages; 1223 for (i = 0; i < kstack_pages; i++) { 1224 moea64_kenter(va, pa); 1225 pa += PAGE_SIZE; 1226 va += PAGE_SIZE; 1227 } 1228 1229 /* 1230 * Allocate virtual address space for the message buffer. 1231 */ 1232 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1233 msgbufp = (struct msgbuf *)virtual_avail; 1234 va = virtual_avail; 1235 virtual_avail += round_page(msgbufsize); 1236 while (va < virtual_avail) { 1237 moea64_kenter(va, pa); 1238 pa += PAGE_SIZE; 1239 va += PAGE_SIZE; 1240 } 1241 1242 /* 1243 * Allocate virtual address space for the dynamic percpu area. 1244 */ 1245 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1246 dpcpu = (void *)virtual_avail; 1247 va = virtual_avail; 1248 virtual_avail += DPCPU_SIZE; 1249 while (va < virtual_avail) { 1250 moea64_kenter(va, pa); 1251 pa += PAGE_SIZE; 1252 va += PAGE_SIZE; 1253 } 1254 dpcpu_init(dpcpu, curcpu); 1255 1256 crashdumpmap = (caddr_t)virtual_avail; 1257 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1258 1259 /* 1260 * Allocate some things for page zeroing. We put this directly 1261 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1262 * of the PVO book-keeping or other parts of the VM system 1263 * from even knowing that this hack exists. 1264 */ 1265 1266 if (!hw_direct_map) { 1267 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1268 MTX_DEF); 1269 for (i = 0; i < 2; i++) { 1270 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1271 virtual_end -= PAGE_SIZE; 1272 1273 moea64_kenter(moea64_scratchpage_va[i], 0); 1274 1275 PMAP_LOCK(kernel_pmap); 1276 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1277 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1278 PMAP_UNLOCK(kernel_pmap); 1279 } 1280 } 1281 1282 numa_mem_regions(&numa_pregions, &numapregions_sz); 1283 } 1284 1285 static void 1286 moea64_pmap_init_qpages(void) 1287 { 1288 struct pcpu *pc; 1289 int i; 1290 1291 if (hw_direct_map) 1292 return; 1293 1294 CPU_FOREACH(i) { 1295 pc = pcpu_find(i); 1296 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1297 if (pc->pc_qmap_addr == 0) 1298 panic("pmap_init_qpages: unable to allocate KVA"); 1299 PMAP_LOCK(kernel_pmap); 1300 pc->pc_aim.qmap_pvo = 1301 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1302 PMAP_UNLOCK(kernel_pmap); 1303 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1304 } 1305 } 1306 1307 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1308 1309 /* 1310 * Activate a user pmap. This mostly involves setting some non-CPU 1311 * state. 1312 */ 1313 void 1314 moea64_activate(struct thread *td) 1315 { 1316 pmap_t pm; 1317 1318 pm = &td->td_proc->p_vmspace->vm_pmap; 1319 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1320 1321 #ifdef __powerpc64__ 1322 PCPU_SET(aim.userslb, pm->pm_slb); 1323 __asm __volatile("slbmte %0, %1; isync" :: 1324 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1325 #else 1326 PCPU_SET(curpmap, pm->pmap_phys); 1327 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1328 #endif 1329 } 1330 1331 void 1332 moea64_deactivate(struct thread *td) 1333 { 1334 pmap_t pm; 1335 1336 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1337 1338 pm = &td->td_proc->p_vmspace->vm_pmap; 1339 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1340 #ifdef __powerpc64__ 1341 PCPU_SET(aim.userslb, NULL); 1342 #else 1343 PCPU_SET(curpmap, NULL); 1344 #endif 1345 } 1346 1347 void 1348 moea64_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1349 { 1350 struct pvo_entry key, *pvo; 1351 vm_page_t m; 1352 int64_t refchg; 1353 1354 key.pvo_vaddr = sva; 1355 PMAP_LOCK(pm); 1356 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1357 pvo != NULL && PVO_VADDR(pvo) < eva; 1358 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1359 if (PVO_IS_SP(pvo)) { 1360 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 1361 pvo = moea64_sp_unwire(pvo); 1362 continue; 1363 } else { 1364 CTR1(KTR_PMAP, "%s: demote before unwire", 1365 __func__); 1366 moea64_sp_demote(pvo); 1367 } 1368 } 1369 1370 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1371 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1372 pvo); 1373 pvo->pvo_vaddr &= ~PVO_WIRED; 1374 refchg = moea64_pte_replace(pvo, 0 /* No invalidation */); 1375 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1376 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1377 if (refchg < 0) 1378 refchg = LPTE_CHG; 1379 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1380 1381 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1382 if (refchg & LPTE_CHG) 1383 vm_page_dirty(m); 1384 if (refchg & LPTE_REF) 1385 vm_page_aflag_set(m, PGA_REFERENCED); 1386 } 1387 pm->pm_stats.wired_count--; 1388 } 1389 PMAP_UNLOCK(pm); 1390 } 1391 1392 static int 1393 moea64_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 1394 { 1395 struct pvo_entry *pvo; 1396 vm_paddr_t pa; 1397 vm_page_t m; 1398 int val; 1399 bool managed; 1400 1401 PMAP_LOCK(pmap); 1402 1403 pvo = moea64_pvo_find_va(pmap, addr); 1404 if (pvo != NULL) { 1405 pa = PVO_PADDR(pvo); 1406 m = PHYS_TO_VM_PAGE(pa); 1407 managed = (pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED; 1408 if (PVO_IS_SP(pvo)) 1409 val = MINCORE_INCORE | MINCORE_PSIND(1); 1410 else 1411 val = MINCORE_INCORE; 1412 } else { 1413 PMAP_UNLOCK(pmap); 1414 return (0); 1415 } 1416 1417 PMAP_UNLOCK(pmap); 1418 1419 if (m == NULL) 1420 return (0); 1421 1422 if (managed) { 1423 if (moea64_is_modified(m)) 1424 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 1425 1426 if (moea64_is_referenced(m)) 1427 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 1428 } 1429 1430 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 1431 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 1432 managed) { 1433 *pap = pa; 1434 } 1435 1436 return (val); 1437 } 1438 1439 /* 1440 * This goes through and sets the physical address of our 1441 * special scratch PTE to the PA we want to zero or copy. Because 1442 * of locking issues (this can get called in pvo_enter() by 1443 * the UMA allocator), we can't use most other utility functions here 1444 */ 1445 1446 static __inline 1447 void moea64_set_scratchpage_pa(int which, vm_paddr_t pa) 1448 { 1449 struct pvo_entry *pvo; 1450 1451 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1452 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1453 1454 pvo = moea64_scratchpage_pvo[which]; 1455 PMAP_LOCK(pvo->pvo_pmap); 1456 pvo->pvo_pte.pa = 1457 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1458 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1459 PMAP_UNLOCK(pvo->pvo_pmap); 1460 isync(); 1461 } 1462 1463 void 1464 moea64_copy_page(vm_page_t msrc, vm_page_t mdst) 1465 { 1466 vm_offset_t dst; 1467 vm_offset_t src; 1468 1469 dst = VM_PAGE_TO_PHYS(mdst); 1470 src = VM_PAGE_TO_PHYS(msrc); 1471 1472 if (hw_direct_map) { 1473 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1474 PAGE_SIZE); 1475 } else { 1476 mtx_lock(&moea64_scratchpage_mtx); 1477 1478 moea64_set_scratchpage_pa(0, src); 1479 moea64_set_scratchpage_pa(1, dst); 1480 1481 bcopy((void *)moea64_scratchpage_va[0], 1482 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1483 1484 mtx_unlock(&moea64_scratchpage_mtx); 1485 } 1486 } 1487 1488 static inline void 1489 moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 1490 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1491 { 1492 void *a_cp, *b_cp; 1493 vm_offset_t a_pg_offset, b_pg_offset; 1494 int cnt; 1495 1496 while (xfersize > 0) { 1497 a_pg_offset = a_offset & PAGE_MASK; 1498 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1499 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1500 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1501 a_pg_offset; 1502 b_pg_offset = b_offset & PAGE_MASK; 1503 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1504 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1505 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1506 b_pg_offset; 1507 bcopy(a_cp, b_cp, cnt); 1508 a_offset += cnt; 1509 b_offset += cnt; 1510 xfersize -= cnt; 1511 } 1512 } 1513 1514 static inline void 1515 moea64_copy_pages_nodmap(vm_page_t *ma, vm_offset_t a_offset, 1516 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1517 { 1518 void *a_cp, *b_cp; 1519 vm_offset_t a_pg_offset, b_pg_offset; 1520 int cnt; 1521 1522 mtx_lock(&moea64_scratchpage_mtx); 1523 while (xfersize > 0) { 1524 a_pg_offset = a_offset & PAGE_MASK; 1525 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1526 moea64_set_scratchpage_pa(0, 1527 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1528 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1529 b_pg_offset = b_offset & PAGE_MASK; 1530 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1531 moea64_set_scratchpage_pa(1, 1532 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1533 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1534 bcopy(a_cp, b_cp, cnt); 1535 a_offset += cnt; 1536 b_offset += cnt; 1537 xfersize -= cnt; 1538 } 1539 mtx_unlock(&moea64_scratchpage_mtx); 1540 } 1541 1542 void 1543 moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1544 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1545 { 1546 1547 if (hw_direct_map) { 1548 moea64_copy_pages_dmap(ma, a_offset, mb, b_offset, 1549 xfersize); 1550 } else { 1551 moea64_copy_pages_nodmap(ma, a_offset, mb, b_offset, 1552 xfersize); 1553 } 1554 } 1555 1556 void 1557 moea64_zero_page_area(vm_page_t m, int off, int size) 1558 { 1559 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1560 1561 if (size + off > PAGE_SIZE) 1562 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1563 1564 if (hw_direct_map) { 1565 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1566 } else { 1567 mtx_lock(&moea64_scratchpage_mtx); 1568 moea64_set_scratchpage_pa(0, pa); 1569 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1570 mtx_unlock(&moea64_scratchpage_mtx); 1571 } 1572 } 1573 1574 /* 1575 * Zero a page of physical memory by temporarily mapping it 1576 */ 1577 void 1578 moea64_zero_page(vm_page_t m) 1579 { 1580 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1581 vm_offset_t va, off; 1582 1583 if (!hw_direct_map) { 1584 mtx_lock(&moea64_scratchpage_mtx); 1585 1586 moea64_set_scratchpage_pa(0, pa); 1587 va = moea64_scratchpage_va[0]; 1588 } else { 1589 va = PHYS_TO_DMAP(pa); 1590 } 1591 1592 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1593 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1594 1595 if (!hw_direct_map) 1596 mtx_unlock(&moea64_scratchpage_mtx); 1597 } 1598 1599 vm_offset_t 1600 moea64_quick_enter_page(vm_page_t m) 1601 { 1602 struct pvo_entry *pvo; 1603 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1604 1605 if (hw_direct_map) 1606 return (PHYS_TO_DMAP(pa)); 1607 1608 /* 1609 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1610 * a critical section and access the PCPU data like on i386. 1611 * Instead, pin the thread and grab the PCPU lock to prevent 1612 * a preempting thread from using the same PCPU data. 1613 */ 1614 sched_pin(); 1615 1616 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1617 pvo = PCPU_GET(aim.qmap_pvo); 1618 1619 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1620 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1621 (uint64_t)pa; 1622 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1623 isync(); 1624 1625 return (PCPU_GET(qmap_addr)); 1626 } 1627 1628 void 1629 moea64_quick_remove_page(vm_offset_t addr) 1630 { 1631 if (hw_direct_map) 1632 return; 1633 1634 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1635 KASSERT(PCPU_GET(qmap_addr) == addr, 1636 ("moea64_quick_remove_page: invalid address")); 1637 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1638 sched_unpin(); 1639 } 1640 1641 boolean_t 1642 moea64_page_is_mapped(vm_page_t m) 1643 { 1644 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1645 } 1646 1647 /* 1648 * Map the given physical page at the specified virtual address in the 1649 * target pmap with the protection requested. If specified the page 1650 * will be wired down. 1651 */ 1652 1653 int 1654 moea64_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1655 vm_prot_t prot, u_int flags, int8_t psind) 1656 { 1657 struct pvo_entry *pvo, *oldpvo, *tpvo; 1658 struct pvo_head *pvo_head; 1659 uint64_t pte_lo; 1660 int error; 1661 vm_paddr_t pa; 1662 1663 if ((m->oflags & VPO_UNMANAGED) == 0) { 1664 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1665 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1666 else 1667 VM_OBJECT_ASSERT_LOCKED(m->object); 1668 } 1669 1670 if (psind > 0) 1671 return (moea64_sp_enter(pmap, va, m, prot, flags, psind)); 1672 1673 pvo = alloc_pvo_entry(0); 1674 if (pvo == NULL) 1675 return (KERN_RESOURCE_SHORTAGE); 1676 pvo->pvo_pmap = NULL; /* to be filled in later */ 1677 pvo->pvo_pte.prot = prot; 1678 1679 pa = VM_PAGE_TO_PHYS(m); 1680 pte_lo = moea64_calc_wimg(pa, pmap_page_get_memattr(m)); 1681 pvo->pvo_pte.pa = pa | pte_lo; 1682 1683 if ((flags & PMAP_ENTER_WIRED) != 0) 1684 pvo->pvo_vaddr |= PVO_WIRED; 1685 1686 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1687 pvo_head = NULL; 1688 } else { 1689 pvo_head = &m->md.mdpg_pvoh; 1690 pvo->pvo_vaddr |= PVO_MANAGED; 1691 } 1692 1693 PV_LOCK(pa); 1694 PMAP_LOCK(pmap); 1695 if (pvo->pvo_pmap == NULL) 1696 init_pvo_entry(pvo, pmap, va); 1697 1698 if (moea64_ps_enabled(pmap) && 1699 (tpvo = moea64_pvo_find_va(pmap, va & ~HPT_SP_MASK)) != NULL && 1700 PVO_IS_SP(tpvo)) { 1701 /* Demote SP before entering a regular page */ 1702 CTR2(KTR_PMAP, "%s: demote before enter: va=%#jx", 1703 __func__, (uintmax_t)va); 1704 moea64_sp_demote_aligned(tpvo); 1705 } 1706 1707 if (prot & VM_PROT_WRITE) 1708 if (pmap_bootstrapped && 1709 (m->oflags & VPO_UNMANAGED) == 0) 1710 vm_page_aflag_set(m, PGA_WRITEABLE); 1711 1712 error = moea64_pvo_enter(pvo, pvo_head, &oldpvo); 1713 if (error == EEXIST) { 1714 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1715 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1716 oldpvo->pvo_pte.prot == prot) { 1717 /* Identical mapping already exists */ 1718 error = 0; 1719 1720 /* If not in page table, reinsert it */ 1721 if (moea64_pte_synch(oldpvo) < 0) { 1722 STAT_MOEA64(moea64_pte_overflow--); 1723 moea64_pte_insert(oldpvo); 1724 } 1725 1726 /* Then just clean up and go home */ 1727 PMAP_UNLOCK(pmap); 1728 PV_UNLOCK(pa); 1729 free_pvo_entry(pvo); 1730 pvo = NULL; 1731 goto out; 1732 } else { 1733 /* Otherwise, need to kill it first */ 1734 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1735 "mapping does not match new mapping")); 1736 moea64_pvo_remove_from_pmap(oldpvo); 1737 moea64_pvo_enter(pvo, pvo_head, NULL); 1738 } 1739 } 1740 PMAP_UNLOCK(pmap); 1741 PV_UNLOCK(pa); 1742 1743 /* Free any dead pages */ 1744 if (error == EEXIST) { 1745 moea64_pvo_remove_from_page(oldpvo); 1746 free_pvo_entry(oldpvo); 1747 } 1748 1749 out: 1750 /* 1751 * Flush the page from the instruction cache if this page is 1752 * mapped executable and cacheable. 1753 */ 1754 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1755 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1756 vm_page_aflag_set(m, PGA_EXECUTABLE); 1757 moea64_syncicache(pmap, va, pa, PAGE_SIZE); 1758 } 1759 1760 #if VM_NRESERVLEVEL > 0 1761 /* 1762 * Try to promote pages. 1763 * 1764 * If the VA of the entered page is not aligned with its PA, 1765 * don't try page promotion as it is not possible. 1766 * This reduces the number of promotion failures dramatically. 1767 */ 1768 if (moea64_ps_enabled(pmap) && pmap != kernel_pmap && pvo != NULL && 1769 (pvo->pvo_vaddr & PVO_MANAGED) != 0 && 1770 (va & HPT_SP_MASK) == (pa & HPT_SP_MASK) && 1771 (m->flags & PG_FICTITIOUS) == 0 && 1772 vm_reserv_level_iffullpop(m) == 0) 1773 moea64_sp_promote(pmap, va, m); 1774 #endif 1775 1776 return (KERN_SUCCESS); 1777 } 1778 1779 static void 1780 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1781 vm_size_t sz) 1782 { 1783 1784 /* 1785 * This is much trickier than on older systems because 1786 * we can't sync the icache on physical addresses directly 1787 * without a direct map. Instead we check a couple of cases 1788 * where the memory is already mapped in and, failing that, 1789 * use the same trick we use for page zeroing to create 1790 * a temporary mapping for this physical address. 1791 */ 1792 1793 if (!pmap_bootstrapped) { 1794 /* 1795 * If PMAP is not bootstrapped, we are likely to be 1796 * in real mode. 1797 */ 1798 __syncicache((void *)(uintptr_t)pa, sz); 1799 } else if (pmap == kernel_pmap) { 1800 __syncicache((void *)va, sz); 1801 } else if (hw_direct_map) { 1802 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1803 } else { 1804 /* Use the scratch page to set up a temp mapping */ 1805 1806 mtx_lock(&moea64_scratchpage_mtx); 1807 1808 moea64_set_scratchpage_pa(1, pa & ~ADDR_POFF); 1809 __syncicache((void *)(moea64_scratchpage_va[1] + 1810 (va & ADDR_POFF)), sz); 1811 1812 mtx_unlock(&moea64_scratchpage_mtx); 1813 } 1814 } 1815 1816 /* 1817 * Maps a sequence of resident pages belonging to the same object. 1818 * The sequence begins with the given page m_start. This page is 1819 * mapped at the given virtual address start. Each subsequent page is 1820 * mapped at a virtual address that is offset from start by the same 1821 * amount as the page is offset from m_start within the object. The 1822 * last page in the sequence is the page with the largest offset from 1823 * m_start that can be mapped at a virtual address less than the given 1824 * virtual address end. Not every virtual page between start and end 1825 * is mapped; only those for which a resident page exists with the 1826 * corresponding offset from m_start are mapped. 1827 */ 1828 void 1829 moea64_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1830 vm_page_t m_start, vm_prot_t prot) 1831 { 1832 vm_page_t m; 1833 vm_pindex_t diff, psize; 1834 vm_offset_t va; 1835 int8_t psind; 1836 1837 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1838 1839 psize = atop(end - start); 1840 m = m_start; 1841 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1842 va = start + ptoa(diff); 1843 if ((va & HPT_SP_MASK) == 0 && va + HPT_SP_SIZE <= end && 1844 m->psind == 1 && moea64_ps_enabled(pm)) 1845 psind = 1; 1846 else 1847 psind = 0; 1848 moea64_enter(pm, va, m, prot & 1849 (VM_PROT_READ | VM_PROT_EXECUTE), 1850 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, psind); 1851 if (psind == 1) 1852 m = &m[HPT_SP_SIZE / PAGE_SIZE - 1]; 1853 m = TAILQ_NEXT(m, listq); 1854 } 1855 } 1856 1857 void 1858 moea64_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1859 vm_prot_t prot) 1860 { 1861 1862 moea64_enter(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1863 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1864 } 1865 1866 vm_paddr_t 1867 moea64_extract(pmap_t pm, vm_offset_t va) 1868 { 1869 struct pvo_entry *pvo; 1870 vm_paddr_t pa; 1871 1872 PMAP_LOCK(pm); 1873 pvo = moea64_pvo_find_va(pm, va); 1874 if (pvo == NULL) 1875 pa = 0; 1876 else 1877 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 1878 PMAP_UNLOCK(pm); 1879 1880 return (pa); 1881 } 1882 1883 /* 1884 * Atomically extract and hold the physical page with the given 1885 * pmap and virtual address pair if that mapping permits the given 1886 * protection. 1887 */ 1888 vm_page_t 1889 moea64_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1890 { 1891 struct pvo_entry *pvo; 1892 vm_page_t m; 1893 1894 m = NULL; 1895 PMAP_LOCK(pmap); 1896 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1897 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1898 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1899 if (!vm_page_wire_mapped(m)) 1900 m = NULL; 1901 } 1902 PMAP_UNLOCK(pmap); 1903 return (m); 1904 } 1905 1906 static void * 1907 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1908 uint8_t *flags, int wait) 1909 { 1910 struct pvo_entry *pvo; 1911 vm_offset_t va; 1912 vm_page_t m; 1913 int needed_lock; 1914 1915 /* 1916 * This entire routine is a horrible hack to avoid bothering kmem 1917 * for new KVA addresses. Because this can get called from inside 1918 * kmem allocation routines, calling kmem for a new address here 1919 * can lead to multiply locking non-recursive mutexes. 1920 */ 1921 1922 *flags = UMA_SLAB_PRIV; 1923 needed_lock = !PMAP_LOCKED(kernel_pmap); 1924 1925 m = vm_page_alloc_domain(NULL, 0, domain, 1926 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1927 if (m == NULL) 1928 return (NULL); 1929 1930 va = VM_PAGE_TO_PHYS(m); 1931 1932 pvo = alloc_pvo_entry(1 /* bootstrap */); 1933 1934 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1935 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1936 1937 if (needed_lock) 1938 PMAP_LOCK(kernel_pmap); 1939 1940 init_pvo_entry(pvo, kernel_pmap, va); 1941 pvo->pvo_vaddr |= PVO_WIRED; 1942 1943 moea64_pvo_enter(pvo, NULL, NULL); 1944 1945 if (needed_lock) 1946 PMAP_UNLOCK(kernel_pmap); 1947 1948 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1949 bzero((void *)va, PAGE_SIZE); 1950 1951 return (void *)va; 1952 } 1953 1954 extern int elf32_nxstack; 1955 1956 void 1957 moea64_init() 1958 { 1959 1960 CTR0(KTR_PMAP, "moea64_init"); 1961 1962 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1963 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1964 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1965 1966 /* 1967 * Are large page mappings enabled? 1968 * 1969 * While HPT superpages are not better tested, leave it disabled by 1970 * default. 1971 */ 1972 superpages_enabled = 0; 1973 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 1974 if (superpages_enabled) { 1975 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1976 ("moea64_init: can't assign to pagesizes[1]")); 1977 1978 if (moea64_large_page_size == 0) { 1979 printf("mmu_oea64: HW does not support large pages. " 1980 "Disabling superpages...\n"); 1981 superpages_enabled = 0; 1982 } else if (!moea64_has_lp_4k_16m) { 1983 printf("mmu_oea64: " 1984 "HW does not support mixed 4KB/16MB page sizes. " 1985 "Disabling superpages...\n"); 1986 superpages_enabled = 0; 1987 } else 1988 pagesizes[1] = HPT_SP_SIZE; 1989 } 1990 1991 if (!hw_direct_map) { 1992 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1993 } 1994 1995 #ifdef COMPAT_FREEBSD32 1996 elf32_nxstack = 1; 1997 #endif 1998 1999 moea64_initialized = TRUE; 2000 } 2001 2002 boolean_t 2003 moea64_is_referenced(vm_page_t m) 2004 { 2005 2006 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2007 ("moea64_is_referenced: page %p is not managed", m)); 2008 2009 return (moea64_query_bit(m, LPTE_REF)); 2010 } 2011 2012 boolean_t 2013 moea64_is_modified(vm_page_t m) 2014 { 2015 2016 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2017 ("moea64_is_modified: page %p is not managed", m)); 2018 2019 /* 2020 * If the page is not busied then this check is racy. 2021 */ 2022 if (!pmap_page_is_write_mapped(m)) 2023 return (FALSE); 2024 2025 return (moea64_query_bit(m, LPTE_CHG)); 2026 } 2027 2028 boolean_t 2029 moea64_is_prefaultable(pmap_t pmap, vm_offset_t va) 2030 { 2031 struct pvo_entry *pvo; 2032 boolean_t rv = TRUE; 2033 2034 PMAP_LOCK(pmap); 2035 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 2036 if (pvo != NULL) 2037 rv = FALSE; 2038 PMAP_UNLOCK(pmap); 2039 return (rv); 2040 } 2041 2042 void 2043 moea64_clear_modify(vm_page_t m) 2044 { 2045 2046 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2047 ("moea64_clear_modify: page %p is not managed", m)); 2048 vm_page_assert_busied(m); 2049 2050 if (!pmap_page_is_write_mapped(m)) 2051 return; 2052 moea64_clear_bit(m, LPTE_CHG); 2053 } 2054 2055 /* 2056 * Clear the write and modified bits in each of the given page's mappings. 2057 */ 2058 void 2059 moea64_remove_write(vm_page_t m) 2060 { 2061 struct pvo_entry *pvo; 2062 int64_t refchg, ret; 2063 pmap_t pmap; 2064 2065 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2066 ("moea64_remove_write: page %p is not managed", m)); 2067 vm_page_assert_busied(m); 2068 2069 if (!pmap_page_is_write_mapped(m)) 2070 return; 2071 2072 powerpc_sync(); 2073 PV_PAGE_LOCK(m); 2074 refchg = 0; 2075 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2076 pmap = pvo->pvo_pmap; 2077 PMAP_LOCK(pmap); 2078 if (!(pvo->pvo_vaddr & PVO_DEAD) && 2079 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2080 if (PVO_IS_SP(pvo)) { 2081 CTR1(KTR_PMAP, "%s: demote before remwr", 2082 __func__); 2083 moea64_sp_demote(pvo); 2084 } 2085 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 2086 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2087 if (ret < 0) 2088 ret = LPTE_CHG; 2089 refchg |= ret; 2090 if (pvo->pvo_pmap == kernel_pmap) 2091 isync(); 2092 } 2093 PMAP_UNLOCK(pmap); 2094 } 2095 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 2096 vm_page_dirty(m); 2097 vm_page_aflag_clear(m, PGA_WRITEABLE); 2098 PV_PAGE_UNLOCK(m); 2099 } 2100 2101 /* 2102 * moea64_ts_referenced: 2103 * 2104 * Return a count of reference bits for a page, clearing those bits. 2105 * It is not necessary for every reference bit to be cleared, but it 2106 * is necessary that 0 only be returned when there are truly no 2107 * reference bits set. 2108 * 2109 * XXX: The exact number of bits to check and clear is a matter that 2110 * should be tested and standardized at some point in the future for 2111 * optimal aging of shared pages. 2112 */ 2113 int 2114 moea64_ts_referenced(vm_page_t m) 2115 { 2116 2117 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2118 ("moea64_ts_referenced: page %p is not managed", m)); 2119 return (moea64_clear_bit(m, LPTE_REF)); 2120 } 2121 2122 /* 2123 * Modify the WIMG settings of all mappings for a page. 2124 */ 2125 void 2126 moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma) 2127 { 2128 struct pvo_entry *pvo; 2129 int64_t refchg; 2130 pmap_t pmap; 2131 uint64_t lo; 2132 2133 CTR3(KTR_PMAP, "%s: pa=%#jx, ma=%#x", 2134 __func__, (uintmax_t)VM_PAGE_TO_PHYS(m), ma); 2135 2136 if ((m->oflags & VPO_UNMANAGED) != 0) { 2137 m->md.mdpg_cache_attrs = ma; 2138 return; 2139 } 2140 2141 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 2142 2143 PV_PAGE_LOCK(m); 2144 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2145 pmap = pvo->pvo_pmap; 2146 PMAP_LOCK(pmap); 2147 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 2148 if (PVO_IS_SP(pvo)) { 2149 CTR1(KTR_PMAP, 2150 "%s: demote before set_memattr", __func__); 2151 moea64_sp_demote(pvo); 2152 } 2153 pvo->pvo_pte.pa &= ~LPTE_WIMG; 2154 pvo->pvo_pte.pa |= lo; 2155 refchg = moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 2156 if (refchg < 0) 2157 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 2158 LPTE_CHG : 0; 2159 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2160 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2161 refchg |= 2162 atomic_readandclear_32(&m->md.mdpg_attrs); 2163 if (refchg & LPTE_CHG) 2164 vm_page_dirty(m); 2165 if (refchg & LPTE_REF) 2166 vm_page_aflag_set(m, PGA_REFERENCED); 2167 } 2168 if (pvo->pvo_pmap == kernel_pmap) 2169 isync(); 2170 } 2171 PMAP_UNLOCK(pmap); 2172 } 2173 m->md.mdpg_cache_attrs = ma; 2174 PV_PAGE_UNLOCK(m); 2175 } 2176 2177 /* 2178 * Map a wired page into kernel virtual address space. 2179 */ 2180 void 2181 moea64_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 2182 { 2183 int error; 2184 struct pvo_entry *pvo, *oldpvo; 2185 2186 do { 2187 pvo = alloc_pvo_entry(0); 2188 if (pvo == NULL) 2189 vm_wait(NULL); 2190 } while (pvo == NULL); 2191 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 2192 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 2193 pvo->pvo_vaddr |= PVO_WIRED; 2194 2195 PMAP_LOCK(kernel_pmap); 2196 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 2197 if (oldpvo != NULL) 2198 moea64_pvo_remove_from_pmap(oldpvo); 2199 init_pvo_entry(pvo, kernel_pmap, va); 2200 error = moea64_pvo_enter(pvo, NULL, NULL); 2201 PMAP_UNLOCK(kernel_pmap); 2202 2203 /* Free any dead pages */ 2204 if (oldpvo != NULL) { 2205 moea64_pvo_remove_from_page(oldpvo); 2206 free_pvo_entry(oldpvo); 2207 } 2208 2209 if (error != 0) 2210 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 2211 (uintmax_t)pa, error); 2212 } 2213 2214 void 2215 moea64_kenter(vm_offset_t va, vm_paddr_t pa) 2216 { 2217 2218 moea64_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 2219 } 2220 2221 /* 2222 * Extract the physical page address associated with the given kernel virtual 2223 * address. 2224 */ 2225 vm_paddr_t 2226 moea64_kextract(vm_offset_t va) 2227 { 2228 struct pvo_entry *pvo; 2229 vm_paddr_t pa; 2230 2231 /* 2232 * Shortcut the direct-mapped case when applicable. We never put 2233 * anything but 1:1 (or 62-bit aliased) mappings below 2234 * VM_MIN_KERNEL_ADDRESS. 2235 */ 2236 if (va < VM_MIN_KERNEL_ADDRESS) 2237 return (va & ~DMAP_BASE_ADDRESS); 2238 2239 PMAP_LOCK(kernel_pmap); 2240 pvo = moea64_pvo_find_va(kernel_pmap, va); 2241 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 2242 va)); 2243 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 2244 PMAP_UNLOCK(kernel_pmap); 2245 return (pa); 2246 } 2247 2248 /* 2249 * Remove a wired page from kernel virtual address space. 2250 */ 2251 void 2252 moea64_kremove(vm_offset_t va) 2253 { 2254 moea64_remove(kernel_pmap, va, va + PAGE_SIZE); 2255 } 2256 2257 /* 2258 * Provide a kernel pointer corresponding to a given userland pointer. 2259 * The returned pointer is valid until the next time this function is 2260 * called in this thread. This is used internally in copyin/copyout. 2261 */ 2262 static int 2263 moea64_map_user_ptr(pmap_t pm, volatile const void *uaddr, 2264 void **kaddr, size_t ulen, size_t *klen) 2265 { 2266 size_t l; 2267 #ifdef __powerpc64__ 2268 struct slb *slb; 2269 #endif 2270 register_t slbv; 2271 2272 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 2273 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 2274 if (l > ulen) 2275 l = ulen; 2276 if (klen) 2277 *klen = l; 2278 else if (l != ulen) 2279 return (EFAULT); 2280 2281 #ifdef __powerpc64__ 2282 /* Try lockless look-up first */ 2283 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 2284 2285 if (slb == NULL) { 2286 /* If it isn't there, we need to pre-fault the VSID */ 2287 PMAP_LOCK(pm); 2288 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 2289 PMAP_UNLOCK(pm); 2290 } else { 2291 slbv = slb->slbv; 2292 } 2293 2294 /* Mark segment no-execute */ 2295 slbv |= SLBV_N; 2296 #else 2297 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 2298 2299 /* Mark segment no-execute */ 2300 slbv |= SR_N; 2301 #endif 2302 2303 /* If we have already set this VSID, we can just return */ 2304 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 2305 return (0); 2306 2307 __asm __volatile("isync"); 2308 curthread->td_pcb->pcb_cpu.aim.usr_segm = 2309 (uintptr_t)uaddr >> ADDR_SR_SHFT; 2310 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 2311 #ifdef __powerpc64__ 2312 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2313 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2314 #else 2315 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2316 #endif 2317 2318 return (0); 2319 } 2320 2321 /* 2322 * Figure out where a given kernel pointer (usually in a fault) points 2323 * to from the VM's perspective, potentially remapping into userland's 2324 * address space. 2325 */ 2326 static int 2327 moea64_decode_kernel_ptr(vm_offset_t addr, int *is_user, 2328 vm_offset_t *decoded_addr) 2329 { 2330 vm_offset_t user_sr; 2331 2332 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2333 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2334 addr &= ADDR_PIDX | ADDR_POFF; 2335 addr |= user_sr << ADDR_SR_SHFT; 2336 *decoded_addr = addr; 2337 *is_user = 1; 2338 } else { 2339 *decoded_addr = addr; 2340 *is_user = 0; 2341 } 2342 2343 return (0); 2344 } 2345 2346 /* 2347 * Map a range of physical addresses into kernel virtual address space. 2348 * 2349 * The value passed in *virt is a suggested virtual address for the mapping. 2350 * Architectures which can support a direct-mapped physical to virtual region 2351 * can return the appropriate address within that region, leaving '*virt' 2352 * unchanged. Other architectures should map the pages starting at '*virt' and 2353 * update '*virt' with the first usable address after the mapped region. 2354 */ 2355 vm_offset_t 2356 moea64_map(vm_offset_t *virt, vm_paddr_t pa_start, 2357 vm_paddr_t pa_end, int prot) 2358 { 2359 vm_offset_t sva, va; 2360 2361 if (hw_direct_map) { 2362 /* 2363 * Check if every page in the region is covered by the direct 2364 * map. The direct map covers all of physical memory. Use 2365 * moea64_calc_wimg() as a shortcut to see if the page is in 2366 * physical memory as a way to see if the direct map covers it. 2367 */ 2368 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2369 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2370 break; 2371 if (va == pa_end) 2372 return (PHYS_TO_DMAP(pa_start)); 2373 } 2374 sva = *virt; 2375 va = sva; 2376 /* XXX respect prot argument */ 2377 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2378 moea64_kenter(va, pa_start); 2379 *virt = va; 2380 2381 return (sva); 2382 } 2383 2384 /* 2385 * Returns true if the pmap's pv is one of the first 2386 * 16 pvs linked to from this page. This count may 2387 * be changed upwards or downwards in the future; it 2388 * is only necessary that true be returned for a small 2389 * subset of pmaps for proper page aging. 2390 */ 2391 boolean_t 2392 moea64_page_exists_quick(pmap_t pmap, vm_page_t m) 2393 { 2394 int loops; 2395 struct pvo_entry *pvo; 2396 boolean_t rv; 2397 2398 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2399 ("moea64_page_exists_quick: page %p is not managed", m)); 2400 loops = 0; 2401 rv = FALSE; 2402 PV_PAGE_LOCK(m); 2403 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2404 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2405 rv = TRUE; 2406 break; 2407 } 2408 if (++loops >= 16) 2409 break; 2410 } 2411 PV_PAGE_UNLOCK(m); 2412 return (rv); 2413 } 2414 2415 void 2416 moea64_page_init(vm_page_t m) 2417 { 2418 2419 m->md.mdpg_attrs = 0; 2420 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2421 LIST_INIT(&m->md.mdpg_pvoh); 2422 } 2423 2424 /* 2425 * Return the number of managed mappings to the given physical page 2426 * that are wired. 2427 */ 2428 int 2429 moea64_page_wired_mappings(vm_page_t m) 2430 { 2431 struct pvo_entry *pvo; 2432 int count; 2433 2434 count = 0; 2435 if ((m->oflags & VPO_UNMANAGED) != 0) 2436 return (count); 2437 PV_PAGE_LOCK(m); 2438 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2439 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2440 count++; 2441 PV_PAGE_UNLOCK(m); 2442 return (count); 2443 } 2444 2445 static uintptr_t moea64_vsidcontext; 2446 2447 uintptr_t 2448 moea64_get_unique_vsid(void) { 2449 u_int entropy; 2450 register_t hash; 2451 uint32_t mask; 2452 int i; 2453 2454 entropy = 0; 2455 __asm __volatile("mftb %0" : "=r"(entropy)); 2456 2457 mtx_lock(&moea64_slb_mutex); 2458 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2459 u_int n; 2460 2461 /* 2462 * Create a new value by mutiplying by a prime and adding in 2463 * entropy from the timebase register. This is to make the 2464 * VSID more random so that the PT hash function collides 2465 * less often. (Note that the prime casues gcc to do shifts 2466 * instead of a multiply.) 2467 */ 2468 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2469 hash = moea64_vsidcontext & (NVSIDS - 1); 2470 if (hash == 0) /* 0 is special, avoid it */ 2471 continue; 2472 n = hash >> 5; 2473 mask = 1 << (hash & (VSID_NBPW - 1)); 2474 hash = (moea64_vsidcontext & VSID_HASHMASK); 2475 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2476 /* anything free in this bucket? */ 2477 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2478 entropy = (moea64_vsidcontext >> 20); 2479 continue; 2480 } 2481 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2482 mask = 1 << i; 2483 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2484 hash |= i; 2485 } 2486 if (hash == VSID_VRMA) /* also special, avoid this too */ 2487 continue; 2488 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2489 ("Allocating in-use VSID %#zx\n", hash)); 2490 moea64_vsid_bitmap[n] |= mask; 2491 mtx_unlock(&moea64_slb_mutex); 2492 return (hash); 2493 } 2494 2495 mtx_unlock(&moea64_slb_mutex); 2496 panic("%s: out of segments",__func__); 2497 } 2498 2499 #ifdef __powerpc64__ 2500 int 2501 moea64_pinit(pmap_t pmap) 2502 { 2503 2504 RB_INIT(&pmap->pmap_pvo); 2505 2506 pmap->pm_slb_tree_root = slb_alloc_tree(); 2507 pmap->pm_slb = slb_alloc_user_cache(); 2508 pmap->pm_slb_len = 0; 2509 2510 return (1); 2511 } 2512 #else 2513 int 2514 moea64_pinit(pmap_t pmap) 2515 { 2516 int i; 2517 uint32_t hash; 2518 2519 RB_INIT(&pmap->pmap_pvo); 2520 2521 if (pmap_bootstrapped) 2522 pmap->pmap_phys = (pmap_t)moea64_kextract((vm_offset_t)pmap); 2523 else 2524 pmap->pmap_phys = pmap; 2525 2526 /* 2527 * Allocate some segment registers for this pmap. 2528 */ 2529 hash = moea64_get_unique_vsid(); 2530 2531 for (i = 0; i < 16; i++) 2532 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2533 2534 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2535 2536 return (1); 2537 } 2538 #endif 2539 2540 /* 2541 * Initialize the pmap associated with process 0. 2542 */ 2543 void 2544 moea64_pinit0(pmap_t pm) 2545 { 2546 2547 PMAP_LOCK_INIT(pm); 2548 moea64_pinit(pm); 2549 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2550 } 2551 2552 /* 2553 * Set the physical protection on the specified range of this map as requested. 2554 */ 2555 static void 2556 moea64_pvo_protect( pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2557 { 2558 struct vm_page *pg; 2559 vm_prot_t oldprot; 2560 int32_t refchg; 2561 2562 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2563 2564 /* 2565 * Change the protection of the page. 2566 */ 2567 oldprot = pvo->pvo_pte.prot; 2568 pvo->pvo_pte.prot = prot; 2569 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2570 2571 /* 2572 * If the PVO is in the page table, update mapping 2573 */ 2574 refchg = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2575 if (refchg < 0) 2576 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2577 2578 if (pm != kernel_pmap && pg != NULL && 2579 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2580 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2581 if ((pg->oflags & VPO_UNMANAGED) == 0) 2582 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2583 moea64_syncicache(pm, PVO_VADDR(pvo), 2584 PVO_PADDR(pvo), PAGE_SIZE); 2585 } 2586 2587 /* 2588 * Update vm about the REF/CHG bits if the page is managed and we have 2589 * removed write access. 2590 */ 2591 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2592 (oldprot & VM_PROT_WRITE)) { 2593 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2594 if (refchg & LPTE_CHG) 2595 vm_page_dirty(pg); 2596 if (refchg & LPTE_REF) 2597 vm_page_aflag_set(pg, PGA_REFERENCED); 2598 } 2599 } 2600 2601 void 2602 moea64_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2603 vm_prot_t prot) 2604 { 2605 struct pvo_entry *pvo, key; 2606 2607 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2608 sva, eva, prot); 2609 2610 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2611 ("moea64_protect: non current pmap")); 2612 2613 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2614 moea64_remove(pm, sva, eva); 2615 return; 2616 } 2617 2618 PMAP_LOCK(pm); 2619 key.pvo_vaddr = sva; 2620 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2621 pvo != NULL && PVO_VADDR(pvo) < eva; 2622 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 2623 if (PVO_IS_SP(pvo)) { 2624 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 2625 pvo = moea64_sp_protect(pvo, prot); 2626 continue; 2627 } else { 2628 CTR1(KTR_PMAP, "%s: demote before protect", 2629 __func__); 2630 moea64_sp_demote(pvo); 2631 } 2632 } 2633 moea64_pvo_protect(pm, pvo, prot); 2634 } 2635 PMAP_UNLOCK(pm); 2636 } 2637 2638 /* 2639 * Map a list of wired pages into kernel virtual address space. This is 2640 * intended for temporary mappings which do not need page modification or 2641 * references recorded. Existing mappings in the region are overwritten. 2642 */ 2643 void 2644 moea64_qenter(vm_offset_t va, vm_page_t *m, int count) 2645 { 2646 while (count-- > 0) { 2647 moea64_kenter(va, VM_PAGE_TO_PHYS(*m)); 2648 va += PAGE_SIZE; 2649 m++; 2650 } 2651 } 2652 2653 /* 2654 * Remove page mappings from kernel virtual address space. Intended for 2655 * temporary mappings entered by moea64_qenter. 2656 */ 2657 void 2658 moea64_qremove(vm_offset_t va, int count) 2659 { 2660 while (count-- > 0) { 2661 moea64_kremove(va); 2662 va += PAGE_SIZE; 2663 } 2664 } 2665 2666 void 2667 moea64_release_vsid(uint64_t vsid) 2668 { 2669 int idx, mask; 2670 2671 mtx_lock(&moea64_slb_mutex); 2672 idx = vsid & (NVSIDS-1); 2673 mask = 1 << (idx % VSID_NBPW); 2674 idx /= VSID_NBPW; 2675 KASSERT(moea64_vsid_bitmap[idx] & mask, 2676 ("Freeing unallocated VSID %#jx", vsid)); 2677 moea64_vsid_bitmap[idx] &= ~mask; 2678 mtx_unlock(&moea64_slb_mutex); 2679 } 2680 2681 void 2682 moea64_release(pmap_t pmap) 2683 { 2684 2685 /* 2686 * Free segment registers' VSIDs 2687 */ 2688 #ifdef __powerpc64__ 2689 slb_free_tree(pmap); 2690 slb_free_user_cache(pmap->pm_slb); 2691 #else 2692 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2693 2694 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2695 #endif 2696 } 2697 2698 /* 2699 * Remove all pages mapped by the specified pmap 2700 */ 2701 void 2702 moea64_remove_pages(pmap_t pm) 2703 { 2704 struct pvo_entry *pvo, *tpvo; 2705 struct pvo_dlist tofree; 2706 2707 SLIST_INIT(&tofree); 2708 2709 PMAP_LOCK(pm); 2710 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2711 if (pvo->pvo_vaddr & PVO_WIRED) 2712 continue; 2713 2714 /* 2715 * For locking reasons, remove this from the page table and 2716 * pmap, but save delinking from the vm_page for a second 2717 * pass 2718 */ 2719 moea64_pvo_remove_from_pmap(pvo); 2720 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2721 } 2722 PMAP_UNLOCK(pm); 2723 2724 while (!SLIST_EMPTY(&tofree)) { 2725 pvo = SLIST_FIRST(&tofree); 2726 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2727 moea64_pvo_remove_from_page(pvo); 2728 free_pvo_entry(pvo); 2729 } 2730 } 2731 2732 static void 2733 moea64_remove_locked(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2734 struct pvo_dlist *tofree) 2735 { 2736 struct pvo_entry *pvo, *tpvo, key; 2737 2738 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2739 2740 key.pvo_vaddr = sva; 2741 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2742 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2743 if (PVO_IS_SP(pvo)) { 2744 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 2745 tpvo = moea64_sp_remove(pvo, tofree); 2746 continue; 2747 } else { 2748 CTR1(KTR_PMAP, "%s: demote before remove", 2749 __func__); 2750 moea64_sp_demote(pvo); 2751 } 2752 } 2753 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2754 2755 /* 2756 * For locking reasons, remove this from the page table and 2757 * pmap, but save delinking from the vm_page for a second 2758 * pass 2759 */ 2760 moea64_pvo_remove_from_pmap(pvo); 2761 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink); 2762 } 2763 } 2764 2765 /* 2766 * Remove the given range of addresses from the specified map. 2767 */ 2768 void 2769 moea64_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2770 { 2771 struct pvo_entry *pvo; 2772 struct pvo_dlist tofree; 2773 2774 /* 2775 * Perform an unsynchronized read. This is, however, safe. 2776 */ 2777 if (pm->pm_stats.resident_count == 0) 2778 return; 2779 2780 SLIST_INIT(&tofree); 2781 PMAP_LOCK(pm); 2782 moea64_remove_locked(pm, sva, eva, &tofree); 2783 PMAP_UNLOCK(pm); 2784 2785 while (!SLIST_EMPTY(&tofree)) { 2786 pvo = SLIST_FIRST(&tofree); 2787 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2788 moea64_pvo_remove_from_page(pvo); 2789 free_pvo_entry(pvo); 2790 } 2791 } 2792 2793 /* 2794 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2795 * will reflect changes in pte's back to the vm_page. 2796 */ 2797 void 2798 moea64_remove_all(vm_page_t m) 2799 { 2800 struct pvo_entry *pvo, *next_pvo; 2801 struct pvo_head freequeue; 2802 int wasdead; 2803 pmap_t pmap; 2804 2805 LIST_INIT(&freequeue); 2806 2807 PV_PAGE_LOCK(m); 2808 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2809 pmap = pvo->pvo_pmap; 2810 PMAP_LOCK(pmap); 2811 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2812 if (!wasdead) { 2813 if (PVO_IS_SP(pvo)) { 2814 CTR1(KTR_PMAP, "%s: demote before remove_all", 2815 __func__); 2816 moea64_sp_demote(pvo); 2817 } 2818 moea64_pvo_remove_from_pmap(pvo); 2819 } 2820 moea64_pvo_remove_from_page_locked(pvo, m); 2821 if (!wasdead) 2822 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2823 PMAP_UNLOCK(pmap); 2824 2825 } 2826 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2827 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2828 PV_PAGE_UNLOCK(m); 2829 2830 /* Clean up UMA allocations */ 2831 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2832 free_pvo_entry(pvo); 2833 } 2834 2835 /* 2836 * Allocate a physical page of memory directly from the phys_avail map. 2837 * Can only be called from moea64_bootstrap before avail start and end are 2838 * calculated. 2839 */ 2840 vm_offset_t 2841 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2842 { 2843 vm_offset_t s, e; 2844 int i, j; 2845 2846 size = round_page(size); 2847 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2848 if (align != 0) 2849 s = roundup2(phys_avail[i], align); 2850 else 2851 s = phys_avail[i]; 2852 e = s + size; 2853 2854 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2855 continue; 2856 2857 if (s + size > platform_real_maxaddr()) 2858 continue; 2859 2860 if (s == phys_avail[i]) { 2861 phys_avail[i] += size; 2862 } else if (e == phys_avail[i + 1]) { 2863 phys_avail[i + 1] -= size; 2864 } else { 2865 for (j = phys_avail_count * 2; j > i; j -= 2) { 2866 phys_avail[j] = phys_avail[j - 2]; 2867 phys_avail[j + 1] = phys_avail[j - 1]; 2868 } 2869 2870 phys_avail[i + 3] = phys_avail[i + 1]; 2871 phys_avail[i + 1] = s; 2872 phys_avail[i + 2] = e; 2873 phys_avail_count++; 2874 } 2875 2876 return (s); 2877 } 2878 panic("moea64_bootstrap_alloc: could not allocate memory"); 2879 } 2880 2881 static int 2882 moea64_pvo_enter(struct pvo_entry *pvo, struct pvo_head *pvo_head, 2883 struct pvo_entry **oldpvop) 2884 { 2885 struct pvo_entry *old_pvo; 2886 int err; 2887 2888 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2889 2890 STAT_MOEA64(moea64_pvo_enter_calls++); 2891 2892 /* 2893 * Add to pmap list 2894 */ 2895 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2896 2897 if (old_pvo != NULL) { 2898 if (oldpvop != NULL) 2899 *oldpvop = old_pvo; 2900 return (EEXIST); 2901 } 2902 2903 if (pvo_head != NULL) { 2904 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2905 } 2906 2907 if (pvo->pvo_vaddr & PVO_WIRED) 2908 pvo->pvo_pmap->pm_stats.wired_count++; 2909 pvo->pvo_pmap->pm_stats.resident_count++; 2910 2911 /* 2912 * Insert it into the hardware page table 2913 */ 2914 err = moea64_pte_insert(pvo); 2915 if (err != 0) { 2916 panic("moea64_pvo_enter: overflow"); 2917 } 2918 2919 STAT_MOEA64(moea64_pvo_entries++); 2920 2921 if (pvo->pvo_pmap == kernel_pmap) 2922 isync(); 2923 2924 #ifdef __powerpc64__ 2925 /* 2926 * Make sure all our bootstrap mappings are in the SLB as soon 2927 * as virtual memory is switched on. 2928 */ 2929 if (!pmap_bootstrapped) 2930 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2931 pvo->pvo_vaddr & PVO_LARGE); 2932 #endif 2933 2934 return (0); 2935 } 2936 2937 static void 2938 moea64_pvo_remove_from_pmap(struct pvo_entry *pvo) 2939 { 2940 struct vm_page *pg; 2941 int32_t refchg; 2942 2943 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2944 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2945 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2946 2947 /* 2948 * If there is an active pte entry, we need to deactivate it 2949 */ 2950 refchg = moea64_pte_unset(pvo); 2951 if (refchg < 0) { 2952 /* 2953 * If it was evicted from the page table, be pessimistic and 2954 * dirty the page. 2955 */ 2956 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2957 refchg = LPTE_CHG; 2958 else 2959 refchg = 0; 2960 } 2961 2962 /* 2963 * Update our statistics. 2964 */ 2965 pvo->pvo_pmap->pm_stats.resident_count--; 2966 if (pvo->pvo_vaddr & PVO_WIRED) 2967 pvo->pvo_pmap->pm_stats.wired_count--; 2968 2969 /* 2970 * Remove this PVO from the pmap list. 2971 */ 2972 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2973 2974 /* 2975 * Mark this for the next sweep 2976 */ 2977 pvo->pvo_vaddr |= PVO_DEAD; 2978 2979 /* Send RC bits to VM */ 2980 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2981 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2982 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2983 if (pg != NULL) { 2984 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2985 if (refchg & LPTE_CHG) 2986 vm_page_dirty(pg); 2987 if (refchg & LPTE_REF) 2988 vm_page_aflag_set(pg, PGA_REFERENCED); 2989 } 2990 } 2991 } 2992 2993 static inline void 2994 moea64_pvo_remove_from_page_locked(struct pvo_entry *pvo, 2995 vm_page_t m) 2996 { 2997 2998 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2999 3000 /* Use NULL pmaps as a sentinel for races in page deletion */ 3001 if (pvo->pvo_pmap == NULL) 3002 return; 3003 pvo->pvo_pmap = NULL; 3004 3005 /* 3006 * Update vm about page writeability/executability if managed 3007 */ 3008 PV_LOCKASSERT(PVO_PADDR(pvo)); 3009 if (pvo->pvo_vaddr & PVO_MANAGED) { 3010 if (m != NULL) { 3011 LIST_REMOVE(pvo, pvo_vlink); 3012 if (LIST_EMPTY(vm_page_to_pvoh(m))) 3013 vm_page_aflag_clear(m, 3014 PGA_WRITEABLE | PGA_EXECUTABLE); 3015 } 3016 } 3017 3018 STAT_MOEA64(moea64_pvo_entries--); 3019 STAT_MOEA64(moea64_pvo_remove_calls++); 3020 } 3021 3022 static void 3023 moea64_pvo_remove_from_page(struct pvo_entry *pvo) 3024 { 3025 vm_page_t pg = NULL; 3026 3027 if (pvo->pvo_vaddr & PVO_MANAGED) 3028 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 3029 3030 PV_LOCK(PVO_PADDR(pvo)); 3031 moea64_pvo_remove_from_page_locked(pvo, pg); 3032 PV_UNLOCK(PVO_PADDR(pvo)); 3033 } 3034 3035 static struct pvo_entry * 3036 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 3037 { 3038 struct pvo_entry key; 3039 3040 PMAP_LOCK_ASSERT(pm, MA_OWNED); 3041 3042 key.pvo_vaddr = va & ~ADDR_POFF; 3043 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 3044 } 3045 3046 static boolean_t 3047 moea64_query_bit(vm_page_t m, uint64_t ptebit) 3048 { 3049 struct pvo_entry *pvo; 3050 int64_t ret; 3051 boolean_t rv; 3052 vm_page_t sp; 3053 3054 /* 3055 * See if this bit is stored in the page already. 3056 * 3057 * For superpages, the bit is stored in the first vm page. 3058 */ 3059 if ((m->md.mdpg_attrs & ptebit) != 0 || 3060 ((sp = PHYS_TO_VM_PAGE(VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK)) != NULL && 3061 (sp->md.mdpg_attrs & (ptebit | MDPG_ATTR_SP)) == 3062 (ptebit | MDPG_ATTR_SP))) 3063 return (TRUE); 3064 3065 /* 3066 * Examine each PTE. Sync so that any pending REF/CHG bits are 3067 * flushed to the PTEs. 3068 */ 3069 rv = FALSE; 3070 powerpc_sync(); 3071 PV_PAGE_LOCK(m); 3072 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 3073 if (PVO_IS_SP(pvo)) { 3074 ret = moea64_sp_query(pvo, ptebit); 3075 /* 3076 * If SP was not demoted, check its REF/CHG bits here. 3077 */ 3078 if (ret != -1) { 3079 if ((ret & ptebit) != 0) { 3080 rv = TRUE; 3081 break; 3082 } 3083 continue; 3084 } 3085 /* else, fallthrough */ 3086 } 3087 3088 ret = 0; 3089 3090 /* 3091 * See if this pvo has a valid PTE. if so, fetch the 3092 * REF/CHG bits from the valid PTE. If the appropriate 3093 * ptebit is set, return success. 3094 */ 3095 PMAP_LOCK(pvo->pvo_pmap); 3096 if (!(pvo->pvo_vaddr & PVO_DEAD)) 3097 ret = moea64_pte_synch(pvo); 3098 PMAP_UNLOCK(pvo->pvo_pmap); 3099 3100 if (ret > 0) { 3101 atomic_set_32(&m->md.mdpg_attrs, 3102 ret & (LPTE_CHG | LPTE_REF)); 3103 if (ret & ptebit) { 3104 rv = TRUE; 3105 break; 3106 } 3107 } 3108 } 3109 PV_PAGE_UNLOCK(m); 3110 3111 return (rv); 3112 } 3113 3114 static u_int 3115 moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 3116 { 3117 u_int count; 3118 struct pvo_entry *pvo; 3119 int64_t ret; 3120 3121 /* 3122 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 3123 * we can reset the right ones). 3124 */ 3125 powerpc_sync(); 3126 3127 /* 3128 * For each pvo entry, clear the pte's ptebit. 3129 */ 3130 count = 0; 3131 PV_PAGE_LOCK(m); 3132 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 3133 if (PVO_IS_SP(pvo)) { 3134 if ((ret = moea64_sp_clear(pvo, m, ptebit)) != -1) { 3135 count += ret; 3136 continue; 3137 } 3138 } 3139 ret = 0; 3140 3141 PMAP_LOCK(pvo->pvo_pmap); 3142 if (!(pvo->pvo_vaddr & PVO_DEAD)) 3143 ret = moea64_pte_clear(pvo, ptebit); 3144 PMAP_UNLOCK(pvo->pvo_pmap); 3145 3146 if (ret > 0 && (ret & ptebit)) 3147 count++; 3148 } 3149 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 3150 PV_PAGE_UNLOCK(m); 3151 3152 return (count); 3153 } 3154 3155 boolean_t 3156 moea64_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 3157 { 3158 struct pvo_entry *pvo, key; 3159 vm_offset_t ppa; 3160 int error = 0; 3161 3162 if (hw_direct_map && mem_valid(pa, size) == 0) 3163 return (0); 3164 3165 PMAP_LOCK(kernel_pmap); 3166 ppa = pa & ~ADDR_POFF; 3167 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 3168 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 3169 ppa < pa + size; ppa += PAGE_SIZE, 3170 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 3171 if (pvo == NULL || PVO_PADDR(pvo) != ppa) { 3172 error = EFAULT; 3173 break; 3174 } 3175 } 3176 PMAP_UNLOCK(kernel_pmap); 3177 3178 return (error); 3179 } 3180 3181 /* 3182 * Map a set of physical memory pages into the kernel virtual 3183 * address space. Return a pointer to where it is mapped. This 3184 * routine is intended to be used for mapping device memory, 3185 * NOT real memory. 3186 */ 3187 void * 3188 moea64_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 3189 { 3190 vm_offset_t va, tmpva, ppa, offset; 3191 3192 ppa = trunc_page(pa); 3193 offset = pa & PAGE_MASK; 3194 size = roundup2(offset + size, PAGE_SIZE); 3195 3196 va = kva_alloc(size); 3197 3198 if (!va) 3199 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 3200 3201 for (tmpva = va; size > 0;) { 3202 moea64_kenter_attr(tmpva, ppa, ma); 3203 size -= PAGE_SIZE; 3204 tmpva += PAGE_SIZE; 3205 ppa += PAGE_SIZE; 3206 } 3207 3208 return ((void *)(va + offset)); 3209 } 3210 3211 void * 3212 moea64_mapdev(vm_paddr_t pa, vm_size_t size) 3213 { 3214 3215 return moea64_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT); 3216 } 3217 3218 void 3219 moea64_unmapdev(vm_offset_t va, vm_size_t size) 3220 { 3221 vm_offset_t base, offset; 3222 3223 base = trunc_page(va); 3224 offset = va & PAGE_MASK; 3225 size = roundup2(offset + size, PAGE_SIZE); 3226 3227 moea64_qremove(base, atop(size)); 3228 kva_free(base, size); 3229 } 3230 3231 void 3232 moea64_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3233 { 3234 struct pvo_entry *pvo; 3235 vm_offset_t lim; 3236 vm_paddr_t pa; 3237 vm_size_t len; 3238 3239 if (__predict_false(pm == NULL)) 3240 pm = &curthread->td_proc->p_vmspace->vm_pmap; 3241 3242 PMAP_LOCK(pm); 3243 while (sz > 0) { 3244 lim = round_page(va+1); 3245 len = MIN(lim - va, sz); 3246 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 3247 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 3248 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 3249 moea64_syncicache(pm, va, pa, len); 3250 } 3251 va += len; 3252 sz -= len; 3253 } 3254 PMAP_UNLOCK(pm); 3255 } 3256 3257 void 3258 moea64_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 3259 { 3260 3261 *va = (void *)(uintptr_t)pa; 3262 } 3263 3264 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 3265 3266 void 3267 moea64_scan_init() 3268 { 3269 struct pvo_entry *pvo; 3270 vm_offset_t va; 3271 int i; 3272 3273 if (!do_minidump) { 3274 /* Initialize phys. segments for dumpsys(). */ 3275 memset(&dump_map, 0, sizeof(dump_map)); 3276 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 3277 for (i = 0; i < pregions_sz; i++) { 3278 dump_map[i].pa_start = pregions[i].mr_start; 3279 dump_map[i].pa_size = pregions[i].mr_size; 3280 } 3281 return; 3282 } 3283 3284 /* Virtual segments for minidumps: */ 3285 memset(&dump_map, 0, sizeof(dump_map)); 3286 3287 /* 1st: kernel .data and .bss. */ 3288 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 3289 dump_map[0].pa_size = round_page((uintptr_t)_end) - 3290 dump_map[0].pa_start; 3291 3292 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 3293 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 3294 dump_map[1].pa_size = round_page(msgbufp->msg_size); 3295 3296 /* 3rd: kernel VM. */ 3297 va = dump_map[1].pa_start + dump_map[1].pa_size; 3298 /* Find start of next chunk (from va). */ 3299 while (va < virtual_end) { 3300 /* Don't dump the buffer cache. */ 3301 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 3302 va = kmi.buffer_eva; 3303 continue; 3304 } 3305 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 3306 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 3307 break; 3308 va += PAGE_SIZE; 3309 } 3310 if (va < virtual_end) { 3311 dump_map[2].pa_start = va; 3312 va += PAGE_SIZE; 3313 /* Find last page in chunk. */ 3314 while (va < virtual_end) { 3315 /* Don't run into the buffer cache. */ 3316 if (va == kmi.buffer_sva) 3317 break; 3318 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 3319 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 3320 break; 3321 va += PAGE_SIZE; 3322 } 3323 dump_map[2].pa_size = va - dump_map[2].pa_start; 3324 } 3325 } 3326 3327 #ifdef __powerpc64__ 3328 3329 static size_t 3330 moea64_scan_pmap() 3331 { 3332 struct pvo_entry *pvo; 3333 vm_paddr_t pa, pa_end; 3334 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 3335 uint64_t lpsize; 3336 3337 lpsize = moea64_large_page_size; 3338 kstart = trunc_page((vm_offset_t)_etext); 3339 kend = round_page((vm_offset_t)_end); 3340 kstart_lp = kstart & ~moea64_large_page_mask; 3341 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 3342 3343 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 3344 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 3345 kstart, kend, kstart_lp, kend_lp); 3346 3347 PMAP_LOCK(kernel_pmap); 3348 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 3349 va = pvo->pvo_vaddr; 3350 3351 if (va & PVO_DEAD) 3352 continue; 3353 3354 /* Skip DMAP (except kernel area) */ 3355 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 3356 if (va & PVO_LARGE) { 3357 pgva = va & ~moea64_large_page_mask; 3358 if (pgva < kstart_lp || pgva >= kend_lp) 3359 continue; 3360 } else { 3361 pgva = trunc_page(va); 3362 if (pgva < kstart || pgva >= kend) 3363 continue; 3364 } 3365 } 3366 3367 pa = PVO_PADDR(pvo); 3368 3369 if (va & PVO_LARGE) { 3370 pa_end = pa + lpsize; 3371 for (; pa < pa_end; pa += PAGE_SIZE) { 3372 if (is_dumpable(pa)) 3373 dump_add_page(pa); 3374 } 3375 } else { 3376 if (is_dumpable(pa)) 3377 dump_add_page(pa); 3378 } 3379 } 3380 PMAP_UNLOCK(kernel_pmap); 3381 3382 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3383 } 3384 3385 static struct dump_context dump_ctx; 3386 3387 static void * 3388 moea64_dump_pmap_init(unsigned blkpgs) 3389 { 3390 dump_ctx.ptex = 0; 3391 dump_ctx.ptex_end = moea64_pteg_count * 8; 3392 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3393 return (&dump_ctx); 3394 } 3395 3396 #else 3397 3398 static size_t 3399 moea64_scan_pmap() 3400 { 3401 return (0); 3402 } 3403 3404 static void * 3405 moea64_dump_pmap_init(unsigned blkpgs) 3406 { 3407 return (NULL); 3408 } 3409 3410 #endif 3411 3412 #ifdef __powerpc64__ 3413 static void 3414 moea64_map_range(vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3415 { 3416 3417 for (; npages > 0; --npages) { 3418 if (moea64_large_page_size != 0 && 3419 (pa & moea64_large_page_mask) == 0 && 3420 (va & moea64_large_page_mask) == 0 && 3421 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3422 PMAP_LOCK(kernel_pmap); 3423 moea64_kenter_large(va, pa, 0, 0); 3424 PMAP_UNLOCK(kernel_pmap); 3425 pa += moea64_large_page_size; 3426 va += moea64_large_page_size; 3427 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3428 } else { 3429 moea64_kenter(va, pa); 3430 pa += PAGE_SIZE; 3431 va += PAGE_SIZE; 3432 } 3433 } 3434 } 3435 3436 static void 3437 moea64_page_array_startup(long pages) 3438 { 3439 long dom_pages[MAXMEMDOM]; 3440 vm_paddr_t pa; 3441 vm_offset_t va, vm_page_base; 3442 vm_size_t needed, size; 3443 long page; 3444 int domain; 3445 int i; 3446 3447 vm_page_base = 0xd000000000000000ULL; 3448 3449 /* Short-circuit single-domain systems. */ 3450 if (vm_ndomains == 1) { 3451 size = round_page(pages * sizeof(struct vm_page)); 3452 pa = vm_phys_early_alloc(0, size); 3453 vm_page_base = moea64_map(&vm_page_base, 3454 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3455 vm_page_array_size = pages; 3456 vm_page_array = (vm_page_t)vm_page_base; 3457 return; 3458 } 3459 3460 page = 0; 3461 for (i = 0; i < MAXMEMDOM; i++) 3462 dom_pages[i] = 0; 3463 3464 /* Now get the number of pages required per domain. */ 3465 for (i = 0; i < vm_phys_nsegs; i++) { 3466 domain = vm_phys_segs[i].domain; 3467 KASSERT(domain < MAXMEMDOM, 3468 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3469 /* Get size of vm_page_array needed for this segment. */ 3470 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3471 dom_pages[domain] += size; 3472 } 3473 3474 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3475 domain = vm_phys_domain(phys_avail[i]); 3476 KASSERT(domain < MAXMEMDOM, 3477 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3478 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3479 dom_pages[domain] += size; 3480 } 3481 3482 /* 3483 * Map in chunks that can get us all 16MB pages. There will be some 3484 * overlap between domains, but that's acceptable for now. 3485 */ 3486 vm_page_array_size = 0; 3487 va = vm_page_base; 3488 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3489 if (dom_pages[i] == 0) 3490 continue; 3491 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3492 size = round_page(size * sizeof(struct vm_page)); 3493 needed = size; 3494 size = roundup2(size, moea64_large_page_size); 3495 pa = vm_phys_early_alloc(i, size); 3496 vm_page_array_size += size / sizeof(struct vm_page); 3497 moea64_map_range(va, pa, size >> PAGE_SHIFT); 3498 /* Scoot up domain 0, to reduce the domain page overlap. */ 3499 if (i == 0) 3500 vm_page_base += size - needed; 3501 va += size; 3502 } 3503 vm_page_array = (vm_page_t)vm_page_base; 3504 vm_page_array_size = pages; 3505 } 3506 #endif 3507 3508 static int64_t 3509 moea64_null_method(void) 3510 { 3511 return (0); 3512 } 3513 3514 static int64_t moea64_pte_replace_default(struct pvo_entry *pvo, int flags) 3515 { 3516 int64_t refchg; 3517 3518 refchg = moea64_pte_unset(pvo); 3519 moea64_pte_insert(pvo); 3520 3521 return (refchg); 3522 } 3523 3524 struct moea64_funcs *moea64_ops; 3525 3526 #define DEFINE_OEA64_IFUNC(ret, func, args, def) \ 3527 DEFINE_IFUNC(, ret, moea64_##func, args) { \ 3528 moea64_##func##_t f; \ 3529 if (moea64_ops == NULL) \ 3530 return ((moea64_##func##_t)def); \ 3531 f = moea64_ops->func; \ 3532 return (f != NULL ? f : (moea64_##func##_t)def);\ 3533 } 3534 3535 DEFINE_OEA64_IFUNC(int64_t, pte_replace, (struct pvo_entry *, int), 3536 moea64_pte_replace_default) 3537 DEFINE_OEA64_IFUNC(int64_t, pte_insert, (struct pvo_entry *), moea64_null_method) 3538 DEFINE_OEA64_IFUNC(int64_t, pte_unset, (struct pvo_entry *), moea64_null_method) 3539 DEFINE_OEA64_IFUNC(int64_t, pte_clear, (struct pvo_entry *, uint64_t), 3540 moea64_null_method) 3541 DEFINE_OEA64_IFUNC(int64_t, pte_synch, (struct pvo_entry *), moea64_null_method) 3542 DEFINE_OEA64_IFUNC(int64_t, pte_insert_sp, (struct pvo_entry *), moea64_null_method) 3543 DEFINE_OEA64_IFUNC(int64_t, pte_unset_sp, (struct pvo_entry *), moea64_null_method) 3544 DEFINE_OEA64_IFUNC(int64_t, pte_replace_sp, (struct pvo_entry *), moea64_null_method) 3545 3546 /* Superpage functions */ 3547 3548 /* MMU interface */ 3549 3550 static bool 3551 moea64_ps_enabled(pmap_t pmap) 3552 { 3553 return (superpages_enabled); 3554 } 3555 3556 static void 3557 moea64_align_superpage(vm_object_t object, vm_ooffset_t offset, 3558 vm_offset_t *addr, vm_size_t size) 3559 { 3560 vm_offset_t sp_offset; 3561 3562 if (size < HPT_SP_SIZE) 3563 return; 3564 3565 CTR4(KTR_PMAP, "%s: offs=%#jx, addr=%p, size=%#jx", 3566 __func__, (uintmax_t)offset, addr, (uintmax_t)size); 3567 3568 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3569 offset += ptoa(object->pg_color); 3570 sp_offset = offset & HPT_SP_MASK; 3571 if (size - ((HPT_SP_SIZE - sp_offset) & HPT_SP_MASK) < HPT_SP_SIZE || 3572 (*addr & HPT_SP_MASK) == sp_offset) 3573 return; 3574 if ((*addr & HPT_SP_MASK) < sp_offset) 3575 *addr = (*addr & ~HPT_SP_MASK) + sp_offset; 3576 else 3577 *addr = ((*addr + HPT_SP_MASK) & ~HPT_SP_MASK) + sp_offset; 3578 } 3579 3580 /* Helpers */ 3581 3582 static __inline void 3583 moea64_pvo_cleanup(struct pvo_dlist *tofree) 3584 { 3585 struct pvo_entry *pvo; 3586 3587 /* clean up */ 3588 while (!SLIST_EMPTY(tofree)) { 3589 pvo = SLIST_FIRST(tofree); 3590 SLIST_REMOVE_HEAD(tofree, pvo_dlink); 3591 if (pvo->pvo_vaddr & PVO_DEAD) 3592 moea64_pvo_remove_from_page(pvo); 3593 free_pvo_entry(pvo); 3594 } 3595 } 3596 3597 static __inline uint16_t 3598 pvo_to_vmpage_flags(struct pvo_entry *pvo) 3599 { 3600 uint16_t flags; 3601 3602 flags = 0; 3603 if ((pvo->pvo_pte.prot & VM_PROT_WRITE) != 0) 3604 flags |= PGA_WRITEABLE; 3605 if ((pvo->pvo_pte.prot & VM_PROT_EXECUTE) != 0) 3606 flags |= PGA_EXECUTABLE; 3607 3608 return (flags); 3609 } 3610 3611 /* 3612 * Check if the given pvo and its superpage are in sva-eva range. 3613 */ 3614 static __inline bool 3615 moea64_sp_pvo_in_range(struct pvo_entry *pvo, vm_offset_t sva, vm_offset_t eva) 3616 { 3617 vm_offset_t spva; 3618 3619 spva = PVO_VADDR(pvo) & ~HPT_SP_MASK; 3620 if (spva >= sva && spva + HPT_SP_SIZE <= eva) { 3621 /* 3622 * Because this function is intended to be called from loops 3623 * that iterate over ordered pvo entries, if the condition 3624 * above is true then the pvo must be the first of its 3625 * superpage. 3626 */ 3627 KASSERT(PVO_VADDR(pvo) == spva, 3628 ("%s: unexpected unaligned superpage pvo", __func__)); 3629 return (true); 3630 } 3631 return (false); 3632 } 3633 3634 /* 3635 * Update vm about the REF/CHG bits if the superpage is managed and 3636 * has (or had) write access. 3637 */ 3638 static void 3639 moea64_sp_refchg_process(struct pvo_entry *sp, vm_page_t m, 3640 int64_t sp_refchg, vm_prot_t prot) 3641 { 3642 vm_page_t m_end; 3643 int64_t refchg; 3644 3645 if ((sp->pvo_vaddr & PVO_MANAGED) != 0 && (prot & VM_PROT_WRITE) != 0) { 3646 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) { 3647 refchg = sp_refchg | 3648 atomic_readandclear_32(&m->md.mdpg_attrs); 3649 if (refchg & LPTE_CHG) 3650 vm_page_dirty(m); 3651 if (refchg & LPTE_REF) 3652 vm_page_aflag_set(m, PGA_REFERENCED); 3653 } 3654 } 3655 } 3656 3657 /* Superpage ops */ 3658 3659 static int 3660 moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 3661 vm_prot_t prot, u_int flags, int8_t psind) 3662 { 3663 struct pvo_entry *pvo, **pvos; 3664 struct pvo_head *pvo_head; 3665 vm_offset_t sva; 3666 vm_page_t sm; 3667 vm_paddr_t pa, spa; 3668 bool sync; 3669 struct pvo_dlist tofree; 3670 int error, i; 3671 uint16_t aflags; 3672 3673 KASSERT((va & HPT_SP_MASK) == 0, ("%s: va %#jx unaligned", 3674 __func__, (uintmax_t)va)); 3675 KASSERT(psind == 1, ("%s: invalid psind: %d", __func__, psind)); 3676 KASSERT(m->psind == 1, ("%s: invalid m->psind: %d", 3677 __func__, m->psind)); 3678 KASSERT(pmap != kernel_pmap, 3679 ("%s: function called with kernel pmap", __func__)); 3680 3681 CTR5(KTR_PMAP, "%s: va=%#jx, pa=%#jx, prot=%#x, flags=%#x, psind=1", 3682 __func__, (uintmax_t)va, (uintmax_t)VM_PAGE_TO_PHYS(m), 3683 prot, flags); 3684 3685 SLIST_INIT(&tofree); 3686 3687 sva = va; 3688 sm = m; 3689 spa = pa = VM_PAGE_TO_PHYS(sm); 3690 3691 /* Try to allocate all PVOs first, to make failure handling easier. */ 3692 pvos = malloc(HPT_SP_PAGES * sizeof(struct pvo_entry *), M_TEMP, 3693 M_NOWAIT); 3694 if (pvos == NULL) { 3695 CTR1(KTR_PMAP, "%s: failed to alloc pvo array", __func__); 3696 return (KERN_RESOURCE_SHORTAGE); 3697 } 3698 3699 for (i = 0; i < HPT_SP_PAGES; i++) { 3700 pvos[i] = alloc_pvo_entry(0); 3701 if (pvos[i] == NULL) { 3702 CTR1(KTR_PMAP, "%s: failed to alloc pvo", __func__); 3703 for (i = i - 1; i >= 0; i--) 3704 free_pvo_entry(pvos[i]); 3705 free(pvos, M_TEMP); 3706 return (KERN_RESOURCE_SHORTAGE); 3707 } 3708 } 3709 3710 SP_PV_LOCK_ALIGNED(spa); 3711 PMAP_LOCK(pmap); 3712 3713 /* Note: moea64_remove_locked() also clears cached REF/CHG bits. */ 3714 moea64_remove_locked(pmap, va, va + HPT_SP_SIZE, &tofree); 3715 3716 /* Enter pages */ 3717 for (i = 0; i < HPT_SP_PAGES; 3718 i++, va += PAGE_SIZE, pa += PAGE_SIZE, m++) { 3719 pvo = pvos[i]; 3720 3721 pvo->pvo_pte.prot = prot; 3722 pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M | 3723 moea64_calc_wimg(pa, pmap_page_get_memattr(m)); 3724 3725 if ((flags & PMAP_ENTER_WIRED) != 0) 3726 pvo->pvo_vaddr |= PVO_WIRED; 3727 pvo->pvo_vaddr |= PVO_LARGE; 3728 3729 if ((m->oflags & VPO_UNMANAGED) != 0) 3730 pvo_head = NULL; 3731 else { 3732 pvo_head = &m->md.mdpg_pvoh; 3733 pvo->pvo_vaddr |= PVO_MANAGED; 3734 } 3735 3736 init_pvo_entry(pvo, pmap, va); 3737 3738 error = moea64_pvo_enter(pvo, pvo_head, NULL); 3739 /* 3740 * All superpage PVOs were previously removed, so no errors 3741 * should occur while inserting the new ones. 3742 */ 3743 KASSERT(error == 0, ("%s: unexpected error " 3744 "when inserting superpage PVO: %d", 3745 __func__, error)); 3746 } 3747 3748 PMAP_UNLOCK(pmap); 3749 SP_PV_UNLOCK_ALIGNED(spa); 3750 3751 sync = (sm->a.flags & PGA_EXECUTABLE) == 0; 3752 /* Note: moea64_pvo_cleanup() also clears page prot. flags. */ 3753 moea64_pvo_cleanup(&tofree); 3754 pvo = pvos[0]; 3755 3756 /* Set vm page flags */ 3757 aflags = pvo_to_vmpage_flags(pvo); 3758 if (aflags != 0) 3759 for (m = sm; m < &sm[HPT_SP_PAGES]; m++) 3760 vm_page_aflag_set(m, aflags); 3761 3762 /* 3763 * Flush the page from the instruction cache if this page is 3764 * mapped executable and cacheable. 3765 */ 3766 if (sync && (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) 3767 moea64_syncicache(pmap, sva, spa, HPT_SP_SIZE); 3768 3769 atomic_add_long(&sp_mappings, 1); 3770 CTR3(KTR_PMAP, "%s: SP success for va %#jx in pmap %p", 3771 __func__, (uintmax_t)sva, pmap); 3772 3773 free(pvos, M_TEMP); 3774 return (KERN_SUCCESS); 3775 } 3776 3777 static void 3778 moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m) 3779 { 3780 struct pvo_entry *first, *pvo; 3781 vm_paddr_t pa, pa_end; 3782 vm_offset_t sva, va_end; 3783 int64_t sp_refchg; 3784 3785 /* This CTR may generate a lot of output. */ 3786 /* CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)va); */ 3787 3788 va &= ~HPT_SP_MASK; 3789 sva = va; 3790 /* Get superpage */ 3791 pa = VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK; 3792 m = PHYS_TO_VM_PAGE(pa); 3793 3794 PMAP_LOCK(pmap); 3795 3796 /* 3797 * Check if all pages meet promotion criteria. 3798 * 3799 * XXX In some cases the loop below may be executed for each or most 3800 * of the entered pages of a superpage, which can be expensive 3801 * (although it was not profiled) and need some optimization. 3802 * 3803 * Some cases where this seems to happen are: 3804 * - When a superpage is first entered read-only and later becomes 3805 * read-write. 3806 * - When some of the superpage's virtual addresses map to previously 3807 * wired/cached pages while others map to pages allocated from a 3808 * different physical address range. A common scenario where this 3809 * happens is when mmap'ing a file that is already present in FS 3810 * block cache and doesn't fill a superpage. 3811 */ 3812 first = pvo = moea64_pvo_find_va(pmap, sva); 3813 for (pa_end = pa + HPT_SP_SIZE; 3814 pa < pa_end; pa += PAGE_SIZE, va += PAGE_SIZE) { 3815 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 3816 CTR3(KTR_PMAP, 3817 "%s: NULL or dead PVO: pmap=%p, va=%#jx", 3818 __func__, pmap, (uintmax_t)va); 3819 goto error; 3820 } 3821 if (PVO_PADDR(pvo) != pa) { 3822 CTR5(KTR_PMAP, "%s: PAs don't match: " 3823 "pmap=%p, va=%#jx, pvo_pa=%#jx, exp_pa=%#jx", 3824 __func__, pmap, (uintmax_t)va, 3825 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)pa); 3826 atomic_add_long(&sp_p_fail_pa, 1); 3827 goto error; 3828 } 3829 if ((first->pvo_vaddr & PVO_FLAGS_PROMOTE) != 3830 (pvo->pvo_vaddr & PVO_FLAGS_PROMOTE)) { 3831 CTR5(KTR_PMAP, "%s: PVO flags don't match: " 3832 "pmap=%p, va=%#jx, pvo_flags=%#jx, exp_flags=%#jx", 3833 __func__, pmap, (uintmax_t)va, 3834 (uintmax_t)(pvo->pvo_vaddr & PVO_FLAGS_PROMOTE), 3835 (uintmax_t)(first->pvo_vaddr & PVO_FLAGS_PROMOTE)); 3836 atomic_add_long(&sp_p_fail_flags, 1); 3837 goto error; 3838 } 3839 if (first->pvo_pte.prot != pvo->pvo_pte.prot) { 3840 CTR5(KTR_PMAP, "%s: PVO protections don't match: " 3841 "pmap=%p, va=%#jx, pvo_prot=%#x, exp_prot=%#x", 3842 __func__, pmap, (uintmax_t)va, 3843 pvo->pvo_pte.prot, first->pvo_pte.prot); 3844 atomic_add_long(&sp_p_fail_prot, 1); 3845 goto error; 3846 } 3847 if ((first->pvo_pte.pa & LPTE_WIMG) != 3848 (pvo->pvo_pte.pa & LPTE_WIMG)) { 3849 CTR5(KTR_PMAP, "%s: WIMG bits don't match: " 3850 "pmap=%p, va=%#jx, pvo_wimg=%#jx, exp_wimg=%#jx", 3851 __func__, pmap, (uintmax_t)va, 3852 (uintmax_t)(pvo->pvo_pte.pa & LPTE_WIMG), 3853 (uintmax_t)(first->pvo_pte.pa & LPTE_WIMG)); 3854 atomic_add_long(&sp_p_fail_wimg, 1); 3855 goto error; 3856 } 3857 3858 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo); 3859 } 3860 3861 /* All OK, promote. */ 3862 3863 /* 3864 * Handle superpage REF/CHG bits. If REF or CHG is set in 3865 * any page, then it must be set in the superpage. 3866 * 3867 * Instead of querying each page, we take advantage of two facts: 3868 * 1- If a page is being promoted, it was referenced. 3869 * 2- If promoted pages are writable, they were modified. 3870 */ 3871 sp_refchg = LPTE_REF | 3872 ((first->pvo_pte.prot & VM_PROT_WRITE) != 0 ? LPTE_CHG : 0); 3873 3874 /* Promote pages */ 3875 3876 for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE; 3877 pvo != NULL && PVO_VADDR(pvo) < va_end; 3878 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 3879 pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK; 3880 pvo->pvo_pte.pa |= LPTE_LP_4K_16M; 3881 pvo->pvo_vaddr |= PVO_LARGE; 3882 } 3883 moea64_pte_replace_sp(first); 3884 3885 /* Send REF/CHG bits to VM */ 3886 moea64_sp_refchg_process(first, m, sp_refchg, first->pvo_pte.prot); 3887 3888 /* Use first page to cache REF/CHG bits */ 3889 atomic_set_32(&m->md.mdpg_attrs, sp_refchg | MDPG_ATTR_SP); 3890 3891 PMAP_UNLOCK(pmap); 3892 3893 atomic_add_long(&sp_mappings, 1); 3894 atomic_add_long(&sp_promotions, 1); 3895 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p", 3896 __func__, (uintmax_t)sva, pmap); 3897 return; 3898 3899 error: 3900 atomic_add_long(&sp_p_failures, 1); 3901 PMAP_UNLOCK(pmap); 3902 } 3903 3904 static void 3905 moea64_sp_demote_aligned(struct pvo_entry *sp) 3906 { 3907 struct pvo_entry *pvo; 3908 vm_offset_t va, va_end; 3909 vm_paddr_t pa; 3910 vm_page_t m; 3911 pmap_t pmap; 3912 int64_t refchg; 3913 3914 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 3915 3916 pmap = sp->pvo_pmap; 3917 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3918 3919 pvo = sp; 3920 3921 /* Demote pages */ 3922 3923 va = PVO_VADDR(pvo); 3924 pa = PVO_PADDR(pvo); 3925 m = PHYS_TO_VM_PAGE(pa); 3926 3927 for (pvo = sp, va_end = va + HPT_SP_SIZE; 3928 pvo != NULL && PVO_VADDR(pvo) < va_end; 3929 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo), 3930 va += PAGE_SIZE, pa += PAGE_SIZE) { 3931 KASSERT(pvo && PVO_VADDR(pvo) == va, 3932 ("%s: missing PVO for va %#jx", __func__, (uintmax_t)va)); 3933 3934 pvo->pvo_vaddr &= ~PVO_LARGE; 3935 pvo->pvo_pte.pa &= ~LPTE_RPGN; 3936 pvo->pvo_pte.pa |= pa; 3937 3938 } 3939 refchg = moea64_pte_replace_sp(sp); 3940 3941 /* 3942 * Clear SP flag 3943 * 3944 * XXX It is possible that another pmap has this page mapped as 3945 * part of a superpage, but as the SP flag is used only for 3946 * caching SP REF/CHG bits, that will be queried if not set 3947 * in cache, it should be ok to clear it here. 3948 */ 3949 atomic_clear_32(&m->md.mdpg_attrs, MDPG_ATTR_SP); 3950 3951 /* 3952 * Handle superpage REF/CHG bits. A bit set in the superpage 3953 * means all pages should consider it set. 3954 */ 3955 moea64_sp_refchg_process(sp, m, refchg, sp->pvo_pte.prot); 3956 3957 atomic_add_long(&sp_demotions, 1); 3958 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p", 3959 __func__, (uintmax_t)PVO_VADDR(sp), pmap); 3960 } 3961 3962 static void 3963 moea64_sp_demote(struct pvo_entry *pvo) 3964 { 3965 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 3966 3967 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 3968 pvo = moea64_pvo_find_va(pvo->pvo_pmap, 3969 PVO_VADDR(pvo) & ~HPT_SP_MASK); 3970 KASSERT(pvo != NULL, ("%s: missing PVO for va %#jx", 3971 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 3972 } 3973 moea64_sp_demote_aligned(pvo); 3974 } 3975 3976 static struct pvo_entry * 3977 moea64_sp_unwire(struct pvo_entry *sp) 3978 { 3979 struct pvo_entry *pvo, *prev; 3980 vm_offset_t eva; 3981 pmap_t pm; 3982 int64_t ret, refchg; 3983 3984 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 3985 3986 pm = sp->pvo_pmap; 3987 PMAP_LOCK_ASSERT(pm, MA_OWNED); 3988 3989 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 3990 refchg = 0; 3991 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 3992 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 3993 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 3994 panic("%s: pvo %p is missing PVO_WIRED", 3995 __func__, pvo); 3996 pvo->pvo_vaddr &= ~PVO_WIRED; 3997 3998 ret = moea64_pte_replace(pvo, 0 /* No invalidation */); 3999 if (ret < 0) 4000 refchg |= LPTE_CHG; 4001 else 4002 refchg |= ret; 4003 4004 pm->pm_stats.wired_count--; 4005 } 4006 4007 /* Send REF/CHG bits to VM */ 4008 moea64_sp_refchg_process(sp, PHYS_TO_VM_PAGE(PVO_PADDR(sp)), 4009 refchg, sp->pvo_pte.prot); 4010 4011 return (prev); 4012 } 4013 4014 static struct pvo_entry * 4015 moea64_sp_protect(struct pvo_entry *sp, vm_prot_t prot) 4016 { 4017 struct pvo_entry *pvo, *prev; 4018 vm_offset_t eva; 4019 pmap_t pm; 4020 vm_page_t m, m_end; 4021 int64_t ret, refchg; 4022 vm_prot_t oldprot; 4023 4024 CTR3(KTR_PMAP, "%s: va=%#jx, prot=%x", 4025 __func__, (uintmax_t)PVO_VADDR(sp), prot); 4026 4027 pm = sp->pvo_pmap; 4028 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4029 4030 oldprot = sp->pvo_pte.prot; 4031 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4032 KASSERT(m != NULL, ("%s: missing vm page for pa %#jx", 4033 __func__, (uintmax_t)PVO_PADDR(sp))); 4034 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4035 refchg = 0; 4036 4037 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4038 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 4039 pvo->pvo_pte.prot = prot; 4040 /* 4041 * If the PVO is in the page table, update mapping 4042 */ 4043 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 4044 if (ret < 0) 4045 refchg |= LPTE_CHG; 4046 else 4047 refchg |= ret; 4048 } 4049 4050 /* Send REF/CHG bits to VM */ 4051 moea64_sp_refchg_process(sp, m, refchg, oldprot); 4052 4053 /* Handle pages that became executable */ 4054 if ((m->a.flags & PGA_EXECUTABLE) == 0 && 4055 (sp->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 4056 if ((m->oflags & VPO_UNMANAGED) == 0) 4057 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) 4058 vm_page_aflag_set(m, PGA_EXECUTABLE); 4059 moea64_syncicache(pm, PVO_VADDR(sp), PVO_PADDR(sp), 4060 HPT_SP_SIZE); 4061 } 4062 4063 return (prev); 4064 } 4065 4066 static struct pvo_entry * 4067 moea64_sp_remove(struct pvo_entry *sp, struct pvo_dlist *tofree) 4068 { 4069 struct pvo_entry *pvo, *tpvo; 4070 vm_offset_t eva; 4071 pmap_t pm; 4072 4073 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 4074 4075 pm = sp->pvo_pmap; 4076 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4077 4078 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4079 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 4080 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 4081 4082 /* 4083 * For locking reasons, remove this from the page table and 4084 * pmap, but save delinking from the vm_page for a second 4085 * pass 4086 */ 4087 moea64_pvo_remove_from_pmap(pvo); 4088 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink); 4089 } 4090 4091 /* 4092 * Clear SP bit 4093 * 4094 * XXX See comment in moea64_sp_demote_aligned() for why it's 4095 * ok to always clear the SP bit on remove/demote. 4096 */ 4097 atomic_clear_32(&PHYS_TO_VM_PAGE(PVO_PADDR(sp))->md.mdpg_attrs, 4098 MDPG_ATTR_SP); 4099 4100 return (tpvo); 4101 } 4102 4103 static int64_t 4104 moea64_sp_query_locked(struct pvo_entry *pvo, uint64_t ptebit) 4105 { 4106 int64_t refchg, ret; 4107 vm_offset_t eva; 4108 vm_page_t m; 4109 pmap_t pmap; 4110 struct pvo_entry *sp; 4111 4112 pmap = pvo->pvo_pmap; 4113 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4114 4115 /* Get first SP PVO */ 4116 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 4117 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK); 4118 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx", 4119 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4120 } else 4121 sp = pvo; 4122 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4123 4124 refchg = 0; 4125 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4126 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 4127 ret = moea64_pte_synch(pvo); 4128 if (ret > 0) { 4129 refchg |= ret & (LPTE_CHG | LPTE_REF); 4130 if ((refchg & ptebit) != 0) 4131 break; 4132 } 4133 } 4134 4135 /* Save results */ 4136 if (refchg != 0) { 4137 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4138 atomic_set_32(&m->md.mdpg_attrs, refchg | MDPG_ATTR_SP); 4139 } 4140 4141 return (refchg); 4142 } 4143 4144 static int64_t 4145 moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit) 4146 { 4147 int64_t refchg; 4148 pmap_t pmap; 4149 4150 pmap = pvo->pvo_pmap; 4151 PMAP_LOCK(pmap); 4152 4153 /* 4154 * Check if SP was demoted/removed before pmap lock was acquired. 4155 */ 4156 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4157 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4158 __func__, (uintmax_t)PVO_PADDR(pvo)); 4159 PMAP_UNLOCK(pmap); 4160 return (-1); 4161 } 4162 4163 refchg = moea64_sp_query_locked(pvo, ptebit); 4164 PMAP_UNLOCK(pmap); 4165 4166 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx", 4167 __func__, (uintmax_t)PVO_VADDR(pvo), 4168 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)refchg); 4169 4170 return (refchg); 4171 } 4172 4173 static int64_t 4174 moea64_sp_pvo_clear(struct pvo_entry *pvo, uint64_t ptebit) 4175 { 4176 int64_t refchg, ret; 4177 pmap_t pmap; 4178 struct pvo_entry *sp; 4179 vm_offset_t eva; 4180 vm_page_t m; 4181 4182 pmap = pvo->pvo_pmap; 4183 PMAP_LOCK(pmap); 4184 4185 /* 4186 * Check if SP was demoted/removed before pmap lock was acquired. 4187 */ 4188 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4189 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4190 __func__, (uintmax_t)PVO_PADDR(pvo)); 4191 PMAP_UNLOCK(pmap); 4192 return (-1); 4193 } 4194 4195 /* Get first SP PVO */ 4196 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 4197 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK); 4198 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx", 4199 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4200 } else 4201 sp = pvo; 4202 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4203 4204 refchg = 0; 4205 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4206 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 4207 ret = moea64_pte_clear(pvo, ptebit); 4208 if (ret > 0) 4209 refchg |= ret & (LPTE_CHG | LPTE_REF); 4210 } 4211 4212 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4213 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 4214 PMAP_UNLOCK(pmap); 4215 4216 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx", 4217 __func__, (uintmax_t)PVO_VADDR(sp), 4218 (uintmax_t)PVO_PADDR(sp), (uintmax_t)refchg); 4219 4220 return (refchg); 4221 } 4222 4223 static int64_t 4224 moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, uint64_t ptebit) 4225 { 4226 int64_t count, ret; 4227 pmap_t pmap; 4228 4229 count = 0; 4230 pmap = pvo->pvo_pmap; 4231 4232 /* 4233 * Since this reference bit is shared by 4096 4KB pages, it 4234 * should not be cleared every time it is tested. Apply a 4235 * simple "hash" function on the physical page number, the 4236 * virtual superpage number, and the pmap address to select 4237 * one 4KB page out of the 4096 on which testing the 4238 * reference bit will result in clearing that reference bit. 4239 * This function is designed to avoid the selection of the 4240 * same 4KB page for every 16MB page mapping. 4241 * 4242 * Always leave the reference bit of a wired mapping set, as 4243 * the current state of its reference bit won't affect page 4244 * replacement. 4245 */ 4246 if (ptebit == LPTE_REF && (((VM_PAGE_TO_PHYS(m) >> PAGE_SHIFT) ^ 4247 (PVO_VADDR(pvo) >> HPT_SP_SHIFT) ^ (uintptr_t)pmap) & 4248 (HPT_SP_PAGES - 1)) == 0 && (pvo->pvo_vaddr & PVO_WIRED) == 0) { 4249 if ((ret = moea64_sp_pvo_clear(pvo, ptebit)) == -1) 4250 return (-1); 4251 4252 if ((ret & ptebit) != 0) 4253 count++; 4254 4255 /* 4256 * If this page was not selected by the hash function, then assume 4257 * its REF bit was set. 4258 */ 4259 } else if (ptebit == LPTE_REF) { 4260 count++; 4261 4262 /* 4263 * To clear the CHG bit of a single SP page, first it must be demoted. 4264 * But if no CHG bit is set, no bit clear and thus no SP demotion is 4265 * needed. 4266 */ 4267 } else { 4268 CTR4(KTR_PMAP, "%s: ptebit=%#jx, va=%#jx, pa=%#jx", 4269 __func__, (uintmax_t)ptebit, (uintmax_t)PVO_VADDR(pvo), 4270 (uintmax_t)PVO_PADDR(pvo)); 4271 4272 PMAP_LOCK(pmap); 4273 4274 /* 4275 * Make sure SP wasn't demoted/removed before pmap lock 4276 * was acquired. 4277 */ 4278 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4279 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4280 __func__, (uintmax_t)PVO_PADDR(pvo)); 4281 PMAP_UNLOCK(pmap); 4282 return (-1); 4283 } 4284 4285 ret = moea64_sp_query_locked(pvo, ptebit); 4286 if ((ret & ptebit) != 0) 4287 count++; 4288 else { 4289 PMAP_UNLOCK(pmap); 4290 return (0); 4291 } 4292 4293 moea64_sp_demote(pvo); 4294 moea64_pte_clear(pvo, ptebit); 4295 4296 /* 4297 * Write protect the mapping to a single page so that a 4298 * subsequent write access may repromote. 4299 */ 4300 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 4301 moea64_pvo_protect(pmap, pvo, 4302 pvo->pvo_pte.prot & ~VM_PROT_WRITE); 4303 4304 PMAP_UNLOCK(pmap); 4305 } 4306 4307 return (count); 4308 } 4309