1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/cpu.h> 146 #include <machine/platform.h> 147 #include <machine/frame.h> 148 #include <machine/md_var.h> 149 #include <machine/psl.h> 150 #include <machine/bat.h> 151 #include <machine/pte.h> 152 #include <machine/sr.h> 153 #include <machine/trap.h> 154 #include <machine/mmuvar.h> 155 156 #include "mmu_if.h" 157 158 #define MOEA_DEBUG 159 160 #define TODO panic("%s: not implemented", __func__); 161 162 static __inline u_int32_t 163 cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167 } 168 169 static __inline uint64_t 170 va_to_vsid(pmap_t pm, vm_offset_t va) 171 { 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173 } 174 175 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 176 #define SYNC() __asm __volatile("sync"); 177 #define EIEIO() __asm __volatile("eieio"); 178 179 /* 180 * The tlbie instruction must be executed in 64-bit mode 181 * so we have to twiddle MSR[SF] around every invocation. 182 * Just to add to the fun, exceptions must be off as well 183 * so that we can't trap in 64-bit mode. What a pain. 184 */ 185 struct mtx tlbie_mutex; 186 187 static __inline void 188 TLBIE(pmap_t pmap, vm_offset_t va) { 189 uint64_t vpn; 190 register_t vpn_hi, vpn_lo; 191 register_t msr; 192 register_t scratch; 193 194 vpn = (uint64_t)(va & ADDR_PIDX); 195 if (pmap != NULL) 196 vpn |= (va_to_vsid(pmap,va) << 28); 197 198 vpn_hi = (uint32_t)(vpn >> 32); 199 vpn_lo = (uint32_t)vpn; 200 201 mtx_lock_spin(&tlbie_mutex); 202 __asm __volatile("\ 203 mfmsr %0; \ 204 clrldi %1,%0,49; \ 205 mtmsr %1; \ 206 insrdi %1,%5,1,0; \ 207 mtmsrd %1; \ 208 ptesync; \ 209 \ 210 sld %1,%2,%4; \ 211 or %1,%1,%3; \ 212 tlbie %1; \ 213 \ 214 mtmsrd %0; \ 215 eieio; \ 216 tlbsync; \ 217 ptesync;" 218 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1)); 219 mtx_unlock_spin(&tlbie_mutex); 220 } 221 222 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 223 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 224 225 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 226 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 227 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 228 229 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 230 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 231 #define PVO_WIRED 0x010 /* PVO entry is wired */ 232 #define PVO_MANAGED 0x020 /* PVO entry is managed */ 233 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 234 bootstrap */ 235 #define PVO_FAKE 0x100 /* fictitious phys page */ 236 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 237 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 238 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 239 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 240 #define PVO_PTEGIDX_CLR(pvo) \ 241 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 242 #define PVO_PTEGIDX_SET(pvo, i) \ 243 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 244 245 #define MOEA_PVO_CHECK(pvo) 246 247 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 248 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 249 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 250 251 struct ofw_map { 252 vm_offset_t om_va; 253 vm_size_t om_len; 254 vm_offset_t om_pa_hi; 255 vm_offset_t om_pa_lo; 256 u_int om_mode; 257 }; 258 259 /* 260 * Map of physical memory regions. 261 */ 262 static struct mem_region *regions; 263 static struct mem_region *pregions; 264 extern u_int phys_avail_count; 265 extern int regions_sz, pregions_sz; 266 extern int ofw_real_mode; 267 static struct ofw_map translations[64]; 268 269 extern struct pmap ofw_pmap; 270 271 extern void bs_remap_earlyboot(void); 272 273 274 /* 275 * Lock for the pteg and pvo tables. 276 */ 277 struct mtx moea64_table_mutex; 278 279 /* 280 * PTEG data. 281 */ 282 static struct lpteg *moea64_pteg_table; 283 u_int moea64_pteg_count; 284 u_int moea64_pteg_mask; 285 286 /* 287 * PVO data. 288 */ 289 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 290 /* lists of unmanaged pages */ 291 struct pvo_head moea64_pvo_kunmanaged = 292 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 293 struct pvo_head moea64_pvo_unmanaged = 294 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 295 296 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 297 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 298 299 vm_offset_t pvo_allocator_start; 300 vm_offset_t pvo_allocator_end; 301 302 #define BPVO_POOL_SIZE 327680 303 static struct pvo_entry *moea64_bpvo_pool; 304 static int moea64_bpvo_pool_index = 0; 305 306 #define VSID_NBPW (sizeof(u_int32_t) * 8) 307 static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 308 309 static boolean_t moea64_initialized = FALSE; 310 311 /* 312 * Statistics. 313 */ 314 u_int moea64_pte_valid = 0; 315 u_int moea64_pte_overflow = 0; 316 u_int moea64_pvo_entries = 0; 317 u_int moea64_pvo_enter_calls = 0; 318 u_int moea64_pvo_remove_calls = 0; 319 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 320 &moea64_pte_valid, 0, ""); 321 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 322 &moea64_pte_overflow, 0, ""); 323 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 324 &moea64_pvo_entries, 0, ""); 325 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 326 &moea64_pvo_enter_calls, 0, ""); 327 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 328 &moea64_pvo_remove_calls, 0, ""); 329 330 vm_offset_t moea64_scratchpage_va[2]; 331 struct pvo_entry *moea64_scratchpage_pvo[2]; 332 struct lpte *moea64_scratchpage_pte[2]; 333 struct mtx moea64_scratchpage_mtx; 334 335 /* 336 * Allocate physical memory for use in moea64_bootstrap. 337 */ 338 static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 339 340 /* 341 * PTE calls. 342 */ 343 static int moea64_pte_insert(u_int, struct lpte *); 344 345 /* 346 * PVO calls. 347 */ 348 static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 349 vm_offset_t, vm_offset_t, uint64_t, int); 350 static void moea64_pvo_remove(struct pvo_entry *, int); 351 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 352 static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 353 354 /* 355 * Utility routines. 356 */ 357 static void moea64_bridge_bootstrap(mmu_t mmup, 358 vm_offset_t kernelstart, vm_offset_t kernelend); 359 static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 360 static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 361 vm_prot_t, boolean_t); 362 static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 363 static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *); 364 static void moea64_kremove(mmu_t, vm_offset_t); 365 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 366 vm_offset_t pa, vm_size_t sz); 367 static void tlbia(void); 368 369 /* 370 * Kernel MMU interface 371 */ 372 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 373 void moea64_clear_modify(mmu_t, vm_page_t); 374 void moea64_clear_reference(mmu_t, vm_page_t); 375 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 376 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 377 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 378 vm_prot_t); 379 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 380 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 381 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 382 void moea64_init(mmu_t); 383 boolean_t moea64_is_modified(mmu_t, vm_page_t); 384 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 385 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 386 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 387 int moea64_page_wired_mappings(mmu_t, vm_page_t); 388 void moea64_pinit(mmu_t, pmap_t); 389 void moea64_pinit0(mmu_t, pmap_t); 390 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 391 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 392 void moea64_qremove(mmu_t, vm_offset_t, int); 393 void moea64_release(mmu_t, pmap_t); 394 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 395 void moea64_remove_all(mmu_t, vm_page_t); 396 void moea64_remove_write(mmu_t, vm_page_t); 397 void moea64_zero_page(mmu_t, vm_page_t); 398 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 399 void moea64_zero_page_idle(mmu_t, vm_page_t); 400 void moea64_activate(mmu_t, struct thread *); 401 void moea64_deactivate(mmu_t, struct thread *); 402 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 403 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 404 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 405 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 406 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 407 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 408 409 static mmu_method_t moea64_bridge_methods[] = { 410 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 411 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 412 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 413 MMUMETHOD(mmu_copy_page, moea64_copy_page), 414 MMUMETHOD(mmu_enter, moea64_enter), 415 MMUMETHOD(mmu_enter_object, moea64_enter_object), 416 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 417 MMUMETHOD(mmu_extract, moea64_extract), 418 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 419 MMUMETHOD(mmu_init, moea64_init), 420 MMUMETHOD(mmu_is_modified, moea64_is_modified), 421 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 422 MMUMETHOD(mmu_map, moea64_map), 423 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 424 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 425 MMUMETHOD(mmu_pinit, moea64_pinit), 426 MMUMETHOD(mmu_pinit0, moea64_pinit0), 427 MMUMETHOD(mmu_protect, moea64_protect), 428 MMUMETHOD(mmu_qenter, moea64_qenter), 429 MMUMETHOD(mmu_qremove, moea64_qremove), 430 MMUMETHOD(mmu_release, moea64_release), 431 MMUMETHOD(mmu_remove, moea64_remove), 432 MMUMETHOD(mmu_remove_all, moea64_remove_all), 433 MMUMETHOD(mmu_remove_write, moea64_remove_write), 434 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 435 MMUMETHOD(mmu_zero_page, moea64_zero_page), 436 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 437 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 438 MMUMETHOD(mmu_activate, moea64_activate), 439 MMUMETHOD(mmu_deactivate, moea64_deactivate), 440 441 /* Internal interfaces */ 442 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 443 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 444 MMUMETHOD(mmu_mapdev, moea64_mapdev), 445 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 446 MMUMETHOD(mmu_kextract, moea64_kextract), 447 MMUMETHOD(mmu_kenter, moea64_kenter), 448 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 449 450 { 0, 0 } 451 }; 452 453 static mmu_def_t oea64_bridge_mmu = { 454 MMU_TYPE_G5, 455 moea64_bridge_methods, 456 0 457 }; 458 MMU_DEF(oea64_bridge_mmu); 459 460 static __inline u_int 461 va_to_pteg(uint64_t vsid, vm_offset_t addr) 462 { 463 u_int hash; 464 465 hash = vsid ^ (((uint64_t)addr & ADDR_PIDX) >> 466 ADDR_PIDX_SHFT); 467 return (hash & moea64_pteg_mask); 468 } 469 470 static __inline struct pvo_head * 471 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 472 { 473 struct vm_page *pg; 474 475 pg = PHYS_TO_VM_PAGE(pa); 476 477 if (pg_p != NULL) 478 *pg_p = pg; 479 480 if (pg == NULL) 481 return (&moea64_pvo_unmanaged); 482 483 return (&pg->md.mdpg_pvoh); 484 } 485 486 static __inline struct pvo_head * 487 vm_page_to_pvoh(vm_page_t m) 488 { 489 490 return (&m->md.mdpg_pvoh); 491 } 492 493 static __inline void 494 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 495 { 496 497 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 498 m->md.mdpg_attrs &= ~ptebit; 499 } 500 501 static __inline u_int64_t 502 moea64_attr_fetch(vm_page_t m) 503 { 504 505 return (m->md.mdpg_attrs); 506 } 507 508 static __inline void 509 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 510 { 511 512 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 513 m->md.mdpg_attrs |= ptebit; 514 } 515 516 static __inline int 517 moea64_pte_compare(const struct lpte *pt, const struct lpte *pvo_pt) 518 { 519 if (pt->pte_hi == pvo_pt->pte_hi) 520 return (1); 521 522 return (0); 523 } 524 525 static __inline int 526 moea64_pte_match(struct lpte *pt, uint64_t vsid, vm_offset_t va, int which) 527 { 528 return (pt->pte_hi & ~LPTE_VALID) == 529 ((vsid << LPTE_VSID_SHIFT) | 530 ((uint64_t)(va >> ADDR_API_SHFT64) & LPTE_API) | which); 531 } 532 533 static __inline void 534 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 535 uint64_t pte_lo) 536 { 537 ASSERT_TABLE_LOCK(); 538 539 /* 540 * Construct a PTE. Default to IMB initially. Valid bit only gets 541 * set when the real pte is set in memory. 542 * 543 * Note: Don't set the valid bit for correct operation of tlb update. 544 */ 545 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 546 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 547 548 pt->pte_lo = pte_lo; 549 } 550 551 static __inline void 552 moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 553 { 554 555 ASSERT_TABLE_LOCK(); 556 557 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 558 } 559 560 static __inline void 561 moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 562 { 563 ASSERT_TABLE_LOCK(); 564 565 /* 566 * As shown in Section 7.6.3.2.3 567 */ 568 pt->pte_lo &= ~ptebit; 569 TLBIE(pmap,va); 570 } 571 572 static __inline void 573 moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 574 { 575 576 ASSERT_TABLE_LOCK(); 577 pvo_pt->pte_hi |= LPTE_VALID; 578 579 /* 580 * Update the PTE as defined in section 7.6.3.1. 581 * Note that the REF/CHG bits are from pvo_pt and thus should have 582 * been saved so this routine can restore them (if desired). 583 */ 584 pt->pte_lo = pvo_pt->pte_lo; 585 EIEIO(); 586 pt->pte_hi = pvo_pt->pte_hi; 587 SYNC(); 588 moea64_pte_valid++; 589 } 590 591 static __inline void 592 moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 593 { 594 ASSERT_TABLE_LOCK(); 595 pvo_pt->pte_hi &= ~LPTE_VALID; 596 597 /* 598 * Force the reg & chg bits back into the PTEs. 599 */ 600 SYNC(); 601 602 /* 603 * Invalidate the pte. 604 */ 605 pt->pte_hi &= ~LPTE_VALID; 606 607 TLBIE(pmap,va); 608 609 /* 610 * Save the reg & chg bits. 611 */ 612 moea64_pte_synch(pt, pvo_pt); 613 moea64_pte_valid--; 614 } 615 616 static __inline void 617 moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 618 { 619 620 /* 621 * Invalidate the PTE 622 */ 623 moea64_pte_unset(pt, pvo_pt, pmap, va); 624 moea64_pte_set(pt, pvo_pt); 625 } 626 627 static __inline uint64_t 628 moea64_calc_wimg(vm_offset_t pa) 629 { 630 uint64_t pte_lo; 631 int i; 632 633 /* 634 * Assume the page is cache inhibited and access is guarded unless 635 * it's in our available memory array. 636 */ 637 pte_lo = LPTE_I | LPTE_G; 638 for (i = 0; i < pregions_sz; i++) { 639 if ((pa >= pregions[i].mr_start) && 640 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 641 pte_lo &= ~(LPTE_I | LPTE_G); 642 pte_lo |= LPTE_M; 643 break; 644 } 645 } 646 647 return pte_lo; 648 } 649 650 /* 651 * Quick sort callout for comparing memory regions. 652 */ 653 static int mr_cmp(const void *a, const void *b); 654 static int om_cmp(const void *a, const void *b); 655 656 static int 657 mr_cmp(const void *a, const void *b) 658 { 659 const struct mem_region *regiona; 660 const struct mem_region *regionb; 661 662 regiona = a; 663 regionb = b; 664 if (regiona->mr_start < regionb->mr_start) 665 return (-1); 666 else if (regiona->mr_start > regionb->mr_start) 667 return (1); 668 else 669 return (0); 670 } 671 672 static int 673 om_cmp(const void *a, const void *b) 674 { 675 const struct ofw_map *mapa; 676 const struct ofw_map *mapb; 677 678 mapa = a; 679 mapb = b; 680 if (mapa->om_pa_hi < mapb->om_pa_hi) 681 return (-1); 682 else if (mapa->om_pa_hi > mapb->om_pa_hi) 683 return (1); 684 else if (mapa->om_pa_lo < mapb->om_pa_lo) 685 return (-1); 686 else if (mapa->om_pa_lo > mapb->om_pa_lo) 687 return (1); 688 else 689 return (0); 690 } 691 692 static void 693 moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 694 { 695 int i = 0; 696 697 /* 698 * Initialize segment registers and MMU 699 */ 700 701 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 702 for (i = 0; i < 16; i++) { 703 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 704 } 705 __asm __volatile ("sync; mtsdr1 %0; isync" 706 :: "r"((u_int)moea64_pteg_table 707 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 708 tlbia(); 709 } 710 711 static void 712 moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 713 { 714 ihandle_t mmui; 715 phandle_t chosen; 716 phandle_t mmu; 717 int sz; 718 int i, j; 719 int ofw_mappings; 720 vm_size_t size, physsz, hwphyssz; 721 vm_offset_t pa, va, off; 722 uint32_t msr; 723 void *dpcpu; 724 725 /* We don't have a direct map since there is no BAT */ 726 hw_direct_map = 0; 727 728 /* Make sure battable is zero, since we have no BAT */ 729 for (i = 0; i < 16; i++) { 730 battable[i].batu = 0; 731 battable[i].batl = 0; 732 } 733 734 /* Get physical memory regions from firmware */ 735 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 736 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 737 738 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 739 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 740 panic("moea64_bootstrap: phys_avail too small"); 741 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 742 phys_avail_count = 0; 743 physsz = 0; 744 hwphyssz = 0; 745 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 746 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 747 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 748 regions[i].mr_start + regions[i].mr_size, 749 regions[i].mr_size); 750 if (hwphyssz != 0 && 751 (physsz + regions[i].mr_size) >= hwphyssz) { 752 if (physsz < hwphyssz) { 753 phys_avail[j] = regions[i].mr_start; 754 phys_avail[j + 1] = regions[i].mr_start + 755 hwphyssz - physsz; 756 physsz = hwphyssz; 757 phys_avail_count++; 758 } 759 break; 760 } 761 phys_avail[j] = regions[i].mr_start; 762 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 763 phys_avail_count++; 764 physsz += regions[i].mr_size; 765 } 766 physmem = btoc(physsz); 767 768 /* 769 * Allocate PTEG table. 770 */ 771 #ifdef PTEGCOUNT 772 moea64_pteg_count = PTEGCOUNT; 773 #else 774 moea64_pteg_count = 0x1000; 775 776 while (moea64_pteg_count < physmem) 777 moea64_pteg_count <<= 1; 778 #endif /* PTEGCOUNT */ 779 780 size = moea64_pteg_count * sizeof(struct lpteg); 781 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 782 moea64_pteg_count, size); 783 784 /* 785 * We now need to allocate memory. This memory, to be allocated, 786 * has to reside in a page table. The page table we are about to 787 * allocate. We don't have BAT. So drop to data real mode for a minute 788 * as a measure of last resort. We do this a couple times. 789 */ 790 791 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 792 DISABLE_TRANS(msr); 793 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 794 ENABLE_TRANS(msr); 795 796 moea64_pteg_mask = moea64_pteg_count - 1; 797 798 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 799 800 /* 801 * Allocate pv/overflow lists. 802 */ 803 size = sizeof(struct pvo_head) * moea64_pteg_count; 804 805 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 806 PAGE_SIZE); 807 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 808 809 DISABLE_TRANS(msr); 810 for (i = 0; i < moea64_pteg_count; i++) 811 LIST_INIT(&moea64_pvo_table[i]); 812 ENABLE_TRANS(msr); 813 814 /* 815 * Initialize the lock that synchronizes access to the pteg and pvo 816 * tables. 817 */ 818 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 819 MTX_RECURSE); 820 821 /* 822 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 823 */ 824 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 825 826 /* 827 * Initialise the unmanaged pvo pool. 828 */ 829 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 830 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 831 moea64_bpvo_pool_index = 0; 832 833 /* 834 * Make sure kernel vsid is allocated as well as VSID 0. 835 */ 836 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 837 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 838 moea64_vsid_bitmap[0] |= 1; 839 840 /* 841 * Initialize the kernel pmap (which is statically allocated). 842 */ 843 for (i = 0; i < 16; i++) 844 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 845 846 kernel_pmap->pmap_phys = kernel_pmap; 847 kernel_pmap->pm_active = ~0; 848 849 PMAP_LOCK_INIT(kernel_pmap); 850 851 /* 852 * Now map in all the other buffers we allocated earlier 853 */ 854 855 DISABLE_TRANS(msr); 856 size = moea64_pteg_count * sizeof(struct lpteg); 857 off = (vm_offset_t)(moea64_pteg_table); 858 for (pa = off; pa < off + size; pa += PAGE_SIZE) 859 moea64_kenter(mmup, pa, pa); 860 size = sizeof(struct pvo_head) * moea64_pteg_count; 861 off = (vm_offset_t)(moea64_pvo_table); 862 for (pa = off; pa < off + size; pa += PAGE_SIZE) 863 moea64_kenter(mmup, pa, pa); 864 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 865 off = (vm_offset_t)(moea64_bpvo_pool); 866 for (pa = off; pa < off + size; pa += PAGE_SIZE) 867 moea64_kenter(mmup, pa, pa); 868 ENABLE_TRANS(msr); 869 870 /* 871 * Map certain important things, like ourselves and the exception 872 * vectors 873 */ 874 875 DISABLE_TRANS(msr); 876 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 877 moea64_kenter(mmup, pa, pa); 878 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 879 moea64_kenter(mmup, pa, pa); 880 ENABLE_TRANS(msr); 881 882 if (!ofw_real_mode) { 883 /* 884 * Set up the Open Firmware pmap and add its mappings. 885 */ 886 887 moea64_pinit(mmup, &ofw_pmap); 888 ofw_pmap.pm_sr[KERNEL_SR] = kernel_pmap->pm_sr[KERNEL_SR]; 889 ofw_pmap.pm_sr[KERNEL2_SR] = kernel_pmap->pm_sr[KERNEL2_SR]; 890 891 if ((chosen = OF_finddevice("/chosen")) == -1) 892 panic("moea64_bootstrap: can't find /chosen"); 893 OF_getprop(chosen, "mmu", &mmui, 4); 894 if ((mmu = OF_instance_to_package(mmui)) == -1) 895 panic("moea64_bootstrap: can't get mmu package"); 896 if ((sz = OF_getproplen(mmu, "translations")) == -1) 897 panic("moea64_bootstrap: can't get ofw translation count"); 898 899 bzero(translations, sz); 900 if (OF_getprop(mmu, "translations", translations, sz) == -1) 901 panic("moea64_bootstrap: can't get ofw translations"); 902 903 CTR0(KTR_PMAP, "moea64_bootstrap: translations"); 904 sz /= sizeof(*translations); 905 qsort(translations, sz, sizeof (*translations), om_cmp); 906 907 for (i = 0, ofw_mappings = 0; i < sz; i++) { 908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 909 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 910 translations[i].om_len); 911 912 if (translations[i].om_pa_lo % PAGE_SIZE) 913 panic("OFW translation not page-aligned!"); 914 915 if (translations[i].om_pa_hi) 916 panic("OFW translations above 32-bit boundary!"); 917 918 /* Now enter the pages for this mapping */ 919 920 /* 921 * Lock the ofw pmap. pmap_kenter(), which we use for the 922 * pages the kernel also needs, does its own locking. 923 */ 924 PMAP_LOCK(&ofw_pmap); 925 DISABLE_TRANS(msr); 926 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 927 struct vm_page m; 928 929 /* Map low memory mappings into the kernel pmap, too. 930 * These are typically mappings made by the loader, 931 * so we need them if we want to keep executing. */ 932 933 if (translations[i].om_va + off < SEGMENT_LENGTH) 934 moea64_kenter(mmup, translations[i].om_va + off, 935 translations[i].om_va + off); 936 937 m.phys_addr = translations[i].om_pa_lo + off; 938 moea64_enter_locked(&ofw_pmap, 939 translations[i].om_va + off, &m, VM_PROT_ALL, 1); 940 941 ofw_mappings++; 942 } 943 ENABLE_TRANS(msr); 944 PMAP_UNLOCK(&ofw_pmap); 945 } 946 } 947 948 #ifdef SMP 949 TLBSYNC(); 950 #endif 951 952 /* 953 * Calculate the last available physical address. 954 */ 955 for (i = 0; phys_avail[i + 2] != 0; i += 2) 956 ; 957 Maxmem = powerpc_btop(phys_avail[i + 1]); 958 959 /* 960 * Initialize MMU and remap early physical mappings 961 */ 962 moea64_bridge_cpu_bootstrap(mmup,0); 963 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 964 pmap_bootstrapped++; 965 bs_remap_earlyboot(); 966 967 /* 968 * Set the start and end of kva. 969 */ 970 virtual_avail = VM_MIN_KERNEL_ADDRESS; 971 virtual_end = VM_MAX_KERNEL_ADDRESS; 972 973 /* 974 * Allocate some stupid buffer regions. 975 */ 976 977 pvo_allocator_start = virtual_avail; 978 virtual_avail += SEGMENT_LENGTH/4; 979 pvo_allocator_end = virtual_avail; 980 981 /* 982 * Allocate some things for page zeroing 983 */ 984 985 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 986 for (i = 0; i < 2; i++) { 987 moea64_scratchpage_va[i] = virtual_avail; 988 virtual_avail += PAGE_SIZE; 989 990 moea64_kenter(mmup,moea64_scratchpage_va[i],kernelstart); 991 992 LOCK_TABLE(); 993 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(kernel_pmap, 994 moea64_scratchpage_va[i],&j); 995 moea64_scratchpage_pte[i] = moea64_pvo_to_pte( 996 moea64_scratchpage_pvo[i],j); 997 UNLOCK_TABLE(); 998 } 999 1000 /* 1001 * Allocate a kernel stack with a guard page for thread0 and map it 1002 * into the kernel page map. 1003 */ 1004 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1005 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1006 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1007 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1008 thread0.td_kstack = va; 1009 thread0.td_kstack_pages = KSTACK_PAGES; 1010 for (i = 0; i < KSTACK_PAGES; i++) { 1011 moea64_kenter(mmup, va, pa);; 1012 pa += PAGE_SIZE; 1013 va += PAGE_SIZE; 1014 } 1015 1016 /* 1017 * Allocate virtual address space for the message buffer. 1018 */ 1019 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1020 msgbufp = (struct msgbuf *)virtual_avail; 1021 va = virtual_avail; 1022 virtual_avail += round_page(MSGBUF_SIZE); 1023 while (va < virtual_avail) { 1024 moea64_kenter(mmup, va, pa);; 1025 pa += PAGE_SIZE; 1026 va += PAGE_SIZE; 1027 } 1028 1029 /* 1030 * Allocate virtual address space for the dynamic percpu area. 1031 */ 1032 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1033 dpcpu = (void *)virtual_avail; 1034 va = virtual_avail; 1035 virtual_avail += DPCPU_SIZE; 1036 while (va < virtual_avail) { 1037 moea64_kenter(mmup, va, pa);; 1038 pa += PAGE_SIZE; 1039 va += PAGE_SIZE; 1040 } 1041 dpcpu_init(dpcpu, 0); 1042 } 1043 1044 /* 1045 * Activate a user pmap. The pmap must be activated before it's address 1046 * space can be accessed in any way. 1047 */ 1048 void 1049 moea64_activate(mmu_t mmu, struct thread *td) 1050 { 1051 pmap_t pm, pmr; 1052 1053 /* 1054 * Load all the data we need up front to encourage the compiler to 1055 * not issue any loads while we have interrupts disabled below. 1056 */ 1057 pm = &td->td_proc->p_vmspace->vm_pmap; 1058 pmr = pm->pmap_phys; 1059 1060 pm->pm_active |= PCPU_GET(cpumask); 1061 PCPU_SET(curpmap, pmr); 1062 } 1063 1064 void 1065 moea64_deactivate(mmu_t mmu, struct thread *td) 1066 { 1067 pmap_t pm; 1068 1069 pm = &td->td_proc->p_vmspace->vm_pmap; 1070 pm->pm_active &= ~(PCPU_GET(cpumask)); 1071 PCPU_SET(curpmap, NULL); 1072 } 1073 1074 void 1075 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1076 { 1077 struct pvo_entry *pvo; 1078 1079 PMAP_LOCK(pm); 1080 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1081 1082 if (pvo != NULL) { 1083 if (wired) { 1084 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1085 pm->pm_stats.wired_count++; 1086 pvo->pvo_vaddr |= PVO_WIRED; 1087 } else { 1088 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1089 pm->pm_stats.wired_count--; 1090 pvo->pvo_vaddr &= ~PVO_WIRED; 1091 } 1092 } 1093 PMAP_UNLOCK(pm); 1094 } 1095 1096 /* 1097 * Zero a page of physical memory by temporarily mapping it into the tlb. 1098 */ 1099 void 1100 moea64_zero_page(mmu_t mmu, vm_page_t m) 1101 { 1102 moea64_zero_page_area(mmu,m,0,PAGE_SIZE); 1103 } 1104 1105 /* 1106 * This goes through and sets the physical address of our 1107 * special scratch PTE to the PA we want to zero or copy. Because 1108 * of locking issues (this can get called in pvo_enter() by 1109 * the UMA allocator), we can't use most other utility functions here 1110 */ 1111 1112 static __inline 1113 void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1114 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1115 (~LPTE_WIMG & ~LPTE_RPGN); 1116 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1117 moea64_calc_wimg(pa) | (uint64_t)pa; 1118 1119 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1120 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1121 1122 moea64_scratchpage_pte[which]->pte_lo = 1123 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo; 1124 EIEIO(); 1125 1126 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1127 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1128 } 1129 1130 void 1131 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1132 { 1133 vm_offset_t dst; 1134 vm_offset_t src; 1135 1136 dst = VM_PAGE_TO_PHYS(mdst); 1137 src = VM_PAGE_TO_PHYS(msrc); 1138 1139 mtx_lock(&moea64_scratchpage_mtx); 1140 1141 moea64_set_scratchpage_pa(0,src); 1142 moea64_set_scratchpage_pa(1,dst); 1143 1144 kcopy((void *)moea64_scratchpage_va[0], 1145 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1146 1147 __syncicache((void *)moea64_scratchpage_va[1],PAGE_SIZE); 1148 1149 mtx_unlock(&moea64_scratchpage_mtx); 1150 } 1151 1152 void 1153 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1154 { 1155 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1156 1157 if (!moea64_initialized) 1158 panic("moea64_zero_page: can't zero pa %#x", pa); 1159 if (size + off > PAGE_SIZE) 1160 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1161 1162 mtx_lock(&moea64_scratchpage_mtx); 1163 1164 moea64_set_scratchpage_pa(0,pa); 1165 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1166 __syncicache((void *)moea64_scratchpage_va[0],PAGE_SIZE); 1167 1168 mtx_unlock(&moea64_scratchpage_mtx); 1169 } 1170 1171 void 1172 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1173 { 1174 1175 moea64_zero_page(mmu, m); 1176 } 1177 1178 /* 1179 * Map the given physical page at the specified virtual address in the 1180 * target pmap with the protection requested. If specified the page 1181 * will be wired down. 1182 */ 1183 void 1184 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1185 vm_prot_t prot, boolean_t wired) 1186 { 1187 1188 vm_page_lock_queues(); 1189 PMAP_LOCK(pmap); 1190 moea64_enter_locked(pmap, va, m, prot, wired); 1191 vm_page_unlock_queues(); 1192 PMAP_UNLOCK(pmap); 1193 } 1194 1195 /* 1196 * Map the given physical page at the specified virtual address in the 1197 * target pmap with the protection requested. If specified the page 1198 * will be wired down. 1199 * 1200 * The page queues and pmap must be locked. 1201 */ 1202 1203 static void 1204 moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1205 boolean_t wired) 1206 { 1207 struct pvo_head *pvo_head; 1208 uma_zone_t zone; 1209 vm_page_t pg; 1210 uint64_t pte_lo; 1211 u_int pvo_flags; 1212 int error; 1213 1214 if (!moea64_initialized) { 1215 pvo_head = &moea64_pvo_kunmanaged; 1216 pg = NULL; 1217 zone = moea64_upvo_zone; 1218 pvo_flags = 0; 1219 } else { 1220 pvo_head = vm_page_to_pvoh(m); 1221 pg = m; 1222 zone = moea64_mpvo_zone; 1223 pvo_flags = PVO_MANAGED; 1224 } 1225 1226 if (pmap_bootstrapped) 1227 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1228 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1229 1230 /* XXX change the pvo head for fake pages */ 1231 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1232 pvo_flags &= ~PVO_MANAGED; 1233 pvo_head = &moea64_pvo_kunmanaged; 1234 zone = moea64_upvo_zone; 1235 } 1236 1237 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1238 1239 if (prot & VM_PROT_WRITE) { 1240 pte_lo |= LPTE_BW; 1241 if (pmap_bootstrapped) 1242 vm_page_flag_set(m, PG_WRITEABLE); 1243 } else 1244 pte_lo |= LPTE_BR; 1245 1246 if (prot & VM_PROT_EXECUTE) 1247 pvo_flags |= VM_PROT_EXECUTE; 1248 1249 if (wired) 1250 pvo_flags |= PVO_WIRED; 1251 1252 if ((m->flags & PG_FICTITIOUS) != 0) 1253 pvo_flags |= PVO_FAKE; 1254 1255 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1256 pte_lo, pvo_flags); 1257 1258 if (pmap == kernel_pmap) 1259 TLBIE(pmap, va); 1260 1261 /* 1262 * Flush the page from the instruction cache if this page is 1263 * mapped executable and cacheable. 1264 */ 1265 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1266 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1267 } 1268 } 1269 1270 static void 1271 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1272 { 1273 /* 1274 * This is much trickier than on older systems because 1275 * we can't sync the icache on physical addresses directly 1276 * without a direct map. Instead we check a couple of cases 1277 * where the memory is already mapped in and, failing that, 1278 * use the same trick we use for page zeroing to create 1279 * a temporary mapping for this physical address. 1280 */ 1281 1282 if (!pmap_bootstrapped) { 1283 /* 1284 * If PMAP is not bootstrapped, we are likely to be 1285 * in real mode. 1286 */ 1287 __syncicache((void *)pa, sz); 1288 } else if (pmap == kernel_pmap) { 1289 __syncicache((void *)va, sz); 1290 } else { 1291 /* Use the scratch page to set up a temp mapping */ 1292 1293 mtx_lock(&moea64_scratchpage_mtx); 1294 1295 moea64_set_scratchpage_pa(1,pa); 1296 __syncicache((void *)moea64_scratchpage_va[1], sz); 1297 1298 mtx_unlock(&moea64_scratchpage_mtx); 1299 } 1300 } 1301 1302 /* 1303 * Maps a sequence of resident pages belonging to the same object. 1304 * The sequence begins with the given page m_start. This page is 1305 * mapped at the given virtual address start. Each subsequent page is 1306 * mapped at a virtual address that is offset from start by the same 1307 * amount as the page is offset from m_start within the object. The 1308 * last page in the sequence is the page with the largest offset from 1309 * m_start that can be mapped at a virtual address less than the given 1310 * virtual address end. Not every virtual page between start and end 1311 * is mapped; only those for which a resident page exists with the 1312 * corresponding offset from m_start are mapped. 1313 */ 1314 void 1315 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1316 vm_page_t m_start, vm_prot_t prot) 1317 { 1318 vm_page_t m; 1319 vm_pindex_t diff, psize; 1320 1321 psize = atop(end - start); 1322 m = m_start; 1323 PMAP_LOCK(pm); 1324 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1325 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1326 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1327 m = TAILQ_NEXT(m, listq); 1328 } 1329 PMAP_UNLOCK(pm); 1330 } 1331 1332 void 1333 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1334 vm_prot_t prot) 1335 { 1336 PMAP_LOCK(pm); 1337 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1338 FALSE); 1339 PMAP_UNLOCK(pm); 1340 1341 } 1342 1343 vm_paddr_t 1344 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1345 { 1346 struct pvo_entry *pvo; 1347 vm_paddr_t pa; 1348 1349 PMAP_LOCK(pm); 1350 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1351 if (pvo == NULL) 1352 pa = 0; 1353 else 1354 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1355 PMAP_UNLOCK(pm); 1356 return (pa); 1357 } 1358 1359 /* 1360 * Atomically extract and hold the physical page with the given 1361 * pmap and virtual address pair if that mapping permits the given 1362 * protection. 1363 */ 1364 vm_page_t 1365 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1366 { 1367 struct pvo_entry *pvo; 1368 vm_page_t m; 1369 1370 m = NULL; 1371 vm_page_lock_queues(); 1372 PMAP_LOCK(pmap); 1373 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1374 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1375 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1376 (prot & VM_PROT_WRITE) == 0)) { 1377 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1378 vm_page_hold(m); 1379 } 1380 vm_page_unlock_queues(); 1381 PMAP_UNLOCK(pmap); 1382 return (m); 1383 } 1384 1385 static void * 1386 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1387 { 1388 /* 1389 * This entire routine is a horrible hack to avoid bothering kmem 1390 * for new KVA addresses. Because this can get called from inside 1391 * kmem allocation routines, calling kmem for a new address here 1392 * can lead to multiply locking non-recursive mutexes. 1393 */ 1394 static vm_pindex_t color; 1395 vm_offset_t va; 1396 1397 vm_page_t m; 1398 int pflags, needed_lock; 1399 1400 *flags = UMA_SLAB_PRIV; 1401 needed_lock = !PMAP_LOCKED(kernel_pmap); 1402 1403 if (needed_lock) 1404 PMAP_LOCK(kernel_pmap); 1405 1406 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1407 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1408 else 1409 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1410 if (wait & M_ZERO) 1411 pflags |= VM_ALLOC_ZERO; 1412 1413 for (;;) { 1414 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1415 if (m == NULL) { 1416 if (wait & M_NOWAIT) 1417 return (NULL); 1418 VM_WAIT; 1419 } else 1420 break; 1421 } 1422 1423 va = pvo_allocator_start; 1424 pvo_allocator_start += PAGE_SIZE; 1425 1426 if (pvo_allocator_start >= pvo_allocator_end) 1427 panic("Ran out of PVO allocator buffer space!"); 1428 1429 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1430 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1431 PVO_WIRED | PVO_BOOTSTRAP); 1432 1433 TLBIE(kernel_pmap, va); 1434 1435 if (needed_lock) 1436 PMAP_UNLOCK(kernel_pmap); 1437 1438 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1439 bzero((void *)va, PAGE_SIZE); 1440 1441 return (void *)va; 1442 } 1443 1444 void 1445 moea64_init(mmu_t mmu) 1446 { 1447 1448 CTR0(KTR_PMAP, "moea64_init"); 1449 1450 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1451 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1452 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1453 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1454 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1455 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1456 1457 if (!hw_direct_map) { 1458 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1459 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1460 } 1461 1462 moea64_initialized = TRUE; 1463 } 1464 1465 boolean_t 1466 moea64_is_modified(mmu_t mmu, vm_page_t m) 1467 { 1468 1469 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1470 return (FALSE); 1471 1472 return (moea64_query_bit(m, LPTE_CHG)); 1473 } 1474 1475 void 1476 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1477 { 1478 1479 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1480 return; 1481 moea64_clear_bit(m, LPTE_REF, NULL); 1482 } 1483 1484 void 1485 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1486 { 1487 1488 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1489 return; 1490 moea64_clear_bit(m, LPTE_CHG, NULL); 1491 } 1492 1493 /* 1494 * Clear the write and modified bits in each of the given page's mappings. 1495 */ 1496 void 1497 moea64_remove_write(mmu_t mmu, vm_page_t m) 1498 { 1499 struct pvo_entry *pvo; 1500 struct lpte *pt; 1501 pmap_t pmap; 1502 uint64_t lo; 1503 1504 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1505 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1506 (m->flags & PG_WRITEABLE) == 0) 1507 return; 1508 lo = moea64_attr_fetch(m); 1509 SYNC(); 1510 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1511 pmap = pvo->pvo_pmap; 1512 PMAP_LOCK(pmap); 1513 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1514 LOCK_TABLE(); 1515 pt = moea64_pvo_to_pte(pvo, -1); 1516 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1517 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1518 if (pt != NULL) { 1519 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1520 lo |= pvo->pvo_pte.lpte.pte_lo; 1521 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1522 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1523 pvo->pvo_pmap, pvo->pvo_vaddr); 1524 } 1525 UNLOCK_TABLE(); 1526 } 1527 PMAP_UNLOCK(pmap); 1528 } 1529 if ((lo & LPTE_CHG) != 0) { 1530 moea64_attr_clear(m, LPTE_CHG); 1531 vm_page_dirty(m); 1532 } 1533 vm_page_flag_clear(m, PG_WRITEABLE); 1534 } 1535 1536 /* 1537 * moea64_ts_referenced: 1538 * 1539 * Return a count of reference bits for a page, clearing those bits. 1540 * It is not necessary for every reference bit to be cleared, but it 1541 * is necessary that 0 only be returned when there are truly no 1542 * reference bits set. 1543 * 1544 * XXX: The exact number of bits to check and clear is a matter that 1545 * should be tested and standardized at some point in the future for 1546 * optimal aging of shared pages. 1547 */ 1548 boolean_t 1549 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1550 { 1551 int count; 1552 1553 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1554 return (0); 1555 1556 count = moea64_clear_bit(m, LPTE_REF, NULL); 1557 1558 return (count); 1559 } 1560 1561 /* 1562 * Map a wired page into kernel virtual address space. 1563 */ 1564 void 1565 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1566 { 1567 uint64_t pte_lo; 1568 int error; 1569 1570 if (!pmap_bootstrapped) { 1571 if (va >= VM_MIN_KERNEL_ADDRESS && va < VM_MAX_KERNEL_ADDRESS) 1572 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1573 } 1574 1575 pte_lo = moea64_calc_wimg(pa); 1576 1577 PMAP_LOCK(kernel_pmap); 1578 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1579 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1580 PVO_WIRED | VM_PROT_EXECUTE); 1581 1582 TLBIE(kernel_pmap, va); 1583 1584 if (error != 0 && error != ENOENT) 1585 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1586 pa, error); 1587 1588 /* 1589 * Flush the memory from the instruction cache. 1590 */ 1591 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1592 __syncicache((void *)va, PAGE_SIZE); 1593 } 1594 PMAP_UNLOCK(kernel_pmap); 1595 } 1596 1597 /* 1598 * Extract the physical page address associated with the given kernel virtual 1599 * address. 1600 */ 1601 vm_offset_t 1602 moea64_kextract(mmu_t mmu, vm_offset_t va) 1603 { 1604 struct pvo_entry *pvo; 1605 vm_paddr_t pa; 1606 1607 PMAP_LOCK(kernel_pmap); 1608 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1609 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1610 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1611 PMAP_UNLOCK(kernel_pmap); 1612 return (pa); 1613 } 1614 1615 /* 1616 * Remove a wired page from kernel virtual address space. 1617 */ 1618 void 1619 moea64_kremove(mmu_t mmu, vm_offset_t va) 1620 { 1621 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1622 } 1623 1624 /* 1625 * Map a range of physical addresses into kernel virtual address space. 1626 * 1627 * The value passed in *virt is a suggested virtual address for the mapping. 1628 * Architectures which can support a direct-mapped physical to virtual region 1629 * can return the appropriate address within that region, leaving '*virt' 1630 * unchanged. We cannot and therefore do not; *virt is updated with the 1631 * first usable address after the mapped region. 1632 */ 1633 vm_offset_t 1634 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1635 vm_offset_t pa_end, int prot) 1636 { 1637 vm_offset_t sva, va; 1638 1639 sva = *virt; 1640 va = sva; 1641 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1642 moea64_kenter(mmu, va, pa_start); 1643 *virt = va; 1644 1645 return (sva); 1646 } 1647 1648 /* 1649 * Returns true if the pmap's pv is one of the first 1650 * 16 pvs linked to from this page. This count may 1651 * be changed upwards or downwards in the future; it 1652 * is only necessary that true be returned for a small 1653 * subset of pmaps for proper page aging. 1654 */ 1655 boolean_t 1656 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1657 { 1658 int loops; 1659 struct pvo_entry *pvo; 1660 1661 if (!moea64_initialized || (m->flags & PG_FICTITIOUS)) 1662 return FALSE; 1663 1664 loops = 0; 1665 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1666 if (pvo->pvo_pmap == pmap) 1667 return (TRUE); 1668 if (++loops >= 16) 1669 break; 1670 } 1671 1672 return (FALSE); 1673 } 1674 1675 /* 1676 * Return the number of managed mappings to the given physical page 1677 * that are wired. 1678 */ 1679 int 1680 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1681 { 1682 struct pvo_entry *pvo; 1683 int count; 1684 1685 count = 0; 1686 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0) 1687 return (count); 1688 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1689 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1690 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1691 count++; 1692 return (count); 1693 } 1694 1695 static u_int moea64_vsidcontext; 1696 1697 void 1698 moea64_pinit(mmu_t mmu, pmap_t pmap) 1699 { 1700 int i, mask; 1701 u_int entropy; 1702 1703 PMAP_LOCK_INIT(pmap); 1704 1705 entropy = 0; 1706 __asm __volatile("mftb %0" : "=r"(entropy)); 1707 1708 if (pmap_bootstrapped) 1709 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1710 else 1711 pmap->pmap_phys = pmap; 1712 1713 /* 1714 * Allocate some segment registers for this pmap. 1715 */ 1716 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1717 u_int hash, n; 1718 1719 /* 1720 * Create a new value by mutiplying by a prime and adding in 1721 * entropy from the timebase register. This is to make the 1722 * VSID more random so that the PT hash function collides 1723 * less often. (Note that the prime casues gcc to do shifts 1724 * instead of a multiply.) 1725 */ 1726 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1727 hash = moea64_vsidcontext & (NPMAPS - 1); 1728 if (hash == 0) /* 0 is special, avoid it */ 1729 continue; 1730 n = hash >> 5; 1731 mask = 1 << (hash & (VSID_NBPW - 1)); 1732 hash = (moea64_vsidcontext & 0xfffff); 1733 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1734 /* anything free in this bucket? */ 1735 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1736 entropy = (moea64_vsidcontext >> 20); 1737 continue; 1738 } 1739 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1740 mask = 1 << i; 1741 hash &= 0xfffff & ~(VSID_NBPW - 1); 1742 hash |= i; 1743 } 1744 moea64_vsid_bitmap[n] |= mask; 1745 for (i = 0; i < 16; i++) { 1746 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1747 } 1748 return; 1749 } 1750 1751 panic("moea64_pinit: out of segments"); 1752 } 1753 1754 /* 1755 * Initialize the pmap associated with process 0. 1756 */ 1757 void 1758 moea64_pinit0(mmu_t mmu, pmap_t pm) 1759 { 1760 moea64_pinit(mmu, pm); 1761 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1762 } 1763 1764 /* 1765 * Set the physical protection on the specified range of this map as requested. 1766 */ 1767 void 1768 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1769 vm_prot_t prot) 1770 { 1771 struct pvo_entry *pvo; 1772 struct lpte *pt; 1773 int pteidx; 1774 1775 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1776 eva, prot); 1777 1778 1779 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1780 ("moea64_protect: non current pmap")); 1781 1782 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1783 moea64_remove(mmu, pm, sva, eva); 1784 return; 1785 } 1786 1787 vm_page_lock_queues(); 1788 PMAP_LOCK(pm); 1789 for (; sva < eva; sva += PAGE_SIZE) { 1790 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1791 if (pvo == NULL) 1792 continue; 1793 1794 /* 1795 * Grab the PTE pointer before we diddle with the cached PTE 1796 * copy. 1797 */ 1798 LOCK_TABLE(); 1799 pt = moea64_pvo_to_pte(pvo, pteidx); 1800 1801 /* 1802 * Change the protection of the page. 1803 */ 1804 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1805 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1806 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1807 if ((prot & VM_PROT_EXECUTE) == 0) 1808 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1809 1810 /* 1811 * If the PVO is in the page table, update that pte as well. 1812 */ 1813 if (pt != NULL) { 1814 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1815 pvo->pvo_pmap, pvo->pvo_vaddr); 1816 if ((pvo->pvo_pte.lpte.pte_lo & 1817 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1818 moea64_syncicache(pm, sva, 1819 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1820 PAGE_SIZE); 1821 } 1822 } 1823 UNLOCK_TABLE(); 1824 } 1825 vm_page_unlock_queues(); 1826 PMAP_UNLOCK(pm); 1827 } 1828 1829 /* 1830 * Map a list of wired pages into kernel virtual address space. This is 1831 * intended for temporary mappings which do not need page modification or 1832 * references recorded. Existing mappings in the region are overwritten. 1833 */ 1834 void 1835 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1836 { 1837 while (count-- > 0) { 1838 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1839 va += PAGE_SIZE; 1840 m++; 1841 } 1842 } 1843 1844 /* 1845 * Remove page mappings from kernel virtual address space. Intended for 1846 * temporary mappings entered by moea64_qenter. 1847 */ 1848 void 1849 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1850 { 1851 while (count-- > 0) { 1852 moea64_kremove(mmu, va); 1853 va += PAGE_SIZE; 1854 } 1855 } 1856 1857 void 1858 moea64_release(mmu_t mmu, pmap_t pmap) 1859 { 1860 int idx, mask; 1861 1862 /* 1863 * Free segment register's VSID 1864 */ 1865 if (pmap->pm_sr[0] == 0) 1866 panic("moea64_release"); 1867 1868 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1869 mask = 1 << (idx % VSID_NBPW); 1870 idx /= VSID_NBPW; 1871 moea64_vsid_bitmap[idx] &= ~mask; 1872 PMAP_LOCK_DESTROY(pmap); 1873 } 1874 1875 /* 1876 * Remove the given range of addresses from the specified map. 1877 */ 1878 void 1879 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1880 { 1881 struct pvo_entry *pvo; 1882 int pteidx; 1883 1884 vm_page_lock_queues(); 1885 PMAP_LOCK(pm); 1886 for (; sva < eva; sva += PAGE_SIZE) { 1887 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1888 if (pvo != NULL) { 1889 moea64_pvo_remove(pvo, pteidx); 1890 } 1891 } 1892 vm_page_unlock_queues(); 1893 PMAP_UNLOCK(pm); 1894 } 1895 1896 /* 1897 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1898 * will reflect changes in pte's back to the vm_page. 1899 */ 1900 void 1901 moea64_remove_all(mmu_t mmu, vm_page_t m) 1902 { 1903 struct pvo_head *pvo_head; 1904 struct pvo_entry *pvo, *next_pvo; 1905 pmap_t pmap; 1906 1907 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1908 1909 pvo_head = vm_page_to_pvoh(m); 1910 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1911 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1912 1913 MOEA_PVO_CHECK(pvo); /* sanity check */ 1914 pmap = pvo->pvo_pmap; 1915 PMAP_LOCK(pmap); 1916 moea64_pvo_remove(pvo, -1); 1917 PMAP_UNLOCK(pmap); 1918 } 1919 vm_page_flag_clear(m, PG_WRITEABLE); 1920 } 1921 1922 /* 1923 * Allocate a physical page of memory directly from the phys_avail map. 1924 * Can only be called from moea64_bootstrap before avail start and end are 1925 * calculated. 1926 */ 1927 static vm_offset_t 1928 moea64_bootstrap_alloc(vm_size_t size, u_int align) 1929 { 1930 vm_offset_t s, e; 1931 int i, j; 1932 1933 size = round_page(size); 1934 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1935 if (align != 0) 1936 s = (phys_avail[i] + align - 1) & ~(align - 1); 1937 else 1938 s = phys_avail[i]; 1939 e = s + size; 1940 1941 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1942 continue; 1943 1944 if (s == phys_avail[i]) { 1945 phys_avail[i] += size; 1946 } else if (e == phys_avail[i + 1]) { 1947 phys_avail[i + 1] -= size; 1948 } else { 1949 for (j = phys_avail_count * 2; j > i; j -= 2) { 1950 phys_avail[j] = phys_avail[j - 2]; 1951 phys_avail[j + 1] = phys_avail[j - 1]; 1952 } 1953 1954 phys_avail[i + 3] = phys_avail[i + 1]; 1955 phys_avail[i + 1] = s; 1956 phys_avail[i + 2] = e; 1957 phys_avail_count++; 1958 } 1959 1960 return (s); 1961 } 1962 panic("moea64_bootstrap_alloc: could not allocate memory"); 1963 } 1964 1965 static void 1966 tlbia(void) 1967 { 1968 vm_offset_t i; 1969 register_t msr, scratch; 1970 1971 for (i = 0; i < 0xFF000; i += 0x00001000) { 1972 __asm __volatile("\ 1973 mfmsr %0; \ 1974 mr %1, %0; \ 1975 insrdi %1,%3,1,0; \ 1976 mtmsrd %1; \ 1977 ptesync; \ 1978 \ 1979 tlbiel %2; \ 1980 \ 1981 mtmsrd %0; \ 1982 eieio; \ 1983 tlbsync; \ 1984 ptesync;" 1985 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 1986 } 1987 } 1988 1989 static int 1990 moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1991 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 1992 { 1993 struct pvo_entry *pvo; 1994 uint64_t vsid; 1995 int first; 1996 u_int ptegidx; 1997 int i; 1998 int bootstrap; 1999 2000 /* 2001 * One nasty thing that can happen here is that the UMA calls to 2002 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2003 * which calls UMA... 2004 * 2005 * We break the loop by detecting recursion and allocating out of 2006 * the bootstrap pool. 2007 */ 2008 2009 moea64_pvo_enter_calls++; 2010 first = 0; 2011 bootstrap = (flags & PVO_BOOTSTRAP); 2012 2013 if (!moea64_initialized) 2014 bootstrap = 1; 2015 2016 /* 2017 * Compute the PTE Group index. 2018 */ 2019 va &= ~ADDR_POFF; 2020 vsid = va_to_vsid(pm, va); 2021 ptegidx = va_to_pteg(vsid, va); 2022 2023 /* 2024 * Remove any existing mapping for this page. Reuse the pvo entry if 2025 * there is a mapping. 2026 */ 2027 LOCK_TABLE(); 2028 2029 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2030 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2031 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2032 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2033 (pte_lo & LPTE_PP)) { 2034 UNLOCK_TABLE(); 2035 return (0); 2036 } 2037 moea64_pvo_remove(pvo, -1); 2038 break; 2039 } 2040 } 2041 2042 /* 2043 * If we aren't overwriting a mapping, try to allocate. 2044 */ 2045 if (bootstrap) { 2046 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2047 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2048 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2049 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2050 } 2051 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2052 moea64_bpvo_pool_index++; 2053 bootstrap = 1; 2054 } else { 2055 /* 2056 * Note: drop the table around the UMA allocation in 2057 * case the UMA allocator needs to manipulate the page 2058 * table. The mapping we are working with is already 2059 * protected by the PMAP lock. 2060 */ 2061 UNLOCK_TABLE(); 2062 pvo = uma_zalloc(zone, M_NOWAIT); 2063 LOCK_TABLE(); 2064 } 2065 2066 if (pvo == NULL) { 2067 UNLOCK_TABLE(); 2068 return (ENOMEM); 2069 } 2070 2071 moea64_pvo_entries++; 2072 pvo->pvo_vaddr = va; 2073 pvo->pvo_pmap = pm; 2074 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2075 pvo->pvo_vaddr &= ~ADDR_POFF; 2076 2077 if (!(flags & VM_PROT_EXECUTE)) 2078 pte_lo |= LPTE_NOEXEC; 2079 if (flags & PVO_WIRED) 2080 pvo->pvo_vaddr |= PVO_WIRED; 2081 if (pvo_head != &moea64_pvo_kunmanaged) 2082 pvo->pvo_vaddr |= PVO_MANAGED; 2083 if (bootstrap) 2084 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2085 if (flags & PVO_FAKE) 2086 pvo->pvo_vaddr |= PVO_FAKE; 2087 2088 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2089 (uint64_t)(pa) | pte_lo); 2090 2091 /* 2092 * Remember if the list was empty and therefore will be the first 2093 * item. 2094 */ 2095 if (LIST_FIRST(pvo_head) == NULL) 2096 first = 1; 2097 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2098 2099 if (pvo->pvo_pte.lpte.pte_lo & PVO_WIRED) 2100 pm->pm_stats.wired_count++; 2101 pm->pm_stats.resident_count++; 2102 2103 /* 2104 * We hope this succeeds but it isn't required. 2105 */ 2106 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2107 if (i >= 0) { 2108 PVO_PTEGIDX_SET(pvo, i); 2109 } else { 2110 panic("moea64_pvo_enter: overflow"); 2111 moea64_pte_overflow++; 2112 } 2113 2114 UNLOCK_TABLE(); 2115 2116 return (first ? ENOENT : 0); 2117 } 2118 2119 static void 2120 moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2121 { 2122 struct lpte *pt; 2123 2124 /* 2125 * If there is an active pte entry, we need to deactivate it (and 2126 * save the ref & cfg bits). 2127 */ 2128 LOCK_TABLE(); 2129 pt = moea64_pvo_to_pte(pvo, pteidx); 2130 if (pt != NULL) { 2131 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2132 pvo->pvo_vaddr); 2133 PVO_PTEGIDX_CLR(pvo); 2134 } else { 2135 moea64_pte_overflow--; 2136 } 2137 UNLOCK_TABLE(); 2138 2139 /* 2140 * Update our statistics. 2141 */ 2142 pvo->pvo_pmap->pm_stats.resident_count--; 2143 if (pvo->pvo_pte.lpte.pte_lo & PVO_WIRED) 2144 pvo->pvo_pmap->pm_stats.wired_count--; 2145 2146 /* 2147 * Save the REF/CHG bits into their cache if the page is managed. 2148 */ 2149 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2150 struct vm_page *pg; 2151 2152 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2153 if (pg != NULL) { 2154 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2155 (LPTE_REF | LPTE_CHG)); 2156 } 2157 } 2158 2159 /* 2160 * Remove this PVO from the PV list. 2161 */ 2162 LIST_REMOVE(pvo, pvo_vlink); 2163 2164 /* 2165 * Remove this from the overflow list and return it to the pool 2166 * if we aren't going to reuse it. 2167 */ 2168 LIST_REMOVE(pvo, pvo_olink); 2169 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2170 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea64_mpvo_zone : 2171 moea64_upvo_zone, pvo); 2172 moea64_pvo_entries--; 2173 moea64_pvo_remove_calls++; 2174 } 2175 2176 static __inline int 2177 moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2178 { 2179 int pteidx; 2180 2181 /* 2182 * We can find the actual pte entry without searching by grabbing 2183 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2184 * noticing the HID bit. 2185 */ 2186 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2187 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2188 pteidx ^= moea64_pteg_mask * 8; 2189 2190 return (pteidx); 2191 } 2192 2193 static struct pvo_entry * 2194 moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2195 { 2196 struct pvo_entry *pvo; 2197 int ptegidx; 2198 uint64_t vsid; 2199 2200 va &= ~ADDR_POFF; 2201 vsid = va_to_vsid(pm, va); 2202 ptegidx = va_to_pteg(vsid, va); 2203 2204 LOCK_TABLE(); 2205 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2206 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2207 if (pteidx_p) 2208 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2209 break; 2210 } 2211 } 2212 UNLOCK_TABLE(); 2213 2214 return (pvo); 2215 } 2216 2217 static struct lpte * 2218 moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2219 { 2220 struct lpte *pt; 2221 2222 /* 2223 * If we haven't been supplied the ptegidx, calculate it. 2224 */ 2225 if (pteidx == -1) { 2226 int ptegidx; 2227 uint64_t vsid; 2228 2229 vsid = va_to_vsid(pvo->pvo_pmap, pvo->pvo_vaddr); 2230 ptegidx = va_to_pteg(vsid, pvo->pvo_vaddr); 2231 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2232 } 2233 2234 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2235 2236 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2237 !PVO_PTEGIDX_ISSET(pvo)) { 2238 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2239 "valid pte index", pvo); 2240 } 2241 2242 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2243 PVO_PTEGIDX_ISSET(pvo)) { 2244 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2245 "pvo but no valid pte", pvo); 2246 } 2247 2248 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2249 LPTE_VALID) { 2250 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2251 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2252 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2253 } 2254 2255 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2256 ~(LPTE_CHG|LPTE_REF)) != 0) { 2257 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2258 "pte %p in moea64_pteg_table difference is %#x", 2259 pvo, pt, 2260 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2261 } 2262 2263 ASSERT_TABLE_LOCK(); 2264 return (pt); 2265 } 2266 2267 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2268 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2269 "moea64_pteg_table but valid in pvo", pvo, pt); 2270 } 2271 2272 return (NULL); 2273 } 2274 2275 static int 2276 moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2277 { 2278 struct lpte *pt; 2279 int i; 2280 2281 ASSERT_TABLE_LOCK(); 2282 2283 /* 2284 * First try primary hash. 2285 */ 2286 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2287 if ((pt->pte_hi & LPTE_VALID) == 0) { 2288 pvo_pt->pte_hi &= ~LPTE_HID; 2289 moea64_pte_set(pt, pvo_pt); 2290 return (i); 2291 } 2292 } 2293 2294 /* 2295 * Now try secondary hash. 2296 */ 2297 ptegidx ^= moea64_pteg_mask; 2298 2299 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2300 if ((pt->pte_hi & LPTE_VALID) == 0) { 2301 pvo_pt->pte_hi |= LPTE_HID; 2302 moea64_pte_set(pt, pvo_pt); 2303 return (i); 2304 } 2305 } 2306 2307 panic("moea64_pte_insert: overflow"); 2308 return (-1); 2309 } 2310 2311 static boolean_t 2312 moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2313 { 2314 struct pvo_entry *pvo; 2315 struct lpte *pt; 2316 2317 #if 0 2318 if (moea64_attr_fetch(m) & ptebit) 2319 return (TRUE); 2320 #endif 2321 2322 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2323 MOEA_PVO_CHECK(pvo); /* sanity check */ 2324 2325 /* 2326 * See if we saved the bit off. If so, cache it and return 2327 * success. 2328 */ 2329 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2330 moea64_attr_save(m, ptebit); 2331 MOEA_PVO_CHECK(pvo); /* sanity check */ 2332 return (TRUE); 2333 } 2334 } 2335 2336 /* 2337 * No luck, now go through the hard part of looking at the PTEs 2338 * themselves. Sync so that any pending REF/CHG bits are flushed to 2339 * the PTEs. 2340 */ 2341 SYNC(); 2342 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2343 MOEA_PVO_CHECK(pvo); /* sanity check */ 2344 2345 /* 2346 * See if this pvo has a valid PTE. if so, fetch the 2347 * REF/CHG bits from the valid PTE. If the appropriate 2348 * ptebit is set, cache it and return success. 2349 */ 2350 LOCK_TABLE(); 2351 pt = moea64_pvo_to_pte(pvo, -1); 2352 if (pt != NULL) { 2353 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2354 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2355 UNLOCK_TABLE(); 2356 2357 moea64_attr_save(m, ptebit); 2358 MOEA_PVO_CHECK(pvo); /* sanity check */ 2359 return (TRUE); 2360 } 2361 } 2362 UNLOCK_TABLE(); 2363 } 2364 2365 return (FALSE); 2366 } 2367 2368 static u_int 2369 moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit) 2370 { 2371 u_int count; 2372 struct pvo_entry *pvo; 2373 struct lpte *pt; 2374 uint64_t rv; 2375 2376 /* 2377 * Clear the cached value. 2378 */ 2379 rv = moea64_attr_fetch(m); 2380 moea64_attr_clear(m, ptebit); 2381 2382 /* 2383 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2384 * we can reset the right ones). note that since the pvo entries and 2385 * list heads are accessed via BAT0 and are never placed in the page 2386 * table, we don't have to worry about further accesses setting the 2387 * REF/CHG bits. 2388 */ 2389 SYNC(); 2390 2391 /* 2392 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2393 * valid pte clear the ptebit from the valid pte. 2394 */ 2395 count = 0; 2396 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2397 MOEA_PVO_CHECK(pvo); /* sanity check */ 2398 2399 LOCK_TABLE(); 2400 pt = moea64_pvo_to_pte(pvo, -1); 2401 if (pt != NULL) { 2402 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2403 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2404 count++; 2405 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2406 } 2407 } 2408 UNLOCK_TABLE(); 2409 rv |= pvo->pvo_pte.lpte.pte_lo; 2410 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2411 MOEA_PVO_CHECK(pvo); /* sanity check */ 2412 } 2413 2414 if (origbit != NULL) { 2415 *origbit = rv; 2416 } 2417 2418 return (count); 2419 } 2420 2421 boolean_t 2422 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2423 { 2424 return (EFAULT); 2425 } 2426 2427 /* 2428 * Map a set of physical memory pages into the kernel virtual 2429 * address space. Return a pointer to where it is mapped. This 2430 * routine is intended to be used for mapping device memory, 2431 * NOT real memory. 2432 */ 2433 void * 2434 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2435 { 2436 vm_offset_t va, tmpva, ppa, offset; 2437 2438 ppa = trunc_page(pa); 2439 offset = pa & PAGE_MASK; 2440 size = roundup(offset + size, PAGE_SIZE); 2441 2442 va = kmem_alloc_nofault(kernel_map, size); 2443 2444 if (!va) 2445 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2446 2447 for (tmpva = va; size > 0;) { 2448 moea64_kenter(mmu, tmpva, ppa); 2449 size -= PAGE_SIZE; 2450 tmpva += PAGE_SIZE; 2451 ppa += PAGE_SIZE; 2452 } 2453 2454 return ((void *)(va + offset)); 2455 } 2456 2457 void 2458 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2459 { 2460 vm_offset_t base, offset; 2461 2462 base = trunc_page(va); 2463 offset = va & PAGE_MASK; 2464 size = roundup(offset + size, PAGE_SIZE); 2465 2466 kmem_free(kernel_map, base, size); 2467 } 2468 2469 static void 2470 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2471 { 2472 struct pvo_entry *pvo; 2473 vm_offset_t lim; 2474 vm_paddr_t pa; 2475 vm_size_t len; 2476 2477 PMAP_LOCK(pm); 2478 while (sz > 0) { 2479 lim = round_page(va); 2480 len = MIN(lim - va, sz); 2481 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2482 if (pvo != NULL) { 2483 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2484 (va & ADDR_POFF); 2485 moea64_syncicache(pm, va, pa, len); 2486 } 2487 va += len; 2488 sz -= len; 2489 } 2490 PMAP_UNLOCK(pm); 2491 } 2492