1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 #include <sys/reboot.h> 69 70 #include <sys/kdb.h> 71 72 #include <dev/ofw/openfirm.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_kern.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_phys.h> 79 #include <vm/vm_map.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_extern.h> 82 #include <vm/vm_pageout.h> 83 #include <vm/uma.h> 84 85 #include <machine/_inttypes.h> 86 #include <machine/cpu.h> 87 #include <machine/ifunc.h> 88 #include <machine/platform.h> 89 #include <machine/frame.h> 90 #include <machine/md_var.h> 91 #include <machine/psl.h> 92 #include <machine/bat.h> 93 #include <machine/hid.h> 94 #include <machine/pte.h> 95 #include <machine/sr.h> 96 #include <machine/trap.h> 97 #include <machine/mmuvar.h> 98 99 #include "mmu_oea64.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_COUNT PA_LOCK_COUNT 123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 124 125 /* 126 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 127 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 128 * index at (N << 45). 129 */ 130 #ifdef __powerpc64__ 131 #define PV_LOCK_IDX(pa) ((pa_index(pa) * (((pa) >> 45) + 1)) % PV_LOCK_COUNT) 132 #else 133 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 134 #endif 135 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 136 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 137 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 138 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 139 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 140 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 141 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 142 143 struct ofw_map { 144 cell_t om_va; 145 cell_t om_len; 146 uint64_t om_pa; 147 cell_t om_mode; 148 }; 149 150 extern unsigned char _etext[]; 151 extern unsigned char _end[]; 152 153 extern void *slbtrap, *slbtrapend; 154 155 /* 156 * Map of physical memory regions. 157 */ 158 static struct mem_region *regions; 159 static struct mem_region *pregions; 160 static struct numa_mem_region *numa_pregions; 161 static u_int phys_avail_count; 162 static int regions_sz, pregions_sz, numapregions_sz; 163 164 extern void bs_remap_earlyboot(void); 165 166 /* 167 * Lock for the SLB tables. 168 */ 169 struct mtx moea64_slb_mutex; 170 171 /* 172 * PTEG data. 173 */ 174 u_long moea64_pteg_count; 175 u_long moea64_pteg_mask; 176 177 /* 178 * PVO data. 179 */ 180 181 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 182 183 static struct pvo_entry *moea64_bpvo_pool; 184 static int moea64_bpvo_pool_index = 0; 185 static int moea64_bpvo_pool_size = 0; 186 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 187 &moea64_bpvo_pool_index, 0, ""); 188 189 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */ 190 #define BPVO_POOL_EXPANSION_FACTOR 3 191 #define VSID_NBPW (sizeof(u_int32_t) * 8) 192 #ifdef __powerpc64__ 193 #define NVSIDS (NPMAPS * 16) 194 #define VSID_HASHMASK 0xffffffffUL 195 #else 196 #define NVSIDS NPMAPS 197 #define VSID_HASHMASK 0xfffffUL 198 #endif 199 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 200 201 static boolean_t moea64_initialized = FALSE; 202 203 #ifdef MOEA64_STATS 204 /* 205 * Statistics. 206 */ 207 u_int moea64_pte_valid = 0; 208 u_int moea64_pte_overflow = 0; 209 u_int moea64_pvo_entries = 0; 210 u_int moea64_pvo_enter_calls = 0; 211 u_int moea64_pvo_remove_calls = 0; 212 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 213 &moea64_pte_valid, 0, ""); 214 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 215 &moea64_pte_overflow, 0, ""); 216 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 217 &moea64_pvo_entries, 0, ""); 218 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 219 &moea64_pvo_enter_calls, 0, ""); 220 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 221 &moea64_pvo_remove_calls, 0, ""); 222 #endif 223 224 vm_offset_t moea64_scratchpage_va[2]; 225 struct pvo_entry *moea64_scratchpage_pvo[2]; 226 struct mtx moea64_scratchpage_mtx; 227 228 uint64_t moea64_large_page_mask = 0; 229 uint64_t moea64_large_page_size = 0; 230 int moea64_large_page_shift = 0; 231 232 /* 233 * PVO calls. 234 */ 235 static int moea64_pvo_enter(struct pvo_entry *pvo, 236 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 237 static void moea64_pvo_remove_from_pmap(struct pvo_entry *pvo); 238 static void moea64_pvo_remove_from_page(struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page_locked( 240 struct pvo_entry *pvo, vm_page_t m); 241 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 242 243 /* 244 * Utility routines. 245 */ 246 static boolean_t moea64_query_bit(vm_page_t, uint64_t); 247 static u_int moea64_clear_bit(vm_page_t, uint64_t); 248 static void moea64_kremove(vm_offset_t); 249 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 250 vm_paddr_t pa, vm_size_t sz); 251 static void moea64_pmap_init_qpages(void); 252 253 /* 254 * Kernel MMU interface 255 */ 256 void moea64_clear_modify(vm_page_t); 257 void moea64_copy_page(vm_page_t, vm_page_t); 258 void moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 259 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 260 int moea64_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 261 u_int flags, int8_t psind); 262 void moea64_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 263 vm_prot_t); 264 void moea64_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 265 vm_paddr_t moea64_extract(pmap_t, vm_offset_t); 266 vm_page_t moea64_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 267 void moea64_init(void); 268 boolean_t moea64_is_modified(vm_page_t); 269 boolean_t moea64_is_prefaultable(pmap_t, vm_offset_t); 270 boolean_t moea64_is_referenced(vm_page_t); 271 int moea64_ts_referenced(vm_page_t); 272 vm_offset_t moea64_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 273 boolean_t moea64_page_exists_quick(pmap_t, vm_page_t); 274 void moea64_page_init(vm_page_t); 275 int moea64_page_wired_mappings(vm_page_t); 276 int moea64_pinit(pmap_t); 277 void moea64_pinit0(pmap_t); 278 void moea64_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 279 void moea64_qenter(vm_offset_t, vm_page_t *, int); 280 void moea64_qremove(vm_offset_t, int); 281 void moea64_release(pmap_t); 282 void moea64_remove(pmap_t, vm_offset_t, vm_offset_t); 283 void moea64_remove_pages(pmap_t); 284 void moea64_remove_all(vm_page_t); 285 void moea64_remove_write(vm_page_t); 286 void moea64_unwire(pmap_t, vm_offset_t, vm_offset_t); 287 void moea64_zero_page(vm_page_t); 288 void moea64_zero_page_area(vm_page_t, int, int); 289 void moea64_activate(struct thread *); 290 void moea64_deactivate(struct thread *); 291 void *moea64_mapdev(vm_paddr_t, vm_size_t); 292 void *moea64_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 293 void moea64_unmapdev(vm_offset_t, vm_size_t); 294 vm_paddr_t moea64_kextract(vm_offset_t); 295 void moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma); 296 void moea64_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t ma); 297 void moea64_kenter(vm_offset_t, vm_paddr_t); 298 boolean_t moea64_dev_direct_mapped(vm_paddr_t, vm_size_t); 299 static void moea64_sync_icache(pmap_t, vm_offset_t, vm_size_t); 300 void moea64_dumpsys_map(vm_paddr_t pa, size_t sz, 301 void **va); 302 void moea64_scan_init(void); 303 vm_offset_t moea64_quick_enter_page(vm_page_t m); 304 void moea64_quick_remove_page(vm_offset_t addr); 305 boolean_t moea64_page_is_mapped(vm_page_t m); 306 static int moea64_map_user_ptr(pmap_t pm, 307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 308 static int moea64_decode_kernel_ptr(vm_offset_t addr, 309 int *is_user, vm_offset_t *decoded_addr); 310 static size_t moea64_scan_pmap(void); 311 static void *moea64_dump_pmap_init(unsigned blkpgs); 312 #ifdef __powerpc64__ 313 static void moea64_page_array_startup(long); 314 #endif 315 316 317 static struct pmap_funcs moea64_methods = { 318 .clear_modify = moea64_clear_modify, 319 .copy_page = moea64_copy_page, 320 .copy_pages = moea64_copy_pages, 321 .enter = moea64_enter, 322 .enter_object = moea64_enter_object, 323 .enter_quick = moea64_enter_quick, 324 .extract = moea64_extract, 325 .extract_and_hold = moea64_extract_and_hold, 326 .init = moea64_init, 327 .is_modified = moea64_is_modified, 328 .is_prefaultable = moea64_is_prefaultable, 329 .is_referenced = moea64_is_referenced, 330 .ts_referenced = moea64_ts_referenced, 331 .map = moea64_map, 332 .page_exists_quick = moea64_page_exists_quick, 333 .page_init = moea64_page_init, 334 .page_wired_mappings = moea64_page_wired_mappings, 335 .pinit = moea64_pinit, 336 .pinit0 = moea64_pinit0, 337 .protect = moea64_protect, 338 .qenter = moea64_qenter, 339 .qremove = moea64_qremove, 340 .release = moea64_release, 341 .remove = moea64_remove, 342 .remove_pages = moea64_remove_pages, 343 .remove_all = moea64_remove_all, 344 .remove_write = moea64_remove_write, 345 .sync_icache = moea64_sync_icache, 346 .unwire = moea64_unwire, 347 .zero_page = moea64_zero_page, 348 .zero_page_area = moea64_zero_page_area, 349 .activate = moea64_activate, 350 .deactivate = moea64_deactivate, 351 .page_set_memattr = moea64_page_set_memattr, 352 .quick_enter_page = moea64_quick_enter_page, 353 .quick_remove_page = moea64_quick_remove_page, 354 .page_is_mapped = moea64_page_is_mapped, 355 #ifdef __powerpc64__ 356 .page_array_startup = moea64_page_array_startup, 357 #endif 358 359 /* Internal interfaces */ 360 .mapdev = moea64_mapdev, 361 .mapdev_attr = moea64_mapdev_attr, 362 .unmapdev = moea64_unmapdev, 363 .kextract = moea64_kextract, 364 .kenter = moea64_kenter, 365 .kenter_attr = moea64_kenter_attr, 366 .dev_direct_mapped = moea64_dev_direct_mapped, 367 .dumpsys_pa_init = moea64_scan_init, 368 .dumpsys_scan_pmap = moea64_scan_pmap, 369 .dumpsys_dump_pmap_init = moea64_dump_pmap_init, 370 .dumpsys_map_chunk = moea64_dumpsys_map, 371 .map_user_ptr = moea64_map_user_ptr, 372 .decode_kernel_ptr = moea64_decode_kernel_ptr, 373 }; 374 375 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods); 376 377 static struct pvo_head * 378 vm_page_to_pvoh(vm_page_t m) 379 { 380 381 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 382 return (&m->md.mdpg_pvoh); 383 } 384 385 static struct pvo_entry * 386 alloc_pvo_entry(int bootstrap) 387 { 388 struct pvo_entry *pvo; 389 390 if (!moea64_initialized || bootstrap) { 391 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 392 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 393 "Try setting machdep.moea64_bpvo_pool_size tunable", 394 __func__, moea64_bpvo_pool_index, 395 moea64_bpvo_pool_size, 396 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 397 } 398 pvo = &moea64_bpvo_pool[ 399 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 400 bzero(pvo, sizeof(*pvo)); 401 pvo->pvo_vaddr = PVO_BOOTSTRAP; 402 } else 403 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 404 405 return (pvo); 406 } 407 408 409 static void 410 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 411 { 412 uint64_t vsid; 413 uint64_t hash; 414 int shift; 415 416 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 417 418 pvo->pvo_pmap = pmap; 419 va &= ~ADDR_POFF; 420 pvo->pvo_vaddr |= va; 421 vsid = va_to_vsid(pmap, va); 422 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 423 | (vsid << 16); 424 425 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 426 ADDR_PIDX_SHFT; 427 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 428 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 429 } 430 431 static void 432 free_pvo_entry(struct pvo_entry *pvo) 433 { 434 435 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 436 uma_zfree(moea64_pvo_zone, pvo); 437 } 438 439 void 440 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 441 { 442 443 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 444 lpte->pte_hi |= LPTE_VALID; 445 446 if (pvo->pvo_vaddr & PVO_LARGE) 447 lpte->pte_hi |= LPTE_BIG; 448 if (pvo->pvo_vaddr & PVO_WIRED) 449 lpte->pte_hi |= LPTE_WIRED; 450 if (pvo->pvo_vaddr & PVO_HID) 451 lpte->pte_hi |= LPTE_HID; 452 453 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 454 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 455 lpte->pte_lo |= LPTE_BW; 456 else 457 lpte->pte_lo |= LPTE_BR; 458 459 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 460 lpte->pte_lo |= LPTE_NOEXEC; 461 } 462 463 static __inline uint64_t 464 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 465 { 466 uint64_t pte_lo; 467 int i; 468 469 if (ma != VM_MEMATTR_DEFAULT) { 470 switch (ma) { 471 case VM_MEMATTR_UNCACHEABLE: 472 return (LPTE_I | LPTE_G); 473 case VM_MEMATTR_CACHEABLE: 474 return (LPTE_M); 475 case VM_MEMATTR_WRITE_COMBINING: 476 case VM_MEMATTR_WRITE_BACK: 477 case VM_MEMATTR_PREFETCHABLE: 478 return (LPTE_I); 479 case VM_MEMATTR_WRITE_THROUGH: 480 return (LPTE_W | LPTE_M); 481 } 482 } 483 484 /* 485 * Assume the page is cache inhibited and access is guarded unless 486 * it's in our available memory array. 487 */ 488 pte_lo = LPTE_I | LPTE_G; 489 for (i = 0; i < pregions_sz; i++) { 490 if ((pa >= pregions[i].mr_start) && 491 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 492 pte_lo &= ~(LPTE_I | LPTE_G); 493 pte_lo |= LPTE_M; 494 break; 495 } 496 } 497 498 return pte_lo; 499 } 500 501 /* 502 * Quick sort callout for comparing memory regions. 503 */ 504 static int om_cmp(const void *a, const void *b); 505 506 static int 507 om_cmp(const void *a, const void *b) 508 { 509 const struct ofw_map *mapa; 510 const struct ofw_map *mapb; 511 512 mapa = a; 513 mapb = b; 514 if (mapa->om_pa < mapb->om_pa) 515 return (-1); 516 else if (mapa->om_pa > mapb->om_pa) 517 return (1); 518 else 519 return (0); 520 } 521 522 static void 523 moea64_add_ofw_mappings(phandle_t mmu, size_t sz) 524 { 525 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 526 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 527 struct pvo_entry *pvo; 528 register_t msr; 529 vm_offset_t off; 530 vm_paddr_t pa_base; 531 int i, j; 532 533 bzero(translations, sz); 534 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 535 sizeof(acells)); 536 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 537 panic("moea64_bootstrap: can't get ofw translations"); 538 539 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 540 sz /= sizeof(cell_t); 541 for (i = 0, j = 0; i < sz; j++) { 542 translations[j].om_va = trans_cells[i++]; 543 translations[j].om_len = trans_cells[i++]; 544 translations[j].om_pa = trans_cells[i++]; 545 if (acells == 2) { 546 translations[j].om_pa <<= 32; 547 translations[j].om_pa |= trans_cells[i++]; 548 } 549 translations[j].om_mode = trans_cells[i++]; 550 } 551 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 552 i, sz)); 553 554 sz = j; 555 qsort(translations, sz, sizeof (*translations), om_cmp); 556 557 for (i = 0; i < sz; i++) { 558 pa_base = translations[i].om_pa; 559 #ifndef __powerpc64__ 560 if ((translations[i].om_pa >> 32) != 0) 561 panic("OFW translations above 32-bit boundary!"); 562 #endif 563 564 if (pa_base % PAGE_SIZE) 565 panic("OFW translation not page-aligned (phys)!"); 566 if (translations[i].om_va % PAGE_SIZE) 567 panic("OFW translation not page-aligned (virt)!"); 568 569 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 570 pa_base, translations[i].om_va, translations[i].om_len); 571 572 /* Now enter the pages for this mapping */ 573 574 DISABLE_TRANS(msr); 575 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 576 /* If this address is direct-mapped, skip remapping */ 577 if (hw_direct_map && 578 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 579 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 580 == LPTE_M) 581 continue; 582 583 PMAP_LOCK(kernel_pmap); 584 pvo = moea64_pvo_find_va(kernel_pmap, 585 translations[i].om_va + off); 586 PMAP_UNLOCK(kernel_pmap); 587 if (pvo != NULL) 588 continue; 589 590 moea64_kenter(translations[i].om_va + off, 591 pa_base + off); 592 } 593 ENABLE_TRANS(msr); 594 } 595 } 596 597 #ifdef __powerpc64__ 598 static void 599 moea64_probe_large_page(void) 600 { 601 uint16_t pvr = mfpvr() >> 16; 602 603 switch (pvr) { 604 case IBM970: 605 case IBM970FX: 606 case IBM970MP: 607 powerpc_sync(); isync(); 608 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 609 powerpc_sync(); isync(); 610 611 /* FALLTHROUGH */ 612 default: 613 if (moea64_large_page_size == 0) { 614 moea64_large_page_size = 0x1000000; /* 16 MB */ 615 moea64_large_page_shift = 24; 616 } 617 } 618 619 moea64_large_page_mask = moea64_large_page_size - 1; 620 } 621 622 static void 623 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 624 { 625 struct slb *cache; 626 struct slb entry; 627 uint64_t esid, slbe; 628 uint64_t i; 629 630 cache = PCPU_GET(aim.slb); 631 esid = va >> ADDR_SR_SHFT; 632 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 633 634 for (i = 0; i < 64; i++) { 635 if (cache[i].slbe == (slbe | i)) 636 return; 637 } 638 639 entry.slbe = slbe; 640 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 641 if (large) 642 entry.slbv |= SLBV_L; 643 644 slb_insert_kernel(entry.slbe, entry.slbv); 645 } 646 #endif 647 648 static int 649 moea64_kenter_large(vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 650 { 651 struct pvo_entry *pvo; 652 uint64_t pte_lo; 653 int error; 654 655 pte_lo = LPTE_M; 656 pte_lo |= attr; 657 658 pvo = alloc_pvo_entry(bootstrap); 659 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 660 init_pvo_entry(pvo, kernel_pmap, va); 661 662 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 663 VM_PROT_EXECUTE; 664 pvo->pvo_pte.pa = pa | pte_lo; 665 error = moea64_pvo_enter(pvo, NULL, NULL); 666 if (error != 0) 667 panic("Error %d inserting large page\n", error); 668 return (0); 669 } 670 671 static void 672 moea64_setup_direct_map(vm_offset_t kernelstart, 673 vm_offset_t kernelend) 674 { 675 register_t msr; 676 vm_paddr_t pa, pkernelstart, pkernelend; 677 vm_offset_t size, off; 678 uint64_t pte_lo; 679 int i; 680 681 if (moea64_large_page_size == 0) 682 hw_direct_map = 0; 683 684 DISABLE_TRANS(msr); 685 if (hw_direct_map) { 686 PMAP_LOCK(kernel_pmap); 687 for (i = 0; i < pregions_sz; i++) { 688 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 689 pregions[i].mr_size; pa += moea64_large_page_size) { 690 pte_lo = LPTE_M; 691 if (pa & moea64_large_page_mask) { 692 pa &= moea64_large_page_mask; 693 pte_lo |= LPTE_G; 694 } 695 if (pa + moea64_large_page_size > 696 pregions[i].mr_start + pregions[i].mr_size) 697 pte_lo |= LPTE_G; 698 699 moea64_kenter_large(PHYS_TO_DMAP(pa), pa, pte_lo, 1); 700 } 701 } 702 PMAP_UNLOCK(kernel_pmap); 703 } 704 705 /* 706 * Make sure the kernel and BPVO pool stay mapped on systems either 707 * without a direct map or on which the kernel is not already executing 708 * out of the direct-mapped region. 709 */ 710 if (kernelstart < DMAP_BASE_ADDRESS) { 711 /* 712 * For pre-dmap execution, we need to use identity mapping 713 * because we will be operating with the mmu on but in the 714 * wrong address configuration until we __restartkernel(). 715 */ 716 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 717 pa += PAGE_SIZE) 718 moea64_kenter(pa, pa); 719 } else if (!hw_direct_map) { 720 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 721 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 722 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 723 pa += PAGE_SIZE) 724 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 725 } 726 727 if (!hw_direct_map) { 728 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 729 off = (vm_offset_t)(moea64_bpvo_pool); 730 for (pa = off; pa < off + size; pa += PAGE_SIZE) 731 moea64_kenter(pa, pa); 732 733 /* Map exception vectors */ 734 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 735 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 736 } 737 ENABLE_TRANS(msr); 738 739 /* 740 * Allow user to override unmapped_buf_allowed for testing. 741 * XXXKIB Only direct map implementation was tested. 742 */ 743 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 744 &unmapped_buf_allowed)) 745 unmapped_buf_allowed = hw_direct_map; 746 } 747 748 /* Quick sort callout for comparing physical addresses. */ 749 static int 750 pa_cmp(const void *a, const void *b) 751 { 752 const vm_paddr_t *pa = a, *pb = b; 753 754 if (*pa < *pb) 755 return (-1); 756 else if (*pa > *pb) 757 return (1); 758 else 759 return (0); 760 } 761 762 void 763 moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 764 { 765 int i, j; 766 vm_size_t physsz, hwphyssz; 767 vm_paddr_t kernelphysstart, kernelphysend; 768 int rm_pavail; 769 770 #ifndef __powerpc64__ 771 /* We don't have a direct map since there is no BAT */ 772 hw_direct_map = 0; 773 774 /* Make sure battable is zero, since we have no BAT */ 775 for (i = 0; i < 16; i++) { 776 battable[i].batu = 0; 777 battable[i].batl = 0; 778 } 779 #else 780 moea64_probe_large_page(); 781 782 /* Use a direct map if we have large page support */ 783 if (moea64_large_page_size > 0) 784 hw_direct_map = 1; 785 else 786 hw_direct_map = 0; 787 788 /* Install trap handlers for SLBs */ 789 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 790 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 791 __syncicache((void *)EXC_DSE, 0x80); 792 __syncicache((void *)EXC_ISE, 0x80); 793 #endif 794 795 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 796 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 797 798 /* Get physical memory regions from firmware */ 799 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 800 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 801 802 if (PHYS_AVAIL_ENTRIES < regions_sz) 803 panic("moea64_bootstrap: phys_avail too small"); 804 805 phys_avail_count = 0; 806 physsz = 0; 807 hwphyssz = 0; 808 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 809 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 810 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 811 regions[i].mr_start, regions[i].mr_start + 812 regions[i].mr_size, regions[i].mr_size); 813 if (hwphyssz != 0 && 814 (physsz + regions[i].mr_size) >= hwphyssz) { 815 if (physsz < hwphyssz) { 816 phys_avail[j] = regions[i].mr_start; 817 phys_avail[j + 1] = regions[i].mr_start + 818 hwphyssz - physsz; 819 physsz = hwphyssz; 820 phys_avail_count++; 821 dump_avail[j] = phys_avail[j]; 822 dump_avail[j + 1] = phys_avail[j + 1]; 823 } 824 break; 825 } 826 phys_avail[j] = regions[i].mr_start; 827 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 828 phys_avail_count++; 829 physsz += regions[i].mr_size; 830 dump_avail[j] = phys_avail[j]; 831 dump_avail[j + 1] = phys_avail[j + 1]; 832 } 833 834 /* Check for overlap with the kernel and exception vectors */ 835 rm_pavail = 0; 836 for (j = 0; j < 2*phys_avail_count; j+=2) { 837 if (phys_avail[j] < EXC_LAST) 838 phys_avail[j] += EXC_LAST; 839 840 if (phys_avail[j] >= kernelphysstart && 841 phys_avail[j+1] <= kernelphysend) { 842 phys_avail[j] = phys_avail[j+1] = ~0; 843 rm_pavail++; 844 continue; 845 } 846 847 if (kernelphysstart >= phys_avail[j] && 848 kernelphysstart < phys_avail[j+1]) { 849 if (kernelphysend < phys_avail[j+1]) { 850 phys_avail[2*phys_avail_count] = 851 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 852 phys_avail[2*phys_avail_count + 1] = 853 phys_avail[j+1]; 854 phys_avail_count++; 855 } 856 857 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 858 } 859 860 if (kernelphysend >= phys_avail[j] && 861 kernelphysend < phys_avail[j+1]) { 862 if (kernelphysstart > phys_avail[j]) { 863 phys_avail[2*phys_avail_count] = phys_avail[j]; 864 phys_avail[2*phys_avail_count + 1] = 865 kernelphysstart & ~PAGE_MASK; 866 phys_avail_count++; 867 } 868 869 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 870 PAGE_SIZE; 871 } 872 } 873 874 /* Remove physical available regions marked for removal (~0) */ 875 if (rm_pavail) { 876 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 877 pa_cmp); 878 phys_avail_count -= rm_pavail; 879 for (i = 2*phys_avail_count; 880 i < 2*(phys_avail_count + rm_pavail); i+=2) 881 phys_avail[i] = phys_avail[i+1] = 0; 882 } 883 884 physmem = btoc(physsz); 885 886 #ifdef PTEGCOUNT 887 moea64_pteg_count = PTEGCOUNT; 888 #else 889 moea64_pteg_count = 0x1000; 890 891 while (moea64_pteg_count < physmem) 892 moea64_pteg_count <<= 1; 893 894 moea64_pteg_count >>= 1; 895 #endif /* PTEGCOUNT */ 896 } 897 898 void 899 moea64_mid_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 900 { 901 int i; 902 903 /* 904 * Set PTEG mask 905 */ 906 moea64_pteg_mask = moea64_pteg_count - 1; 907 908 /* 909 * Initialize SLB table lock and page locks 910 */ 911 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 912 for (i = 0; i < PV_LOCK_COUNT; i++) 913 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 914 915 /* 916 * Initialise the bootstrap pvo pool. 917 */ 918 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 919 if (moea64_bpvo_pool_size == 0) { 920 if (!hw_direct_map) 921 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) / 922 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR; 923 else 924 moea64_bpvo_pool_size = BPVO_POOL_SIZE; 925 } 926 927 if (boothowto & RB_VERBOSE) { 928 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n", 929 moea64_bpvo_pool_size, 930 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576); 931 } 932 933 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 934 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 935 moea64_bpvo_pool_index = 0; 936 937 /* Place at address usable through the direct map */ 938 if (hw_direct_map) 939 moea64_bpvo_pool = (struct pvo_entry *) 940 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 941 942 /* 943 * Make sure kernel vsid is allocated as well as VSID 0. 944 */ 945 #ifndef __powerpc64__ 946 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 947 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 948 moea64_vsid_bitmap[0] |= 1; 949 #endif 950 951 /* 952 * Initialize the kernel pmap (which is statically allocated). 953 */ 954 #ifdef __powerpc64__ 955 for (i = 0; i < 64; i++) { 956 pcpup->pc_aim.slb[i].slbv = 0; 957 pcpup->pc_aim.slb[i].slbe = 0; 958 } 959 #else 960 for (i = 0; i < 16; i++) 961 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 962 #endif 963 964 kernel_pmap->pmap_phys = kernel_pmap; 965 CPU_FILL(&kernel_pmap->pm_active); 966 RB_INIT(&kernel_pmap->pmap_pvo); 967 968 PMAP_LOCK_INIT(kernel_pmap); 969 970 /* 971 * Now map in all the other buffers we allocated earlier 972 */ 973 974 moea64_setup_direct_map(kernelstart, kernelend); 975 } 976 977 void 978 moea64_late_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 979 { 980 ihandle_t mmui; 981 phandle_t chosen; 982 phandle_t mmu; 983 ssize_t sz; 984 int i; 985 vm_offset_t pa, va; 986 void *dpcpu; 987 988 /* 989 * Set up the Open Firmware pmap and add its mappings if not in real 990 * mode. 991 */ 992 993 chosen = OF_finddevice("/chosen"); 994 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 995 mmu = OF_instance_to_package(mmui); 996 if (mmu == -1 || 997 (sz = OF_getproplen(mmu, "translations")) == -1) 998 sz = 0; 999 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1000 panic("moea64_bootstrap: too many ofw translations"); 1001 1002 if (sz > 0) 1003 moea64_add_ofw_mappings(mmu, sz); 1004 } 1005 1006 /* 1007 * Calculate the last available physical address. 1008 */ 1009 Maxmem = 0; 1010 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1011 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 1012 1013 /* 1014 * Initialize MMU. 1015 */ 1016 pmap_cpu_bootstrap(0); 1017 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1018 pmap_bootstrapped++; 1019 1020 /* 1021 * Set the start and end of kva. 1022 */ 1023 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1024 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1025 1026 /* 1027 * Map the entire KVA range into the SLB. We must not fault there. 1028 */ 1029 #ifdef __powerpc64__ 1030 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1031 moea64_bootstrap_slb_prefault(va, 0); 1032 #endif 1033 1034 /* 1035 * Remap any early IO mappings (console framebuffer, etc.) 1036 */ 1037 bs_remap_earlyboot(); 1038 1039 /* 1040 * Figure out how far we can extend virtual_end into segment 16 1041 * without running into existing mappings. Segment 16 is guaranteed 1042 * to contain neither RAM nor devices (at least on Apple hardware), 1043 * but will generally contain some OFW mappings we should not 1044 * step on. 1045 */ 1046 1047 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1048 PMAP_LOCK(kernel_pmap); 1049 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1050 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1051 virtual_end += PAGE_SIZE; 1052 PMAP_UNLOCK(kernel_pmap); 1053 #endif 1054 1055 /* 1056 * Allocate a kernel stack with a guard page for thread0 and map it 1057 * into the kernel page map. 1058 */ 1059 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1060 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1061 virtual_avail = va + kstack_pages * PAGE_SIZE; 1062 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1063 thread0.td_kstack = va; 1064 thread0.td_kstack_pages = kstack_pages; 1065 for (i = 0; i < kstack_pages; i++) { 1066 moea64_kenter(va, pa); 1067 pa += PAGE_SIZE; 1068 va += PAGE_SIZE; 1069 } 1070 1071 /* 1072 * Allocate virtual address space for the message buffer. 1073 */ 1074 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1075 msgbufp = (struct msgbuf *)virtual_avail; 1076 va = virtual_avail; 1077 virtual_avail += round_page(msgbufsize); 1078 while (va < virtual_avail) { 1079 moea64_kenter(va, pa); 1080 pa += PAGE_SIZE; 1081 va += PAGE_SIZE; 1082 } 1083 1084 /* 1085 * Allocate virtual address space for the dynamic percpu area. 1086 */ 1087 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1088 dpcpu = (void *)virtual_avail; 1089 va = virtual_avail; 1090 virtual_avail += DPCPU_SIZE; 1091 while (va < virtual_avail) { 1092 moea64_kenter(va, pa); 1093 pa += PAGE_SIZE; 1094 va += PAGE_SIZE; 1095 } 1096 dpcpu_init(dpcpu, curcpu); 1097 1098 crashdumpmap = (caddr_t)virtual_avail; 1099 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1100 1101 /* 1102 * Allocate some things for page zeroing. We put this directly 1103 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1104 * of the PVO book-keeping or other parts of the VM system 1105 * from even knowing that this hack exists. 1106 */ 1107 1108 if (!hw_direct_map) { 1109 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1110 MTX_DEF); 1111 for (i = 0; i < 2; i++) { 1112 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1113 virtual_end -= PAGE_SIZE; 1114 1115 moea64_kenter(moea64_scratchpage_va[i], 0); 1116 1117 PMAP_LOCK(kernel_pmap); 1118 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1119 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1120 PMAP_UNLOCK(kernel_pmap); 1121 } 1122 } 1123 1124 numa_mem_regions(&numa_pregions, &numapregions_sz); 1125 } 1126 1127 static void 1128 moea64_pmap_init_qpages(void) 1129 { 1130 struct pcpu *pc; 1131 int i; 1132 1133 if (hw_direct_map) 1134 return; 1135 1136 CPU_FOREACH(i) { 1137 pc = pcpu_find(i); 1138 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1139 if (pc->pc_qmap_addr == 0) 1140 panic("pmap_init_qpages: unable to allocate KVA"); 1141 PMAP_LOCK(kernel_pmap); 1142 pc->pc_aim.qmap_pvo = 1143 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1144 PMAP_UNLOCK(kernel_pmap); 1145 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1146 } 1147 } 1148 1149 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1150 1151 /* 1152 * Activate a user pmap. This mostly involves setting some non-CPU 1153 * state. 1154 */ 1155 void 1156 moea64_activate(struct thread *td) 1157 { 1158 pmap_t pm; 1159 1160 pm = &td->td_proc->p_vmspace->vm_pmap; 1161 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1162 1163 #ifdef __powerpc64__ 1164 PCPU_SET(aim.userslb, pm->pm_slb); 1165 __asm __volatile("slbmte %0, %1; isync" :: 1166 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1167 #else 1168 PCPU_SET(curpmap, pm->pmap_phys); 1169 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1170 #endif 1171 } 1172 1173 void 1174 moea64_deactivate(struct thread *td) 1175 { 1176 pmap_t pm; 1177 1178 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1179 1180 pm = &td->td_proc->p_vmspace->vm_pmap; 1181 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1182 #ifdef __powerpc64__ 1183 PCPU_SET(aim.userslb, NULL); 1184 #else 1185 PCPU_SET(curpmap, NULL); 1186 #endif 1187 } 1188 1189 void 1190 moea64_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1191 { 1192 struct pvo_entry key, *pvo; 1193 vm_page_t m; 1194 int64_t refchg; 1195 1196 key.pvo_vaddr = sva; 1197 PMAP_LOCK(pm); 1198 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1199 pvo != NULL && PVO_VADDR(pvo) < eva; 1200 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1201 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1202 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1203 pvo); 1204 pvo->pvo_vaddr &= ~PVO_WIRED; 1205 refchg = moea64_pte_replace(pvo, 0 /* No invalidation */); 1206 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1207 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1208 if (refchg < 0) 1209 refchg = LPTE_CHG; 1210 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1211 1212 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1213 if (refchg & LPTE_CHG) 1214 vm_page_dirty(m); 1215 if (refchg & LPTE_REF) 1216 vm_page_aflag_set(m, PGA_REFERENCED); 1217 } 1218 pm->pm_stats.wired_count--; 1219 } 1220 PMAP_UNLOCK(pm); 1221 } 1222 1223 /* 1224 * This goes through and sets the physical address of our 1225 * special scratch PTE to the PA we want to zero or copy. Because 1226 * of locking issues (this can get called in pvo_enter() by 1227 * the UMA allocator), we can't use most other utility functions here 1228 */ 1229 1230 static __inline 1231 void moea64_set_scratchpage_pa(int which, vm_paddr_t pa) 1232 { 1233 struct pvo_entry *pvo; 1234 1235 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1236 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1237 1238 pvo = moea64_scratchpage_pvo[which]; 1239 PMAP_LOCK(pvo->pvo_pmap); 1240 pvo->pvo_pte.pa = 1241 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1242 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1243 PMAP_UNLOCK(pvo->pvo_pmap); 1244 isync(); 1245 } 1246 1247 void 1248 moea64_copy_page(vm_page_t msrc, vm_page_t mdst) 1249 { 1250 vm_offset_t dst; 1251 vm_offset_t src; 1252 1253 dst = VM_PAGE_TO_PHYS(mdst); 1254 src = VM_PAGE_TO_PHYS(msrc); 1255 1256 if (hw_direct_map) { 1257 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1258 PAGE_SIZE); 1259 } else { 1260 mtx_lock(&moea64_scratchpage_mtx); 1261 1262 moea64_set_scratchpage_pa(0, src); 1263 moea64_set_scratchpage_pa(1, dst); 1264 1265 bcopy((void *)moea64_scratchpage_va[0], 1266 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1267 1268 mtx_unlock(&moea64_scratchpage_mtx); 1269 } 1270 } 1271 1272 static inline void 1273 moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 1274 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1275 { 1276 void *a_cp, *b_cp; 1277 vm_offset_t a_pg_offset, b_pg_offset; 1278 int cnt; 1279 1280 while (xfersize > 0) { 1281 a_pg_offset = a_offset & PAGE_MASK; 1282 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1283 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1284 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1285 a_pg_offset; 1286 b_pg_offset = b_offset & PAGE_MASK; 1287 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1288 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1289 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1290 b_pg_offset; 1291 bcopy(a_cp, b_cp, cnt); 1292 a_offset += cnt; 1293 b_offset += cnt; 1294 xfersize -= cnt; 1295 } 1296 } 1297 1298 static inline void 1299 moea64_copy_pages_nodmap(vm_page_t *ma, vm_offset_t a_offset, 1300 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1301 { 1302 void *a_cp, *b_cp; 1303 vm_offset_t a_pg_offset, b_pg_offset; 1304 int cnt; 1305 1306 mtx_lock(&moea64_scratchpage_mtx); 1307 while (xfersize > 0) { 1308 a_pg_offset = a_offset & PAGE_MASK; 1309 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1310 moea64_set_scratchpage_pa(0, 1311 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1312 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1313 b_pg_offset = b_offset & PAGE_MASK; 1314 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1315 moea64_set_scratchpage_pa(1, 1316 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1317 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1318 bcopy(a_cp, b_cp, cnt); 1319 a_offset += cnt; 1320 b_offset += cnt; 1321 xfersize -= cnt; 1322 } 1323 mtx_unlock(&moea64_scratchpage_mtx); 1324 } 1325 1326 void 1327 moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1328 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1329 { 1330 1331 if (hw_direct_map) { 1332 moea64_copy_pages_dmap(ma, a_offset, mb, b_offset, 1333 xfersize); 1334 } else { 1335 moea64_copy_pages_nodmap(ma, a_offset, mb, b_offset, 1336 xfersize); 1337 } 1338 } 1339 1340 void 1341 moea64_zero_page_area(vm_page_t m, int off, int size) 1342 { 1343 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1344 1345 if (size + off > PAGE_SIZE) 1346 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1347 1348 if (hw_direct_map) { 1349 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1350 } else { 1351 mtx_lock(&moea64_scratchpage_mtx); 1352 moea64_set_scratchpage_pa(0, pa); 1353 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1354 mtx_unlock(&moea64_scratchpage_mtx); 1355 } 1356 } 1357 1358 /* 1359 * Zero a page of physical memory by temporarily mapping it 1360 */ 1361 void 1362 moea64_zero_page(vm_page_t m) 1363 { 1364 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1365 vm_offset_t va, off; 1366 1367 if (!hw_direct_map) { 1368 mtx_lock(&moea64_scratchpage_mtx); 1369 1370 moea64_set_scratchpage_pa(0, pa); 1371 va = moea64_scratchpage_va[0]; 1372 } else { 1373 va = PHYS_TO_DMAP(pa); 1374 } 1375 1376 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1377 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1378 1379 if (!hw_direct_map) 1380 mtx_unlock(&moea64_scratchpage_mtx); 1381 } 1382 1383 vm_offset_t 1384 moea64_quick_enter_page(vm_page_t m) 1385 { 1386 struct pvo_entry *pvo; 1387 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1388 1389 if (hw_direct_map) 1390 return (PHYS_TO_DMAP(pa)); 1391 1392 /* 1393 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1394 * a critical section and access the PCPU data like on i386. 1395 * Instead, pin the thread and grab the PCPU lock to prevent 1396 * a preempting thread from using the same PCPU data. 1397 */ 1398 sched_pin(); 1399 1400 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1401 pvo = PCPU_GET(aim.qmap_pvo); 1402 1403 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1404 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1405 (uint64_t)pa; 1406 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1407 isync(); 1408 1409 return (PCPU_GET(qmap_addr)); 1410 } 1411 1412 void 1413 moea64_quick_remove_page(vm_offset_t addr) 1414 { 1415 if (hw_direct_map) 1416 return; 1417 1418 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1419 KASSERT(PCPU_GET(qmap_addr) == addr, 1420 ("moea64_quick_remove_page: invalid address")); 1421 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1422 sched_unpin(); 1423 } 1424 1425 boolean_t 1426 moea64_page_is_mapped(vm_page_t m) 1427 { 1428 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1429 } 1430 1431 /* 1432 * Map the given physical page at the specified virtual address in the 1433 * target pmap with the protection requested. If specified the page 1434 * will be wired down. 1435 */ 1436 1437 int 1438 moea64_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1439 vm_prot_t prot, u_int flags, int8_t psind) 1440 { 1441 struct pvo_entry *pvo, *oldpvo; 1442 struct pvo_head *pvo_head; 1443 uint64_t pte_lo; 1444 int error; 1445 1446 if ((m->oflags & VPO_UNMANAGED) == 0) { 1447 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1448 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1449 else 1450 VM_OBJECT_ASSERT_LOCKED(m->object); 1451 } 1452 1453 pvo = alloc_pvo_entry(0); 1454 if (pvo == NULL) 1455 return (KERN_RESOURCE_SHORTAGE); 1456 pvo->pvo_pmap = NULL; /* to be filled in later */ 1457 pvo->pvo_pte.prot = prot; 1458 1459 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1460 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1461 1462 if ((flags & PMAP_ENTER_WIRED) != 0) 1463 pvo->pvo_vaddr |= PVO_WIRED; 1464 1465 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1466 pvo_head = NULL; 1467 } else { 1468 pvo_head = &m->md.mdpg_pvoh; 1469 pvo->pvo_vaddr |= PVO_MANAGED; 1470 } 1471 1472 PV_PAGE_LOCK(m); 1473 PMAP_LOCK(pmap); 1474 if (pvo->pvo_pmap == NULL) 1475 init_pvo_entry(pvo, pmap, va); 1476 if (prot & VM_PROT_WRITE) 1477 if (pmap_bootstrapped && 1478 (m->oflags & VPO_UNMANAGED) == 0) 1479 vm_page_aflag_set(m, PGA_WRITEABLE); 1480 1481 error = moea64_pvo_enter(pvo, pvo_head, &oldpvo); 1482 if (error == EEXIST) { 1483 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1484 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1485 oldpvo->pvo_pte.prot == prot) { 1486 /* Identical mapping already exists */ 1487 error = 0; 1488 1489 /* If not in page table, reinsert it */ 1490 if (moea64_pte_synch(oldpvo) < 0) { 1491 STAT_MOEA64(moea64_pte_overflow--); 1492 moea64_pte_insert(oldpvo); 1493 } 1494 1495 /* Then just clean up and go home */ 1496 PV_PAGE_UNLOCK(m); 1497 PMAP_UNLOCK(pmap); 1498 free_pvo_entry(pvo); 1499 goto out; 1500 } else { 1501 /* Otherwise, need to kill it first */ 1502 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1503 "mapping does not match new mapping")); 1504 moea64_pvo_remove_from_pmap(oldpvo); 1505 moea64_pvo_enter(pvo, pvo_head, NULL); 1506 } 1507 } 1508 PMAP_UNLOCK(pmap); 1509 PV_PAGE_UNLOCK(m); 1510 1511 /* Free any dead pages */ 1512 if (error == EEXIST) { 1513 moea64_pvo_remove_from_page(oldpvo); 1514 free_pvo_entry(oldpvo); 1515 } 1516 1517 out: 1518 /* 1519 * Flush the page from the instruction cache if this page is 1520 * mapped executable and cacheable. 1521 */ 1522 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1523 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1524 vm_page_aflag_set(m, PGA_EXECUTABLE); 1525 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1526 } 1527 return (KERN_SUCCESS); 1528 } 1529 1530 static void 1531 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1532 vm_size_t sz) 1533 { 1534 1535 /* 1536 * This is much trickier than on older systems because 1537 * we can't sync the icache on physical addresses directly 1538 * without a direct map. Instead we check a couple of cases 1539 * where the memory is already mapped in and, failing that, 1540 * use the same trick we use for page zeroing to create 1541 * a temporary mapping for this physical address. 1542 */ 1543 1544 if (!pmap_bootstrapped) { 1545 /* 1546 * If PMAP is not bootstrapped, we are likely to be 1547 * in real mode. 1548 */ 1549 __syncicache((void *)(uintptr_t)pa, sz); 1550 } else if (pmap == kernel_pmap) { 1551 __syncicache((void *)va, sz); 1552 } else if (hw_direct_map) { 1553 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1554 } else { 1555 /* Use the scratch page to set up a temp mapping */ 1556 1557 mtx_lock(&moea64_scratchpage_mtx); 1558 1559 moea64_set_scratchpage_pa(1, pa & ~ADDR_POFF); 1560 __syncicache((void *)(moea64_scratchpage_va[1] + 1561 (va & ADDR_POFF)), sz); 1562 1563 mtx_unlock(&moea64_scratchpage_mtx); 1564 } 1565 } 1566 1567 /* 1568 * Maps a sequence of resident pages belonging to the same object. 1569 * The sequence begins with the given page m_start. This page is 1570 * mapped at the given virtual address start. Each subsequent page is 1571 * mapped at a virtual address that is offset from start by the same 1572 * amount as the page is offset from m_start within the object. The 1573 * last page in the sequence is the page with the largest offset from 1574 * m_start that can be mapped at a virtual address less than the given 1575 * virtual address end. Not every virtual page between start and end 1576 * is mapped; only those for which a resident page exists with the 1577 * corresponding offset from m_start are mapped. 1578 */ 1579 void 1580 moea64_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1581 vm_page_t m_start, vm_prot_t prot) 1582 { 1583 vm_page_t m; 1584 vm_pindex_t diff, psize; 1585 1586 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1587 1588 psize = atop(end - start); 1589 m = m_start; 1590 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1591 moea64_enter(pm, start + ptoa(diff), m, prot & 1592 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1593 PMAP_ENTER_QUICK_LOCKED, 0); 1594 m = TAILQ_NEXT(m, listq); 1595 } 1596 } 1597 1598 void 1599 moea64_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1600 vm_prot_t prot) 1601 { 1602 1603 moea64_enter(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1604 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1605 } 1606 1607 vm_paddr_t 1608 moea64_extract(pmap_t pm, vm_offset_t va) 1609 { 1610 struct pvo_entry *pvo; 1611 vm_paddr_t pa; 1612 1613 PMAP_LOCK(pm); 1614 pvo = moea64_pvo_find_va(pm, va); 1615 if (pvo == NULL) 1616 pa = 0; 1617 else 1618 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1619 PMAP_UNLOCK(pm); 1620 1621 return (pa); 1622 } 1623 1624 /* 1625 * Atomically extract and hold the physical page with the given 1626 * pmap and virtual address pair if that mapping permits the given 1627 * protection. 1628 */ 1629 vm_page_t 1630 moea64_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1631 { 1632 struct pvo_entry *pvo; 1633 vm_page_t m; 1634 1635 m = NULL; 1636 PMAP_LOCK(pmap); 1637 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1638 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1639 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1640 if (!vm_page_wire_mapped(m)) 1641 m = NULL; 1642 } 1643 PMAP_UNLOCK(pmap); 1644 return (m); 1645 } 1646 1647 static void * 1648 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1649 uint8_t *flags, int wait) 1650 { 1651 struct pvo_entry *pvo; 1652 vm_offset_t va; 1653 vm_page_t m; 1654 int needed_lock; 1655 1656 /* 1657 * This entire routine is a horrible hack to avoid bothering kmem 1658 * for new KVA addresses. Because this can get called from inside 1659 * kmem allocation routines, calling kmem for a new address here 1660 * can lead to multiply locking non-recursive mutexes. 1661 */ 1662 1663 *flags = UMA_SLAB_PRIV; 1664 needed_lock = !PMAP_LOCKED(kernel_pmap); 1665 1666 m = vm_page_alloc_domain(NULL, 0, domain, 1667 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1668 if (m == NULL) 1669 return (NULL); 1670 1671 va = VM_PAGE_TO_PHYS(m); 1672 1673 pvo = alloc_pvo_entry(1 /* bootstrap */); 1674 1675 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1676 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1677 1678 if (needed_lock) 1679 PMAP_LOCK(kernel_pmap); 1680 1681 init_pvo_entry(pvo, kernel_pmap, va); 1682 pvo->pvo_vaddr |= PVO_WIRED; 1683 1684 moea64_pvo_enter(pvo, NULL, NULL); 1685 1686 if (needed_lock) 1687 PMAP_UNLOCK(kernel_pmap); 1688 1689 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1690 bzero((void *)va, PAGE_SIZE); 1691 1692 return (void *)va; 1693 } 1694 1695 extern int elf32_nxstack; 1696 1697 void 1698 moea64_init() 1699 { 1700 1701 CTR0(KTR_PMAP, "moea64_init"); 1702 1703 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1704 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1705 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1706 1707 if (!hw_direct_map) { 1708 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1709 } 1710 1711 #ifdef COMPAT_FREEBSD32 1712 elf32_nxstack = 1; 1713 #endif 1714 1715 moea64_initialized = TRUE; 1716 } 1717 1718 boolean_t 1719 moea64_is_referenced(vm_page_t m) 1720 { 1721 1722 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1723 ("moea64_is_referenced: page %p is not managed", m)); 1724 1725 return (moea64_query_bit(m, LPTE_REF)); 1726 } 1727 1728 boolean_t 1729 moea64_is_modified(vm_page_t m) 1730 { 1731 1732 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1733 ("moea64_is_modified: page %p is not managed", m)); 1734 1735 /* 1736 * If the page is not busied then this check is racy. 1737 */ 1738 if (!pmap_page_is_write_mapped(m)) 1739 return (FALSE); 1740 1741 return (moea64_query_bit(m, LPTE_CHG)); 1742 } 1743 1744 boolean_t 1745 moea64_is_prefaultable(pmap_t pmap, vm_offset_t va) 1746 { 1747 struct pvo_entry *pvo; 1748 boolean_t rv = TRUE; 1749 1750 PMAP_LOCK(pmap); 1751 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1752 if (pvo != NULL) 1753 rv = FALSE; 1754 PMAP_UNLOCK(pmap); 1755 return (rv); 1756 } 1757 1758 void 1759 moea64_clear_modify(vm_page_t m) 1760 { 1761 1762 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1763 ("moea64_clear_modify: page %p is not managed", m)); 1764 vm_page_assert_busied(m); 1765 1766 if (!pmap_page_is_write_mapped(m)) 1767 return; 1768 moea64_clear_bit(m, LPTE_CHG); 1769 } 1770 1771 /* 1772 * Clear the write and modified bits in each of the given page's mappings. 1773 */ 1774 void 1775 moea64_remove_write(vm_page_t m) 1776 { 1777 struct pvo_entry *pvo; 1778 int64_t refchg, ret; 1779 pmap_t pmap; 1780 1781 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1782 ("moea64_remove_write: page %p is not managed", m)); 1783 vm_page_assert_busied(m); 1784 1785 if (!pmap_page_is_write_mapped(m)) 1786 return 1787 1788 powerpc_sync(); 1789 PV_PAGE_LOCK(m); 1790 refchg = 0; 1791 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1792 pmap = pvo->pvo_pmap; 1793 PMAP_LOCK(pmap); 1794 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1795 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1796 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1797 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 1798 if (ret < 0) 1799 ret = LPTE_CHG; 1800 refchg |= ret; 1801 if (pvo->pvo_pmap == kernel_pmap) 1802 isync(); 1803 } 1804 PMAP_UNLOCK(pmap); 1805 } 1806 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1807 vm_page_dirty(m); 1808 vm_page_aflag_clear(m, PGA_WRITEABLE); 1809 PV_PAGE_UNLOCK(m); 1810 } 1811 1812 /* 1813 * moea64_ts_referenced: 1814 * 1815 * Return a count of reference bits for a page, clearing those bits. 1816 * It is not necessary for every reference bit to be cleared, but it 1817 * is necessary that 0 only be returned when there are truly no 1818 * reference bits set. 1819 * 1820 * XXX: The exact number of bits to check and clear is a matter that 1821 * should be tested and standardized at some point in the future for 1822 * optimal aging of shared pages. 1823 */ 1824 int 1825 moea64_ts_referenced(vm_page_t m) 1826 { 1827 1828 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1829 ("moea64_ts_referenced: page %p is not managed", m)); 1830 return (moea64_clear_bit(m, LPTE_REF)); 1831 } 1832 1833 /* 1834 * Modify the WIMG settings of all mappings for a page. 1835 */ 1836 void 1837 moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma) 1838 { 1839 struct pvo_entry *pvo; 1840 int64_t refchg; 1841 pmap_t pmap; 1842 uint64_t lo; 1843 1844 if ((m->oflags & VPO_UNMANAGED) != 0) { 1845 m->md.mdpg_cache_attrs = ma; 1846 return; 1847 } 1848 1849 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1850 1851 PV_PAGE_LOCK(m); 1852 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1853 pmap = pvo->pvo_pmap; 1854 PMAP_LOCK(pmap); 1855 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1856 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1857 pvo->pvo_pte.pa |= lo; 1858 refchg = moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1859 if (refchg < 0) 1860 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1861 LPTE_CHG : 0; 1862 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1863 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1864 refchg |= 1865 atomic_readandclear_32(&m->md.mdpg_attrs); 1866 if (refchg & LPTE_CHG) 1867 vm_page_dirty(m); 1868 if (refchg & LPTE_REF) 1869 vm_page_aflag_set(m, PGA_REFERENCED); 1870 } 1871 if (pvo->pvo_pmap == kernel_pmap) 1872 isync(); 1873 } 1874 PMAP_UNLOCK(pmap); 1875 } 1876 m->md.mdpg_cache_attrs = ma; 1877 PV_PAGE_UNLOCK(m); 1878 } 1879 1880 /* 1881 * Map a wired page into kernel virtual address space. 1882 */ 1883 void 1884 moea64_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1885 { 1886 int error; 1887 struct pvo_entry *pvo, *oldpvo; 1888 1889 do { 1890 pvo = alloc_pvo_entry(0); 1891 if (pvo == NULL) 1892 vm_wait(NULL); 1893 } while (pvo == NULL); 1894 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1895 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1896 pvo->pvo_vaddr |= PVO_WIRED; 1897 1898 PMAP_LOCK(kernel_pmap); 1899 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1900 if (oldpvo != NULL) 1901 moea64_pvo_remove_from_pmap(oldpvo); 1902 init_pvo_entry(pvo, kernel_pmap, va); 1903 error = moea64_pvo_enter(pvo, NULL, NULL); 1904 PMAP_UNLOCK(kernel_pmap); 1905 1906 /* Free any dead pages */ 1907 if (oldpvo != NULL) { 1908 moea64_pvo_remove_from_page(oldpvo); 1909 free_pvo_entry(oldpvo); 1910 } 1911 1912 if (error != 0) 1913 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1914 (uintmax_t)pa, error); 1915 } 1916 1917 void 1918 moea64_kenter(vm_offset_t va, vm_paddr_t pa) 1919 { 1920 1921 moea64_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1922 } 1923 1924 /* 1925 * Extract the physical page address associated with the given kernel virtual 1926 * address. 1927 */ 1928 vm_paddr_t 1929 moea64_kextract(vm_offset_t va) 1930 { 1931 struct pvo_entry *pvo; 1932 vm_paddr_t pa; 1933 1934 /* 1935 * Shortcut the direct-mapped case when applicable. We never put 1936 * anything but 1:1 (or 62-bit aliased) mappings below 1937 * VM_MIN_KERNEL_ADDRESS. 1938 */ 1939 if (va < VM_MIN_KERNEL_ADDRESS) 1940 return (va & ~DMAP_BASE_ADDRESS); 1941 1942 PMAP_LOCK(kernel_pmap); 1943 pvo = moea64_pvo_find_va(kernel_pmap, va); 1944 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1945 va)); 1946 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1947 PMAP_UNLOCK(kernel_pmap); 1948 return (pa); 1949 } 1950 1951 /* 1952 * Remove a wired page from kernel virtual address space. 1953 */ 1954 void 1955 moea64_kremove(vm_offset_t va) 1956 { 1957 moea64_remove(kernel_pmap, va, va + PAGE_SIZE); 1958 } 1959 1960 /* 1961 * Provide a kernel pointer corresponding to a given userland pointer. 1962 * The returned pointer is valid until the next time this function is 1963 * called in this thread. This is used internally in copyin/copyout. 1964 */ 1965 static int 1966 moea64_map_user_ptr(pmap_t pm, volatile const void *uaddr, 1967 void **kaddr, size_t ulen, size_t *klen) 1968 { 1969 size_t l; 1970 #ifdef __powerpc64__ 1971 struct slb *slb; 1972 #endif 1973 register_t slbv; 1974 1975 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1976 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1977 if (l > ulen) 1978 l = ulen; 1979 if (klen) 1980 *klen = l; 1981 else if (l != ulen) 1982 return (EFAULT); 1983 1984 #ifdef __powerpc64__ 1985 /* Try lockless look-up first */ 1986 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1987 1988 if (slb == NULL) { 1989 /* If it isn't there, we need to pre-fault the VSID */ 1990 PMAP_LOCK(pm); 1991 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1992 PMAP_UNLOCK(pm); 1993 } else { 1994 slbv = slb->slbv; 1995 } 1996 1997 /* Mark segment no-execute */ 1998 slbv |= SLBV_N; 1999 #else 2000 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 2001 2002 /* Mark segment no-execute */ 2003 slbv |= SR_N; 2004 #endif 2005 2006 /* If we have already set this VSID, we can just return */ 2007 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 2008 return (0); 2009 2010 __asm __volatile("isync"); 2011 curthread->td_pcb->pcb_cpu.aim.usr_segm = 2012 (uintptr_t)uaddr >> ADDR_SR_SHFT; 2013 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 2014 #ifdef __powerpc64__ 2015 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2016 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2017 #else 2018 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2019 #endif 2020 2021 return (0); 2022 } 2023 2024 /* 2025 * Figure out where a given kernel pointer (usually in a fault) points 2026 * to from the VM's perspective, potentially remapping into userland's 2027 * address space. 2028 */ 2029 static int 2030 moea64_decode_kernel_ptr(vm_offset_t addr, int *is_user, 2031 vm_offset_t *decoded_addr) 2032 { 2033 vm_offset_t user_sr; 2034 2035 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2036 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2037 addr &= ADDR_PIDX | ADDR_POFF; 2038 addr |= user_sr << ADDR_SR_SHFT; 2039 *decoded_addr = addr; 2040 *is_user = 1; 2041 } else { 2042 *decoded_addr = addr; 2043 *is_user = 0; 2044 } 2045 2046 return (0); 2047 } 2048 2049 /* 2050 * Map a range of physical addresses into kernel virtual address space. 2051 * 2052 * The value passed in *virt is a suggested virtual address for the mapping. 2053 * Architectures which can support a direct-mapped physical to virtual region 2054 * can return the appropriate address within that region, leaving '*virt' 2055 * unchanged. Other architectures should map the pages starting at '*virt' and 2056 * update '*virt' with the first usable address after the mapped region. 2057 */ 2058 vm_offset_t 2059 moea64_map(vm_offset_t *virt, vm_paddr_t pa_start, 2060 vm_paddr_t pa_end, int prot) 2061 { 2062 vm_offset_t sva, va; 2063 2064 if (hw_direct_map) { 2065 /* 2066 * Check if every page in the region is covered by the direct 2067 * map. The direct map covers all of physical memory. Use 2068 * moea64_calc_wimg() as a shortcut to see if the page is in 2069 * physical memory as a way to see if the direct map covers it. 2070 */ 2071 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2072 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2073 break; 2074 if (va == pa_end) 2075 return (PHYS_TO_DMAP(pa_start)); 2076 } 2077 sva = *virt; 2078 va = sva; 2079 /* XXX respect prot argument */ 2080 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2081 moea64_kenter(va, pa_start); 2082 *virt = va; 2083 2084 return (sva); 2085 } 2086 2087 /* 2088 * Returns true if the pmap's pv is one of the first 2089 * 16 pvs linked to from this page. This count may 2090 * be changed upwards or downwards in the future; it 2091 * is only necessary that true be returned for a small 2092 * subset of pmaps for proper page aging. 2093 */ 2094 boolean_t 2095 moea64_page_exists_quick(pmap_t pmap, vm_page_t m) 2096 { 2097 int loops; 2098 struct pvo_entry *pvo; 2099 boolean_t rv; 2100 2101 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2102 ("moea64_page_exists_quick: page %p is not managed", m)); 2103 loops = 0; 2104 rv = FALSE; 2105 PV_PAGE_LOCK(m); 2106 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2107 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2108 rv = TRUE; 2109 break; 2110 } 2111 if (++loops >= 16) 2112 break; 2113 } 2114 PV_PAGE_UNLOCK(m); 2115 return (rv); 2116 } 2117 2118 void 2119 moea64_page_init(vm_page_t m) 2120 { 2121 2122 m->md.mdpg_attrs = 0; 2123 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2124 LIST_INIT(&m->md.mdpg_pvoh); 2125 } 2126 2127 /* 2128 * Return the number of managed mappings to the given physical page 2129 * that are wired. 2130 */ 2131 int 2132 moea64_page_wired_mappings(vm_page_t m) 2133 { 2134 struct pvo_entry *pvo; 2135 int count; 2136 2137 count = 0; 2138 if ((m->oflags & VPO_UNMANAGED) != 0) 2139 return (count); 2140 PV_PAGE_LOCK(m); 2141 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2142 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2143 count++; 2144 PV_PAGE_UNLOCK(m); 2145 return (count); 2146 } 2147 2148 static uintptr_t moea64_vsidcontext; 2149 2150 uintptr_t 2151 moea64_get_unique_vsid(void) { 2152 u_int entropy; 2153 register_t hash; 2154 uint32_t mask; 2155 int i; 2156 2157 entropy = 0; 2158 __asm __volatile("mftb %0" : "=r"(entropy)); 2159 2160 mtx_lock(&moea64_slb_mutex); 2161 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2162 u_int n; 2163 2164 /* 2165 * Create a new value by mutiplying by a prime and adding in 2166 * entropy from the timebase register. This is to make the 2167 * VSID more random so that the PT hash function collides 2168 * less often. (Note that the prime casues gcc to do shifts 2169 * instead of a multiply.) 2170 */ 2171 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2172 hash = moea64_vsidcontext & (NVSIDS - 1); 2173 if (hash == 0) /* 0 is special, avoid it */ 2174 continue; 2175 n = hash >> 5; 2176 mask = 1 << (hash & (VSID_NBPW - 1)); 2177 hash = (moea64_vsidcontext & VSID_HASHMASK); 2178 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2179 /* anything free in this bucket? */ 2180 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2181 entropy = (moea64_vsidcontext >> 20); 2182 continue; 2183 } 2184 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2185 mask = 1 << i; 2186 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2187 hash |= i; 2188 } 2189 if (hash == VSID_VRMA) /* also special, avoid this too */ 2190 continue; 2191 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2192 ("Allocating in-use VSID %#zx\n", hash)); 2193 moea64_vsid_bitmap[n] |= mask; 2194 mtx_unlock(&moea64_slb_mutex); 2195 return (hash); 2196 } 2197 2198 mtx_unlock(&moea64_slb_mutex); 2199 panic("%s: out of segments",__func__); 2200 } 2201 2202 #ifdef __powerpc64__ 2203 int 2204 moea64_pinit(pmap_t pmap) 2205 { 2206 2207 RB_INIT(&pmap->pmap_pvo); 2208 2209 pmap->pm_slb_tree_root = slb_alloc_tree(); 2210 pmap->pm_slb = slb_alloc_user_cache(); 2211 pmap->pm_slb_len = 0; 2212 2213 return (1); 2214 } 2215 #else 2216 int 2217 moea64_pinit(pmap_t pmap) 2218 { 2219 int i; 2220 uint32_t hash; 2221 2222 RB_INIT(&pmap->pmap_pvo); 2223 2224 if (pmap_bootstrapped) 2225 pmap->pmap_phys = (pmap_t)moea64_kextract((vm_offset_t)pmap); 2226 else 2227 pmap->pmap_phys = pmap; 2228 2229 /* 2230 * Allocate some segment registers for this pmap. 2231 */ 2232 hash = moea64_get_unique_vsid(); 2233 2234 for (i = 0; i < 16; i++) 2235 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2236 2237 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2238 2239 return (1); 2240 } 2241 #endif 2242 2243 /* 2244 * Initialize the pmap associated with process 0. 2245 */ 2246 void 2247 moea64_pinit0(pmap_t pm) 2248 { 2249 2250 PMAP_LOCK_INIT(pm); 2251 moea64_pinit(pm); 2252 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2253 } 2254 2255 /* 2256 * Set the physical protection on the specified range of this map as requested. 2257 */ 2258 static void 2259 moea64_pvo_protect( pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2260 { 2261 struct vm_page *pg; 2262 vm_prot_t oldprot; 2263 int32_t refchg; 2264 2265 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2266 2267 /* 2268 * Change the protection of the page. 2269 */ 2270 oldprot = pvo->pvo_pte.prot; 2271 pvo->pvo_pte.prot = prot; 2272 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2273 2274 /* 2275 * If the PVO is in the page table, update mapping 2276 */ 2277 refchg = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2278 if (refchg < 0) 2279 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2280 2281 if (pm != kernel_pmap && pg != NULL && 2282 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2283 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2284 if ((pg->oflags & VPO_UNMANAGED) == 0) 2285 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2286 moea64_syncicache(pm, PVO_VADDR(pvo), 2287 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2288 } 2289 2290 /* 2291 * Update vm about the REF/CHG bits if the page is managed and we have 2292 * removed write access. 2293 */ 2294 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2295 (oldprot & VM_PROT_WRITE)) { 2296 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2297 if (refchg & LPTE_CHG) 2298 vm_page_dirty(pg); 2299 if (refchg & LPTE_REF) 2300 vm_page_aflag_set(pg, PGA_REFERENCED); 2301 } 2302 } 2303 2304 void 2305 moea64_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2306 vm_prot_t prot) 2307 { 2308 struct pvo_entry *pvo, *tpvo, key; 2309 2310 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2311 sva, eva, prot); 2312 2313 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2314 ("moea64_protect: non current pmap")); 2315 2316 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2317 moea64_remove(pm, sva, eva); 2318 return; 2319 } 2320 2321 PMAP_LOCK(pm); 2322 key.pvo_vaddr = sva; 2323 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2324 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2325 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2326 moea64_pvo_protect(pm, pvo, prot); 2327 } 2328 PMAP_UNLOCK(pm); 2329 } 2330 2331 /* 2332 * Map a list of wired pages into kernel virtual address space. This is 2333 * intended for temporary mappings which do not need page modification or 2334 * references recorded. Existing mappings in the region are overwritten. 2335 */ 2336 void 2337 moea64_qenter(vm_offset_t va, vm_page_t *m, int count) 2338 { 2339 while (count-- > 0) { 2340 moea64_kenter(va, VM_PAGE_TO_PHYS(*m)); 2341 va += PAGE_SIZE; 2342 m++; 2343 } 2344 } 2345 2346 /* 2347 * Remove page mappings from kernel virtual address space. Intended for 2348 * temporary mappings entered by moea64_qenter. 2349 */ 2350 void 2351 moea64_qremove(vm_offset_t va, int count) 2352 { 2353 while (count-- > 0) { 2354 moea64_kremove(va); 2355 va += PAGE_SIZE; 2356 } 2357 } 2358 2359 void 2360 moea64_release_vsid(uint64_t vsid) 2361 { 2362 int idx, mask; 2363 2364 mtx_lock(&moea64_slb_mutex); 2365 idx = vsid & (NVSIDS-1); 2366 mask = 1 << (idx % VSID_NBPW); 2367 idx /= VSID_NBPW; 2368 KASSERT(moea64_vsid_bitmap[idx] & mask, 2369 ("Freeing unallocated VSID %#jx", vsid)); 2370 moea64_vsid_bitmap[idx] &= ~mask; 2371 mtx_unlock(&moea64_slb_mutex); 2372 } 2373 2374 2375 void 2376 moea64_release(pmap_t pmap) 2377 { 2378 2379 /* 2380 * Free segment registers' VSIDs 2381 */ 2382 #ifdef __powerpc64__ 2383 slb_free_tree(pmap); 2384 slb_free_user_cache(pmap->pm_slb); 2385 #else 2386 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2387 2388 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2389 #endif 2390 } 2391 2392 /* 2393 * Remove all pages mapped by the specified pmap 2394 */ 2395 void 2396 moea64_remove_pages(pmap_t pm) 2397 { 2398 struct pvo_entry *pvo, *tpvo; 2399 struct pvo_dlist tofree; 2400 2401 SLIST_INIT(&tofree); 2402 2403 PMAP_LOCK(pm); 2404 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2405 if (pvo->pvo_vaddr & PVO_WIRED) 2406 continue; 2407 2408 /* 2409 * For locking reasons, remove this from the page table and 2410 * pmap, but save delinking from the vm_page for a second 2411 * pass 2412 */ 2413 moea64_pvo_remove_from_pmap(pvo); 2414 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2415 } 2416 PMAP_UNLOCK(pm); 2417 2418 while (!SLIST_EMPTY(&tofree)) { 2419 pvo = SLIST_FIRST(&tofree); 2420 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2421 moea64_pvo_remove_from_page(pvo); 2422 free_pvo_entry(pvo); 2423 } 2424 } 2425 2426 /* 2427 * Remove the given range of addresses from the specified map. 2428 */ 2429 void 2430 moea64_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2431 { 2432 struct pvo_entry *pvo, *tpvo, key; 2433 struct pvo_dlist tofree; 2434 2435 /* 2436 * Perform an unsynchronized read. This is, however, safe. 2437 */ 2438 if (pm->pm_stats.resident_count == 0) 2439 return; 2440 2441 key.pvo_vaddr = sva; 2442 2443 SLIST_INIT(&tofree); 2444 2445 PMAP_LOCK(pm); 2446 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2447 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2448 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2449 2450 /* 2451 * For locking reasons, remove this from the page table and 2452 * pmap, but save delinking from the vm_page for a second 2453 * pass 2454 */ 2455 moea64_pvo_remove_from_pmap(pvo); 2456 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2457 } 2458 PMAP_UNLOCK(pm); 2459 2460 while (!SLIST_EMPTY(&tofree)) { 2461 pvo = SLIST_FIRST(&tofree); 2462 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2463 moea64_pvo_remove_from_page(pvo); 2464 free_pvo_entry(pvo); 2465 } 2466 } 2467 2468 /* 2469 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2470 * will reflect changes in pte's back to the vm_page. 2471 */ 2472 void 2473 moea64_remove_all(vm_page_t m) 2474 { 2475 struct pvo_entry *pvo, *next_pvo; 2476 struct pvo_head freequeue; 2477 int wasdead; 2478 pmap_t pmap; 2479 2480 LIST_INIT(&freequeue); 2481 2482 PV_PAGE_LOCK(m); 2483 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2484 pmap = pvo->pvo_pmap; 2485 PMAP_LOCK(pmap); 2486 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2487 if (!wasdead) 2488 moea64_pvo_remove_from_pmap(pvo); 2489 moea64_pvo_remove_from_page_locked(pvo, m); 2490 if (!wasdead) 2491 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2492 PMAP_UNLOCK(pmap); 2493 2494 } 2495 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2496 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2497 PV_PAGE_UNLOCK(m); 2498 2499 /* Clean up UMA allocations */ 2500 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2501 free_pvo_entry(pvo); 2502 } 2503 2504 /* 2505 * Allocate a physical page of memory directly from the phys_avail map. 2506 * Can only be called from moea64_bootstrap before avail start and end are 2507 * calculated. 2508 */ 2509 vm_offset_t 2510 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2511 { 2512 vm_offset_t s, e; 2513 int i, j; 2514 2515 size = round_page(size); 2516 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2517 if (align != 0) 2518 s = roundup2(phys_avail[i], align); 2519 else 2520 s = phys_avail[i]; 2521 e = s + size; 2522 2523 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2524 continue; 2525 2526 if (s + size > platform_real_maxaddr()) 2527 continue; 2528 2529 if (s == phys_avail[i]) { 2530 phys_avail[i] += size; 2531 } else if (e == phys_avail[i + 1]) { 2532 phys_avail[i + 1] -= size; 2533 } else { 2534 for (j = phys_avail_count * 2; j > i; j -= 2) { 2535 phys_avail[j] = phys_avail[j - 2]; 2536 phys_avail[j + 1] = phys_avail[j - 1]; 2537 } 2538 2539 phys_avail[i + 3] = phys_avail[i + 1]; 2540 phys_avail[i + 1] = s; 2541 phys_avail[i + 2] = e; 2542 phys_avail_count++; 2543 } 2544 2545 return (s); 2546 } 2547 panic("moea64_bootstrap_alloc: could not allocate memory"); 2548 } 2549 2550 static int 2551 moea64_pvo_enter(struct pvo_entry *pvo, struct pvo_head *pvo_head, 2552 struct pvo_entry **oldpvop) 2553 { 2554 struct pvo_entry *old_pvo; 2555 int err; 2556 2557 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2558 2559 STAT_MOEA64(moea64_pvo_enter_calls++); 2560 2561 /* 2562 * Add to pmap list 2563 */ 2564 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2565 2566 if (old_pvo != NULL) { 2567 if (oldpvop != NULL) 2568 *oldpvop = old_pvo; 2569 return (EEXIST); 2570 } 2571 2572 if (pvo_head != NULL) { 2573 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2574 } 2575 2576 if (pvo->pvo_vaddr & PVO_WIRED) 2577 pvo->pvo_pmap->pm_stats.wired_count++; 2578 pvo->pvo_pmap->pm_stats.resident_count++; 2579 2580 /* 2581 * Insert it into the hardware page table 2582 */ 2583 err = moea64_pte_insert(pvo); 2584 if (err != 0) { 2585 panic("moea64_pvo_enter: overflow"); 2586 } 2587 2588 STAT_MOEA64(moea64_pvo_entries++); 2589 2590 if (pvo->pvo_pmap == kernel_pmap) 2591 isync(); 2592 2593 #ifdef __powerpc64__ 2594 /* 2595 * Make sure all our bootstrap mappings are in the SLB as soon 2596 * as virtual memory is switched on. 2597 */ 2598 if (!pmap_bootstrapped) 2599 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2600 pvo->pvo_vaddr & PVO_LARGE); 2601 #endif 2602 2603 return (0); 2604 } 2605 2606 static void 2607 moea64_pvo_remove_from_pmap(struct pvo_entry *pvo) 2608 { 2609 struct vm_page *pg; 2610 int32_t refchg; 2611 2612 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2613 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2614 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2615 2616 /* 2617 * If there is an active pte entry, we need to deactivate it 2618 */ 2619 refchg = moea64_pte_unset(pvo); 2620 if (refchg < 0) { 2621 /* 2622 * If it was evicted from the page table, be pessimistic and 2623 * dirty the page. 2624 */ 2625 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2626 refchg = LPTE_CHG; 2627 else 2628 refchg = 0; 2629 } 2630 2631 /* 2632 * Update our statistics. 2633 */ 2634 pvo->pvo_pmap->pm_stats.resident_count--; 2635 if (pvo->pvo_vaddr & PVO_WIRED) 2636 pvo->pvo_pmap->pm_stats.wired_count--; 2637 2638 /* 2639 * Remove this PVO from the pmap list. 2640 */ 2641 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2642 2643 /* 2644 * Mark this for the next sweep 2645 */ 2646 pvo->pvo_vaddr |= PVO_DEAD; 2647 2648 /* Send RC bits to VM */ 2649 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2650 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2651 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2652 if (pg != NULL) { 2653 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2654 if (refchg & LPTE_CHG) 2655 vm_page_dirty(pg); 2656 if (refchg & LPTE_REF) 2657 vm_page_aflag_set(pg, PGA_REFERENCED); 2658 } 2659 } 2660 } 2661 2662 static inline void 2663 moea64_pvo_remove_from_page_locked(struct pvo_entry *pvo, 2664 vm_page_t m) 2665 { 2666 2667 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2668 2669 /* Use NULL pmaps as a sentinel for races in page deletion */ 2670 if (pvo->pvo_pmap == NULL) 2671 return; 2672 pvo->pvo_pmap = NULL; 2673 2674 /* 2675 * Update vm about page writeability/executability if managed 2676 */ 2677 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2678 if (pvo->pvo_vaddr & PVO_MANAGED) { 2679 if (m != NULL) { 2680 LIST_REMOVE(pvo, pvo_vlink); 2681 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2682 vm_page_aflag_clear(m, 2683 PGA_WRITEABLE | PGA_EXECUTABLE); 2684 } 2685 } 2686 2687 STAT_MOEA64(moea64_pvo_entries--); 2688 STAT_MOEA64(moea64_pvo_remove_calls++); 2689 } 2690 2691 static void 2692 moea64_pvo_remove_from_page(struct pvo_entry *pvo) 2693 { 2694 vm_page_t pg = NULL; 2695 2696 if (pvo->pvo_vaddr & PVO_MANAGED) 2697 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2698 2699 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2700 moea64_pvo_remove_from_page_locked(pvo, pg); 2701 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2702 } 2703 2704 static struct pvo_entry * 2705 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2706 { 2707 struct pvo_entry key; 2708 2709 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2710 2711 key.pvo_vaddr = va & ~ADDR_POFF; 2712 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2713 } 2714 2715 static boolean_t 2716 moea64_query_bit(vm_page_t m, uint64_t ptebit) 2717 { 2718 struct pvo_entry *pvo; 2719 int64_t ret; 2720 boolean_t rv; 2721 2722 /* 2723 * See if this bit is stored in the page already. 2724 */ 2725 if (m->md.mdpg_attrs & ptebit) 2726 return (TRUE); 2727 2728 /* 2729 * Examine each PTE. Sync so that any pending REF/CHG bits are 2730 * flushed to the PTEs. 2731 */ 2732 rv = FALSE; 2733 powerpc_sync(); 2734 PV_PAGE_LOCK(m); 2735 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2736 ret = 0; 2737 2738 /* 2739 * See if this pvo has a valid PTE. if so, fetch the 2740 * REF/CHG bits from the valid PTE. If the appropriate 2741 * ptebit is set, return success. 2742 */ 2743 PMAP_LOCK(pvo->pvo_pmap); 2744 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2745 ret = moea64_pte_synch(pvo); 2746 PMAP_UNLOCK(pvo->pvo_pmap); 2747 2748 if (ret > 0) { 2749 atomic_set_32(&m->md.mdpg_attrs, 2750 ret & (LPTE_CHG | LPTE_REF)); 2751 if (ret & ptebit) { 2752 rv = TRUE; 2753 break; 2754 } 2755 } 2756 } 2757 PV_PAGE_UNLOCK(m); 2758 2759 return (rv); 2760 } 2761 2762 static u_int 2763 moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 2764 { 2765 u_int count; 2766 struct pvo_entry *pvo; 2767 int64_t ret; 2768 2769 /* 2770 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2771 * we can reset the right ones). 2772 */ 2773 powerpc_sync(); 2774 2775 /* 2776 * For each pvo entry, clear the pte's ptebit. 2777 */ 2778 count = 0; 2779 PV_PAGE_LOCK(m); 2780 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2781 ret = 0; 2782 2783 PMAP_LOCK(pvo->pvo_pmap); 2784 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2785 ret = moea64_pte_clear(pvo, ptebit); 2786 PMAP_UNLOCK(pvo->pvo_pmap); 2787 2788 if (ret > 0 && (ret & ptebit)) 2789 count++; 2790 } 2791 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2792 PV_PAGE_UNLOCK(m); 2793 2794 return (count); 2795 } 2796 2797 boolean_t 2798 moea64_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2799 { 2800 struct pvo_entry *pvo, key; 2801 vm_offset_t ppa; 2802 int error = 0; 2803 2804 if (hw_direct_map && mem_valid(pa, size) == 0) 2805 return (0); 2806 2807 PMAP_LOCK(kernel_pmap); 2808 ppa = pa & ~ADDR_POFF; 2809 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2810 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2811 ppa < pa + size; ppa += PAGE_SIZE, 2812 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2813 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2814 error = EFAULT; 2815 break; 2816 } 2817 } 2818 PMAP_UNLOCK(kernel_pmap); 2819 2820 return (error); 2821 } 2822 2823 /* 2824 * Map a set of physical memory pages into the kernel virtual 2825 * address space. Return a pointer to where it is mapped. This 2826 * routine is intended to be used for mapping device memory, 2827 * NOT real memory. 2828 */ 2829 void * 2830 moea64_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2831 { 2832 vm_offset_t va, tmpva, ppa, offset; 2833 2834 ppa = trunc_page(pa); 2835 offset = pa & PAGE_MASK; 2836 size = roundup2(offset + size, PAGE_SIZE); 2837 2838 va = kva_alloc(size); 2839 2840 if (!va) 2841 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2842 2843 for (tmpva = va; size > 0;) { 2844 moea64_kenter_attr(tmpva, ppa, ma); 2845 size -= PAGE_SIZE; 2846 tmpva += PAGE_SIZE; 2847 ppa += PAGE_SIZE; 2848 } 2849 2850 return ((void *)(va + offset)); 2851 } 2852 2853 void * 2854 moea64_mapdev(vm_paddr_t pa, vm_size_t size) 2855 { 2856 2857 return moea64_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT); 2858 } 2859 2860 void 2861 moea64_unmapdev(vm_offset_t va, vm_size_t size) 2862 { 2863 vm_offset_t base, offset; 2864 2865 base = trunc_page(va); 2866 offset = va & PAGE_MASK; 2867 size = roundup2(offset + size, PAGE_SIZE); 2868 2869 kva_free(base, size); 2870 } 2871 2872 void 2873 moea64_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2874 { 2875 struct pvo_entry *pvo; 2876 vm_offset_t lim; 2877 vm_paddr_t pa; 2878 vm_size_t len; 2879 2880 if (__predict_false(pm == NULL)) 2881 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2882 2883 PMAP_LOCK(pm); 2884 while (sz > 0) { 2885 lim = round_page(va+1); 2886 len = MIN(lim - va, sz); 2887 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2888 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2889 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2890 moea64_syncicache(pm, va, pa, len); 2891 } 2892 va += len; 2893 sz -= len; 2894 } 2895 PMAP_UNLOCK(pm); 2896 } 2897 2898 void 2899 moea64_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2900 { 2901 2902 *va = (void *)(uintptr_t)pa; 2903 } 2904 2905 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2906 2907 void 2908 moea64_scan_init() 2909 { 2910 struct pvo_entry *pvo; 2911 vm_offset_t va; 2912 int i; 2913 2914 if (!do_minidump) { 2915 /* Initialize phys. segments for dumpsys(). */ 2916 memset(&dump_map, 0, sizeof(dump_map)); 2917 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2918 for (i = 0; i < pregions_sz; i++) { 2919 dump_map[i].pa_start = pregions[i].mr_start; 2920 dump_map[i].pa_size = pregions[i].mr_size; 2921 } 2922 return; 2923 } 2924 2925 /* Virtual segments for minidumps: */ 2926 memset(&dump_map, 0, sizeof(dump_map)); 2927 2928 /* 1st: kernel .data and .bss. */ 2929 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2930 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2931 dump_map[0].pa_start; 2932 2933 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2934 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2935 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2936 2937 /* 3rd: kernel VM. */ 2938 va = dump_map[1].pa_start + dump_map[1].pa_size; 2939 /* Find start of next chunk (from va). */ 2940 while (va < virtual_end) { 2941 /* Don't dump the buffer cache. */ 2942 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2943 va = kmi.buffer_eva; 2944 continue; 2945 } 2946 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2947 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2948 break; 2949 va += PAGE_SIZE; 2950 } 2951 if (va < virtual_end) { 2952 dump_map[2].pa_start = va; 2953 va += PAGE_SIZE; 2954 /* Find last page in chunk. */ 2955 while (va < virtual_end) { 2956 /* Don't run into the buffer cache. */ 2957 if (va == kmi.buffer_sva) 2958 break; 2959 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2960 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2961 break; 2962 va += PAGE_SIZE; 2963 } 2964 dump_map[2].pa_size = va - dump_map[2].pa_start; 2965 } 2966 } 2967 2968 #ifdef __powerpc64__ 2969 2970 static size_t 2971 moea64_scan_pmap() 2972 { 2973 struct pvo_entry *pvo; 2974 vm_paddr_t pa, pa_end; 2975 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 2976 uint64_t lpsize; 2977 2978 lpsize = moea64_large_page_size; 2979 kstart = trunc_page((vm_offset_t)_etext); 2980 kend = round_page((vm_offset_t)_end); 2981 kstart_lp = kstart & ~moea64_large_page_mask; 2982 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 2983 2984 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 2985 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 2986 kstart, kend, kstart_lp, kend_lp); 2987 2988 PMAP_LOCK(kernel_pmap); 2989 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 2990 va = pvo->pvo_vaddr; 2991 2992 if (va & PVO_DEAD) 2993 continue; 2994 2995 /* Skip DMAP (except kernel area) */ 2996 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 2997 if (va & PVO_LARGE) { 2998 pgva = va & ~moea64_large_page_mask; 2999 if (pgva < kstart_lp || pgva >= kend_lp) 3000 continue; 3001 } else { 3002 pgva = trunc_page(va); 3003 if (pgva < kstart || pgva >= kend) 3004 continue; 3005 } 3006 } 3007 3008 pa = pvo->pvo_pte.pa & LPTE_RPGN; 3009 3010 if (va & PVO_LARGE) { 3011 pa_end = pa + lpsize; 3012 for (; pa < pa_end; pa += PAGE_SIZE) { 3013 if (is_dumpable(pa)) 3014 dump_add_page(pa); 3015 } 3016 } else { 3017 if (is_dumpable(pa)) 3018 dump_add_page(pa); 3019 } 3020 } 3021 PMAP_UNLOCK(kernel_pmap); 3022 3023 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3024 } 3025 3026 static struct dump_context dump_ctx; 3027 3028 static void * 3029 moea64_dump_pmap_init(unsigned blkpgs) 3030 { 3031 dump_ctx.ptex = 0; 3032 dump_ctx.ptex_end = moea64_pteg_count * 8; 3033 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3034 return (&dump_ctx); 3035 } 3036 3037 #else 3038 3039 static size_t 3040 moea64_scan_pmap() 3041 { 3042 return (0); 3043 } 3044 3045 static void * 3046 moea64_dump_pmap_init(unsigned blkpgs) 3047 { 3048 return (NULL); 3049 } 3050 3051 #endif 3052 3053 #ifdef __powerpc64__ 3054 static void 3055 moea64_map_range(vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3056 { 3057 3058 for (; npages > 0; --npages) { 3059 if (moea64_large_page_size != 0 && 3060 (pa & moea64_large_page_mask) == 0 && 3061 (va & moea64_large_page_mask) == 0 && 3062 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3063 PMAP_LOCK(kernel_pmap); 3064 moea64_kenter_large(va, pa, 0, 0); 3065 PMAP_UNLOCK(kernel_pmap); 3066 pa += moea64_large_page_size; 3067 va += moea64_large_page_size; 3068 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3069 } else { 3070 moea64_kenter(va, pa); 3071 pa += PAGE_SIZE; 3072 va += PAGE_SIZE; 3073 } 3074 } 3075 } 3076 3077 static void 3078 moea64_page_array_startup(long pages) 3079 { 3080 long dom_pages[MAXMEMDOM]; 3081 vm_paddr_t pa; 3082 vm_offset_t va, vm_page_base; 3083 vm_size_t needed, size; 3084 long page; 3085 int domain; 3086 int i; 3087 3088 vm_page_base = 0xd000000000000000ULL; 3089 3090 /* Short-circuit single-domain systems. */ 3091 if (vm_ndomains == 1) { 3092 size = round_page(pages * sizeof(struct vm_page)); 3093 pa = vm_phys_early_alloc(0, size); 3094 vm_page_base = moea64_map(&vm_page_base, 3095 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3096 vm_page_array_size = pages; 3097 vm_page_array = (vm_page_t)vm_page_base; 3098 return; 3099 } 3100 3101 page = 0; 3102 for (i = 0; i < MAXMEMDOM; i++) 3103 dom_pages[i] = 0; 3104 3105 /* Now get the number of pages required per domain. */ 3106 for (i = 0; i < vm_phys_nsegs; i++) { 3107 domain = vm_phys_segs[i].domain; 3108 KASSERT(domain < MAXMEMDOM, 3109 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3110 /* Get size of vm_page_array needed for this segment. */ 3111 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3112 dom_pages[domain] += size; 3113 } 3114 3115 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3116 domain = _vm_phys_domain(phys_avail[i]); 3117 KASSERT(domain < MAXMEMDOM, 3118 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3119 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3120 dom_pages[domain] += size; 3121 } 3122 3123 /* 3124 * Map in chunks that can get us all 16MB pages. There will be some 3125 * overlap between domains, but that's acceptable for now. 3126 */ 3127 vm_page_array_size = 0; 3128 va = vm_page_base; 3129 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3130 if (dom_pages[i] == 0) 3131 continue; 3132 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3133 size = round_page(size * sizeof(struct vm_page)); 3134 needed = size; 3135 size = roundup2(size, moea64_large_page_size); 3136 pa = vm_phys_early_alloc(i, size); 3137 vm_page_array_size += size / sizeof(struct vm_page); 3138 moea64_map_range(va, pa, size >> PAGE_SHIFT); 3139 /* Scoot up domain 0, to reduce the domain page overlap. */ 3140 if (i == 0) 3141 vm_page_base += size - needed; 3142 va += size; 3143 } 3144 vm_page_array = (vm_page_t)vm_page_base; 3145 vm_page_array_size = pages; 3146 } 3147 #endif 3148 3149 static int64_t 3150 moea64_null_method(void) 3151 { 3152 return (0); 3153 } 3154 3155 static int64_t moea64_pte_replace_default(struct pvo_entry *pvo, int flags) 3156 { 3157 int64_t refchg; 3158 3159 refchg = moea64_pte_unset(pvo); 3160 moea64_pte_insert(pvo); 3161 3162 return (refchg); 3163 } 3164 3165 struct moea64_funcs *moea64_ops; 3166 3167 #define DEFINE_OEA64_IFUNC(ret, func, args, def) \ 3168 DEFINE_IFUNC(, ret, moea64_##func, args) { \ 3169 moea64_##func##_t f; \ 3170 if (moea64_ops == NULL) \ 3171 return ((moea64_##func##_t)def); \ 3172 f = moea64_ops->func; \ 3173 return (f != NULL ? f : (moea64_##func##_t)def);\ 3174 } 3175 3176 DEFINE_OEA64_IFUNC(int64_t, pte_replace, (struct pvo_entry *, int), 3177 moea64_pte_replace_default) 3178 DEFINE_OEA64_IFUNC(int64_t, pte_insert, (struct pvo_entry *), moea64_null_method) 3179 DEFINE_OEA64_IFUNC(int64_t, pte_unset, (struct pvo_entry *), moea64_null_method) 3180 DEFINE_OEA64_IFUNC(int64_t, pte_clear, (struct pvo_entry *, uint64_t), 3181 moea64_null_method) 3182 DEFINE_OEA64_IFUNC(int64_t, pte_synch, (struct pvo_entry *), moea64_null_method) 3183