1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * Since the information managed by this module is also stored by the 100 * logical address mapping module, this module may throw away valid virtual 101 * to physical mappings at almost any time. However, invalidations of 102 * mappings must be done as requested. 103 * 104 * In order to cope with hardware architectures which make virtual to 105 * physical map invalidates expensive, this module may delay invalidate 106 * reduced protection operations until such time as they are actually 107 * necessary. This module is given full information as to which processors 108 * are currently using which maps, and to when physical maps must be made 109 * correct. 110 */ 111 112 #include "opt_compat.h" 113 #include "opt_kstack_pages.h" 114 115 #include <sys/param.h> 116 #include <sys/kernel.h> 117 #include <sys/queue.h> 118 #include <sys/cpuset.h> 119 #include <sys/ktr.h> 120 #include <sys/lock.h> 121 #include <sys/msgbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/mutex.h> 124 #include <sys/proc.h> 125 #include <sys/rwlock.h> 126 #include <sys/sched.h> 127 #include <sys/sysctl.h> 128 #include <sys/systm.h> 129 #include <sys/vmmeter.h> 130 131 #include <sys/kdb.h> 132 133 #include <dev/ofw/openfirm.h> 134 135 #include <vm/vm.h> 136 #include <vm/vm_param.h> 137 #include <vm/vm_kern.h> 138 #include <vm/vm_page.h> 139 #include <vm/vm_map.h> 140 #include <vm/vm_object.h> 141 #include <vm/vm_extern.h> 142 #include <vm/vm_pageout.h> 143 #include <vm/vm_pager.h> 144 #include <vm/uma.h> 145 146 #include <machine/_inttypes.h> 147 #include <machine/cpu.h> 148 #include <machine/platform.h> 149 #include <machine/frame.h> 150 #include <machine/md_var.h> 151 #include <machine/psl.h> 152 #include <machine/bat.h> 153 #include <machine/hid.h> 154 #include <machine/pte.h> 155 #include <machine/sr.h> 156 #include <machine/trap.h> 157 #include <machine/mmuvar.h> 158 159 #include "mmu_oea64.h" 160 #include "mmu_if.h" 161 #include "moea64_if.h" 162 163 void moea64_release_vsid(uint64_t vsid); 164 uintptr_t moea64_get_unique_vsid(void); 165 166 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 167 #define ENABLE_TRANS(msr) mtmsr(msr) 168 169 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 170 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 171 #define VSID_HASH_MASK 0x0000007fffffffffULL 172 173 /* 174 * Locking semantics: 175 * -- Read lock: if no modifications are being made to either the PVO lists 176 * or page table or if any modifications being made result in internal 177 * changes (e.g. wiring, protection) such that the existence of the PVOs 178 * is unchanged and they remain associated with the same pmap (in which 179 * case the changes should be protected by the pmap lock) 180 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 181 */ 182 183 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 184 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 185 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 186 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 187 188 struct ofw_map { 189 cell_t om_va; 190 cell_t om_len; 191 cell_t om_pa_hi; 192 cell_t om_pa_lo; 193 cell_t om_mode; 194 }; 195 196 /* 197 * Map of physical memory regions. 198 */ 199 static struct mem_region *regions; 200 static struct mem_region *pregions; 201 static u_int phys_avail_count; 202 static int regions_sz, pregions_sz; 203 204 extern void bs_remap_earlyboot(void); 205 206 /* 207 * Lock for the pteg and pvo tables. 208 */ 209 struct rwlock moea64_table_lock; 210 struct mtx moea64_slb_mutex; 211 212 /* 213 * PTEG data. 214 */ 215 u_int moea64_pteg_count; 216 u_int moea64_pteg_mask; 217 218 /* 219 * PVO data. 220 */ 221 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 222 223 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 224 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 225 226 #define BPVO_POOL_SIZE 327680 227 static struct pvo_entry *moea64_bpvo_pool; 228 static int moea64_bpvo_pool_index = 0; 229 230 #define VSID_NBPW (sizeof(u_int32_t) * 8) 231 #ifdef __powerpc64__ 232 #define NVSIDS (NPMAPS * 16) 233 #define VSID_HASHMASK 0xffffffffUL 234 #else 235 #define NVSIDS NPMAPS 236 #define VSID_HASHMASK 0xfffffUL 237 #endif 238 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 239 240 static boolean_t moea64_initialized = FALSE; 241 242 /* 243 * Statistics. 244 */ 245 u_int moea64_pte_valid = 0; 246 u_int moea64_pte_overflow = 0; 247 u_int moea64_pvo_entries = 0; 248 u_int moea64_pvo_enter_calls = 0; 249 u_int moea64_pvo_remove_calls = 0; 250 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 251 &moea64_pte_valid, 0, ""); 252 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 253 &moea64_pte_overflow, 0, ""); 254 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 255 &moea64_pvo_entries, 0, ""); 256 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 257 &moea64_pvo_enter_calls, 0, ""); 258 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 259 &moea64_pvo_remove_calls, 0, ""); 260 261 vm_offset_t moea64_scratchpage_va[2]; 262 struct pvo_entry *moea64_scratchpage_pvo[2]; 263 uintptr_t moea64_scratchpage_pte[2]; 264 struct mtx moea64_scratchpage_mtx; 265 266 uint64_t moea64_large_page_mask = 0; 267 int moea64_large_page_size = 0; 268 int moea64_large_page_shift = 0; 269 270 /* 271 * PVO calls. 272 */ 273 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 274 vm_offset_t, vm_offset_t, uint64_t, int); 275 static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 276 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 277 278 /* 279 * Utility routines. 280 */ 281 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 282 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 283 static void moea64_kremove(mmu_t, vm_offset_t); 284 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 285 vm_offset_t pa, vm_size_t sz); 286 287 /* 288 * Kernel MMU interface 289 */ 290 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 291 void moea64_clear_modify(mmu_t, vm_page_t); 292 void moea64_clear_reference(mmu_t, vm_page_t); 293 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 294 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 295 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 296 vm_prot_t); 297 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 298 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 299 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 300 void moea64_init(mmu_t); 301 boolean_t moea64_is_modified(mmu_t, vm_page_t); 302 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 303 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 304 int moea64_ts_referenced(mmu_t, vm_page_t); 305 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 306 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 307 int moea64_page_wired_mappings(mmu_t, vm_page_t); 308 void moea64_pinit(mmu_t, pmap_t); 309 void moea64_pinit0(mmu_t, pmap_t); 310 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 311 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 312 void moea64_qremove(mmu_t, vm_offset_t, int); 313 void moea64_release(mmu_t, pmap_t); 314 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 315 void moea64_remove_pages(mmu_t, pmap_t); 316 void moea64_remove_all(mmu_t, vm_page_t); 317 void moea64_remove_write(mmu_t, vm_page_t); 318 void moea64_zero_page(mmu_t, vm_page_t); 319 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 320 void moea64_zero_page_idle(mmu_t, vm_page_t); 321 void moea64_activate(mmu_t, struct thread *); 322 void moea64_deactivate(mmu_t, struct thread *); 323 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 324 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 325 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 326 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 327 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 328 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 329 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 330 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 331 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 332 333 static mmu_method_t moea64_methods[] = { 334 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 335 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 336 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 337 MMUMETHOD(mmu_copy_page, moea64_copy_page), 338 MMUMETHOD(mmu_enter, moea64_enter), 339 MMUMETHOD(mmu_enter_object, moea64_enter_object), 340 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 341 MMUMETHOD(mmu_extract, moea64_extract), 342 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 343 MMUMETHOD(mmu_init, moea64_init), 344 MMUMETHOD(mmu_is_modified, moea64_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 348 MMUMETHOD(mmu_map, moea64_map), 349 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 350 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 351 MMUMETHOD(mmu_pinit, moea64_pinit), 352 MMUMETHOD(mmu_pinit0, moea64_pinit0), 353 MMUMETHOD(mmu_protect, moea64_protect), 354 MMUMETHOD(mmu_qenter, moea64_qenter), 355 MMUMETHOD(mmu_qremove, moea64_qremove), 356 MMUMETHOD(mmu_release, moea64_release), 357 MMUMETHOD(mmu_remove, moea64_remove), 358 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 359 MMUMETHOD(mmu_remove_all, moea64_remove_all), 360 MMUMETHOD(mmu_remove_write, moea64_remove_write), 361 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 362 MMUMETHOD(mmu_zero_page, moea64_zero_page), 363 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 364 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 365 MMUMETHOD(mmu_activate, moea64_activate), 366 MMUMETHOD(mmu_deactivate, moea64_deactivate), 367 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 368 369 /* Internal interfaces */ 370 MMUMETHOD(mmu_mapdev, moea64_mapdev), 371 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 372 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 373 MMUMETHOD(mmu_kextract, moea64_kextract), 374 MMUMETHOD(mmu_kenter, moea64_kenter), 375 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 376 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 377 378 { 0, 0 } 379 }; 380 381 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 382 383 static __inline u_int 384 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 385 { 386 uint64_t hash; 387 int shift; 388 389 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 390 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 391 shift); 392 return (hash & moea64_pteg_mask); 393 } 394 395 static __inline struct pvo_head * 396 vm_page_to_pvoh(vm_page_t m) 397 { 398 399 return (&m->md.mdpg_pvoh); 400 } 401 402 static __inline void 403 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 404 uint64_t pte_lo, int flags) 405 { 406 407 /* 408 * Construct a PTE. Default to IMB initially. Valid bit only gets 409 * set when the real pte is set in memory. 410 * 411 * Note: Don't set the valid bit for correct operation of tlb update. 412 */ 413 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 414 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 415 416 if (flags & PVO_LARGE) 417 pt->pte_hi |= LPTE_BIG; 418 419 pt->pte_lo = pte_lo; 420 } 421 422 static __inline uint64_t 423 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 424 { 425 uint64_t pte_lo; 426 int i; 427 428 if (ma != VM_MEMATTR_DEFAULT) { 429 switch (ma) { 430 case VM_MEMATTR_UNCACHEABLE: 431 return (LPTE_I | LPTE_G); 432 case VM_MEMATTR_WRITE_COMBINING: 433 case VM_MEMATTR_WRITE_BACK: 434 case VM_MEMATTR_PREFETCHABLE: 435 return (LPTE_I); 436 case VM_MEMATTR_WRITE_THROUGH: 437 return (LPTE_W | LPTE_M); 438 } 439 } 440 441 /* 442 * Assume the page is cache inhibited and access is guarded unless 443 * it's in our available memory array. 444 */ 445 pte_lo = LPTE_I | LPTE_G; 446 for (i = 0; i < pregions_sz; i++) { 447 if ((pa >= pregions[i].mr_start) && 448 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 449 pte_lo &= ~(LPTE_I | LPTE_G); 450 pte_lo |= LPTE_M; 451 break; 452 } 453 } 454 455 return pte_lo; 456 } 457 458 /* 459 * Quick sort callout for comparing memory regions. 460 */ 461 static int om_cmp(const void *a, const void *b); 462 463 static int 464 om_cmp(const void *a, const void *b) 465 { 466 const struct ofw_map *mapa; 467 const struct ofw_map *mapb; 468 469 mapa = a; 470 mapb = b; 471 if (mapa->om_pa_hi < mapb->om_pa_hi) 472 return (-1); 473 else if (mapa->om_pa_hi > mapb->om_pa_hi) 474 return (1); 475 else if (mapa->om_pa_lo < mapb->om_pa_lo) 476 return (-1); 477 else if (mapa->om_pa_lo > mapb->om_pa_lo) 478 return (1); 479 else 480 return (0); 481 } 482 483 static void 484 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 485 { 486 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 487 register_t msr; 488 vm_offset_t off; 489 vm_paddr_t pa_base; 490 int i; 491 492 bzero(translations, sz); 493 if (OF_getprop(mmu, "translations", translations, sz) == -1) 494 panic("moea64_bootstrap: can't get ofw translations"); 495 496 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 497 sz /= sizeof(*translations); 498 qsort(translations, sz, sizeof (*translations), om_cmp); 499 500 for (i = 0; i < sz; i++) { 501 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 502 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 503 translations[i].om_len); 504 505 if (translations[i].om_pa_lo % PAGE_SIZE) 506 panic("OFW translation not page-aligned!"); 507 508 pa_base = translations[i].om_pa_lo; 509 510 #ifdef __powerpc64__ 511 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 512 #else 513 if (translations[i].om_pa_hi) 514 panic("OFW translations above 32-bit boundary!"); 515 #endif 516 517 /* Now enter the pages for this mapping */ 518 519 DISABLE_TRANS(msr); 520 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 521 if (moea64_pvo_find_va(kernel_pmap, 522 translations[i].om_va + off) != NULL) 523 continue; 524 525 moea64_kenter(mmup, translations[i].om_va + off, 526 pa_base + off); 527 } 528 ENABLE_TRANS(msr); 529 } 530 } 531 532 #ifdef __powerpc64__ 533 static void 534 moea64_probe_large_page(void) 535 { 536 uint16_t pvr = mfpvr() >> 16; 537 538 switch (pvr) { 539 case IBM970: 540 case IBM970FX: 541 case IBM970MP: 542 powerpc_sync(); isync(); 543 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 544 powerpc_sync(); isync(); 545 546 /* FALLTHROUGH */ 547 case IBMCELLBE: 548 moea64_large_page_size = 0x1000000; /* 16 MB */ 549 moea64_large_page_shift = 24; 550 break; 551 default: 552 moea64_large_page_size = 0; 553 } 554 555 moea64_large_page_mask = moea64_large_page_size - 1; 556 } 557 558 static void 559 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 560 { 561 struct slb *cache; 562 struct slb entry; 563 uint64_t esid, slbe; 564 uint64_t i; 565 566 cache = PCPU_GET(slb); 567 esid = va >> ADDR_SR_SHFT; 568 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 569 570 for (i = 0; i < 64; i++) { 571 if (cache[i].slbe == (slbe | i)) 572 return; 573 } 574 575 entry.slbe = slbe; 576 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 577 if (large) 578 entry.slbv |= SLBV_L; 579 580 slb_insert_kernel(entry.slbe, entry.slbv); 581 } 582 #endif 583 584 static void 585 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 586 vm_offset_t kernelend) 587 { 588 register_t msr; 589 vm_paddr_t pa; 590 vm_offset_t size, off; 591 uint64_t pte_lo; 592 int i; 593 594 if (moea64_large_page_size == 0) 595 hw_direct_map = 0; 596 597 DISABLE_TRANS(msr); 598 if (hw_direct_map) { 599 LOCK_TABLE_WR(); 600 PMAP_LOCK(kernel_pmap); 601 for (i = 0; i < pregions_sz; i++) { 602 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 603 pregions[i].mr_size; pa += moea64_large_page_size) { 604 pte_lo = LPTE_M; 605 606 /* 607 * Set memory access as guarded if prefetch within 608 * the page could exit the available physmem area. 609 */ 610 if (pa & moea64_large_page_mask) { 611 pa &= moea64_large_page_mask; 612 pte_lo |= LPTE_G; 613 } 614 if (pa + moea64_large_page_size > 615 pregions[i].mr_start + pregions[i].mr_size) 616 pte_lo |= LPTE_G; 617 618 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 619 NULL, pa, pa, pte_lo, 620 PVO_WIRED | PVO_LARGE); 621 } 622 } 623 PMAP_UNLOCK(kernel_pmap); 624 UNLOCK_TABLE_WR(); 625 } else { 626 size = sizeof(struct pvo_head) * moea64_pteg_count; 627 off = (vm_offset_t)(moea64_pvo_table); 628 for (pa = off; pa < off + size; pa += PAGE_SIZE) 629 moea64_kenter(mmup, pa, pa); 630 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 631 off = (vm_offset_t)(moea64_bpvo_pool); 632 for (pa = off; pa < off + size; pa += PAGE_SIZE) 633 moea64_kenter(mmup, pa, pa); 634 635 /* 636 * Map certain important things, like ourselves. 637 * 638 * NOTE: We do not map the exception vector space. That code is 639 * used only in real mode, and leaving it unmapped allows us to 640 * catch NULL pointer deferences, instead of making NULL a valid 641 * address. 642 */ 643 644 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 645 pa += PAGE_SIZE) 646 moea64_kenter(mmup, pa, pa); 647 } 648 ENABLE_TRANS(msr); 649 } 650 651 void 652 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 653 { 654 int i, j; 655 vm_size_t physsz, hwphyssz; 656 657 #ifndef __powerpc64__ 658 /* We don't have a direct map since there is no BAT */ 659 hw_direct_map = 0; 660 661 /* Make sure battable is zero, since we have no BAT */ 662 for (i = 0; i < 16; i++) { 663 battable[i].batu = 0; 664 battable[i].batl = 0; 665 } 666 #else 667 moea64_probe_large_page(); 668 669 /* Use a direct map if we have large page support */ 670 if (moea64_large_page_size > 0) 671 hw_direct_map = 1; 672 else 673 hw_direct_map = 0; 674 #endif 675 676 /* Get physical memory regions from firmware */ 677 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 678 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 679 680 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 681 panic("moea64_bootstrap: phys_avail too small"); 682 683 phys_avail_count = 0; 684 physsz = 0; 685 hwphyssz = 0; 686 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 687 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 688 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 689 regions[i].mr_start + regions[i].mr_size, 690 regions[i].mr_size); 691 if (hwphyssz != 0 && 692 (physsz + regions[i].mr_size) >= hwphyssz) { 693 if (physsz < hwphyssz) { 694 phys_avail[j] = regions[i].mr_start; 695 phys_avail[j + 1] = regions[i].mr_start + 696 hwphyssz - physsz; 697 physsz = hwphyssz; 698 phys_avail_count++; 699 } 700 break; 701 } 702 phys_avail[j] = regions[i].mr_start; 703 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 704 phys_avail_count++; 705 physsz += regions[i].mr_size; 706 } 707 708 /* Check for overlap with the kernel and exception vectors */ 709 for (j = 0; j < 2*phys_avail_count; j+=2) { 710 if (phys_avail[j] < EXC_LAST) 711 phys_avail[j] += EXC_LAST; 712 713 if (kernelstart >= phys_avail[j] && 714 kernelstart < phys_avail[j+1]) { 715 if (kernelend < phys_avail[j+1]) { 716 phys_avail[2*phys_avail_count] = 717 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 718 phys_avail[2*phys_avail_count + 1] = 719 phys_avail[j+1]; 720 phys_avail_count++; 721 } 722 723 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 724 } 725 726 if (kernelend >= phys_avail[j] && 727 kernelend < phys_avail[j+1]) { 728 if (kernelstart > phys_avail[j]) { 729 phys_avail[2*phys_avail_count] = phys_avail[j]; 730 phys_avail[2*phys_avail_count + 1] = 731 kernelstart & ~PAGE_MASK; 732 phys_avail_count++; 733 } 734 735 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 736 } 737 } 738 739 physmem = btoc(physsz); 740 741 #ifdef PTEGCOUNT 742 moea64_pteg_count = PTEGCOUNT; 743 #else 744 moea64_pteg_count = 0x1000; 745 746 while (moea64_pteg_count < physmem) 747 moea64_pteg_count <<= 1; 748 749 moea64_pteg_count >>= 1; 750 #endif /* PTEGCOUNT */ 751 } 752 753 void 754 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 755 { 756 vm_size_t size; 757 register_t msr; 758 int i; 759 760 /* 761 * Set PTEG mask 762 */ 763 moea64_pteg_mask = moea64_pteg_count - 1; 764 765 /* 766 * Allocate pv/overflow lists. 767 */ 768 size = sizeof(struct pvo_head) * moea64_pteg_count; 769 770 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 771 PAGE_SIZE); 772 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 773 774 DISABLE_TRANS(msr); 775 for (i = 0; i < moea64_pteg_count; i++) 776 LIST_INIT(&moea64_pvo_table[i]); 777 ENABLE_TRANS(msr); 778 779 /* 780 * Initialize the lock that synchronizes access to the pteg and pvo 781 * tables. 782 */ 783 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 784 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 785 786 /* 787 * Initialise the unmanaged pvo pool. 788 */ 789 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 790 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 791 moea64_bpvo_pool_index = 0; 792 793 /* 794 * Make sure kernel vsid is allocated as well as VSID 0. 795 */ 796 #ifndef __powerpc64__ 797 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 798 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 799 moea64_vsid_bitmap[0] |= 1; 800 #endif 801 802 /* 803 * Initialize the kernel pmap (which is statically allocated). 804 */ 805 #ifdef __powerpc64__ 806 for (i = 0; i < 64; i++) { 807 pcpup->pc_slb[i].slbv = 0; 808 pcpup->pc_slb[i].slbe = 0; 809 } 810 #else 811 for (i = 0; i < 16; i++) 812 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 813 #endif 814 815 kernel_pmap->pmap_phys = kernel_pmap; 816 CPU_FILL(&kernel_pmap->pm_active); 817 RB_INIT(&kernel_pmap->pmap_pvo); 818 819 PMAP_LOCK_INIT(kernel_pmap); 820 821 /* 822 * Now map in all the other buffers we allocated earlier 823 */ 824 825 moea64_setup_direct_map(mmup, kernelstart, kernelend); 826 } 827 828 void 829 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 830 { 831 ihandle_t mmui; 832 phandle_t chosen; 833 phandle_t mmu; 834 size_t sz; 835 int i; 836 vm_offset_t pa, va; 837 void *dpcpu; 838 839 /* 840 * Set up the Open Firmware pmap and add its mappings if not in real 841 * mode. 842 */ 843 844 chosen = OF_finddevice("/chosen"); 845 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 846 mmu = OF_instance_to_package(mmui); 847 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 848 sz = 0; 849 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 850 panic("moea64_bootstrap: too many ofw translations"); 851 852 if (sz > 0) 853 moea64_add_ofw_mappings(mmup, mmu, sz); 854 } 855 856 /* 857 * Calculate the last available physical address. 858 */ 859 for (i = 0; phys_avail[i + 2] != 0; i += 2) 860 ; 861 Maxmem = powerpc_btop(phys_avail[i + 1]); 862 863 /* 864 * Initialize MMU and remap early physical mappings 865 */ 866 MMU_CPU_BOOTSTRAP(mmup,0); 867 mtmsr(mfmsr() | PSL_DR | PSL_IR); 868 pmap_bootstrapped++; 869 bs_remap_earlyboot(); 870 871 /* 872 * Set the start and end of kva. 873 */ 874 virtual_avail = VM_MIN_KERNEL_ADDRESS; 875 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 876 877 /* 878 * Map the entire KVA range into the SLB. We must not fault there. 879 */ 880 #ifdef __powerpc64__ 881 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 882 moea64_bootstrap_slb_prefault(va, 0); 883 #endif 884 885 /* 886 * Figure out how far we can extend virtual_end into segment 16 887 * without running into existing mappings. Segment 16 is guaranteed 888 * to contain neither RAM nor devices (at least on Apple hardware), 889 * but will generally contain some OFW mappings we should not 890 * step on. 891 */ 892 893 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 894 PMAP_LOCK(kernel_pmap); 895 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 896 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 897 virtual_end += PAGE_SIZE; 898 PMAP_UNLOCK(kernel_pmap); 899 #endif 900 901 /* 902 * Allocate a kernel stack with a guard page for thread0 and map it 903 * into the kernel page map. 904 */ 905 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 906 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 907 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 908 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 909 thread0.td_kstack = va; 910 thread0.td_kstack_pages = KSTACK_PAGES; 911 for (i = 0; i < KSTACK_PAGES; i++) { 912 moea64_kenter(mmup, va, pa); 913 pa += PAGE_SIZE; 914 va += PAGE_SIZE; 915 } 916 917 /* 918 * Allocate virtual address space for the message buffer. 919 */ 920 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 921 msgbufp = (struct msgbuf *)virtual_avail; 922 va = virtual_avail; 923 virtual_avail += round_page(msgbufsize); 924 while (va < virtual_avail) { 925 moea64_kenter(mmup, va, pa); 926 pa += PAGE_SIZE; 927 va += PAGE_SIZE; 928 } 929 930 /* 931 * Allocate virtual address space for the dynamic percpu area. 932 */ 933 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 934 dpcpu = (void *)virtual_avail; 935 va = virtual_avail; 936 virtual_avail += DPCPU_SIZE; 937 while (va < virtual_avail) { 938 moea64_kenter(mmup, va, pa); 939 pa += PAGE_SIZE; 940 va += PAGE_SIZE; 941 } 942 dpcpu_init(dpcpu, 0); 943 944 /* 945 * Allocate some things for page zeroing. We put this directly 946 * in the page table, marked with LPTE_LOCKED, to avoid any 947 * of the PVO book-keeping or other parts of the VM system 948 * from even knowing that this hack exists. 949 */ 950 951 if (!hw_direct_map) { 952 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 953 MTX_DEF); 954 for (i = 0; i < 2; i++) { 955 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 956 virtual_end -= PAGE_SIZE; 957 958 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 959 960 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 961 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 962 LOCK_TABLE_RD(); 963 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 964 mmup, moea64_scratchpage_pvo[i]); 965 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 966 |= LPTE_LOCKED; 967 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 968 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 969 moea64_scratchpage_pvo[i]->pvo_vpn); 970 UNLOCK_TABLE_RD(); 971 } 972 } 973 } 974 975 /* 976 * Activate a user pmap. The pmap must be activated before its address 977 * space can be accessed in any way. 978 */ 979 void 980 moea64_activate(mmu_t mmu, struct thread *td) 981 { 982 pmap_t pm; 983 984 pm = &td->td_proc->p_vmspace->vm_pmap; 985 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 986 987 #ifdef __powerpc64__ 988 PCPU_SET(userslb, pm->pm_slb); 989 #else 990 PCPU_SET(curpmap, pm->pmap_phys); 991 #endif 992 } 993 994 void 995 moea64_deactivate(mmu_t mmu, struct thread *td) 996 { 997 pmap_t pm; 998 999 pm = &td->td_proc->p_vmspace->vm_pmap; 1000 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1001 #ifdef __powerpc64__ 1002 PCPU_SET(userslb, NULL); 1003 #else 1004 PCPU_SET(curpmap, NULL); 1005 #endif 1006 } 1007 1008 void 1009 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1010 { 1011 struct pvo_entry *pvo; 1012 uintptr_t pt; 1013 uint64_t vsid; 1014 int i, ptegidx; 1015 1016 LOCK_TABLE_WR(); 1017 PMAP_LOCK(pm); 1018 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1019 1020 if (pvo != NULL) { 1021 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1022 1023 if (wired) { 1024 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1025 pm->pm_stats.wired_count++; 1026 pvo->pvo_vaddr |= PVO_WIRED; 1027 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1028 } else { 1029 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1030 pm->pm_stats.wired_count--; 1031 pvo->pvo_vaddr &= ~PVO_WIRED; 1032 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1033 } 1034 1035 if (pt != -1) { 1036 /* Update wiring flag in page table. */ 1037 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1038 pvo->pvo_vpn); 1039 } else if (wired) { 1040 /* 1041 * If we are wiring the page, and it wasn't in the 1042 * page table before, add it. 1043 */ 1044 vsid = PVO_VSID(pvo); 1045 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1046 pvo->pvo_vaddr & PVO_LARGE); 1047 1048 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1049 1050 if (i >= 0) { 1051 PVO_PTEGIDX_CLR(pvo); 1052 PVO_PTEGIDX_SET(pvo, i); 1053 } 1054 } 1055 1056 } 1057 UNLOCK_TABLE_WR(); 1058 PMAP_UNLOCK(pm); 1059 } 1060 1061 /* 1062 * This goes through and sets the physical address of our 1063 * special scratch PTE to the PA we want to zero or copy. Because 1064 * of locking issues (this can get called in pvo_enter() by 1065 * the UMA allocator), we can't use most other utility functions here 1066 */ 1067 1068 static __inline 1069 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1070 1071 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1072 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1073 1074 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1075 ~(LPTE_WIMG | LPTE_RPGN); 1076 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1077 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1078 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1079 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1080 moea64_scratchpage_pvo[which]->pvo_vpn); 1081 isync(); 1082 } 1083 1084 void 1085 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1086 { 1087 vm_offset_t dst; 1088 vm_offset_t src; 1089 1090 dst = VM_PAGE_TO_PHYS(mdst); 1091 src = VM_PAGE_TO_PHYS(msrc); 1092 1093 if (hw_direct_map) { 1094 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1095 } else { 1096 mtx_lock(&moea64_scratchpage_mtx); 1097 1098 moea64_set_scratchpage_pa(mmu, 0, src); 1099 moea64_set_scratchpage_pa(mmu, 1, dst); 1100 1101 bcopy((void *)moea64_scratchpage_va[0], 1102 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1103 1104 mtx_unlock(&moea64_scratchpage_mtx); 1105 } 1106 } 1107 1108 void 1109 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1110 { 1111 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1112 1113 if (size + off > PAGE_SIZE) 1114 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1115 1116 if (hw_direct_map) { 1117 bzero((caddr_t)pa + off, size); 1118 } else { 1119 mtx_lock(&moea64_scratchpage_mtx); 1120 moea64_set_scratchpage_pa(mmu, 0, pa); 1121 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1122 mtx_unlock(&moea64_scratchpage_mtx); 1123 } 1124 } 1125 1126 /* 1127 * Zero a page of physical memory by temporarily mapping it 1128 */ 1129 void 1130 moea64_zero_page(mmu_t mmu, vm_page_t m) 1131 { 1132 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1133 vm_offset_t va, off; 1134 1135 if (!hw_direct_map) { 1136 mtx_lock(&moea64_scratchpage_mtx); 1137 1138 moea64_set_scratchpage_pa(mmu, 0, pa); 1139 va = moea64_scratchpage_va[0]; 1140 } else { 1141 va = pa; 1142 } 1143 1144 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1145 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1146 1147 if (!hw_direct_map) 1148 mtx_unlock(&moea64_scratchpage_mtx); 1149 } 1150 1151 void 1152 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1153 { 1154 1155 moea64_zero_page(mmu, m); 1156 } 1157 1158 /* 1159 * Map the given physical page at the specified virtual address in the 1160 * target pmap with the protection requested. If specified the page 1161 * will be wired down. 1162 */ 1163 1164 void 1165 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1166 vm_prot_t prot, boolean_t wired) 1167 { 1168 struct pvo_head *pvo_head; 1169 uma_zone_t zone; 1170 vm_page_t pg; 1171 uint64_t pte_lo; 1172 u_int pvo_flags; 1173 int error; 1174 1175 if (!moea64_initialized) { 1176 pvo_head = NULL; 1177 pg = NULL; 1178 zone = moea64_upvo_zone; 1179 pvo_flags = 0; 1180 } else { 1181 pvo_head = vm_page_to_pvoh(m); 1182 pg = m; 1183 zone = moea64_mpvo_zone; 1184 pvo_flags = PVO_MANAGED; 1185 } 1186 1187 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1188 VM_OBJECT_LOCKED(m->object), 1189 ("moea64_enter: page %p is not busy", m)); 1190 1191 /* XXX change the pvo head for fake pages */ 1192 if ((m->oflags & VPO_UNMANAGED) != 0) { 1193 pvo_flags &= ~PVO_MANAGED; 1194 pvo_head = NULL; 1195 zone = moea64_upvo_zone; 1196 } 1197 1198 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1199 1200 if (prot & VM_PROT_WRITE) { 1201 pte_lo |= LPTE_BW; 1202 if (pmap_bootstrapped && 1203 (m->oflags & VPO_UNMANAGED) == 0) 1204 vm_page_aflag_set(m, PGA_WRITEABLE); 1205 } else 1206 pte_lo |= LPTE_BR; 1207 1208 if ((prot & VM_PROT_EXECUTE) == 0) 1209 pte_lo |= LPTE_NOEXEC; 1210 1211 if (wired) 1212 pvo_flags |= PVO_WIRED; 1213 1214 LOCK_TABLE_WR(); 1215 PMAP_LOCK(pmap); 1216 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1217 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1218 PMAP_UNLOCK(pmap); 1219 UNLOCK_TABLE_WR(); 1220 1221 /* 1222 * Flush the page from the instruction cache if this page is 1223 * mapped executable and cacheable. 1224 */ 1225 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1226 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1227 vm_page_aflag_set(m, PGA_EXECUTABLE); 1228 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1229 } 1230 } 1231 1232 static void 1233 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1234 vm_size_t sz) 1235 { 1236 1237 /* 1238 * This is much trickier than on older systems because 1239 * we can't sync the icache on physical addresses directly 1240 * without a direct map. Instead we check a couple of cases 1241 * where the memory is already mapped in and, failing that, 1242 * use the same trick we use for page zeroing to create 1243 * a temporary mapping for this physical address. 1244 */ 1245 1246 if (!pmap_bootstrapped) { 1247 /* 1248 * If PMAP is not bootstrapped, we are likely to be 1249 * in real mode. 1250 */ 1251 __syncicache((void *)pa, sz); 1252 } else if (pmap == kernel_pmap) { 1253 __syncicache((void *)va, sz); 1254 } else if (hw_direct_map) { 1255 __syncicache((void *)pa, sz); 1256 } else { 1257 /* Use the scratch page to set up a temp mapping */ 1258 1259 mtx_lock(&moea64_scratchpage_mtx); 1260 1261 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1262 __syncicache((void *)(moea64_scratchpage_va[1] + 1263 (va & ADDR_POFF)), sz); 1264 1265 mtx_unlock(&moea64_scratchpage_mtx); 1266 } 1267 } 1268 1269 /* 1270 * Maps a sequence of resident pages belonging to the same object. 1271 * The sequence begins with the given page m_start. This page is 1272 * mapped at the given virtual address start. Each subsequent page is 1273 * mapped at a virtual address that is offset from start by the same 1274 * amount as the page is offset from m_start within the object. The 1275 * last page in the sequence is the page with the largest offset from 1276 * m_start that can be mapped at a virtual address less than the given 1277 * virtual address end. Not every virtual page between start and end 1278 * is mapped; only those for which a resident page exists with the 1279 * corresponding offset from m_start are mapped. 1280 */ 1281 void 1282 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1283 vm_page_t m_start, vm_prot_t prot) 1284 { 1285 vm_page_t m; 1286 vm_pindex_t diff, psize; 1287 1288 psize = atop(end - start); 1289 m = m_start; 1290 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1291 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1292 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1293 m = TAILQ_NEXT(m, listq); 1294 } 1295 } 1296 1297 void 1298 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1299 vm_prot_t prot) 1300 { 1301 1302 moea64_enter(mmu, pm, va, m, 1303 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1304 } 1305 1306 vm_paddr_t 1307 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1308 { 1309 struct pvo_entry *pvo; 1310 vm_paddr_t pa; 1311 1312 PMAP_LOCK(pm); 1313 pvo = moea64_pvo_find_va(pm, va); 1314 if (pvo == NULL) 1315 pa = 0; 1316 else 1317 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1318 (va - PVO_VADDR(pvo)); 1319 PMAP_UNLOCK(pm); 1320 return (pa); 1321 } 1322 1323 /* 1324 * Atomically extract and hold the physical page with the given 1325 * pmap and virtual address pair if that mapping permits the given 1326 * protection. 1327 */ 1328 vm_page_t 1329 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1330 { 1331 struct pvo_entry *pvo; 1332 vm_page_t m; 1333 vm_paddr_t pa; 1334 1335 m = NULL; 1336 pa = 0; 1337 PMAP_LOCK(pmap); 1338 retry: 1339 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1340 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1341 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1342 (prot & VM_PROT_WRITE) == 0)) { 1343 if (vm_page_pa_tryrelock(pmap, 1344 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1345 goto retry; 1346 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1347 vm_page_hold(m); 1348 } 1349 PA_UNLOCK_COND(pa); 1350 PMAP_UNLOCK(pmap); 1351 return (m); 1352 } 1353 1354 static mmu_t installed_mmu; 1355 1356 static void * 1357 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1358 { 1359 /* 1360 * This entire routine is a horrible hack to avoid bothering kmem 1361 * for new KVA addresses. Because this can get called from inside 1362 * kmem allocation routines, calling kmem for a new address here 1363 * can lead to multiply locking non-recursive mutexes. 1364 */ 1365 vm_offset_t va; 1366 1367 vm_page_t m; 1368 int pflags, needed_lock; 1369 1370 *flags = UMA_SLAB_PRIV; 1371 needed_lock = !PMAP_LOCKED(kernel_pmap); 1372 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1373 1374 for (;;) { 1375 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1376 if (m == NULL) { 1377 if (wait & M_NOWAIT) 1378 return (NULL); 1379 VM_WAIT; 1380 } else 1381 break; 1382 } 1383 1384 va = VM_PAGE_TO_PHYS(m); 1385 1386 LOCK_TABLE_WR(); 1387 if (needed_lock) 1388 PMAP_LOCK(kernel_pmap); 1389 1390 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1391 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP); 1392 1393 if (needed_lock) 1394 PMAP_UNLOCK(kernel_pmap); 1395 UNLOCK_TABLE_WR(); 1396 1397 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1398 bzero((void *)va, PAGE_SIZE); 1399 1400 return (void *)va; 1401 } 1402 1403 extern int elf32_nxstack; 1404 1405 void 1406 moea64_init(mmu_t mmu) 1407 { 1408 1409 CTR0(KTR_PMAP, "moea64_init"); 1410 1411 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1412 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1413 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1414 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1415 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1416 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1417 1418 if (!hw_direct_map) { 1419 installed_mmu = mmu; 1420 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1421 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1422 } 1423 1424 #ifdef COMPAT_FREEBSD32 1425 elf32_nxstack = 1; 1426 #endif 1427 1428 moea64_initialized = TRUE; 1429 } 1430 1431 boolean_t 1432 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1433 { 1434 1435 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1436 ("moea64_is_referenced: page %p is not managed", m)); 1437 return (moea64_query_bit(mmu, m, PTE_REF)); 1438 } 1439 1440 boolean_t 1441 moea64_is_modified(mmu_t mmu, vm_page_t m) 1442 { 1443 1444 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1445 ("moea64_is_modified: page %p is not managed", m)); 1446 1447 /* 1448 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1449 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1450 * is clear, no PTEs can have LPTE_CHG set. 1451 */ 1452 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1453 if ((m->oflags & VPO_BUSY) == 0 && 1454 (m->aflags & PGA_WRITEABLE) == 0) 1455 return (FALSE); 1456 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1457 } 1458 1459 boolean_t 1460 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1461 { 1462 struct pvo_entry *pvo; 1463 boolean_t rv; 1464 1465 PMAP_LOCK(pmap); 1466 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1467 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1468 PMAP_UNLOCK(pmap); 1469 return (rv); 1470 } 1471 1472 void 1473 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1474 { 1475 1476 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1477 ("moea64_clear_reference: page %p is not managed", m)); 1478 moea64_clear_bit(mmu, m, LPTE_REF); 1479 } 1480 1481 void 1482 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1483 { 1484 1485 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1486 ("moea64_clear_modify: page %p is not managed", m)); 1487 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1488 KASSERT((m->oflags & VPO_BUSY) == 0, 1489 ("moea64_clear_modify: page %p is busy", m)); 1490 1491 /* 1492 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1493 * set. If the object containing the page is locked and the page is 1494 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1495 */ 1496 if ((m->aflags & PGA_WRITEABLE) == 0) 1497 return; 1498 moea64_clear_bit(mmu, m, LPTE_CHG); 1499 } 1500 1501 /* 1502 * Clear the write and modified bits in each of the given page's mappings. 1503 */ 1504 void 1505 moea64_remove_write(mmu_t mmu, vm_page_t m) 1506 { 1507 struct pvo_entry *pvo; 1508 uintptr_t pt; 1509 pmap_t pmap; 1510 uint64_t lo = 0; 1511 1512 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1513 ("moea64_remove_write: page %p is not managed", m)); 1514 1515 /* 1516 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1517 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1518 * is clear, no page table entries need updating. 1519 */ 1520 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1521 if ((m->oflags & VPO_BUSY) == 0 && 1522 (m->aflags & PGA_WRITEABLE) == 0) 1523 return; 1524 powerpc_sync(); 1525 LOCK_TABLE_RD(); 1526 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1527 pmap = pvo->pvo_pmap; 1528 PMAP_LOCK(pmap); 1529 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1530 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1531 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1532 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1533 if (pt != -1) { 1534 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1535 lo |= pvo->pvo_pte.lpte.pte_lo; 1536 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1537 MOEA64_PTE_CHANGE(mmu, pt, 1538 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1539 if (pvo->pvo_pmap == kernel_pmap) 1540 isync(); 1541 } 1542 } 1543 if ((lo & LPTE_CHG) != 0) 1544 vm_page_dirty(m); 1545 PMAP_UNLOCK(pmap); 1546 } 1547 UNLOCK_TABLE_RD(); 1548 vm_page_aflag_clear(m, PGA_WRITEABLE); 1549 } 1550 1551 /* 1552 * moea64_ts_referenced: 1553 * 1554 * Return a count of reference bits for a page, clearing those bits. 1555 * It is not necessary for every reference bit to be cleared, but it 1556 * is necessary that 0 only be returned when there are truly no 1557 * reference bits set. 1558 * 1559 * XXX: The exact number of bits to check and clear is a matter that 1560 * should be tested and standardized at some point in the future for 1561 * optimal aging of shared pages. 1562 */ 1563 int 1564 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1565 { 1566 1567 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1568 ("moea64_ts_referenced: page %p is not managed", m)); 1569 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1570 } 1571 1572 /* 1573 * Modify the WIMG settings of all mappings for a page. 1574 */ 1575 void 1576 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1577 { 1578 struct pvo_entry *pvo; 1579 struct pvo_head *pvo_head; 1580 uintptr_t pt; 1581 pmap_t pmap; 1582 uint64_t lo; 1583 1584 if ((m->oflags & VPO_UNMANAGED) != 0) { 1585 m->md.mdpg_cache_attrs = ma; 1586 return; 1587 } 1588 1589 pvo_head = vm_page_to_pvoh(m); 1590 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1591 LOCK_TABLE_RD(); 1592 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1593 pmap = pvo->pvo_pmap; 1594 PMAP_LOCK(pmap); 1595 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1596 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1597 pvo->pvo_pte.lpte.pte_lo |= lo; 1598 if (pt != -1) { 1599 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1600 pvo->pvo_vpn); 1601 if (pvo->pvo_pmap == kernel_pmap) 1602 isync(); 1603 } 1604 PMAP_UNLOCK(pmap); 1605 } 1606 UNLOCK_TABLE_RD(); 1607 m->md.mdpg_cache_attrs = ma; 1608 } 1609 1610 /* 1611 * Map a wired page into kernel virtual address space. 1612 */ 1613 void 1614 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1615 { 1616 uint64_t pte_lo; 1617 int error; 1618 1619 pte_lo = moea64_calc_wimg(pa, ma); 1620 1621 LOCK_TABLE_WR(); 1622 PMAP_LOCK(kernel_pmap); 1623 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1624 NULL, va, pa, pte_lo, PVO_WIRED); 1625 PMAP_UNLOCK(kernel_pmap); 1626 UNLOCK_TABLE_WR(); 1627 1628 if (error != 0 && error != ENOENT) 1629 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1630 pa, error); 1631 } 1632 1633 void 1634 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1635 { 1636 1637 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1638 } 1639 1640 /* 1641 * Extract the physical page address associated with the given kernel virtual 1642 * address. 1643 */ 1644 vm_paddr_t 1645 moea64_kextract(mmu_t mmu, vm_offset_t va) 1646 { 1647 struct pvo_entry *pvo; 1648 vm_paddr_t pa; 1649 1650 /* 1651 * Shortcut the direct-mapped case when applicable. We never put 1652 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1653 */ 1654 if (va < VM_MIN_KERNEL_ADDRESS) 1655 return (va); 1656 1657 PMAP_LOCK(kernel_pmap); 1658 pvo = moea64_pvo_find_va(kernel_pmap, va); 1659 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1660 va)); 1661 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1662 PMAP_UNLOCK(kernel_pmap); 1663 return (pa); 1664 } 1665 1666 /* 1667 * Remove a wired page from kernel virtual address space. 1668 */ 1669 void 1670 moea64_kremove(mmu_t mmu, vm_offset_t va) 1671 { 1672 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1673 } 1674 1675 /* 1676 * Map a range of physical addresses into kernel virtual address space. 1677 * 1678 * The value passed in *virt is a suggested virtual address for the mapping. 1679 * Architectures which can support a direct-mapped physical to virtual region 1680 * can return the appropriate address within that region, leaving '*virt' 1681 * unchanged. We cannot and therefore do not; *virt is updated with the 1682 * first usable address after the mapped region. 1683 */ 1684 vm_offset_t 1685 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1686 vm_paddr_t pa_end, int prot) 1687 { 1688 vm_offset_t sva, va; 1689 1690 sva = *virt; 1691 va = sva; 1692 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1693 moea64_kenter(mmu, va, pa_start); 1694 *virt = va; 1695 1696 return (sva); 1697 } 1698 1699 /* 1700 * Returns true if the pmap's pv is one of the first 1701 * 16 pvs linked to from this page. This count may 1702 * be changed upwards or downwards in the future; it 1703 * is only necessary that true be returned for a small 1704 * subset of pmaps for proper page aging. 1705 */ 1706 boolean_t 1707 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1708 { 1709 int loops; 1710 struct pvo_entry *pvo; 1711 boolean_t rv; 1712 1713 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1714 ("moea64_page_exists_quick: page %p is not managed", m)); 1715 loops = 0; 1716 rv = FALSE; 1717 LOCK_TABLE_RD(); 1718 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1719 if (pvo->pvo_pmap == pmap) { 1720 rv = TRUE; 1721 break; 1722 } 1723 if (++loops >= 16) 1724 break; 1725 } 1726 UNLOCK_TABLE_RD(); 1727 return (rv); 1728 } 1729 1730 /* 1731 * Return the number of managed mappings to the given physical page 1732 * that are wired. 1733 */ 1734 int 1735 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1736 { 1737 struct pvo_entry *pvo; 1738 int count; 1739 1740 count = 0; 1741 if ((m->oflags & VPO_UNMANAGED) != 0) 1742 return (count); 1743 LOCK_TABLE_RD(); 1744 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1745 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1746 count++; 1747 UNLOCK_TABLE_RD(); 1748 return (count); 1749 } 1750 1751 static uintptr_t moea64_vsidcontext; 1752 1753 uintptr_t 1754 moea64_get_unique_vsid(void) { 1755 u_int entropy; 1756 register_t hash; 1757 uint32_t mask; 1758 int i; 1759 1760 entropy = 0; 1761 __asm __volatile("mftb %0" : "=r"(entropy)); 1762 1763 mtx_lock(&moea64_slb_mutex); 1764 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1765 u_int n; 1766 1767 /* 1768 * Create a new value by mutiplying by a prime and adding in 1769 * entropy from the timebase register. This is to make the 1770 * VSID more random so that the PT hash function collides 1771 * less often. (Note that the prime casues gcc to do shifts 1772 * instead of a multiply.) 1773 */ 1774 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1775 hash = moea64_vsidcontext & (NVSIDS - 1); 1776 if (hash == 0) /* 0 is special, avoid it */ 1777 continue; 1778 n = hash >> 5; 1779 mask = 1 << (hash & (VSID_NBPW - 1)); 1780 hash = (moea64_vsidcontext & VSID_HASHMASK); 1781 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1782 /* anything free in this bucket? */ 1783 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1784 entropy = (moea64_vsidcontext >> 20); 1785 continue; 1786 } 1787 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1788 mask = 1 << i; 1789 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1790 hash |= i; 1791 } 1792 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1793 ("Allocating in-use VSID %#zx\n", hash)); 1794 moea64_vsid_bitmap[n] |= mask; 1795 mtx_unlock(&moea64_slb_mutex); 1796 return (hash); 1797 } 1798 1799 mtx_unlock(&moea64_slb_mutex); 1800 panic("%s: out of segments",__func__); 1801 } 1802 1803 #ifdef __powerpc64__ 1804 void 1805 moea64_pinit(mmu_t mmu, pmap_t pmap) 1806 { 1807 PMAP_LOCK_INIT(pmap); 1808 RB_INIT(&pmap->pmap_pvo); 1809 1810 pmap->pm_slb_tree_root = slb_alloc_tree(); 1811 pmap->pm_slb = slb_alloc_user_cache(); 1812 pmap->pm_slb_len = 0; 1813 } 1814 #else 1815 void 1816 moea64_pinit(mmu_t mmu, pmap_t pmap) 1817 { 1818 int i; 1819 uint32_t hash; 1820 1821 PMAP_LOCK_INIT(pmap); 1822 RB_INIT(&pmap->pmap_pvo); 1823 1824 if (pmap_bootstrapped) 1825 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1826 (vm_offset_t)pmap); 1827 else 1828 pmap->pmap_phys = pmap; 1829 1830 /* 1831 * Allocate some segment registers for this pmap. 1832 */ 1833 hash = moea64_get_unique_vsid(); 1834 1835 for (i = 0; i < 16; i++) 1836 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1837 1838 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1839 } 1840 #endif 1841 1842 /* 1843 * Initialize the pmap associated with process 0. 1844 */ 1845 void 1846 moea64_pinit0(mmu_t mmu, pmap_t pm) 1847 { 1848 moea64_pinit(mmu, pm); 1849 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1850 } 1851 1852 /* 1853 * Set the physical protection on the specified range of this map as requested. 1854 */ 1855 static void 1856 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1857 { 1858 uintptr_t pt; 1859 struct vm_page *pg; 1860 uint64_t oldlo; 1861 1862 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1863 1864 /* 1865 * Grab the PTE pointer before we diddle with the cached PTE 1866 * copy. 1867 */ 1868 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1869 1870 /* 1871 * Change the protection of the page. 1872 */ 1873 oldlo = pvo->pvo_pte.lpte.pte_lo; 1874 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1875 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1876 if ((prot & VM_PROT_EXECUTE) == 0) 1877 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1878 if (prot & VM_PROT_WRITE) 1879 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1880 else 1881 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1882 1883 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1884 1885 /* 1886 * If the PVO is in the page table, update that pte as well. 1887 */ 1888 if (pt != -1) 1889 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1890 pvo->pvo_vpn); 1891 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1892 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1893 if ((pg->oflags & VPO_UNMANAGED) == 0) 1894 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1895 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1896 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1897 } 1898 1899 /* 1900 * Update vm about the REF/CHG bits if the page is managed and we have 1901 * removed write access. 1902 */ 1903 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1904 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) { 1905 if (pg != NULL) { 1906 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1907 vm_page_dirty(pg); 1908 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1909 vm_page_aflag_set(pg, PGA_REFERENCED); 1910 } 1911 } 1912 } 1913 1914 void 1915 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1916 vm_prot_t prot) 1917 { 1918 struct pvo_entry *pvo, *tpvo, key; 1919 1920 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1921 sva, eva, prot); 1922 1923 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1924 ("moea64_protect: non current pmap")); 1925 1926 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1927 moea64_remove(mmu, pm, sva, eva); 1928 return; 1929 } 1930 1931 LOCK_TABLE_RD(); 1932 PMAP_LOCK(pm); 1933 key.pvo_vaddr = sva; 1934 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1935 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1936 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1937 moea64_pvo_protect(mmu, pm, pvo, prot); 1938 } 1939 UNLOCK_TABLE_RD(); 1940 PMAP_UNLOCK(pm); 1941 } 1942 1943 /* 1944 * Map a list of wired pages into kernel virtual address space. This is 1945 * intended for temporary mappings which do not need page modification or 1946 * references recorded. Existing mappings in the region are overwritten. 1947 */ 1948 void 1949 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1950 { 1951 while (count-- > 0) { 1952 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1953 va += PAGE_SIZE; 1954 m++; 1955 } 1956 } 1957 1958 /* 1959 * Remove page mappings from kernel virtual address space. Intended for 1960 * temporary mappings entered by moea64_qenter. 1961 */ 1962 void 1963 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1964 { 1965 while (count-- > 0) { 1966 moea64_kremove(mmu, va); 1967 va += PAGE_SIZE; 1968 } 1969 } 1970 1971 void 1972 moea64_release_vsid(uint64_t vsid) 1973 { 1974 int idx, mask; 1975 1976 mtx_lock(&moea64_slb_mutex); 1977 idx = vsid & (NVSIDS-1); 1978 mask = 1 << (idx % VSID_NBPW); 1979 idx /= VSID_NBPW; 1980 KASSERT(moea64_vsid_bitmap[idx] & mask, 1981 ("Freeing unallocated VSID %#jx", vsid)); 1982 moea64_vsid_bitmap[idx] &= ~mask; 1983 mtx_unlock(&moea64_slb_mutex); 1984 } 1985 1986 1987 void 1988 moea64_release(mmu_t mmu, pmap_t pmap) 1989 { 1990 1991 /* 1992 * Free segment registers' VSIDs 1993 */ 1994 #ifdef __powerpc64__ 1995 slb_free_tree(pmap); 1996 slb_free_user_cache(pmap->pm_slb); 1997 #else 1998 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 1999 2000 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2001 #endif 2002 2003 PMAP_LOCK_DESTROY(pmap); 2004 } 2005 2006 /* 2007 * Remove all pages mapped by the specified pmap 2008 */ 2009 void 2010 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2011 { 2012 struct pvo_entry *pvo, *tpvo; 2013 2014 LOCK_TABLE_WR(); 2015 PMAP_LOCK(pm); 2016 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2017 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2018 moea64_pvo_remove(mmu, pvo); 2019 } 2020 UNLOCK_TABLE_WR(); 2021 PMAP_UNLOCK(pm); 2022 } 2023 2024 /* 2025 * Remove the given range of addresses from the specified map. 2026 */ 2027 void 2028 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2029 { 2030 struct pvo_entry *pvo, *tpvo, key; 2031 2032 /* 2033 * Perform an unsynchronized read. This is, however, safe. 2034 */ 2035 if (pm->pm_stats.resident_count == 0) 2036 return; 2037 2038 LOCK_TABLE_WR(); 2039 PMAP_LOCK(pm); 2040 key.pvo_vaddr = sva; 2041 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2042 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2043 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2044 moea64_pvo_remove(mmu, pvo); 2045 } 2046 UNLOCK_TABLE_WR(); 2047 PMAP_UNLOCK(pm); 2048 } 2049 2050 /* 2051 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2052 * will reflect changes in pte's back to the vm_page. 2053 */ 2054 void 2055 moea64_remove_all(mmu_t mmu, vm_page_t m) 2056 { 2057 struct pvo_entry *pvo, *next_pvo; 2058 pmap_t pmap; 2059 2060 LOCK_TABLE_WR(); 2061 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2062 pmap = pvo->pvo_pmap; 2063 PMAP_LOCK(pmap); 2064 moea64_pvo_remove(mmu, pvo); 2065 PMAP_UNLOCK(pmap); 2066 } 2067 UNLOCK_TABLE_WR(); 2068 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2069 vm_page_dirty(m); 2070 vm_page_aflag_clear(m, PGA_WRITEABLE); 2071 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2072 } 2073 2074 /* 2075 * Allocate a physical page of memory directly from the phys_avail map. 2076 * Can only be called from moea64_bootstrap before avail start and end are 2077 * calculated. 2078 */ 2079 vm_offset_t 2080 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2081 { 2082 vm_offset_t s, e; 2083 int i, j; 2084 2085 size = round_page(size); 2086 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2087 if (align != 0) 2088 s = (phys_avail[i] + align - 1) & ~(align - 1); 2089 else 2090 s = phys_avail[i]; 2091 e = s + size; 2092 2093 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2094 continue; 2095 2096 if (s + size > platform_real_maxaddr()) 2097 continue; 2098 2099 if (s == phys_avail[i]) { 2100 phys_avail[i] += size; 2101 } else if (e == phys_avail[i + 1]) { 2102 phys_avail[i + 1] -= size; 2103 } else { 2104 for (j = phys_avail_count * 2; j > i; j -= 2) { 2105 phys_avail[j] = phys_avail[j - 2]; 2106 phys_avail[j + 1] = phys_avail[j - 1]; 2107 } 2108 2109 phys_avail[i + 3] = phys_avail[i + 1]; 2110 phys_avail[i + 1] = s; 2111 phys_avail[i + 2] = e; 2112 phys_avail_count++; 2113 } 2114 2115 return (s); 2116 } 2117 panic("moea64_bootstrap_alloc: could not allocate memory"); 2118 } 2119 2120 static int 2121 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2122 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2123 uint64_t pte_lo, int flags) 2124 { 2125 struct pvo_entry *pvo; 2126 uint64_t vsid; 2127 int first; 2128 u_int ptegidx; 2129 int i; 2130 int bootstrap; 2131 2132 /* 2133 * One nasty thing that can happen here is that the UMA calls to 2134 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2135 * which calls UMA... 2136 * 2137 * We break the loop by detecting recursion and allocating out of 2138 * the bootstrap pool. 2139 */ 2140 2141 first = 0; 2142 bootstrap = (flags & PVO_BOOTSTRAP); 2143 2144 if (!moea64_initialized) 2145 bootstrap = 1; 2146 2147 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2148 rw_assert(&moea64_table_lock, RA_WLOCKED); 2149 2150 /* 2151 * Compute the PTE Group index. 2152 */ 2153 va &= ~ADDR_POFF; 2154 vsid = va_to_vsid(pm, va); 2155 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2156 2157 /* 2158 * Remove any existing mapping for this page. Reuse the pvo entry if 2159 * there is a mapping. 2160 */ 2161 moea64_pvo_enter_calls++; 2162 2163 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2164 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2165 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2166 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2167 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2168 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2169 /* Re-insert if spilled */ 2170 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2171 &pvo->pvo_pte.lpte); 2172 if (i >= 0) 2173 PVO_PTEGIDX_SET(pvo, i); 2174 moea64_pte_overflow--; 2175 } 2176 return (0); 2177 } 2178 moea64_pvo_remove(mmu, pvo); 2179 break; 2180 } 2181 } 2182 2183 /* 2184 * If we aren't overwriting a mapping, try to allocate. 2185 */ 2186 if (bootstrap) { 2187 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2188 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2189 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2190 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2191 } 2192 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2193 moea64_bpvo_pool_index++; 2194 bootstrap = 1; 2195 } else { 2196 pvo = uma_zalloc(zone, M_NOWAIT); 2197 } 2198 2199 if (pvo == NULL) 2200 return (ENOMEM); 2201 2202 moea64_pvo_entries++; 2203 pvo->pvo_vaddr = va; 2204 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2205 | (vsid << 16); 2206 pvo->pvo_pmap = pm; 2207 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2208 pvo->pvo_vaddr &= ~ADDR_POFF; 2209 2210 if (flags & PVO_WIRED) 2211 pvo->pvo_vaddr |= PVO_WIRED; 2212 if (pvo_head != NULL) 2213 pvo->pvo_vaddr |= PVO_MANAGED; 2214 if (bootstrap) 2215 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2216 if (flags & PVO_LARGE) 2217 pvo->pvo_vaddr |= PVO_LARGE; 2218 2219 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2220 (uint64_t)(pa) | pte_lo, flags); 2221 2222 /* 2223 * Add to pmap list 2224 */ 2225 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2226 2227 /* 2228 * Remember if the list was empty and therefore will be the first 2229 * item. 2230 */ 2231 if (pvo_head != NULL) { 2232 if (LIST_FIRST(pvo_head) == NULL) 2233 first = 1; 2234 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2235 } 2236 2237 if (pvo->pvo_vaddr & PVO_WIRED) { 2238 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2239 pm->pm_stats.wired_count++; 2240 } 2241 pm->pm_stats.resident_count++; 2242 2243 /* 2244 * We hope this succeeds but it isn't required. 2245 */ 2246 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2247 if (i >= 0) { 2248 PVO_PTEGIDX_SET(pvo, i); 2249 } else { 2250 panic("moea64_pvo_enter: overflow"); 2251 moea64_pte_overflow++; 2252 } 2253 2254 if (pm == kernel_pmap) 2255 isync(); 2256 2257 #ifdef __powerpc64__ 2258 /* 2259 * Make sure all our bootstrap mappings are in the SLB as soon 2260 * as virtual memory is switched on. 2261 */ 2262 if (!pmap_bootstrapped) 2263 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2264 #endif 2265 2266 return (first ? ENOENT : 0); 2267 } 2268 2269 static void 2270 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2271 { 2272 struct vm_page *pg; 2273 uintptr_t pt; 2274 2275 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2276 rw_assert(&moea64_table_lock, RA_WLOCKED); 2277 2278 /* 2279 * If there is an active pte entry, we need to deactivate it (and 2280 * save the ref & cfg bits). 2281 */ 2282 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2283 if (pt != -1) { 2284 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2285 PVO_PTEGIDX_CLR(pvo); 2286 } else { 2287 moea64_pte_overflow--; 2288 } 2289 2290 /* 2291 * Update our statistics. 2292 */ 2293 pvo->pvo_pmap->pm_stats.resident_count--; 2294 if (pvo->pvo_vaddr & PVO_WIRED) 2295 pvo->pvo_pmap->pm_stats.wired_count--; 2296 2297 /* 2298 * Remove this PVO from the pmap list. 2299 */ 2300 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2301 2302 /* 2303 * Remove this from the overflow list and return it to the pool 2304 * if we aren't going to reuse it. 2305 */ 2306 LIST_REMOVE(pvo, pvo_olink); 2307 2308 /* 2309 * Update vm about the REF/CHG bits if the page is managed. 2310 */ 2311 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2312 2313 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2314 LIST_REMOVE(pvo, pvo_vlink); 2315 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2316 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2317 vm_page_dirty(pg); 2318 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2319 vm_page_aflag_set(pg, PGA_REFERENCED); 2320 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2321 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2322 } 2323 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2324 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2325 } 2326 2327 moea64_pvo_entries--; 2328 moea64_pvo_remove_calls++; 2329 2330 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2331 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2332 moea64_upvo_zone, pvo); 2333 } 2334 2335 static struct pvo_entry * 2336 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2337 { 2338 struct pvo_entry key; 2339 2340 key.pvo_vaddr = va & ~ADDR_POFF; 2341 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2342 } 2343 2344 static boolean_t 2345 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2346 { 2347 struct pvo_entry *pvo; 2348 uintptr_t pt; 2349 2350 LOCK_TABLE_RD(); 2351 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2352 /* 2353 * See if we saved the bit off. If so, return success. 2354 */ 2355 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2356 UNLOCK_TABLE_RD(); 2357 return (TRUE); 2358 } 2359 } 2360 2361 /* 2362 * No luck, now go through the hard part of looking at the PTEs 2363 * themselves. Sync so that any pending REF/CHG bits are flushed to 2364 * the PTEs. 2365 */ 2366 powerpc_sync(); 2367 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2368 2369 /* 2370 * See if this pvo has a valid PTE. if so, fetch the 2371 * REF/CHG bits from the valid PTE. If the appropriate 2372 * ptebit is set, return success. 2373 */ 2374 PMAP_LOCK(pvo->pvo_pmap); 2375 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2376 if (pt != -1) { 2377 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2378 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2379 PMAP_UNLOCK(pvo->pvo_pmap); 2380 UNLOCK_TABLE_RD(); 2381 return (TRUE); 2382 } 2383 } 2384 PMAP_UNLOCK(pvo->pvo_pmap); 2385 } 2386 2387 UNLOCK_TABLE_RD(); 2388 return (FALSE); 2389 } 2390 2391 static u_int 2392 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2393 { 2394 u_int count; 2395 struct pvo_entry *pvo; 2396 uintptr_t pt; 2397 2398 /* 2399 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2400 * we can reset the right ones). note that since the pvo entries and 2401 * list heads are accessed via BAT0 and are never placed in the page 2402 * table, we don't have to worry about further accesses setting the 2403 * REF/CHG bits. 2404 */ 2405 powerpc_sync(); 2406 2407 /* 2408 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2409 * valid pte clear the ptebit from the valid pte. 2410 */ 2411 count = 0; 2412 LOCK_TABLE_RD(); 2413 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2414 PMAP_LOCK(pvo->pvo_pmap); 2415 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2416 if (pt != -1) { 2417 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2418 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2419 count++; 2420 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2421 pvo->pvo_vpn, ptebit); 2422 } 2423 } 2424 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2425 PMAP_UNLOCK(pvo->pvo_pmap); 2426 } 2427 2428 UNLOCK_TABLE_RD(); 2429 return (count); 2430 } 2431 2432 boolean_t 2433 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2434 { 2435 struct pvo_entry *pvo, key; 2436 vm_offset_t ppa; 2437 int error = 0; 2438 2439 PMAP_LOCK(kernel_pmap); 2440 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2441 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2442 ppa < pa + size; ppa += PAGE_SIZE, 2443 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2444 if (pvo == NULL || 2445 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2446 error = EFAULT; 2447 break; 2448 } 2449 } 2450 PMAP_UNLOCK(kernel_pmap); 2451 2452 return (error); 2453 } 2454 2455 /* 2456 * Map a set of physical memory pages into the kernel virtual 2457 * address space. Return a pointer to where it is mapped. This 2458 * routine is intended to be used for mapping device memory, 2459 * NOT real memory. 2460 */ 2461 void * 2462 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2463 { 2464 vm_offset_t va, tmpva, ppa, offset; 2465 2466 ppa = trunc_page(pa); 2467 offset = pa & PAGE_MASK; 2468 size = roundup2(offset + size, PAGE_SIZE); 2469 2470 va = kmem_alloc_nofault(kernel_map, size); 2471 2472 if (!va) 2473 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2474 2475 for (tmpva = va; size > 0;) { 2476 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2477 size -= PAGE_SIZE; 2478 tmpva += PAGE_SIZE; 2479 ppa += PAGE_SIZE; 2480 } 2481 2482 return ((void *)(va + offset)); 2483 } 2484 2485 void * 2486 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2487 { 2488 2489 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2490 } 2491 2492 void 2493 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2494 { 2495 vm_offset_t base, offset; 2496 2497 base = trunc_page(va); 2498 offset = va & PAGE_MASK; 2499 size = roundup2(offset + size, PAGE_SIZE); 2500 2501 kmem_free(kernel_map, base, size); 2502 } 2503 2504 void 2505 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2506 { 2507 struct pvo_entry *pvo; 2508 vm_offset_t lim; 2509 vm_paddr_t pa; 2510 vm_size_t len; 2511 2512 PMAP_LOCK(pm); 2513 while (sz > 0) { 2514 lim = round_page(va); 2515 len = MIN(lim - va, sz); 2516 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2517 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2518 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2519 (va & ADDR_POFF); 2520 moea64_syncicache(mmu, pm, va, pa, len); 2521 } 2522 va += len; 2523 sz -= len; 2524 } 2525 PMAP_UNLOCK(pm); 2526 } 2527