1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/cpu.h> 146 #include <machine/platform.h> 147 #include <machine/frame.h> 148 #include <machine/md_var.h> 149 #include <machine/psl.h> 150 #include <machine/bat.h> 151 #include <machine/pte.h> 152 #include <machine/sr.h> 153 #include <machine/trap.h> 154 #include <machine/mmuvar.h> 155 156 #include "mmu_if.h" 157 158 #define MOEA_DEBUG 159 160 #define TODO panic("%s: not implemented", __func__); 161 162 static __inline u_int32_t 163 cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167 } 168 169 static __inline uint64_t 170 va_to_vsid(pmap_t pm, vm_offset_t va) 171 { 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173 } 174 175 #define PTESYNC() __asm __volatile("ptesync"); 176 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 177 #define SYNC() __asm __volatile("sync"); 178 #define EIEIO() __asm __volatile("eieio"); 179 180 /* 181 * The tlbie instruction must be executed in 64-bit mode 182 * so we have to twiddle MSR[SF] around every invocation. 183 * Just to add to the fun, exceptions must be off as well 184 * so that we can't trap in 64-bit mode. What a pain. 185 */ 186 struct mtx tlbie_mutex; 187 188 static __inline void 189 TLBIE(pmap_t pmap, vm_offset_t va) { 190 uint64_t vpn; 191 register_t vpn_hi, vpn_lo; 192 register_t msr; 193 register_t scratch; 194 195 vpn = (uint64_t)(va & ADDR_PIDX); 196 if (pmap != NULL) 197 vpn |= (va_to_vsid(pmap,va) << 28); 198 vpn &= ~(0xffffULL << 48); 199 200 vpn_hi = (uint32_t)(vpn >> 32); 201 vpn_lo = (uint32_t)vpn; 202 203 mtx_lock_spin(&tlbie_mutex); 204 __asm __volatile("\ 205 mfmsr %0; \ 206 mr %1, %0; \ 207 insrdi %1,%5,1,0; \ 208 mtmsrd %1; \ 209 ptesync; \ 210 \ 211 sld %1,%2,%4; \ 212 or %1,%1,%3; \ 213 tlbie %1; \ 214 \ 215 mtmsrd %0; \ 216 eieio; \ 217 tlbsync; \ 218 ptesync;" 219 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 220 : "memory"); 221 mtx_unlock_spin(&tlbie_mutex); 222 } 223 224 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 225 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 226 227 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 228 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 229 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 230 #define VSID_HASH_MASK 0x0000007fffffffffULL 231 232 #define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 233 #define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 234 #define PVO_WIRED 0x010UL /* PVO entry is wired */ 235 #define PVO_MANAGED 0x020UL /* PVO entry is managed */ 236 #define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 237 bootstrap */ 238 #define PVO_FAKE 0x100UL /* fictitious phys page */ 239 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 240 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 241 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 242 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 243 #define PVO_PTEGIDX_CLR(pvo) \ 244 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 245 #define PVO_PTEGIDX_SET(pvo, i) \ 246 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 247 248 #define MOEA_PVO_CHECK(pvo) 249 250 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 251 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 252 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 253 254 struct ofw_map { 255 vm_offset_t om_va; 256 vm_size_t om_len; 257 vm_offset_t om_pa_hi; 258 vm_offset_t om_pa_lo; 259 u_int om_mode; 260 }; 261 262 /* 263 * Map of physical memory regions. 264 */ 265 static struct mem_region *regions; 266 static struct mem_region *pregions; 267 extern u_int phys_avail_count; 268 extern int regions_sz, pregions_sz; 269 extern int ofw_real_mode; 270 271 extern struct pmap ofw_pmap; 272 273 extern void bs_remap_earlyboot(void); 274 275 276 /* 277 * Lock for the pteg and pvo tables. 278 */ 279 struct mtx moea64_table_mutex; 280 281 /* 282 * PTEG data. 283 */ 284 static struct lpteg *moea64_pteg_table; 285 u_int moea64_pteg_count; 286 u_int moea64_pteg_mask; 287 288 /* 289 * PVO data. 290 */ 291 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 292 /* lists of unmanaged pages */ 293 struct pvo_head moea64_pvo_kunmanaged = 294 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 295 struct pvo_head moea64_pvo_unmanaged = 296 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 297 298 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 299 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 300 301 #define BPVO_POOL_SIZE 327680 302 static struct pvo_entry *moea64_bpvo_pool; 303 static int moea64_bpvo_pool_index = 0; 304 305 #define VSID_NBPW (sizeof(u_int32_t) * 8) 306 static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 307 308 static boolean_t moea64_initialized = FALSE; 309 310 /* 311 * Statistics. 312 */ 313 u_int moea64_pte_valid = 0; 314 u_int moea64_pte_overflow = 0; 315 u_int moea64_pvo_entries = 0; 316 u_int moea64_pvo_enter_calls = 0; 317 u_int moea64_pvo_remove_calls = 0; 318 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 319 &moea64_pte_valid, 0, ""); 320 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 321 &moea64_pte_overflow, 0, ""); 322 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 323 &moea64_pvo_entries, 0, ""); 324 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 325 &moea64_pvo_enter_calls, 0, ""); 326 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 327 &moea64_pvo_remove_calls, 0, ""); 328 329 vm_offset_t moea64_scratchpage_va[2]; 330 struct lpte *moea64_scratchpage_pte[2]; 331 struct mtx moea64_scratchpage_mtx; 332 333 /* 334 * Allocate physical memory for use in moea64_bootstrap. 335 */ 336 static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 337 338 /* 339 * PTE calls. 340 */ 341 static int moea64_pte_insert(u_int, struct lpte *); 342 343 /* 344 * PVO calls. 345 */ 346 static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 347 vm_offset_t, vm_offset_t, uint64_t, int); 348 static void moea64_pvo_remove(struct pvo_entry *, int); 349 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 350 static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 351 352 /* 353 * Utility routines. 354 */ 355 static void moea64_bridge_bootstrap(mmu_t mmup, 356 vm_offset_t kernelstart, vm_offset_t kernelend); 357 static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 358 static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 359 vm_prot_t, boolean_t); 360 static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 361 static u_int moea64_clear_bit(vm_page_t, u_int64_t); 362 static void moea64_kremove(mmu_t, vm_offset_t); 363 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 364 vm_offset_t pa, vm_size_t sz); 365 static void tlbia(void); 366 367 /* 368 * Kernel MMU interface 369 */ 370 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 371 void moea64_clear_modify(mmu_t, vm_page_t); 372 void moea64_clear_reference(mmu_t, vm_page_t); 373 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 374 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 375 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 376 vm_prot_t); 377 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 378 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 379 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 380 void moea64_init(mmu_t); 381 boolean_t moea64_is_modified(mmu_t, vm_page_t); 382 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 383 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 384 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 385 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 386 int moea64_page_wired_mappings(mmu_t, vm_page_t); 387 void moea64_pinit(mmu_t, pmap_t); 388 void moea64_pinit0(mmu_t, pmap_t); 389 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 390 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 391 void moea64_qremove(mmu_t, vm_offset_t, int); 392 void moea64_release(mmu_t, pmap_t); 393 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 394 void moea64_remove_all(mmu_t, vm_page_t); 395 void moea64_remove_write(mmu_t, vm_page_t); 396 void moea64_zero_page(mmu_t, vm_page_t); 397 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 398 void moea64_zero_page_idle(mmu_t, vm_page_t); 399 void moea64_activate(mmu_t, struct thread *); 400 void moea64_deactivate(mmu_t, struct thread *); 401 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 402 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 403 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 404 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 405 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 406 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 407 408 static mmu_method_t moea64_bridge_methods[] = { 409 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 410 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 411 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 412 MMUMETHOD(mmu_copy_page, moea64_copy_page), 413 MMUMETHOD(mmu_enter, moea64_enter), 414 MMUMETHOD(mmu_enter_object, moea64_enter_object), 415 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 416 MMUMETHOD(mmu_extract, moea64_extract), 417 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 418 MMUMETHOD(mmu_init, moea64_init), 419 MMUMETHOD(mmu_is_modified, moea64_is_modified), 420 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 421 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 422 MMUMETHOD(mmu_map, moea64_map), 423 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 424 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 425 MMUMETHOD(mmu_pinit, moea64_pinit), 426 MMUMETHOD(mmu_pinit0, moea64_pinit0), 427 MMUMETHOD(mmu_protect, moea64_protect), 428 MMUMETHOD(mmu_qenter, moea64_qenter), 429 MMUMETHOD(mmu_qremove, moea64_qremove), 430 MMUMETHOD(mmu_release, moea64_release), 431 MMUMETHOD(mmu_remove, moea64_remove), 432 MMUMETHOD(mmu_remove_all, moea64_remove_all), 433 MMUMETHOD(mmu_remove_write, moea64_remove_write), 434 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 435 MMUMETHOD(mmu_zero_page, moea64_zero_page), 436 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 437 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 438 MMUMETHOD(mmu_activate, moea64_activate), 439 MMUMETHOD(mmu_deactivate, moea64_deactivate), 440 441 /* Internal interfaces */ 442 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 443 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 444 MMUMETHOD(mmu_mapdev, moea64_mapdev), 445 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 446 MMUMETHOD(mmu_kextract, moea64_kextract), 447 MMUMETHOD(mmu_kenter, moea64_kenter), 448 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 449 450 { 0, 0 } 451 }; 452 453 static mmu_def_t oea64_bridge_mmu = { 454 MMU_TYPE_G5, 455 moea64_bridge_methods, 456 0 457 }; 458 MMU_DEF(oea64_bridge_mmu); 459 460 static __inline u_int 461 va_to_pteg(uint64_t vsid, vm_offset_t addr) 462 { 463 uint64_t hash; 464 465 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 466 ADDR_PIDX_SHFT); 467 return (hash & moea64_pteg_mask); 468 } 469 470 static __inline struct pvo_head * 471 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 472 { 473 struct vm_page *pg; 474 475 pg = PHYS_TO_VM_PAGE(pa); 476 477 if (pg_p != NULL) 478 *pg_p = pg; 479 480 if (pg == NULL) 481 return (&moea64_pvo_unmanaged); 482 483 return (&pg->md.mdpg_pvoh); 484 } 485 486 static __inline struct pvo_head * 487 vm_page_to_pvoh(vm_page_t m) 488 { 489 490 return (&m->md.mdpg_pvoh); 491 } 492 493 static __inline void 494 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 495 { 496 497 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 498 m->md.mdpg_attrs &= ~ptebit; 499 } 500 501 static __inline u_int64_t 502 moea64_attr_fetch(vm_page_t m) 503 { 504 505 return (m->md.mdpg_attrs); 506 } 507 508 static __inline void 509 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 510 { 511 512 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 513 m->md.mdpg_attrs |= ptebit; 514 } 515 516 static __inline void 517 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 518 uint64_t pte_lo) 519 { 520 ASSERT_TABLE_LOCK(); 521 522 /* 523 * Construct a PTE. Default to IMB initially. Valid bit only gets 524 * set when the real pte is set in memory. 525 * 526 * Note: Don't set the valid bit for correct operation of tlb update. 527 */ 528 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 529 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 530 531 pt->pte_lo = pte_lo; 532 } 533 534 static __inline void 535 moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 536 { 537 538 ASSERT_TABLE_LOCK(); 539 540 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 541 } 542 543 static __inline void 544 moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 545 { 546 ASSERT_TABLE_LOCK(); 547 548 /* 549 * As shown in Section 7.6.3.2.3 550 */ 551 pt->pte_lo &= ~ptebit; 552 TLBIE(pmap,va); 553 } 554 555 static __inline void 556 moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 557 { 558 559 ASSERT_TABLE_LOCK(); 560 pvo_pt->pte_hi |= LPTE_VALID; 561 562 /* 563 * Update the PTE as defined in section 7.6.3.1. 564 * Note that the REF/CHG bits are from pvo_pt and thus should have 565 * been saved so this routine can restore them (if desired). 566 */ 567 pt->pte_lo = pvo_pt->pte_lo; 568 EIEIO(); 569 pt->pte_hi = pvo_pt->pte_hi; 570 PTESYNC(); 571 moea64_pte_valid++; 572 } 573 574 static __inline void 575 moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 576 { 577 ASSERT_TABLE_LOCK(); 578 pvo_pt->pte_hi &= ~LPTE_VALID; 579 580 /* 581 * Force the reg & chg bits back into the PTEs. 582 */ 583 SYNC(); 584 585 /* 586 * Invalidate the pte. 587 */ 588 pt->pte_hi &= ~LPTE_VALID; 589 TLBIE(pmap,va); 590 591 /* 592 * Save the reg & chg bits. 593 */ 594 moea64_pte_synch(pt, pvo_pt); 595 moea64_pte_valid--; 596 } 597 598 static __inline void 599 moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 600 { 601 602 /* 603 * Invalidate the PTE 604 */ 605 moea64_pte_unset(pt, pvo_pt, pmap, va); 606 moea64_pte_set(pt, pvo_pt); 607 if (pmap == kernel_pmap) 608 isync(); 609 } 610 611 static __inline uint64_t 612 moea64_calc_wimg(vm_offset_t pa) 613 { 614 uint64_t pte_lo; 615 int i; 616 617 /* 618 * Assume the page is cache inhibited and access is guarded unless 619 * it's in our available memory array. 620 */ 621 pte_lo = LPTE_I | LPTE_G; 622 for (i = 0; i < pregions_sz; i++) { 623 if ((pa >= pregions[i].mr_start) && 624 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 625 pte_lo &= ~(LPTE_I | LPTE_G); 626 pte_lo |= LPTE_M; 627 break; 628 } 629 } 630 631 return pte_lo; 632 } 633 634 /* 635 * Quick sort callout for comparing memory regions. 636 */ 637 static int mr_cmp(const void *a, const void *b); 638 static int om_cmp(const void *a, const void *b); 639 640 static int 641 mr_cmp(const void *a, const void *b) 642 { 643 const struct mem_region *regiona; 644 const struct mem_region *regionb; 645 646 regiona = a; 647 regionb = b; 648 if (regiona->mr_start < regionb->mr_start) 649 return (-1); 650 else if (regiona->mr_start > regionb->mr_start) 651 return (1); 652 else 653 return (0); 654 } 655 656 static int 657 om_cmp(const void *a, const void *b) 658 { 659 const struct ofw_map *mapa; 660 const struct ofw_map *mapb; 661 662 mapa = a; 663 mapb = b; 664 if (mapa->om_pa_hi < mapb->om_pa_hi) 665 return (-1); 666 else if (mapa->om_pa_hi > mapb->om_pa_hi) 667 return (1); 668 else if (mapa->om_pa_lo < mapb->om_pa_lo) 669 return (-1); 670 else if (mapa->om_pa_lo > mapb->om_pa_lo) 671 return (1); 672 else 673 return (0); 674 } 675 676 static void 677 moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 678 { 679 int i = 0; 680 681 /* 682 * Initialize segment registers and MMU 683 */ 684 685 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 686 for (i = 0; i < 16; i++) { 687 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 688 } 689 __asm __volatile ("ptesync; mtsdr1 %0; isync" 690 :: "r"((u_int)moea64_pteg_table 691 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 692 tlbia(); 693 } 694 695 static void 696 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 697 { 698 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 699 register_t msr; 700 vm_offset_t off; 701 vm_paddr_t pa_base; 702 int i, ofw_mappings; 703 704 bzero(translations, sz); 705 if (OF_getprop(mmu, "translations", translations, sz) == -1) 706 panic("moea64_bootstrap: can't get ofw translations"); 707 708 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 709 sz /= sizeof(*translations); 710 qsort(translations, sz, sizeof (*translations), om_cmp); 711 712 for (i = 0, ofw_mappings = 0; i < sz; i++) { 713 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 714 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 715 translations[i].om_len); 716 717 if (translations[i].om_pa_lo % PAGE_SIZE) 718 panic("OFW translation not page-aligned!"); 719 720 if (translations[i].om_pa_hi) 721 panic("OFW translations above 32-bit boundary!"); 722 723 pa_base = translations[i].om_pa_lo; 724 725 /* Now enter the pages for this mapping */ 726 727 DISABLE_TRANS(msr); 728 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 729 moea64_kenter(mmup, translations[i].om_va + off, 730 pa_base + off); 731 732 ofw_mappings++; 733 } 734 ENABLE_TRANS(msr); 735 } 736 } 737 738 static void 739 moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 740 { 741 ihandle_t mmui; 742 phandle_t chosen; 743 phandle_t mmu; 744 size_t sz; 745 int i, j; 746 vm_size_t size, physsz, hwphyssz; 747 vm_offset_t pa, va, off; 748 register_t msr; 749 void *dpcpu; 750 751 /* We don't have a direct map since there is no BAT */ 752 hw_direct_map = 0; 753 754 /* Make sure battable is zero, since we have no BAT */ 755 for (i = 0; i < 16; i++) { 756 battable[i].batu = 0; 757 battable[i].batl = 0; 758 } 759 760 /* Get physical memory regions from firmware */ 761 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 762 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 763 764 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 765 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 766 panic("moea64_bootstrap: phys_avail too small"); 767 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 768 phys_avail_count = 0; 769 physsz = 0; 770 hwphyssz = 0; 771 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 772 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 773 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 774 regions[i].mr_start + regions[i].mr_size, 775 regions[i].mr_size); 776 if (hwphyssz != 0 && 777 (physsz + regions[i].mr_size) >= hwphyssz) { 778 if (physsz < hwphyssz) { 779 phys_avail[j] = regions[i].mr_start; 780 phys_avail[j + 1] = regions[i].mr_start + 781 hwphyssz - physsz; 782 physsz = hwphyssz; 783 phys_avail_count++; 784 } 785 break; 786 } 787 phys_avail[j] = regions[i].mr_start; 788 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 789 phys_avail_count++; 790 physsz += regions[i].mr_size; 791 } 792 physmem = btoc(physsz); 793 794 /* 795 * Allocate PTEG table. 796 */ 797 #ifdef PTEGCOUNT 798 moea64_pteg_count = PTEGCOUNT; 799 #else 800 moea64_pteg_count = 0x1000; 801 802 while (moea64_pteg_count < physmem) 803 moea64_pteg_count <<= 1; 804 #endif /* PTEGCOUNT */ 805 806 size = moea64_pteg_count * sizeof(struct lpteg); 807 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 808 moea64_pteg_count, size); 809 810 /* 811 * We now need to allocate memory. This memory, to be allocated, 812 * has to reside in a page table. The page table we are about to 813 * allocate. We don't have BAT. So drop to data real mode for a minute 814 * as a measure of last resort. We do this a couple times. 815 */ 816 817 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 818 DISABLE_TRANS(msr); 819 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 820 ENABLE_TRANS(msr); 821 822 moea64_pteg_mask = moea64_pteg_count - 1; 823 824 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 825 826 /* 827 * Allocate pv/overflow lists. 828 */ 829 size = sizeof(struct pvo_head) * moea64_pteg_count; 830 831 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 832 PAGE_SIZE); 833 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 834 835 DISABLE_TRANS(msr); 836 for (i = 0; i < moea64_pteg_count; i++) 837 LIST_INIT(&moea64_pvo_table[i]); 838 ENABLE_TRANS(msr); 839 840 /* 841 * Initialize the lock that synchronizes access to the pteg and pvo 842 * tables. 843 */ 844 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 845 MTX_RECURSE); 846 847 /* 848 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 849 */ 850 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 851 852 /* 853 * Initialise the unmanaged pvo pool. 854 */ 855 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 856 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 857 moea64_bpvo_pool_index = 0; 858 859 /* 860 * Make sure kernel vsid is allocated as well as VSID 0. 861 */ 862 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 863 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 864 moea64_vsid_bitmap[0] |= 1; 865 866 /* 867 * Initialize the kernel pmap (which is statically allocated). 868 */ 869 for (i = 0; i < 16; i++) 870 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 871 872 kernel_pmap->pmap_phys = kernel_pmap; 873 kernel_pmap->pm_active = ~0; 874 875 PMAP_LOCK_INIT(kernel_pmap); 876 877 /* 878 * Now map in all the other buffers we allocated earlier 879 */ 880 881 DISABLE_TRANS(msr); 882 size = moea64_pteg_count * sizeof(struct lpteg); 883 off = (vm_offset_t)(moea64_pteg_table); 884 for (pa = off; pa < off + size; pa += PAGE_SIZE) 885 moea64_kenter(mmup, pa, pa); 886 size = sizeof(struct pvo_head) * moea64_pteg_count; 887 off = (vm_offset_t)(moea64_pvo_table); 888 for (pa = off; pa < off + size; pa += PAGE_SIZE) 889 moea64_kenter(mmup, pa, pa); 890 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 891 off = (vm_offset_t)(moea64_bpvo_pool); 892 for (pa = off; pa < off + size; pa += PAGE_SIZE) 893 moea64_kenter(mmup, pa, pa); 894 895 /* 896 * Map certain important things, like ourselves. 897 * 898 * NOTE: We do not map the exception vector space. That code is 899 * used only in real mode, and leaving it unmapped allows us to 900 * catch NULL pointer deferences, instead of making NULL a valid 901 * address. 902 */ 903 904 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 905 moea64_kenter(mmup, pa, pa); 906 ENABLE_TRANS(msr); 907 908 if (!ofw_real_mode) { 909 /* 910 * Set up the Open Firmware pmap and add its mappings. 911 */ 912 913 moea64_pinit(mmup, &ofw_pmap); 914 for (i = 0; i < 16; i++) 915 ofw_pmap.pm_sr[i] = kernel_pmap->pm_sr[i]; 916 917 if ((chosen = OF_finddevice("/chosen")) == -1) 918 panic("moea64_bootstrap: can't find /chosen"); 919 OF_getprop(chosen, "mmu", &mmui, 4); 920 if ((mmu = OF_instance_to_package(mmui)) == -1) 921 panic("moea64_bootstrap: can't get mmu package"); 922 if ((sz = OF_getproplen(mmu, "translations")) == -1) 923 panic("moea64_bootstrap: can't get ofw translation count"); 924 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 925 panic("moea64_bootstrap: too many ofw translations"); 926 927 moea64_add_ofw_mappings(mmup, mmu, sz); 928 } 929 930 #ifdef SMP 931 TLBSYNC(); 932 #endif 933 934 /* 935 * Calculate the last available physical address. 936 */ 937 for (i = 0; phys_avail[i + 2] != 0; i += 2) 938 ; 939 Maxmem = powerpc_btop(phys_avail[i + 1]); 940 941 /* 942 * Initialize MMU and remap early physical mappings 943 */ 944 moea64_bridge_cpu_bootstrap(mmup,0); 945 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 946 pmap_bootstrapped++; 947 bs_remap_earlyboot(); 948 949 /* 950 * Set the start and end of kva. 951 */ 952 virtual_avail = VM_MIN_KERNEL_ADDRESS; 953 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 954 955 /* 956 * Figure out how far we can extend virtual_end into segment 16 957 * without running into existing mappings. Segment 16 is guaranteed 958 * to contain neither RAM nor devices (at least on Apple hardware), 959 * but will generally contain some OFW mappings we should not 960 * step on. 961 */ 962 963 PMAP_LOCK(kernel_pmap); 964 while (moea64_pvo_find_va(kernel_pmap, virtual_end+1, NULL) == NULL) 965 virtual_end += PAGE_SIZE; 966 PMAP_UNLOCK(kernel_pmap); 967 968 /* 969 * Allocate some things for page zeroing. We put this directly 970 * in the page table, marked with LPTE_LOCKED, to avoid any 971 * of the PVO book-keeping or other parts of the VM system 972 * from even knowing that this hack exists. 973 */ 974 975 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 976 for (i = 0; i < 2; i++) { 977 struct lpte pt; 978 uint64_t vsid; 979 int pteidx, ptegidx; 980 981 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 982 virtual_end -= PAGE_SIZE; 983 984 LOCK_TABLE(); 985 986 vsid = va_to_vsid(kernel_pmap, moea64_scratchpage_va[i]); 987 moea64_pte_create(&pt, vsid, moea64_scratchpage_va[i], 988 LPTE_NOEXEC); 989 pt.pte_hi |= LPTE_LOCKED; 990 991 ptegidx = va_to_pteg(vsid, moea64_scratchpage_va[i]); 992 pteidx = moea64_pte_insert(ptegidx, &pt); 993 if (pt.pte_hi & LPTE_HID) 994 ptegidx ^= moea64_pteg_mask; 995 996 moea64_scratchpage_pte[i] = 997 &moea64_pteg_table[ptegidx].pt[pteidx]; 998 999 UNLOCK_TABLE(); 1000 } 1001 1002 /* 1003 * Allocate a kernel stack with a guard page for thread0 and map it 1004 * into the kernel page map. 1005 */ 1006 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1007 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1008 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1009 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1010 thread0.td_kstack = va; 1011 thread0.td_kstack_pages = KSTACK_PAGES; 1012 for (i = 0; i < KSTACK_PAGES; i++) { 1013 moea64_kenter(mmup, va, pa); 1014 pa += PAGE_SIZE; 1015 va += PAGE_SIZE; 1016 } 1017 1018 /* 1019 * Allocate virtual address space for the message buffer. 1020 */ 1021 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1022 msgbufp = (struct msgbuf *)virtual_avail; 1023 va = virtual_avail; 1024 virtual_avail += round_page(MSGBUF_SIZE); 1025 while (va < virtual_avail) { 1026 moea64_kenter(mmup, va, pa); 1027 pa += PAGE_SIZE; 1028 va += PAGE_SIZE; 1029 } 1030 1031 /* 1032 * Allocate virtual address space for the dynamic percpu area. 1033 */ 1034 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1035 dpcpu = (void *)virtual_avail; 1036 virtual_avail += DPCPU_SIZE; 1037 while (va < virtual_avail) { 1038 moea64_kenter(mmup, va, pa); 1039 pa += PAGE_SIZE; 1040 va += PAGE_SIZE; 1041 } 1042 dpcpu_init(dpcpu, 0); 1043 } 1044 1045 /* 1046 * Activate a user pmap. The pmap must be activated before it's address 1047 * space can be accessed in any way. 1048 */ 1049 void 1050 moea64_activate(mmu_t mmu, struct thread *td) 1051 { 1052 pmap_t pm, pmr; 1053 1054 /* 1055 * Load all the data we need up front to encourage the compiler to 1056 * not issue any loads while we have interrupts disabled below. 1057 */ 1058 pm = &td->td_proc->p_vmspace->vm_pmap; 1059 pmr = pm->pmap_phys; 1060 1061 pm->pm_active |= PCPU_GET(cpumask); 1062 PCPU_SET(curpmap, pmr); 1063 } 1064 1065 void 1066 moea64_deactivate(mmu_t mmu, struct thread *td) 1067 { 1068 pmap_t pm; 1069 1070 pm = &td->td_proc->p_vmspace->vm_pmap; 1071 pm->pm_active &= ~(PCPU_GET(cpumask)); 1072 PCPU_SET(curpmap, NULL); 1073 } 1074 1075 void 1076 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1077 { 1078 struct pvo_entry *pvo; 1079 1080 PMAP_LOCK(pm); 1081 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1082 1083 if (pvo != NULL) { 1084 if (wired) { 1085 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1086 pm->pm_stats.wired_count++; 1087 pvo->pvo_vaddr |= PVO_WIRED; 1088 } else { 1089 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1090 pm->pm_stats.wired_count--; 1091 pvo->pvo_vaddr &= ~PVO_WIRED; 1092 } 1093 } 1094 PMAP_UNLOCK(pm); 1095 } 1096 1097 /* 1098 * This goes through and sets the physical address of our 1099 * special scratch PTE to the PA we want to zero or copy. Because 1100 * of locking issues (this can get called in pvo_enter() by 1101 * the UMA allocator), we can't use most other utility functions here 1102 */ 1103 1104 static __inline 1105 void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1106 1107 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1108 1109 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1110 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1111 1112 moea64_scratchpage_pte[which]->pte_lo &= 1113 ~(LPTE_WIMG | LPTE_RPGN); 1114 moea64_scratchpage_pte[which]->pte_lo |= 1115 moea64_calc_wimg(pa) | (uint64_t)pa; 1116 EIEIO(); 1117 1118 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1119 PTESYNC(); isync(); 1120 } 1121 1122 void 1123 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1124 { 1125 vm_offset_t dst; 1126 vm_offset_t src; 1127 1128 dst = VM_PAGE_TO_PHYS(mdst); 1129 src = VM_PAGE_TO_PHYS(msrc); 1130 1131 mtx_lock(&moea64_scratchpage_mtx); 1132 1133 moea64_set_scratchpage_pa(0,src); 1134 moea64_set_scratchpage_pa(1,dst); 1135 1136 kcopy((void *)moea64_scratchpage_va[0], 1137 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1138 1139 mtx_unlock(&moea64_scratchpage_mtx); 1140 } 1141 1142 void 1143 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1144 { 1145 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1146 1147 if (!moea64_initialized) 1148 panic("moea64_zero_page: can't zero pa %#x", pa); 1149 if (size + off > PAGE_SIZE) 1150 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1151 1152 mtx_lock(&moea64_scratchpage_mtx); 1153 1154 moea64_set_scratchpage_pa(0,pa); 1155 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1156 mtx_unlock(&moea64_scratchpage_mtx); 1157 } 1158 1159 /* 1160 * Zero a page of physical memory by temporarily mapping it 1161 */ 1162 void 1163 moea64_zero_page(mmu_t mmu, vm_page_t m) 1164 { 1165 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1166 vm_offset_t off; 1167 1168 if (!moea64_initialized) 1169 panic("moea64_zero_page: can't zero pa %#x", pa); 1170 1171 mtx_lock(&moea64_scratchpage_mtx); 1172 1173 moea64_set_scratchpage_pa(0,pa); 1174 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1175 __asm __volatile("dcbz 0,%0" :: 1176 "r"(moea64_scratchpage_va[0] + off)); 1177 mtx_unlock(&moea64_scratchpage_mtx); 1178 } 1179 1180 void 1181 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1182 { 1183 1184 moea64_zero_page(mmu, m); 1185 } 1186 1187 /* 1188 * Map the given physical page at the specified virtual address in the 1189 * target pmap with the protection requested. If specified the page 1190 * will be wired down. 1191 */ 1192 void 1193 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1194 vm_prot_t prot, boolean_t wired) 1195 { 1196 1197 vm_page_lock_queues(); 1198 PMAP_LOCK(pmap); 1199 moea64_enter_locked(pmap, va, m, prot, wired); 1200 vm_page_unlock_queues(); 1201 PMAP_UNLOCK(pmap); 1202 } 1203 1204 /* 1205 * Map the given physical page at the specified virtual address in the 1206 * target pmap with the protection requested. If specified the page 1207 * will be wired down. 1208 * 1209 * The page queues and pmap must be locked. 1210 */ 1211 1212 static void 1213 moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1214 boolean_t wired) 1215 { 1216 struct pvo_head *pvo_head; 1217 uma_zone_t zone; 1218 vm_page_t pg; 1219 uint64_t pte_lo; 1220 u_int pvo_flags; 1221 int error; 1222 1223 if (!moea64_initialized) { 1224 pvo_head = &moea64_pvo_kunmanaged; 1225 pg = NULL; 1226 zone = moea64_upvo_zone; 1227 pvo_flags = 0; 1228 } else { 1229 pvo_head = vm_page_to_pvoh(m); 1230 pg = m; 1231 zone = moea64_mpvo_zone; 1232 pvo_flags = PVO_MANAGED; 1233 } 1234 1235 if (pmap_bootstrapped) 1236 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1237 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1238 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1239 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1240 ("moea64_enter_locked: page %p is not busy", m)); 1241 1242 /* XXX change the pvo head for fake pages */ 1243 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1244 pvo_flags &= ~PVO_MANAGED; 1245 pvo_head = &moea64_pvo_kunmanaged; 1246 zone = moea64_upvo_zone; 1247 } 1248 1249 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1250 1251 if (prot & VM_PROT_WRITE) { 1252 pte_lo |= LPTE_BW; 1253 if (pmap_bootstrapped && 1254 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1255 vm_page_flag_set(m, PG_WRITEABLE); 1256 } else 1257 pte_lo |= LPTE_BR; 1258 1259 if (prot & VM_PROT_EXECUTE) 1260 pvo_flags |= VM_PROT_EXECUTE; 1261 1262 if (wired) 1263 pvo_flags |= PVO_WIRED; 1264 1265 if ((m->flags & PG_FICTITIOUS) != 0) 1266 pvo_flags |= PVO_FAKE; 1267 1268 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1269 pte_lo, pvo_flags); 1270 1271 /* 1272 * Flush the page from the instruction cache if this page is 1273 * mapped executable and cacheable. 1274 */ 1275 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1276 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1277 } 1278 } 1279 1280 static void 1281 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1282 { 1283 1284 /* 1285 * This is much trickier than on older systems because 1286 * we can't sync the icache on physical addresses directly 1287 * without a direct map. Instead we check a couple of cases 1288 * where the memory is already mapped in and, failing that, 1289 * use the same trick we use for page zeroing to create 1290 * a temporary mapping for this physical address. 1291 */ 1292 1293 if (!pmap_bootstrapped) { 1294 /* 1295 * If PMAP is not bootstrapped, we are likely to be 1296 * in real mode. 1297 */ 1298 __syncicache((void *)pa, sz); 1299 } else if (pmap == kernel_pmap) { 1300 __syncicache((void *)va, sz); 1301 } else { 1302 /* Use the scratch page to set up a temp mapping */ 1303 1304 mtx_lock(&moea64_scratchpage_mtx); 1305 1306 moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1307 __syncicache((void *)(moea64_scratchpage_va[1] + 1308 (va & ADDR_POFF)), sz); 1309 1310 mtx_unlock(&moea64_scratchpage_mtx); 1311 } 1312 } 1313 1314 /* 1315 * Maps a sequence of resident pages belonging to the same object. 1316 * The sequence begins with the given page m_start. This page is 1317 * mapped at the given virtual address start. Each subsequent page is 1318 * mapped at a virtual address that is offset from start by the same 1319 * amount as the page is offset from m_start within the object. The 1320 * last page in the sequence is the page with the largest offset from 1321 * m_start that can be mapped at a virtual address less than the given 1322 * virtual address end. Not every virtual page between start and end 1323 * is mapped; only those for which a resident page exists with the 1324 * corresponding offset from m_start are mapped. 1325 */ 1326 void 1327 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1328 vm_page_t m_start, vm_prot_t prot) 1329 { 1330 vm_page_t m; 1331 vm_pindex_t diff, psize; 1332 1333 psize = atop(end - start); 1334 m = m_start; 1335 vm_page_lock_queues(); 1336 PMAP_LOCK(pm); 1337 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1338 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1339 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1340 m = TAILQ_NEXT(m, listq); 1341 } 1342 vm_page_unlock_queues(); 1343 PMAP_UNLOCK(pm); 1344 } 1345 1346 void 1347 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1348 vm_prot_t prot) 1349 { 1350 1351 vm_page_lock_queues(); 1352 PMAP_LOCK(pm); 1353 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1354 FALSE); 1355 vm_page_unlock_queues(); 1356 PMAP_UNLOCK(pm); 1357 } 1358 1359 vm_paddr_t 1360 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1361 { 1362 struct pvo_entry *pvo; 1363 vm_paddr_t pa; 1364 1365 PMAP_LOCK(pm); 1366 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1367 if (pvo == NULL) 1368 pa = 0; 1369 else 1370 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1371 PMAP_UNLOCK(pm); 1372 return (pa); 1373 } 1374 1375 /* 1376 * Atomically extract and hold the physical page with the given 1377 * pmap and virtual address pair if that mapping permits the given 1378 * protection. 1379 */ 1380 vm_page_t 1381 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1382 { 1383 struct pvo_entry *pvo; 1384 vm_page_t m; 1385 vm_paddr_t pa; 1386 1387 m = NULL; 1388 pa = 0; 1389 PMAP_LOCK(pmap); 1390 retry: 1391 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1392 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1393 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1394 (prot & VM_PROT_WRITE) == 0)) { 1395 if (vm_page_pa_tryrelock(pmap, 1396 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1397 goto retry; 1398 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1399 vm_page_hold(m); 1400 } 1401 PA_UNLOCK_COND(pa); 1402 PMAP_UNLOCK(pmap); 1403 return (m); 1404 } 1405 1406 static void * 1407 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1408 { 1409 /* 1410 * This entire routine is a horrible hack to avoid bothering kmem 1411 * for new KVA addresses. Because this can get called from inside 1412 * kmem allocation routines, calling kmem for a new address here 1413 * can lead to multiply locking non-recursive mutexes. 1414 */ 1415 static vm_pindex_t color; 1416 vm_offset_t va; 1417 1418 vm_page_t m; 1419 int pflags, needed_lock; 1420 1421 *flags = UMA_SLAB_PRIV; 1422 needed_lock = !PMAP_LOCKED(kernel_pmap); 1423 1424 if (needed_lock) 1425 PMAP_LOCK(kernel_pmap); 1426 1427 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1428 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1429 else 1430 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1431 if (wait & M_ZERO) 1432 pflags |= VM_ALLOC_ZERO; 1433 1434 for (;;) { 1435 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1436 if (m == NULL) { 1437 if (wait & M_NOWAIT) 1438 return (NULL); 1439 VM_WAIT; 1440 } else 1441 break; 1442 } 1443 1444 va = VM_PAGE_TO_PHYS(m); 1445 1446 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1447 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1448 PVO_WIRED | PVO_BOOTSTRAP); 1449 1450 if (needed_lock) 1451 PMAP_UNLOCK(kernel_pmap); 1452 1453 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1454 bzero((void *)va, PAGE_SIZE); 1455 1456 return (void *)va; 1457 } 1458 1459 void 1460 moea64_init(mmu_t mmu) 1461 { 1462 1463 CTR0(KTR_PMAP, "moea64_init"); 1464 1465 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1466 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1467 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1468 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1469 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1470 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1471 1472 if (!hw_direct_map) { 1473 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1474 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1475 } 1476 1477 moea64_initialized = TRUE; 1478 } 1479 1480 boolean_t 1481 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1482 { 1483 1484 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1485 ("moea64_is_referenced: page %p is not managed", m)); 1486 return (moea64_query_bit(m, PTE_REF)); 1487 } 1488 1489 boolean_t 1490 moea64_is_modified(mmu_t mmu, vm_page_t m) 1491 { 1492 1493 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1494 ("moea64_is_modified: page %p is not managed", m)); 1495 1496 /* 1497 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1498 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1499 * is clear, no PTEs can have LPTE_CHG set. 1500 */ 1501 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1502 if ((m->oflags & VPO_BUSY) == 0 && 1503 (m->flags & PG_WRITEABLE) == 0) 1504 return (FALSE); 1505 return (moea64_query_bit(m, LPTE_CHG)); 1506 } 1507 1508 void 1509 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1510 { 1511 1512 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1513 ("moea64_clear_reference: page %p is not managed", m)); 1514 moea64_clear_bit(m, LPTE_REF); 1515 } 1516 1517 void 1518 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1519 { 1520 1521 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1522 ("moea64_clear_modify: page %p is not managed", m)); 1523 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1524 KASSERT((m->oflags & VPO_BUSY) == 0, 1525 ("moea64_clear_modify: page %p is busy", m)); 1526 1527 /* 1528 * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1529 * set. If the object containing the page is locked and the page is 1530 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1531 */ 1532 if ((m->flags & PG_WRITEABLE) == 0) 1533 return; 1534 moea64_clear_bit(m, LPTE_CHG); 1535 } 1536 1537 /* 1538 * Clear the write and modified bits in each of the given page's mappings. 1539 */ 1540 void 1541 moea64_remove_write(mmu_t mmu, vm_page_t m) 1542 { 1543 struct pvo_entry *pvo; 1544 struct lpte *pt; 1545 pmap_t pmap; 1546 uint64_t lo; 1547 1548 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1549 ("moea64_remove_write: page %p is not managed", m)); 1550 1551 /* 1552 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1553 * another thread while the object is locked. Thus, if PG_WRITEABLE 1554 * is clear, no page table entries need updating. 1555 */ 1556 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1557 if ((m->oflags & VPO_BUSY) == 0 && 1558 (m->flags & PG_WRITEABLE) == 0) 1559 return; 1560 vm_page_lock_queues(); 1561 lo = moea64_attr_fetch(m); 1562 SYNC(); 1563 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1564 pmap = pvo->pvo_pmap; 1565 PMAP_LOCK(pmap); 1566 LOCK_TABLE(); 1567 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1568 pt = moea64_pvo_to_pte(pvo, -1); 1569 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1570 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1571 if (pt != NULL) { 1572 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1573 lo |= pvo->pvo_pte.lpte.pte_lo; 1574 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1575 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1576 pvo->pvo_pmap, PVO_VADDR(pvo)); 1577 } 1578 } 1579 UNLOCK_TABLE(); 1580 PMAP_UNLOCK(pmap); 1581 } 1582 if ((lo & LPTE_CHG) != 0) { 1583 moea64_attr_clear(m, LPTE_CHG); 1584 vm_page_dirty(m); 1585 } 1586 vm_page_flag_clear(m, PG_WRITEABLE); 1587 vm_page_unlock_queues(); 1588 } 1589 1590 /* 1591 * moea64_ts_referenced: 1592 * 1593 * Return a count of reference bits for a page, clearing those bits. 1594 * It is not necessary for every reference bit to be cleared, but it 1595 * is necessary that 0 only be returned when there are truly no 1596 * reference bits set. 1597 * 1598 * XXX: The exact number of bits to check and clear is a matter that 1599 * should be tested and standardized at some point in the future for 1600 * optimal aging of shared pages. 1601 */ 1602 boolean_t 1603 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1604 { 1605 1606 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1607 ("moea64_ts_referenced: page %p is not managed", m)); 1608 return (moea64_clear_bit(m, LPTE_REF)); 1609 } 1610 1611 /* 1612 * Map a wired page into kernel virtual address space. 1613 */ 1614 void 1615 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1616 { 1617 uint64_t pte_lo; 1618 int error; 1619 1620 #if 0 1621 if (!pmap_bootstrapped) { 1622 if (va >= VM_MIN_KERNEL_ADDRESS && va < virtual_end) 1623 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1624 } 1625 #endif 1626 1627 pte_lo = moea64_calc_wimg(pa); 1628 1629 PMAP_LOCK(kernel_pmap); 1630 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1631 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1632 PVO_WIRED | VM_PROT_EXECUTE); 1633 1634 if (error != 0 && error != ENOENT) 1635 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1636 pa, error); 1637 1638 /* 1639 * Flush the memory from the instruction cache. 1640 */ 1641 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1642 __syncicache((void *)va, PAGE_SIZE); 1643 } 1644 PMAP_UNLOCK(kernel_pmap); 1645 } 1646 1647 /* 1648 * Extract the physical page address associated with the given kernel virtual 1649 * address. 1650 */ 1651 vm_offset_t 1652 moea64_kextract(mmu_t mmu, vm_offset_t va) 1653 { 1654 struct pvo_entry *pvo; 1655 vm_paddr_t pa; 1656 1657 /* 1658 * Shortcut the direct-mapped case when applicable. We never put 1659 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1660 */ 1661 if (va < VM_MIN_KERNEL_ADDRESS) 1662 return (va); 1663 1664 PMAP_LOCK(kernel_pmap); 1665 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1666 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1667 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1668 PMAP_UNLOCK(kernel_pmap); 1669 return (pa); 1670 } 1671 1672 /* 1673 * Remove a wired page from kernel virtual address space. 1674 */ 1675 void 1676 moea64_kremove(mmu_t mmu, vm_offset_t va) 1677 { 1678 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1679 } 1680 1681 /* 1682 * Map a range of physical addresses into kernel virtual address space. 1683 * 1684 * The value passed in *virt is a suggested virtual address for the mapping. 1685 * Architectures which can support a direct-mapped physical to virtual region 1686 * can return the appropriate address within that region, leaving '*virt' 1687 * unchanged. We cannot and therefore do not; *virt is updated with the 1688 * first usable address after the mapped region. 1689 */ 1690 vm_offset_t 1691 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1692 vm_offset_t pa_end, int prot) 1693 { 1694 vm_offset_t sva, va; 1695 1696 sva = *virt; 1697 va = sva; 1698 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1699 moea64_kenter(mmu, va, pa_start); 1700 *virt = va; 1701 1702 return (sva); 1703 } 1704 1705 /* 1706 * Returns true if the pmap's pv is one of the first 1707 * 16 pvs linked to from this page. This count may 1708 * be changed upwards or downwards in the future; it 1709 * is only necessary that true be returned for a small 1710 * subset of pmaps for proper page aging. 1711 */ 1712 boolean_t 1713 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1714 { 1715 int loops; 1716 struct pvo_entry *pvo; 1717 boolean_t rv; 1718 1719 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1720 ("moea64_page_exists_quick: page %p is not managed", m)); 1721 loops = 0; 1722 rv = FALSE; 1723 vm_page_lock_queues(); 1724 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1725 if (pvo->pvo_pmap == pmap) { 1726 rv = TRUE; 1727 break; 1728 } 1729 if (++loops >= 16) 1730 break; 1731 } 1732 vm_page_unlock_queues(); 1733 return (rv); 1734 } 1735 1736 /* 1737 * Return the number of managed mappings to the given physical page 1738 * that are wired. 1739 */ 1740 int 1741 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1742 { 1743 struct pvo_entry *pvo; 1744 int count; 1745 1746 count = 0; 1747 if ((m->flags & PG_FICTITIOUS) != 0) 1748 return (count); 1749 vm_page_lock_queues(); 1750 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1751 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1752 count++; 1753 vm_page_unlock_queues(); 1754 return (count); 1755 } 1756 1757 static u_int moea64_vsidcontext; 1758 1759 void 1760 moea64_pinit(mmu_t mmu, pmap_t pmap) 1761 { 1762 int i, mask; 1763 u_int entropy; 1764 1765 PMAP_LOCK_INIT(pmap); 1766 1767 entropy = 0; 1768 __asm __volatile("mftb %0" : "=r"(entropy)); 1769 1770 if (pmap_bootstrapped) 1771 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1772 else 1773 pmap->pmap_phys = pmap; 1774 1775 /* 1776 * Allocate some segment registers for this pmap. 1777 */ 1778 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1779 u_int hash, n; 1780 1781 /* 1782 * Create a new value by mutiplying by a prime and adding in 1783 * entropy from the timebase register. This is to make the 1784 * VSID more random so that the PT hash function collides 1785 * less often. (Note that the prime casues gcc to do shifts 1786 * instead of a multiply.) 1787 */ 1788 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1789 hash = moea64_vsidcontext & (NPMAPS - 1); 1790 if (hash == 0) /* 0 is special, avoid it */ 1791 continue; 1792 n = hash >> 5; 1793 mask = 1 << (hash & (VSID_NBPW - 1)); 1794 hash = (moea64_vsidcontext & 0xfffff); 1795 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1796 /* anything free in this bucket? */ 1797 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1798 entropy = (moea64_vsidcontext >> 20); 1799 continue; 1800 } 1801 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1802 mask = 1 << i; 1803 hash &= 0xfffff & ~(VSID_NBPW - 1); 1804 hash |= i; 1805 } 1806 moea64_vsid_bitmap[n] |= mask; 1807 for (i = 0; i < 16; i++) { 1808 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1809 } 1810 return; 1811 } 1812 1813 panic("moea64_pinit: out of segments"); 1814 } 1815 1816 /* 1817 * Initialize the pmap associated with process 0. 1818 */ 1819 void 1820 moea64_pinit0(mmu_t mmu, pmap_t pm) 1821 { 1822 moea64_pinit(mmu, pm); 1823 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1824 } 1825 1826 /* 1827 * Set the physical protection on the specified range of this map as requested. 1828 */ 1829 void 1830 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1831 vm_prot_t prot) 1832 { 1833 struct pvo_entry *pvo; 1834 struct lpte *pt; 1835 int pteidx; 1836 1837 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1838 eva, prot); 1839 1840 1841 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1842 ("moea64_protect: non current pmap")); 1843 1844 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1845 moea64_remove(mmu, pm, sva, eva); 1846 return; 1847 } 1848 1849 vm_page_lock_queues(); 1850 PMAP_LOCK(pm); 1851 for (; sva < eva; sva += PAGE_SIZE) { 1852 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1853 if (pvo == NULL) 1854 continue; 1855 1856 /* 1857 * Grab the PTE pointer before we diddle with the cached PTE 1858 * copy. 1859 */ 1860 LOCK_TABLE(); 1861 pt = moea64_pvo_to_pte(pvo, pteidx); 1862 1863 /* 1864 * Change the protection of the page. 1865 */ 1866 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1867 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1868 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1869 if ((prot & VM_PROT_EXECUTE) == 0) 1870 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1871 1872 /* 1873 * If the PVO is in the page table, update that pte as well. 1874 */ 1875 if (pt != NULL) { 1876 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1877 pvo->pvo_pmap, PVO_VADDR(pvo)); 1878 if ((pvo->pvo_pte.lpte.pte_lo & 1879 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1880 moea64_syncicache(pm, sva, 1881 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1882 PAGE_SIZE); 1883 } 1884 } 1885 UNLOCK_TABLE(); 1886 } 1887 vm_page_unlock_queues(); 1888 PMAP_UNLOCK(pm); 1889 } 1890 1891 /* 1892 * Map a list of wired pages into kernel virtual address space. This is 1893 * intended for temporary mappings which do not need page modification or 1894 * references recorded. Existing mappings in the region are overwritten. 1895 */ 1896 void 1897 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1898 { 1899 while (count-- > 0) { 1900 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1901 va += PAGE_SIZE; 1902 m++; 1903 } 1904 } 1905 1906 /* 1907 * Remove page mappings from kernel virtual address space. Intended for 1908 * temporary mappings entered by moea64_qenter. 1909 */ 1910 void 1911 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1912 { 1913 while (count-- > 0) { 1914 moea64_kremove(mmu, va); 1915 va += PAGE_SIZE; 1916 } 1917 } 1918 1919 void 1920 moea64_release(mmu_t mmu, pmap_t pmap) 1921 { 1922 int idx, mask; 1923 1924 /* 1925 * Free segment register's VSID 1926 */ 1927 if (pmap->pm_sr[0] == 0) 1928 panic("moea64_release"); 1929 1930 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1931 mask = 1 << (idx % VSID_NBPW); 1932 idx /= VSID_NBPW; 1933 moea64_vsid_bitmap[idx] &= ~mask; 1934 PMAP_LOCK_DESTROY(pmap); 1935 } 1936 1937 /* 1938 * Remove the given range of addresses from the specified map. 1939 */ 1940 void 1941 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1942 { 1943 struct pvo_entry *pvo; 1944 int pteidx; 1945 1946 vm_page_lock_queues(); 1947 PMAP_LOCK(pm); 1948 for (; sva < eva; sva += PAGE_SIZE) { 1949 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1950 if (pvo != NULL) { 1951 moea64_pvo_remove(pvo, pteidx); 1952 } 1953 } 1954 vm_page_unlock_queues(); 1955 PMAP_UNLOCK(pm); 1956 } 1957 1958 /* 1959 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1960 * will reflect changes in pte's back to the vm_page. 1961 */ 1962 void 1963 moea64_remove_all(mmu_t mmu, vm_page_t m) 1964 { 1965 struct pvo_head *pvo_head; 1966 struct pvo_entry *pvo, *next_pvo; 1967 pmap_t pmap; 1968 1969 vm_page_lock_queues(); 1970 pvo_head = vm_page_to_pvoh(m); 1971 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1972 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1973 1974 MOEA_PVO_CHECK(pvo); /* sanity check */ 1975 pmap = pvo->pvo_pmap; 1976 PMAP_LOCK(pmap); 1977 moea64_pvo_remove(pvo, -1); 1978 PMAP_UNLOCK(pmap); 1979 } 1980 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 1981 moea64_attr_clear(m, LPTE_CHG); 1982 vm_page_dirty(m); 1983 } 1984 vm_page_flag_clear(m, PG_WRITEABLE); 1985 vm_page_unlock_queues(); 1986 } 1987 1988 /* 1989 * Allocate a physical page of memory directly from the phys_avail map. 1990 * Can only be called from moea64_bootstrap before avail start and end are 1991 * calculated. 1992 */ 1993 static vm_offset_t 1994 moea64_bootstrap_alloc(vm_size_t size, u_int align) 1995 { 1996 vm_offset_t s, e; 1997 int i, j; 1998 1999 size = round_page(size); 2000 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2001 if (align != 0) 2002 s = (phys_avail[i] + align - 1) & ~(align - 1); 2003 else 2004 s = phys_avail[i]; 2005 e = s + size; 2006 2007 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2008 continue; 2009 2010 if (s == phys_avail[i]) { 2011 phys_avail[i] += size; 2012 } else if (e == phys_avail[i + 1]) { 2013 phys_avail[i + 1] -= size; 2014 } else { 2015 for (j = phys_avail_count * 2; j > i; j -= 2) { 2016 phys_avail[j] = phys_avail[j - 2]; 2017 phys_avail[j + 1] = phys_avail[j - 1]; 2018 } 2019 2020 phys_avail[i + 3] = phys_avail[i + 1]; 2021 phys_avail[i + 1] = s; 2022 phys_avail[i + 2] = e; 2023 phys_avail_count++; 2024 } 2025 2026 return (s); 2027 } 2028 panic("moea64_bootstrap_alloc: could not allocate memory"); 2029 } 2030 2031 static void 2032 tlbia(void) 2033 { 2034 vm_offset_t i; 2035 register_t msr, scratch; 2036 2037 for (i = 0; i < 0xFF000; i += 0x00001000) { 2038 __asm __volatile("\ 2039 mfmsr %0; \ 2040 mr %1, %0; \ 2041 insrdi %1,%3,1,0; \ 2042 mtmsrd %1; \ 2043 ptesync; \ 2044 \ 2045 tlbiel %2; \ 2046 \ 2047 mtmsrd %0; \ 2048 eieio; \ 2049 tlbsync; \ 2050 ptesync;" 2051 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 2052 } 2053 } 2054 2055 static int 2056 moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2057 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 2058 { 2059 struct pvo_entry *pvo; 2060 uint64_t vsid; 2061 int first; 2062 u_int ptegidx; 2063 int i; 2064 int bootstrap; 2065 2066 /* 2067 * One nasty thing that can happen here is that the UMA calls to 2068 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2069 * which calls UMA... 2070 * 2071 * We break the loop by detecting recursion and allocating out of 2072 * the bootstrap pool. 2073 */ 2074 2075 moea64_pvo_enter_calls++; 2076 first = 0; 2077 bootstrap = (flags & PVO_BOOTSTRAP); 2078 2079 if (!moea64_initialized) 2080 bootstrap = 1; 2081 2082 /* 2083 * Compute the PTE Group index. 2084 */ 2085 va &= ~ADDR_POFF; 2086 vsid = va_to_vsid(pm, va); 2087 ptegidx = va_to_pteg(vsid, va); 2088 2089 /* 2090 * Remove any existing mapping for this page. Reuse the pvo entry if 2091 * there is a mapping. 2092 */ 2093 LOCK_TABLE(); 2094 2095 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2096 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2097 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2098 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2099 (pte_lo & LPTE_PP)) { 2100 UNLOCK_TABLE(); 2101 return (0); 2102 } 2103 moea64_pvo_remove(pvo, -1); 2104 break; 2105 } 2106 } 2107 2108 /* 2109 * If we aren't overwriting a mapping, try to allocate. 2110 */ 2111 if (bootstrap) { 2112 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2113 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2114 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2115 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2116 } 2117 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2118 moea64_bpvo_pool_index++; 2119 bootstrap = 1; 2120 } else { 2121 /* 2122 * Note: drop the table lock around the UMA allocation in 2123 * case the UMA allocator needs to manipulate the page 2124 * table. The mapping we are working with is already 2125 * protected by the PMAP lock. 2126 */ 2127 UNLOCK_TABLE(); 2128 pvo = uma_zalloc(zone, M_NOWAIT); 2129 LOCK_TABLE(); 2130 } 2131 2132 if (pvo == NULL) { 2133 UNLOCK_TABLE(); 2134 return (ENOMEM); 2135 } 2136 2137 moea64_pvo_entries++; 2138 pvo->pvo_vaddr = va; 2139 pvo->pvo_pmap = pm; 2140 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2141 pvo->pvo_vaddr &= ~ADDR_POFF; 2142 2143 if (!(flags & VM_PROT_EXECUTE)) 2144 pte_lo |= LPTE_NOEXEC; 2145 if (flags & PVO_WIRED) 2146 pvo->pvo_vaddr |= PVO_WIRED; 2147 if (pvo_head != &moea64_pvo_kunmanaged) 2148 pvo->pvo_vaddr |= PVO_MANAGED; 2149 if (bootstrap) 2150 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2151 if (flags & PVO_FAKE) 2152 pvo->pvo_vaddr |= PVO_FAKE; 2153 2154 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2155 (uint64_t)(pa) | pte_lo); 2156 2157 /* 2158 * Remember if the list was empty and therefore will be the first 2159 * item. 2160 */ 2161 if (LIST_FIRST(pvo_head) == NULL) 2162 first = 1; 2163 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2164 2165 if (pvo->pvo_vaddr & PVO_WIRED) 2166 pm->pm_stats.wired_count++; 2167 pm->pm_stats.resident_count++; 2168 2169 /* 2170 * We hope this succeeds but it isn't required. 2171 */ 2172 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2173 if (i >= 0) { 2174 PVO_PTEGIDX_SET(pvo, i); 2175 } else { 2176 panic("moea64_pvo_enter: overflow"); 2177 moea64_pte_overflow++; 2178 } 2179 2180 if (pm == kernel_pmap) 2181 isync(); 2182 2183 UNLOCK_TABLE(); 2184 2185 return (first ? ENOENT : 0); 2186 } 2187 2188 static void 2189 moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2190 { 2191 struct lpte *pt; 2192 2193 /* 2194 * If there is an active pte entry, we need to deactivate it (and 2195 * save the ref & cfg bits). 2196 */ 2197 LOCK_TABLE(); 2198 pt = moea64_pvo_to_pte(pvo, pteidx); 2199 if (pt != NULL) { 2200 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2201 PVO_VADDR(pvo)); 2202 PVO_PTEGIDX_CLR(pvo); 2203 } else { 2204 moea64_pte_overflow--; 2205 } 2206 2207 /* 2208 * Update our statistics. 2209 */ 2210 pvo->pvo_pmap->pm_stats.resident_count--; 2211 if (pvo->pvo_vaddr & PVO_WIRED) 2212 pvo->pvo_pmap->pm_stats.wired_count--; 2213 2214 /* 2215 * Save the REF/CHG bits into their cache if the page is managed. 2216 */ 2217 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2218 struct vm_page *pg; 2219 2220 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2221 if (pg != NULL) { 2222 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2223 (LPTE_REF | LPTE_CHG)); 2224 } 2225 } 2226 2227 /* 2228 * Remove this PVO from the PV list. 2229 */ 2230 LIST_REMOVE(pvo, pvo_vlink); 2231 2232 /* 2233 * Remove this from the overflow list and return it to the pool 2234 * if we aren't going to reuse it. 2235 */ 2236 LIST_REMOVE(pvo, pvo_olink); 2237 UNLOCK_TABLE(); 2238 2239 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2240 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2241 moea64_upvo_zone, pvo); 2242 2243 moea64_pvo_entries--; 2244 moea64_pvo_remove_calls++; 2245 } 2246 2247 static __inline int 2248 moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2249 { 2250 2251 /* 2252 * We can find the actual pte entry without searching by grabbing 2253 * the PTEG index from 3 unused bits in pvo_vaddr and by 2254 * noticing the HID bit. 2255 */ 2256 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2257 ptegidx ^= moea64_pteg_mask; 2258 2259 return ((ptegidx << 3) | PVO_PTEGIDX_GET(pvo)); 2260 } 2261 2262 static struct pvo_entry * 2263 moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2264 { 2265 struct pvo_entry *pvo; 2266 int ptegidx; 2267 uint64_t vsid; 2268 2269 va &= ~ADDR_POFF; 2270 vsid = va_to_vsid(pm, va); 2271 ptegidx = va_to_pteg(vsid, va); 2272 2273 LOCK_TABLE(); 2274 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2275 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2276 if (pteidx_p) 2277 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2278 break; 2279 } 2280 } 2281 UNLOCK_TABLE(); 2282 2283 return (pvo); 2284 } 2285 2286 static struct lpte * 2287 moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2288 { 2289 struct lpte *pt; 2290 2291 /* 2292 * If we haven't been supplied the ptegidx, calculate it. 2293 */ 2294 if (pteidx == -1) { 2295 int ptegidx; 2296 uint64_t vsid; 2297 2298 vsid = va_to_vsid(pvo->pvo_pmap, PVO_VADDR(pvo)); 2299 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo)); 2300 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2301 } 2302 2303 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2304 2305 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2306 !PVO_PTEGIDX_ISSET(pvo)) { 2307 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2308 "valid pte index", pvo); 2309 } 2310 2311 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2312 PVO_PTEGIDX_ISSET(pvo)) { 2313 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2314 "pvo but no valid pte", pvo); 2315 } 2316 2317 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2318 LPTE_VALID) { 2319 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2320 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2321 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2322 } 2323 2324 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2325 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { 2326 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2327 "pte %p in moea64_pteg_table difference is %#x", 2328 pvo, pt, 2329 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2330 } 2331 2332 ASSERT_TABLE_LOCK(); 2333 return (pt); 2334 } 2335 2336 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2337 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2338 "moea64_pteg_table but valid in pvo", pvo, pt); 2339 } 2340 2341 return (NULL); 2342 } 2343 2344 static int 2345 moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2346 { 2347 struct lpte *pt; 2348 int i; 2349 2350 ASSERT_TABLE_LOCK(); 2351 2352 /* 2353 * First try primary hash. 2354 */ 2355 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2356 if ((pt->pte_hi & LPTE_VALID) == 0 && 2357 (pt->pte_hi & LPTE_LOCKED) == 0) { 2358 pvo_pt->pte_hi &= ~LPTE_HID; 2359 moea64_pte_set(pt, pvo_pt); 2360 return (i); 2361 } 2362 } 2363 2364 /* 2365 * Now try secondary hash. 2366 */ 2367 ptegidx ^= moea64_pteg_mask; 2368 2369 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2370 if ((pt->pte_hi & LPTE_VALID) == 0 && 2371 (pt->pte_hi & LPTE_LOCKED) == 0) { 2372 pvo_pt->pte_hi |= LPTE_HID; 2373 moea64_pte_set(pt, pvo_pt); 2374 return (i); 2375 } 2376 } 2377 2378 panic("moea64_pte_insert: overflow"); 2379 return (-1); 2380 } 2381 2382 static boolean_t 2383 moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2384 { 2385 struct pvo_entry *pvo; 2386 struct lpte *pt; 2387 2388 if (moea64_attr_fetch(m) & ptebit) 2389 return (TRUE); 2390 2391 vm_page_lock_queues(); 2392 2393 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2394 MOEA_PVO_CHECK(pvo); /* sanity check */ 2395 2396 /* 2397 * See if we saved the bit off. If so, cache it and return 2398 * success. 2399 */ 2400 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2401 moea64_attr_save(m, ptebit); 2402 MOEA_PVO_CHECK(pvo); /* sanity check */ 2403 vm_page_unlock_queues(); 2404 return (TRUE); 2405 } 2406 } 2407 2408 /* 2409 * No luck, now go through the hard part of looking at the PTEs 2410 * themselves. Sync so that any pending REF/CHG bits are flushed to 2411 * the PTEs. 2412 */ 2413 SYNC(); 2414 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2415 MOEA_PVO_CHECK(pvo); /* sanity check */ 2416 2417 /* 2418 * See if this pvo has a valid PTE. if so, fetch the 2419 * REF/CHG bits from the valid PTE. If the appropriate 2420 * ptebit is set, cache it and return success. 2421 */ 2422 LOCK_TABLE(); 2423 pt = moea64_pvo_to_pte(pvo, -1); 2424 if (pt != NULL) { 2425 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2426 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2427 UNLOCK_TABLE(); 2428 2429 moea64_attr_save(m, ptebit); 2430 MOEA_PVO_CHECK(pvo); /* sanity check */ 2431 vm_page_unlock_queues(); 2432 return (TRUE); 2433 } 2434 } 2435 UNLOCK_TABLE(); 2436 } 2437 2438 vm_page_unlock_queues(); 2439 return (FALSE); 2440 } 2441 2442 static u_int 2443 moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 2444 { 2445 u_int count; 2446 struct pvo_entry *pvo; 2447 struct lpte *pt; 2448 2449 vm_page_lock_queues(); 2450 2451 /* 2452 * Clear the cached value. 2453 */ 2454 moea64_attr_clear(m, ptebit); 2455 2456 /* 2457 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2458 * we can reset the right ones). note that since the pvo entries and 2459 * list heads are accessed via BAT0 and are never placed in the page 2460 * table, we don't have to worry about further accesses setting the 2461 * REF/CHG bits. 2462 */ 2463 SYNC(); 2464 2465 /* 2466 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2467 * valid pte clear the ptebit from the valid pte. 2468 */ 2469 count = 0; 2470 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2471 MOEA_PVO_CHECK(pvo); /* sanity check */ 2472 2473 LOCK_TABLE(); 2474 pt = moea64_pvo_to_pte(pvo, -1); 2475 if (pt != NULL) { 2476 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2477 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2478 count++; 2479 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2480 } 2481 } 2482 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2483 MOEA_PVO_CHECK(pvo); /* sanity check */ 2484 UNLOCK_TABLE(); 2485 } 2486 2487 vm_page_unlock_queues(); 2488 return (count); 2489 } 2490 2491 boolean_t 2492 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2493 { 2494 struct pvo_entry *pvo; 2495 vm_offset_t ppa; 2496 int error = 0; 2497 2498 PMAP_LOCK(kernel_pmap); 2499 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2500 pvo = moea64_pvo_find_va(kernel_pmap, ppa, NULL); 2501 if (pvo == NULL || 2502 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2503 error = EFAULT; 2504 break; 2505 } 2506 } 2507 PMAP_UNLOCK(kernel_pmap); 2508 2509 return (error); 2510 } 2511 2512 /* 2513 * Map a set of physical memory pages into the kernel virtual 2514 * address space. Return a pointer to where it is mapped. This 2515 * routine is intended to be used for mapping device memory, 2516 * NOT real memory. 2517 */ 2518 void * 2519 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2520 { 2521 vm_offset_t va, tmpva, ppa, offset; 2522 2523 ppa = trunc_page(pa); 2524 offset = pa & PAGE_MASK; 2525 size = roundup(offset + size, PAGE_SIZE); 2526 2527 va = kmem_alloc_nofault(kernel_map, size); 2528 2529 if (!va) 2530 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2531 2532 for (tmpva = va; size > 0;) { 2533 moea64_kenter(mmu, tmpva, ppa); 2534 size -= PAGE_SIZE; 2535 tmpva += PAGE_SIZE; 2536 ppa += PAGE_SIZE; 2537 } 2538 2539 return ((void *)(va + offset)); 2540 } 2541 2542 void 2543 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2544 { 2545 vm_offset_t base, offset; 2546 2547 base = trunc_page(va); 2548 offset = va & PAGE_MASK; 2549 size = roundup(offset + size, PAGE_SIZE); 2550 2551 kmem_free(kernel_map, base, size); 2552 } 2553 2554 static void 2555 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2556 { 2557 struct pvo_entry *pvo; 2558 vm_offset_t lim; 2559 vm_paddr_t pa; 2560 vm_size_t len; 2561 2562 PMAP_LOCK(pm); 2563 while (sz > 0) { 2564 lim = round_page(va); 2565 len = MIN(lim - va, sz); 2566 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2567 if (pvo != NULL) { 2568 pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | 2569 (va & ADDR_POFF); 2570 moea64_syncicache(pm, va, pa, len); 2571 } 2572 va += len; 2573 sz -= len; 2574 } 2575 PMAP_UNLOCK(pm); 2576 } 2577