1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* 31 * Manages physical address maps. 32 * 33 * Since the information managed by this module is also stored by the 34 * logical address mapping module, this module may throw away valid virtual 35 * to physical mappings at almost any time. However, invalidations of 36 * mappings must be done as requested. 37 * 38 * In order to cope with hardware architectures which make virtual to 39 * physical map invalidates expensive, this module may delay invalidate 40 * reduced protection operations until such time as they are actually 41 * necessary. This module is given full information as to which processors 42 * are currently using which maps, and to when physical maps must be made 43 * correct. 44 */ 45 46 #include "opt_kstack_pages.h" 47 48 #include <sys/param.h> 49 #include <sys/kernel.h> 50 #include <sys/conf.h> 51 #include <sys/queue.h> 52 #include <sys/cpuset.h> 53 #include <sys/kerneldump.h> 54 #include <sys/ktr.h> 55 #include <sys/lock.h> 56 #include <sys/msgbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/mman.h> 59 #include <sys/mutex.h> 60 #include <sys/proc.h> 61 #include <sys/rwlock.h> 62 #include <sys/sched.h> 63 #include <sys/sysctl.h> 64 #include <sys/systm.h> 65 #include <sys/vmmeter.h> 66 #include <sys/smp.h> 67 #include <sys/reboot.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/pmap.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_kern.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_phys.h> 79 #include <vm/vm_map.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_extern.h> 82 #include <vm/vm_pageout.h> 83 #include <vm/vm_dumpset.h> 84 #include <vm/vm_radix.h> 85 #include <vm/vm_reserv.h> 86 #include <vm/uma.h> 87 88 #include <machine/_inttypes.h> 89 #include <machine/cpu.h> 90 #include <machine/ifunc.h> 91 #include <machine/platform.h> 92 #include <machine/frame.h> 93 #include <machine/md_var.h> 94 #include <machine/psl.h> 95 #include <machine/bat.h> 96 #include <machine/hid.h> 97 #include <machine/pte.h> 98 #include <machine/sr.h> 99 #include <machine/trap.h> 100 #include <machine/mmuvar.h> 101 102 #include "mmu_oea64.h" 103 104 void moea64_release_vsid(uint64_t vsid); 105 uintptr_t moea64_get_unique_vsid(void); 106 107 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 108 #define ENABLE_TRANS(msr) mtmsr(msr) 109 110 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 111 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 112 #define VSID_HASH_MASK 0x0000007fffffffffULL 113 114 /* 115 * Locking semantics: 116 * 117 * There are two locks of interest: the page locks and the pmap locks, which 118 * protect their individual PVO lists and are locked in that order. The contents 119 * of all PVO entries are protected by the locks of their respective pmaps. 120 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 121 * into any list. 122 * 123 */ 124 125 #define PV_LOCK_COUNT MAXCPU 126 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 127 128 #define PV_LOCK_SHIFT 21 129 #define pa_index(pa) ((pa) >> PV_LOCK_SHIFT) 130 131 /* 132 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 133 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 134 * index at (N << 45). 135 */ 136 #ifdef __powerpc64__ 137 #define PV_LOCK_IDX(pa) ((pa_index(pa) * (((pa) >> 45) + 1)) % PV_LOCK_COUNT) 138 #else 139 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 140 #endif 141 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 142 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 143 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 144 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 145 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 146 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 147 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 148 149 /* Superpage PV lock */ 150 151 #define PV_LOCK_SIZE (1 << PV_LOCK_SHIFT) 152 153 static __always_inline void 154 moea64_sp_pv_lock(vm_paddr_t pa) 155 { 156 vm_paddr_t pa_end; 157 158 /* Note: breaking when pa_end is reached to avoid overflows */ 159 pa_end = pa + (HPT_SP_SIZE - PV_LOCK_SIZE); 160 for (;;) { 161 mtx_lock_flags(PV_LOCKPTR(pa), MTX_DUPOK); 162 if (pa == pa_end) 163 break; 164 pa += PV_LOCK_SIZE; 165 } 166 } 167 168 static __always_inline void 169 moea64_sp_pv_unlock(vm_paddr_t pa) 170 { 171 vm_paddr_t pa_end; 172 173 /* Note: breaking when pa_end is reached to avoid overflows */ 174 pa_end = pa; 175 pa += HPT_SP_SIZE - PV_LOCK_SIZE; 176 for (;;) { 177 mtx_unlock_flags(PV_LOCKPTR(pa), MTX_DUPOK); 178 if (pa == pa_end) 179 break; 180 pa -= PV_LOCK_SIZE; 181 } 182 } 183 184 #define SP_PV_LOCK_ALIGNED(pa) moea64_sp_pv_lock(pa) 185 #define SP_PV_UNLOCK_ALIGNED(pa) moea64_sp_pv_unlock(pa) 186 #define SP_PV_LOCK(pa) moea64_sp_pv_lock((pa) & ~HPT_SP_MASK) 187 #define SP_PV_UNLOCK(pa) moea64_sp_pv_unlock((pa) & ~HPT_SP_MASK) 188 #define SP_PV_PAGE_LOCK(m) SP_PV_LOCK(VM_PAGE_TO_PHYS(m)) 189 #define SP_PV_PAGE_UNLOCK(m) SP_PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 190 191 struct ofw_map { 192 cell_t om_va; 193 cell_t om_len; 194 uint64_t om_pa; 195 cell_t om_mode; 196 }; 197 198 extern unsigned char _etext[]; 199 extern unsigned char _end[]; 200 201 extern void *slbtrap, *slbtrapend; 202 203 /* 204 * Map of physical memory regions. 205 */ 206 static struct mem_region *regions; 207 static struct mem_region *pregions; 208 static struct numa_mem_region *numa_pregions; 209 static u_int phys_avail_count; 210 static int regions_sz, pregions_sz, numapregions_sz; 211 212 extern void bs_remap_earlyboot(void); 213 214 /* 215 * Lock for the SLB tables. 216 */ 217 struct mtx moea64_slb_mutex; 218 219 /* 220 * PTEG data. 221 */ 222 u_long moea64_pteg_count; 223 u_long moea64_pteg_mask; 224 225 /* 226 * PVO data. 227 */ 228 229 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 230 231 static struct pvo_entry *moea64_bpvo_pool; 232 static int moea64_bpvo_pool_index = 0; 233 static int moea64_bpvo_pool_size = 0; 234 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 235 &moea64_bpvo_pool_index, 0, ""); 236 237 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */ 238 #define BPVO_POOL_EXPANSION_FACTOR 3 239 #define VSID_NBPW (sizeof(u_int32_t) * 8) 240 #ifdef __powerpc64__ 241 #define NVSIDS (NPMAPS * 16) 242 #define VSID_HASHMASK 0xffffffffUL 243 #else 244 #define NVSIDS NPMAPS 245 #define VSID_HASHMASK 0xfffffUL 246 #endif 247 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 248 249 static bool moea64_initialized = false; 250 251 #ifdef MOEA64_STATS 252 /* 253 * Statistics. 254 */ 255 u_int moea64_pte_valid = 0; 256 u_int moea64_pte_overflow = 0; 257 u_int moea64_pvo_entries = 0; 258 u_int moea64_pvo_enter_calls = 0; 259 u_int moea64_pvo_remove_calls = 0; 260 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 261 &moea64_pte_valid, 0, ""); 262 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 263 &moea64_pte_overflow, 0, ""); 264 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 265 &moea64_pvo_entries, 0, ""); 266 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 267 &moea64_pvo_enter_calls, 0, ""); 268 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 269 &moea64_pvo_remove_calls, 0, ""); 270 #endif 271 272 vm_offset_t moea64_scratchpage_va[2]; 273 struct pvo_entry *moea64_scratchpage_pvo[2]; 274 struct mtx moea64_scratchpage_mtx; 275 276 uint64_t moea64_large_page_mask = 0; 277 uint64_t moea64_large_page_size = 0; 278 int moea64_large_page_shift = 0; 279 bool moea64_has_lp_4k_16m = false; 280 281 /* 282 * PVO calls. 283 */ 284 static int moea64_pvo_enter(struct pvo_entry *pvo, 285 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 286 static void moea64_pvo_remove_from_pmap(struct pvo_entry *pvo); 287 static void moea64_pvo_remove_from_page(struct pvo_entry *pvo); 288 static void moea64_pvo_remove_from_page_locked( 289 struct pvo_entry *pvo, vm_page_t m); 290 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 291 292 /* 293 * Utility routines. 294 */ 295 static bool moea64_query_bit(vm_page_t, uint64_t); 296 static u_int moea64_clear_bit(vm_page_t, uint64_t); 297 static void moea64_kremove(vm_offset_t); 298 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 299 vm_paddr_t pa, vm_size_t sz); 300 static void moea64_pmap_init_qpages(void *); 301 static void moea64_remove_locked(pmap_t, vm_offset_t, 302 vm_offset_t, struct pvo_dlist *); 303 304 /* 305 * Superpages data and routines. 306 */ 307 308 /* 309 * PVO flags (in vaddr) that must match for promotion to succeed. 310 * Note that protection bits are checked separately, as they reside in 311 * another field. 312 */ 313 #define PVO_FLAGS_PROMOTE (PVO_WIRED | PVO_MANAGED | PVO_PTEGIDX_VALID) 314 315 #define PVO_IS_SP(pvo) (((pvo)->pvo_vaddr & PVO_LARGE) && \ 316 (pvo)->pvo_pmap != kernel_pmap) 317 318 /* Get physical address from PVO. */ 319 #define PVO_PADDR(pvo) moea64_pvo_paddr(pvo) 320 321 /* MD page flag indicating that the page is a superpage. */ 322 #define MDPG_ATTR_SP 0x40000000 323 324 SYSCTL_DECL(_vm_pmap); 325 326 static SYSCTL_NODE(_vm_pmap, OID_AUTO, sp, CTLFLAG_RD, 0, 327 "SP page mapping counters"); 328 329 static u_long sp_demotions; 330 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, demotions, CTLFLAG_RD, 331 &sp_demotions, 0, "SP page demotions"); 332 333 static u_long sp_mappings; 334 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, mappings, CTLFLAG_RD, 335 &sp_mappings, 0, "SP page mappings"); 336 337 static u_long sp_p_failures; 338 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_failures, CTLFLAG_RD, 339 &sp_p_failures, 0, "SP page promotion failures"); 340 341 static u_long sp_p_fail_pa; 342 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_pa, CTLFLAG_RD, 343 &sp_p_fail_pa, 0, "SP page promotion failure: PAs don't match"); 344 345 static u_long sp_p_fail_flags; 346 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_flags, CTLFLAG_RD, 347 &sp_p_fail_flags, 0, "SP page promotion failure: page flags don't match"); 348 349 static u_long sp_p_fail_prot; 350 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_prot, CTLFLAG_RD, 351 &sp_p_fail_prot, 0, 352 "SP page promotion failure: page protections don't match"); 353 354 static u_long sp_p_fail_wimg; 355 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_wimg, CTLFLAG_RD, 356 &sp_p_fail_wimg, 0, "SP page promotion failure: WIMG bits don't match"); 357 358 static u_long sp_promotions; 359 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, promotions, CTLFLAG_RD, 360 &sp_promotions, 0, "SP page promotions"); 361 362 static bool moea64_ps_enabled(pmap_t); 363 static void moea64_align_superpage(vm_object_t, vm_ooffset_t, 364 vm_offset_t *, vm_size_t); 365 366 static int moea64_sp_enter(pmap_t pmap, vm_offset_t va, 367 vm_page_t m, vm_prot_t prot, u_int flags, int8_t psind); 368 static struct pvo_entry *moea64_sp_remove(struct pvo_entry *sp, 369 struct pvo_dlist *tofree); 370 371 #if VM_NRESERVLEVEL > 0 372 static void moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m); 373 #endif 374 static void moea64_sp_demote_aligned(struct pvo_entry *sp); 375 static void moea64_sp_demote(struct pvo_entry *pvo); 376 377 static struct pvo_entry *moea64_sp_unwire(struct pvo_entry *sp); 378 static struct pvo_entry *moea64_sp_protect(struct pvo_entry *sp, 379 vm_prot_t prot); 380 381 static int64_t moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit); 382 static int64_t moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, 383 uint64_t ptebit); 384 385 static __inline bool moea64_sp_pvo_in_range(struct pvo_entry *pvo, 386 vm_offset_t sva, vm_offset_t eva); 387 388 /* 389 * Kernel MMU interface 390 */ 391 void moea64_clear_modify(vm_page_t); 392 void moea64_copy_page(vm_page_t, vm_page_t); 393 void moea64_copy_page_dmap(vm_page_t, vm_page_t); 394 void moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 395 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 396 void moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 397 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 398 int moea64_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 399 u_int flags, int8_t psind); 400 void moea64_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 401 vm_prot_t); 402 void moea64_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 403 vm_paddr_t moea64_extract(pmap_t, vm_offset_t); 404 vm_page_t moea64_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 405 void moea64_init(void); 406 bool moea64_is_modified(vm_page_t); 407 bool moea64_is_prefaultable(pmap_t, vm_offset_t); 408 bool moea64_is_referenced(vm_page_t); 409 int moea64_ts_referenced(vm_page_t); 410 vm_offset_t moea64_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 411 bool moea64_page_exists_quick(pmap_t, vm_page_t); 412 void moea64_page_init(vm_page_t); 413 int moea64_page_wired_mappings(vm_page_t); 414 int moea64_pinit(pmap_t); 415 void moea64_pinit0(pmap_t); 416 void moea64_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 417 void moea64_qenter(vm_offset_t, vm_page_t *, int); 418 void moea64_qremove(vm_offset_t, int); 419 void moea64_release(pmap_t); 420 void moea64_remove(pmap_t, vm_offset_t, vm_offset_t); 421 void moea64_remove_pages(pmap_t); 422 void moea64_remove_all(vm_page_t); 423 void moea64_remove_write(vm_page_t); 424 void moea64_unwire(pmap_t, vm_offset_t, vm_offset_t); 425 void moea64_zero_page(vm_page_t); 426 void moea64_zero_page_dmap(vm_page_t); 427 void moea64_zero_page_area(vm_page_t, int, int); 428 void moea64_activate(struct thread *); 429 void moea64_deactivate(struct thread *); 430 void *moea64_mapdev(vm_paddr_t, vm_size_t); 431 void *moea64_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 432 void moea64_unmapdev(void *, vm_size_t); 433 vm_paddr_t moea64_kextract(vm_offset_t); 434 void moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma); 435 void moea64_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t ma); 436 void moea64_kenter(vm_offset_t, vm_paddr_t); 437 int moea64_dev_direct_mapped(vm_paddr_t, vm_size_t); 438 static void moea64_sync_icache(pmap_t, vm_offset_t, vm_size_t); 439 void moea64_dumpsys_map(vm_paddr_t pa, size_t sz, 440 void **va); 441 void moea64_scan_init(void); 442 vm_offset_t moea64_quick_enter_page(vm_page_t m); 443 vm_offset_t moea64_quick_enter_page_dmap(vm_page_t m); 444 void moea64_quick_remove_page(vm_offset_t addr); 445 bool moea64_page_is_mapped(vm_page_t m); 446 static int moea64_map_user_ptr(pmap_t pm, 447 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 448 static int moea64_decode_kernel_ptr(vm_offset_t addr, 449 int *is_user, vm_offset_t *decoded_addr); 450 static size_t moea64_scan_pmap(struct bitset *dump_bitset); 451 static void *moea64_dump_pmap_init(unsigned blkpgs); 452 #ifdef __powerpc64__ 453 static void moea64_page_array_startup(long); 454 #endif 455 static int moea64_mincore(pmap_t, vm_offset_t, vm_paddr_t *); 456 457 static struct pmap_funcs moea64_methods = { 458 .clear_modify = moea64_clear_modify, 459 .copy_page = moea64_copy_page, 460 .copy_pages = moea64_copy_pages, 461 .enter = moea64_enter, 462 .enter_object = moea64_enter_object, 463 .enter_quick = moea64_enter_quick, 464 .extract = moea64_extract, 465 .extract_and_hold = moea64_extract_and_hold, 466 .init = moea64_init, 467 .is_modified = moea64_is_modified, 468 .is_prefaultable = moea64_is_prefaultable, 469 .is_referenced = moea64_is_referenced, 470 .ts_referenced = moea64_ts_referenced, 471 .map = moea64_map, 472 .mincore = moea64_mincore, 473 .page_exists_quick = moea64_page_exists_quick, 474 .page_init = moea64_page_init, 475 .page_wired_mappings = moea64_page_wired_mappings, 476 .pinit = moea64_pinit, 477 .pinit0 = moea64_pinit0, 478 .protect = moea64_protect, 479 .qenter = moea64_qenter, 480 .qremove = moea64_qremove, 481 .release = moea64_release, 482 .remove = moea64_remove, 483 .remove_pages = moea64_remove_pages, 484 .remove_all = moea64_remove_all, 485 .remove_write = moea64_remove_write, 486 .sync_icache = moea64_sync_icache, 487 .unwire = moea64_unwire, 488 .zero_page = moea64_zero_page, 489 .zero_page_area = moea64_zero_page_area, 490 .activate = moea64_activate, 491 .deactivate = moea64_deactivate, 492 .page_set_memattr = moea64_page_set_memattr, 493 .quick_enter_page = moea64_quick_enter_page, 494 .quick_remove_page = moea64_quick_remove_page, 495 .page_is_mapped = moea64_page_is_mapped, 496 #ifdef __powerpc64__ 497 .page_array_startup = moea64_page_array_startup, 498 #endif 499 .ps_enabled = moea64_ps_enabled, 500 .align_superpage = moea64_align_superpage, 501 502 /* Internal interfaces */ 503 .mapdev = moea64_mapdev, 504 .mapdev_attr = moea64_mapdev_attr, 505 .unmapdev = moea64_unmapdev, 506 .kextract = moea64_kextract, 507 .kenter = moea64_kenter, 508 .kenter_attr = moea64_kenter_attr, 509 .dev_direct_mapped = moea64_dev_direct_mapped, 510 .dumpsys_pa_init = moea64_scan_init, 511 .dumpsys_scan_pmap = moea64_scan_pmap, 512 .dumpsys_dump_pmap_init = moea64_dump_pmap_init, 513 .dumpsys_map_chunk = moea64_dumpsys_map, 514 .map_user_ptr = moea64_map_user_ptr, 515 .decode_kernel_ptr = moea64_decode_kernel_ptr, 516 }; 517 518 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods); 519 520 /* 521 * Get physical address from PVO. 522 * 523 * For superpages, the lower bits are not stored on pvo_pte.pa and must be 524 * obtained from VA. 525 */ 526 static __always_inline vm_paddr_t 527 moea64_pvo_paddr(struct pvo_entry *pvo) 528 { 529 vm_paddr_t pa; 530 531 pa = (pvo)->pvo_pte.pa & LPTE_RPGN; 532 533 if (PVO_IS_SP(pvo)) { 534 pa &= ~HPT_SP_MASK; /* This is needed to clear LPTE_LP bits. */ 535 pa |= PVO_VADDR(pvo) & HPT_SP_MASK; 536 } 537 return (pa); 538 } 539 540 static struct pvo_head * 541 vm_page_to_pvoh(vm_page_t m) 542 { 543 544 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 545 return (&m->md.mdpg_pvoh); 546 } 547 548 static struct pvo_entry * 549 alloc_pvo_entry(int bootstrap) 550 { 551 struct pvo_entry *pvo; 552 553 if (!moea64_initialized || bootstrap) { 554 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 555 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 556 "Try setting machdep.moea64_bpvo_pool_size tunable", 557 __func__, moea64_bpvo_pool_index, 558 moea64_bpvo_pool_size, 559 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 560 } 561 pvo = &moea64_bpvo_pool[ 562 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 563 bzero(pvo, sizeof(*pvo)); 564 pvo->pvo_vaddr = PVO_BOOTSTRAP; 565 } else 566 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 567 568 return (pvo); 569 } 570 571 static void 572 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 573 { 574 uint64_t vsid; 575 uint64_t hash; 576 int shift; 577 578 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 579 580 pvo->pvo_pmap = pmap; 581 va &= ~ADDR_POFF; 582 pvo->pvo_vaddr |= va; 583 vsid = va_to_vsid(pmap, va); 584 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 585 | (vsid << 16); 586 587 if (pmap == kernel_pmap && (pvo->pvo_vaddr & PVO_LARGE) != 0) 588 shift = moea64_large_page_shift; 589 else 590 shift = ADDR_PIDX_SHFT; 591 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 592 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 593 } 594 595 static void 596 free_pvo_entry(struct pvo_entry *pvo) 597 { 598 599 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 600 uma_zfree(moea64_pvo_zone, pvo); 601 } 602 603 void 604 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 605 { 606 607 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 608 lpte->pte_hi |= LPTE_VALID; 609 610 if (pvo->pvo_vaddr & PVO_LARGE) 611 lpte->pte_hi |= LPTE_BIG; 612 if (pvo->pvo_vaddr & PVO_WIRED) 613 lpte->pte_hi |= LPTE_WIRED; 614 if (pvo->pvo_vaddr & PVO_HID) 615 lpte->pte_hi |= LPTE_HID; 616 617 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 618 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 619 lpte->pte_lo |= LPTE_BW; 620 else 621 lpte->pte_lo |= LPTE_BR; 622 623 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 624 lpte->pte_lo |= LPTE_NOEXEC; 625 } 626 627 static __inline uint64_t 628 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 629 { 630 uint64_t pte_lo; 631 int i; 632 633 if (ma != VM_MEMATTR_DEFAULT) { 634 switch (ma) { 635 case VM_MEMATTR_UNCACHEABLE: 636 return (LPTE_I | LPTE_G); 637 case VM_MEMATTR_CACHEABLE: 638 return (LPTE_M); 639 case VM_MEMATTR_WRITE_COMBINING: 640 case VM_MEMATTR_WRITE_BACK: 641 case VM_MEMATTR_PREFETCHABLE: 642 return (LPTE_I); 643 case VM_MEMATTR_WRITE_THROUGH: 644 return (LPTE_W | LPTE_M); 645 } 646 } 647 648 /* 649 * Assume the page is cache inhibited and access is guarded unless 650 * it's in our available memory array. 651 */ 652 pte_lo = LPTE_I | LPTE_G; 653 for (i = 0; i < pregions_sz; i++) { 654 if ((pa >= pregions[i].mr_start) && 655 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 656 pte_lo &= ~(LPTE_I | LPTE_G); 657 pte_lo |= LPTE_M; 658 break; 659 } 660 } 661 662 return pte_lo; 663 } 664 665 /* 666 * Quick sort callout for comparing memory regions. 667 */ 668 static int om_cmp(const void *a, const void *b); 669 670 static int 671 om_cmp(const void *a, const void *b) 672 { 673 const struct ofw_map *mapa; 674 const struct ofw_map *mapb; 675 676 mapa = a; 677 mapb = b; 678 if (mapa->om_pa < mapb->om_pa) 679 return (-1); 680 else if (mapa->om_pa > mapb->om_pa) 681 return (1); 682 else 683 return (0); 684 } 685 686 static void 687 moea64_add_ofw_mappings(phandle_t mmu, size_t sz) 688 { 689 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 690 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 691 struct pvo_entry *pvo; 692 register_t msr; 693 vm_offset_t off; 694 vm_paddr_t pa_base; 695 int i, j; 696 697 bzero(translations, sz); 698 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 699 sizeof(acells)); 700 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 701 panic("moea64_bootstrap: can't get ofw translations"); 702 703 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 704 sz /= sizeof(cell_t); 705 for (i = 0, j = 0; i < sz; j++) { 706 translations[j].om_va = trans_cells[i++]; 707 translations[j].om_len = trans_cells[i++]; 708 translations[j].om_pa = trans_cells[i++]; 709 if (acells == 2) { 710 translations[j].om_pa <<= 32; 711 translations[j].om_pa |= trans_cells[i++]; 712 } 713 translations[j].om_mode = trans_cells[i++]; 714 } 715 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 716 i, sz)); 717 718 sz = j; 719 qsort(translations, sz, sizeof (*translations), om_cmp); 720 721 for (i = 0; i < sz; i++) { 722 pa_base = translations[i].om_pa; 723 #ifndef __powerpc64__ 724 if ((translations[i].om_pa >> 32) != 0) 725 panic("OFW translations above 32-bit boundary!"); 726 #endif 727 728 if (pa_base % PAGE_SIZE) 729 panic("OFW translation not page-aligned (phys)!"); 730 if (translations[i].om_va % PAGE_SIZE) 731 panic("OFW translation not page-aligned (virt)!"); 732 733 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 734 pa_base, translations[i].om_va, translations[i].om_len); 735 736 /* Now enter the pages for this mapping */ 737 738 DISABLE_TRANS(msr); 739 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 740 /* If this address is direct-mapped, skip remapping */ 741 if (hw_direct_map && 742 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 743 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 744 == LPTE_M) 745 continue; 746 747 PMAP_LOCK(kernel_pmap); 748 pvo = moea64_pvo_find_va(kernel_pmap, 749 translations[i].om_va + off); 750 PMAP_UNLOCK(kernel_pmap); 751 if (pvo != NULL) 752 continue; 753 754 moea64_kenter(translations[i].om_va + off, 755 pa_base + off); 756 } 757 ENABLE_TRANS(msr); 758 } 759 } 760 761 #ifdef __powerpc64__ 762 static void 763 moea64_probe_large_page(void) 764 { 765 uint16_t pvr = mfpvr() >> 16; 766 767 switch (pvr) { 768 case IBM970: 769 case IBM970FX: 770 case IBM970MP: 771 powerpc_sync(); isync(); 772 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 773 powerpc_sync(); isync(); 774 775 /* FALLTHROUGH */ 776 default: 777 if (moea64_large_page_size == 0) { 778 moea64_large_page_size = 0x1000000; /* 16 MB */ 779 moea64_large_page_shift = 24; 780 } 781 } 782 783 moea64_large_page_mask = moea64_large_page_size - 1; 784 } 785 786 static void 787 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 788 { 789 struct slb *cache; 790 struct slb entry; 791 uint64_t esid, slbe; 792 uint64_t i; 793 794 cache = PCPU_GET(aim.slb); 795 esid = va >> ADDR_SR_SHFT; 796 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 797 798 for (i = 0; i < 64; i++) { 799 if (cache[i].slbe == (slbe | i)) 800 return; 801 } 802 803 entry.slbe = slbe; 804 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 805 if (large) 806 entry.slbv |= SLBV_L; 807 808 slb_insert_kernel(entry.slbe, entry.slbv); 809 } 810 #endif 811 812 static int 813 moea64_kenter_large(vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 814 { 815 struct pvo_entry *pvo; 816 uint64_t pte_lo; 817 int error; 818 819 pte_lo = LPTE_M; 820 pte_lo |= attr; 821 822 pvo = alloc_pvo_entry(bootstrap); 823 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 824 init_pvo_entry(pvo, kernel_pmap, va); 825 826 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 827 VM_PROT_EXECUTE; 828 pvo->pvo_pte.pa = pa | pte_lo; 829 error = moea64_pvo_enter(pvo, NULL, NULL); 830 if (error != 0) 831 panic("Error %d inserting large page\n", error); 832 return (0); 833 } 834 835 static void 836 moea64_setup_direct_map(vm_offset_t kernelstart, 837 vm_offset_t kernelend) 838 { 839 register_t msr; 840 vm_paddr_t pa, pkernelstart, pkernelend; 841 vm_offset_t size, off; 842 uint64_t pte_lo; 843 int i; 844 845 if (moea64_large_page_size == 0) 846 hw_direct_map = 0; 847 848 DISABLE_TRANS(msr); 849 if (hw_direct_map) { 850 PMAP_LOCK(kernel_pmap); 851 for (i = 0; i < pregions_sz; i++) { 852 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 853 pregions[i].mr_size; pa += moea64_large_page_size) { 854 pte_lo = LPTE_M; 855 if (pa & moea64_large_page_mask) { 856 pa &= moea64_large_page_mask; 857 pte_lo |= LPTE_G; 858 } 859 if (pa + moea64_large_page_size > 860 pregions[i].mr_start + pregions[i].mr_size) 861 pte_lo |= LPTE_G; 862 863 moea64_kenter_large(PHYS_TO_DMAP(pa), pa, pte_lo, 1); 864 } 865 } 866 PMAP_UNLOCK(kernel_pmap); 867 } 868 869 /* 870 * Make sure the kernel and BPVO pool stay mapped on systems either 871 * without a direct map or on which the kernel is not already executing 872 * out of the direct-mapped region. 873 */ 874 if (kernelstart < DMAP_BASE_ADDRESS) { 875 /* 876 * For pre-dmap execution, we need to use identity mapping 877 * because we will be operating with the mmu on but in the 878 * wrong address configuration until we __restartkernel(). 879 */ 880 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 881 pa += PAGE_SIZE) 882 moea64_kenter(pa, pa); 883 } else if (!hw_direct_map) { 884 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 885 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 886 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 887 pa += PAGE_SIZE) 888 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 889 } 890 891 if (!hw_direct_map) { 892 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 893 off = (vm_offset_t)(moea64_bpvo_pool); 894 for (pa = off; pa < off + size; pa += PAGE_SIZE) 895 moea64_kenter(pa, pa); 896 897 /* Map exception vectors */ 898 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 899 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 900 } 901 ENABLE_TRANS(msr); 902 903 /* 904 * Allow user to override unmapped_buf_allowed for testing. 905 * XXXKIB Only direct map implementation was tested. 906 */ 907 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 908 &unmapped_buf_allowed)) 909 unmapped_buf_allowed = hw_direct_map; 910 } 911 912 /* Quick sort callout for comparing physical addresses. */ 913 static int 914 pa_cmp(const void *a, const void *b) 915 { 916 const vm_paddr_t *pa = a, *pb = b; 917 918 if (*pa < *pb) 919 return (-1); 920 else if (*pa > *pb) 921 return (1); 922 else 923 return (0); 924 } 925 926 void 927 moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 928 { 929 int i, j; 930 vm_size_t physsz, hwphyssz; 931 vm_paddr_t kernelphysstart, kernelphysend; 932 int rm_pavail; 933 934 /* Level 0 reservations consist of 4096 pages (16MB superpage). */ 935 vm_level_0_order = 12; 936 937 #ifndef __powerpc64__ 938 /* We don't have a direct map since there is no BAT */ 939 hw_direct_map = 0; 940 941 /* Make sure battable is zero, since we have no BAT */ 942 for (i = 0; i < 16; i++) { 943 battable[i].batu = 0; 944 battable[i].batl = 0; 945 } 946 #else 947 /* Install trap handlers for SLBs */ 948 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 949 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 950 __syncicache((void *)EXC_DSE, 0x80); 951 __syncicache((void *)EXC_ISE, 0x80); 952 #endif 953 954 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 955 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 956 957 /* Get physical memory regions from firmware */ 958 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 959 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 960 961 if (PHYS_AVAIL_ENTRIES < regions_sz) 962 panic("moea64_bootstrap: phys_avail too small"); 963 964 phys_avail_count = 0; 965 physsz = 0; 966 hwphyssz = 0; 967 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 968 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 969 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 970 regions[i].mr_start, regions[i].mr_start + 971 regions[i].mr_size, regions[i].mr_size); 972 if (hwphyssz != 0 && 973 (physsz + regions[i].mr_size) >= hwphyssz) { 974 if (physsz < hwphyssz) { 975 phys_avail[j] = regions[i].mr_start; 976 phys_avail[j + 1] = regions[i].mr_start + 977 hwphyssz - physsz; 978 physsz = hwphyssz; 979 phys_avail_count++; 980 dump_avail[j] = phys_avail[j]; 981 dump_avail[j + 1] = phys_avail[j + 1]; 982 } 983 break; 984 } 985 phys_avail[j] = regions[i].mr_start; 986 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 987 phys_avail_count++; 988 physsz += regions[i].mr_size; 989 dump_avail[j] = phys_avail[j]; 990 dump_avail[j + 1] = phys_avail[j + 1]; 991 } 992 993 /* Check for overlap with the kernel and exception vectors */ 994 rm_pavail = 0; 995 for (j = 0; j < 2*phys_avail_count; j+=2) { 996 if (phys_avail[j] < EXC_LAST) 997 phys_avail[j] += EXC_LAST; 998 999 if (phys_avail[j] >= kernelphysstart && 1000 phys_avail[j+1] <= kernelphysend) { 1001 phys_avail[j] = phys_avail[j+1] = ~0; 1002 rm_pavail++; 1003 continue; 1004 } 1005 1006 if (kernelphysstart >= phys_avail[j] && 1007 kernelphysstart < phys_avail[j+1]) { 1008 if (kernelphysend < phys_avail[j+1]) { 1009 phys_avail[2*phys_avail_count] = 1010 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 1011 phys_avail[2*phys_avail_count + 1] = 1012 phys_avail[j+1]; 1013 phys_avail_count++; 1014 } 1015 1016 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 1017 } 1018 1019 if (kernelphysend >= phys_avail[j] && 1020 kernelphysend < phys_avail[j+1]) { 1021 if (kernelphysstart > phys_avail[j]) { 1022 phys_avail[2*phys_avail_count] = phys_avail[j]; 1023 phys_avail[2*phys_avail_count + 1] = 1024 kernelphysstart & ~PAGE_MASK; 1025 phys_avail_count++; 1026 } 1027 1028 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 1029 PAGE_SIZE; 1030 } 1031 } 1032 1033 /* Remove physical available regions marked for removal (~0) */ 1034 if (rm_pavail) { 1035 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 1036 pa_cmp); 1037 phys_avail_count -= rm_pavail; 1038 for (i = 2*phys_avail_count; 1039 i < 2*(phys_avail_count + rm_pavail); i+=2) 1040 phys_avail[i] = phys_avail[i+1] = 0; 1041 } 1042 1043 physmem = btoc(physsz); 1044 1045 #ifdef PTEGCOUNT 1046 moea64_pteg_count = PTEGCOUNT; 1047 #else 1048 moea64_pteg_count = 0x1000; 1049 1050 while (moea64_pteg_count < physmem) 1051 moea64_pteg_count <<= 1; 1052 1053 moea64_pteg_count >>= 1; 1054 #endif /* PTEGCOUNT */ 1055 } 1056 1057 void 1058 moea64_mid_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 1059 { 1060 int i; 1061 1062 /* 1063 * Set PTEG mask 1064 */ 1065 moea64_pteg_mask = moea64_pteg_count - 1; 1066 1067 /* 1068 * Initialize SLB table lock and page locks 1069 */ 1070 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 1071 for (i = 0; i < PV_LOCK_COUNT; i++) 1072 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 1073 1074 /* 1075 * Initialise the bootstrap pvo pool. 1076 */ 1077 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 1078 if (moea64_bpvo_pool_size == 0) { 1079 if (!hw_direct_map) 1080 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) / 1081 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR; 1082 else 1083 moea64_bpvo_pool_size = BPVO_POOL_SIZE; 1084 } 1085 1086 if (boothowto & RB_VERBOSE) { 1087 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n", 1088 moea64_bpvo_pool_size, 1089 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576); 1090 } 1091 1092 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 1093 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 1094 moea64_bpvo_pool_index = 0; 1095 1096 /* Place at address usable through the direct map */ 1097 if (hw_direct_map) 1098 moea64_bpvo_pool = (struct pvo_entry *) 1099 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 1100 1101 /* 1102 * Make sure kernel vsid is allocated as well as VSID 0. 1103 */ 1104 #ifndef __powerpc64__ 1105 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 1106 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 1107 moea64_vsid_bitmap[0] |= 1; 1108 #endif 1109 1110 /* 1111 * Initialize the kernel pmap (which is statically allocated). 1112 */ 1113 #ifdef __powerpc64__ 1114 for (i = 0; i < 64; i++) { 1115 pcpup->pc_aim.slb[i].slbv = 0; 1116 pcpup->pc_aim.slb[i].slbe = 0; 1117 } 1118 #else 1119 for (i = 0; i < 16; i++) 1120 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 1121 #endif 1122 1123 kernel_pmap->pmap_phys = kernel_pmap; 1124 CPU_FILL(&kernel_pmap->pm_active); 1125 RB_INIT(&kernel_pmap->pmap_pvo); 1126 1127 PMAP_LOCK_INIT(kernel_pmap); 1128 1129 /* 1130 * Now map in all the other buffers we allocated earlier 1131 */ 1132 1133 moea64_setup_direct_map(kernelstart, kernelend); 1134 } 1135 1136 void 1137 moea64_late_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 1138 { 1139 ihandle_t mmui; 1140 phandle_t chosen; 1141 phandle_t mmu; 1142 ssize_t sz; 1143 int i; 1144 vm_offset_t pa, va; 1145 void *dpcpu; 1146 1147 /* 1148 * Set up the Open Firmware pmap and add its mappings if not in real 1149 * mode. 1150 */ 1151 1152 chosen = OF_finddevice("/chosen"); 1153 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 1154 mmu = OF_instance_to_package(mmui); 1155 if (mmu == -1 || 1156 (sz = OF_getproplen(mmu, "translations")) == -1) 1157 sz = 0; 1158 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1159 panic("moea64_bootstrap: too many ofw translations"); 1160 1161 if (sz > 0) 1162 moea64_add_ofw_mappings(mmu, sz); 1163 } 1164 1165 /* 1166 * Calculate the last available physical address. 1167 */ 1168 Maxmem = 0; 1169 for (i = 0; phys_avail[i + 1] != 0; i += 2) 1170 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 1171 1172 /* 1173 * Initialize MMU. 1174 */ 1175 pmap_cpu_bootstrap(0); 1176 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1177 pmap_bootstrapped++; 1178 1179 /* 1180 * Set the start and end of kva. 1181 */ 1182 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1183 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1184 1185 /* 1186 * Map the entire KVA range into the SLB. We must not fault there. 1187 */ 1188 #ifdef __powerpc64__ 1189 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1190 moea64_bootstrap_slb_prefault(va, 0); 1191 #endif 1192 1193 /* 1194 * Remap any early IO mappings (console framebuffer, etc.) 1195 */ 1196 bs_remap_earlyboot(); 1197 1198 /* 1199 * Figure out how far we can extend virtual_end into segment 16 1200 * without running into existing mappings. Segment 16 is guaranteed 1201 * to contain neither RAM nor devices (at least on Apple hardware), 1202 * but will generally contain some OFW mappings we should not 1203 * step on. 1204 */ 1205 1206 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1207 PMAP_LOCK(kernel_pmap); 1208 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1209 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1210 virtual_end += PAGE_SIZE; 1211 PMAP_UNLOCK(kernel_pmap); 1212 #endif 1213 1214 /* 1215 * Allocate a kernel stack with a guard page for thread0 and map it 1216 * into the kernel page map. 1217 */ 1218 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1219 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1220 virtual_avail = va + kstack_pages * PAGE_SIZE; 1221 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1222 thread0.td_kstack = va; 1223 thread0.td_kstack_pages = kstack_pages; 1224 for (i = 0; i < kstack_pages; i++) { 1225 moea64_kenter(va, pa); 1226 pa += PAGE_SIZE; 1227 va += PAGE_SIZE; 1228 } 1229 1230 /* 1231 * Allocate virtual address space for the message buffer. 1232 */ 1233 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1234 msgbufp = (struct msgbuf *)virtual_avail; 1235 va = virtual_avail; 1236 virtual_avail += round_page(msgbufsize); 1237 while (va < virtual_avail) { 1238 moea64_kenter(va, pa); 1239 pa += PAGE_SIZE; 1240 va += PAGE_SIZE; 1241 } 1242 1243 /* 1244 * Allocate virtual address space for the dynamic percpu area. 1245 */ 1246 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1247 dpcpu = (void *)virtual_avail; 1248 va = virtual_avail; 1249 virtual_avail += DPCPU_SIZE; 1250 while (va < virtual_avail) { 1251 moea64_kenter(va, pa); 1252 pa += PAGE_SIZE; 1253 va += PAGE_SIZE; 1254 } 1255 dpcpu_init(dpcpu, curcpu); 1256 1257 crashdumpmap = (caddr_t)virtual_avail; 1258 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1259 1260 /* 1261 * Allocate some things for page zeroing. We put this directly 1262 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1263 * of the PVO book-keeping or other parts of the VM system 1264 * from even knowing that this hack exists. 1265 */ 1266 1267 if (!hw_direct_map) { 1268 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1269 MTX_DEF); 1270 for (i = 0; i < 2; i++) { 1271 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1272 virtual_end -= PAGE_SIZE; 1273 1274 moea64_kenter(moea64_scratchpage_va[i], 0); 1275 1276 PMAP_LOCK(kernel_pmap); 1277 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1278 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1279 PMAP_UNLOCK(kernel_pmap); 1280 } 1281 } 1282 1283 numa_mem_regions(&numa_pregions, &numapregions_sz); 1284 } 1285 1286 static void 1287 moea64_pmap_init_qpages(void *dummy __unused) 1288 { 1289 struct pcpu *pc; 1290 int i; 1291 1292 if (hw_direct_map) 1293 return; 1294 1295 CPU_FOREACH(i) { 1296 pc = pcpu_find(i); 1297 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1298 if (pc->pc_qmap_addr == 0) 1299 panic("pmap_init_qpages: unable to allocate KVA"); 1300 PMAP_LOCK(kernel_pmap); 1301 pc->pc_aim.qmap_pvo = 1302 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1303 PMAP_UNLOCK(kernel_pmap); 1304 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1305 } 1306 } 1307 1308 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1309 1310 /* 1311 * Activate a user pmap. This mostly involves setting some non-CPU 1312 * state. 1313 */ 1314 void 1315 moea64_activate(struct thread *td) 1316 { 1317 pmap_t pm; 1318 1319 pm = &td->td_proc->p_vmspace->vm_pmap; 1320 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1321 1322 #ifdef __powerpc64__ 1323 PCPU_SET(aim.userslb, pm->pm_slb); 1324 __asm __volatile("slbmte %0, %1; isync" :: 1325 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1326 #else 1327 PCPU_SET(curpmap, pm->pmap_phys); 1328 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1329 #endif 1330 } 1331 1332 void 1333 moea64_deactivate(struct thread *td) 1334 { 1335 pmap_t pm; 1336 1337 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1338 1339 pm = &td->td_proc->p_vmspace->vm_pmap; 1340 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1341 #ifdef __powerpc64__ 1342 PCPU_SET(aim.userslb, NULL); 1343 #else 1344 PCPU_SET(curpmap, NULL); 1345 #endif 1346 } 1347 1348 void 1349 moea64_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1350 { 1351 struct pvo_entry key, *pvo; 1352 vm_page_t m; 1353 int64_t refchg; 1354 1355 key.pvo_vaddr = sva; 1356 PMAP_LOCK(pm); 1357 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1358 pvo != NULL && PVO_VADDR(pvo) < eva; 1359 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1360 if (PVO_IS_SP(pvo)) { 1361 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 1362 pvo = moea64_sp_unwire(pvo); 1363 continue; 1364 } else { 1365 CTR1(KTR_PMAP, "%s: demote before unwire", 1366 __func__); 1367 moea64_sp_demote(pvo); 1368 } 1369 } 1370 1371 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1372 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1373 pvo); 1374 pvo->pvo_vaddr &= ~PVO_WIRED; 1375 refchg = moea64_pte_replace(pvo, 0 /* No invalidation */); 1376 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1377 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1378 if (refchg < 0) 1379 refchg = LPTE_CHG; 1380 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1381 1382 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1383 if (refchg & LPTE_CHG) 1384 vm_page_dirty(m); 1385 if (refchg & LPTE_REF) 1386 vm_page_aflag_set(m, PGA_REFERENCED); 1387 } 1388 pm->pm_stats.wired_count--; 1389 } 1390 PMAP_UNLOCK(pm); 1391 } 1392 1393 static int 1394 moea64_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 1395 { 1396 struct pvo_entry *pvo; 1397 vm_paddr_t pa; 1398 vm_page_t m; 1399 int val; 1400 bool managed; 1401 1402 PMAP_LOCK(pmap); 1403 1404 pvo = moea64_pvo_find_va(pmap, addr); 1405 if (pvo != NULL) { 1406 pa = PVO_PADDR(pvo); 1407 m = PHYS_TO_VM_PAGE(pa); 1408 managed = (pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED; 1409 if (PVO_IS_SP(pvo)) 1410 val = MINCORE_INCORE | MINCORE_PSIND(1); 1411 else 1412 val = MINCORE_INCORE; 1413 } else { 1414 PMAP_UNLOCK(pmap); 1415 return (0); 1416 } 1417 1418 PMAP_UNLOCK(pmap); 1419 1420 if (m == NULL) 1421 return (0); 1422 1423 if (managed) { 1424 if (moea64_is_modified(m)) 1425 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 1426 1427 if (moea64_is_referenced(m)) 1428 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 1429 } 1430 1431 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 1432 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 1433 managed) { 1434 *pap = pa; 1435 } 1436 1437 return (val); 1438 } 1439 1440 /* 1441 * This goes through and sets the physical address of our 1442 * special scratch PTE to the PA we want to zero or copy. Because 1443 * of locking issues (this can get called in pvo_enter() by 1444 * the UMA allocator), we can't use most other utility functions here 1445 */ 1446 1447 static __inline 1448 void moea64_set_scratchpage_pa(int which, vm_paddr_t pa) 1449 { 1450 struct pvo_entry *pvo; 1451 1452 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1453 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1454 1455 pvo = moea64_scratchpage_pvo[which]; 1456 PMAP_LOCK(pvo->pvo_pmap); 1457 pvo->pvo_pte.pa = 1458 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1459 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1460 PMAP_UNLOCK(pvo->pvo_pmap); 1461 isync(); 1462 } 1463 1464 void 1465 moea64_copy_page(vm_page_t msrc, vm_page_t mdst) 1466 { 1467 mtx_lock(&moea64_scratchpage_mtx); 1468 1469 moea64_set_scratchpage_pa(0, VM_PAGE_TO_PHYS(msrc)); 1470 moea64_set_scratchpage_pa(1, VM_PAGE_TO_PHYS(mdst)); 1471 1472 bcopy((void *)moea64_scratchpage_va[0], 1473 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1474 1475 mtx_unlock(&moea64_scratchpage_mtx); 1476 } 1477 1478 void 1479 moea64_copy_page_dmap(vm_page_t msrc, vm_page_t mdst) 1480 { 1481 vm_offset_t dst; 1482 vm_offset_t src; 1483 1484 dst = VM_PAGE_TO_PHYS(mdst); 1485 src = VM_PAGE_TO_PHYS(msrc); 1486 1487 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1488 PAGE_SIZE); 1489 } 1490 1491 inline void 1492 moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 1493 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1494 { 1495 void *a_cp, *b_cp; 1496 vm_offset_t a_pg_offset, b_pg_offset; 1497 int cnt; 1498 1499 while (xfersize > 0) { 1500 a_pg_offset = a_offset & PAGE_MASK; 1501 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1502 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1503 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1504 a_pg_offset; 1505 b_pg_offset = b_offset & PAGE_MASK; 1506 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1507 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1508 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1509 b_pg_offset; 1510 bcopy(a_cp, b_cp, cnt); 1511 a_offset += cnt; 1512 b_offset += cnt; 1513 xfersize -= cnt; 1514 } 1515 } 1516 1517 void 1518 moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1519 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1520 { 1521 void *a_cp, *b_cp; 1522 vm_offset_t a_pg_offset, b_pg_offset; 1523 int cnt; 1524 1525 mtx_lock(&moea64_scratchpage_mtx); 1526 while (xfersize > 0) { 1527 a_pg_offset = a_offset & PAGE_MASK; 1528 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1529 moea64_set_scratchpage_pa(0, 1530 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1531 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1532 b_pg_offset = b_offset & PAGE_MASK; 1533 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1534 moea64_set_scratchpage_pa(1, 1535 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1536 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1537 bcopy(a_cp, b_cp, cnt); 1538 a_offset += cnt; 1539 b_offset += cnt; 1540 xfersize -= cnt; 1541 } 1542 mtx_unlock(&moea64_scratchpage_mtx); 1543 } 1544 1545 void 1546 moea64_zero_page_area(vm_page_t m, int off, int size) 1547 { 1548 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1549 1550 if (size + off > PAGE_SIZE) 1551 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1552 1553 if (hw_direct_map) { 1554 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1555 } else { 1556 mtx_lock(&moea64_scratchpage_mtx); 1557 moea64_set_scratchpage_pa(0, pa); 1558 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1559 mtx_unlock(&moea64_scratchpage_mtx); 1560 } 1561 } 1562 1563 /* 1564 * Zero a page of physical memory by temporarily mapping it 1565 */ 1566 void 1567 moea64_zero_page(vm_page_t m) 1568 { 1569 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1570 vm_offset_t va; 1571 1572 mtx_lock(&moea64_scratchpage_mtx); 1573 1574 moea64_set_scratchpage_pa(0, pa); 1575 va = moea64_scratchpage_va[0]; 1576 1577 bzero((void *)va, PAGE_SIZE); 1578 1579 mtx_unlock(&moea64_scratchpage_mtx); 1580 } 1581 1582 void 1583 moea64_zero_page_dmap(vm_page_t m) 1584 { 1585 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1586 vm_offset_t va; 1587 1588 va = PHYS_TO_DMAP(pa); 1589 bzero((void *)va, PAGE_SIZE); 1590 } 1591 1592 vm_offset_t 1593 moea64_quick_enter_page(vm_page_t m) 1594 { 1595 struct pvo_entry *pvo; 1596 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1597 1598 /* 1599 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1600 * a critical section and access the PCPU data like on i386. 1601 * Instead, pin the thread and grab the PCPU lock to prevent 1602 * a preempting thread from using the same PCPU data. 1603 */ 1604 sched_pin(); 1605 1606 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1607 pvo = PCPU_GET(aim.qmap_pvo); 1608 1609 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1610 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1611 (uint64_t)pa; 1612 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1613 isync(); 1614 1615 return (PCPU_GET(qmap_addr)); 1616 } 1617 1618 vm_offset_t 1619 moea64_quick_enter_page_dmap(vm_page_t m) 1620 { 1621 1622 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 1623 } 1624 1625 void 1626 moea64_quick_remove_page(vm_offset_t addr) 1627 { 1628 1629 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1630 KASSERT(PCPU_GET(qmap_addr) == addr, 1631 ("moea64_quick_remove_page: invalid address")); 1632 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1633 sched_unpin(); 1634 } 1635 1636 bool 1637 moea64_page_is_mapped(vm_page_t m) 1638 { 1639 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1640 } 1641 1642 /* 1643 * Map the given physical page at the specified virtual address in the 1644 * target pmap with the protection requested. If specified the page 1645 * will be wired down. 1646 */ 1647 1648 int 1649 moea64_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1650 vm_prot_t prot, u_int flags, int8_t psind) 1651 { 1652 struct pvo_entry *pvo, *oldpvo, *tpvo; 1653 struct pvo_head *pvo_head; 1654 uint64_t pte_lo; 1655 int error; 1656 vm_paddr_t pa; 1657 1658 if ((m->oflags & VPO_UNMANAGED) == 0) { 1659 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1660 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1661 else 1662 VM_OBJECT_ASSERT_LOCKED(m->object); 1663 } 1664 1665 if (psind > 0) 1666 return (moea64_sp_enter(pmap, va, m, prot, flags, psind)); 1667 1668 pvo = alloc_pvo_entry(0); 1669 if (pvo == NULL) 1670 return (KERN_RESOURCE_SHORTAGE); 1671 pvo->pvo_pmap = NULL; /* to be filled in later */ 1672 pvo->pvo_pte.prot = prot; 1673 1674 pa = VM_PAGE_TO_PHYS(m); 1675 pte_lo = moea64_calc_wimg(pa, pmap_page_get_memattr(m)); 1676 pvo->pvo_pte.pa = pa | pte_lo; 1677 1678 if ((flags & PMAP_ENTER_WIRED) != 0) 1679 pvo->pvo_vaddr |= PVO_WIRED; 1680 1681 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1682 pvo_head = NULL; 1683 } else { 1684 pvo_head = &m->md.mdpg_pvoh; 1685 pvo->pvo_vaddr |= PVO_MANAGED; 1686 } 1687 1688 PV_LOCK(pa); 1689 PMAP_LOCK(pmap); 1690 if (pvo->pvo_pmap == NULL) 1691 init_pvo_entry(pvo, pmap, va); 1692 1693 if (moea64_ps_enabled(pmap) && 1694 (tpvo = moea64_pvo_find_va(pmap, va & ~HPT_SP_MASK)) != NULL && 1695 PVO_IS_SP(tpvo)) { 1696 /* Demote SP before entering a regular page */ 1697 CTR2(KTR_PMAP, "%s: demote before enter: va=%#jx", 1698 __func__, (uintmax_t)va); 1699 moea64_sp_demote_aligned(tpvo); 1700 } 1701 1702 if (prot & VM_PROT_WRITE) 1703 if (pmap_bootstrapped && 1704 (m->oflags & VPO_UNMANAGED) == 0) 1705 vm_page_aflag_set(m, PGA_WRITEABLE); 1706 1707 error = moea64_pvo_enter(pvo, pvo_head, &oldpvo); 1708 if (error == EEXIST) { 1709 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1710 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1711 oldpvo->pvo_pte.prot == prot) { 1712 /* Identical mapping already exists */ 1713 error = 0; 1714 1715 /* If not in page table, reinsert it */ 1716 if (moea64_pte_synch(oldpvo) < 0) { 1717 STAT_MOEA64(moea64_pte_overflow--); 1718 moea64_pte_insert(oldpvo); 1719 } 1720 1721 /* Then just clean up and go home */ 1722 PMAP_UNLOCK(pmap); 1723 PV_UNLOCK(pa); 1724 free_pvo_entry(pvo); 1725 pvo = NULL; 1726 goto out; 1727 } else { 1728 /* Otherwise, need to kill it first */ 1729 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1730 "mapping does not match new mapping")); 1731 moea64_pvo_remove_from_pmap(oldpvo); 1732 moea64_pvo_enter(pvo, pvo_head, NULL); 1733 } 1734 } 1735 PMAP_UNLOCK(pmap); 1736 PV_UNLOCK(pa); 1737 1738 /* Free any dead pages */ 1739 if (error == EEXIST) { 1740 moea64_pvo_remove_from_page(oldpvo); 1741 free_pvo_entry(oldpvo); 1742 } 1743 1744 out: 1745 /* 1746 * Flush the page from the instruction cache if this page is 1747 * mapped executable and cacheable. 1748 */ 1749 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1750 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1751 vm_page_aflag_set(m, PGA_EXECUTABLE); 1752 moea64_syncicache(pmap, va, pa, PAGE_SIZE); 1753 } 1754 1755 #if VM_NRESERVLEVEL > 0 1756 /* 1757 * Try to promote pages. 1758 * 1759 * If the VA of the entered page is not aligned with its PA, 1760 * don't try page promotion as it is not possible. 1761 * This reduces the number of promotion failures dramatically. 1762 * 1763 * Ignore VM_PROT_NO_PROMOTE unless PMAP_ENTER_QUICK_LOCKED. 1764 */ 1765 if (moea64_ps_enabled(pmap) && pmap != kernel_pmap && pvo != NULL && 1766 (pvo->pvo_vaddr & PVO_MANAGED) != 0 && 1767 (va & HPT_SP_MASK) == (pa & HPT_SP_MASK) && 1768 ((prot & VM_PROT_NO_PROMOTE) == 0 || 1769 (flags & PMAP_ENTER_QUICK_LOCKED) == 0) && 1770 (m->flags & PG_FICTITIOUS) == 0 && 1771 vm_reserv_level_iffullpop(m) == 0) 1772 moea64_sp_promote(pmap, va, m); 1773 #endif 1774 1775 return (KERN_SUCCESS); 1776 } 1777 1778 static void 1779 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1780 vm_size_t sz) 1781 { 1782 1783 /* 1784 * This is much trickier than on older systems because 1785 * we can't sync the icache on physical addresses directly 1786 * without a direct map. Instead we check a couple of cases 1787 * where the memory is already mapped in and, failing that, 1788 * use the same trick we use for page zeroing to create 1789 * a temporary mapping for this physical address. 1790 */ 1791 1792 if (!pmap_bootstrapped) { 1793 /* 1794 * If PMAP is not bootstrapped, we are likely to be 1795 * in real mode. 1796 */ 1797 __syncicache((void *)(uintptr_t)pa, sz); 1798 } else if (pmap == kernel_pmap) { 1799 __syncicache((void *)va, sz); 1800 } else if (hw_direct_map) { 1801 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1802 } else { 1803 /* Use the scratch page to set up a temp mapping */ 1804 1805 mtx_lock(&moea64_scratchpage_mtx); 1806 1807 moea64_set_scratchpage_pa(1, pa & ~ADDR_POFF); 1808 __syncicache((void *)(moea64_scratchpage_va[1] + 1809 (va & ADDR_POFF)), sz); 1810 1811 mtx_unlock(&moea64_scratchpage_mtx); 1812 } 1813 } 1814 1815 /* 1816 * Maps a sequence of resident pages belonging to the same object. 1817 * The sequence begins with the given page m_start. This page is 1818 * mapped at the given virtual address start. Each subsequent page is 1819 * mapped at a virtual address that is offset from start by the same 1820 * amount as the page is offset from m_start within the object. The 1821 * last page in the sequence is the page with the largest offset from 1822 * m_start that can be mapped at a virtual address less than the given 1823 * virtual address end. Not every virtual page between start and end 1824 * is mapped; only those for which a resident page exists with the 1825 * corresponding offset from m_start are mapped. 1826 */ 1827 void 1828 moea64_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1829 vm_page_t m_start, vm_prot_t prot) 1830 { 1831 struct pctrie_iter pages; 1832 vm_page_t m; 1833 vm_offset_t va; 1834 int8_t psind; 1835 1836 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1837 1838 vm_page_iter_limit_init(&pages, m_start->object, 1839 m_start->pindex + atop(end - start)); 1840 m = vm_radix_iter_lookup(&pages, m_start->pindex); 1841 while (m != NULL) { 1842 va = start + ptoa(m->pindex - m_start->pindex); 1843 if ((va & HPT_SP_MASK) == 0 && va + HPT_SP_SIZE <= end && 1844 m->psind == 1 && moea64_ps_enabled(pm)) 1845 psind = 1; 1846 else 1847 psind = 0; 1848 moea64_enter(pm, va, m, prot & 1849 (VM_PROT_READ | VM_PROT_EXECUTE), 1850 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, psind); 1851 if (psind == 1) 1852 m = vm_radix_iter_jump(&pages, HPT_SP_SIZE / PAGE_SIZE); 1853 else 1854 m = vm_radix_iter_step(&pages); 1855 } 1856 } 1857 1858 void 1859 moea64_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1860 vm_prot_t prot) 1861 { 1862 1863 moea64_enter(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE | 1864 VM_PROT_NO_PROMOTE), PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 1865 0); 1866 } 1867 1868 vm_paddr_t 1869 moea64_extract(pmap_t pm, vm_offset_t va) 1870 { 1871 struct pvo_entry *pvo; 1872 vm_paddr_t pa; 1873 1874 PMAP_LOCK(pm); 1875 pvo = moea64_pvo_find_va(pm, va); 1876 if (pvo == NULL) 1877 pa = 0; 1878 else 1879 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 1880 PMAP_UNLOCK(pm); 1881 1882 return (pa); 1883 } 1884 1885 /* 1886 * Atomically extract and hold the physical page with the given 1887 * pmap and virtual address pair if that mapping permits the given 1888 * protection. 1889 */ 1890 vm_page_t 1891 moea64_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1892 { 1893 struct pvo_entry *pvo; 1894 vm_page_t m; 1895 1896 m = NULL; 1897 PMAP_LOCK(pmap); 1898 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1899 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1900 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1901 if (!vm_page_wire_mapped(m)) 1902 m = NULL; 1903 } 1904 PMAP_UNLOCK(pmap); 1905 return (m); 1906 } 1907 1908 static void * 1909 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1910 uint8_t *flags, int wait) 1911 { 1912 struct pvo_entry *pvo; 1913 vm_offset_t va; 1914 vm_page_t m; 1915 int needed_lock; 1916 1917 /* 1918 * This entire routine is a horrible hack to avoid bothering kmem 1919 * for new KVA addresses. Because this can get called from inside 1920 * kmem allocation routines, calling kmem for a new address here 1921 * can lead to multiply locking non-recursive mutexes. 1922 */ 1923 1924 *flags = UMA_SLAB_PRIV; 1925 needed_lock = !PMAP_LOCKED(kernel_pmap); 1926 1927 m = vm_page_alloc_noobj_domain(domain, malloc2vm_flags(wait) | 1928 VM_ALLOC_WIRED); 1929 if (m == NULL) 1930 return (NULL); 1931 1932 va = VM_PAGE_TO_PHYS(m); 1933 1934 pvo = alloc_pvo_entry(1 /* bootstrap */); 1935 1936 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1937 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1938 1939 if (needed_lock) 1940 PMAP_LOCK(kernel_pmap); 1941 1942 init_pvo_entry(pvo, kernel_pmap, va); 1943 pvo->pvo_vaddr |= PVO_WIRED; 1944 1945 moea64_pvo_enter(pvo, NULL, NULL); 1946 1947 if (needed_lock) 1948 PMAP_UNLOCK(kernel_pmap); 1949 1950 return (void *)va; 1951 } 1952 1953 extern int elf32_nxstack; 1954 1955 void 1956 moea64_init(void) 1957 { 1958 1959 CTR0(KTR_PMAP, "moea64_init"); 1960 1961 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1962 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1963 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1964 1965 /* 1966 * Are large page mappings enabled? 1967 * 1968 * While HPT superpages are not better tested, leave it disabled by 1969 * default. 1970 */ 1971 superpages_enabled = 0; 1972 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 1973 if (superpages_enabled) { 1974 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1975 ("moea64_init: can't assign to pagesizes[1]")); 1976 1977 if (moea64_large_page_size == 0) { 1978 printf("mmu_oea64: HW does not support large pages. " 1979 "Disabling superpages...\n"); 1980 superpages_enabled = 0; 1981 } else if (!moea64_has_lp_4k_16m) { 1982 printf("mmu_oea64: " 1983 "HW does not support mixed 4KB/16MB page sizes. " 1984 "Disabling superpages...\n"); 1985 superpages_enabled = 0; 1986 } else 1987 pagesizes[1] = HPT_SP_SIZE; 1988 } 1989 1990 if (!hw_direct_map) { 1991 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1992 } 1993 1994 #ifdef COMPAT_FREEBSD32 1995 elf32_nxstack = 1; 1996 #endif 1997 1998 moea64_initialized = true; 1999 } 2000 2001 bool 2002 moea64_is_referenced(vm_page_t m) 2003 { 2004 2005 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2006 ("moea64_is_referenced: page %p is not managed", m)); 2007 2008 return (moea64_query_bit(m, LPTE_REF)); 2009 } 2010 2011 bool 2012 moea64_is_modified(vm_page_t m) 2013 { 2014 2015 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2016 ("moea64_is_modified: page %p is not managed", m)); 2017 2018 /* 2019 * If the page is not busied then this check is racy. 2020 */ 2021 if (!pmap_page_is_write_mapped(m)) 2022 return (false); 2023 2024 return (moea64_query_bit(m, LPTE_CHG)); 2025 } 2026 2027 bool 2028 moea64_is_prefaultable(pmap_t pmap, vm_offset_t va) 2029 { 2030 struct pvo_entry *pvo; 2031 bool rv = true; 2032 2033 PMAP_LOCK(pmap); 2034 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 2035 if (pvo != NULL) 2036 rv = false; 2037 PMAP_UNLOCK(pmap); 2038 return (rv); 2039 } 2040 2041 void 2042 moea64_clear_modify(vm_page_t m) 2043 { 2044 2045 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2046 ("moea64_clear_modify: page %p is not managed", m)); 2047 vm_page_assert_busied(m); 2048 2049 if (!pmap_page_is_write_mapped(m)) 2050 return; 2051 moea64_clear_bit(m, LPTE_CHG); 2052 } 2053 2054 /* 2055 * Clear the write and modified bits in each of the given page's mappings. 2056 */ 2057 void 2058 moea64_remove_write(vm_page_t m) 2059 { 2060 struct pvo_entry *pvo; 2061 int64_t refchg, ret; 2062 pmap_t pmap; 2063 2064 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2065 ("moea64_remove_write: page %p is not managed", m)); 2066 vm_page_assert_busied(m); 2067 2068 if (!pmap_page_is_write_mapped(m)) 2069 return; 2070 2071 powerpc_sync(); 2072 PV_PAGE_LOCK(m); 2073 refchg = 0; 2074 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2075 pmap = pvo->pvo_pmap; 2076 PMAP_LOCK(pmap); 2077 if (!(pvo->pvo_vaddr & PVO_DEAD) && 2078 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2079 if (PVO_IS_SP(pvo)) { 2080 CTR1(KTR_PMAP, "%s: demote before remwr", 2081 __func__); 2082 moea64_sp_demote(pvo); 2083 } 2084 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 2085 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2086 if (ret < 0) 2087 ret = LPTE_CHG; 2088 refchg |= ret; 2089 if (pvo->pvo_pmap == kernel_pmap) 2090 isync(); 2091 } 2092 PMAP_UNLOCK(pmap); 2093 } 2094 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 2095 vm_page_dirty(m); 2096 vm_page_aflag_clear(m, PGA_WRITEABLE); 2097 PV_PAGE_UNLOCK(m); 2098 } 2099 2100 /* 2101 * moea64_ts_referenced: 2102 * 2103 * Return a count of reference bits for a page, clearing those bits. 2104 * It is not necessary for every reference bit to be cleared, but it 2105 * is necessary that 0 only be returned when there are truly no 2106 * reference bits set. 2107 * 2108 * XXX: The exact number of bits to check and clear is a matter that 2109 * should be tested and standardized at some point in the future for 2110 * optimal aging of shared pages. 2111 */ 2112 int 2113 moea64_ts_referenced(vm_page_t m) 2114 { 2115 2116 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2117 ("moea64_ts_referenced: page %p is not managed", m)); 2118 return (moea64_clear_bit(m, LPTE_REF)); 2119 } 2120 2121 /* 2122 * Modify the WIMG settings of all mappings for a page. 2123 */ 2124 void 2125 moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma) 2126 { 2127 struct pvo_entry *pvo; 2128 int64_t refchg; 2129 pmap_t pmap; 2130 uint64_t lo; 2131 2132 CTR3(KTR_PMAP, "%s: pa=%#jx, ma=%#x", 2133 __func__, (uintmax_t)VM_PAGE_TO_PHYS(m), ma); 2134 2135 if (m->md.mdpg_cache_attrs == ma) 2136 return; 2137 2138 if ((m->oflags & VPO_UNMANAGED) != 0) { 2139 m->md.mdpg_cache_attrs = ma; 2140 return; 2141 } 2142 2143 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 2144 2145 PV_PAGE_LOCK(m); 2146 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2147 pmap = pvo->pvo_pmap; 2148 PMAP_LOCK(pmap); 2149 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 2150 if (PVO_IS_SP(pvo)) { 2151 CTR1(KTR_PMAP, 2152 "%s: demote before set_memattr", __func__); 2153 moea64_sp_demote(pvo); 2154 } 2155 pvo->pvo_pte.pa &= ~LPTE_WIMG; 2156 pvo->pvo_pte.pa |= lo; 2157 refchg = moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 2158 if (refchg < 0) 2159 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 2160 LPTE_CHG : 0; 2161 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2162 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2163 refchg |= 2164 atomic_readandclear_32(&m->md.mdpg_attrs); 2165 if (refchg & LPTE_CHG) 2166 vm_page_dirty(m); 2167 if (refchg & LPTE_REF) 2168 vm_page_aflag_set(m, PGA_REFERENCED); 2169 } 2170 if (pvo->pvo_pmap == kernel_pmap) 2171 isync(); 2172 } 2173 PMAP_UNLOCK(pmap); 2174 } 2175 m->md.mdpg_cache_attrs = ma; 2176 PV_PAGE_UNLOCK(m); 2177 } 2178 2179 /* 2180 * Map a wired page into kernel virtual address space. 2181 */ 2182 void 2183 moea64_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 2184 { 2185 int error; 2186 struct pvo_entry *pvo, *oldpvo; 2187 2188 do { 2189 pvo = alloc_pvo_entry(0); 2190 if (pvo == NULL) 2191 vm_wait(NULL); 2192 } while (pvo == NULL); 2193 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 2194 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 2195 pvo->pvo_vaddr |= PVO_WIRED; 2196 2197 PMAP_LOCK(kernel_pmap); 2198 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 2199 if (oldpvo != NULL) 2200 moea64_pvo_remove_from_pmap(oldpvo); 2201 init_pvo_entry(pvo, kernel_pmap, va); 2202 error = moea64_pvo_enter(pvo, NULL, NULL); 2203 PMAP_UNLOCK(kernel_pmap); 2204 2205 /* Free any dead pages */ 2206 if (oldpvo != NULL) { 2207 moea64_pvo_remove_from_page(oldpvo); 2208 free_pvo_entry(oldpvo); 2209 } 2210 2211 if (error != 0) 2212 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 2213 (uintmax_t)pa, error); 2214 } 2215 2216 void 2217 moea64_kenter(vm_offset_t va, vm_paddr_t pa) 2218 { 2219 2220 moea64_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 2221 } 2222 2223 /* 2224 * Extract the physical page address associated with the given kernel virtual 2225 * address. 2226 */ 2227 vm_paddr_t 2228 moea64_kextract(vm_offset_t va) 2229 { 2230 struct pvo_entry *pvo; 2231 vm_paddr_t pa; 2232 2233 /* 2234 * Shortcut the direct-mapped case when applicable. We never put 2235 * anything but 1:1 (or 62-bit aliased) mappings below 2236 * VM_MIN_KERNEL_ADDRESS. 2237 */ 2238 if (va < VM_MIN_KERNEL_ADDRESS) 2239 return (va & ~DMAP_BASE_ADDRESS); 2240 2241 PMAP_LOCK(kernel_pmap); 2242 pvo = moea64_pvo_find_va(kernel_pmap, va); 2243 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 2244 va)); 2245 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 2246 PMAP_UNLOCK(kernel_pmap); 2247 return (pa); 2248 } 2249 2250 /* 2251 * Remove a wired page from kernel virtual address space. 2252 */ 2253 void 2254 moea64_kremove(vm_offset_t va) 2255 { 2256 moea64_remove(kernel_pmap, va, va + PAGE_SIZE); 2257 } 2258 2259 /* 2260 * Provide a kernel pointer corresponding to a given userland pointer. 2261 * The returned pointer is valid until the next time this function is 2262 * called in this thread. This is used internally in copyin/copyout. 2263 */ 2264 static int 2265 moea64_map_user_ptr(pmap_t pm, volatile const void *uaddr, 2266 void **kaddr, size_t ulen, size_t *klen) 2267 { 2268 size_t l; 2269 #ifdef __powerpc64__ 2270 struct slb *slb; 2271 #endif 2272 register_t slbv; 2273 2274 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 2275 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 2276 if (l > ulen) 2277 l = ulen; 2278 if (klen) 2279 *klen = l; 2280 else if (l != ulen) 2281 return (EFAULT); 2282 2283 #ifdef __powerpc64__ 2284 /* Try lockless look-up first */ 2285 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 2286 2287 if (slb == NULL) { 2288 /* If it isn't there, we need to pre-fault the VSID */ 2289 PMAP_LOCK(pm); 2290 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 2291 PMAP_UNLOCK(pm); 2292 } else { 2293 slbv = slb->slbv; 2294 } 2295 2296 /* Mark segment no-execute */ 2297 slbv |= SLBV_N; 2298 #else 2299 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 2300 2301 /* Mark segment no-execute */ 2302 slbv |= SR_N; 2303 #endif 2304 2305 /* If we have already set this VSID, we can just return */ 2306 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 2307 return (0); 2308 2309 __asm __volatile("isync"); 2310 curthread->td_pcb->pcb_cpu.aim.usr_segm = 2311 (uintptr_t)uaddr >> ADDR_SR_SHFT; 2312 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 2313 #ifdef __powerpc64__ 2314 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2315 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2316 #else 2317 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2318 #endif 2319 2320 return (0); 2321 } 2322 2323 /* 2324 * Figure out where a given kernel pointer (usually in a fault) points 2325 * to from the VM's perspective, potentially remapping into userland's 2326 * address space. 2327 */ 2328 static int 2329 moea64_decode_kernel_ptr(vm_offset_t addr, int *is_user, 2330 vm_offset_t *decoded_addr) 2331 { 2332 vm_offset_t user_sr; 2333 2334 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2335 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2336 addr &= ADDR_PIDX | ADDR_POFF; 2337 addr |= user_sr << ADDR_SR_SHFT; 2338 *decoded_addr = addr; 2339 *is_user = 1; 2340 } else { 2341 *decoded_addr = addr; 2342 *is_user = 0; 2343 } 2344 2345 return (0); 2346 } 2347 2348 /* 2349 * Map a range of physical addresses into kernel virtual address space. 2350 * 2351 * The value passed in *virt is a suggested virtual address for the mapping. 2352 * Architectures which can support a direct-mapped physical to virtual region 2353 * can return the appropriate address within that region, leaving '*virt' 2354 * unchanged. Other architectures should map the pages starting at '*virt' and 2355 * update '*virt' with the first usable address after the mapped region. 2356 */ 2357 vm_offset_t 2358 moea64_map(vm_offset_t *virt, vm_paddr_t pa_start, 2359 vm_paddr_t pa_end, int prot) 2360 { 2361 vm_offset_t sva, va; 2362 2363 if (hw_direct_map) { 2364 /* 2365 * Check if every page in the region is covered by the direct 2366 * map. The direct map covers all of physical memory. Use 2367 * moea64_calc_wimg() as a shortcut to see if the page is in 2368 * physical memory as a way to see if the direct map covers it. 2369 */ 2370 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2371 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2372 break; 2373 if (va == pa_end) 2374 return (PHYS_TO_DMAP(pa_start)); 2375 } 2376 sva = *virt; 2377 va = sva; 2378 /* XXX respect prot argument */ 2379 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2380 moea64_kenter(va, pa_start); 2381 *virt = va; 2382 2383 return (sva); 2384 } 2385 2386 /* 2387 * Returns true if the pmap's pv is one of the first 2388 * 16 pvs linked to from this page. This count may 2389 * be changed upwards or downwards in the future; it 2390 * is only necessary that true be returned for a small 2391 * subset of pmaps for proper page aging. 2392 */ 2393 bool 2394 moea64_page_exists_quick(pmap_t pmap, vm_page_t m) 2395 { 2396 int loops; 2397 struct pvo_entry *pvo; 2398 bool rv; 2399 2400 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2401 ("moea64_page_exists_quick: page %p is not managed", m)); 2402 loops = 0; 2403 rv = false; 2404 PV_PAGE_LOCK(m); 2405 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2406 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2407 rv = true; 2408 break; 2409 } 2410 if (++loops >= 16) 2411 break; 2412 } 2413 PV_PAGE_UNLOCK(m); 2414 return (rv); 2415 } 2416 2417 void 2418 moea64_page_init(vm_page_t m) 2419 { 2420 2421 m->md.mdpg_attrs = 0; 2422 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2423 LIST_INIT(&m->md.mdpg_pvoh); 2424 } 2425 2426 /* 2427 * Return the number of managed mappings to the given physical page 2428 * that are wired. 2429 */ 2430 int 2431 moea64_page_wired_mappings(vm_page_t m) 2432 { 2433 struct pvo_entry *pvo; 2434 int count; 2435 2436 count = 0; 2437 if ((m->oflags & VPO_UNMANAGED) != 0) 2438 return (count); 2439 PV_PAGE_LOCK(m); 2440 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2441 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2442 count++; 2443 PV_PAGE_UNLOCK(m); 2444 return (count); 2445 } 2446 2447 static uintptr_t moea64_vsidcontext; 2448 2449 uintptr_t 2450 moea64_get_unique_vsid(void) { 2451 u_int entropy; 2452 register_t hash; 2453 uint32_t mask; 2454 int i; 2455 2456 entropy = 0; 2457 __asm __volatile("mftb %0" : "=r"(entropy)); 2458 2459 mtx_lock(&moea64_slb_mutex); 2460 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2461 u_int n; 2462 2463 /* 2464 * Create a new value by multiplying by a prime and adding in 2465 * entropy from the timebase register. This is to make the 2466 * VSID more random so that the PT hash function collides 2467 * less often. (Note that the prime casues gcc to do shifts 2468 * instead of a multiply.) 2469 */ 2470 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2471 hash = moea64_vsidcontext & (NVSIDS - 1); 2472 if (hash == 0) /* 0 is special, avoid it */ 2473 continue; 2474 n = hash >> 5; 2475 mask = 1 << (hash & (VSID_NBPW - 1)); 2476 hash = (moea64_vsidcontext & VSID_HASHMASK); 2477 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2478 /* anything free in this bucket? */ 2479 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2480 entropy = (moea64_vsidcontext >> 20); 2481 continue; 2482 } 2483 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2484 mask = 1 << i; 2485 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2486 hash |= i; 2487 } 2488 if (hash == VSID_VRMA) /* also special, avoid this too */ 2489 continue; 2490 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2491 ("Allocating in-use VSID %#zx\n", hash)); 2492 moea64_vsid_bitmap[n] |= mask; 2493 mtx_unlock(&moea64_slb_mutex); 2494 return (hash); 2495 } 2496 2497 mtx_unlock(&moea64_slb_mutex); 2498 panic("%s: out of segments",__func__); 2499 } 2500 2501 #ifdef __powerpc64__ 2502 int 2503 moea64_pinit(pmap_t pmap) 2504 { 2505 2506 RB_INIT(&pmap->pmap_pvo); 2507 2508 pmap->pm_slb_tree_root = slb_alloc_tree(); 2509 pmap->pm_slb = slb_alloc_user_cache(); 2510 pmap->pm_slb_len = 0; 2511 2512 return (1); 2513 } 2514 #else 2515 int 2516 moea64_pinit(pmap_t pmap) 2517 { 2518 int i; 2519 uint32_t hash; 2520 2521 RB_INIT(&pmap->pmap_pvo); 2522 2523 if (pmap_bootstrapped) 2524 pmap->pmap_phys = (pmap_t)moea64_kextract((vm_offset_t)pmap); 2525 else 2526 pmap->pmap_phys = pmap; 2527 2528 /* 2529 * Allocate some segment registers for this pmap. 2530 */ 2531 hash = moea64_get_unique_vsid(); 2532 2533 for (i = 0; i < 16; i++) 2534 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2535 2536 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2537 2538 return (1); 2539 } 2540 #endif 2541 2542 /* 2543 * Initialize the pmap associated with process 0. 2544 */ 2545 void 2546 moea64_pinit0(pmap_t pm) 2547 { 2548 2549 PMAP_LOCK_INIT(pm); 2550 moea64_pinit(pm); 2551 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2552 } 2553 2554 /* 2555 * Set the physical protection on the specified range of this map as requested. 2556 */ 2557 static void 2558 moea64_pvo_protect( pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2559 { 2560 struct vm_page *pg; 2561 vm_prot_t oldprot; 2562 int32_t refchg; 2563 2564 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2565 2566 /* 2567 * Change the protection of the page. 2568 */ 2569 oldprot = pvo->pvo_pte.prot; 2570 pvo->pvo_pte.prot = prot; 2571 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2572 2573 /* 2574 * If the PVO is in the page table, update mapping 2575 */ 2576 refchg = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2577 if (refchg < 0) 2578 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2579 2580 if (pm != kernel_pmap && pg != NULL && 2581 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2582 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2583 if ((pg->oflags & VPO_UNMANAGED) == 0) 2584 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2585 moea64_syncicache(pm, PVO_VADDR(pvo), 2586 PVO_PADDR(pvo), PAGE_SIZE); 2587 } 2588 2589 /* 2590 * Update vm about the REF/CHG bits if the page is managed and we have 2591 * removed write access. 2592 */ 2593 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2594 (oldprot & VM_PROT_WRITE)) { 2595 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2596 if (refchg & LPTE_CHG) 2597 vm_page_dirty(pg); 2598 if (refchg & LPTE_REF) 2599 vm_page_aflag_set(pg, PGA_REFERENCED); 2600 } 2601 } 2602 2603 void 2604 moea64_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2605 vm_prot_t prot) 2606 { 2607 struct pvo_entry *pvo, key; 2608 2609 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2610 sva, eva, prot); 2611 2612 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2613 ("moea64_protect: non current pmap")); 2614 2615 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2616 moea64_remove(pm, sva, eva); 2617 return; 2618 } 2619 2620 PMAP_LOCK(pm); 2621 key.pvo_vaddr = sva; 2622 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2623 pvo != NULL && PVO_VADDR(pvo) < eva; 2624 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 2625 if (PVO_IS_SP(pvo)) { 2626 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 2627 pvo = moea64_sp_protect(pvo, prot); 2628 continue; 2629 } else { 2630 CTR1(KTR_PMAP, "%s: demote before protect", 2631 __func__); 2632 moea64_sp_demote(pvo); 2633 } 2634 } 2635 moea64_pvo_protect(pm, pvo, prot); 2636 } 2637 PMAP_UNLOCK(pm); 2638 } 2639 2640 /* 2641 * Map a list of wired pages into kernel virtual address space. This is 2642 * intended for temporary mappings which do not need page modification or 2643 * references recorded. Existing mappings in the region are overwritten. 2644 */ 2645 void 2646 moea64_qenter(vm_offset_t va, vm_page_t *m, int count) 2647 { 2648 while (count-- > 0) { 2649 moea64_kenter(va, VM_PAGE_TO_PHYS(*m)); 2650 va += PAGE_SIZE; 2651 m++; 2652 } 2653 } 2654 2655 /* 2656 * Remove page mappings from kernel virtual address space. Intended for 2657 * temporary mappings entered by moea64_qenter. 2658 */ 2659 void 2660 moea64_qremove(vm_offset_t va, int count) 2661 { 2662 while (count-- > 0) { 2663 moea64_kremove(va); 2664 va += PAGE_SIZE; 2665 } 2666 } 2667 2668 void 2669 moea64_release_vsid(uint64_t vsid) 2670 { 2671 int idx, mask; 2672 2673 mtx_lock(&moea64_slb_mutex); 2674 idx = vsid & (NVSIDS-1); 2675 mask = 1 << (idx % VSID_NBPW); 2676 idx /= VSID_NBPW; 2677 KASSERT(moea64_vsid_bitmap[idx] & mask, 2678 ("Freeing unallocated VSID %#jx", vsid)); 2679 moea64_vsid_bitmap[idx] &= ~mask; 2680 mtx_unlock(&moea64_slb_mutex); 2681 } 2682 2683 void 2684 moea64_release(pmap_t pmap) 2685 { 2686 2687 /* 2688 * Free segment registers' VSIDs 2689 */ 2690 #ifdef __powerpc64__ 2691 slb_free_tree(pmap); 2692 slb_free_user_cache(pmap->pm_slb); 2693 #else 2694 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2695 2696 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2697 #endif 2698 } 2699 2700 /* 2701 * Remove all pages mapped by the specified pmap 2702 */ 2703 void 2704 moea64_remove_pages(pmap_t pm) 2705 { 2706 struct pvo_entry *pvo, *tpvo; 2707 struct pvo_dlist tofree; 2708 2709 SLIST_INIT(&tofree); 2710 2711 PMAP_LOCK(pm); 2712 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2713 if (pvo->pvo_vaddr & PVO_WIRED) 2714 continue; 2715 2716 /* 2717 * For locking reasons, remove this from the page table and 2718 * pmap, but save delinking from the vm_page for a second 2719 * pass 2720 */ 2721 moea64_pvo_remove_from_pmap(pvo); 2722 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2723 } 2724 PMAP_UNLOCK(pm); 2725 2726 while (!SLIST_EMPTY(&tofree)) { 2727 pvo = SLIST_FIRST(&tofree); 2728 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2729 moea64_pvo_remove_from_page(pvo); 2730 free_pvo_entry(pvo); 2731 } 2732 } 2733 2734 static void 2735 moea64_remove_locked(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2736 struct pvo_dlist *tofree) 2737 { 2738 struct pvo_entry *pvo, *tpvo, key; 2739 2740 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2741 2742 key.pvo_vaddr = sva; 2743 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2744 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2745 if (PVO_IS_SP(pvo)) { 2746 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 2747 tpvo = moea64_sp_remove(pvo, tofree); 2748 continue; 2749 } else { 2750 CTR1(KTR_PMAP, "%s: demote before remove", 2751 __func__); 2752 moea64_sp_demote(pvo); 2753 } 2754 } 2755 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2756 2757 /* 2758 * For locking reasons, remove this from the page table and 2759 * pmap, but save delinking from the vm_page for a second 2760 * pass 2761 */ 2762 moea64_pvo_remove_from_pmap(pvo); 2763 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink); 2764 } 2765 } 2766 2767 /* 2768 * Remove the given range of addresses from the specified map. 2769 */ 2770 void 2771 moea64_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2772 { 2773 struct pvo_entry *pvo; 2774 struct pvo_dlist tofree; 2775 2776 /* 2777 * Perform an unsynchronized read. This is, however, safe. 2778 */ 2779 if (pm->pm_stats.resident_count == 0) 2780 return; 2781 2782 SLIST_INIT(&tofree); 2783 PMAP_LOCK(pm); 2784 moea64_remove_locked(pm, sva, eva, &tofree); 2785 PMAP_UNLOCK(pm); 2786 2787 while (!SLIST_EMPTY(&tofree)) { 2788 pvo = SLIST_FIRST(&tofree); 2789 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2790 moea64_pvo_remove_from_page(pvo); 2791 free_pvo_entry(pvo); 2792 } 2793 } 2794 2795 /* 2796 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2797 * will reflect changes in pte's back to the vm_page. 2798 */ 2799 void 2800 moea64_remove_all(vm_page_t m) 2801 { 2802 struct pvo_entry *pvo, *next_pvo; 2803 struct pvo_head freequeue; 2804 int wasdead; 2805 pmap_t pmap; 2806 2807 LIST_INIT(&freequeue); 2808 2809 PV_PAGE_LOCK(m); 2810 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2811 pmap = pvo->pvo_pmap; 2812 PMAP_LOCK(pmap); 2813 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2814 if (!wasdead) { 2815 if (PVO_IS_SP(pvo)) { 2816 CTR1(KTR_PMAP, "%s: demote before remove_all", 2817 __func__); 2818 moea64_sp_demote(pvo); 2819 } 2820 moea64_pvo_remove_from_pmap(pvo); 2821 } 2822 moea64_pvo_remove_from_page_locked(pvo, m); 2823 if (!wasdead) 2824 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2825 PMAP_UNLOCK(pmap); 2826 2827 } 2828 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2829 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2830 PV_PAGE_UNLOCK(m); 2831 2832 /* Clean up UMA allocations */ 2833 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2834 free_pvo_entry(pvo); 2835 } 2836 2837 /* 2838 * Allocate a physical page of memory directly from the phys_avail map. 2839 * Can only be called from moea64_bootstrap before avail start and end are 2840 * calculated. 2841 */ 2842 vm_offset_t 2843 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2844 { 2845 vm_offset_t s, e; 2846 int i, j; 2847 2848 size = round_page(size); 2849 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2850 if (align != 0) 2851 s = roundup2(phys_avail[i], align); 2852 else 2853 s = phys_avail[i]; 2854 e = s + size; 2855 2856 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2857 continue; 2858 2859 if (s + size > platform_real_maxaddr()) 2860 continue; 2861 2862 if (s == phys_avail[i]) { 2863 phys_avail[i] += size; 2864 } else if (e == phys_avail[i + 1]) { 2865 phys_avail[i + 1] -= size; 2866 } else { 2867 for (j = phys_avail_count * 2; j > i; j -= 2) { 2868 phys_avail[j] = phys_avail[j - 2]; 2869 phys_avail[j + 1] = phys_avail[j - 1]; 2870 } 2871 2872 phys_avail[i + 3] = phys_avail[i + 1]; 2873 phys_avail[i + 1] = s; 2874 phys_avail[i + 2] = e; 2875 phys_avail_count++; 2876 } 2877 2878 return (s); 2879 } 2880 panic("moea64_bootstrap_alloc: could not allocate memory"); 2881 } 2882 2883 static int 2884 moea64_pvo_enter(struct pvo_entry *pvo, struct pvo_head *pvo_head, 2885 struct pvo_entry **oldpvop) 2886 { 2887 struct pvo_entry *old_pvo; 2888 int err; 2889 2890 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2891 2892 STAT_MOEA64(moea64_pvo_enter_calls++); 2893 2894 /* 2895 * Add to pmap list 2896 */ 2897 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2898 2899 if (old_pvo != NULL) { 2900 if (oldpvop != NULL) 2901 *oldpvop = old_pvo; 2902 return (EEXIST); 2903 } 2904 2905 if (pvo_head != NULL) { 2906 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2907 } 2908 2909 if (pvo->pvo_vaddr & PVO_WIRED) 2910 pvo->pvo_pmap->pm_stats.wired_count++; 2911 pvo->pvo_pmap->pm_stats.resident_count++; 2912 2913 /* 2914 * Insert it into the hardware page table 2915 */ 2916 err = moea64_pte_insert(pvo); 2917 if (err != 0) { 2918 panic("moea64_pvo_enter: overflow"); 2919 } 2920 2921 STAT_MOEA64(moea64_pvo_entries++); 2922 2923 if (pvo->pvo_pmap == kernel_pmap) 2924 isync(); 2925 2926 #ifdef __powerpc64__ 2927 /* 2928 * Make sure all our bootstrap mappings are in the SLB as soon 2929 * as virtual memory is switched on. 2930 */ 2931 if (!pmap_bootstrapped) 2932 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2933 pvo->pvo_vaddr & PVO_LARGE); 2934 #endif 2935 2936 return (0); 2937 } 2938 2939 static void 2940 moea64_pvo_remove_from_pmap(struct pvo_entry *pvo) 2941 { 2942 struct vm_page *pg; 2943 int32_t refchg; 2944 2945 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2946 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2947 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2948 2949 /* 2950 * If there is an active pte entry, we need to deactivate it 2951 */ 2952 refchg = moea64_pte_unset(pvo); 2953 if (refchg < 0) { 2954 /* 2955 * If it was evicted from the page table, be pessimistic and 2956 * dirty the page. 2957 */ 2958 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2959 refchg = LPTE_CHG; 2960 else 2961 refchg = 0; 2962 } 2963 2964 /* 2965 * Update our statistics. 2966 */ 2967 pvo->pvo_pmap->pm_stats.resident_count--; 2968 if (pvo->pvo_vaddr & PVO_WIRED) 2969 pvo->pvo_pmap->pm_stats.wired_count--; 2970 2971 /* 2972 * Remove this PVO from the pmap list. 2973 */ 2974 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2975 2976 /* 2977 * Mark this for the next sweep 2978 */ 2979 pvo->pvo_vaddr |= PVO_DEAD; 2980 2981 /* Send RC bits to VM */ 2982 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2983 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2984 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2985 if (pg != NULL) { 2986 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2987 if (refchg & LPTE_CHG) 2988 vm_page_dirty(pg); 2989 if (refchg & LPTE_REF) 2990 vm_page_aflag_set(pg, PGA_REFERENCED); 2991 } 2992 } 2993 } 2994 2995 static inline void 2996 moea64_pvo_remove_from_page_locked(struct pvo_entry *pvo, 2997 vm_page_t m) 2998 { 2999 3000 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 3001 3002 /* Use NULL pmaps as a sentinel for races in page deletion */ 3003 if (pvo->pvo_pmap == NULL) 3004 return; 3005 pvo->pvo_pmap = NULL; 3006 3007 /* 3008 * Update vm about page writeability/executability if managed 3009 */ 3010 PV_LOCKASSERT(PVO_PADDR(pvo)); 3011 if (pvo->pvo_vaddr & PVO_MANAGED) { 3012 if (m != NULL) { 3013 LIST_REMOVE(pvo, pvo_vlink); 3014 if (LIST_EMPTY(vm_page_to_pvoh(m))) 3015 vm_page_aflag_clear(m, 3016 PGA_WRITEABLE | PGA_EXECUTABLE); 3017 } 3018 } 3019 3020 STAT_MOEA64(moea64_pvo_entries--); 3021 STAT_MOEA64(moea64_pvo_remove_calls++); 3022 } 3023 3024 static void 3025 moea64_pvo_remove_from_page(struct pvo_entry *pvo) 3026 { 3027 vm_page_t pg = NULL; 3028 3029 if (pvo->pvo_vaddr & PVO_MANAGED) 3030 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 3031 3032 PV_LOCK(PVO_PADDR(pvo)); 3033 moea64_pvo_remove_from_page_locked(pvo, pg); 3034 PV_UNLOCK(PVO_PADDR(pvo)); 3035 } 3036 3037 static struct pvo_entry * 3038 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 3039 { 3040 struct pvo_entry key; 3041 3042 PMAP_LOCK_ASSERT(pm, MA_OWNED); 3043 3044 key.pvo_vaddr = va & ~ADDR_POFF; 3045 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 3046 } 3047 3048 static bool 3049 moea64_query_bit(vm_page_t m, uint64_t ptebit) 3050 { 3051 struct pvo_entry *pvo; 3052 int64_t ret; 3053 bool rv; 3054 vm_page_t sp; 3055 3056 /* 3057 * See if this bit is stored in the page already. 3058 * 3059 * For superpages, the bit is stored in the first vm page. 3060 */ 3061 if ((m->md.mdpg_attrs & ptebit) != 0 || 3062 ((sp = PHYS_TO_VM_PAGE(VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK)) != NULL && 3063 (sp->md.mdpg_attrs & (ptebit | MDPG_ATTR_SP)) == 3064 (ptebit | MDPG_ATTR_SP))) 3065 return (true); 3066 3067 /* 3068 * Examine each PTE. Sync so that any pending REF/CHG bits are 3069 * flushed to the PTEs. 3070 */ 3071 rv = false; 3072 powerpc_sync(); 3073 PV_PAGE_LOCK(m); 3074 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 3075 if (PVO_IS_SP(pvo)) { 3076 ret = moea64_sp_query(pvo, ptebit); 3077 /* 3078 * If SP was not demoted, check its REF/CHG bits here. 3079 */ 3080 if (ret != -1) { 3081 if ((ret & ptebit) != 0) { 3082 rv = true; 3083 break; 3084 } 3085 continue; 3086 } 3087 /* else, fallthrough */ 3088 } 3089 3090 ret = 0; 3091 3092 /* 3093 * See if this pvo has a valid PTE. if so, fetch the 3094 * REF/CHG bits from the valid PTE. If the appropriate 3095 * ptebit is set, return success. 3096 */ 3097 PMAP_LOCK(pvo->pvo_pmap); 3098 if (!(pvo->pvo_vaddr & PVO_DEAD)) 3099 ret = moea64_pte_synch(pvo); 3100 PMAP_UNLOCK(pvo->pvo_pmap); 3101 3102 if (ret > 0) { 3103 atomic_set_32(&m->md.mdpg_attrs, 3104 ret & (LPTE_CHG | LPTE_REF)); 3105 if (ret & ptebit) { 3106 rv = true; 3107 break; 3108 } 3109 } 3110 } 3111 PV_PAGE_UNLOCK(m); 3112 3113 return (rv); 3114 } 3115 3116 static u_int 3117 moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 3118 { 3119 u_int count; 3120 struct pvo_entry *pvo; 3121 int64_t ret; 3122 3123 /* 3124 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 3125 * we can reset the right ones). 3126 */ 3127 powerpc_sync(); 3128 3129 /* 3130 * For each pvo entry, clear the pte's ptebit. 3131 */ 3132 count = 0; 3133 PV_PAGE_LOCK(m); 3134 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 3135 if (PVO_IS_SP(pvo)) { 3136 if ((ret = moea64_sp_clear(pvo, m, ptebit)) != -1) { 3137 count += ret; 3138 continue; 3139 } 3140 } 3141 ret = 0; 3142 3143 PMAP_LOCK(pvo->pvo_pmap); 3144 if (!(pvo->pvo_vaddr & PVO_DEAD)) 3145 ret = moea64_pte_clear(pvo, ptebit); 3146 PMAP_UNLOCK(pvo->pvo_pmap); 3147 3148 if (ret > 0 && (ret & ptebit)) 3149 count++; 3150 } 3151 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 3152 PV_PAGE_UNLOCK(m); 3153 3154 return (count); 3155 } 3156 3157 int 3158 moea64_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 3159 { 3160 struct pvo_entry *pvo, key; 3161 vm_offset_t ppa; 3162 int error = 0; 3163 3164 if (hw_direct_map && mem_valid(pa, size) == 0) 3165 return (0); 3166 3167 PMAP_LOCK(kernel_pmap); 3168 ppa = pa & ~ADDR_POFF; 3169 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 3170 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 3171 ppa < pa + size; ppa += PAGE_SIZE, 3172 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 3173 if (pvo == NULL || PVO_PADDR(pvo) != ppa) { 3174 error = EFAULT; 3175 break; 3176 } 3177 } 3178 PMAP_UNLOCK(kernel_pmap); 3179 3180 return (error); 3181 } 3182 3183 /* 3184 * Map a set of physical memory pages into the kernel virtual 3185 * address space. Return a pointer to where it is mapped. This 3186 * routine is intended to be used for mapping device memory, 3187 * NOT real memory. 3188 */ 3189 void * 3190 moea64_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 3191 { 3192 vm_offset_t va, tmpva, ppa, offset; 3193 3194 ppa = trunc_page(pa); 3195 offset = pa & PAGE_MASK; 3196 size = roundup2(offset + size, PAGE_SIZE); 3197 3198 va = kva_alloc(size); 3199 3200 if (!va) 3201 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 3202 3203 for (tmpva = va; size > 0;) { 3204 moea64_kenter_attr(tmpva, ppa, ma); 3205 size -= PAGE_SIZE; 3206 tmpva += PAGE_SIZE; 3207 ppa += PAGE_SIZE; 3208 } 3209 3210 return ((void *)(va + offset)); 3211 } 3212 3213 void * 3214 moea64_mapdev(vm_paddr_t pa, vm_size_t size) 3215 { 3216 3217 return moea64_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT); 3218 } 3219 3220 void 3221 moea64_unmapdev(void *p, vm_size_t size) 3222 { 3223 vm_offset_t base, offset, va; 3224 3225 va = (vm_offset_t)p; 3226 base = trunc_page(va); 3227 offset = va & PAGE_MASK; 3228 size = roundup2(offset + size, PAGE_SIZE); 3229 3230 moea64_qremove(base, atop(size)); 3231 kva_free(base, size); 3232 } 3233 3234 void 3235 moea64_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3236 { 3237 struct pvo_entry *pvo; 3238 vm_offset_t lim; 3239 vm_paddr_t pa; 3240 vm_size_t len; 3241 3242 if (__predict_false(pm == NULL)) 3243 pm = &curthread->td_proc->p_vmspace->vm_pmap; 3244 3245 PMAP_LOCK(pm); 3246 while (sz > 0) { 3247 lim = round_page(va+1); 3248 len = MIN(lim - va, sz); 3249 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 3250 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 3251 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 3252 moea64_syncicache(pm, va, pa, len); 3253 } 3254 va += len; 3255 sz -= len; 3256 } 3257 PMAP_UNLOCK(pm); 3258 } 3259 3260 void 3261 moea64_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 3262 { 3263 3264 *va = (void *)(uintptr_t)pa; 3265 } 3266 3267 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 3268 3269 void 3270 moea64_scan_init(void) 3271 { 3272 struct pvo_entry *pvo; 3273 vm_offset_t va; 3274 int i; 3275 3276 if (!do_minidump) { 3277 /* Initialize phys. segments for dumpsys(). */ 3278 memset(&dump_map, 0, sizeof(dump_map)); 3279 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 3280 for (i = 0; i < pregions_sz; i++) { 3281 dump_map[i].pa_start = pregions[i].mr_start; 3282 dump_map[i].pa_size = pregions[i].mr_size; 3283 } 3284 return; 3285 } 3286 3287 /* Virtual segments for minidumps: */ 3288 memset(&dump_map, 0, sizeof(dump_map)); 3289 3290 /* 1st: kernel .data and .bss. */ 3291 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 3292 dump_map[0].pa_size = round_page((uintptr_t)_end) - 3293 dump_map[0].pa_start; 3294 3295 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 3296 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 3297 dump_map[1].pa_size = round_page(msgbufp->msg_size); 3298 3299 /* 3rd: kernel VM. */ 3300 va = dump_map[1].pa_start + dump_map[1].pa_size; 3301 /* Find start of next chunk (from va). */ 3302 while (va < virtual_end) { 3303 /* Don't dump the buffer cache. */ 3304 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 3305 va = kmi.buffer_eva; 3306 continue; 3307 } 3308 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 3309 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 3310 break; 3311 va += PAGE_SIZE; 3312 } 3313 if (va < virtual_end) { 3314 dump_map[2].pa_start = va; 3315 va += PAGE_SIZE; 3316 /* Find last page in chunk. */ 3317 while (va < virtual_end) { 3318 /* Don't run into the buffer cache. */ 3319 if (va == kmi.buffer_sva) 3320 break; 3321 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 3322 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 3323 break; 3324 va += PAGE_SIZE; 3325 } 3326 dump_map[2].pa_size = va - dump_map[2].pa_start; 3327 } 3328 } 3329 3330 #ifdef __powerpc64__ 3331 3332 static size_t 3333 moea64_scan_pmap(struct bitset *dump_bitset) 3334 { 3335 struct pvo_entry *pvo; 3336 vm_paddr_t pa, pa_end; 3337 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 3338 uint64_t lpsize; 3339 3340 lpsize = moea64_large_page_size; 3341 kstart = trunc_page((vm_offset_t)_etext); 3342 kend = round_page((vm_offset_t)_end); 3343 kstart_lp = kstart & ~moea64_large_page_mask; 3344 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 3345 3346 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 3347 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 3348 kstart, kend, kstart_lp, kend_lp); 3349 3350 PMAP_LOCK(kernel_pmap); 3351 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 3352 va = pvo->pvo_vaddr; 3353 3354 if (va & PVO_DEAD) 3355 continue; 3356 3357 /* Skip DMAP (except kernel area) */ 3358 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 3359 if (va & PVO_LARGE) { 3360 pgva = va & ~moea64_large_page_mask; 3361 if (pgva < kstart_lp || pgva >= kend_lp) 3362 continue; 3363 } else { 3364 pgva = trunc_page(va); 3365 if (pgva < kstart || pgva >= kend) 3366 continue; 3367 } 3368 } 3369 3370 pa = PVO_PADDR(pvo); 3371 3372 if (va & PVO_LARGE) { 3373 pa_end = pa + lpsize; 3374 for (; pa < pa_end; pa += PAGE_SIZE) { 3375 if (vm_phys_is_dumpable(pa)) 3376 vm_page_dump_add(dump_bitset, pa); 3377 } 3378 } else { 3379 if (vm_phys_is_dumpable(pa)) 3380 vm_page_dump_add(dump_bitset, pa); 3381 } 3382 } 3383 PMAP_UNLOCK(kernel_pmap); 3384 3385 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3386 } 3387 3388 static struct dump_context dump_ctx; 3389 3390 static void * 3391 moea64_dump_pmap_init(unsigned blkpgs) 3392 { 3393 dump_ctx.ptex = 0; 3394 dump_ctx.ptex_end = moea64_pteg_count * 8; 3395 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3396 return (&dump_ctx); 3397 } 3398 3399 #else 3400 3401 static size_t 3402 moea64_scan_pmap(struct bitset *dump_bitset __unused) 3403 { 3404 return (0); 3405 } 3406 3407 static void * 3408 moea64_dump_pmap_init(unsigned blkpgs) 3409 { 3410 return (NULL); 3411 } 3412 3413 #endif 3414 3415 #ifdef __powerpc64__ 3416 static void 3417 moea64_map_range(vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3418 { 3419 3420 for (; npages > 0; --npages) { 3421 if (moea64_large_page_size != 0 && 3422 (pa & moea64_large_page_mask) == 0 && 3423 (va & moea64_large_page_mask) == 0 && 3424 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3425 PMAP_LOCK(kernel_pmap); 3426 moea64_kenter_large(va, pa, 0, 0); 3427 PMAP_UNLOCK(kernel_pmap); 3428 pa += moea64_large_page_size; 3429 va += moea64_large_page_size; 3430 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3431 } else { 3432 moea64_kenter(va, pa); 3433 pa += PAGE_SIZE; 3434 va += PAGE_SIZE; 3435 } 3436 } 3437 } 3438 3439 static void 3440 moea64_page_array_startup(long pages) 3441 { 3442 long dom_pages[MAXMEMDOM]; 3443 vm_paddr_t pa; 3444 vm_offset_t va, vm_page_base; 3445 vm_size_t needed, size; 3446 int domain; 3447 int i; 3448 3449 vm_page_base = 0xd000000000000000ULL; 3450 3451 /* Short-circuit single-domain systems. */ 3452 if (vm_ndomains == 1) { 3453 size = round_page(pages * sizeof(struct vm_page)); 3454 pa = vm_phys_early_alloc(0, size); 3455 vm_page_base = moea64_map(&vm_page_base, 3456 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3457 vm_page_array_size = pages; 3458 vm_page_array = (vm_page_t)vm_page_base; 3459 return; 3460 } 3461 3462 for (i = 0; i < MAXMEMDOM; i++) 3463 dom_pages[i] = 0; 3464 3465 /* Now get the number of pages required per domain. */ 3466 for (i = 0; i < vm_phys_nsegs; i++) { 3467 domain = vm_phys_segs[i].domain; 3468 KASSERT(domain < MAXMEMDOM, 3469 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3470 /* Get size of vm_page_array needed for this segment. */ 3471 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3472 dom_pages[domain] += size; 3473 } 3474 3475 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3476 domain = vm_phys_domain(phys_avail[i]); 3477 KASSERT(domain < MAXMEMDOM, 3478 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3479 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3480 dom_pages[domain] += size; 3481 } 3482 3483 /* 3484 * Map in chunks that can get us all 16MB pages. There will be some 3485 * overlap between domains, but that's acceptable for now. 3486 */ 3487 vm_page_array_size = 0; 3488 va = vm_page_base; 3489 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3490 if (dom_pages[i] == 0) 3491 continue; 3492 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3493 size = round_page(size * sizeof(struct vm_page)); 3494 needed = size; 3495 size = roundup2(size, moea64_large_page_size); 3496 pa = vm_phys_early_alloc(i, size); 3497 vm_page_array_size += size / sizeof(struct vm_page); 3498 moea64_map_range(va, pa, size >> PAGE_SHIFT); 3499 /* Scoot up domain 0, to reduce the domain page overlap. */ 3500 if (i == 0) 3501 vm_page_base += size - needed; 3502 va += size; 3503 } 3504 vm_page_array = (vm_page_t)vm_page_base; 3505 vm_page_array_size = pages; 3506 } 3507 #endif 3508 3509 static int64_t 3510 moea64_null_method(void) 3511 { 3512 return (0); 3513 } 3514 3515 static int64_t moea64_pte_replace_default(struct pvo_entry *pvo, int flags) 3516 { 3517 int64_t refchg; 3518 3519 refchg = moea64_pte_unset(pvo); 3520 moea64_pte_insert(pvo); 3521 3522 return (refchg); 3523 } 3524 3525 struct moea64_funcs *moea64_ops; 3526 3527 #define DEFINE_OEA64_IFUNC(ret, func, args, def) \ 3528 DEFINE_IFUNC(, ret, moea64_##func, args) { \ 3529 moea64_##func##_t f; \ 3530 if (moea64_ops == NULL) \ 3531 return ((moea64_##func##_t)def); \ 3532 f = moea64_ops->func; \ 3533 return (f != NULL ? f : (moea64_##func##_t)def);\ 3534 } 3535 3536 void 3537 moea64_install(void) 3538 { 3539 #ifdef __powerpc64__ 3540 if (hw_direct_map == -1) { 3541 moea64_probe_large_page(); 3542 3543 /* Use a direct map if we have large page support */ 3544 if (moea64_large_page_size > 0) 3545 hw_direct_map = 1; 3546 else 3547 hw_direct_map = 0; 3548 } 3549 #endif 3550 3551 /* 3552 * Default to non-DMAP, and switch over to DMAP functions once we know 3553 * we have DMAP. 3554 */ 3555 if (hw_direct_map) { 3556 moea64_methods.quick_enter_page = moea64_quick_enter_page_dmap; 3557 moea64_methods.quick_remove_page = NULL; 3558 moea64_methods.copy_page = moea64_copy_page_dmap; 3559 moea64_methods.zero_page = moea64_zero_page_dmap; 3560 moea64_methods.copy_pages = moea64_copy_pages_dmap; 3561 } 3562 } 3563 3564 DEFINE_OEA64_IFUNC(int64_t, pte_replace, (struct pvo_entry *, int), 3565 moea64_pte_replace_default) 3566 DEFINE_OEA64_IFUNC(int64_t, pte_insert, (struct pvo_entry *), moea64_null_method) 3567 DEFINE_OEA64_IFUNC(int64_t, pte_unset, (struct pvo_entry *), moea64_null_method) 3568 DEFINE_OEA64_IFUNC(int64_t, pte_clear, (struct pvo_entry *, uint64_t), 3569 moea64_null_method) 3570 DEFINE_OEA64_IFUNC(int64_t, pte_synch, (struct pvo_entry *), moea64_null_method) 3571 DEFINE_OEA64_IFUNC(int64_t, pte_insert_sp, (struct pvo_entry *), moea64_null_method) 3572 DEFINE_OEA64_IFUNC(int64_t, pte_unset_sp, (struct pvo_entry *), moea64_null_method) 3573 DEFINE_OEA64_IFUNC(int64_t, pte_replace_sp, (struct pvo_entry *), moea64_null_method) 3574 3575 /* Superpage functions */ 3576 3577 /* MMU interface */ 3578 3579 static bool 3580 moea64_ps_enabled(pmap_t pmap) 3581 { 3582 return (superpages_enabled); 3583 } 3584 3585 static void 3586 moea64_align_superpage(vm_object_t object, vm_ooffset_t offset, 3587 vm_offset_t *addr, vm_size_t size) 3588 { 3589 vm_offset_t sp_offset; 3590 3591 if (size < HPT_SP_SIZE) 3592 return; 3593 3594 CTR4(KTR_PMAP, "%s: offs=%#jx, addr=%p, size=%#jx", 3595 __func__, (uintmax_t)offset, addr, (uintmax_t)size); 3596 3597 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3598 offset += ptoa(object->pg_color); 3599 sp_offset = offset & HPT_SP_MASK; 3600 if (size - ((HPT_SP_SIZE - sp_offset) & HPT_SP_MASK) < HPT_SP_SIZE || 3601 (*addr & HPT_SP_MASK) == sp_offset) 3602 return; 3603 if ((*addr & HPT_SP_MASK) < sp_offset) 3604 *addr = (*addr & ~HPT_SP_MASK) + sp_offset; 3605 else 3606 *addr = ((*addr + HPT_SP_MASK) & ~HPT_SP_MASK) + sp_offset; 3607 } 3608 3609 /* Helpers */ 3610 3611 static __inline void 3612 moea64_pvo_cleanup(struct pvo_dlist *tofree) 3613 { 3614 struct pvo_entry *pvo; 3615 3616 /* clean up */ 3617 while (!SLIST_EMPTY(tofree)) { 3618 pvo = SLIST_FIRST(tofree); 3619 SLIST_REMOVE_HEAD(tofree, pvo_dlink); 3620 if (pvo->pvo_vaddr & PVO_DEAD) 3621 moea64_pvo_remove_from_page(pvo); 3622 free_pvo_entry(pvo); 3623 } 3624 } 3625 3626 static __inline uint16_t 3627 pvo_to_vmpage_flags(struct pvo_entry *pvo) 3628 { 3629 uint16_t flags; 3630 3631 flags = 0; 3632 if ((pvo->pvo_pte.prot & VM_PROT_WRITE) != 0) 3633 flags |= PGA_WRITEABLE; 3634 if ((pvo->pvo_pte.prot & VM_PROT_EXECUTE) != 0) 3635 flags |= PGA_EXECUTABLE; 3636 3637 return (flags); 3638 } 3639 3640 /* 3641 * Check if the given pvo and its superpage are in sva-eva range. 3642 */ 3643 static __inline bool 3644 moea64_sp_pvo_in_range(struct pvo_entry *pvo, vm_offset_t sva, vm_offset_t eva) 3645 { 3646 vm_offset_t spva; 3647 3648 spva = PVO_VADDR(pvo) & ~HPT_SP_MASK; 3649 if (spva >= sva && spva + HPT_SP_SIZE <= eva) { 3650 /* 3651 * Because this function is intended to be called from loops 3652 * that iterate over ordered pvo entries, if the condition 3653 * above is true then the pvo must be the first of its 3654 * superpage. 3655 */ 3656 KASSERT(PVO_VADDR(pvo) == spva, 3657 ("%s: unexpected unaligned superpage pvo", __func__)); 3658 return (true); 3659 } 3660 return (false); 3661 } 3662 3663 /* 3664 * Update vm about the REF/CHG bits if the superpage is managed and 3665 * has (or had) write access. 3666 */ 3667 static void 3668 moea64_sp_refchg_process(struct pvo_entry *sp, vm_page_t m, 3669 int64_t sp_refchg, vm_prot_t prot) 3670 { 3671 vm_page_t m_end; 3672 int64_t refchg; 3673 3674 if ((sp->pvo_vaddr & PVO_MANAGED) != 0 && (prot & VM_PROT_WRITE) != 0) { 3675 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) { 3676 refchg = sp_refchg | 3677 atomic_readandclear_32(&m->md.mdpg_attrs); 3678 if (refchg & LPTE_CHG) 3679 vm_page_dirty(m); 3680 if (refchg & LPTE_REF) 3681 vm_page_aflag_set(m, PGA_REFERENCED); 3682 } 3683 } 3684 } 3685 3686 /* Superpage ops */ 3687 3688 static int 3689 moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 3690 vm_prot_t prot, u_int flags, int8_t psind) 3691 { 3692 struct pvo_entry *pvo, **pvos; 3693 struct pvo_head *pvo_head; 3694 vm_offset_t sva; 3695 vm_page_t sm; 3696 vm_paddr_t pa, spa; 3697 bool sync; 3698 struct pvo_dlist tofree; 3699 int error __diagused, i; 3700 uint16_t aflags; 3701 3702 KASSERT((va & HPT_SP_MASK) == 0, ("%s: va %#jx unaligned", 3703 __func__, (uintmax_t)va)); 3704 KASSERT(psind == 1, ("%s: invalid psind: %d", __func__, psind)); 3705 KASSERT(m->psind == 1, ("%s: invalid m->psind: %d", 3706 __func__, m->psind)); 3707 KASSERT(pmap != kernel_pmap, 3708 ("%s: function called with kernel pmap", __func__)); 3709 3710 CTR5(KTR_PMAP, "%s: va=%#jx, pa=%#jx, prot=%#x, flags=%#x, psind=1", 3711 __func__, (uintmax_t)va, (uintmax_t)VM_PAGE_TO_PHYS(m), 3712 prot, flags); 3713 3714 SLIST_INIT(&tofree); 3715 3716 sva = va; 3717 sm = m; 3718 spa = pa = VM_PAGE_TO_PHYS(sm); 3719 3720 /* Try to allocate all PVOs first, to make failure handling easier. */ 3721 pvos = malloc(HPT_SP_PAGES * sizeof(struct pvo_entry *), M_TEMP, 3722 M_NOWAIT); 3723 if (pvos == NULL) { 3724 CTR1(KTR_PMAP, "%s: failed to alloc pvo array", __func__); 3725 return (KERN_RESOURCE_SHORTAGE); 3726 } 3727 3728 for (i = 0; i < HPT_SP_PAGES; i++) { 3729 pvos[i] = alloc_pvo_entry(0); 3730 if (pvos[i] == NULL) { 3731 CTR1(KTR_PMAP, "%s: failed to alloc pvo", __func__); 3732 for (i = i - 1; i >= 0; i--) 3733 free_pvo_entry(pvos[i]); 3734 free(pvos, M_TEMP); 3735 return (KERN_RESOURCE_SHORTAGE); 3736 } 3737 } 3738 3739 SP_PV_LOCK_ALIGNED(spa); 3740 PMAP_LOCK(pmap); 3741 3742 /* Note: moea64_remove_locked() also clears cached REF/CHG bits. */ 3743 moea64_remove_locked(pmap, va, va + HPT_SP_SIZE, &tofree); 3744 3745 /* Enter pages */ 3746 for (i = 0; i < HPT_SP_PAGES; 3747 i++, va += PAGE_SIZE, pa += PAGE_SIZE, m++) { 3748 pvo = pvos[i]; 3749 3750 pvo->pvo_pte.prot = prot; 3751 pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M | 3752 moea64_calc_wimg(pa, pmap_page_get_memattr(m)); 3753 3754 if ((flags & PMAP_ENTER_WIRED) != 0) 3755 pvo->pvo_vaddr |= PVO_WIRED; 3756 pvo->pvo_vaddr |= PVO_LARGE; 3757 3758 if ((m->oflags & VPO_UNMANAGED) != 0) 3759 pvo_head = NULL; 3760 else { 3761 pvo_head = &m->md.mdpg_pvoh; 3762 pvo->pvo_vaddr |= PVO_MANAGED; 3763 } 3764 3765 init_pvo_entry(pvo, pmap, va); 3766 3767 error = moea64_pvo_enter(pvo, pvo_head, NULL); 3768 /* 3769 * All superpage PVOs were previously removed, so no errors 3770 * should occur while inserting the new ones. 3771 */ 3772 KASSERT(error == 0, ("%s: unexpected error " 3773 "when inserting superpage PVO: %d", 3774 __func__, error)); 3775 } 3776 3777 PMAP_UNLOCK(pmap); 3778 SP_PV_UNLOCK_ALIGNED(spa); 3779 3780 sync = (sm->a.flags & PGA_EXECUTABLE) == 0; 3781 /* Note: moea64_pvo_cleanup() also clears page prot. flags. */ 3782 moea64_pvo_cleanup(&tofree); 3783 pvo = pvos[0]; 3784 3785 /* Set vm page flags */ 3786 aflags = pvo_to_vmpage_flags(pvo); 3787 if (aflags != 0) 3788 for (m = sm; m < &sm[HPT_SP_PAGES]; m++) 3789 vm_page_aflag_set(m, aflags); 3790 3791 /* 3792 * Flush the page from the instruction cache if this page is 3793 * mapped executable and cacheable. 3794 */ 3795 if (sync && (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) 3796 moea64_syncicache(pmap, sva, spa, HPT_SP_SIZE); 3797 3798 atomic_add_long(&sp_mappings, 1); 3799 CTR3(KTR_PMAP, "%s: SP success for va %#jx in pmap %p", 3800 __func__, (uintmax_t)sva, pmap); 3801 3802 free(pvos, M_TEMP); 3803 return (KERN_SUCCESS); 3804 } 3805 3806 #if VM_NRESERVLEVEL > 0 3807 static void 3808 moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m) 3809 { 3810 struct pvo_entry *first, *pvo; 3811 vm_paddr_t pa, pa_end; 3812 vm_offset_t sva, va_end; 3813 int64_t sp_refchg; 3814 3815 /* This CTR may generate a lot of output. */ 3816 /* CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)va); */ 3817 3818 va &= ~HPT_SP_MASK; 3819 sva = va; 3820 /* Get superpage */ 3821 pa = VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK; 3822 m = PHYS_TO_VM_PAGE(pa); 3823 3824 PMAP_LOCK(pmap); 3825 3826 /* 3827 * Check if all pages meet promotion criteria. 3828 * 3829 * XXX In some cases the loop below may be executed for each or most 3830 * of the entered pages of a superpage, which can be expensive 3831 * (although it was not profiled) and need some optimization. 3832 * 3833 * Some cases where this seems to happen are: 3834 * - When a superpage is first entered read-only and later becomes 3835 * read-write. 3836 * - When some of the superpage's virtual addresses map to previously 3837 * wired/cached pages while others map to pages allocated from a 3838 * different physical address range. A common scenario where this 3839 * happens is when mmap'ing a file that is already present in FS 3840 * block cache and doesn't fill a superpage. 3841 */ 3842 first = pvo = moea64_pvo_find_va(pmap, sva); 3843 for (pa_end = pa + HPT_SP_SIZE; 3844 pa < pa_end; pa += PAGE_SIZE, va += PAGE_SIZE) { 3845 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 3846 CTR3(KTR_PMAP, 3847 "%s: NULL or dead PVO: pmap=%p, va=%#jx", 3848 __func__, pmap, (uintmax_t)va); 3849 goto error; 3850 } 3851 if (PVO_PADDR(pvo) != pa) { 3852 CTR5(KTR_PMAP, "%s: PAs don't match: " 3853 "pmap=%p, va=%#jx, pvo_pa=%#jx, exp_pa=%#jx", 3854 __func__, pmap, (uintmax_t)va, 3855 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)pa); 3856 atomic_add_long(&sp_p_fail_pa, 1); 3857 goto error; 3858 } 3859 if ((first->pvo_vaddr & PVO_FLAGS_PROMOTE) != 3860 (pvo->pvo_vaddr & PVO_FLAGS_PROMOTE)) { 3861 CTR5(KTR_PMAP, "%s: PVO flags don't match: " 3862 "pmap=%p, va=%#jx, pvo_flags=%#jx, exp_flags=%#jx", 3863 __func__, pmap, (uintmax_t)va, 3864 (uintmax_t)(pvo->pvo_vaddr & PVO_FLAGS_PROMOTE), 3865 (uintmax_t)(first->pvo_vaddr & PVO_FLAGS_PROMOTE)); 3866 atomic_add_long(&sp_p_fail_flags, 1); 3867 goto error; 3868 } 3869 if (first->pvo_pte.prot != pvo->pvo_pte.prot) { 3870 CTR5(KTR_PMAP, "%s: PVO protections don't match: " 3871 "pmap=%p, va=%#jx, pvo_prot=%#x, exp_prot=%#x", 3872 __func__, pmap, (uintmax_t)va, 3873 pvo->pvo_pte.prot, first->pvo_pte.prot); 3874 atomic_add_long(&sp_p_fail_prot, 1); 3875 goto error; 3876 } 3877 if ((first->pvo_pte.pa & LPTE_WIMG) != 3878 (pvo->pvo_pte.pa & LPTE_WIMG)) { 3879 CTR5(KTR_PMAP, "%s: WIMG bits don't match: " 3880 "pmap=%p, va=%#jx, pvo_wimg=%#jx, exp_wimg=%#jx", 3881 __func__, pmap, (uintmax_t)va, 3882 (uintmax_t)(pvo->pvo_pte.pa & LPTE_WIMG), 3883 (uintmax_t)(first->pvo_pte.pa & LPTE_WIMG)); 3884 atomic_add_long(&sp_p_fail_wimg, 1); 3885 goto error; 3886 } 3887 3888 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo); 3889 } 3890 3891 /* All OK, promote. */ 3892 3893 /* 3894 * Handle superpage REF/CHG bits. If REF or CHG is set in 3895 * any page, then it must be set in the superpage. 3896 * 3897 * Instead of querying each page, we take advantage of two facts: 3898 * 1- If a page is being promoted, it was referenced. 3899 * 2- If promoted pages are writable, they were modified. 3900 */ 3901 sp_refchg = LPTE_REF | 3902 ((first->pvo_pte.prot & VM_PROT_WRITE) != 0 ? LPTE_CHG : 0); 3903 3904 /* Promote pages */ 3905 3906 for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE; 3907 pvo != NULL && PVO_VADDR(pvo) < va_end; 3908 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 3909 pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK; 3910 pvo->pvo_pte.pa |= LPTE_LP_4K_16M; 3911 pvo->pvo_vaddr |= PVO_LARGE; 3912 } 3913 moea64_pte_replace_sp(first); 3914 3915 /* Send REF/CHG bits to VM */ 3916 moea64_sp_refchg_process(first, m, sp_refchg, first->pvo_pte.prot); 3917 3918 /* Use first page to cache REF/CHG bits */ 3919 atomic_set_32(&m->md.mdpg_attrs, sp_refchg | MDPG_ATTR_SP); 3920 3921 PMAP_UNLOCK(pmap); 3922 3923 atomic_add_long(&sp_mappings, 1); 3924 atomic_add_long(&sp_promotions, 1); 3925 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p", 3926 __func__, (uintmax_t)sva, pmap); 3927 return; 3928 3929 error: 3930 atomic_add_long(&sp_p_failures, 1); 3931 PMAP_UNLOCK(pmap); 3932 } 3933 #endif 3934 3935 static void 3936 moea64_sp_demote_aligned(struct pvo_entry *sp) 3937 { 3938 struct pvo_entry *pvo; 3939 vm_offset_t va, va_end; 3940 vm_paddr_t pa; 3941 vm_page_t m; 3942 pmap_t pmap __diagused; 3943 int64_t refchg; 3944 3945 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 3946 3947 pmap = sp->pvo_pmap; 3948 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3949 3950 pvo = sp; 3951 3952 /* Demote pages */ 3953 3954 va = PVO_VADDR(pvo); 3955 pa = PVO_PADDR(pvo); 3956 m = PHYS_TO_VM_PAGE(pa); 3957 3958 for (pvo = sp, va_end = va + HPT_SP_SIZE; 3959 pvo != NULL && PVO_VADDR(pvo) < va_end; 3960 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo), 3961 va += PAGE_SIZE, pa += PAGE_SIZE) { 3962 KASSERT(pvo && PVO_VADDR(pvo) == va, 3963 ("%s: missing PVO for va %#jx", __func__, (uintmax_t)va)); 3964 3965 pvo->pvo_vaddr &= ~PVO_LARGE; 3966 pvo->pvo_pte.pa &= ~LPTE_RPGN; 3967 pvo->pvo_pte.pa |= pa; 3968 3969 } 3970 refchg = moea64_pte_replace_sp(sp); 3971 3972 /* 3973 * Clear SP flag 3974 * 3975 * XXX It is possible that another pmap has this page mapped as 3976 * part of a superpage, but as the SP flag is used only for 3977 * caching SP REF/CHG bits, that will be queried if not set 3978 * in cache, it should be ok to clear it here. 3979 */ 3980 atomic_clear_32(&m->md.mdpg_attrs, MDPG_ATTR_SP); 3981 3982 /* 3983 * Handle superpage REF/CHG bits. A bit set in the superpage 3984 * means all pages should consider it set. 3985 */ 3986 moea64_sp_refchg_process(sp, m, refchg, sp->pvo_pte.prot); 3987 3988 atomic_add_long(&sp_demotions, 1); 3989 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p", 3990 __func__, (uintmax_t)PVO_VADDR(sp), pmap); 3991 } 3992 3993 static void 3994 moea64_sp_demote(struct pvo_entry *pvo) 3995 { 3996 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 3997 3998 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 3999 pvo = moea64_pvo_find_va(pvo->pvo_pmap, 4000 PVO_VADDR(pvo) & ~HPT_SP_MASK); 4001 KASSERT(pvo != NULL, ("%s: missing PVO for va %#jx", 4002 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4003 } 4004 moea64_sp_demote_aligned(pvo); 4005 } 4006 4007 static struct pvo_entry * 4008 moea64_sp_unwire(struct pvo_entry *sp) 4009 { 4010 struct pvo_entry *pvo, *prev; 4011 vm_offset_t eva; 4012 pmap_t pm; 4013 int64_t ret, refchg; 4014 4015 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 4016 4017 pm = sp->pvo_pmap; 4018 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4019 4020 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4021 refchg = 0; 4022 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4023 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 4024 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 4025 panic("%s: pvo %p is missing PVO_WIRED", 4026 __func__, pvo); 4027 pvo->pvo_vaddr &= ~PVO_WIRED; 4028 4029 ret = moea64_pte_replace(pvo, 0 /* No invalidation */); 4030 if (ret < 0) 4031 refchg |= LPTE_CHG; 4032 else 4033 refchg |= ret; 4034 4035 pm->pm_stats.wired_count--; 4036 } 4037 4038 /* Send REF/CHG bits to VM */ 4039 moea64_sp_refchg_process(sp, PHYS_TO_VM_PAGE(PVO_PADDR(sp)), 4040 refchg, sp->pvo_pte.prot); 4041 4042 return (prev); 4043 } 4044 4045 static struct pvo_entry * 4046 moea64_sp_protect(struct pvo_entry *sp, vm_prot_t prot) 4047 { 4048 struct pvo_entry *pvo, *prev; 4049 vm_offset_t eva; 4050 pmap_t pm; 4051 vm_page_t m, m_end; 4052 int64_t ret, refchg; 4053 vm_prot_t oldprot; 4054 4055 CTR3(KTR_PMAP, "%s: va=%#jx, prot=%x", 4056 __func__, (uintmax_t)PVO_VADDR(sp), prot); 4057 4058 pm = sp->pvo_pmap; 4059 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4060 4061 oldprot = sp->pvo_pte.prot; 4062 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4063 KASSERT(m != NULL, ("%s: missing vm page for pa %#jx", 4064 __func__, (uintmax_t)PVO_PADDR(sp))); 4065 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4066 refchg = 0; 4067 4068 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4069 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 4070 pvo->pvo_pte.prot = prot; 4071 /* 4072 * If the PVO is in the page table, update mapping 4073 */ 4074 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 4075 if (ret < 0) 4076 refchg |= LPTE_CHG; 4077 else 4078 refchg |= ret; 4079 } 4080 4081 /* Send REF/CHG bits to VM */ 4082 moea64_sp_refchg_process(sp, m, refchg, oldprot); 4083 4084 /* Handle pages that became executable */ 4085 if ((m->a.flags & PGA_EXECUTABLE) == 0 && 4086 (sp->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 4087 if ((m->oflags & VPO_UNMANAGED) == 0) 4088 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) 4089 vm_page_aflag_set(m, PGA_EXECUTABLE); 4090 moea64_syncicache(pm, PVO_VADDR(sp), PVO_PADDR(sp), 4091 HPT_SP_SIZE); 4092 } 4093 4094 return (prev); 4095 } 4096 4097 static struct pvo_entry * 4098 moea64_sp_remove(struct pvo_entry *sp, struct pvo_dlist *tofree) 4099 { 4100 struct pvo_entry *pvo, *tpvo; 4101 vm_offset_t eva; 4102 pmap_t pm __diagused; 4103 4104 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 4105 4106 pm = sp->pvo_pmap; 4107 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4108 4109 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4110 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 4111 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 4112 4113 /* 4114 * For locking reasons, remove this from the page table and 4115 * pmap, but save delinking from the vm_page for a second 4116 * pass 4117 */ 4118 moea64_pvo_remove_from_pmap(pvo); 4119 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink); 4120 } 4121 4122 /* 4123 * Clear SP bit 4124 * 4125 * XXX See comment in moea64_sp_demote_aligned() for why it's 4126 * ok to always clear the SP bit on remove/demote. 4127 */ 4128 atomic_clear_32(&PHYS_TO_VM_PAGE(PVO_PADDR(sp))->md.mdpg_attrs, 4129 MDPG_ATTR_SP); 4130 4131 return (tpvo); 4132 } 4133 4134 static int64_t 4135 moea64_sp_query_locked(struct pvo_entry *pvo, uint64_t ptebit) 4136 { 4137 int64_t refchg, ret; 4138 vm_offset_t eva; 4139 vm_page_t m; 4140 pmap_t pmap; 4141 struct pvo_entry *sp; 4142 4143 pmap = pvo->pvo_pmap; 4144 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4145 4146 /* Get first SP PVO */ 4147 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 4148 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK); 4149 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx", 4150 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4151 } else 4152 sp = pvo; 4153 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4154 4155 refchg = 0; 4156 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4157 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 4158 ret = moea64_pte_synch(pvo); 4159 if (ret > 0) { 4160 refchg |= ret & (LPTE_CHG | LPTE_REF); 4161 if ((refchg & ptebit) != 0) 4162 break; 4163 } 4164 } 4165 4166 /* Save results */ 4167 if (refchg != 0) { 4168 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4169 atomic_set_32(&m->md.mdpg_attrs, refchg | MDPG_ATTR_SP); 4170 } 4171 4172 return (refchg); 4173 } 4174 4175 static int64_t 4176 moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit) 4177 { 4178 int64_t refchg; 4179 pmap_t pmap; 4180 4181 pmap = pvo->pvo_pmap; 4182 PMAP_LOCK(pmap); 4183 4184 /* 4185 * Check if SP was demoted/removed before pmap lock was acquired. 4186 */ 4187 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4188 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4189 __func__, (uintmax_t)PVO_PADDR(pvo)); 4190 PMAP_UNLOCK(pmap); 4191 return (-1); 4192 } 4193 4194 refchg = moea64_sp_query_locked(pvo, ptebit); 4195 PMAP_UNLOCK(pmap); 4196 4197 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx", 4198 __func__, (uintmax_t)PVO_VADDR(pvo), 4199 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)refchg); 4200 4201 return (refchg); 4202 } 4203 4204 static int64_t 4205 moea64_sp_pvo_clear(struct pvo_entry *pvo, uint64_t ptebit) 4206 { 4207 int64_t refchg, ret; 4208 pmap_t pmap; 4209 struct pvo_entry *sp; 4210 vm_offset_t eva; 4211 vm_page_t m; 4212 4213 pmap = pvo->pvo_pmap; 4214 PMAP_LOCK(pmap); 4215 4216 /* 4217 * Check if SP was demoted/removed before pmap lock was acquired. 4218 */ 4219 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4220 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4221 __func__, (uintmax_t)PVO_PADDR(pvo)); 4222 PMAP_UNLOCK(pmap); 4223 return (-1); 4224 } 4225 4226 /* Get first SP PVO */ 4227 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 4228 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK); 4229 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx", 4230 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4231 } else 4232 sp = pvo; 4233 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4234 4235 refchg = 0; 4236 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4237 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 4238 ret = moea64_pte_clear(pvo, ptebit); 4239 if (ret > 0) 4240 refchg |= ret & (LPTE_CHG | LPTE_REF); 4241 } 4242 4243 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4244 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 4245 PMAP_UNLOCK(pmap); 4246 4247 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx", 4248 __func__, (uintmax_t)PVO_VADDR(sp), 4249 (uintmax_t)PVO_PADDR(sp), (uintmax_t)refchg); 4250 4251 return (refchg); 4252 } 4253 4254 static int64_t 4255 moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, uint64_t ptebit) 4256 { 4257 int64_t count, ret; 4258 pmap_t pmap; 4259 4260 count = 0; 4261 pmap = pvo->pvo_pmap; 4262 4263 /* 4264 * Since this reference bit is shared by 4096 4KB pages, it 4265 * should not be cleared every time it is tested. Apply a 4266 * simple "hash" function on the physical page number, the 4267 * virtual superpage number, and the pmap address to select 4268 * one 4KB page out of the 4096 on which testing the 4269 * reference bit will result in clearing that reference bit. 4270 * This function is designed to avoid the selection of the 4271 * same 4KB page for every 16MB page mapping. 4272 * 4273 * Always leave the reference bit of a wired mapping set, as 4274 * the current state of its reference bit won't affect page 4275 * replacement. 4276 */ 4277 if (ptebit == LPTE_REF && (((VM_PAGE_TO_PHYS(m) >> PAGE_SHIFT) ^ 4278 (PVO_VADDR(pvo) >> HPT_SP_SHIFT) ^ (uintptr_t)pmap) & 4279 (HPT_SP_PAGES - 1)) == 0 && (pvo->pvo_vaddr & PVO_WIRED) == 0) { 4280 if ((ret = moea64_sp_pvo_clear(pvo, ptebit)) == -1) 4281 return (-1); 4282 4283 if ((ret & ptebit) != 0) 4284 count++; 4285 4286 /* 4287 * If this page was not selected by the hash function, then assume 4288 * its REF bit was set. 4289 */ 4290 } else if (ptebit == LPTE_REF) { 4291 count++; 4292 4293 /* 4294 * To clear the CHG bit of a single SP page, first it must be demoted. 4295 * But if no CHG bit is set, no bit clear and thus no SP demotion is 4296 * needed. 4297 */ 4298 } else { 4299 CTR4(KTR_PMAP, "%s: ptebit=%#jx, va=%#jx, pa=%#jx", 4300 __func__, (uintmax_t)ptebit, (uintmax_t)PVO_VADDR(pvo), 4301 (uintmax_t)PVO_PADDR(pvo)); 4302 4303 PMAP_LOCK(pmap); 4304 4305 /* 4306 * Make sure SP wasn't demoted/removed before pmap lock 4307 * was acquired. 4308 */ 4309 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4310 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4311 __func__, (uintmax_t)PVO_PADDR(pvo)); 4312 PMAP_UNLOCK(pmap); 4313 return (-1); 4314 } 4315 4316 ret = moea64_sp_query_locked(pvo, ptebit); 4317 if ((ret & ptebit) != 0) 4318 count++; 4319 else { 4320 PMAP_UNLOCK(pmap); 4321 return (0); 4322 } 4323 4324 moea64_sp_demote(pvo); 4325 moea64_pte_clear(pvo, ptebit); 4326 4327 /* 4328 * Write protect the mapping to a single page so that a 4329 * subsequent write access may repromote. 4330 */ 4331 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 4332 moea64_pvo_protect(pmap, pvo, 4333 pvo->pvo_pte.prot & ~VM_PROT_WRITE); 4334 4335 PMAP_UNLOCK(pmap); 4336 } 4337 4338 return (count); 4339 } 4340