1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_phys.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_PER_DOM (PA_LOCK_COUNT * 3) 123 #define PV_LOCK_COUNT (PV_LOCK_PER_DOM * MAXMEMDOM) 124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 125 126 /* 127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 129 * index at (N << 45). 130 */ 131 #ifdef __powerpc64__ 132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 134 #else 135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 136 #endif 137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 144 145 struct ofw_map { 146 cell_t om_va; 147 cell_t om_len; 148 uint64_t om_pa; 149 cell_t om_mode; 150 }; 151 152 extern unsigned char _etext[]; 153 extern unsigned char _end[]; 154 155 extern void *slbtrap, *slbtrapend; 156 157 /* 158 * Map of physical memory regions. 159 */ 160 static struct mem_region *regions; 161 static struct mem_region *pregions; 162 static struct numa_mem_region *numa_pregions; 163 static u_int phys_avail_count; 164 static int regions_sz, pregions_sz, numapregions_sz; 165 166 extern void bs_remap_earlyboot(void); 167 168 /* 169 * Lock for the SLB tables. 170 */ 171 struct mtx moea64_slb_mutex; 172 173 /* 174 * PTEG data. 175 */ 176 u_long moea64_pteg_count; 177 u_long moea64_pteg_mask; 178 179 /* 180 * PVO data. 181 */ 182 183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 184 185 static struct pvo_entry *moea64_bpvo_pool; 186 static int moea64_bpvo_pool_index = 0; 187 static int moea64_bpvo_pool_size = 327680; 188 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 190 &moea64_bpvo_pool_index, 0, ""); 191 192 #define VSID_NBPW (sizeof(u_int32_t) * 8) 193 #ifdef __powerpc64__ 194 #define NVSIDS (NPMAPS * 16) 195 #define VSID_HASHMASK 0xffffffffUL 196 #else 197 #define NVSIDS NPMAPS 198 #define VSID_HASHMASK 0xfffffUL 199 #endif 200 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 201 202 static boolean_t moea64_initialized = FALSE; 203 204 #ifdef MOEA64_STATS 205 /* 206 * Statistics. 207 */ 208 u_int moea64_pte_valid = 0; 209 u_int moea64_pte_overflow = 0; 210 u_int moea64_pvo_entries = 0; 211 u_int moea64_pvo_enter_calls = 0; 212 u_int moea64_pvo_remove_calls = 0; 213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 214 &moea64_pte_valid, 0, ""); 215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 216 &moea64_pte_overflow, 0, ""); 217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 218 &moea64_pvo_entries, 0, ""); 219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 220 &moea64_pvo_enter_calls, 0, ""); 221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 222 &moea64_pvo_remove_calls, 0, ""); 223 #endif 224 225 vm_offset_t moea64_scratchpage_va[2]; 226 struct pvo_entry *moea64_scratchpage_pvo[2]; 227 struct mtx moea64_scratchpage_mtx; 228 229 uint64_t moea64_large_page_mask = 0; 230 uint64_t moea64_large_page_size = 0; 231 int moea64_large_page_shift = 0; 232 233 /* 234 * PVO calls. 235 */ 236 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 237 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 238 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 240 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 241 struct pvo_entry *pvo, vm_page_t m); 242 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 243 244 /* 245 * Utility routines. 246 */ 247 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 248 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 249 static void moea64_kremove(mmu_t, vm_offset_t); 250 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 251 vm_paddr_t pa, vm_size_t sz); 252 static void moea64_pmap_init_qpages(void); 253 254 /* 255 * Kernel MMU interface 256 */ 257 void moea64_clear_modify(mmu_t, vm_page_t); 258 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 259 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 260 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 261 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 262 u_int flags, int8_t psind); 263 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 264 vm_prot_t); 265 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 266 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 267 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 268 void moea64_init(mmu_t); 269 boolean_t moea64_is_modified(mmu_t, vm_page_t); 270 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 271 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 272 int moea64_ts_referenced(mmu_t, vm_page_t); 273 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 274 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 275 void moea64_page_init(mmu_t, vm_page_t); 276 int moea64_page_wired_mappings(mmu_t, vm_page_t); 277 void moea64_pinit(mmu_t, pmap_t); 278 void moea64_pinit0(mmu_t, pmap_t); 279 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 280 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 281 void moea64_qremove(mmu_t, vm_offset_t, int); 282 void moea64_release(mmu_t, pmap_t); 283 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 284 void moea64_remove_pages(mmu_t, pmap_t); 285 void moea64_remove_all(mmu_t, vm_page_t); 286 void moea64_remove_write(mmu_t, vm_page_t); 287 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 288 void moea64_zero_page(mmu_t, vm_page_t); 289 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 290 void moea64_activate(mmu_t, struct thread *); 291 void moea64_deactivate(mmu_t, struct thread *); 292 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 293 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 294 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 295 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 296 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 297 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 298 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 299 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 300 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 301 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 302 void **va); 303 void moea64_scan_init(mmu_t mmu); 304 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 305 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 306 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 308 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 309 int *is_user, vm_offset_t *decoded_addr); 310 static size_t moea64_scan_pmap(mmu_t mmu); 311 static void *moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs); 312 #ifdef __powerpc64__ 313 static void moea64_page_array_startup(mmu_t, long); 314 #endif 315 316 317 static mmu_method_t moea64_methods[] = { 318 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 319 MMUMETHOD(mmu_copy_page, moea64_copy_page), 320 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 321 MMUMETHOD(mmu_enter, moea64_enter), 322 MMUMETHOD(mmu_enter_object, moea64_enter_object), 323 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 324 MMUMETHOD(mmu_extract, moea64_extract), 325 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 326 MMUMETHOD(mmu_init, moea64_init), 327 MMUMETHOD(mmu_is_modified, moea64_is_modified), 328 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 329 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 330 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 331 MMUMETHOD(mmu_map, moea64_map), 332 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 333 MMUMETHOD(mmu_page_init, moea64_page_init), 334 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 335 MMUMETHOD(mmu_pinit, moea64_pinit), 336 MMUMETHOD(mmu_pinit0, moea64_pinit0), 337 MMUMETHOD(mmu_protect, moea64_protect), 338 MMUMETHOD(mmu_qenter, moea64_qenter), 339 MMUMETHOD(mmu_qremove, moea64_qremove), 340 MMUMETHOD(mmu_release, moea64_release), 341 MMUMETHOD(mmu_remove, moea64_remove), 342 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 343 MMUMETHOD(mmu_remove_all, moea64_remove_all), 344 MMUMETHOD(mmu_remove_write, moea64_remove_write), 345 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 346 MMUMETHOD(mmu_unwire, moea64_unwire), 347 MMUMETHOD(mmu_zero_page, moea64_zero_page), 348 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 349 MMUMETHOD(mmu_activate, moea64_activate), 350 MMUMETHOD(mmu_deactivate, moea64_deactivate), 351 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 352 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 353 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 354 #ifdef __powerpc64__ 355 MMUMETHOD(mmu_page_array_startup, moea64_page_array_startup), 356 #endif 357 358 /* Internal interfaces */ 359 MMUMETHOD(mmu_mapdev, moea64_mapdev), 360 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 361 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 362 MMUMETHOD(mmu_kextract, moea64_kextract), 363 MMUMETHOD(mmu_kenter, moea64_kenter), 364 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 365 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 366 MMUMETHOD(mmu_scan_init, moea64_scan_init), 367 MMUMETHOD(mmu_scan_pmap, moea64_scan_pmap), 368 MMUMETHOD(mmu_dump_pmap_init, moea64_dump_pmap_init), 369 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 370 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 371 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 372 373 { 0, 0 } 374 }; 375 376 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 377 378 static struct pvo_head * 379 vm_page_to_pvoh(vm_page_t m) 380 { 381 382 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 383 return (&m->md.mdpg_pvoh); 384 } 385 386 static struct pvo_entry * 387 alloc_pvo_entry(int bootstrap) 388 { 389 struct pvo_entry *pvo; 390 391 if (!moea64_initialized || bootstrap) { 392 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 393 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 394 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 395 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 396 } 397 pvo = &moea64_bpvo_pool[ 398 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 399 bzero(pvo, sizeof(*pvo)); 400 pvo->pvo_vaddr = PVO_BOOTSTRAP; 401 } else 402 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 403 404 return (pvo); 405 } 406 407 408 static void 409 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 410 { 411 uint64_t vsid; 412 uint64_t hash; 413 int shift; 414 415 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 416 417 pvo->pvo_pmap = pmap; 418 va &= ~ADDR_POFF; 419 pvo->pvo_vaddr |= va; 420 vsid = va_to_vsid(pmap, va); 421 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 422 | (vsid << 16); 423 424 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 425 ADDR_PIDX_SHFT; 426 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 427 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 428 } 429 430 static void 431 free_pvo_entry(struct pvo_entry *pvo) 432 { 433 434 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 435 uma_zfree(moea64_pvo_zone, pvo); 436 } 437 438 void 439 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 440 { 441 442 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 443 lpte->pte_hi |= LPTE_VALID; 444 445 if (pvo->pvo_vaddr & PVO_LARGE) 446 lpte->pte_hi |= LPTE_BIG; 447 if (pvo->pvo_vaddr & PVO_WIRED) 448 lpte->pte_hi |= LPTE_WIRED; 449 if (pvo->pvo_vaddr & PVO_HID) 450 lpte->pte_hi |= LPTE_HID; 451 452 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 453 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 454 lpte->pte_lo |= LPTE_BW; 455 else 456 lpte->pte_lo |= LPTE_BR; 457 458 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 459 lpte->pte_lo |= LPTE_NOEXEC; 460 } 461 462 static __inline uint64_t 463 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 464 { 465 uint64_t pte_lo; 466 int i; 467 468 if (ma != VM_MEMATTR_DEFAULT) { 469 switch (ma) { 470 case VM_MEMATTR_UNCACHEABLE: 471 return (LPTE_I | LPTE_G); 472 case VM_MEMATTR_CACHEABLE: 473 return (LPTE_M); 474 case VM_MEMATTR_WRITE_COMBINING: 475 case VM_MEMATTR_WRITE_BACK: 476 case VM_MEMATTR_PREFETCHABLE: 477 return (LPTE_I); 478 case VM_MEMATTR_WRITE_THROUGH: 479 return (LPTE_W | LPTE_M); 480 } 481 } 482 483 /* 484 * Assume the page is cache inhibited and access is guarded unless 485 * it's in our available memory array. 486 */ 487 pte_lo = LPTE_I | LPTE_G; 488 for (i = 0; i < pregions_sz; i++) { 489 if ((pa >= pregions[i].mr_start) && 490 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 491 pte_lo &= ~(LPTE_I | LPTE_G); 492 pte_lo |= LPTE_M; 493 break; 494 } 495 } 496 497 return pte_lo; 498 } 499 500 /* 501 * Quick sort callout for comparing memory regions. 502 */ 503 static int om_cmp(const void *a, const void *b); 504 505 static int 506 om_cmp(const void *a, const void *b) 507 { 508 const struct ofw_map *mapa; 509 const struct ofw_map *mapb; 510 511 mapa = a; 512 mapb = b; 513 if (mapa->om_pa < mapb->om_pa) 514 return (-1); 515 else if (mapa->om_pa > mapb->om_pa) 516 return (1); 517 else 518 return (0); 519 } 520 521 static void 522 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 523 { 524 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 525 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 526 struct pvo_entry *pvo; 527 register_t msr; 528 vm_offset_t off; 529 vm_paddr_t pa_base; 530 int i, j; 531 532 bzero(translations, sz); 533 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 534 sizeof(acells)); 535 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 536 panic("moea64_bootstrap: can't get ofw translations"); 537 538 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 539 sz /= sizeof(cell_t); 540 for (i = 0, j = 0; i < sz; j++) { 541 translations[j].om_va = trans_cells[i++]; 542 translations[j].om_len = trans_cells[i++]; 543 translations[j].om_pa = trans_cells[i++]; 544 if (acells == 2) { 545 translations[j].om_pa <<= 32; 546 translations[j].om_pa |= trans_cells[i++]; 547 } 548 translations[j].om_mode = trans_cells[i++]; 549 } 550 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 551 i, sz)); 552 553 sz = j; 554 qsort(translations, sz, sizeof (*translations), om_cmp); 555 556 for (i = 0; i < sz; i++) { 557 pa_base = translations[i].om_pa; 558 #ifndef __powerpc64__ 559 if ((translations[i].om_pa >> 32) != 0) 560 panic("OFW translations above 32-bit boundary!"); 561 #endif 562 563 if (pa_base % PAGE_SIZE) 564 panic("OFW translation not page-aligned (phys)!"); 565 if (translations[i].om_va % PAGE_SIZE) 566 panic("OFW translation not page-aligned (virt)!"); 567 568 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 569 pa_base, translations[i].om_va, translations[i].om_len); 570 571 /* Now enter the pages for this mapping */ 572 573 DISABLE_TRANS(msr); 574 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 575 /* If this address is direct-mapped, skip remapping */ 576 if (hw_direct_map && 577 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 578 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 579 == LPTE_M) 580 continue; 581 582 PMAP_LOCK(kernel_pmap); 583 pvo = moea64_pvo_find_va(kernel_pmap, 584 translations[i].om_va + off); 585 PMAP_UNLOCK(kernel_pmap); 586 if (pvo != NULL) 587 continue; 588 589 moea64_kenter(mmup, translations[i].om_va + off, 590 pa_base + off); 591 } 592 ENABLE_TRANS(msr); 593 } 594 } 595 596 #ifdef __powerpc64__ 597 static void 598 moea64_probe_large_page(void) 599 { 600 uint16_t pvr = mfpvr() >> 16; 601 602 switch (pvr) { 603 case IBM970: 604 case IBM970FX: 605 case IBM970MP: 606 powerpc_sync(); isync(); 607 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 608 powerpc_sync(); isync(); 609 610 /* FALLTHROUGH */ 611 default: 612 if (moea64_large_page_size == 0) { 613 moea64_large_page_size = 0x1000000; /* 16 MB */ 614 moea64_large_page_shift = 24; 615 } 616 } 617 618 moea64_large_page_mask = moea64_large_page_size - 1; 619 } 620 621 static void 622 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 623 { 624 struct slb *cache; 625 struct slb entry; 626 uint64_t esid, slbe; 627 uint64_t i; 628 629 cache = PCPU_GET(aim.slb); 630 esid = va >> ADDR_SR_SHFT; 631 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 632 633 for (i = 0; i < 64; i++) { 634 if (cache[i].slbe == (slbe | i)) 635 return; 636 } 637 638 entry.slbe = slbe; 639 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 640 if (large) 641 entry.slbv |= SLBV_L; 642 643 slb_insert_kernel(entry.slbe, entry.slbv); 644 } 645 #endif 646 647 static int 648 moea64_kenter_large(mmu_t mmup, vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 649 { 650 struct pvo_entry *pvo; 651 uint64_t pte_lo; 652 int error; 653 654 pte_lo = LPTE_M; 655 pte_lo |= attr; 656 657 pvo = alloc_pvo_entry(bootstrap); 658 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 659 init_pvo_entry(pvo, kernel_pmap, va); 660 661 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 662 VM_PROT_EXECUTE; 663 pvo->pvo_pte.pa = pa | pte_lo; 664 error = moea64_pvo_enter(mmup, pvo, NULL, NULL); 665 if (error != 0) 666 panic("Error %d inserting large page\n", error); 667 return (0); 668 } 669 670 static void 671 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 672 vm_offset_t kernelend) 673 { 674 register_t msr; 675 vm_paddr_t pa, pkernelstart, pkernelend; 676 vm_offset_t size, off; 677 uint64_t pte_lo; 678 int i; 679 680 if (moea64_large_page_size == 0) 681 hw_direct_map = 0; 682 683 DISABLE_TRANS(msr); 684 if (hw_direct_map) { 685 PMAP_LOCK(kernel_pmap); 686 for (i = 0; i < pregions_sz; i++) { 687 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 688 pregions[i].mr_size; pa += moea64_large_page_size) { 689 pte_lo = LPTE_M; 690 if (pa & moea64_large_page_mask) { 691 pa &= moea64_large_page_mask; 692 pte_lo |= LPTE_G; 693 } 694 if (pa + moea64_large_page_size > 695 pregions[i].mr_start + pregions[i].mr_size) 696 pte_lo |= LPTE_G; 697 698 moea64_kenter_large(mmup, PHYS_TO_DMAP(pa), pa, pte_lo, 1); 699 } 700 } 701 PMAP_UNLOCK(kernel_pmap); 702 } 703 704 /* 705 * Make sure the kernel and BPVO pool stay mapped on systems either 706 * without a direct map or on which the kernel is not already executing 707 * out of the direct-mapped region. 708 */ 709 if (kernelstart < DMAP_BASE_ADDRESS) { 710 /* 711 * For pre-dmap execution, we need to use identity mapping 712 * because we will be operating with the mmu on but in the 713 * wrong address configuration until we __restartkernel(). 714 */ 715 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 716 pa += PAGE_SIZE) 717 moea64_kenter(mmup, pa, pa); 718 } else if (!hw_direct_map) { 719 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 720 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 721 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 722 pa += PAGE_SIZE) 723 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 724 } 725 726 if (!hw_direct_map) { 727 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 728 off = (vm_offset_t)(moea64_bpvo_pool); 729 for (pa = off; pa < off + size; pa += PAGE_SIZE) 730 moea64_kenter(mmup, pa, pa); 731 732 /* Map exception vectors */ 733 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 734 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 735 } 736 ENABLE_TRANS(msr); 737 738 /* 739 * Allow user to override unmapped_buf_allowed for testing. 740 * XXXKIB Only direct map implementation was tested. 741 */ 742 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 743 &unmapped_buf_allowed)) 744 unmapped_buf_allowed = hw_direct_map; 745 } 746 747 /* Quick sort callout for comparing physical addresses. */ 748 static int 749 pa_cmp(const void *a, const void *b) 750 { 751 const vm_paddr_t *pa = a, *pb = b; 752 753 if (*pa < *pb) 754 return (-1); 755 else if (*pa > *pb) 756 return (1); 757 else 758 return (0); 759 } 760 761 void 762 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 763 { 764 int i, j; 765 vm_size_t physsz, hwphyssz; 766 vm_paddr_t kernelphysstart, kernelphysend; 767 int rm_pavail; 768 769 #ifndef __powerpc64__ 770 /* We don't have a direct map since there is no BAT */ 771 hw_direct_map = 0; 772 773 /* Make sure battable is zero, since we have no BAT */ 774 for (i = 0; i < 16; i++) { 775 battable[i].batu = 0; 776 battable[i].batl = 0; 777 } 778 #else 779 moea64_probe_large_page(); 780 781 /* Use a direct map if we have large page support */ 782 if (moea64_large_page_size > 0) 783 hw_direct_map = 1; 784 else 785 hw_direct_map = 0; 786 787 /* Install trap handlers for SLBs */ 788 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 789 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 790 __syncicache((void *)EXC_DSE, 0x80); 791 __syncicache((void *)EXC_ISE, 0x80); 792 #endif 793 794 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 795 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 796 797 /* Get physical memory regions from firmware */ 798 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 799 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 800 801 if (PHYS_AVAIL_ENTRIES < regions_sz) 802 panic("moea64_bootstrap: phys_avail too small"); 803 804 phys_avail_count = 0; 805 physsz = 0; 806 hwphyssz = 0; 807 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 808 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 809 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 810 regions[i].mr_start, regions[i].mr_start + 811 regions[i].mr_size, regions[i].mr_size); 812 if (hwphyssz != 0 && 813 (physsz + regions[i].mr_size) >= hwphyssz) { 814 if (physsz < hwphyssz) { 815 phys_avail[j] = regions[i].mr_start; 816 phys_avail[j + 1] = regions[i].mr_start + 817 hwphyssz - physsz; 818 physsz = hwphyssz; 819 phys_avail_count++; 820 dump_avail[j] = phys_avail[j]; 821 dump_avail[j + 1] = phys_avail[j + 1]; 822 } 823 break; 824 } 825 phys_avail[j] = regions[i].mr_start; 826 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 827 phys_avail_count++; 828 physsz += regions[i].mr_size; 829 dump_avail[j] = phys_avail[j]; 830 dump_avail[j + 1] = phys_avail[j + 1]; 831 } 832 833 /* Check for overlap with the kernel and exception vectors */ 834 rm_pavail = 0; 835 for (j = 0; j < 2*phys_avail_count; j+=2) { 836 if (phys_avail[j] < EXC_LAST) 837 phys_avail[j] += EXC_LAST; 838 839 if (phys_avail[j] >= kernelphysstart && 840 phys_avail[j+1] <= kernelphysend) { 841 phys_avail[j] = phys_avail[j+1] = ~0; 842 rm_pavail++; 843 continue; 844 } 845 846 if (kernelphysstart >= phys_avail[j] && 847 kernelphysstart < phys_avail[j+1]) { 848 if (kernelphysend < phys_avail[j+1]) { 849 phys_avail[2*phys_avail_count] = 850 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 851 phys_avail[2*phys_avail_count + 1] = 852 phys_avail[j+1]; 853 phys_avail_count++; 854 } 855 856 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 857 } 858 859 if (kernelphysend >= phys_avail[j] && 860 kernelphysend < phys_avail[j+1]) { 861 if (kernelphysstart > phys_avail[j]) { 862 phys_avail[2*phys_avail_count] = phys_avail[j]; 863 phys_avail[2*phys_avail_count + 1] = 864 kernelphysstart & ~PAGE_MASK; 865 phys_avail_count++; 866 } 867 868 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 869 PAGE_SIZE; 870 } 871 } 872 873 /* Remove physical available regions marked for removal (~0) */ 874 if (rm_pavail) { 875 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 876 pa_cmp); 877 phys_avail_count -= rm_pavail; 878 for (i = 2*phys_avail_count; 879 i < 2*(phys_avail_count + rm_pavail); i+=2) 880 phys_avail[i] = phys_avail[i+1] = 0; 881 } 882 883 physmem = btoc(physsz); 884 885 #ifdef PTEGCOUNT 886 moea64_pteg_count = PTEGCOUNT; 887 #else 888 moea64_pteg_count = 0x1000; 889 890 while (moea64_pteg_count < physmem) 891 moea64_pteg_count <<= 1; 892 893 moea64_pteg_count >>= 1; 894 #endif /* PTEGCOUNT */ 895 } 896 897 void 898 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 899 { 900 int i; 901 902 /* 903 * Set PTEG mask 904 */ 905 moea64_pteg_mask = moea64_pteg_count - 1; 906 907 /* 908 * Initialize SLB table lock and page locks 909 */ 910 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 911 for (i = 0; i < PV_LOCK_COUNT; i++) 912 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 913 914 /* 915 * Initialise the bootstrap pvo pool. 916 */ 917 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 918 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 919 moea64_bpvo_pool_index = 0; 920 921 /* Place at address usable through the direct map */ 922 if (hw_direct_map) 923 moea64_bpvo_pool = (struct pvo_entry *) 924 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 925 926 /* 927 * Make sure kernel vsid is allocated as well as VSID 0. 928 */ 929 #ifndef __powerpc64__ 930 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 931 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 932 moea64_vsid_bitmap[0] |= 1; 933 #endif 934 935 /* 936 * Initialize the kernel pmap (which is statically allocated). 937 */ 938 #ifdef __powerpc64__ 939 for (i = 0; i < 64; i++) { 940 pcpup->pc_aim.slb[i].slbv = 0; 941 pcpup->pc_aim.slb[i].slbe = 0; 942 } 943 #else 944 for (i = 0; i < 16; i++) 945 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 946 #endif 947 948 kernel_pmap->pmap_phys = kernel_pmap; 949 CPU_FILL(&kernel_pmap->pm_active); 950 RB_INIT(&kernel_pmap->pmap_pvo); 951 952 PMAP_LOCK_INIT(kernel_pmap); 953 954 /* 955 * Now map in all the other buffers we allocated earlier 956 */ 957 958 moea64_setup_direct_map(mmup, kernelstart, kernelend); 959 } 960 961 void 962 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 963 { 964 ihandle_t mmui; 965 phandle_t chosen; 966 phandle_t mmu; 967 ssize_t sz; 968 int i; 969 vm_offset_t pa, va; 970 void *dpcpu; 971 972 /* 973 * Set up the Open Firmware pmap and add its mappings if not in real 974 * mode. 975 */ 976 977 chosen = OF_finddevice("/chosen"); 978 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 979 mmu = OF_instance_to_package(mmui); 980 if (mmu == -1 || 981 (sz = OF_getproplen(mmu, "translations")) == -1) 982 sz = 0; 983 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 984 panic("moea64_bootstrap: too many ofw translations"); 985 986 if (sz > 0) 987 moea64_add_ofw_mappings(mmup, mmu, sz); 988 } 989 990 /* 991 * Calculate the last available physical address. 992 */ 993 Maxmem = 0; 994 for (i = 0; phys_avail[i + 2] != 0; i += 2) 995 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 996 997 /* 998 * Initialize MMU. 999 */ 1000 MMU_CPU_BOOTSTRAP(mmup,0); 1001 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1002 pmap_bootstrapped++; 1003 1004 /* 1005 * Set the start and end of kva. 1006 */ 1007 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1008 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1009 1010 /* 1011 * Map the entire KVA range into the SLB. We must not fault there. 1012 */ 1013 #ifdef __powerpc64__ 1014 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1015 moea64_bootstrap_slb_prefault(va, 0); 1016 #endif 1017 1018 /* 1019 * Remap any early IO mappings (console framebuffer, etc.) 1020 */ 1021 bs_remap_earlyboot(); 1022 1023 /* 1024 * Figure out how far we can extend virtual_end into segment 16 1025 * without running into existing mappings. Segment 16 is guaranteed 1026 * to contain neither RAM nor devices (at least on Apple hardware), 1027 * but will generally contain some OFW mappings we should not 1028 * step on. 1029 */ 1030 1031 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1032 PMAP_LOCK(kernel_pmap); 1033 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1034 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1035 virtual_end += PAGE_SIZE; 1036 PMAP_UNLOCK(kernel_pmap); 1037 #endif 1038 1039 /* 1040 * Allocate a kernel stack with a guard page for thread0 and map it 1041 * into the kernel page map. 1042 */ 1043 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1044 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1045 virtual_avail = va + kstack_pages * PAGE_SIZE; 1046 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1047 thread0.td_kstack = va; 1048 thread0.td_kstack_pages = kstack_pages; 1049 for (i = 0; i < kstack_pages; i++) { 1050 moea64_kenter(mmup, va, pa); 1051 pa += PAGE_SIZE; 1052 va += PAGE_SIZE; 1053 } 1054 1055 /* 1056 * Allocate virtual address space for the message buffer. 1057 */ 1058 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1059 msgbufp = (struct msgbuf *)virtual_avail; 1060 va = virtual_avail; 1061 virtual_avail += round_page(msgbufsize); 1062 while (va < virtual_avail) { 1063 moea64_kenter(mmup, va, pa); 1064 pa += PAGE_SIZE; 1065 va += PAGE_SIZE; 1066 } 1067 1068 /* 1069 * Allocate virtual address space for the dynamic percpu area. 1070 */ 1071 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1072 dpcpu = (void *)virtual_avail; 1073 va = virtual_avail; 1074 virtual_avail += DPCPU_SIZE; 1075 while (va < virtual_avail) { 1076 moea64_kenter(mmup, va, pa); 1077 pa += PAGE_SIZE; 1078 va += PAGE_SIZE; 1079 } 1080 dpcpu_init(dpcpu, curcpu); 1081 1082 crashdumpmap = (caddr_t)virtual_avail; 1083 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1084 1085 /* 1086 * Allocate some things for page zeroing. We put this directly 1087 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1088 * of the PVO book-keeping or other parts of the VM system 1089 * from even knowing that this hack exists. 1090 */ 1091 1092 if (!hw_direct_map) { 1093 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1094 MTX_DEF); 1095 for (i = 0; i < 2; i++) { 1096 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1097 virtual_end -= PAGE_SIZE; 1098 1099 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1100 1101 PMAP_LOCK(kernel_pmap); 1102 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1103 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1104 PMAP_UNLOCK(kernel_pmap); 1105 } 1106 } 1107 1108 numa_mem_regions(&numa_pregions, &numapregions_sz); 1109 } 1110 1111 static void 1112 moea64_pmap_init_qpages(void) 1113 { 1114 struct pcpu *pc; 1115 int i; 1116 1117 if (hw_direct_map) 1118 return; 1119 1120 CPU_FOREACH(i) { 1121 pc = pcpu_find(i); 1122 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1123 if (pc->pc_qmap_addr == 0) 1124 panic("pmap_init_qpages: unable to allocate KVA"); 1125 PMAP_LOCK(kernel_pmap); 1126 pc->pc_aim.qmap_pvo = 1127 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1128 PMAP_UNLOCK(kernel_pmap); 1129 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1130 } 1131 } 1132 1133 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1134 1135 /* 1136 * Activate a user pmap. This mostly involves setting some non-CPU 1137 * state. 1138 */ 1139 void 1140 moea64_activate(mmu_t mmu, struct thread *td) 1141 { 1142 pmap_t pm; 1143 1144 pm = &td->td_proc->p_vmspace->vm_pmap; 1145 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1146 1147 #ifdef __powerpc64__ 1148 PCPU_SET(aim.userslb, pm->pm_slb); 1149 __asm __volatile("slbmte %0, %1; isync" :: 1150 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1151 #else 1152 PCPU_SET(curpmap, pm->pmap_phys); 1153 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1154 #endif 1155 } 1156 1157 void 1158 moea64_deactivate(mmu_t mmu, struct thread *td) 1159 { 1160 pmap_t pm; 1161 1162 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1163 1164 pm = &td->td_proc->p_vmspace->vm_pmap; 1165 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1166 #ifdef __powerpc64__ 1167 PCPU_SET(aim.userslb, NULL); 1168 #else 1169 PCPU_SET(curpmap, NULL); 1170 #endif 1171 } 1172 1173 void 1174 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1175 { 1176 struct pvo_entry key, *pvo; 1177 vm_page_t m; 1178 int64_t refchg; 1179 1180 key.pvo_vaddr = sva; 1181 PMAP_LOCK(pm); 1182 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1183 pvo != NULL && PVO_VADDR(pvo) < eva; 1184 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1185 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1186 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1187 pvo); 1188 pvo->pvo_vaddr &= ~PVO_WIRED; 1189 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1190 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1191 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1192 if (refchg < 0) 1193 refchg = LPTE_CHG; 1194 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1195 1196 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1197 if (refchg & LPTE_CHG) 1198 vm_page_dirty(m); 1199 if (refchg & LPTE_REF) 1200 vm_page_aflag_set(m, PGA_REFERENCED); 1201 } 1202 pm->pm_stats.wired_count--; 1203 } 1204 PMAP_UNLOCK(pm); 1205 } 1206 1207 /* 1208 * This goes through and sets the physical address of our 1209 * special scratch PTE to the PA we want to zero or copy. Because 1210 * of locking issues (this can get called in pvo_enter() by 1211 * the UMA allocator), we can't use most other utility functions here 1212 */ 1213 1214 static __inline 1215 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1216 { 1217 struct pvo_entry *pvo; 1218 1219 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1220 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1221 1222 pvo = moea64_scratchpage_pvo[which]; 1223 PMAP_LOCK(pvo->pvo_pmap); 1224 pvo->pvo_pte.pa = 1225 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1226 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1227 PMAP_UNLOCK(pvo->pvo_pmap); 1228 isync(); 1229 } 1230 1231 void 1232 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1233 { 1234 vm_offset_t dst; 1235 vm_offset_t src; 1236 1237 dst = VM_PAGE_TO_PHYS(mdst); 1238 src = VM_PAGE_TO_PHYS(msrc); 1239 1240 if (hw_direct_map) { 1241 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1242 PAGE_SIZE); 1243 } else { 1244 mtx_lock(&moea64_scratchpage_mtx); 1245 1246 moea64_set_scratchpage_pa(mmu, 0, src); 1247 moea64_set_scratchpage_pa(mmu, 1, dst); 1248 1249 bcopy((void *)moea64_scratchpage_va[0], 1250 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1251 1252 mtx_unlock(&moea64_scratchpage_mtx); 1253 } 1254 } 1255 1256 static inline void 1257 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1258 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1259 { 1260 void *a_cp, *b_cp; 1261 vm_offset_t a_pg_offset, b_pg_offset; 1262 int cnt; 1263 1264 while (xfersize > 0) { 1265 a_pg_offset = a_offset & PAGE_MASK; 1266 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1267 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1268 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1269 a_pg_offset; 1270 b_pg_offset = b_offset & PAGE_MASK; 1271 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1272 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1273 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1274 b_pg_offset; 1275 bcopy(a_cp, b_cp, cnt); 1276 a_offset += cnt; 1277 b_offset += cnt; 1278 xfersize -= cnt; 1279 } 1280 } 1281 1282 static inline void 1283 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1284 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1285 { 1286 void *a_cp, *b_cp; 1287 vm_offset_t a_pg_offset, b_pg_offset; 1288 int cnt; 1289 1290 mtx_lock(&moea64_scratchpage_mtx); 1291 while (xfersize > 0) { 1292 a_pg_offset = a_offset & PAGE_MASK; 1293 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1294 moea64_set_scratchpage_pa(mmu, 0, 1295 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1296 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1297 b_pg_offset = b_offset & PAGE_MASK; 1298 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1299 moea64_set_scratchpage_pa(mmu, 1, 1300 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1301 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1302 bcopy(a_cp, b_cp, cnt); 1303 a_offset += cnt; 1304 b_offset += cnt; 1305 xfersize -= cnt; 1306 } 1307 mtx_unlock(&moea64_scratchpage_mtx); 1308 } 1309 1310 void 1311 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1312 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1313 { 1314 1315 if (hw_direct_map) { 1316 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1317 xfersize); 1318 } else { 1319 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1320 xfersize); 1321 } 1322 } 1323 1324 void 1325 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1326 { 1327 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1328 1329 if (size + off > PAGE_SIZE) 1330 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1331 1332 if (hw_direct_map) { 1333 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1334 } else { 1335 mtx_lock(&moea64_scratchpage_mtx); 1336 moea64_set_scratchpage_pa(mmu, 0, pa); 1337 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1338 mtx_unlock(&moea64_scratchpage_mtx); 1339 } 1340 } 1341 1342 /* 1343 * Zero a page of physical memory by temporarily mapping it 1344 */ 1345 void 1346 moea64_zero_page(mmu_t mmu, vm_page_t m) 1347 { 1348 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1349 vm_offset_t va, off; 1350 1351 if (!hw_direct_map) { 1352 mtx_lock(&moea64_scratchpage_mtx); 1353 1354 moea64_set_scratchpage_pa(mmu, 0, pa); 1355 va = moea64_scratchpage_va[0]; 1356 } else { 1357 va = PHYS_TO_DMAP(pa); 1358 } 1359 1360 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1361 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1362 1363 if (!hw_direct_map) 1364 mtx_unlock(&moea64_scratchpage_mtx); 1365 } 1366 1367 vm_offset_t 1368 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1369 { 1370 struct pvo_entry *pvo; 1371 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1372 1373 if (hw_direct_map) 1374 return (PHYS_TO_DMAP(pa)); 1375 1376 /* 1377 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1378 * a critical section and access the PCPU data like on i386. 1379 * Instead, pin the thread and grab the PCPU lock to prevent 1380 * a preempting thread from using the same PCPU data. 1381 */ 1382 sched_pin(); 1383 1384 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1385 pvo = PCPU_GET(aim.qmap_pvo); 1386 1387 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1388 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1389 (uint64_t)pa; 1390 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1391 isync(); 1392 1393 return (PCPU_GET(qmap_addr)); 1394 } 1395 1396 void 1397 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1398 { 1399 if (hw_direct_map) 1400 return; 1401 1402 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1403 KASSERT(PCPU_GET(qmap_addr) == addr, 1404 ("moea64_quick_remove_page: invalid address")); 1405 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1406 sched_unpin(); 1407 } 1408 1409 /* 1410 * Map the given physical page at the specified virtual address in the 1411 * target pmap with the protection requested. If specified the page 1412 * will be wired down. 1413 */ 1414 1415 int 1416 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1417 vm_prot_t prot, u_int flags, int8_t psind) 1418 { 1419 struct pvo_entry *pvo, *oldpvo; 1420 struct pvo_head *pvo_head; 1421 uint64_t pte_lo; 1422 int error; 1423 1424 if ((m->oflags & VPO_UNMANAGED) == 0) { 1425 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1426 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1427 else 1428 VM_OBJECT_ASSERT_LOCKED(m->object); 1429 } 1430 1431 pvo = alloc_pvo_entry(0); 1432 if (pvo == NULL) 1433 return (KERN_RESOURCE_SHORTAGE); 1434 pvo->pvo_pmap = NULL; /* to be filled in later */ 1435 pvo->pvo_pte.prot = prot; 1436 1437 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1438 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1439 1440 if ((flags & PMAP_ENTER_WIRED) != 0) 1441 pvo->pvo_vaddr |= PVO_WIRED; 1442 1443 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1444 pvo_head = NULL; 1445 } else { 1446 pvo_head = &m->md.mdpg_pvoh; 1447 pvo->pvo_vaddr |= PVO_MANAGED; 1448 } 1449 1450 PV_PAGE_LOCK(m); 1451 PMAP_LOCK(pmap); 1452 if (pvo->pvo_pmap == NULL) 1453 init_pvo_entry(pvo, pmap, va); 1454 if (prot & VM_PROT_WRITE) 1455 if (pmap_bootstrapped && 1456 (m->oflags & VPO_UNMANAGED) == 0) 1457 vm_page_aflag_set(m, PGA_WRITEABLE); 1458 1459 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1460 if (error == EEXIST) { 1461 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1462 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1463 oldpvo->pvo_pte.prot == prot) { 1464 /* Identical mapping already exists */ 1465 error = 0; 1466 1467 /* If not in page table, reinsert it */ 1468 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1469 STAT_MOEA64(moea64_pte_overflow--); 1470 MOEA64_PTE_INSERT(mmu, oldpvo); 1471 } 1472 1473 /* Then just clean up and go home */ 1474 PV_PAGE_UNLOCK(m); 1475 PMAP_UNLOCK(pmap); 1476 free_pvo_entry(pvo); 1477 goto out; 1478 } else { 1479 /* Otherwise, need to kill it first */ 1480 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1481 "mapping does not match new mapping")); 1482 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1483 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1484 } 1485 } 1486 PMAP_UNLOCK(pmap); 1487 PV_PAGE_UNLOCK(m); 1488 1489 /* Free any dead pages */ 1490 if (error == EEXIST) { 1491 moea64_pvo_remove_from_page(mmu, oldpvo); 1492 free_pvo_entry(oldpvo); 1493 } 1494 1495 out: 1496 /* 1497 * Flush the page from the instruction cache if this page is 1498 * mapped executable and cacheable. 1499 */ 1500 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1501 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1502 vm_page_aflag_set(m, PGA_EXECUTABLE); 1503 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1504 } 1505 return (KERN_SUCCESS); 1506 } 1507 1508 static void 1509 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1510 vm_size_t sz) 1511 { 1512 1513 /* 1514 * This is much trickier than on older systems because 1515 * we can't sync the icache on physical addresses directly 1516 * without a direct map. Instead we check a couple of cases 1517 * where the memory is already mapped in and, failing that, 1518 * use the same trick we use for page zeroing to create 1519 * a temporary mapping for this physical address. 1520 */ 1521 1522 if (!pmap_bootstrapped) { 1523 /* 1524 * If PMAP is not bootstrapped, we are likely to be 1525 * in real mode. 1526 */ 1527 __syncicache((void *)(uintptr_t)pa, sz); 1528 } else if (pmap == kernel_pmap) { 1529 __syncicache((void *)va, sz); 1530 } else if (hw_direct_map) { 1531 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1532 } else { 1533 /* Use the scratch page to set up a temp mapping */ 1534 1535 mtx_lock(&moea64_scratchpage_mtx); 1536 1537 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1538 __syncicache((void *)(moea64_scratchpage_va[1] + 1539 (va & ADDR_POFF)), sz); 1540 1541 mtx_unlock(&moea64_scratchpage_mtx); 1542 } 1543 } 1544 1545 /* 1546 * Maps a sequence of resident pages belonging to the same object. 1547 * The sequence begins with the given page m_start. This page is 1548 * mapped at the given virtual address start. Each subsequent page is 1549 * mapped at a virtual address that is offset from start by the same 1550 * amount as the page is offset from m_start within the object. The 1551 * last page in the sequence is the page with the largest offset from 1552 * m_start that can be mapped at a virtual address less than the given 1553 * virtual address end. Not every virtual page between start and end 1554 * is mapped; only those for which a resident page exists with the 1555 * corresponding offset from m_start are mapped. 1556 */ 1557 void 1558 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1559 vm_page_t m_start, vm_prot_t prot) 1560 { 1561 vm_page_t m; 1562 vm_pindex_t diff, psize; 1563 1564 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1565 1566 psize = atop(end - start); 1567 m = m_start; 1568 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1569 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1570 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1571 PMAP_ENTER_QUICK_LOCKED, 0); 1572 m = TAILQ_NEXT(m, listq); 1573 } 1574 } 1575 1576 void 1577 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1578 vm_prot_t prot) 1579 { 1580 1581 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1582 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1583 } 1584 1585 vm_paddr_t 1586 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1587 { 1588 struct pvo_entry *pvo; 1589 vm_paddr_t pa; 1590 1591 PMAP_LOCK(pm); 1592 pvo = moea64_pvo_find_va(pm, va); 1593 if (pvo == NULL) 1594 pa = 0; 1595 else 1596 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1597 PMAP_UNLOCK(pm); 1598 1599 return (pa); 1600 } 1601 1602 /* 1603 * Atomically extract and hold the physical page with the given 1604 * pmap and virtual address pair if that mapping permits the given 1605 * protection. 1606 */ 1607 vm_page_t 1608 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1609 { 1610 struct pvo_entry *pvo; 1611 vm_page_t m; 1612 1613 m = NULL; 1614 PMAP_LOCK(pmap); 1615 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1616 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1617 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1618 if (!vm_page_wire_mapped(m)) 1619 m = NULL; 1620 } 1621 PMAP_UNLOCK(pmap); 1622 return (m); 1623 } 1624 1625 static mmu_t installed_mmu; 1626 1627 static void * 1628 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1629 uint8_t *flags, int wait) 1630 { 1631 struct pvo_entry *pvo; 1632 vm_offset_t va; 1633 vm_page_t m; 1634 int needed_lock; 1635 1636 /* 1637 * This entire routine is a horrible hack to avoid bothering kmem 1638 * for new KVA addresses. Because this can get called from inside 1639 * kmem allocation routines, calling kmem for a new address here 1640 * can lead to multiply locking non-recursive mutexes. 1641 */ 1642 1643 *flags = UMA_SLAB_PRIV; 1644 needed_lock = !PMAP_LOCKED(kernel_pmap); 1645 1646 m = vm_page_alloc_domain(NULL, 0, domain, 1647 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1648 if (m == NULL) 1649 return (NULL); 1650 1651 va = VM_PAGE_TO_PHYS(m); 1652 1653 pvo = alloc_pvo_entry(1 /* bootstrap */); 1654 1655 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1656 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1657 1658 if (needed_lock) 1659 PMAP_LOCK(kernel_pmap); 1660 1661 init_pvo_entry(pvo, kernel_pmap, va); 1662 pvo->pvo_vaddr |= PVO_WIRED; 1663 1664 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1665 1666 if (needed_lock) 1667 PMAP_UNLOCK(kernel_pmap); 1668 1669 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1670 bzero((void *)va, PAGE_SIZE); 1671 1672 return (void *)va; 1673 } 1674 1675 extern int elf32_nxstack; 1676 1677 void 1678 moea64_init(mmu_t mmu) 1679 { 1680 1681 CTR0(KTR_PMAP, "moea64_init"); 1682 1683 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1684 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1685 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1686 1687 if (!hw_direct_map) { 1688 installed_mmu = mmu; 1689 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1690 } 1691 1692 #ifdef COMPAT_FREEBSD32 1693 elf32_nxstack = 1; 1694 #endif 1695 1696 moea64_initialized = TRUE; 1697 } 1698 1699 boolean_t 1700 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1701 { 1702 1703 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1704 ("moea64_is_referenced: page %p is not managed", m)); 1705 1706 return (moea64_query_bit(mmu, m, LPTE_REF)); 1707 } 1708 1709 boolean_t 1710 moea64_is_modified(mmu_t mmu, vm_page_t m) 1711 { 1712 1713 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1714 ("moea64_is_modified: page %p is not managed", m)); 1715 1716 /* 1717 * If the page is not busied then this check is racy. 1718 */ 1719 if (!pmap_page_is_write_mapped(m)) 1720 return (FALSE); 1721 1722 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1723 } 1724 1725 boolean_t 1726 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1727 { 1728 struct pvo_entry *pvo; 1729 boolean_t rv = TRUE; 1730 1731 PMAP_LOCK(pmap); 1732 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1733 if (pvo != NULL) 1734 rv = FALSE; 1735 PMAP_UNLOCK(pmap); 1736 return (rv); 1737 } 1738 1739 void 1740 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1741 { 1742 1743 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1744 ("moea64_clear_modify: page %p is not managed", m)); 1745 vm_page_assert_busied(m); 1746 1747 if (!pmap_page_is_write_mapped(m)) 1748 return; 1749 moea64_clear_bit(mmu, m, LPTE_CHG); 1750 } 1751 1752 /* 1753 * Clear the write and modified bits in each of the given page's mappings. 1754 */ 1755 void 1756 moea64_remove_write(mmu_t mmu, vm_page_t m) 1757 { 1758 struct pvo_entry *pvo; 1759 int64_t refchg, ret; 1760 pmap_t pmap; 1761 1762 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1763 ("moea64_remove_write: page %p is not managed", m)); 1764 vm_page_assert_busied(m); 1765 1766 if (!pmap_page_is_write_mapped(m)) 1767 return 1768 1769 powerpc_sync(); 1770 PV_PAGE_LOCK(m); 1771 refchg = 0; 1772 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1773 pmap = pvo->pvo_pmap; 1774 PMAP_LOCK(pmap); 1775 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1776 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1777 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1778 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1779 MOEA64_PTE_PROT_UPDATE); 1780 if (ret < 0) 1781 ret = LPTE_CHG; 1782 refchg |= ret; 1783 if (pvo->pvo_pmap == kernel_pmap) 1784 isync(); 1785 } 1786 PMAP_UNLOCK(pmap); 1787 } 1788 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1789 vm_page_dirty(m); 1790 vm_page_aflag_clear(m, PGA_WRITEABLE); 1791 PV_PAGE_UNLOCK(m); 1792 } 1793 1794 /* 1795 * moea64_ts_referenced: 1796 * 1797 * Return a count of reference bits for a page, clearing those bits. 1798 * It is not necessary for every reference bit to be cleared, but it 1799 * is necessary that 0 only be returned when there are truly no 1800 * reference bits set. 1801 * 1802 * XXX: The exact number of bits to check and clear is a matter that 1803 * should be tested and standardized at some point in the future for 1804 * optimal aging of shared pages. 1805 */ 1806 int 1807 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1808 { 1809 1810 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1811 ("moea64_ts_referenced: page %p is not managed", m)); 1812 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1813 } 1814 1815 /* 1816 * Modify the WIMG settings of all mappings for a page. 1817 */ 1818 void 1819 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1820 { 1821 struct pvo_entry *pvo; 1822 int64_t refchg; 1823 pmap_t pmap; 1824 uint64_t lo; 1825 1826 if ((m->oflags & VPO_UNMANAGED) != 0) { 1827 m->md.mdpg_cache_attrs = ma; 1828 return; 1829 } 1830 1831 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1832 1833 PV_PAGE_LOCK(m); 1834 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1835 pmap = pvo->pvo_pmap; 1836 PMAP_LOCK(pmap); 1837 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1838 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1839 pvo->pvo_pte.pa |= lo; 1840 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1841 MOEA64_PTE_INVALIDATE); 1842 if (refchg < 0) 1843 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1844 LPTE_CHG : 0; 1845 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1846 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1847 refchg |= 1848 atomic_readandclear_32(&m->md.mdpg_attrs); 1849 if (refchg & LPTE_CHG) 1850 vm_page_dirty(m); 1851 if (refchg & LPTE_REF) 1852 vm_page_aflag_set(m, PGA_REFERENCED); 1853 } 1854 if (pvo->pvo_pmap == kernel_pmap) 1855 isync(); 1856 } 1857 PMAP_UNLOCK(pmap); 1858 } 1859 m->md.mdpg_cache_attrs = ma; 1860 PV_PAGE_UNLOCK(m); 1861 } 1862 1863 /* 1864 * Map a wired page into kernel virtual address space. 1865 */ 1866 void 1867 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1868 { 1869 int error; 1870 struct pvo_entry *pvo, *oldpvo; 1871 1872 do { 1873 pvo = alloc_pvo_entry(0); 1874 if (pvo == NULL) 1875 vm_wait(NULL); 1876 } while (pvo == NULL); 1877 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1878 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1879 pvo->pvo_vaddr |= PVO_WIRED; 1880 1881 PMAP_LOCK(kernel_pmap); 1882 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1883 if (oldpvo != NULL) 1884 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1885 init_pvo_entry(pvo, kernel_pmap, va); 1886 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1887 PMAP_UNLOCK(kernel_pmap); 1888 1889 /* Free any dead pages */ 1890 if (oldpvo != NULL) { 1891 moea64_pvo_remove_from_page(mmu, oldpvo); 1892 free_pvo_entry(oldpvo); 1893 } 1894 1895 if (error != 0) 1896 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1897 (uintmax_t)pa, error); 1898 } 1899 1900 void 1901 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1902 { 1903 1904 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1905 } 1906 1907 /* 1908 * Extract the physical page address associated with the given kernel virtual 1909 * address. 1910 */ 1911 vm_paddr_t 1912 moea64_kextract(mmu_t mmu, vm_offset_t va) 1913 { 1914 struct pvo_entry *pvo; 1915 vm_paddr_t pa; 1916 1917 /* 1918 * Shortcut the direct-mapped case when applicable. We never put 1919 * anything but 1:1 (or 62-bit aliased) mappings below 1920 * VM_MIN_KERNEL_ADDRESS. 1921 */ 1922 if (va < VM_MIN_KERNEL_ADDRESS) 1923 return (va & ~DMAP_BASE_ADDRESS); 1924 1925 PMAP_LOCK(kernel_pmap); 1926 pvo = moea64_pvo_find_va(kernel_pmap, va); 1927 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1928 va)); 1929 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1930 PMAP_UNLOCK(kernel_pmap); 1931 return (pa); 1932 } 1933 1934 /* 1935 * Remove a wired page from kernel virtual address space. 1936 */ 1937 void 1938 moea64_kremove(mmu_t mmu, vm_offset_t va) 1939 { 1940 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1941 } 1942 1943 /* 1944 * Provide a kernel pointer corresponding to a given userland pointer. 1945 * The returned pointer is valid until the next time this function is 1946 * called in this thread. This is used internally in copyin/copyout. 1947 */ 1948 static int 1949 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1950 void **kaddr, size_t ulen, size_t *klen) 1951 { 1952 size_t l; 1953 #ifdef __powerpc64__ 1954 struct slb *slb; 1955 #endif 1956 register_t slbv; 1957 1958 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1959 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1960 if (l > ulen) 1961 l = ulen; 1962 if (klen) 1963 *klen = l; 1964 else if (l != ulen) 1965 return (EFAULT); 1966 1967 #ifdef __powerpc64__ 1968 /* Try lockless look-up first */ 1969 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1970 1971 if (slb == NULL) { 1972 /* If it isn't there, we need to pre-fault the VSID */ 1973 PMAP_LOCK(pm); 1974 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1975 PMAP_UNLOCK(pm); 1976 } else { 1977 slbv = slb->slbv; 1978 } 1979 1980 /* Mark segment no-execute */ 1981 slbv |= SLBV_N; 1982 #else 1983 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1984 1985 /* Mark segment no-execute */ 1986 slbv |= SR_N; 1987 #endif 1988 1989 /* If we have already set this VSID, we can just return */ 1990 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1991 return (0); 1992 1993 __asm __volatile("isync"); 1994 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1995 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1996 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1997 #ifdef __powerpc64__ 1998 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1999 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2000 #else 2001 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2002 #endif 2003 2004 return (0); 2005 } 2006 2007 /* 2008 * Figure out where a given kernel pointer (usually in a fault) points 2009 * to from the VM's perspective, potentially remapping into userland's 2010 * address space. 2011 */ 2012 static int 2013 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2014 vm_offset_t *decoded_addr) 2015 { 2016 vm_offset_t user_sr; 2017 2018 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2019 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2020 addr &= ADDR_PIDX | ADDR_POFF; 2021 addr |= user_sr << ADDR_SR_SHFT; 2022 *decoded_addr = addr; 2023 *is_user = 1; 2024 } else { 2025 *decoded_addr = addr; 2026 *is_user = 0; 2027 } 2028 2029 return (0); 2030 } 2031 2032 /* 2033 * Map a range of physical addresses into kernel virtual address space. 2034 * 2035 * The value passed in *virt is a suggested virtual address for the mapping. 2036 * Architectures which can support a direct-mapped physical to virtual region 2037 * can return the appropriate address within that region, leaving '*virt' 2038 * unchanged. Other architectures should map the pages starting at '*virt' and 2039 * update '*virt' with the first usable address after the mapped region. 2040 */ 2041 vm_offset_t 2042 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2043 vm_paddr_t pa_end, int prot) 2044 { 2045 vm_offset_t sva, va; 2046 2047 if (hw_direct_map) { 2048 /* 2049 * Check if every page in the region is covered by the direct 2050 * map. The direct map covers all of physical memory. Use 2051 * moea64_calc_wimg() as a shortcut to see if the page is in 2052 * physical memory as a way to see if the direct map covers it. 2053 */ 2054 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2055 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2056 break; 2057 if (va == pa_end) 2058 return (PHYS_TO_DMAP(pa_start)); 2059 } 2060 sva = *virt; 2061 va = sva; 2062 /* XXX respect prot argument */ 2063 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2064 moea64_kenter(mmu, va, pa_start); 2065 *virt = va; 2066 2067 return (sva); 2068 } 2069 2070 /* 2071 * Returns true if the pmap's pv is one of the first 2072 * 16 pvs linked to from this page. This count may 2073 * be changed upwards or downwards in the future; it 2074 * is only necessary that true be returned for a small 2075 * subset of pmaps for proper page aging. 2076 */ 2077 boolean_t 2078 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2079 { 2080 int loops; 2081 struct pvo_entry *pvo; 2082 boolean_t rv; 2083 2084 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2085 ("moea64_page_exists_quick: page %p is not managed", m)); 2086 loops = 0; 2087 rv = FALSE; 2088 PV_PAGE_LOCK(m); 2089 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2090 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2091 rv = TRUE; 2092 break; 2093 } 2094 if (++loops >= 16) 2095 break; 2096 } 2097 PV_PAGE_UNLOCK(m); 2098 return (rv); 2099 } 2100 2101 void 2102 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2103 { 2104 2105 m->md.mdpg_attrs = 0; 2106 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2107 LIST_INIT(&m->md.mdpg_pvoh); 2108 } 2109 2110 /* 2111 * Return the number of managed mappings to the given physical page 2112 * that are wired. 2113 */ 2114 int 2115 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2116 { 2117 struct pvo_entry *pvo; 2118 int count; 2119 2120 count = 0; 2121 if ((m->oflags & VPO_UNMANAGED) != 0) 2122 return (count); 2123 PV_PAGE_LOCK(m); 2124 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2125 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2126 count++; 2127 PV_PAGE_UNLOCK(m); 2128 return (count); 2129 } 2130 2131 static uintptr_t moea64_vsidcontext; 2132 2133 uintptr_t 2134 moea64_get_unique_vsid(void) { 2135 u_int entropy; 2136 register_t hash; 2137 uint32_t mask; 2138 int i; 2139 2140 entropy = 0; 2141 __asm __volatile("mftb %0" : "=r"(entropy)); 2142 2143 mtx_lock(&moea64_slb_mutex); 2144 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2145 u_int n; 2146 2147 /* 2148 * Create a new value by mutiplying by a prime and adding in 2149 * entropy from the timebase register. This is to make the 2150 * VSID more random so that the PT hash function collides 2151 * less often. (Note that the prime casues gcc to do shifts 2152 * instead of a multiply.) 2153 */ 2154 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2155 hash = moea64_vsidcontext & (NVSIDS - 1); 2156 if (hash == 0) /* 0 is special, avoid it */ 2157 continue; 2158 n = hash >> 5; 2159 mask = 1 << (hash & (VSID_NBPW - 1)); 2160 hash = (moea64_vsidcontext & VSID_HASHMASK); 2161 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2162 /* anything free in this bucket? */ 2163 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2164 entropy = (moea64_vsidcontext >> 20); 2165 continue; 2166 } 2167 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2168 mask = 1 << i; 2169 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2170 hash |= i; 2171 } 2172 if (hash == VSID_VRMA) /* also special, avoid this too */ 2173 continue; 2174 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2175 ("Allocating in-use VSID %#zx\n", hash)); 2176 moea64_vsid_bitmap[n] |= mask; 2177 mtx_unlock(&moea64_slb_mutex); 2178 return (hash); 2179 } 2180 2181 mtx_unlock(&moea64_slb_mutex); 2182 panic("%s: out of segments",__func__); 2183 } 2184 2185 #ifdef __powerpc64__ 2186 void 2187 moea64_pinit(mmu_t mmu, pmap_t pmap) 2188 { 2189 2190 RB_INIT(&pmap->pmap_pvo); 2191 2192 pmap->pm_slb_tree_root = slb_alloc_tree(); 2193 pmap->pm_slb = slb_alloc_user_cache(); 2194 pmap->pm_slb_len = 0; 2195 } 2196 #else 2197 void 2198 moea64_pinit(mmu_t mmu, pmap_t pmap) 2199 { 2200 int i; 2201 uint32_t hash; 2202 2203 RB_INIT(&pmap->pmap_pvo); 2204 2205 if (pmap_bootstrapped) 2206 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2207 (vm_offset_t)pmap); 2208 else 2209 pmap->pmap_phys = pmap; 2210 2211 /* 2212 * Allocate some segment registers for this pmap. 2213 */ 2214 hash = moea64_get_unique_vsid(); 2215 2216 for (i = 0; i < 16; i++) 2217 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2218 2219 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2220 } 2221 #endif 2222 2223 /* 2224 * Initialize the pmap associated with process 0. 2225 */ 2226 void 2227 moea64_pinit0(mmu_t mmu, pmap_t pm) 2228 { 2229 2230 PMAP_LOCK_INIT(pm); 2231 moea64_pinit(mmu, pm); 2232 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2233 } 2234 2235 /* 2236 * Set the physical protection on the specified range of this map as requested. 2237 */ 2238 static void 2239 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2240 { 2241 struct vm_page *pg; 2242 vm_prot_t oldprot; 2243 int32_t refchg; 2244 2245 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2246 2247 /* 2248 * Change the protection of the page. 2249 */ 2250 oldprot = pvo->pvo_pte.prot; 2251 pvo->pvo_pte.prot = prot; 2252 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2253 2254 /* 2255 * If the PVO is in the page table, update mapping 2256 */ 2257 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2258 if (refchg < 0) 2259 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2260 2261 if (pm != kernel_pmap && pg != NULL && 2262 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2263 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2264 if ((pg->oflags & VPO_UNMANAGED) == 0) 2265 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2266 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2267 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2268 } 2269 2270 /* 2271 * Update vm about the REF/CHG bits if the page is managed and we have 2272 * removed write access. 2273 */ 2274 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2275 (oldprot & VM_PROT_WRITE)) { 2276 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2277 if (refchg & LPTE_CHG) 2278 vm_page_dirty(pg); 2279 if (refchg & LPTE_REF) 2280 vm_page_aflag_set(pg, PGA_REFERENCED); 2281 } 2282 } 2283 2284 void 2285 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2286 vm_prot_t prot) 2287 { 2288 struct pvo_entry *pvo, *tpvo, key; 2289 2290 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2291 sva, eva, prot); 2292 2293 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2294 ("moea64_protect: non current pmap")); 2295 2296 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2297 moea64_remove(mmu, pm, sva, eva); 2298 return; 2299 } 2300 2301 PMAP_LOCK(pm); 2302 key.pvo_vaddr = sva; 2303 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2304 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2305 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2306 moea64_pvo_protect(mmu, pm, pvo, prot); 2307 } 2308 PMAP_UNLOCK(pm); 2309 } 2310 2311 /* 2312 * Map a list of wired pages into kernel virtual address space. This is 2313 * intended for temporary mappings which do not need page modification or 2314 * references recorded. Existing mappings in the region are overwritten. 2315 */ 2316 void 2317 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2318 { 2319 while (count-- > 0) { 2320 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2321 va += PAGE_SIZE; 2322 m++; 2323 } 2324 } 2325 2326 /* 2327 * Remove page mappings from kernel virtual address space. Intended for 2328 * temporary mappings entered by moea64_qenter. 2329 */ 2330 void 2331 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2332 { 2333 while (count-- > 0) { 2334 moea64_kremove(mmu, va); 2335 va += PAGE_SIZE; 2336 } 2337 } 2338 2339 void 2340 moea64_release_vsid(uint64_t vsid) 2341 { 2342 int idx, mask; 2343 2344 mtx_lock(&moea64_slb_mutex); 2345 idx = vsid & (NVSIDS-1); 2346 mask = 1 << (idx % VSID_NBPW); 2347 idx /= VSID_NBPW; 2348 KASSERT(moea64_vsid_bitmap[idx] & mask, 2349 ("Freeing unallocated VSID %#jx", vsid)); 2350 moea64_vsid_bitmap[idx] &= ~mask; 2351 mtx_unlock(&moea64_slb_mutex); 2352 } 2353 2354 2355 void 2356 moea64_release(mmu_t mmu, pmap_t pmap) 2357 { 2358 2359 /* 2360 * Free segment registers' VSIDs 2361 */ 2362 #ifdef __powerpc64__ 2363 slb_free_tree(pmap); 2364 slb_free_user_cache(pmap->pm_slb); 2365 #else 2366 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2367 2368 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2369 #endif 2370 } 2371 2372 /* 2373 * Remove all pages mapped by the specified pmap 2374 */ 2375 void 2376 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2377 { 2378 struct pvo_entry *pvo, *tpvo; 2379 struct pvo_dlist tofree; 2380 2381 SLIST_INIT(&tofree); 2382 2383 PMAP_LOCK(pm); 2384 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2385 if (pvo->pvo_vaddr & PVO_WIRED) 2386 continue; 2387 2388 /* 2389 * For locking reasons, remove this from the page table and 2390 * pmap, but save delinking from the vm_page for a second 2391 * pass 2392 */ 2393 moea64_pvo_remove_from_pmap(mmu, pvo); 2394 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2395 } 2396 PMAP_UNLOCK(pm); 2397 2398 while (!SLIST_EMPTY(&tofree)) { 2399 pvo = SLIST_FIRST(&tofree); 2400 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2401 moea64_pvo_remove_from_page(mmu, pvo); 2402 free_pvo_entry(pvo); 2403 } 2404 } 2405 2406 /* 2407 * Remove the given range of addresses from the specified map. 2408 */ 2409 void 2410 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2411 { 2412 struct pvo_entry *pvo, *tpvo, key; 2413 struct pvo_dlist tofree; 2414 2415 /* 2416 * Perform an unsynchronized read. This is, however, safe. 2417 */ 2418 if (pm->pm_stats.resident_count == 0) 2419 return; 2420 2421 key.pvo_vaddr = sva; 2422 2423 SLIST_INIT(&tofree); 2424 2425 PMAP_LOCK(pm); 2426 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2427 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2428 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2429 2430 /* 2431 * For locking reasons, remove this from the page table and 2432 * pmap, but save delinking from the vm_page for a second 2433 * pass 2434 */ 2435 moea64_pvo_remove_from_pmap(mmu, pvo); 2436 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2437 } 2438 PMAP_UNLOCK(pm); 2439 2440 while (!SLIST_EMPTY(&tofree)) { 2441 pvo = SLIST_FIRST(&tofree); 2442 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2443 moea64_pvo_remove_from_page(mmu, pvo); 2444 free_pvo_entry(pvo); 2445 } 2446 } 2447 2448 /* 2449 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2450 * will reflect changes in pte's back to the vm_page. 2451 */ 2452 void 2453 moea64_remove_all(mmu_t mmu, vm_page_t m) 2454 { 2455 struct pvo_entry *pvo, *next_pvo; 2456 struct pvo_head freequeue; 2457 int wasdead; 2458 pmap_t pmap; 2459 2460 LIST_INIT(&freequeue); 2461 2462 PV_PAGE_LOCK(m); 2463 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2464 pmap = pvo->pvo_pmap; 2465 PMAP_LOCK(pmap); 2466 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2467 if (!wasdead) 2468 moea64_pvo_remove_from_pmap(mmu, pvo); 2469 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2470 if (!wasdead) 2471 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2472 PMAP_UNLOCK(pmap); 2473 2474 } 2475 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2476 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2477 PV_PAGE_UNLOCK(m); 2478 2479 /* Clean up UMA allocations */ 2480 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2481 free_pvo_entry(pvo); 2482 } 2483 2484 /* 2485 * Allocate a physical page of memory directly from the phys_avail map. 2486 * Can only be called from moea64_bootstrap before avail start and end are 2487 * calculated. 2488 */ 2489 vm_offset_t 2490 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2491 { 2492 vm_offset_t s, e; 2493 int i, j; 2494 2495 size = round_page(size); 2496 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2497 if (align != 0) 2498 s = roundup2(phys_avail[i], align); 2499 else 2500 s = phys_avail[i]; 2501 e = s + size; 2502 2503 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2504 continue; 2505 2506 if (s + size > platform_real_maxaddr()) 2507 continue; 2508 2509 if (s == phys_avail[i]) { 2510 phys_avail[i] += size; 2511 } else if (e == phys_avail[i + 1]) { 2512 phys_avail[i + 1] -= size; 2513 } else { 2514 for (j = phys_avail_count * 2; j > i; j -= 2) { 2515 phys_avail[j] = phys_avail[j - 2]; 2516 phys_avail[j + 1] = phys_avail[j - 1]; 2517 } 2518 2519 phys_avail[i + 3] = phys_avail[i + 1]; 2520 phys_avail[i + 1] = s; 2521 phys_avail[i + 2] = e; 2522 phys_avail_count++; 2523 } 2524 2525 return (s); 2526 } 2527 panic("moea64_bootstrap_alloc: could not allocate memory"); 2528 } 2529 2530 static int 2531 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2532 struct pvo_entry **oldpvop) 2533 { 2534 struct pvo_entry *old_pvo; 2535 int err; 2536 2537 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2538 2539 STAT_MOEA64(moea64_pvo_enter_calls++); 2540 2541 /* 2542 * Add to pmap list 2543 */ 2544 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2545 2546 if (old_pvo != NULL) { 2547 if (oldpvop != NULL) 2548 *oldpvop = old_pvo; 2549 return (EEXIST); 2550 } 2551 2552 if (pvo_head != NULL) { 2553 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2554 } 2555 2556 if (pvo->pvo_vaddr & PVO_WIRED) 2557 pvo->pvo_pmap->pm_stats.wired_count++; 2558 pvo->pvo_pmap->pm_stats.resident_count++; 2559 2560 /* 2561 * Insert it into the hardware page table 2562 */ 2563 err = MOEA64_PTE_INSERT(mmu, pvo); 2564 if (err != 0) { 2565 panic("moea64_pvo_enter: overflow"); 2566 } 2567 2568 STAT_MOEA64(moea64_pvo_entries++); 2569 2570 if (pvo->pvo_pmap == kernel_pmap) 2571 isync(); 2572 2573 #ifdef __powerpc64__ 2574 /* 2575 * Make sure all our bootstrap mappings are in the SLB as soon 2576 * as virtual memory is switched on. 2577 */ 2578 if (!pmap_bootstrapped) 2579 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2580 pvo->pvo_vaddr & PVO_LARGE); 2581 #endif 2582 2583 return (0); 2584 } 2585 2586 static void 2587 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2588 { 2589 struct vm_page *pg; 2590 int32_t refchg; 2591 2592 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2593 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2594 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2595 2596 /* 2597 * If there is an active pte entry, we need to deactivate it 2598 */ 2599 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2600 if (refchg < 0) { 2601 /* 2602 * If it was evicted from the page table, be pessimistic and 2603 * dirty the page. 2604 */ 2605 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2606 refchg = LPTE_CHG; 2607 else 2608 refchg = 0; 2609 } 2610 2611 /* 2612 * Update our statistics. 2613 */ 2614 pvo->pvo_pmap->pm_stats.resident_count--; 2615 if (pvo->pvo_vaddr & PVO_WIRED) 2616 pvo->pvo_pmap->pm_stats.wired_count--; 2617 2618 /* 2619 * Remove this PVO from the pmap list. 2620 */ 2621 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2622 2623 /* 2624 * Mark this for the next sweep 2625 */ 2626 pvo->pvo_vaddr |= PVO_DEAD; 2627 2628 /* Send RC bits to VM */ 2629 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2630 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2631 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2632 if (pg != NULL) { 2633 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2634 if (refchg & LPTE_CHG) 2635 vm_page_dirty(pg); 2636 if (refchg & LPTE_REF) 2637 vm_page_aflag_set(pg, PGA_REFERENCED); 2638 } 2639 } 2640 } 2641 2642 static inline void 2643 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2644 vm_page_t m) 2645 { 2646 2647 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2648 2649 /* Use NULL pmaps as a sentinel for races in page deletion */ 2650 if (pvo->pvo_pmap == NULL) 2651 return; 2652 pvo->pvo_pmap = NULL; 2653 2654 /* 2655 * Update vm about page writeability/executability if managed 2656 */ 2657 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2658 if (pvo->pvo_vaddr & PVO_MANAGED) { 2659 if (m != NULL) { 2660 LIST_REMOVE(pvo, pvo_vlink); 2661 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2662 vm_page_aflag_clear(m, 2663 PGA_WRITEABLE | PGA_EXECUTABLE); 2664 } 2665 } 2666 2667 STAT_MOEA64(moea64_pvo_entries--); 2668 STAT_MOEA64(moea64_pvo_remove_calls++); 2669 } 2670 2671 static void 2672 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2673 { 2674 vm_page_t pg = NULL; 2675 2676 if (pvo->pvo_vaddr & PVO_MANAGED) 2677 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2678 2679 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2680 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2681 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2682 } 2683 2684 static struct pvo_entry * 2685 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2686 { 2687 struct pvo_entry key; 2688 2689 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2690 2691 key.pvo_vaddr = va & ~ADDR_POFF; 2692 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2693 } 2694 2695 static boolean_t 2696 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2697 { 2698 struct pvo_entry *pvo; 2699 int64_t ret; 2700 boolean_t rv; 2701 2702 /* 2703 * See if this bit is stored in the page already. 2704 */ 2705 if (m->md.mdpg_attrs & ptebit) 2706 return (TRUE); 2707 2708 /* 2709 * Examine each PTE. Sync so that any pending REF/CHG bits are 2710 * flushed to the PTEs. 2711 */ 2712 rv = FALSE; 2713 powerpc_sync(); 2714 PV_PAGE_LOCK(m); 2715 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2716 ret = 0; 2717 2718 /* 2719 * See if this pvo has a valid PTE. if so, fetch the 2720 * REF/CHG bits from the valid PTE. If the appropriate 2721 * ptebit is set, return success. 2722 */ 2723 PMAP_LOCK(pvo->pvo_pmap); 2724 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2725 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2726 PMAP_UNLOCK(pvo->pvo_pmap); 2727 2728 if (ret > 0) { 2729 atomic_set_32(&m->md.mdpg_attrs, 2730 ret & (LPTE_CHG | LPTE_REF)); 2731 if (ret & ptebit) { 2732 rv = TRUE; 2733 break; 2734 } 2735 } 2736 } 2737 PV_PAGE_UNLOCK(m); 2738 2739 return (rv); 2740 } 2741 2742 static u_int 2743 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2744 { 2745 u_int count; 2746 struct pvo_entry *pvo; 2747 int64_t ret; 2748 2749 /* 2750 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2751 * we can reset the right ones). 2752 */ 2753 powerpc_sync(); 2754 2755 /* 2756 * For each pvo entry, clear the pte's ptebit. 2757 */ 2758 count = 0; 2759 PV_PAGE_LOCK(m); 2760 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2761 ret = 0; 2762 2763 PMAP_LOCK(pvo->pvo_pmap); 2764 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2765 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2766 PMAP_UNLOCK(pvo->pvo_pmap); 2767 2768 if (ret > 0 && (ret & ptebit)) 2769 count++; 2770 } 2771 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2772 PV_PAGE_UNLOCK(m); 2773 2774 return (count); 2775 } 2776 2777 boolean_t 2778 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2779 { 2780 struct pvo_entry *pvo, key; 2781 vm_offset_t ppa; 2782 int error = 0; 2783 2784 if (hw_direct_map && mem_valid(pa, size) == 0) 2785 return (0); 2786 2787 PMAP_LOCK(kernel_pmap); 2788 ppa = pa & ~ADDR_POFF; 2789 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2790 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2791 ppa < pa + size; ppa += PAGE_SIZE, 2792 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2793 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2794 error = EFAULT; 2795 break; 2796 } 2797 } 2798 PMAP_UNLOCK(kernel_pmap); 2799 2800 return (error); 2801 } 2802 2803 /* 2804 * Map a set of physical memory pages into the kernel virtual 2805 * address space. Return a pointer to where it is mapped. This 2806 * routine is intended to be used for mapping device memory, 2807 * NOT real memory. 2808 */ 2809 void * 2810 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2811 { 2812 vm_offset_t va, tmpva, ppa, offset; 2813 2814 ppa = trunc_page(pa); 2815 offset = pa & PAGE_MASK; 2816 size = roundup2(offset + size, PAGE_SIZE); 2817 2818 va = kva_alloc(size); 2819 2820 if (!va) 2821 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2822 2823 for (tmpva = va; size > 0;) { 2824 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2825 size -= PAGE_SIZE; 2826 tmpva += PAGE_SIZE; 2827 ppa += PAGE_SIZE; 2828 } 2829 2830 return ((void *)(va + offset)); 2831 } 2832 2833 void * 2834 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2835 { 2836 2837 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2838 } 2839 2840 void 2841 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2842 { 2843 vm_offset_t base, offset; 2844 2845 base = trunc_page(va); 2846 offset = va & PAGE_MASK; 2847 size = roundup2(offset + size, PAGE_SIZE); 2848 2849 kva_free(base, size); 2850 } 2851 2852 void 2853 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2854 { 2855 struct pvo_entry *pvo; 2856 vm_offset_t lim; 2857 vm_paddr_t pa; 2858 vm_size_t len; 2859 2860 if (__predict_false(pm == NULL)) 2861 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2862 2863 PMAP_LOCK(pm); 2864 while (sz > 0) { 2865 lim = round_page(va+1); 2866 len = MIN(lim - va, sz); 2867 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2868 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2869 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2870 moea64_syncicache(mmu, pm, va, pa, len); 2871 } 2872 va += len; 2873 sz -= len; 2874 } 2875 PMAP_UNLOCK(pm); 2876 } 2877 2878 void 2879 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2880 { 2881 2882 *va = (void *)(uintptr_t)pa; 2883 } 2884 2885 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2886 2887 void 2888 moea64_scan_init(mmu_t mmu) 2889 { 2890 struct pvo_entry *pvo; 2891 vm_offset_t va; 2892 int i; 2893 2894 if (!do_minidump) { 2895 /* Initialize phys. segments for dumpsys(). */ 2896 memset(&dump_map, 0, sizeof(dump_map)); 2897 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2898 for (i = 0; i < pregions_sz; i++) { 2899 dump_map[i].pa_start = pregions[i].mr_start; 2900 dump_map[i].pa_size = pregions[i].mr_size; 2901 } 2902 return; 2903 } 2904 2905 /* Virtual segments for minidumps: */ 2906 memset(&dump_map, 0, sizeof(dump_map)); 2907 2908 /* 1st: kernel .data and .bss. */ 2909 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2910 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2911 dump_map[0].pa_start; 2912 2913 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2914 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2915 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2916 2917 /* 3rd: kernel VM. */ 2918 va = dump_map[1].pa_start + dump_map[1].pa_size; 2919 /* Find start of next chunk (from va). */ 2920 while (va < virtual_end) { 2921 /* Don't dump the buffer cache. */ 2922 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2923 va = kmi.buffer_eva; 2924 continue; 2925 } 2926 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2927 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2928 break; 2929 va += PAGE_SIZE; 2930 } 2931 if (va < virtual_end) { 2932 dump_map[2].pa_start = va; 2933 va += PAGE_SIZE; 2934 /* Find last page in chunk. */ 2935 while (va < virtual_end) { 2936 /* Don't run into the buffer cache. */ 2937 if (va == kmi.buffer_sva) 2938 break; 2939 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2940 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2941 break; 2942 va += PAGE_SIZE; 2943 } 2944 dump_map[2].pa_size = va - dump_map[2].pa_start; 2945 } 2946 } 2947 2948 #ifdef __powerpc64__ 2949 2950 static size_t 2951 moea64_scan_pmap(mmu_t mmu) 2952 { 2953 struct pvo_entry *pvo; 2954 vm_paddr_t pa, pa_end; 2955 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 2956 uint64_t lpsize; 2957 2958 lpsize = moea64_large_page_size; 2959 kstart = trunc_page((vm_offset_t)_etext); 2960 kend = round_page((vm_offset_t)_end); 2961 kstart_lp = kstart & ~moea64_large_page_mask; 2962 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 2963 2964 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 2965 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 2966 kstart, kend, kstart_lp, kend_lp); 2967 2968 PMAP_LOCK(kernel_pmap); 2969 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 2970 va = pvo->pvo_vaddr; 2971 2972 if (va & PVO_DEAD) 2973 continue; 2974 2975 /* Skip DMAP (except kernel area) */ 2976 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 2977 if (va & PVO_LARGE) { 2978 pgva = va & ~moea64_large_page_mask; 2979 if (pgva < kstart_lp || pgva >= kend_lp) 2980 continue; 2981 } else { 2982 pgva = trunc_page(va); 2983 if (pgva < kstart || pgva >= kend) 2984 continue; 2985 } 2986 } 2987 2988 pa = pvo->pvo_pte.pa & LPTE_RPGN; 2989 2990 if (va & PVO_LARGE) { 2991 pa_end = pa + lpsize; 2992 for (; pa < pa_end; pa += PAGE_SIZE) { 2993 if (is_dumpable(pa)) 2994 dump_add_page(pa); 2995 } 2996 } else { 2997 if (is_dumpable(pa)) 2998 dump_add_page(pa); 2999 } 3000 } 3001 PMAP_UNLOCK(kernel_pmap); 3002 3003 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3004 } 3005 3006 static struct dump_context dump_ctx; 3007 3008 static void * 3009 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3010 { 3011 dump_ctx.ptex = 0; 3012 dump_ctx.ptex_end = moea64_pteg_count * 8; 3013 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3014 return (&dump_ctx); 3015 } 3016 3017 #else 3018 3019 static size_t 3020 moea64_scan_pmap(mmu_t mmu) 3021 { 3022 return (0); 3023 } 3024 3025 static void * 3026 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3027 { 3028 return (NULL); 3029 } 3030 3031 #endif 3032 3033 #ifdef __powerpc64__ 3034 static void 3035 moea64_map_range(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3036 { 3037 3038 for (; npages > 0; --npages) { 3039 if (moea64_large_page_size != 0 && 3040 (pa & moea64_large_page_mask) == 0 && 3041 (va & moea64_large_page_mask) == 0 && 3042 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3043 PMAP_LOCK(kernel_pmap); 3044 moea64_kenter_large(mmu, va, pa, 0, 0); 3045 PMAP_UNLOCK(kernel_pmap); 3046 pa += moea64_large_page_size; 3047 va += moea64_large_page_size; 3048 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3049 } else { 3050 moea64_kenter(mmu, va, pa); 3051 pa += PAGE_SIZE; 3052 va += PAGE_SIZE; 3053 } 3054 } 3055 } 3056 3057 static void 3058 moea64_page_array_startup(mmu_t mmu, long pages) 3059 { 3060 long dom_pages[MAXMEMDOM]; 3061 vm_paddr_t pa; 3062 vm_offset_t va, vm_page_base; 3063 vm_size_t needed, size; 3064 long page; 3065 int domain; 3066 int i; 3067 3068 vm_page_base = 0xd000000000000000ULL; 3069 3070 /* Short-circuit single-domain systems. */ 3071 if (vm_ndomains == 1) { 3072 size = round_page(pages * sizeof(struct vm_page)); 3073 pa = vm_phys_early_alloc(0, size); 3074 vm_page_base = moea64_map(mmu, &vm_page_base, 3075 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3076 vm_page_array_size = pages; 3077 vm_page_array = (vm_page_t)vm_page_base; 3078 return; 3079 } 3080 3081 page = 0; 3082 for (i = 0; i < MAXMEMDOM; i++) 3083 dom_pages[i] = 0; 3084 3085 /* Now get the number of pages required per domain. */ 3086 for (i = 0; i < vm_phys_nsegs; i++) { 3087 domain = vm_phys_segs[i].domain; 3088 KASSERT(domain < MAXMEMDOM, 3089 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3090 /* Get size of vm_page_array needed for this segment. */ 3091 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3092 dom_pages[domain] += size; 3093 } 3094 3095 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3096 domain = _vm_phys_domain(phys_avail[i]); 3097 KASSERT(domain < MAXMEMDOM, 3098 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3099 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3100 dom_pages[domain] += size; 3101 } 3102 3103 /* 3104 * Map in chunks that can get us all 16MB pages. There will be some 3105 * overlap between domains, but that's acceptable for now. 3106 */ 3107 vm_page_array_size = 0; 3108 va = vm_page_base; 3109 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3110 if (dom_pages[i] == 0) 3111 continue; 3112 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3113 size = round_page(size * sizeof(struct vm_page)); 3114 needed = size; 3115 size = roundup2(size, moea64_large_page_size); 3116 pa = vm_phys_early_alloc(i, size); 3117 vm_page_array_size += size / sizeof(struct vm_page); 3118 moea64_map_range(mmu, va, pa, size >> PAGE_SHIFT); 3119 /* Scoot up domain 0, to reduce the domain page overlap. */ 3120 if (i == 0) 3121 vm_page_base += size - needed; 3122 va += size; 3123 } 3124 vm_page_array = (vm_page_t)vm_page_base; 3125 vm_page_array_size = pages; 3126 } 3127 #endif 3128