1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/_inttypes.h> 146 #include <machine/cpu.h> 147 #include <machine/platform.h> 148 #include <machine/frame.h> 149 #include <machine/md_var.h> 150 #include <machine/psl.h> 151 #include <machine/bat.h> 152 #include <machine/hid.h> 153 #include <machine/pte.h> 154 #include <machine/sr.h> 155 #include <machine/trap.h> 156 #include <machine/mmuvar.h> 157 158 #include "mmu_oea64.h" 159 #include "mmu_if.h" 160 #include "moea64_if.h" 161 162 void moea64_release_vsid(uint64_t vsid); 163 uintptr_t moea64_get_unique_vsid(void); 164 165 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 166 #define ENABLE_TRANS(msr) mtmsr(msr) 167 168 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 169 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 170 #define VSID_HASH_MASK 0x0000007fffffffffULL 171 172 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 173 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 174 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 175 176 struct ofw_map { 177 cell_t om_va; 178 cell_t om_len; 179 cell_t om_pa_hi; 180 cell_t om_pa_lo; 181 cell_t om_mode; 182 }; 183 184 /* 185 * Map of physical memory regions. 186 */ 187 static struct mem_region *regions; 188 static struct mem_region *pregions; 189 static u_int phys_avail_count; 190 static int regions_sz, pregions_sz; 191 192 extern void bs_remap_earlyboot(void); 193 194 /* 195 * Lock for the pteg and pvo tables. 196 */ 197 struct mtx moea64_table_mutex; 198 struct mtx moea64_slb_mutex; 199 200 /* 201 * PTEG data. 202 */ 203 u_int moea64_pteg_count; 204 u_int moea64_pteg_mask; 205 206 /* 207 * PVO data. 208 */ 209 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 210 struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */ 211 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 212 213 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 214 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 215 216 #define BPVO_POOL_SIZE 327680 217 static struct pvo_entry *moea64_bpvo_pool; 218 static int moea64_bpvo_pool_index = 0; 219 220 #define VSID_NBPW (sizeof(u_int32_t) * 8) 221 #ifdef __powerpc64__ 222 #define NVSIDS (NPMAPS * 16) 223 #define VSID_HASHMASK 0xffffffffUL 224 #else 225 #define NVSIDS NPMAPS 226 #define VSID_HASHMASK 0xfffffUL 227 #endif 228 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 229 230 static boolean_t moea64_initialized = FALSE; 231 232 /* 233 * Statistics. 234 */ 235 u_int moea64_pte_valid = 0; 236 u_int moea64_pte_overflow = 0; 237 u_int moea64_pvo_entries = 0; 238 u_int moea64_pvo_enter_calls = 0; 239 u_int moea64_pvo_remove_calls = 0; 240 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 241 &moea64_pte_valid, 0, ""); 242 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 243 &moea64_pte_overflow, 0, ""); 244 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 245 &moea64_pvo_entries, 0, ""); 246 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 247 &moea64_pvo_enter_calls, 0, ""); 248 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 249 &moea64_pvo_remove_calls, 0, ""); 250 251 vm_offset_t moea64_scratchpage_va[2]; 252 struct pvo_entry *moea64_scratchpage_pvo[2]; 253 uintptr_t moea64_scratchpage_pte[2]; 254 struct mtx moea64_scratchpage_mtx; 255 256 uint64_t moea64_large_page_mask = 0; 257 int moea64_large_page_size = 0; 258 int moea64_large_page_shift = 0; 259 260 /* 261 * PVO calls. 262 */ 263 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 264 vm_offset_t, vm_offset_t, uint64_t, int); 265 static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 266 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 267 268 /* 269 * Utility routines. 270 */ 271 static void moea64_enter_locked(mmu_t, pmap_t, vm_offset_t, 272 vm_page_t, vm_prot_t, boolean_t); 273 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 274 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 275 static void moea64_kremove(mmu_t, vm_offset_t); 276 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 277 vm_offset_t pa, vm_size_t sz); 278 279 /* 280 * Kernel MMU interface 281 */ 282 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 283 void moea64_clear_modify(mmu_t, vm_page_t); 284 void moea64_clear_reference(mmu_t, vm_page_t); 285 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 286 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 287 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 288 vm_prot_t); 289 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 290 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 291 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 292 void moea64_init(mmu_t); 293 boolean_t moea64_is_modified(mmu_t, vm_page_t); 294 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 295 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 296 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 297 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 298 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 299 int moea64_page_wired_mappings(mmu_t, vm_page_t); 300 void moea64_pinit(mmu_t, pmap_t); 301 void moea64_pinit0(mmu_t, pmap_t); 302 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 303 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304 void moea64_qremove(mmu_t, vm_offset_t, int); 305 void moea64_release(mmu_t, pmap_t); 306 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307 void moea64_remove_all(mmu_t, vm_page_t); 308 void moea64_remove_write(mmu_t, vm_page_t); 309 void moea64_zero_page(mmu_t, vm_page_t); 310 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 311 void moea64_zero_page_idle(mmu_t, vm_page_t); 312 void moea64_activate(mmu_t, struct thread *); 313 void moea64_deactivate(mmu_t, struct thread *); 314 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 315 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 316 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 317 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 318 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 319 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 320 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 321 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 322 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 323 324 static mmu_method_t moea64_methods[] = { 325 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 326 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 327 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 328 MMUMETHOD(mmu_copy_page, moea64_copy_page), 329 MMUMETHOD(mmu_enter, moea64_enter), 330 MMUMETHOD(mmu_enter_object, moea64_enter_object), 331 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 332 MMUMETHOD(mmu_extract, moea64_extract), 333 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 334 MMUMETHOD(mmu_init, moea64_init), 335 MMUMETHOD(mmu_is_modified, moea64_is_modified), 336 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 337 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 338 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 339 MMUMETHOD(mmu_map, moea64_map), 340 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 341 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 342 MMUMETHOD(mmu_pinit, moea64_pinit), 343 MMUMETHOD(mmu_pinit0, moea64_pinit0), 344 MMUMETHOD(mmu_protect, moea64_protect), 345 MMUMETHOD(mmu_qenter, moea64_qenter), 346 MMUMETHOD(mmu_qremove, moea64_qremove), 347 MMUMETHOD(mmu_release, moea64_release), 348 MMUMETHOD(mmu_remove, moea64_remove), 349 MMUMETHOD(mmu_remove_all, moea64_remove_all), 350 MMUMETHOD(mmu_remove_write, moea64_remove_write), 351 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 352 MMUMETHOD(mmu_zero_page, moea64_zero_page), 353 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 354 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 355 MMUMETHOD(mmu_activate, moea64_activate), 356 MMUMETHOD(mmu_deactivate, moea64_deactivate), 357 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 358 359 /* Internal interfaces */ 360 MMUMETHOD(mmu_mapdev, moea64_mapdev), 361 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 362 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 363 MMUMETHOD(mmu_kextract, moea64_kextract), 364 MMUMETHOD(mmu_kenter, moea64_kenter), 365 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 366 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 367 368 { 0, 0 } 369 }; 370 371 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 372 373 static __inline u_int 374 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 375 { 376 uint64_t hash; 377 int shift; 378 379 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 380 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 381 shift); 382 return (hash & moea64_pteg_mask); 383 } 384 385 static __inline struct pvo_head * 386 vm_page_to_pvoh(vm_page_t m) 387 { 388 389 return (&m->md.mdpg_pvoh); 390 } 391 392 static __inline void 393 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 394 { 395 396 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 397 m->md.mdpg_attrs &= ~ptebit; 398 } 399 400 static __inline u_int64_t 401 moea64_attr_fetch(vm_page_t m) 402 { 403 404 return (m->md.mdpg_attrs); 405 } 406 407 static __inline void 408 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 409 { 410 411 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 412 m->md.mdpg_attrs |= ptebit; 413 } 414 415 static __inline void 416 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 417 uint64_t pte_lo, int flags) 418 { 419 420 ASSERT_TABLE_LOCK(); 421 422 /* 423 * Construct a PTE. Default to IMB initially. Valid bit only gets 424 * set when the real pte is set in memory. 425 * 426 * Note: Don't set the valid bit for correct operation of tlb update. 427 */ 428 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 429 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 430 431 if (flags & PVO_LARGE) 432 pt->pte_hi |= LPTE_BIG; 433 434 pt->pte_lo = pte_lo; 435 } 436 437 static __inline uint64_t 438 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 439 { 440 uint64_t pte_lo; 441 int i; 442 443 if (ma != VM_MEMATTR_DEFAULT) { 444 switch (ma) { 445 case VM_MEMATTR_UNCACHEABLE: 446 return (LPTE_I | LPTE_G); 447 case VM_MEMATTR_WRITE_COMBINING: 448 case VM_MEMATTR_WRITE_BACK: 449 case VM_MEMATTR_PREFETCHABLE: 450 return (LPTE_I); 451 case VM_MEMATTR_WRITE_THROUGH: 452 return (LPTE_W | LPTE_M); 453 } 454 } 455 456 /* 457 * Assume the page is cache inhibited and access is guarded unless 458 * it's in our available memory array. 459 */ 460 pte_lo = LPTE_I | LPTE_G; 461 for (i = 0; i < pregions_sz; i++) { 462 if ((pa >= pregions[i].mr_start) && 463 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 464 pte_lo &= ~(LPTE_I | LPTE_G); 465 pte_lo |= LPTE_M; 466 break; 467 } 468 } 469 470 return pte_lo; 471 } 472 473 /* 474 * Quick sort callout for comparing memory regions. 475 */ 476 static int om_cmp(const void *a, const void *b); 477 478 static int 479 om_cmp(const void *a, const void *b) 480 { 481 const struct ofw_map *mapa; 482 const struct ofw_map *mapb; 483 484 mapa = a; 485 mapb = b; 486 if (mapa->om_pa_hi < mapb->om_pa_hi) 487 return (-1); 488 else if (mapa->om_pa_hi > mapb->om_pa_hi) 489 return (1); 490 else if (mapa->om_pa_lo < mapb->om_pa_lo) 491 return (-1); 492 else if (mapa->om_pa_lo > mapb->om_pa_lo) 493 return (1); 494 else 495 return (0); 496 } 497 498 static void 499 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 500 { 501 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 502 register_t msr; 503 vm_offset_t off; 504 vm_paddr_t pa_base; 505 int i; 506 507 bzero(translations, sz); 508 if (OF_getprop(mmu, "translations", translations, sz) == -1) 509 panic("moea64_bootstrap: can't get ofw translations"); 510 511 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 512 sz /= sizeof(*translations); 513 qsort(translations, sz, sizeof (*translations), om_cmp); 514 515 for (i = 0; i < sz; i++) { 516 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 517 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 518 translations[i].om_len); 519 520 if (translations[i].om_pa_lo % PAGE_SIZE) 521 panic("OFW translation not page-aligned!"); 522 523 pa_base = translations[i].om_pa_lo; 524 525 #ifdef __powerpc64__ 526 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 527 #else 528 if (translations[i].om_pa_hi) 529 panic("OFW translations above 32-bit boundary!"); 530 #endif 531 532 /* Now enter the pages for this mapping */ 533 534 DISABLE_TRANS(msr); 535 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 536 if (moea64_pvo_find_va(kernel_pmap, 537 translations[i].om_va + off) != NULL) 538 continue; 539 540 moea64_kenter(mmup, translations[i].om_va + off, 541 pa_base + off); 542 } 543 ENABLE_TRANS(msr); 544 } 545 } 546 547 #ifdef __powerpc64__ 548 static void 549 moea64_probe_large_page(void) 550 { 551 uint16_t pvr = mfpvr() >> 16; 552 553 switch (pvr) { 554 case IBM970: 555 case IBM970FX: 556 case IBM970MP: 557 powerpc_sync(); isync(); 558 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 559 powerpc_sync(); isync(); 560 561 /* FALLTHROUGH */ 562 case IBMCELLBE: 563 moea64_large_page_size = 0x1000000; /* 16 MB */ 564 moea64_large_page_shift = 24; 565 break; 566 default: 567 moea64_large_page_size = 0; 568 } 569 570 moea64_large_page_mask = moea64_large_page_size - 1; 571 } 572 573 static void 574 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 575 { 576 struct slb *cache; 577 struct slb entry; 578 uint64_t esid, slbe; 579 uint64_t i; 580 581 cache = PCPU_GET(slb); 582 esid = va >> ADDR_SR_SHFT; 583 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 584 585 for (i = 0; i < 64; i++) { 586 if (cache[i].slbe == (slbe | i)) 587 return; 588 } 589 590 entry.slbe = slbe; 591 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 592 if (large) 593 entry.slbv |= SLBV_L; 594 595 slb_insert_kernel(entry.slbe, entry.slbv); 596 } 597 #endif 598 599 static void 600 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 601 vm_offset_t kernelend) 602 { 603 register_t msr; 604 vm_paddr_t pa; 605 vm_offset_t size, off; 606 uint64_t pte_lo; 607 int i; 608 609 if (moea64_large_page_size == 0) 610 hw_direct_map = 0; 611 612 DISABLE_TRANS(msr); 613 if (hw_direct_map) { 614 PMAP_LOCK(kernel_pmap); 615 for (i = 0; i < pregions_sz; i++) { 616 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 617 pregions[i].mr_size; pa += moea64_large_page_size) { 618 pte_lo = LPTE_M; 619 620 /* 621 * Set memory access as guarded if prefetch within 622 * the page could exit the available physmem area. 623 */ 624 if (pa & moea64_large_page_mask) { 625 pa &= moea64_large_page_mask; 626 pte_lo |= LPTE_G; 627 } 628 if (pa + moea64_large_page_size > 629 pregions[i].mr_start + pregions[i].mr_size) 630 pte_lo |= LPTE_G; 631 632 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 633 &moea64_pvo_kunmanaged, pa, pa, 634 pte_lo, PVO_WIRED | PVO_LARGE); 635 } 636 } 637 PMAP_UNLOCK(kernel_pmap); 638 } else { 639 size = sizeof(struct pvo_head) * moea64_pteg_count; 640 off = (vm_offset_t)(moea64_pvo_table); 641 for (pa = off; pa < off + size; pa += PAGE_SIZE) 642 moea64_kenter(mmup, pa, pa); 643 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 644 off = (vm_offset_t)(moea64_bpvo_pool); 645 for (pa = off; pa < off + size; pa += PAGE_SIZE) 646 moea64_kenter(mmup, pa, pa); 647 648 /* 649 * Map certain important things, like ourselves. 650 * 651 * NOTE: We do not map the exception vector space. That code is 652 * used only in real mode, and leaving it unmapped allows us to 653 * catch NULL pointer deferences, instead of making NULL a valid 654 * address. 655 */ 656 657 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 658 pa += PAGE_SIZE) 659 moea64_kenter(mmup, pa, pa); 660 } 661 ENABLE_TRANS(msr); 662 } 663 664 void 665 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 666 { 667 int i, j; 668 vm_size_t physsz, hwphyssz; 669 670 #ifndef __powerpc64__ 671 /* We don't have a direct map since there is no BAT */ 672 hw_direct_map = 0; 673 674 /* Make sure battable is zero, since we have no BAT */ 675 for (i = 0; i < 16; i++) { 676 battable[i].batu = 0; 677 battable[i].batl = 0; 678 } 679 #else 680 moea64_probe_large_page(); 681 682 /* Use a direct map if we have large page support */ 683 if (moea64_large_page_size > 0) 684 hw_direct_map = 1; 685 else 686 hw_direct_map = 0; 687 #endif 688 689 /* Get physical memory regions from firmware */ 690 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 691 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 692 693 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 694 panic("moea64_bootstrap: phys_avail too small"); 695 696 phys_avail_count = 0; 697 physsz = 0; 698 hwphyssz = 0; 699 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 700 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 701 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 702 regions[i].mr_start + regions[i].mr_size, 703 regions[i].mr_size); 704 if (hwphyssz != 0 && 705 (physsz + regions[i].mr_size) >= hwphyssz) { 706 if (physsz < hwphyssz) { 707 phys_avail[j] = regions[i].mr_start; 708 phys_avail[j + 1] = regions[i].mr_start + 709 hwphyssz - physsz; 710 physsz = hwphyssz; 711 phys_avail_count++; 712 } 713 break; 714 } 715 phys_avail[j] = regions[i].mr_start; 716 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 717 phys_avail_count++; 718 physsz += regions[i].mr_size; 719 } 720 721 /* Check for overlap with the kernel and exception vectors */ 722 for (j = 0; j < 2*phys_avail_count; j+=2) { 723 if (phys_avail[j] < EXC_LAST) 724 phys_avail[j] += EXC_LAST; 725 726 if (kernelstart >= phys_avail[j] && 727 kernelstart < phys_avail[j+1]) { 728 if (kernelend < phys_avail[j+1]) { 729 phys_avail[2*phys_avail_count] = 730 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 731 phys_avail[2*phys_avail_count + 1] = 732 phys_avail[j+1]; 733 phys_avail_count++; 734 } 735 736 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 737 } 738 739 if (kernelend >= phys_avail[j] && 740 kernelend < phys_avail[j+1]) { 741 if (kernelstart > phys_avail[j]) { 742 phys_avail[2*phys_avail_count] = phys_avail[j]; 743 phys_avail[2*phys_avail_count + 1] = 744 kernelstart & ~PAGE_MASK; 745 phys_avail_count++; 746 } 747 748 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 749 } 750 } 751 752 physmem = btoc(physsz); 753 754 #ifdef PTEGCOUNT 755 moea64_pteg_count = PTEGCOUNT; 756 #else 757 moea64_pteg_count = 0x1000; 758 759 while (moea64_pteg_count < physmem) 760 moea64_pteg_count <<= 1; 761 762 moea64_pteg_count >>= 1; 763 #endif /* PTEGCOUNT */ 764 } 765 766 void 767 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 768 { 769 vm_size_t size; 770 register_t msr; 771 int i; 772 773 /* 774 * Set PTEG mask 775 */ 776 moea64_pteg_mask = moea64_pteg_count - 1; 777 778 /* 779 * Allocate pv/overflow lists. 780 */ 781 size = sizeof(struct pvo_head) * moea64_pteg_count; 782 783 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 784 PAGE_SIZE); 785 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 786 787 DISABLE_TRANS(msr); 788 for (i = 0; i < moea64_pteg_count; i++) 789 LIST_INIT(&moea64_pvo_table[i]); 790 ENABLE_TRANS(msr); 791 792 /* 793 * Initialize the lock that synchronizes access to the pteg and pvo 794 * tables. 795 */ 796 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 797 MTX_RECURSE); 798 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 799 800 /* 801 * Initialise the unmanaged pvo pool. 802 */ 803 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 804 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 805 moea64_bpvo_pool_index = 0; 806 807 /* 808 * Make sure kernel vsid is allocated as well as VSID 0. 809 */ 810 #ifndef __powerpc64__ 811 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 812 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 813 moea64_vsid_bitmap[0] |= 1; 814 #endif 815 816 /* 817 * Initialize the kernel pmap (which is statically allocated). 818 */ 819 #ifdef __powerpc64__ 820 for (i = 0; i < 64; i++) { 821 pcpup->pc_slb[i].slbv = 0; 822 pcpup->pc_slb[i].slbe = 0; 823 } 824 #else 825 for (i = 0; i < 16; i++) 826 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 827 #endif 828 829 kernel_pmap->pmap_phys = kernel_pmap; 830 kernel_pmap->pm_active = ~0; 831 832 PMAP_LOCK_INIT(kernel_pmap); 833 834 /* 835 * Now map in all the other buffers we allocated earlier 836 */ 837 838 moea64_setup_direct_map(mmup, kernelstart, kernelend); 839 } 840 841 void 842 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 843 { 844 ihandle_t mmui; 845 phandle_t chosen; 846 phandle_t mmu; 847 size_t sz; 848 int i; 849 vm_offset_t pa, va; 850 void *dpcpu; 851 852 /* 853 * Set up the Open Firmware pmap and add its mappings if not in real 854 * mode. 855 */ 856 857 chosen = OF_finddevice("/chosen"); 858 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 859 mmu = OF_instance_to_package(mmui); 860 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 861 sz = 0; 862 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 863 panic("moea64_bootstrap: too many ofw translations"); 864 865 if (sz > 0) 866 moea64_add_ofw_mappings(mmup, mmu, sz); 867 } 868 869 /* 870 * Calculate the last available physical address. 871 */ 872 for (i = 0; phys_avail[i + 2] != 0; i += 2) 873 ; 874 Maxmem = powerpc_btop(phys_avail[i + 1]); 875 876 /* 877 * Initialize MMU and remap early physical mappings 878 */ 879 MMU_CPU_BOOTSTRAP(mmup,0); 880 mtmsr(mfmsr() | PSL_DR | PSL_IR); 881 pmap_bootstrapped++; 882 bs_remap_earlyboot(); 883 884 /* 885 * Set the start and end of kva. 886 */ 887 virtual_avail = VM_MIN_KERNEL_ADDRESS; 888 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 889 890 /* 891 * Map the entire KVA range into the SLB. We must not fault there. 892 */ 893 #ifdef __powerpc64__ 894 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 895 moea64_bootstrap_slb_prefault(va, 0); 896 #endif 897 898 /* 899 * Figure out how far we can extend virtual_end into segment 16 900 * without running into existing mappings. Segment 16 is guaranteed 901 * to contain neither RAM nor devices (at least on Apple hardware), 902 * but will generally contain some OFW mappings we should not 903 * step on. 904 */ 905 906 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 907 PMAP_LOCK(kernel_pmap); 908 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 909 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 910 virtual_end += PAGE_SIZE; 911 PMAP_UNLOCK(kernel_pmap); 912 #endif 913 914 /* 915 * Allocate a kernel stack with a guard page for thread0 and map it 916 * into the kernel page map. 917 */ 918 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 919 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 920 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 921 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 922 thread0.td_kstack = va; 923 thread0.td_kstack_pages = KSTACK_PAGES; 924 for (i = 0; i < KSTACK_PAGES; i++) { 925 moea64_kenter(mmup, va, pa); 926 pa += PAGE_SIZE; 927 va += PAGE_SIZE; 928 } 929 930 /* 931 * Allocate virtual address space for the message buffer. 932 */ 933 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 934 msgbufp = (struct msgbuf *)virtual_avail; 935 va = virtual_avail; 936 virtual_avail += round_page(msgbufsize); 937 while (va < virtual_avail) { 938 moea64_kenter(mmup, va, pa); 939 pa += PAGE_SIZE; 940 va += PAGE_SIZE; 941 } 942 943 /* 944 * Allocate virtual address space for the dynamic percpu area. 945 */ 946 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 947 dpcpu = (void *)virtual_avail; 948 va = virtual_avail; 949 virtual_avail += DPCPU_SIZE; 950 while (va < virtual_avail) { 951 moea64_kenter(mmup, va, pa); 952 pa += PAGE_SIZE; 953 va += PAGE_SIZE; 954 } 955 dpcpu_init(dpcpu, 0); 956 957 /* 958 * Allocate some things for page zeroing. We put this directly 959 * in the page table, marked with LPTE_LOCKED, to avoid any 960 * of the PVO book-keeping or other parts of the VM system 961 * from even knowing that this hack exists. 962 */ 963 964 if (!hw_direct_map) { 965 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 966 MTX_DEF); 967 for (i = 0; i < 2; i++) { 968 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 969 virtual_end -= PAGE_SIZE; 970 971 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 972 973 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 974 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 975 LOCK_TABLE(); 976 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 977 mmup, moea64_scratchpage_pvo[i]); 978 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 979 |= LPTE_LOCKED; 980 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 981 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 982 moea64_scratchpage_pvo[i]->pvo_vpn); 983 UNLOCK_TABLE(); 984 } 985 } 986 } 987 988 /* 989 * Activate a user pmap. The pmap must be activated before its address 990 * space can be accessed in any way. 991 */ 992 void 993 moea64_activate(mmu_t mmu, struct thread *td) 994 { 995 pmap_t pm; 996 997 pm = &td->td_proc->p_vmspace->vm_pmap; 998 pm->pm_active |= PCPU_GET(cpumask); 999 1000 #ifdef __powerpc64__ 1001 PCPU_SET(userslb, pm->pm_slb); 1002 #else 1003 PCPU_SET(curpmap, pm->pmap_phys); 1004 #endif 1005 } 1006 1007 void 1008 moea64_deactivate(mmu_t mmu, struct thread *td) 1009 { 1010 pmap_t pm; 1011 1012 pm = &td->td_proc->p_vmspace->vm_pmap; 1013 pm->pm_active &= ~(PCPU_GET(cpumask)); 1014 #ifdef __powerpc64__ 1015 PCPU_SET(userslb, NULL); 1016 #else 1017 PCPU_SET(curpmap, NULL); 1018 #endif 1019 } 1020 1021 void 1022 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1023 { 1024 struct pvo_entry *pvo; 1025 uintptr_t pt; 1026 uint64_t vsid; 1027 int i, ptegidx; 1028 1029 PMAP_LOCK(pm); 1030 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1031 1032 if (pvo != NULL) { 1033 LOCK_TABLE(); 1034 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1035 1036 if (wired) { 1037 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1038 pm->pm_stats.wired_count++; 1039 pvo->pvo_vaddr |= PVO_WIRED; 1040 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1041 } else { 1042 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1043 pm->pm_stats.wired_count--; 1044 pvo->pvo_vaddr &= ~PVO_WIRED; 1045 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1046 } 1047 1048 if (pt != -1) { 1049 /* Update wiring flag in page table. */ 1050 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1051 pvo->pvo_vpn); 1052 } else if (wired) { 1053 /* 1054 * If we are wiring the page, and it wasn't in the 1055 * page table before, add it. 1056 */ 1057 vsid = PVO_VSID(pvo); 1058 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1059 pvo->pvo_vaddr & PVO_LARGE); 1060 1061 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1062 1063 if (i >= 0) { 1064 PVO_PTEGIDX_CLR(pvo); 1065 PVO_PTEGIDX_SET(pvo, i); 1066 } 1067 } 1068 1069 UNLOCK_TABLE(); 1070 } 1071 PMAP_UNLOCK(pm); 1072 } 1073 1074 /* 1075 * This goes through and sets the physical address of our 1076 * special scratch PTE to the PA we want to zero or copy. Because 1077 * of locking issues (this can get called in pvo_enter() by 1078 * the UMA allocator), we can't use most other utility functions here 1079 */ 1080 1081 static __inline 1082 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1083 1084 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1085 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1086 1087 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1088 ~(LPTE_WIMG | LPTE_RPGN); 1089 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1090 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1091 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1092 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1093 moea64_scratchpage_pvo[which]->pvo_vpn); 1094 isync(); 1095 } 1096 1097 void 1098 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1099 { 1100 vm_offset_t dst; 1101 vm_offset_t src; 1102 1103 dst = VM_PAGE_TO_PHYS(mdst); 1104 src = VM_PAGE_TO_PHYS(msrc); 1105 1106 if (hw_direct_map) { 1107 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1108 } else { 1109 mtx_lock(&moea64_scratchpage_mtx); 1110 1111 moea64_set_scratchpage_pa(mmu, 0, src); 1112 moea64_set_scratchpage_pa(mmu, 1, dst); 1113 1114 kcopy((void *)moea64_scratchpage_va[0], 1115 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1116 1117 mtx_unlock(&moea64_scratchpage_mtx); 1118 } 1119 } 1120 1121 void 1122 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1123 { 1124 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1125 1126 if (size + off > PAGE_SIZE) 1127 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1128 1129 if (hw_direct_map) { 1130 bzero((caddr_t)pa + off, size); 1131 } else { 1132 mtx_lock(&moea64_scratchpage_mtx); 1133 moea64_set_scratchpage_pa(mmu, 0, pa); 1134 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1135 mtx_unlock(&moea64_scratchpage_mtx); 1136 } 1137 } 1138 1139 /* 1140 * Zero a page of physical memory by temporarily mapping it 1141 */ 1142 void 1143 moea64_zero_page(mmu_t mmu, vm_page_t m) 1144 { 1145 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1146 vm_offset_t va, off; 1147 1148 if (!hw_direct_map) { 1149 mtx_lock(&moea64_scratchpage_mtx); 1150 1151 moea64_set_scratchpage_pa(mmu, 0, pa); 1152 va = moea64_scratchpage_va[0]; 1153 } else { 1154 va = pa; 1155 } 1156 1157 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1158 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1159 1160 if (!hw_direct_map) 1161 mtx_unlock(&moea64_scratchpage_mtx); 1162 } 1163 1164 void 1165 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1166 { 1167 1168 moea64_zero_page(mmu, m); 1169 } 1170 1171 /* 1172 * Map the given physical page at the specified virtual address in the 1173 * target pmap with the protection requested. If specified the page 1174 * will be wired down. 1175 */ 1176 void 1177 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1178 vm_prot_t prot, boolean_t wired) 1179 { 1180 1181 vm_page_lock_queues(); 1182 PMAP_LOCK(pmap); 1183 moea64_enter_locked(mmu, pmap, va, m, prot, wired); 1184 vm_page_unlock_queues(); 1185 PMAP_UNLOCK(pmap); 1186 } 1187 1188 /* 1189 * Map the given physical page at the specified virtual address in the 1190 * target pmap with the protection requested. If specified the page 1191 * will be wired down. 1192 * 1193 * The page queues and pmap must be locked. 1194 */ 1195 1196 static void 1197 moea64_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1198 vm_prot_t prot, boolean_t wired) 1199 { 1200 struct pvo_head *pvo_head; 1201 uma_zone_t zone; 1202 vm_page_t pg; 1203 uint64_t pte_lo; 1204 u_int pvo_flags; 1205 int error; 1206 1207 if (!moea64_initialized) { 1208 pvo_head = &moea64_pvo_kunmanaged; 1209 pg = NULL; 1210 zone = moea64_upvo_zone; 1211 pvo_flags = 0; 1212 } else { 1213 pvo_head = vm_page_to_pvoh(m); 1214 pg = m; 1215 zone = moea64_mpvo_zone; 1216 pvo_flags = PVO_MANAGED; 1217 } 1218 1219 if (pmap_bootstrapped) 1220 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1221 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1222 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1223 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1224 ("moea64_enter_locked: page %p is not busy", m)); 1225 1226 /* XXX change the pvo head for fake pages */ 1227 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1228 pvo_flags &= ~PVO_MANAGED; 1229 pvo_head = &moea64_pvo_kunmanaged; 1230 zone = moea64_upvo_zone; 1231 } 1232 1233 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1234 1235 if (prot & VM_PROT_WRITE) { 1236 pte_lo |= LPTE_BW; 1237 if (pmap_bootstrapped && 1238 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1239 vm_page_flag_set(m, PG_WRITEABLE); 1240 } else 1241 pte_lo |= LPTE_BR; 1242 1243 if ((prot & VM_PROT_EXECUTE) == 0) 1244 pte_lo |= LPTE_NOEXEC; 1245 1246 if (wired) 1247 pvo_flags |= PVO_WIRED; 1248 1249 if ((m->flags & PG_FICTITIOUS) != 0) 1250 pvo_flags |= PVO_FAKE; 1251 1252 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1253 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1254 1255 /* 1256 * Flush the page from the instruction cache if this page is 1257 * mapped executable and cacheable. 1258 */ 1259 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) 1260 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1261 } 1262 1263 static void 1264 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1265 vm_size_t sz) 1266 { 1267 1268 /* 1269 * This is much trickier than on older systems because 1270 * we can't sync the icache on physical addresses directly 1271 * without a direct map. Instead we check a couple of cases 1272 * where the memory is already mapped in and, failing that, 1273 * use the same trick we use for page zeroing to create 1274 * a temporary mapping for this physical address. 1275 */ 1276 1277 if (!pmap_bootstrapped) { 1278 /* 1279 * If PMAP is not bootstrapped, we are likely to be 1280 * in real mode. 1281 */ 1282 __syncicache((void *)pa, sz); 1283 } else if (pmap == kernel_pmap) { 1284 __syncicache((void *)va, sz); 1285 } else if (hw_direct_map) { 1286 __syncicache((void *)pa, sz); 1287 } else { 1288 /* Use the scratch page to set up a temp mapping */ 1289 1290 mtx_lock(&moea64_scratchpage_mtx); 1291 1292 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1293 __syncicache((void *)(moea64_scratchpage_va[1] + 1294 (va & ADDR_POFF)), sz); 1295 1296 mtx_unlock(&moea64_scratchpage_mtx); 1297 } 1298 } 1299 1300 /* 1301 * Maps a sequence of resident pages belonging to the same object. 1302 * The sequence begins with the given page m_start. This page is 1303 * mapped at the given virtual address start. Each subsequent page is 1304 * mapped at a virtual address that is offset from start by the same 1305 * amount as the page is offset from m_start within the object. The 1306 * last page in the sequence is the page with the largest offset from 1307 * m_start that can be mapped at a virtual address less than the given 1308 * virtual address end. Not every virtual page between start and end 1309 * is mapped; only those for which a resident page exists with the 1310 * corresponding offset from m_start are mapped. 1311 */ 1312 void 1313 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1314 vm_page_t m_start, vm_prot_t prot) 1315 { 1316 vm_page_t m; 1317 vm_pindex_t diff, psize; 1318 1319 psize = atop(end - start); 1320 m = m_start; 1321 vm_page_lock_queues(); 1322 PMAP_LOCK(pm); 1323 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1324 moea64_enter_locked(mmu, pm, start + ptoa(diff), m, prot & 1325 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1326 m = TAILQ_NEXT(m, listq); 1327 } 1328 vm_page_unlock_queues(); 1329 PMAP_UNLOCK(pm); 1330 } 1331 1332 void 1333 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1334 vm_prot_t prot) 1335 { 1336 1337 vm_page_lock_queues(); 1338 PMAP_LOCK(pm); 1339 moea64_enter_locked(mmu, pm, va, m, 1340 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1341 vm_page_unlock_queues(); 1342 PMAP_UNLOCK(pm); 1343 } 1344 1345 vm_paddr_t 1346 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1347 { 1348 struct pvo_entry *pvo; 1349 vm_paddr_t pa; 1350 1351 PMAP_LOCK(pm); 1352 pvo = moea64_pvo_find_va(pm, va); 1353 if (pvo == NULL) 1354 pa = 0; 1355 else 1356 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1357 (va - PVO_VADDR(pvo)); 1358 PMAP_UNLOCK(pm); 1359 return (pa); 1360 } 1361 1362 /* 1363 * Atomically extract and hold the physical page with the given 1364 * pmap and virtual address pair if that mapping permits the given 1365 * protection. 1366 */ 1367 vm_page_t 1368 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1369 { 1370 struct pvo_entry *pvo; 1371 vm_page_t m; 1372 vm_paddr_t pa; 1373 1374 m = NULL; 1375 pa = 0; 1376 PMAP_LOCK(pmap); 1377 retry: 1378 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1379 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1380 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1381 (prot & VM_PROT_WRITE) == 0)) { 1382 if (vm_page_pa_tryrelock(pmap, 1383 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1384 goto retry; 1385 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1386 vm_page_hold(m); 1387 } 1388 PA_UNLOCK_COND(pa); 1389 PMAP_UNLOCK(pmap); 1390 return (m); 1391 } 1392 1393 static mmu_t installed_mmu; 1394 1395 static void * 1396 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1397 { 1398 /* 1399 * This entire routine is a horrible hack to avoid bothering kmem 1400 * for new KVA addresses. Because this can get called from inside 1401 * kmem allocation routines, calling kmem for a new address here 1402 * can lead to multiply locking non-recursive mutexes. 1403 */ 1404 static vm_pindex_t color; 1405 vm_offset_t va; 1406 1407 vm_page_t m; 1408 int pflags, needed_lock; 1409 1410 *flags = UMA_SLAB_PRIV; 1411 needed_lock = !PMAP_LOCKED(kernel_pmap); 1412 1413 if (needed_lock) 1414 PMAP_LOCK(kernel_pmap); 1415 1416 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1417 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1418 else 1419 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1420 if (wait & M_ZERO) 1421 pflags |= VM_ALLOC_ZERO; 1422 1423 for (;;) { 1424 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1425 if (m == NULL) { 1426 if (wait & M_NOWAIT) 1427 return (NULL); 1428 VM_WAIT; 1429 } else 1430 break; 1431 } 1432 1433 va = VM_PAGE_TO_PHYS(m); 1434 1435 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1436 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1437 PVO_WIRED | PVO_BOOTSTRAP); 1438 1439 if (needed_lock) 1440 PMAP_UNLOCK(kernel_pmap); 1441 1442 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1443 bzero((void *)va, PAGE_SIZE); 1444 1445 return (void *)va; 1446 } 1447 1448 void 1449 moea64_init(mmu_t mmu) 1450 { 1451 1452 CTR0(KTR_PMAP, "moea64_init"); 1453 1454 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1455 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1456 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1457 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1458 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1459 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1460 1461 if (!hw_direct_map) { 1462 installed_mmu = mmu; 1463 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1464 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1465 } 1466 1467 moea64_initialized = TRUE; 1468 } 1469 1470 boolean_t 1471 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1472 { 1473 1474 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1475 ("moea64_is_referenced: page %p is not managed", m)); 1476 return (moea64_query_bit(mmu, m, PTE_REF)); 1477 } 1478 1479 boolean_t 1480 moea64_is_modified(mmu_t mmu, vm_page_t m) 1481 { 1482 1483 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1484 ("moea64_is_modified: page %p is not managed", m)); 1485 1486 /* 1487 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1488 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1489 * is clear, no PTEs can have LPTE_CHG set. 1490 */ 1491 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1492 if ((m->oflags & VPO_BUSY) == 0 && 1493 (m->flags & PG_WRITEABLE) == 0) 1494 return (FALSE); 1495 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1496 } 1497 1498 boolean_t 1499 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1500 { 1501 struct pvo_entry *pvo; 1502 boolean_t rv; 1503 1504 PMAP_LOCK(pmap); 1505 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1506 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1507 PMAP_UNLOCK(pmap); 1508 return (rv); 1509 } 1510 1511 void 1512 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1513 { 1514 1515 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1516 ("moea64_clear_reference: page %p is not managed", m)); 1517 moea64_clear_bit(mmu, m, LPTE_REF); 1518 } 1519 1520 void 1521 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1522 { 1523 1524 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1525 ("moea64_clear_modify: page %p is not managed", m)); 1526 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1527 KASSERT((m->oflags & VPO_BUSY) == 0, 1528 ("moea64_clear_modify: page %p is busy", m)); 1529 1530 /* 1531 * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1532 * set. If the object containing the page is locked and the page is 1533 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1534 */ 1535 if ((m->flags & PG_WRITEABLE) == 0) 1536 return; 1537 moea64_clear_bit(mmu, m, LPTE_CHG); 1538 } 1539 1540 /* 1541 * Clear the write and modified bits in each of the given page's mappings. 1542 */ 1543 void 1544 moea64_remove_write(mmu_t mmu, vm_page_t m) 1545 { 1546 struct pvo_entry *pvo; 1547 uintptr_t pt; 1548 pmap_t pmap; 1549 uint64_t lo; 1550 1551 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1552 ("moea64_remove_write: page %p is not managed", m)); 1553 1554 /* 1555 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1556 * another thread while the object is locked. Thus, if PG_WRITEABLE 1557 * is clear, no page table entries need updating. 1558 */ 1559 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1560 if ((m->oflags & VPO_BUSY) == 0 && 1561 (m->flags & PG_WRITEABLE) == 0) 1562 return; 1563 vm_page_lock_queues(); 1564 lo = moea64_attr_fetch(m); 1565 powerpc_sync(); 1566 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1567 pmap = pvo->pvo_pmap; 1568 PMAP_LOCK(pmap); 1569 LOCK_TABLE(); 1570 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1571 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1572 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1573 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1574 if (pt != -1) { 1575 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1576 lo |= pvo->pvo_pte.lpte.pte_lo; 1577 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1578 MOEA64_PTE_CHANGE(mmu, pt, 1579 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1580 if (pvo->pvo_pmap == kernel_pmap) 1581 isync(); 1582 } 1583 } 1584 UNLOCK_TABLE(); 1585 PMAP_UNLOCK(pmap); 1586 } 1587 if ((lo & LPTE_CHG) != 0) { 1588 moea64_attr_clear(m, LPTE_CHG); 1589 vm_page_dirty(m); 1590 } 1591 vm_page_flag_clear(m, PG_WRITEABLE); 1592 vm_page_unlock_queues(); 1593 } 1594 1595 /* 1596 * moea64_ts_referenced: 1597 * 1598 * Return a count of reference bits for a page, clearing those bits. 1599 * It is not necessary for every reference bit to be cleared, but it 1600 * is necessary that 0 only be returned when there are truly no 1601 * reference bits set. 1602 * 1603 * XXX: The exact number of bits to check and clear is a matter that 1604 * should be tested and standardized at some point in the future for 1605 * optimal aging of shared pages. 1606 */ 1607 boolean_t 1608 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1609 { 1610 1611 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1612 ("moea64_ts_referenced: page %p is not managed", m)); 1613 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1614 } 1615 1616 /* 1617 * Modify the WIMG settings of all mappings for a page. 1618 */ 1619 void 1620 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1621 { 1622 struct pvo_entry *pvo; 1623 struct pvo_head *pvo_head; 1624 uintptr_t pt; 1625 pmap_t pmap; 1626 uint64_t lo; 1627 1628 if (m->flags & PG_FICTITIOUS) { 1629 m->md.mdpg_cache_attrs = ma; 1630 return; 1631 } 1632 1633 vm_page_lock_queues(); 1634 pvo_head = vm_page_to_pvoh(m); 1635 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1636 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1637 pmap = pvo->pvo_pmap; 1638 PMAP_LOCK(pmap); 1639 LOCK_TABLE(); 1640 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1641 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1642 pvo->pvo_pte.lpte.pte_lo |= lo; 1643 if (pt != -1) { 1644 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1645 pvo->pvo_vpn); 1646 if (pvo->pvo_pmap == kernel_pmap) 1647 isync(); 1648 } 1649 UNLOCK_TABLE(); 1650 PMAP_UNLOCK(pmap); 1651 } 1652 m->md.mdpg_cache_attrs = ma; 1653 vm_page_unlock_queues(); 1654 } 1655 1656 /* 1657 * Map a wired page into kernel virtual address space. 1658 */ 1659 void 1660 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1661 { 1662 uint64_t pte_lo; 1663 int error; 1664 1665 pte_lo = moea64_calc_wimg(pa, ma); 1666 1667 PMAP_LOCK(kernel_pmap); 1668 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1669 &moea64_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1670 1671 if (error != 0 && error != ENOENT) 1672 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1673 pa, error); 1674 1675 /* 1676 * Flush the memory from the instruction cache. 1677 */ 1678 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) 1679 __syncicache((void *)va, PAGE_SIZE); 1680 PMAP_UNLOCK(kernel_pmap); 1681 } 1682 1683 void 1684 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1685 { 1686 1687 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1688 } 1689 1690 /* 1691 * Extract the physical page address associated with the given kernel virtual 1692 * address. 1693 */ 1694 vm_offset_t 1695 moea64_kextract(mmu_t mmu, vm_offset_t va) 1696 { 1697 struct pvo_entry *pvo; 1698 vm_paddr_t pa; 1699 1700 /* 1701 * Shortcut the direct-mapped case when applicable. We never put 1702 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1703 */ 1704 if (va < VM_MIN_KERNEL_ADDRESS) 1705 return (va); 1706 1707 PMAP_LOCK(kernel_pmap); 1708 pvo = moea64_pvo_find_va(kernel_pmap, va); 1709 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1710 va)); 1711 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) + (va - PVO_VADDR(pvo)); 1712 PMAP_UNLOCK(kernel_pmap); 1713 return (pa); 1714 } 1715 1716 /* 1717 * Remove a wired page from kernel virtual address space. 1718 */ 1719 void 1720 moea64_kremove(mmu_t mmu, vm_offset_t va) 1721 { 1722 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1723 } 1724 1725 /* 1726 * Map a range of physical addresses into kernel virtual address space. 1727 * 1728 * The value passed in *virt is a suggested virtual address for the mapping. 1729 * Architectures which can support a direct-mapped physical to virtual region 1730 * can return the appropriate address within that region, leaving '*virt' 1731 * unchanged. We cannot and therefore do not; *virt is updated with the 1732 * first usable address after the mapped region. 1733 */ 1734 vm_offset_t 1735 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1736 vm_offset_t pa_end, int prot) 1737 { 1738 vm_offset_t sva, va; 1739 1740 sva = *virt; 1741 va = sva; 1742 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1743 moea64_kenter(mmu, va, pa_start); 1744 *virt = va; 1745 1746 return (sva); 1747 } 1748 1749 /* 1750 * Returns true if the pmap's pv is one of the first 1751 * 16 pvs linked to from this page. This count may 1752 * be changed upwards or downwards in the future; it 1753 * is only necessary that true be returned for a small 1754 * subset of pmaps for proper page aging. 1755 */ 1756 boolean_t 1757 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1758 { 1759 int loops; 1760 struct pvo_entry *pvo; 1761 boolean_t rv; 1762 1763 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1764 ("moea64_page_exists_quick: page %p is not managed", m)); 1765 loops = 0; 1766 rv = FALSE; 1767 vm_page_lock_queues(); 1768 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1769 if (pvo->pvo_pmap == pmap) { 1770 rv = TRUE; 1771 break; 1772 } 1773 if (++loops >= 16) 1774 break; 1775 } 1776 vm_page_unlock_queues(); 1777 return (rv); 1778 } 1779 1780 /* 1781 * Return the number of managed mappings to the given physical page 1782 * that are wired. 1783 */ 1784 int 1785 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1786 { 1787 struct pvo_entry *pvo; 1788 int count; 1789 1790 count = 0; 1791 if ((m->flags & PG_FICTITIOUS) != 0) 1792 return (count); 1793 vm_page_lock_queues(); 1794 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1795 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1796 count++; 1797 vm_page_unlock_queues(); 1798 return (count); 1799 } 1800 1801 static uintptr_t moea64_vsidcontext; 1802 1803 uintptr_t 1804 moea64_get_unique_vsid(void) { 1805 u_int entropy; 1806 register_t hash; 1807 uint32_t mask; 1808 int i; 1809 1810 entropy = 0; 1811 __asm __volatile("mftb %0" : "=r"(entropy)); 1812 1813 mtx_lock(&moea64_slb_mutex); 1814 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1815 u_int n; 1816 1817 /* 1818 * Create a new value by mutiplying by a prime and adding in 1819 * entropy from the timebase register. This is to make the 1820 * VSID more random so that the PT hash function collides 1821 * less often. (Note that the prime casues gcc to do shifts 1822 * instead of a multiply.) 1823 */ 1824 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1825 hash = moea64_vsidcontext & (NVSIDS - 1); 1826 if (hash == 0) /* 0 is special, avoid it */ 1827 continue; 1828 n = hash >> 5; 1829 mask = 1 << (hash & (VSID_NBPW - 1)); 1830 hash = (moea64_vsidcontext & VSID_HASHMASK); 1831 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1832 /* anything free in this bucket? */ 1833 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1834 entropy = (moea64_vsidcontext >> 20); 1835 continue; 1836 } 1837 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1838 mask = 1 << i; 1839 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1840 hash |= i; 1841 } 1842 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1843 ("Allocating in-use VSID %#zx\n", hash)); 1844 moea64_vsid_bitmap[n] |= mask; 1845 mtx_unlock(&moea64_slb_mutex); 1846 return (hash); 1847 } 1848 1849 mtx_unlock(&moea64_slb_mutex); 1850 panic("%s: out of segments",__func__); 1851 } 1852 1853 #ifdef __powerpc64__ 1854 void 1855 moea64_pinit(mmu_t mmu, pmap_t pmap) 1856 { 1857 PMAP_LOCK_INIT(pmap); 1858 1859 pmap->pm_slb_tree_root = slb_alloc_tree(); 1860 pmap->pm_slb = slb_alloc_user_cache(); 1861 pmap->pm_slb_len = 0; 1862 } 1863 #else 1864 void 1865 moea64_pinit(mmu_t mmu, pmap_t pmap) 1866 { 1867 int i; 1868 uint32_t hash; 1869 1870 PMAP_LOCK_INIT(pmap); 1871 1872 if (pmap_bootstrapped) 1873 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1874 (vm_offset_t)pmap); 1875 else 1876 pmap->pmap_phys = pmap; 1877 1878 /* 1879 * Allocate some segment registers for this pmap. 1880 */ 1881 hash = moea64_get_unique_vsid(); 1882 1883 for (i = 0; i < 16; i++) 1884 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1885 1886 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1887 } 1888 #endif 1889 1890 /* 1891 * Initialize the pmap associated with process 0. 1892 */ 1893 void 1894 moea64_pinit0(mmu_t mmu, pmap_t pm) 1895 { 1896 moea64_pinit(mmu, pm); 1897 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1898 } 1899 1900 /* 1901 * Set the physical protection on the specified range of this map as requested. 1902 */ 1903 void 1904 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1905 vm_prot_t prot) 1906 { 1907 struct pvo_entry *pvo; 1908 uintptr_t pt; 1909 1910 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1911 eva, prot); 1912 1913 1914 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1915 ("moea64_protect: non current pmap")); 1916 1917 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1918 moea64_remove(mmu, pm, sva, eva); 1919 return; 1920 } 1921 1922 vm_page_lock_queues(); 1923 PMAP_LOCK(pm); 1924 for (; sva < eva; sva += PAGE_SIZE) { 1925 pvo = moea64_pvo_find_va(pm, sva); 1926 if (pvo == NULL) 1927 continue; 1928 1929 /* 1930 * Grab the PTE pointer before we diddle with the cached PTE 1931 * copy. 1932 */ 1933 LOCK_TABLE(); 1934 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1935 1936 /* 1937 * Change the protection of the page. 1938 */ 1939 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1940 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1941 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1942 if ((prot & VM_PROT_EXECUTE) == 0) 1943 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1944 1945 /* 1946 * If the PVO is in the page table, update that pte as well. 1947 */ 1948 if (pt != -1) { 1949 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1950 pvo->pvo_vpn); 1951 if ((pvo->pvo_pte.lpte.pte_lo & 1952 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1953 moea64_syncicache(mmu, pm, sva, 1954 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1955 PAGE_SIZE); 1956 } 1957 } 1958 UNLOCK_TABLE(); 1959 } 1960 vm_page_unlock_queues(); 1961 PMAP_UNLOCK(pm); 1962 } 1963 1964 /* 1965 * Map a list of wired pages into kernel virtual address space. This is 1966 * intended for temporary mappings which do not need page modification or 1967 * references recorded. Existing mappings in the region are overwritten. 1968 */ 1969 void 1970 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1971 { 1972 while (count-- > 0) { 1973 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1974 va += PAGE_SIZE; 1975 m++; 1976 } 1977 } 1978 1979 /* 1980 * Remove page mappings from kernel virtual address space. Intended for 1981 * temporary mappings entered by moea64_qenter. 1982 */ 1983 void 1984 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1985 { 1986 while (count-- > 0) { 1987 moea64_kremove(mmu, va); 1988 va += PAGE_SIZE; 1989 } 1990 } 1991 1992 void 1993 moea64_release_vsid(uint64_t vsid) 1994 { 1995 int idx, mask; 1996 1997 mtx_lock(&moea64_slb_mutex); 1998 idx = vsid & (NVSIDS-1); 1999 mask = 1 << (idx % VSID_NBPW); 2000 idx /= VSID_NBPW; 2001 KASSERT(moea64_vsid_bitmap[idx] & mask, 2002 ("Freeing unallocated VSID %#jx", vsid)); 2003 moea64_vsid_bitmap[idx] &= ~mask; 2004 mtx_unlock(&moea64_slb_mutex); 2005 } 2006 2007 2008 void 2009 moea64_release(mmu_t mmu, pmap_t pmap) 2010 { 2011 2012 /* 2013 * Free segment registers' VSIDs 2014 */ 2015 #ifdef __powerpc64__ 2016 slb_free_tree(pmap); 2017 slb_free_user_cache(pmap->pm_slb); 2018 #else 2019 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2020 2021 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2022 #endif 2023 2024 PMAP_LOCK_DESTROY(pmap); 2025 } 2026 2027 /* 2028 * Remove the given range of addresses from the specified map. 2029 */ 2030 void 2031 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2032 { 2033 struct pvo_entry *pvo; 2034 2035 vm_page_lock_queues(); 2036 PMAP_LOCK(pm); 2037 for (; sva < eva; sva += PAGE_SIZE) { 2038 pvo = moea64_pvo_find_va(pm, sva); 2039 if (pvo != NULL) 2040 moea64_pvo_remove(mmu, pvo); 2041 } 2042 vm_page_unlock_queues(); 2043 PMAP_UNLOCK(pm); 2044 } 2045 2046 /* 2047 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2048 * will reflect changes in pte's back to the vm_page. 2049 */ 2050 void 2051 moea64_remove_all(mmu_t mmu, vm_page_t m) 2052 { 2053 struct pvo_head *pvo_head; 2054 struct pvo_entry *pvo, *next_pvo; 2055 pmap_t pmap; 2056 2057 vm_page_lock_queues(); 2058 pvo_head = vm_page_to_pvoh(m); 2059 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 2060 next_pvo = LIST_NEXT(pvo, pvo_vlink); 2061 2062 pmap = pvo->pvo_pmap; 2063 PMAP_LOCK(pmap); 2064 moea64_pvo_remove(mmu, pvo); 2065 PMAP_UNLOCK(pmap); 2066 } 2067 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 2068 moea64_attr_clear(m, LPTE_CHG); 2069 vm_page_dirty(m); 2070 } 2071 vm_page_flag_clear(m, PG_WRITEABLE); 2072 vm_page_unlock_queues(); 2073 } 2074 2075 /* 2076 * Allocate a physical page of memory directly from the phys_avail map. 2077 * Can only be called from moea64_bootstrap before avail start and end are 2078 * calculated. 2079 */ 2080 vm_offset_t 2081 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2082 { 2083 vm_offset_t s, e; 2084 int i, j; 2085 2086 size = round_page(size); 2087 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2088 if (align != 0) 2089 s = (phys_avail[i] + align - 1) & ~(align - 1); 2090 else 2091 s = phys_avail[i]; 2092 e = s + size; 2093 2094 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2095 continue; 2096 2097 if (s + size > platform_real_maxaddr()) 2098 continue; 2099 2100 if (s == phys_avail[i]) { 2101 phys_avail[i] += size; 2102 } else if (e == phys_avail[i + 1]) { 2103 phys_avail[i + 1] -= size; 2104 } else { 2105 for (j = phys_avail_count * 2; j > i; j -= 2) { 2106 phys_avail[j] = phys_avail[j - 2]; 2107 phys_avail[j + 1] = phys_avail[j - 1]; 2108 } 2109 2110 phys_avail[i + 3] = phys_avail[i + 1]; 2111 phys_avail[i + 1] = s; 2112 phys_avail[i + 2] = e; 2113 phys_avail_count++; 2114 } 2115 2116 return (s); 2117 } 2118 panic("moea64_bootstrap_alloc: could not allocate memory"); 2119 } 2120 2121 static int 2122 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2123 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2124 uint64_t pte_lo, int flags) 2125 { 2126 struct pvo_entry *pvo; 2127 uint64_t vsid; 2128 int first; 2129 u_int ptegidx; 2130 int i; 2131 int bootstrap; 2132 2133 /* 2134 * One nasty thing that can happen here is that the UMA calls to 2135 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2136 * which calls UMA... 2137 * 2138 * We break the loop by detecting recursion and allocating out of 2139 * the bootstrap pool. 2140 */ 2141 2142 first = 0; 2143 bootstrap = (flags & PVO_BOOTSTRAP); 2144 2145 if (!moea64_initialized) 2146 bootstrap = 1; 2147 2148 /* 2149 * Compute the PTE Group index. 2150 */ 2151 va &= ~ADDR_POFF; 2152 vsid = va_to_vsid(pm, va); 2153 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2154 2155 /* 2156 * Remove any existing mapping for this page. Reuse the pvo entry if 2157 * there is a mapping. 2158 */ 2159 LOCK_TABLE(); 2160 2161 moea64_pvo_enter_calls++; 2162 2163 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2164 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2165 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2166 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2167 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2168 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2169 /* Re-insert if spilled */ 2170 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2171 &pvo->pvo_pte.lpte); 2172 if (i >= 0) 2173 PVO_PTEGIDX_SET(pvo, i); 2174 moea64_pte_overflow--; 2175 } 2176 UNLOCK_TABLE(); 2177 return (0); 2178 } 2179 moea64_pvo_remove(mmu, pvo); 2180 break; 2181 } 2182 } 2183 2184 /* 2185 * If we aren't overwriting a mapping, try to allocate. 2186 */ 2187 if (bootstrap) { 2188 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2189 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2190 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2191 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2192 } 2193 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2194 moea64_bpvo_pool_index++; 2195 bootstrap = 1; 2196 } else { 2197 /* 2198 * Note: drop the table lock around the UMA allocation in 2199 * case the UMA allocator needs to manipulate the page 2200 * table. The mapping we are working with is already 2201 * protected by the PMAP lock. 2202 */ 2203 UNLOCK_TABLE(); 2204 pvo = uma_zalloc(zone, M_NOWAIT); 2205 LOCK_TABLE(); 2206 } 2207 2208 if (pvo == NULL) { 2209 UNLOCK_TABLE(); 2210 return (ENOMEM); 2211 } 2212 2213 moea64_pvo_entries++; 2214 pvo->pvo_vaddr = va; 2215 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2216 | (vsid << 16); 2217 pvo->pvo_pmap = pm; 2218 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2219 pvo->pvo_vaddr &= ~ADDR_POFF; 2220 2221 if (flags & PVO_WIRED) 2222 pvo->pvo_vaddr |= PVO_WIRED; 2223 if (pvo_head != &moea64_pvo_kunmanaged) 2224 pvo->pvo_vaddr |= PVO_MANAGED; 2225 if (bootstrap) 2226 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2227 if (flags & PVO_FAKE) 2228 pvo->pvo_vaddr |= PVO_FAKE; 2229 if (flags & PVO_LARGE) 2230 pvo->pvo_vaddr |= PVO_LARGE; 2231 2232 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2233 (uint64_t)(pa) | pte_lo, flags); 2234 2235 /* 2236 * Remember if the list was empty and therefore will be the first 2237 * item. 2238 */ 2239 if (LIST_FIRST(pvo_head) == NULL) 2240 first = 1; 2241 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2242 2243 if (pvo->pvo_vaddr & PVO_WIRED) { 2244 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2245 pm->pm_stats.wired_count++; 2246 } 2247 pm->pm_stats.resident_count++; 2248 2249 /* 2250 * We hope this succeeds but it isn't required. 2251 */ 2252 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2253 if (i >= 0) { 2254 PVO_PTEGIDX_SET(pvo, i); 2255 } else { 2256 panic("moea64_pvo_enter: overflow"); 2257 moea64_pte_overflow++; 2258 } 2259 2260 if (pm == kernel_pmap) 2261 isync(); 2262 2263 UNLOCK_TABLE(); 2264 2265 #ifdef __powerpc64__ 2266 /* 2267 * Make sure all our bootstrap mappings are in the SLB as soon 2268 * as virtual memory is switched on. 2269 */ 2270 if (!pmap_bootstrapped) 2271 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2272 #endif 2273 2274 return (first ? ENOENT : 0); 2275 } 2276 2277 static void 2278 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2279 { 2280 uintptr_t pt; 2281 2282 /* 2283 * If there is an active pte entry, we need to deactivate it (and 2284 * save the ref & cfg bits). 2285 */ 2286 LOCK_TABLE(); 2287 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2288 if (pt != -1) { 2289 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2290 PVO_PTEGIDX_CLR(pvo); 2291 } else { 2292 moea64_pte_overflow--; 2293 } 2294 2295 /* 2296 * Update our statistics. 2297 */ 2298 pvo->pvo_pmap->pm_stats.resident_count--; 2299 if (pvo->pvo_vaddr & PVO_WIRED) 2300 pvo->pvo_pmap->pm_stats.wired_count--; 2301 2302 /* 2303 * Save the REF/CHG bits into their cache if the page is managed. 2304 */ 2305 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2306 struct vm_page *pg; 2307 2308 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2309 if (pg != NULL) { 2310 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2311 (LPTE_REF | LPTE_CHG)); 2312 } 2313 } 2314 2315 /* 2316 * Remove this PVO from the PV list. 2317 */ 2318 LIST_REMOVE(pvo, pvo_vlink); 2319 2320 /* 2321 * Remove this from the overflow list and return it to the pool 2322 * if we aren't going to reuse it. 2323 */ 2324 LIST_REMOVE(pvo, pvo_olink); 2325 2326 moea64_pvo_entries--; 2327 moea64_pvo_remove_calls++; 2328 2329 UNLOCK_TABLE(); 2330 2331 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2332 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2333 moea64_upvo_zone, pvo); 2334 } 2335 2336 static struct pvo_entry * 2337 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2338 { 2339 struct pvo_entry *pvo; 2340 int ptegidx; 2341 uint64_t vsid; 2342 #ifdef __powerpc64__ 2343 uint64_t slbv; 2344 2345 if (pm == kernel_pmap) { 2346 slbv = kernel_va_to_slbv(va); 2347 } else { 2348 struct slb *slb; 2349 slb = user_va_to_slb_entry(pm, va); 2350 /* The page is not mapped if the segment isn't */ 2351 if (slb == NULL) 2352 return NULL; 2353 slbv = slb->slbv; 2354 } 2355 2356 vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2357 if (slbv & SLBV_L) 2358 va &= ~moea64_large_page_mask; 2359 else 2360 va &= ~ADDR_POFF; 2361 ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L); 2362 #else 2363 va &= ~ADDR_POFF; 2364 vsid = va_to_vsid(pm, va); 2365 ptegidx = va_to_pteg(vsid, va, 0); 2366 #endif 2367 2368 LOCK_TABLE(); 2369 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2370 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2371 break; 2372 } 2373 UNLOCK_TABLE(); 2374 2375 return (pvo); 2376 } 2377 2378 static boolean_t 2379 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2380 { 2381 struct pvo_entry *pvo; 2382 uintptr_t pt; 2383 2384 if (moea64_attr_fetch(m) & ptebit) 2385 return (TRUE); 2386 2387 vm_page_lock_queues(); 2388 2389 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2390 2391 /* 2392 * See if we saved the bit off. If so, cache it and return 2393 * success. 2394 */ 2395 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2396 moea64_attr_save(m, ptebit); 2397 vm_page_unlock_queues(); 2398 return (TRUE); 2399 } 2400 } 2401 2402 /* 2403 * No luck, now go through the hard part of looking at the PTEs 2404 * themselves. Sync so that any pending REF/CHG bits are flushed to 2405 * the PTEs. 2406 */ 2407 powerpc_sync(); 2408 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2409 2410 /* 2411 * See if this pvo has a valid PTE. if so, fetch the 2412 * REF/CHG bits from the valid PTE. If the appropriate 2413 * ptebit is set, cache it and return success. 2414 */ 2415 LOCK_TABLE(); 2416 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2417 if (pt != -1) { 2418 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2419 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2420 UNLOCK_TABLE(); 2421 2422 moea64_attr_save(m, ptebit); 2423 vm_page_unlock_queues(); 2424 return (TRUE); 2425 } 2426 } 2427 UNLOCK_TABLE(); 2428 } 2429 2430 vm_page_unlock_queues(); 2431 return (FALSE); 2432 } 2433 2434 static u_int 2435 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2436 { 2437 u_int count; 2438 struct pvo_entry *pvo; 2439 uintptr_t pt; 2440 2441 vm_page_lock_queues(); 2442 2443 /* 2444 * Clear the cached value. 2445 */ 2446 moea64_attr_clear(m, ptebit); 2447 2448 /* 2449 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2450 * we can reset the right ones). note that since the pvo entries and 2451 * list heads are accessed via BAT0 and are never placed in the page 2452 * table, we don't have to worry about further accesses setting the 2453 * REF/CHG bits. 2454 */ 2455 powerpc_sync(); 2456 2457 /* 2458 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2459 * valid pte clear the ptebit from the valid pte. 2460 */ 2461 count = 0; 2462 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2463 2464 LOCK_TABLE(); 2465 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2466 if (pt != -1) { 2467 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2468 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2469 count++; 2470 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2471 pvo->pvo_vpn, ptebit); 2472 } 2473 } 2474 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2475 UNLOCK_TABLE(); 2476 } 2477 2478 vm_page_unlock_queues(); 2479 return (count); 2480 } 2481 2482 boolean_t 2483 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2484 { 2485 struct pvo_entry *pvo; 2486 vm_offset_t ppa; 2487 int error = 0; 2488 2489 PMAP_LOCK(kernel_pmap); 2490 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2491 pvo = moea64_pvo_find_va(kernel_pmap, ppa); 2492 if (pvo == NULL || 2493 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2494 error = EFAULT; 2495 break; 2496 } 2497 } 2498 PMAP_UNLOCK(kernel_pmap); 2499 2500 return (error); 2501 } 2502 2503 /* 2504 * Map a set of physical memory pages into the kernel virtual 2505 * address space. Return a pointer to where it is mapped. This 2506 * routine is intended to be used for mapping device memory, 2507 * NOT real memory. 2508 */ 2509 void * 2510 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2511 { 2512 vm_offset_t va, tmpva, ppa, offset; 2513 2514 ppa = trunc_page(pa); 2515 offset = pa & PAGE_MASK; 2516 size = roundup(offset + size, PAGE_SIZE); 2517 2518 va = kmem_alloc_nofault(kernel_map, size); 2519 2520 if (!va) 2521 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2522 2523 for (tmpva = va; size > 0;) { 2524 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2525 size -= PAGE_SIZE; 2526 tmpva += PAGE_SIZE; 2527 ppa += PAGE_SIZE; 2528 } 2529 2530 return ((void *)(va + offset)); 2531 } 2532 2533 void * 2534 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2535 { 2536 2537 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2538 } 2539 2540 void 2541 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2542 { 2543 vm_offset_t base, offset; 2544 2545 base = trunc_page(va); 2546 offset = va & PAGE_MASK; 2547 size = roundup(offset + size, PAGE_SIZE); 2548 2549 kmem_free(kernel_map, base, size); 2550 } 2551 2552 void 2553 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2554 { 2555 struct pvo_entry *pvo; 2556 vm_offset_t lim; 2557 vm_paddr_t pa; 2558 vm_size_t len; 2559 2560 PMAP_LOCK(pm); 2561 while (sz > 0) { 2562 lim = round_page(va); 2563 len = MIN(lim - va, sz); 2564 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2565 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2566 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2567 (va & ADDR_POFF); 2568 moea64_syncicache(mmu, pm, va, pa, len); 2569 } 2570 va += len; 2571 sz -= len; 2572 } 2573 PMAP_UNLOCK(pm); 2574 } 2575