1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 #include <sys/reboot.h> 69 70 #include <sys/kdb.h> 71 72 #include <dev/ofw/openfirm.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_kern.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_phys.h> 79 #include <vm/vm_map.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_extern.h> 82 #include <vm/vm_pageout.h> 83 #include <vm/uma.h> 84 85 #include <machine/_inttypes.h> 86 #include <machine/cpu.h> 87 #include <machine/platform.h> 88 #include <machine/frame.h> 89 #include <machine/md_var.h> 90 #include <machine/psl.h> 91 #include <machine/bat.h> 92 #include <machine/hid.h> 93 #include <machine/pte.h> 94 #include <machine/sr.h> 95 #include <machine/trap.h> 96 #include <machine/mmuvar.h> 97 98 #include "mmu_oea64.h" 99 #include "mmu_if.h" 100 #include "moea64_if.h" 101 102 void moea64_release_vsid(uint64_t vsid); 103 uintptr_t moea64_get_unique_vsid(void); 104 105 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 106 #define ENABLE_TRANS(msr) mtmsr(msr) 107 108 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 109 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 110 #define VSID_HASH_MASK 0x0000007fffffffffULL 111 112 /* 113 * Locking semantics: 114 * 115 * There are two locks of interest: the page locks and the pmap locks, which 116 * protect their individual PVO lists and are locked in that order. The contents 117 * of all PVO entries are protected by the locks of their respective pmaps. 118 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 119 * into any list. 120 * 121 */ 122 123 #define PV_LOCK_PER_DOM (PA_LOCK_COUNT * 3) 124 #define PV_LOCK_COUNT (PV_LOCK_PER_DOM * MAXMEMDOM) 125 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 126 127 /* 128 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 129 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 130 * index at (N << 45). 131 */ 132 #ifdef __powerpc64__ 133 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 134 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 135 #else 136 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 137 #endif 138 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 139 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 140 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 141 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 142 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 144 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 145 146 struct ofw_map { 147 cell_t om_va; 148 cell_t om_len; 149 uint64_t om_pa; 150 cell_t om_mode; 151 }; 152 153 extern unsigned char _etext[]; 154 extern unsigned char _end[]; 155 156 extern void *slbtrap, *slbtrapend; 157 158 /* 159 * Map of physical memory regions. 160 */ 161 static struct mem_region *regions; 162 static struct mem_region *pregions; 163 static struct numa_mem_region *numa_pregions; 164 static u_int phys_avail_count; 165 static int regions_sz, pregions_sz, numapregions_sz; 166 167 extern void bs_remap_earlyboot(void); 168 169 /* 170 * Lock for the SLB tables. 171 */ 172 struct mtx moea64_slb_mutex; 173 174 /* 175 * PTEG data. 176 */ 177 u_long moea64_pteg_count; 178 u_long moea64_pteg_mask; 179 180 /* 181 * PVO data. 182 */ 183 184 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 185 186 static struct pvo_entry *moea64_bpvo_pool; 187 static int moea64_bpvo_pool_index = 0; 188 static int moea64_bpvo_pool_size = 0; 189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 190 &moea64_bpvo_pool_index, 0, ""); 191 192 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */ 193 #define BPVO_POOL_EXPANSION_FACTOR 3 194 #define VSID_NBPW (sizeof(u_int32_t) * 8) 195 #ifdef __powerpc64__ 196 #define NVSIDS (NPMAPS * 16) 197 #define VSID_HASHMASK 0xffffffffUL 198 #else 199 #define NVSIDS NPMAPS 200 #define VSID_HASHMASK 0xfffffUL 201 #endif 202 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 203 204 static boolean_t moea64_initialized = FALSE; 205 206 #ifdef MOEA64_STATS 207 /* 208 * Statistics. 209 */ 210 u_int moea64_pte_valid = 0; 211 u_int moea64_pte_overflow = 0; 212 u_int moea64_pvo_entries = 0; 213 u_int moea64_pvo_enter_calls = 0; 214 u_int moea64_pvo_remove_calls = 0; 215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 216 &moea64_pte_valid, 0, ""); 217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 218 &moea64_pte_overflow, 0, ""); 219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 220 &moea64_pvo_entries, 0, ""); 221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 222 &moea64_pvo_enter_calls, 0, ""); 223 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 224 &moea64_pvo_remove_calls, 0, ""); 225 #endif 226 227 vm_offset_t moea64_scratchpage_va[2]; 228 struct pvo_entry *moea64_scratchpage_pvo[2]; 229 struct mtx moea64_scratchpage_mtx; 230 231 uint64_t moea64_large_page_mask = 0; 232 uint64_t moea64_large_page_size = 0; 233 int moea64_large_page_shift = 0; 234 235 /* 236 * PVO calls. 237 */ 238 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 239 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 240 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 241 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 242 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 243 struct pvo_entry *pvo, vm_page_t m); 244 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 245 246 /* 247 * Utility routines. 248 */ 249 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 250 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 251 static void moea64_kremove(mmu_t, vm_offset_t); 252 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 253 vm_paddr_t pa, vm_size_t sz); 254 static void moea64_pmap_init_qpages(void); 255 256 /* 257 * Kernel MMU interface 258 */ 259 void moea64_clear_modify(mmu_t, vm_page_t); 260 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 261 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 262 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 263 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 264 u_int flags, int8_t psind); 265 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 266 vm_prot_t); 267 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 268 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 269 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 270 void moea64_init(mmu_t); 271 boolean_t moea64_is_modified(mmu_t, vm_page_t); 272 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 273 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 274 int moea64_ts_referenced(mmu_t, vm_page_t); 275 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 276 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 277 void moea64_page_init(mmu_t, vm_page_t); 278 int moea64_page_wired_mappings(mmu_t, vm_page_t); 279 void moea64_pinit(mmu_t, pmap_t); 280 void moea64_pinit0(mmu_t, pmap_t); 281 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 282 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 283 void moea64_qremove(mmu_t, vm_offset_t, int); 284 void moea64_release(mmu_t, pmap_t); 285 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 286 void moea64_remove_pages(mmu_t, pmap_t); 287 void moea64_remove_all(mmu_t, vm_page_t); 288 void moea64_remove_write(mmu_t, vm_page_t); 289 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 290 void moea64_zero_page(mmu_t, vm_page_t); 291 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 292 void moea64_activate(mmu_t, struct thread *); 293 void moea64_deactivate(mmu_t, struct thread *); 294 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 295 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 296 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 297 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 298 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 299 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 300 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 301 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 302 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 303 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 304 void **va); 305 void moea64_scan_init(mmu_t mmu); 306 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 307 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 308 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 309 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 310 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 311 int *is_user, vm_offset_t *decoded_addr); 312 static size_t moea64_scan_pmap(mmu_t mmu); 313 static void *moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs); 314 #ifdef __powerpc64__ 315 static void moea64_page_array_startup(mmu_t, long); 316 #endif 317 318 319 static mmu_method_t moea64_methods[] = { 320 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 321 MMUMETHOD(mmu_copy_page, moea64_copy_page), 322 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 323 MMUMETHOD(mmu_enter, moea64_enter), 324 MMUMETHOD(mmu_enter_object, moea64_enter_object), 325 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 326 MMUMETHOD(mmu_extract, moea64_extract), 327 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 328 MMUMETHOD(mmu_init, moea64_init), 329 MMUMETHOD(mmu_is_modified, moea64_is_modified), 330 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 331 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 332 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 333 MMUMETHOD(mmu_map, moea64_map), 334 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 335 MMUMETHOD(mmu_page_init, moea64_page_init), 336 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 337 MMUMETHOD(mmu_pinit, moea64_pinit), 338 MMUMETHOD(mmu_pinit0, moea64_pinit0), 339 MMUMETHOD(mmu_protect, moea64_protect), 340 MMUMETHOD(mmu_qenter, moea64_qenter), 341 MMUMETHOD(mmu_qremove, moea64_qremove), 342 MMUMETHOD(mmu_release, moea64_release), 343 MMUMETHOD(mmu_remove, moea64_remove), 344 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 345 MMUMETHOD(mmu_remove_all, moea64_remove_all), 346 MMUMETHOD(mmu_remove_write, moea64_remove_write), 347 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 348 MMUMETHOD(mmu_unwire, moea64_unwire), 349 MMUMETHOD(mmu_zero_page, moea64_zero_page), 350 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 351 MMUMETHOD(mmu_activate, moea64_activate), 352 MMUMETHOD(mmu_deactivate, moea64_deactivate), 353 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 354 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 355 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 356 #ifdef __powerpc64__ 357 MMUMETHOD(mmu_page_array_startup, moea64_page_array_startup), 358 #endif 359 360 /* Internal interfaces */ 361 MMUMETHOD(mmu_mapdev, moea64_mapdev), 362 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 363 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 364 MMUMETHOD(mmu_kextract, moea64_kextract), 365 MMUMETHOD(mmu_kenter, moea64_kenter), 366 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 367 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 368 MMUMETHOD(mmu_scan_init, moea64_scan_init), 369 MMUMETHOD(mmu_scan_pmap, moea64_scan_pmap), 370 MMUMETHOD(mmu_dump_pmap_init, moea64_dump_pmap_init), 371 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 372 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 373 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 374 375 { 0, 0 } 376 }; 377 378 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 379 380 static struct pvo_head * 381 vm_page_to_pvoh(vm_page_t m) 382 { 383 384 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 385 return (&m->md.mdpg_pvoh); 386 } 387 388 static struct pvo_entry * 389 alloc_pvo_entry(int bootstrap) 390 { 391 struct pvo_entry *pvo; 392 393 if (!moea64_initialized || bootstrap) { 394 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 395 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 396 "Try setting machdep.moea64_bpvo_pool_size tunable", 397 __func__, moea64_bpvo_pool_index, 398 moea64_bpvo_pool_size, 399 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 400 } 401 pvo = &moea64_bpvo_pool[ 402 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 403 bzero(pvo, sizeof(*pvo)); 404 pvo->pvo_vaddr = PVO_BOOTSTRAP; 405 } else 406 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 407 408 return (pvo); 409 } 410 411 412 static void 413 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 414 { 415 uint64_t vsid; 416 uint64_t hash; 417 int shift; 418 419 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 420 421 pvo->pvo_pmap = pmap; 422 va &= ~ADDR_POFF; 423 pvo->pvo_vaddr |= va; 424 vsid = va_to_vsid(pmap, va); 425 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 426 | (vsid << 16); 427 428 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 429 ADDR_PIDX_SHFT; 430 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 431 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 432 } 433 434 static void 435 free_pvo_entry(struct pvo_entry *pvo) 436 { 437 438 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 439 uma_zfree(moea64_pvo_zone, pvo); 440 } 441 442 void 443 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 444 { 445 446 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 447 lpte->pte_hi |= LPTE_VALID; 448 449 if (pvo->pvo_vaddr & PVO_LARGE) 450 lpte->pte_hi |= LPTE_BIG; 451 if (pvo->pvo_vaddr & PVO_WIRED) 452 lpte->pte_hi |= LPTE_WIRED; 453 if (pvo->pvo_vaddr & PVO_HID) 454 lpte->pte_hi |= LPTE_HID; 455 456 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 457 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 458 lpte->pte_lo |= LPTE_BW; 459 else 460 lpte->pte_lo |= LPTE_BR; 461 462 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 463 lpte->pte_lo |= LPTE_NOEXEC; 464 } 465 466 static __inline uint64_t 467 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 468 { 469 uint64_t pte_lo; 470 int i; 471 472 if (ma != VM_MEMATTR_DEFAULT) { 473 switch (ma) { 474 case VM_MEMATTR_UNCACHEABLE: 475 return (LPTE_I | LPTE_G); 476 case VM_MEMATTR_CACHEABLE: 477 return (LPTE_M); 478 case VM_MEMATTR_WRITE_COMBINING: 479 case VM_MEMATTR_WRITE_BACK: 480 case VM_MEMATTR_PREFETCHABLE: 481 return (LPTE_I); 482 case VM_MEMATTR_WRITE_THROUGH: 483 return (LPTE_W | LPTE_M); 484 } 485 } 486 487 /* 488 * Assume the page is cache inhibited and access is guarded unless 489 * it's in our available memory array. 490 */ 491 pte_lo = LPTE_I | LPTE_G; 492 for (i = 0; i < pregions_sz; i++) { 493 if ((pa >= pregions[i].mr_start) && 494 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 495 pte_lo &= ~(LPTE_I | LPTE_G); 496 pte_lo |= LPTE_M; 497 break; 498 } 499 } 500 501 return pte_lo; 502 } 503 504 /* 505 * Quick sort callout for comparing memory regions. 506 */ 507 static int om_cmp(const void *a, const void *b); 508 509 static int 510 om_cmp(const void *a, const void *b) 511 { 512 const struct ofw_map *mapa; 513 const struct ofw_map *mapb; 514 515 mapa = a; 516 mapb = b; 517 if (mapa->om_pa < mapb->om_pa) 518 return (-1); 519 else if (mapa->om_pa > mapb->om_pa) 520 return (1); 521 else 522 return (0); 523 } 524 525 static void 526 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 527 { 528 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 529 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 530 struct pvo_entry *pvo; 531 register_t msr; 532 vm_offset_t off; 533 vm_paddr_t pa_base; 534 int i, j; 535 536 bzero(translations, sz); 537 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 538 sizeof(acells)); 539 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 540 panic("moea64_bootstrap: can't get ofw translations"); 541 542 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 543 sz /= sizeof(cell_t); 544 for (i = 0, j = 0; i < sz; j++) { 545 translations[j].om_va = trans_cells[i++]; 546 translations[j].om_len = trans_cells[i++]; 547 translations[j].om_pa = trans_cells[i++]; 548 if (acells == 2) { 549 translations[j].om_pa <<= 32; 550 translations[j].om_pa |= trans_cells[i++]; 551 } 552 translations[j].om_mode = trans_cells[i++]; 553 } 554 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 555 i, sz)); 556 557 sz = j; 558 qsort(translations, sz, sizeof (*translations), om_cmp); 559 560 for (i = 0; i < sz; i++) { 561 pa_base = translations[i].om_pa; 562 #ifndef __powerpc64__ 563 if ((translations[i].om_pa >> 32) != 0) 564 panic("OFW translations above 32-bit boundary!"); 565 #endif 566 567 if (pa_base % PAGE_SIZE) 568 panic("OFW translation not page-aligned (phys)!"); 569 if (translations[i].om_va % PAGE_SIZE) 570 panic("OFW translation not page-aligned (virt)!"); 571 572 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 573 pa_base, translations[i].om_va, translations[i].om_len); 574 575 /* Now enter the pages for this mapping */ 576 577 DISABLE_TRANS(msr); 578 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 579 /* If this address is direct-mapped, skip remapping */ 580 if (hw_direct_map && 581 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 582 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 583 == LPTE_M) 584 continue; 585 586 PMAP_LOCK(kernel_pmap); 587 pvo = moea64_pvo_find_va(kernel_pmap, 588 translations[i].om_va + off); 589 PMAP_UNLOCK(kernel_pmap); 590 if (pvo != NULL) 591 continue; 592 593 moea64_kenter(mmup, translations[i].om_va + off, 594 pa_base + off); 595 } 596 ENABLE_TRANS(msr); 597 } 598 } 599 600 #ifdef __powerpc64__ 601 static void 602 moea64_probe_large_page(void) 603 { 604 uint16_t pvr = mfpvr() >> 16; 605 606 switch (pvr) { 607 case IBM970: 608 case IBM970FX: 609 case IBM970MP: 610 powerpc_sync(); isync(); 611 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 612 powerpc_sync(); isync(); 613 614 /* FALLTHROUGH */ 615 default: 616 if (moea64_large_page_size == 0) { 617 moea64_large_page_size = 0x1000000; /* 16 MB */ 618 moea64_large_page_shift = 24; 619 } 620 } 621 622 moea64_large_page_mask = moea64_large_page_size - 1; 623 } 624 625 static void 626 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 627 { 628 struct slb *cache; 629 struct slb entry; 630 uint64_t esid, slbe; 631 uint64_t i; 632 633 cache = PCPU_GET(aim.slb); 634 esid = va >> ADDR_SR_SHFT; 635 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 636 637 for (i = 0; i < 64; i++) { 638 if (cache[i].slbe == (slbe | i)) 639 return; 640 } 641 642 entry.slbe = slbe; 643 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 644 if (large) 645 entry.slbv |= SLBV_L; 646 647 slb_insert_kernel(entry.slbe, entry.slbv); 648 } 649 #endif 650 651 static int 652 moea64_kenter_large(mmu_t mmup, vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 653 { 654 struct pvo_entry *pvo; 655 uint64_t pte_lo; 656 int error; 657 658 pte_lo = LPTE_M; 659 pte_lo |= attr; 660 661 pvo = alloc_pvo_entry(bootstrap); 662 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 663 init_pvo_entry(pvo, kernel_pmap, va); 664 665 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 666 VM_PROT_EXECUTE; 667 pvo->pvo_pte.pa = pa | pte_lo; 668 error = moea64_pvo_enter(mmup, pvo, NULL, NULL); 669 if (error != 0) 670 panic("Error %d inserting large page\n", error); 671 return (0); 672 } 673 674 static void 675 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 676 vm_offset_t kernelend) 677 { 678 register_t msr; 679 vm_paddr_t pa, pkernelstart, pkernelend; 680 vm_offset_t size, off; 681 uint64_t pte_lo; 682 int i; 683 684 if (moea64_large_page_size == 0) 685 hw_direct_map = 0; 686 687 DISABLE_TRANS(msr); 688 if (hw_direct_map) { 689 PMAP_LOCK(kernel_pmap); 690 for (i = 0; i < pregions_sz; i++) { 691 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 692 pregions[i].mr_size; pa += moea64_large_page_size) { 693 pte_lo = LPTE_M; 694 if (pa & moea64_large_page_mask) { 695 pa &= moea64_large_page_mask; 696 pte_lo |= LPTE_G; 697 } 698 if (pa + moea64_large_page_size > 699 pregions[i].mr_start + pregions[i].mr_size) 700 pte_lo |= LPTE_G; 701 702 moea64_kenter_large(mmup, PHYS_TO_DMAP(pa), pa, pte_lo, 1); 703 } 704 } 705 PMAP_UNLOCK(kernel_pmap); 706 } 707 708 /* 709 * Make sure the kernel and BPVO pool stay mapped on systems either 710 * without a direct map or on which the kernel is not already executing 711 * out of the direct-mapped region. 712 */ 713 if (kernelstart < DMAP_BASE_ADDRESS) { 714 /* 715 * For pre-dmap execution, we need to use identity mapping 716 * because we will be operating with the mmu on but in the 717 * wrong address configuration until we __restartkernel(). 718 */ 719 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 720 pa += PAGE_SIZE) 721 moea64_kenter(mmup, pa, pa); 722 } else if (!hw_direct_map) { 723 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 724 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 725 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 726 pa += PAGE_SIZE) 727 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 728 } 729 730 if (!hw_direct_map) { 731 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 732 off = (vm_offset_t)(moea64_bpvo_pool); 733 for (pa = off; pa < off + size; pa += PAGE_SIZE) 734 moea64_kenter(mmup, pa, pa); 735 736 /* Map exception vectors */ 737 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 738 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 739 } 740 ENABLE_TRANS(msr); 741 742 /* 743 * Allow user to override unmapped_buf_allowed for testing. 744 * XXXKIB Only direct map implementation was tested. 745 */ 746 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 747 &unmapped_buf_allowed)) 748 unmapped_buf_allowed = hw_direct_map; 749 } 750 751 /* Quick sort callout for comparing physical addresses. */ 752 static int 753 pa_cmp(const void *a, const void *b) 754 { 755 const vm_paddr_t *pa = a, *pb = b; 756 757 if (*pa < *pb) 758 return (-1); 759 else if (*pa > *pb) 760 return (1); 761 else 762 return (0); 763 } 764 765 void 766 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 767 { 768 int i, j; 769 vm_size_t physsz, hwphyssz; 770 vm_paddr_t kernelphysstart, kernelphysend; 771 int rm_pavail; 772 773 #ifndef __powerpc64__ 774 /* We don't have a direct map since there is no BAT */ 775 hw_direct_map = 0; 776 777 /* Make sure battable is zero, since we have no BAT */ 778 for (i = 0; i < 16; i++) { 779 battable[i].batu = 0; 780 battable[i].batl = 0; 781 } 782 #else 783 moea64_probe_large_page(); 784 785 /* Use a direct map if we have large page support */ 786 if (moea64_large_page_size > 0) 787 hw_direct_map = 1; 788 else 789 hw_direct_map = 0; 790 791 /* Install trap handlers for SLBs */ 792 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 793 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 794 __syncicache((void *)EXC_DSE, 0x80); 795 __syncicache((void *)EXC_ISE, 0x80); 796 #endif 797 798 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 799 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 800 801 /* Get physical memory regions from firmware */ 802 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 803 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 804 805 if (PHYS_AVAIL_ENTRIES < regions_sz) 806 panic("moea64_bootstrap: phys_avail too small"); 807 808 phys_avail_count = 0; 809 physsz = 0; 810 hwphyssz = 0; 811 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 812 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 813 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 814 regions[i].mr_start, regions[i].mr_start + 815 regions[i].mr_size, regions[i].mr_size); 816 if (hwphyssz != 0 && 817 (physsz + regions[i].mr_size) >= hwphyssz) { 818 if (physsz < hwphyssz) { 819 phys_avail[j] = regions[i].mr_start; 820 phys_avail[j + 1] = regions[i].mr_start + 821 hwphyssz - physsz; 822 physsz = hwphyssz; 823 phys_avail_count++; 824 dump_avail[j] = phys_avail[j]; 825 dump_avail[j + 1] = phys_avail[j + 1]; 826 } 827 break; 828 } 829 phys_avail[j] = regions[i].mr_start; 830 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 831 phys_avail_count++; 832 physsz += regions[i].mr_size; 833 dump_avail[j] = phys_avail[j]; 834 dump_avail[j + 1] = phys_avail[j + 1]; 835 } 836 837 /* Check for overlap with the kernel and exception vectors */ 838 rm_pavail = 0; 839 for (j = 0; j < 2*phys_avail_count; j+=2) { 840 if (phys_avail[j] < EXC_LAST) 841 phys_avail[j] += EXC_LAST; 842 843 if (phys_avail[j] >= kernelphysstart && 844 phys_avail[j+1] <= kernelphysend) { 845 phys_avail[j] = phys_avail[j+1] = ~0; 846 rm_pavail++; 847 continue; 848 } 849 850 if (kernelphysstart >= phys_avail[j] && 851 kernelphysstart < phys_avail[j+1]) { 852 if (kernelphysend < phys_avail[j+1]) { 853 phys_avail[2*phys_avail_count] = 854 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 855 phys_avail[2*phys_avail_count + 1] = 856 phys_avail[j+1]; 857 phys_avail_count++; 858 } 859 860 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 861 } 862 863 if (kernelphysend >= phys_avail[j] && 864 kernelphysend < phys_avail[j+1]) { 865 if (kernelphysstart > phys_avail[j]) { 866 phys_avail[2*phys_avail_count] = phys_avail[j]; 867 phys_avail[2*phys_avail_count + 1] = 868 kernelphysstart & ~PAGE_MASK; 869 phys_avail_count++; 870 } 871 872 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 873 PAGE_SIZE; 874 } 875 } 876 877 /* Remove physical available regions marked for removal (~0) */ 878 if (rm_pavail) { 879 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 880 pa_cmp); 881 phys_avail_count -= rm_pavail; 882 for (i = 2*phys_avail_count; 883 i < 2*(phys_avail_count + rm_pavail); i+=2) 884 phys_avail[i] = phys_avail[i+1] = 0; 885 } 886 887 physmem = btoc(physsz); 888 889 #ifdef PTEGCOUNT 890 moea64_pteg_count = PTEGCOUNT; 891 #else 892 moea64_pteg_count = 0x1000; 893 894 while (moea64_pteg_count < physmem) 895 moea64_pteg_count <<= 1; 896 897 moea64_pteg_count >>= 1; 898 #endif /* PTEGCOUNT */ 899 } 900 901 void 902 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 903 { 904 int i; 905 906 /* 907 * Set PTEG mask 908 */ 909 moea64_pteg_mask = moea64_pteg_count - 1; 910 911 /* 912 * Initialize SLB table lock and page locks 913 */ 914 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 915 for (i = 0; i < PV_LOCK_COUNT; i++) 916 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 917 918 /* 919 * Initialise the bootstrap pvo pool. 920 */ 921 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 922 if (moea64_bpvo_pool_size == 0) { 923 if (!hw_direct_map) 924 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) / 925 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR; 926 else 927 moea64_bpvo_pool_size = BPVO_POOL_SIZE; 928 } 929 930 if (boothowto & RB_VERBOSE) { 931 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n", 932 moea64_bpvo_pool_size, 933 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576); 934 } 935 936 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 937 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 938 moea64_bpvo_pool_index = 0; 939 940 /* Place at address usable through the direct map */ 941 if (hw_direct_map) 942 moea64_bpvo_pool = (struct pvo_entry *) 943 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 944 945 /* 946 * Make sure kernel vsid is allocated as well as VSID 0. 947 */ 948 #ifndef __powerpc64__ 949 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 950 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 951 moea64_vsid_bitmap[0] |= 1; 952 #endif 953 954 /* 955 * Initialize the kernel pmap (which is statically allocated). 956 */ 957 #ifdef __powerpc64__ 958 for (i = 0; i < 64; i++) { 959 pcpup->pc_aim.slb[i].slbv = 0; 960 pcpup->pc_aim.slb[i].slbe = 0; 961 } 962 #else 963 for (i = 0; i < 16; i++) 964 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 965 #endif 966 967 kernel_pmap->pmap_phys = kernel_pmap; 968 CPU_FILL(&kernel_pmap->pm_active); 969 RB_INIT(&kernel_pmap->pmap_pvo); 970 971 PMAP_LOCK_INIT(kernel_pmap); 972 973 /* 974 * Now map in all the other buffers we allocated earlier 975 */ 976 977 moea64_setup_direct_map(mmup, kernelstart, kernelend); 978 } 979 980 void 981 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 982 { 983 ihandle_t mmui; 984 phandle_t chosen; 985 phandle_t mmu; 986 ssize_t sz; 987 int i; 988 vm_offset_t pa, va; 989 void *dpcpu; 990 991 /* 992 * Set up the Open Firmware pmap and add its mappings if not in real 993 * mode. 994 */ 995 996 chosen = OF_finddevice("/chosen"); 997 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 998 mmu = OF_instance_to_package(mmui); 999 if (mmu == -1 || 1000 (sz = OF_getproplen(mmu, "translations")) == -1) 1001 sz = 0; 1002 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1003 panic("moea64_bootstrap: too many ofw translations"); 1004 1005 if (sz > 0) 1006 moea64_add_ofw_mappings(mmup, mmu, sz); 1007 } 1008 1009 /* 1010 * Calculate the last available physical address. 1011 */ 1012 Maxmem = 0; 1013 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1014 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 1015 1016 /* 1017 * Initialize MMU. 1018 */ 1019 MMU_CPU_BOOTSTRAP(mmup,0); 1020 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1021 pmap_bootstrapped++; 1022 1023 /* 1024 * Set the start and end of kva. 1025 */ 1026 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1027 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1028 1029 /* 1030 * Map the entire KVA range into the SLB. We must not fault there. 1031 */ 1032 #ifdef __powerpc64__ 1033 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1034 moea64_bootstrap_slb_prefault(va, 0); 1035 #endif 1036 1037 /* 1038 * Remap any early IO mappings (console framebuffer, etc.) 1039 */ 1040 bs_remap_earlyboot(); 1041 1042 /* 1043 * Figure out how far we can extend virtual_end into segment 16 1044 * without running into existing mappings. Segment 16 is guaranteed 1045 * to contain neither RAM nor devices (at least on Apple hardware), 1046 * but will generally contain some OFW mappings we should not 1047 * step on. 1048 */ 1049 1050 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1051 PMAP_LOCK(kernel_pmap); 1052 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1053 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1054 virtual_end += PAGE_SIZE; 1055 PMAP_UNLOCK(kernel_pmap); 1056 #endif 1057 1058 /* 1059 * Allocate a kernel stack with a guard page for thread0 and map it 1060 * into the kernel page map. 1061 */ 1062 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1063 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1064 virtual_avail = va + kstack_pages * PAGE_SIZE; 1065 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1066 thread0.td_kstack = va; 1067 thread0.td_kstack_pages = kstack_pages; 1068 for (i = 0; i < kstack_pages; i++) { 1069 moea64_kenter(mmup, va, pa); 1070 pa += PAGE_SIZE; 1071 va += PAGE_SIZE; 1072 } 1073 1074 /* 1075 * Allocate virtual address space for the message buffer. 1076 */ 1077 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1078 msgbufp = (struct msgbuf *)virtual_avail; 1079 va = virtual_avail; 1080 virtual_avail += round_page(msgbufsize); 1081 while (va < virtual_avail) { 1082 moea64_kenter(mmup, va, pa); 1083 pa += PAGE_SIZE; 1084 va += PAGE_SIZE; 1085 } 1086 1087 /* 1088 * Allocate virtual address space for the dynamic percpu area. 1089 */ 1090 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1091 dpcpu = (void *)virtual_avail; 1092 va = virtual_avail; 1093 virtual_avail += DPCPU_SIZE; 1094 while (va < virtual_avail) { 1095 moea64_kenter(mmup, va, pa); 1096 pa += PAGE_SIZE; 1097 va += PAGE_SIZE; 1098 } 1099 dpcpu_init(dpcpu, curcpu); 1100 1101 crashdumpmap = (caddr_t)virtual_avail; 1102 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1103 1104 /* 1105 * Allocate some things for page zeroing. We put this directly 1106 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1107 * of the PVO book-keeping or other parts of the VM system 1108 * from even knowing that this hack exists. 1109 */ 1110 1111 if (!hw_direct_map) { 1112 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1113 MTX_DEF); 1114 for (i = 0; i < 2; i++) { 1115 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1116 virtual_end -= PAGE_SIZE; 1117 1118 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1119 1120 PMAP_LOCK(kernel_pmap); 1121 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1122 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1123 PMAP_UNLOCK(kernel_pmap); 1124 } 1125 } 1126 1127 numa_mem_regions(&numa_pregions, &numapregions_sz); 1128 } 1129 1130 static void 1131 moea64_pmap_init_qpages(void) 1132 { 1133 struct pcpu *pc; 1134 int i; 1135 1136 if (hw_direct_map) 1137 return; 1138 1139 CPU_FOREACH(i) { 1140 pc = pcpu_find(i); 1141 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1142 if (pc->pc_qmap_addr == 0) 1143 panic("pmap_init_qpages: unable to allocate KVA"); 1144 PMAP_LOCK(kernel_pmap); 1145 pc->pc_aim.qmap_pvo = 1146 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1147 PMAP_UNLOCK(kernel_pmap); 1148 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1149 } 1150 } 1151 1152 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1153 1154 /* 1155 * Activate a user pmap. This mostly involves setting some non-CPU 1156 * state. 1157 */ 1158 void 1159 moea64_activate(mmu_t mmu, struct thread *td) 1160 { 1161 pmap_t pm; 1162 1163 pm = &td->td_proc->p_vmspace->vm_pmap; 1164 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1165 1166 #ifdef __powerpc64__ 1167 PCPU_SET(aim.userslb, pm->pm_slb); 1168 __asm __volatile("slbmte %0, %1; isync" :: 1169 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1170 #else 1171 PCPU_SET(curpmap, pm->pmap_phys); 1172 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1173 #endif 1174 } 1175 1176 void 1177 moea64_deactivate(mmu_t mmu, struct thread *td) 1178 { 1179 pmap_t pm; 1180 1181 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1182 1183 pm = &td->td_proc->p_vmspace->vm_pmap; 1184 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1185 #ifdef __powerpc64__ 1186 PCPU_SET(aim.userslb, NULL); 1187 #else 1188 PCPU_SET(curpmap, NULL); 1189 #endif 1190 } 1191 1192 void 1193 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1194 { 1195 struct pvo_entry key, *pvo; 1196 vm_page_t m; 1197 int64_t refchg; 1198 1199 key.pvo_vaddr = sva; 1200 PMAP_LOCK(pm); 1201 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1202 pvo != NULL && PVO_VADDR(pvo) < eva; 1203 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1204 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1205 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1206 pvo); 1207 pvo->pvo_vaddr &= ~PVO_WIRED; 1208 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1209 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1210 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1211 if (refchg < 0) 1212 refchg = LPTE_CHG; 1213 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1214 1215 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1216 if (refchg & LPTE_CHG) 1217 vm_page_dirty(m); 1218 if (refchg & LPTE_REF) 1219 vm_page_aflag_set(m, PGA_REFERENCED); 1220 } 1221 pm->pm_stats.wired_count--; 1222 } 1223 PMAP_UNLOCK(pm); 1224 } 1225 1226 /* 1227 * This goes through and sets the physical address of our 1228 * special scratch PTE to the PA we want to zero or copy. Because 1229 * of locking issues (this can get called in pvo_enter() by 1230 * the UMA allocator), we can't use most other utility functions here 1231 */ 1232 1233 static __inline 1234 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1235 { 1236 struct pvo_entry *pvo; 1237 1238 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1239 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1240 1241 pvo = moea64_scratchpage_pvo[which]; 1242 PMAP_LOCK(pvo->pvo_pmap); 1243 pvo->pvo_pte.pa = 1244 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1245 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1246 PMAP_UNLOCK(pvo->pvo_pmap); 1247 isync(); 1248 } 1249 1250 void 1251 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1252 { 1253 vm_offset_t dst; 1254 vm_offset_t src; 1255 1256 dst = VM_PAGE_TO_PHYS(mdst); 1257 src = VM_PAGE_TO_PHYS(msrc); 1258 1259 if (hw_direct_map) { 1260 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1261 PAGE_SIZE); 1262 } else { 1263 mtx_lock(&moea64_scratchpage_mtx); 1264 1265 moea64_set_scratchpage_pa(mmu, 0, src); 1266 moea64_set_scratchpage_pa(mmu, 1, dst); 1267 1268 bcopy((void *)moea64_scratchpage_va[0], 1269 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1270 1271 mtx_unlock(&moea64_scratchpage_mtx); 1272 } 1273 } 1274 1275 static inline void 1276 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1277 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1278 { 1279 void *a_cp, *b_cp; 1280 vm_offset_t a_pg_offset, b_pg_offset; 1281 int cnt; 1282 1283 while (xfersize > 0) { 1284 a_pg_offset = a_offset & PAGE_MASK; 1285 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1286 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1287 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1288 a_pg_offset; 1289 b_pg_offset = b_offset & PAGE_MASK; 1290 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1291 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1292 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1293 b_pg_offset; 1294 bcopy(a_cp, b_cp, cnt); 1295 a_offset += cnt; 1296 b_offset += cnt; 1297 xfersize -= cnt; 1298 } 1299 } 1300 1301 static inline void 1302 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1303 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1304 { 1305 void *a_cp, *b_cp; 1306 vm_offset_t a_pg_offset, b_pg_offset; 1307 int cnt; 1308 1309 mtx_lock(&moea64_scratchpage_mtx); 1310 while (xfersize > 0) { 1311 a_pg_offset = a_offset & PAGE_MASK; 1312 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1313 moea64_set_scratchpage_pa(mmu, 0, 1314 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1315 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1316 b_pg_offset = b_offset & PAGE_MASK; 1317 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1318 moea64_set_scratchpage_pa(mmu, 1, 1319 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1320 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1321 bcopy(a_cp, b_cp, cnt); 1322 a_offset += cnt; 1323 b_offset += cnt; 1324 xfersize -= cnt; 1325 } 1326 mtx_unlock(&moea64_scratchpage_mtx); 1327 } 1328 1329 void 1330 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1331 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1332 { 1333 1334 if (hw_direct_map) { 1335 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1336 xfersize); 1337 } else { 1338 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1339 xfersize); 1340 } 1341 } 1342 1343 void 1344 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1345 { 1346 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1347 1348 if (size + off > PAGE_SIZE) 1349 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1350 1351 if (hw_direct_map) { 1352 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1353 } else { 1354 mtx_lock(&moea64_scratchpage_mtx); 1355 moea64_set_scratchpage_pa(mmu, 0, pa); 1356 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1357 mtx_unlock(&moea64_scratchpage_mtx); 1358 } 1359 } 1360 1361 /* 1362 * Zero a page of physical memory by temporarily mapping it 1363 */ 1364 void 1365 moea64_zero_page(mmu_t mmu, vm_page_t m) 1366 { 1367 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1368 vm_offset_t va, off; 1369 1370 if (!hw_direct_map) { 1371 mtx_lock(&moea64_scratchpage_mtx); 1372 1373 moea64_set_scratchpage_pa(mmu, 0, pa); 1374 va = moea64_scratchpage_va[0]; 1375 } else { 1376 va = PHYS_TO_DMAP(pa); 1377 } 1378 1379 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1380 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1381 1382 if (!hw_direct_map) 1383 mtx_unlock(&moea64_scratchpage_mtx); 1384 } 1385 1386 vm_offset_t 1387 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1388 { 1389 struct pvo_entry *pvo; 1390 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1391 1392 if (hw_direct_map) 1393 return (PHYS_TO_DMAP(pa)); 1394 1395 /* 1396 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1397 * a critical section and access the PCPU data like on i386. 1398 * Instead, pin the thread and grab the PCPU lock to prevent 1399 * a preempting thread from using the same PCPU data. 1400 */ 1401 sched_pin(); 1402 1403 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1404 pvo = PCPU_GET(aim.qmap_pvo); 1405 1406 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1407 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1408 (uint64_t)pa; 1409 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1410 isync(); 1411 1412 return (PCPU_GET(qmap_addr)); 1413 } 1414 1415 void 1416 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1417 { 1418 if (hw_direct_map) 1419 return; 1420 1421 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1422 KASSERT(PCPU_GET(qmap_addr) == addr, 1423 ("moea64_quick_remove_page: invalid address")); 1424 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1425 sched_unpin(); 1426 } 1427 1428 /* 1429 * Map the given physical page at the specified virtual address in the 1430 * target pmap with the protection requested. If specified the page 1431 * will be wired down. 1432 */ 1433 1434 int 1435 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1436 vm_prot_t prot, u_int flags, int8_t psind) 1437 { 1438 struct pvo_entry *pvo, *oldpvo; 1439 struct pvo_head *pvo_head; 1440 uint64_t pte_lo; 1441 int error; 1442 1443 if ((m->oflags & VPO_UNMANAGED) == 0) { 1444 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1445 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1446 else 1447 VM_OBJECT_ASSERT_LOCKED(m->object); 1448 } 1449 1450 pvo = alloc_pvo_entry(0); 1451 if (pvo == NULL) 1452 return (KERN_RESOURCE_SHORTAGE); 1453 pvo->pvo_pmap = NULL; /* to be filled in later */ 1454 pvo->pvo_pte.prot = prot; 1455 1456 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1457 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1458 1459 if ((flags & PMAP_ENTER_WIRED) != 0) 1460 pvo->pvo_vaddr |= PVO_WIRED; 1461 1462 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1463 pvo_head = NULL; 1464 } else { 1465 pvo_head = &m->md.mdpg_pvoh; 1466 pvo->pvo_vaddr |= PVO_MANAGED; 1467 } 1468 1469 PV_PAGE_LOCK(m); 1470 PMAP_LOCK(pmap); 1471 if (pvo->pvo_pmap == NULL) 1472 init_pvo_entry(pvo, pmap, va); 1473 if (prot & VM_PROT_WRITE) 1474 if (pmap_bootstrapped && 1475 (m->oflags & VPO_UNMANAGED) == 0) 1476 vm_page_aflag_set(m, PGA_WRITEABLE); 1477 1478 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1479 if (error == EEXIST) { 1480 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1481 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1482 oldpvo->pvo_pte.prot == prot) { 1483 /* Identical mapping already exists */ 1484 error = 0; 1485 1486 /* If not in page table, reinsert it */ 1487 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1488 STAT_MOEA64(moea64_pte_overflow--); 1489 MOEA64_PTE_INSERT(mmu, oldpvo); 1490 } 1491 1492 /* Then just clean up and go home */ 1493 PV_PAGE_UNLOCK(m); 1494 PMAP_UNLOCK(pmap); 1495 free_pvo_entry(pvo); 1496 goto out; 1497 } else { 1498 /* Otherwise, need to kill it first */ 1499 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1500 "mapping does not match new mapping")); 1501 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1502 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1503 } 1504 } 1505 PMAP_UNLOCK(pmap); 1506 PV_PAGE_UNLOCK(m); 1507 1508 /* Free any dead pages */ 1509 if (error == EEXIST) { 1510 moea64_pvo_remove_from_page(mmu, oldpvo); 1511 free_pvo_entry(oldpvo); 1512 } 1513 1514 out: 1515 /* 1516 * Flush the page from the instruction cache if this page is 1517 * mapped executable and cacheable. 1518 */ 1519 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1520 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1521 vm_page_aflag_set(m, PGA_EXECUTABLE); 1522 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1523 } 1524 return (KERN_SUCCESS); 1525 } 1526 1527 static void 1528 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1529 vm_size_t sz) 1530 { 1531 1532 /* 1533 * This is much trickier than on older systems because 1534 * we can't sync the icache on physical addresses directly 1535 * without a direct map. Instead we check a couple of cases 1536 * where the memory is already mapped in and, failing that, 1537 * use the same trick we use for page zeroing to create 1538 * a temporary mapping for this physical address. 1539 */ 1540 1541 if (!pmap_bootstrapped) { 1542 /* 1543 * If PMAP is not bootstrapped, we are likely to be 1544 * in real mode. 1545 */ 1546 __syncicache((void *)(uintptr_t)pa, sz); 1547 } else if (pmap == kernel_pmap) { 1548 __syncicache((void *)va, sz); 1549 } else if (hw_direct_map) { 1550 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1551 } else { 1552 /* Use the scratch page to set up a temp mapping */ 1553 1554 mtx_lock(&moea64_scratchpage_mtx); 1555 1556 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1557 __syncicache((void *)(moea64_scratchpage_va[1] + 1558 (va & ADDR_POFF)), sz); 1559 1560 mtx_unlock(&moea64_scratchpage_mtx); 1561 } 1562 } 1563 1564 /* 1565 * Maps a sequence of resident pages belonging to the same object. 1566 * The sequence begins with the given page m_start. This page is 1567 * mapped at the given virtual address start. Each subsequent page is 1568 * mapped at a virtual address that is offset from start by the same 1569 * amount as the page is offset from m_start within the object. The 1570 * last page in the sequence is the page with the largest offset from 1571 * m_start that can be mapped at a virtual address less than the given 1572 * virtual address end. Not every virtual page between start and end 1573 * is mapped; only those for which a resident page exists with the 1574 * corresponding offset from m_start are mapped. 1575 */ 1576 void 1577 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1578 vm_page_t m_start, vm_prot_t prot) 1579 { 1580 vm_page_t m; 1581 vm_pindex_t diff, psize; 1582 1583 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1584 1585 psize = atop(end - start); 1586 m = m_start; 1587 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1588 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1589 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1590 PMAP_ENTER_QUICK_LOCKED, 0); 1591 m = TAILQ_NEXT(m, listq); 1592 } 1593 } 1594 1595 void 1596 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1597 vm_prot_t prot) 1598 { 1599 1600 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1601 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1602 } 1603 1604 vm_paddr_t 1605 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1606 { 1607 struct pvo_entry *pvo; 1608 vm_paddr_t pa; 1609 1610 PMAP_LOCK(pm); 1611 pvo = moea64_pvo_find_va(pm, va); 1612 if (pvo == NULL) 1613 pa = 0; 1614 else 1615 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1616 PMAP_UNLOCK(pm); 1617 1618 return (pa); 1619 } 1620 1621 /* 1622 * Atomically extract and hold the physical page with the given 1623 * pmap and virtual address pair if that mapping permits the given 1624 * protection. 1625 */ 1626 vm_page_t 1627 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1628 { 1629 struct pvo_entry *pvo; 1630 vm_page_t m; 1631 1632 m = NULL; 1633 PMAP_LOCK(pmap); 1634 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1635 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1636 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1637 if (!vm_page_wire_mapped(m)) 1638 m = NULL; 1639 } 1640 PMAP_UNLOCK(pmap); 1641 return (m); 1642 } 1643 1644 static mmu_t installed_mmu; 1645 1646 static void * 1647 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1648 uint8_t *flags, int wait) 1649 { 1650 struct pvo_entry *pvo; 1651 vm_offset_t va; 1652 vm_page_t m; 1653 int needed_lock; 1654 1655 /* 1656 * This entire routine is a horrible hack to avoid bothering kmem 1657 * for new KVA addresses. Because this can get called from inside 1658 * kmem allocation routines, calling kmem for a new address here 1659 * can lead to multiply locking non-recursive mutexes. 1660 */ 1661 1662 *flags = UMA_SLAB_PRIV; 1663 needed_lock = !PMAP_LOCKED(kernel_pmap); 1664 1665 m = vm_page_alloc_domain(NULL, 0, domain, 1666 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1667 if (m == NULL) 1668 return (NULL); 1669 1670 va = VM_PAGE_TO_PHYS(m); 1671 1672 pvo = alloc_pvo_entry(1 /* bootstrap */); 1673 1674 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1675 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1676 1677 if (needed_lock) 1678 PMAP_LOCK(kernel_pmap); 1679 1680 init_pvo_entry(pvo, kernel_pmap, va); 1681 pvo->pvo_vaddr |= PVO_WIRED; 1682 1683 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1684 1685 if (needed_lock) 1686 PMAP_UNLOCK(kernel_pmap); 1687 1688 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1689 bzero((void *)va, PAGE_SIZE); 1690 1691 return (void *)va; 1692 } 1693 1694 extern int elf32_nxstack; 1695 1696 void 1697 moea64_init(mmu_t mmu) 1698 { 1699 1700 CTR0(KTR_PMAP, "moea64_init"); 1701 1702 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1703 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1704 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1705 1706 if (!hw_direct_map) { 1707 installed_mmu = mmu; 1708 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1709 } 1710 1711 #ifdef COMPAT_FREEBSD32 1712 elf32_nxstack = 1; 1713 #endif 1714 1715 moea64_initialized = TRUE; 1716 } 1717 1718 boolean_t 1719 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1720 { 1721 1722 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1723 ("moea64_is_referenced: page %p is not managed", m)); 1724 1725 return (moea64_query_bit(mmu, m, LPTE_REF)); 1726 } 1727 1728 boolean_t 1729 moea64_is_modified(mmu_t mmu, vm_page_t m) 1730 { 1731 1732 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1733 ("moea64_is_modified: page %p is not managed", m)); 1734 1735 /* 1736 * If the page is not busied then this check is racy. 1737 */ 1738 if (!pmap_page_is_write_mapped(m)) 1739 return (FALSE); 1740 1741 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1742 } 1743 1744 boolean_t 1745 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1746 { 1747 struct pvo_entry *pvo; 1748 boolean_t rv = TRUE; 1749 1750 PMAP_LOCK(pmap); 1751 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1752 if (pvo != NULL) 1753 rv = FALSE; 1754 PMAP_UNLOCK(pmap); 1755 return (rv); 1756 } 1757 1758 void 1759 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1760 { 1761 1762 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1763 ("moea64_clear_modify: page %p is not managed", m)); 1764 vm_page_assert_busied(m); 1765 1766 if (!pmap_page_is_write_mapped(m)) 1767 return; 1768 moea64_clear_bit(mmu, m, LPTE_CHG); 1769 } 1770 1771 /* 1772 * Clear the write and modified bits in each of the given page's mappings. 1773 */ 1774 void 1775 moea64_remove_write(mmu_t mmu, vm_page_t m) 1776 { 1777 struct pvo_entry *pvo; 1778 int64_t refchg, ret; 1779 pmap_t pmap; 1780 1781 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1782 ("moea64_remove_write: page %p is not managed", m)); 1783 vm_page_assert_busied(m); 1784 1785 if (!pmap_page_is_write_mapped(m)) 1786 return 1787 1788 powerpc_sync(); 1789 PV_PAGE_LOCK(m); 1790 refchg = 0; 1791 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1792 pmap = pvo->pvo_pmap; 1793 PMAP_LOCK(pmap); 1794 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1795 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1796 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1797 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1798 MOEA64_PTE_PROT_UPDATE); 1799 if (ret < 0) 1800 ret = LPTE_CHG; 1801 refchg |= ret; 1802 if (pvo->pvo_pmap == kernel_pmap) 1803 isync(); 1804 } 1805 PMAP_UNLOCK(pmap); 1806 } 1807 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1808 vm_page_dirty(m); 1809 vm_page_aflag_clear(m, PGA_WRITEABLE); 1810 PV_PAGE_UNLOCK(m); 1811 } 1812 1813 /* 1814 * moea64_ts_referenced: 1815 * 1816 * Return a count of reference bits for a page, clearing those bits. 1817 * It is not necessary for every reference bit to be cleared, but it 1818 * is necessary that 0 only be returned when there are truly no 1819 * reference bits set. 1820 * 1821 * XXX: The exact number of bits to check and clear is a matter that 1822 * should be tested and standardized at some point in the future for 1823 * optimal aging of shared pages. 1824 */ 1825 int 1826 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1827 { 1828 1829 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1830 ("moea64_ts_referenced: page %p is not managed", m)); 1831 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1832 } 1833 1834 /* 1835 * Modify the WIMG settings of all mappings for a page. 1836 */ 1837 void 1838 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1839 { 1840 struct pvo_entry *pvo; 1841 int64_t refchg; 1842 pmap_t pmap; 1843 uint64_t lo; 1844 1845 if ((m->oflags & VPO_UNMANAGED) != 0) { 1846 m->md.mdpg_cache_attrs = ma; 1847 return; 1848 } 1849 1850 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1851 1852 PV_PAGE_LOCK(m); 1853 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1854 pmap = pvo->pvo_pmap; 1855 PMAP_LOCK(pmap); 1856 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1857 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1858 pvo->pvo_pte.pa |= lo; 1859 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1860 MOEA64_PTE_INVALIDATE); 1861 if (refchg < 0) 1862 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1863 LPTE_CHG : 0; 1864 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1865 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1866 refchg |= 1867 atomic_readandclear_32(&m->md.mdpg_attrs); 1868 if (refchg & LPTE_CHG) 1869 vm_page_dirty(m); 1870 if (refchg & LPTE_REF) 1871 vm_page_aflag_set(m, PGA_REFERENCED); 1872 } 1873 if (pvo->pvo_pmap == kernel_pmap) 1874 isync(); 1875 } 1876 PMAP_UNLOCK(pmap); 1877 } 1878 m->md.mdpg_cache_attrs = ma; 1879 PV_PAGE_UNLOCK(m); 1880 } 1881 1882 /* 1883 * Map a wired page into kernel virtual address space. 1884 */ 1885 void 1886 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1887 { 1888 int error; 1889 struct pvo_entry *pvo, *oldpvo; 1890 1891 do { 1892 pvo = alloc_pvo_entry(0); 1893 if (pvo == NULL) 1894 vm_wait(NULL); 1895 } while (pvo == NULL); 1896 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1897 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1898 pvo->pvo_vaddr |= PVO_WIRED; 1899 1900 PMAP_LOCK(kernel_pmap); 1901 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1902 if (oldpvo != NULL) 1903 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1904 init_pvo_entry(pvo, kernel_pmap, va); 1905 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1906 PMAP_UNLOCK(kernel_pmap); 1907 1908 /* Free any dead pages */ 1909 if (oldpvo != NULL) { 1910 moea64_pvo_remove_from_page(mmu, oldpvo); 1911 free_pvo_entry(oldpvo); 1912 } 1913 1914 if (error != 0) 1915 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1916 (uintmax_t)pa, error); 1917 } 1918 1919 void 1920 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1921 { 1922 1923 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1924 } 1925 1926 /* 1927 * Extract the physical page address associated with the given kernel virtual 1928 * address. 1929 */ 1930 vm_paddr_t 1931 moea64_kextract(mmu_t mmu, vm_offset_t va) 1932 { 1933 struct pvo_entry *pvo; 1934 vm_paddr_t pa; 1935 1936 /* 1937 * Shortcut the direct-mapped case when applicable. We never put 1938 * anything but 1:1 (or 62-bit aliased) mappings below 1939 * VM_MIN_KERNEL_ADDRESS. 1940 */ 1941 if (va < VM_MIN_KERNEL_ADDRESS) 1942 return (va & ~DMAP_BASE_ADDRESS); 1943 1944 PMAP_LOCK(kernel_pmap); 1945 pvo = moea64_pvo_find_va(kernel_pmap, va); 1946 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1947 va)); 1948 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1949 PMAP_UNLOCK(kernel_pmap); 1950 return (pa); 1951 } 1952 1953 /* 1954 * Remove a wired page from kernel virtual address space. 1955 */ 1956 void 1957 moea64_kremove(mmu_t mmu, vm_offset_t va) 1958 { 1959 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1960 } 1961 1962 /* 1963 * Provide a kernel pointer corresponding to a given userland pointer. 1964 * The returned pointer is valid until the next time this function is 1965 * called in this thread. This is used internally in copyin/copyout. 1966 */ 1967 static int 1968 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1969 void **kaddr, size_t ulen, size_t *klen) 1970 { 1971 size_t l; 1972 #ifdef __powerpc64__ 1973 struct slb *slb; 1974 #endif 1975 register_t slbv; 1976 1977 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1978 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1979 if (l > ulen) 1980 l = ulen; 1981 if (klen) 1982 *klen = l; 1983 else if (l != ulen) 1984 return (EFAULT); 1985 1986 #ifdef __powerpc64__ 1987 /* Try lockless look-up first */ 1988 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1989 1990 if (slb == NULL) { 1991 /* If it isn't there, we need to pre-fault the VSID */ 1992 PMAP_LOCK(pm); 1993 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1994 PMAP_UNLOCK(pm); 1995 } else { 1996 slbv = slb->slbv; 1997 } 1998 1999 /* Mark segment no-execute */ 2000 slbv |= SLBV_N; 2001 #else 2002 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 2003 2004 /* Mark segment no-execute */ 2005 slbv |= SR_N; 2006 #endif 2007 2008 /* If we have already set this VSID, we can just return */ 2009 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 2010 return (0); 2011 2012 __asm __volatile("isync"); 2013 curthread->td_pcb->pcb_cpu.aim.usr_segm = 2014 (uintptr_t)uaddr >> ADDR_SR_SHFT; 2015 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 2016 #ifdef __powerpc64__ 2017 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2018 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2019 #else 2020 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2021 #endif 2022 2023 return (0); 2024 } 2025 2026 /* 2027 * Figure out where a given kernel pointer (usually in a fault) points 2028 * to from the VM's perspective, potentially remapping into userland's 2029 * address space. 2030 */ 2031 static int 2032 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2033 vm_offset_t *decoded_addr) 2034 { 2035 vm_offset_t user_sr; 2036 2037 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2038 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2039 addr &= ADDR_PIDX | ADDR_POFF; 2040 addr |= user_sr << ADDR_SR_SHFT; 2041 *decoded_addr = addr; 2042 *is_user = 1; 2043 } else { 2044 *decoded_addr = addr; 2045 *is_user = 0; 2046 } 2047 2048 return (0); 2049 } 2050 2051 /* 2052 * Map a range of physical addresses into kernel virtual address space. 2053 * 2054 * The value passed in *virt is a suggested virtual address for the mapping. 2055 * Architectures which can support a direct-mapped physical to virtual region 2056 * can return the appropriate address within that region, leaving '*virt' 2057 * unchanged. Other architectures should map the pages starting at '*virt' and 2058 * update '*virt' with the first usable address after the mapped region. 2059 */ 2060 vm_offset_t 2061 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2062 vm_paddr_t pa_end, int prot) 2063 { 2064 vm_offset_t sva, va; 2065 2066 if (hw_direct_map) { 2067 /* 2068 * Check if every page in the region is covered by the direct 2069 * map. The direct map covers all of physical memory. Use 2070 * moea64_calc_wimg() as a shortcut to see if the page is in 2071 * physical memory as a way to see if the direct map covers it. 2072 */ 2073 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2074 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2075 break; 2076 if (va == pa_end) 2077 return (PHYS_TO_DMAP(pa_start)); 2078 } 2079 sva = *virt; 2080 va = sva; 2081 /* XXX respect prot argument */ 2082 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2083 moea64_kenter(mmu, va, pa_start); 2084 *virt = va; 2085 2086 return (sva); 2087 } 2088 2089 /* 2090 * Returns true if the pmap's pv is one of the first 2091 * 16 pvs linked to from this page. This count may 2092 * be changed upwards or downwards in the future; it 2093 * is only necessary that true be returned for a small 2094 * subset of pmaps for proper page aging. 2095 */ 2096 boolean_t 2097 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2098 { 2099 int loops; 2100 struct pvo_entry *pvo; 2101 boolean_t rv; 2102 2103 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2104 ("moea64_page_exists_quick: page %p is not managed", m)); 2105 loops = 0; 2106 rv = FALSE; 2107 PV_PAGE_LOCK(m); 2108 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2109 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2110 rv = TRUE; 2111 break; 2112 } 2113 if (++loops >= 16) 2114 break; 2115 } 2116 PV_PAGE_UNLOCK(m); 2117 return (rv); 2118 } 2119 2120 void 2121 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2122 { 2123 2124 m->md.mdpg_attrs = 0; 2125 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2126 LIST_INIT(&m->md.mdpg_pvoh); 2127 } 2128 2129 /* 2130 * Return the number of managed mappings to the given physical page 2131 * that are wired. 2132 */ 2133 int 2134 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2135 { 2136 struct pvo_entry *pvo; 2137 int count; 2138 2139 count = 0; 2140 if ((m->oflags & VPO_UNMANAGED) != 0) 2141 return (count); 2142 PV_PAGE_LOCK(m); 2143 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2144 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2145 count++; 2146 PV_PAGE_UNLOCK(m); 2147 return (count); 2148 } 2149 2150 static uintptr_t moea64_vsidcontext; 2151 2152 uintptr_t 2153 moea64_get_unique_vsid(void) { 2154 u_int entropy; 2155 register_t hash; 2156 uint32_t mask; 2157 int i; 2158 2159 entropy = 0; 2160 __asm __volatile("mftb %0" : "=r"(entropy)); 2161 2162 mtx_lock(&moea64_slb_mutex); 2163 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2164 u_int n; 2165 2166 /* 2167 * Create a new value by mutiplying by a prime and adding in 2168 * entropy from the timebase register. This is to make the 2169 * VSID more random so that the PT hash function collides 2170 * less often. (Note that the prime casues gcc to do shifts 2171 * instead of a multiply.) 2172 */ 2173 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2174 hash = moea64_vsidcontext & (NVSIDS - 1); 2175 if (hash == 0) /* 0 is special, avoid it */ 2176 continue; 2177 n = hash >> 5; 2178 mask = 1 << (hash & (VSID_NBPW - 1)); 2179 hash = (moea64_vsidcontext & VSID_HASHMASK); 2180 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2181 /* anything free in this bucket? */ 2182 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2183 entropy = (moea64_vsidcontext >> 20); 2184 continue; 2185 } 2186 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2187 mask = 1 << i; 2188 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2189 hash |= i; 2190 } 2191 if (hash == VSID_VRMA) /* also special, avoid this too */ 2192 continue; 2193 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2194 ("Allocating in-use VSID %#zx\n", hash)); 2195 moea64_vsid_bitmap[n] |= mask; 2196 mtx_unlock(&moea64_slb_mutex); 2197 return (hash); 2198 } 2199 2200 mtx_unlock(&moea64_slb_mutex); 2201 panic("%s: out of segments",__func__); 2202 } 2203 2204 #ifdef __powerpc64__ 2205 void 2206 moea64_pinit(mmu_t mmu, pmap_t pmap) 2207 { 2208 2209 RB_INIT(&pmap->pmap_pvo); 2210 2211 pmap->pm_slb_tree_root = slb_alloc_tree(); 2212 pmap->pm_slb = slb_alloc_user_cache(); 2213 pmap->pm_slb_len = 0; 2214 } 2215 #else 2216 void 2217 moea64_pinit(mmu_t mmu, pmap_t pmap) 2218 { 2219 int i; 2220 uint32_t hash; 2221 2222 RB_INIT(&pmap->pmap_pvo); 2223 2224 if (pmap_bootstrapped) 2225 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2226 (vm_offset_t)pmap); 2227 else 2228 pmap->pmap_phys = pmap; 2229 2230 /* 2231 * Allocate some segment registers for this pmap. 2232 */ 2233 hash = moea64_get_unique_vsid(); 2234 2235 for (i = 0; i < 16; i++) 2236 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2237 2238 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2239 } 2240 #endif 2241 2242 /* 2243 * Initialize the pmap associated with process 0. 2244 */ 2245 void 2246 moea64_pinit0(mmu_t mmu, pmap_t pm) 2247 { 2248 2249 PMAP_LOCK_INIT(pm); 2250 moea64_pinit(mmu, pm); 2251 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2252 } 2253 2254 /* 2255 * Set the physical protection on the specified range of this map as requested. 2256 */ 2257 static void 2258 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2259 { 2260 struct vm_page *pg; 2261 vm_prot_t oldprot; 2262 int32_t refchg; 2263 2264 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2265 2266 /* 2267 * Change the protection of the page. 2268 */ 2269 oldprot = pvo->pvo_pte.prot; 2270 pvo->pvo_pte.prot = prot; 2271 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2272 2273 /* 2274 * If the PVO is in the page table, update mapping 2275 */ 2276 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2277 if (refchg < 0) 2278 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2279 2280 if (pm != kernel_pmap && pg != NULL && 2281 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2282 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2283 if ((pg->oflags & VPO_UNMANAGED) == 0) 2284 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2285 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2286 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2287 } 2288 2289 /* 2290 * Update vm about the REF/CHG bits if the page is managed and we have 2291 * removed write access. 2292 */ 2293 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2294 (oldprot & VM_PROT_WRITE)) { 2295 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2296 if (refchg & LPTE_CHG) 2297 vm_page_dirty(pg); 2298 if (refchg & LPTE_REF) 2299 vm_page_aflag_set(pg, PGA_REFERENCED); 2300 } 2301 } 2302 2303 void 2304 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2305 vm_prot_t prot) 2306 { 2307 struct pvo_entry *pvo, *tpvo, key; 2308 2309 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2310 sva, eva, prot); 2311 2312 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2313 ("moea64_protect: non current pmap")); 2314 2315 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2316 moea64_remove(mmu, pm, sva, eva); 2317 return; 2318 } 2319 2320 PMAP_LOCK(pm); 2321 key.pvo_vaddr = sva; 2322 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2323 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2324 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2325 moea64_pvo_protect(mmu, pm, pvo, prot); 2326 } 2327 PMAP_UNLOCK(pm); 2328 } 2329 2330 /* 2331 * Map a list of wired pages into kernel virtual address space. This is 2332 * intended for temporary mappings which do not need page modification or 2333 * references recorded. Existing mappings in the region are overwritten. 2334 */ 2335 void 2336 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2337 { 2338 while (count-- > 0) { 2339 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2340 va += PAGE_SIZE; 2341 m++; 2342 } 2343 } 2344 2345 /* 2346 * Remove page mappings from kernel virtual address space. Intended for 2347 * temporary mappings entered by moea64_qenter. 2348 */ 2349 void 2350 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2351 { 2352 while (count-- > 0) { 2353 moea64_kremove(mmu, va); 2354 va += PAGE_SIZE; 2355 } 2356 } 2357 2358 void 2359 moea64_release_vsid(uint64_t vsid) 2360 { 2361 int idx, mask; 2362 2363 mtx_lock(&moea64_slb_mutex); 2364 idx = vsid & (NVSIDS-1); 2365 mask = 1 << (idx % VSID_NBPW); 2366 idx /= VSID_NBPW; 2367 KASSERT(moea64_vsid_bitmap[idx] & mask, 2368 ("Freeing unallocated VSID %#jx", vsid)); 2369 moea64_vsid_bitmap[idx] &= ~mask; 2370 mtx_unlock(&moea64_slb_mutex); 2371 } 2372 2373 2374 void 2375 moea64_release(mmu_t mmu, pmap_t pmap) 2376 { 2377 2378 /* 2379 * Free segment registers' VSIDs 2380 */ 2381 #ifdef __powerpc64__ 2382 slb_free_tree(pmap); 2383 slb_free_user_cache(pmap->pm_slb); 2384 #else 2385 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2386 2387 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2388 #endif 2389 } 2390 2391 /* 2392 * Remove all pages mapped by the specified pmap 2393 */ 2394 void 2395 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2396 { 2397 struct pvo_entry *pvo, *tpvo; 2398 struct pvo_dlist tofree; 2399 2400 SLIST_INIT(&tofree); 2401 2402 PMAP_LOCK(pm); 2403 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2404 if (pvo->pvo_vaddr & PVO_WIRED) 2405 continue; 2406 2407 /* 2408 * For locking reasons, remove this from the page table and 2409 * pmap, but save delinking from the vm_page for a second 2410 * pass 2411 */ 2412 moea64_pvo_remove_from_pmap(mmu, pvo); 2413 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2414 } 2415 PMAP_UNLOCK(pm); 2416 2417 while (!SLIST_EMPTY(&tofree)) { 2418 pvo = SLIST_FIRST(&tofree); 2419 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2420 moea64_pvo_remove_from_page(mmu, pvo); 2421 free_pvo_entry(pvo); 2422 } 2423 } 2424 2425 /* 2426 * Remove the given range of addresses from the specified map. 2427 */ 2428 void 2429 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2430 { 2431 struct pvo_entry *pvo, *tpvo, key; 2432 struct pvo_dlist tofree; 2433 2434 /* 2435 * Perform an unsynchronized read. This is, however, safe. 2436 */ 2437 if (pm->pm_stats.resident_count == 0) 2438 return; 2439 2440 key.pvo_vaddr = sva; 2441 2442 SLIST_INIT(&tofree); 2443 2444 PMAP_LOCK(pm); 2445 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2446 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2447 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2448 2449 /* 2450 * For locking reasons, remove this from the page table and 2451 * pmap, but save delinking from the vm_page for a second 2452 * pass 2453 */ 2454 moea64_pvo_remove_from_pmap(mmu, pvo); 2455 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2456 } 2457 PMAP_UNLOCK(pm); 2458 2459 while (!SLIST_EMPTY(&tofree)) { 2460 pvo = SLIST_FIRST(&tofree); 2461 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2462 moea64_pvo_remove_from_page(mmu, pvo); 2463 free_pvo_entry(pvo); 2464 } 2465 } 2466 2467 /* 2468 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2469 * will reflect changes in pte's back to the vm_page. 2470 */ 2471 void 2472 moea64_remove_all(mmu_t mmu, vm_page_t m) 2473 { 2474 struct pvo_entry *pvo, *next_pvo; 2475 struct pvo_head freequeue; 2476 int wasdead; 2477 pmap_t pmap; 2478 2479 LIST_INIT(&freequeue); 2480 2481 PV_PAGE_LOCK(m); 2482 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2483 pmap = pvo->pvo_pmap; 2484 PMAP_LOCK(pmap); 2485 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2486 if (!wasdead) 2487 moea64_pvo_remove_from_pmap(mmu, pvo); 2488 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2489 if (!wasdead) 2490 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2491 PMAP_UNLOCK(pmap); 2492 2493 } 2494 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2495 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2496 PV_PAGE_UNLOCK(m); 2497 2498 /* Clean up UMA allocations */ 2499 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2500 free_pvo_entry(pvo); 2501 } 2502 2503 /* 2504 * Allocate a physical page of memory directly from the phys_avail map. 2505 * Can only be called from moea64_bootstrap before avail start and end are 2506 * calculated. 2507 */ 2508 vm_offset_t 2509 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2510 { 2511 vm_offset_t s, e; 2512 int i, j; 2513 2514 size = round_page(size); 2515 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2516 if (align != 0) 2517 s = roundup2(phys_avail[i], align); 2518 else 2519 s = phys_avail[i]; 2520 e = s + size; 2521 2522 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2523 continue; 2524 2525 if (s + size > platform_real_maxaddr()) 2526 continue; 2527 2528 if (s == phys_avail[i]) { 2529 phys_avail[i] += size; 2530 } else if (e == phys_avail[i + 1]) { 2531 phys_avail[i + 1] -= size; 2532 } else { 2533 for (j = phys_avail_count * 2; j > i; j -= 2) { 2534 phys_avail[j] = phys_avail[j - 2]; 2535 phys_avail[j + 1] = phys_avail[j - 1]; 2536 } 2537 2538 phys_avail[i + 3] = phys_avail[i + 1]; 2539 phys_avail[i + 1] = s; 2540 phys_avail[i + 2] = e; 2541 phys_avail_count++; 2542 } 2543 2544 return (s); 2545 } 2546 panic("moea64_bootstrap_alloc: could not allocate memory"); 2547 } 2548 2549 static int 2550 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2551 struct pvo_entry **oldpvop) 2552 { 2553 struct pvo_entry *old_pvo; 2554 int err; 2555 2556 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2557 2558 STAT_MOEA64(moea64_pvo_enter_calls++); 2559 2560 /* 2561 * Add to pmap list 2562 */ 2563 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2564 2565 if (old_pvo != NULL) { 2566 if (oldpvop != NULL) 2567 *oldpvop = old_pvo; 2568 return (EEXIST); 2569 } 2570 2571 if (pvo_head != NULL) { 2572 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2573 } 2574 2575 if (pvo->pvo_vaddr & PVO_WIRED) 2576 pvo->pvo_pmap->pm_stats.wired_count++; 2577 pvo->pvo_pmap->pm_stats.resident_count++; 2578 2579 /* 2580 * Insert it into the hardware page table 2581 */ 2582 err = MOEA64_PTE_INSERT(mmu, pvo); 2583 if (err != 0) { 2584 panic("moea64_pvo_enter: overflow"); 2585 } 2586 2587 STAT_MOEA64(moea64_pvo_entries++); 2588 2589 if (pvo->pvo_pmap == kernel_pmap) 2590 isync(); 2591 2592 #ifdef __powerpc64__ 2593 /* 2594 * Make sure all our bootstrap mappings are in the SLB as soon 2595 * as virtual memory is switched on. 2596 */ 2597 if (!pmap_bootstrapped) 2598 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2599 pvo->pvo_vaddr & PVO_LARGE); 2600 #endif 2601 2602 return (0); 2603 } 2604 2605 static void 2606 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2607 { 2608 struct vm_page *pg; 2609 int32_t refchg; 2610 2611 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2612 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2613 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2614 2615 /* 2616 * If there is an active pte entry, we need to deactivate it 2617 */ 2618 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2619 if (refchg < 0) { 2620 /* 2621 * If it was evicted from the page table, be pessimistic and 2622 * dirty the page. 2623 */ 2624 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2625 refchg = LPTE_CHG; 2626 else 2627 refchg = 0; 2628 } 2629 2630 /* 2631 * Update our statistics. 2632 */ 2633 pvo->pvo_pmap->pm_stats.resident_count--; 2634 if (pvo->pvo_vaddr & PVO_WIRED) 2635 pvo->pvo_pmap->pm_stats.wired_count--; 2636 2637 /* 2638 * Remove this PVO from the pmap list. 2639 */ 2640 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2641 2642 /* 2643 * Mark this for the next sweep 2644 */ 2645 pvo->pvo_vaddr |= PVO_DEAD; 2646 2647 /* Send RC bits to VM */ 2648 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2649 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2650 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2651 if (pg != NULL) { 2652 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2653 if (refchg & LPTE_CHG) 2654 vm_page_dirty(pg); 2655 if (refchg & LPTE_REF) 2656 vm_page_aflag_set(pg, PGA_REFERENCED); 2657 } 2658 } 2659 } 2660 2661 static inline void 2662 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2663 vm_page_t m) 2664 { 2665 2666 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2667 2668 /* Use NULL pmaps as a sentinel for races in page deletion */ 2669 if (pvo->pvo_pmap == NULL) 2670 return; 2671 pvo->pvo_pmap = NULL; 2672 2673 /* 2674 * Update vm about page writeability/executability if managed 2675 */ 2676 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2677 if (pvo->pvo_vaddr & PVO_MANAGED) { 2678 if (m != NULL) { 2679 LIST_REMOVE(pvo, pvo_vlink); 2680 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2681 vm_page_aflag_clear(m, 2682 PGA_WRITEABLE | PGA_EXECUTABLE); 2683 } 2684 } 2685 2686 STAT_MOEA64(moea64_pvo_entries--); 2687 STAT_MOEA64(moea64_pvo_remove_calls++); 2688 } 2689 2690 static void 2691 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2692 { 2693 vm_page_t pg = NULL; 2694 2695 if (pvo->pvo_vaddr & PVO_MANAGED) 2696 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2697 2698 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2699 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2700 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2701 } 2702 2703 static struct pvo_entry * 2704 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2705 { 2706 struct pvo_entry key; 2707 2708 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2709 2710 key.pvo_vaddr = va & ~ADDR_POFF; 2711 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2712 } 2713 2714 static boolean_t 2715 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2716 { 2717 struct pvo_entry *pvo; 2718 int64_t ret; 2719 boolean_t rv; 2720 2721 /* 2722 * See if this bit is stored in the page already. 2723 */ 2724 if (m->md.mdpg_attrs & ptebit) 2725 return (TRUE); 2726 2727 /* 2728 * Examine each PTE. Sync so that any pending REF/CHG bits are 2729 * flushed to the PTEs. 2730 */ 2731 rv = FALSE; 2732 powerpc_sync(); 2733 PV_PAGE_LOCK(m); 2734 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2735 ret = 0; 2736 2737 /* 2738 * See if this pvo has a valid PTE. if so, fetch the 2739 * REF/CHG bits from the valid PTE. If the appropriate 2740 * ptebit is set, return success. 2741 */ 2742 PMAP_LOCK(pvo->pvo_pmap); 2743 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2744 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2745 PMAP_UNLOCK(pvo->pvo_pmap); 2746 2747 if (ret > 0) { 2748 atomic_set_32(&m->md.mdpg_attrs, 2749 ret & (LPTE_CHG | LPTE_REF)); 2750 if (ret & ptebit) { 2751 rv = TRUE; 2752 break; 2753 } 2754 } 2755 } 2756 PV_PAGE_UNLOCK(m); 2757 2758 return (rv); 2759 } 2760 2761 static u_int 2762 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2763 { 2764 u_int count; 2765 struct pvo_entry *pvo; 2766 int64_t ret; 2767 2768 /* 2769 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2770 * we can reset the right ones). 2771 */ 2772 powerpc_sync(); 2773 2774 /* 2775 * For each pvo entry, clear the pte's ptebit. 2776 */ 2777 count = 0; 2778 PV_PAGE_LOCK(m); 2779 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2780 ret = 0; 2781 2782 PMAP_LOCK(pvo->pvo_pmap); 2783 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2784 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2785 PMAP_UNLOCK(pvo->pvo_pmap); 2786 2787 if (ret > 0 && (ret & ptebit)) 2788 count++; 2789 } 2790 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2791 PV_PAGE_UNLOCK(m); 2792 2793 return (count); 2794 } 2795 2796 boolean_t 2797 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2798 { 2799 struct pvo_entry *pvo, key; 2800 vm_offset_t ppa; 2801 int error = 0; 2802 2803 if (hw_direct_map && mem_valid(pa, size) == 0) 2804 return (0); 2805 2806 PMAP_LOCK(kernel_pmap); 2807 ppa = pa & ~ADDR_POFF; 2808 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2809 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2810 ppa < pa + size; ppa += PAGE_SIZE, 2811 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2812 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2813 error = EFAULT; 2814 break; 2815 } 2816 } 2817 PMAP_UNLOCK(kernel_pmap); 2818 2819 return (error); 2820 } 2821 2822 /* 2823 * Map a set of physical memory pages into the kernel virtual 2824 * address space. Return a pointer to where it is mapped. This 2825 * routine is intended to be used for mapping device memory, 2826 * NOT real memory. 2827 */ 2828 void * 2829 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2830 { 2831 vm_offset_t va, tmpva, ppa, offset; 2832 2833 ppa = trunc_page(pa); 2834 offset = pa & PAGE_MASK; 2835 size = roundup2(offset + size, PAGE_SIZE); 2836 2837 va = kva_alloc(size); 2838 2839 if (!va) 2840 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2841 2842 for (tmpva = va; size > 0;) { 2843 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2844 size -= PAGE_SIZE; 2845 tmpva += PAGE_SIZE; 2846 ppa += PAGE_SIZE; 2847 } 2848 2849 return ((void *)(va + offset)); 2850 } 2851 2852 void * 2853 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2854 { 2855 2856 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2857 } 2858 2859 void 2860 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2861 { 2862 vm_offset_t base, offset; 2863 2864 base = trunc_page(va); 2865 offset = va & PAGE_MASK; 2866 size = roundup2(offset + size, PAGE_SIZE); 2867 2868 kva_free(base, size); 2869 } 2870 2871 void 2872 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2873 { 2874 struct pvo_entry *pvo; 2875 vm_offset_t lim; 2876 vm_paddr_t pa; 2877 vm_size_t len; 2878 2879 if (__predict_false(pm == NULL)) 2880 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2881 2882 PMAP_LOCK(pm); 2883 while (sz > 0) { 2884 lim = round_page(va+1); 2885 len = MIN(lim - va, sz); 2886 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2887 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2888 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2889 moea64_syncicache(mmu, pm, va, pa, len); 2890 } 2891 va += len; 2892 sz -= len; 2893 } 2894 PMAP_UNLOCK(pm); 2895 } 2896 2897 void 2898 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2899 { 2900 2901 *va = (void *)(uintptr_t)pa; 2902 } 2903 2904 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2905 2906 void 2907 moea64_scan_init(mmu_t mmu) 2908 { 2909 struct pvo_entry *pvo; 2910 vm_offset_t va; 2911 int i; 2912 2913 if (!do_minidump) { 2914 /* Initialize phys. segments for dumpsys(). */ 2915 memset(&dump_map, 0, sizeof(dump_map)); 2916 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2917 for (i = 0; i < pregions_sz; i++) { 2918 dump_map[i].pa_start = pregions[i].mr_start; 2919 dump_map[i].pa_size = pregions[i].mr_size; 2920 } 2921 return; 2922 } 2923 2924 /* Virtual segments for minidumps: */ 2925 memset(&dump_map, 0, sizeof(dump_map)); 2926 2927 /* 1st: kernel .data and .bss. */ 2928 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2929 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2930 dump_map[0].pa_start; 2931 2932 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2933 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2934 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2935 2936 /* 3rd: kernel VM. */ 2937 va = dump_map[1].pa_start + dump_map[1].pa_size; 2938 /* Find start of next chunk (from va). */ 2939 while (va < virtual_end) { 2940 /* Don't dump the buffer cache. */ 2941 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2942 va = kmi.buffer_eva; 2943 continue; 2944 } 2945 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2946 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2947 break; 2948 va += PAGE_SIZE; 2949 } 2950 if (va < virtual_end) { 2951 dump_map[2].pa_start = va; 2952 va += PAGE_SIZE; 2953 /* Find last page in chunk. */ 2954 while (va < virtual_end) { 2955 /* Don't run into the buffer cache. */ 2956 if (va == kmi.buffer_sva) 2957 break; 2958 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2959 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2960 break; 2961 va += PAGE_SIZE; 2962 } 2963 dump_map[2].pa_size = va - dump_map[2].pa_start; 2964 } 2965 } 2966 2967 #ifdef __powerpc64__ 2968 2969 static size_t 2970 moea64_scan_pmap(mmu_t mmu) 2971 { 2972 struct pvo_entry *pvo; 2973 vm_paddr_t pa, pa_end; 2974 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 2975 uint64_t lpsize; 2976 2977 lpsize = moea64_large_page_size; 2978 kstart = trunc_page((vm_offset_t)_etext); 2979 kend = round_page((vm_offset_t)_end); 2980 kstart_lp = kstart & ~moea64_large_page_mask; 2981 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 2982 2983 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 2984 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 2985 kstart, kend, kstart_lp, kend_lp); 2986 2987 PMAP_LOCK(kernel_pmap); 2988 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 2989 va = pvo->pvo_vaddr; 2990 2991 if (va & PVO_DEAD) 2992 continue; 2993 2994 /* Skip DMAP (except kernel area) */ 2995 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 2996 if (va & PVO_LARGE) { 2997 pgva = va & ~moea64_large_page_mask; 2998 if (pgva < kstart_lp || pgva >= kend_lp) 2999 continue; 3000 } else { 3001 pgva = trunc_page(va); 3002 if (pgva < kstart || pgva >= kend) 3003 continue; 3004 } 3005 } 3006 3007 pa = pvo->pvo_pte.pa & LPTE_RPGN; 3008 3009 if (va & PVO_LARGE) { 3010 pa_end = pa + lpsize; 3011 for (; pa < pa_end; pa += PAGE_SIZE) { 3012 if (is_dumpable(pa)) 3013 dump_add_page(pa); 3014 } 3015 } else { 3016 if (is_dumpable(pa)) 3017 dump_add_page(pa); 3018 } 3019 } 3020 PMAP_UNLOCK(kernel_pmap); 3021 3022 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3023 } 3024 3025 static struct dump_context dump_ctx; 3026 3027 static void * 3028 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3029 { 3030 dump_ctx.ptex = 0; 3031 dump_ctx.ptex_end = moea64_pteg_count * 8; 3032 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3033 return (&dump_ctx); 3034 } 3035 3036 #else 3037 3038 static size_t 3039 moea64_scan_pmap(mmu_t mmu) 3040 { 3041 return (0); 3042 } 3043 3044 static void * 3045 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3046 { 3047 return (NULL); 3048 } 3049 3050 #endif 3051 3052 #ifdef __powerpc64__ 3053 static void 3054 moea64_map_range(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3055 { 3056 3057 for (; npages > 0; --npages) { 3058 if (moea64_large_page_size != 0 && 3059 (pa & moea64_large_page_mask) == 0 && 3060 (va & moea64_large_page_mask) == 0 && 3061 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3062 PMAP_LOCK(kernel_pmap); 3063 moea64_kenter_large(mmu, va, pa, 0, 0); 3064 PMAP_UNLOCK(kernel_pmap); 3065 pa += moea64_large_page_size; 3066 va += moea64_large_page_size; 3067 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3068 } else { 3069 moea64_kenter(mmu, va, pa); 3070 pa += PAGE_SIZE; 3071 va += PAGE_SIZE; 3072 } 3073 } 3074 } 3075 3076 static void 3077 moea64_page_array_startup(mmu_t mmu, long pages) 3078 { 3079 long dom_pages[MAXMEMDOM]; 3080 vm_paddr_t pa; 3081 vm_offset_t va, vm_page_base; 3082 vm_size_t needed, size; 3083 long page; 3084 int domain; 3085 int i; 3086 3087 vm_page_base = 0xd000000000000000ULL; 3088 3089 /* Short-circuit single-domain systems. */ 3090 if (vm_ndomains == 1) { 3091 size = round_page(pages * sizeof(struct vm_page)); 3092 pa = vm_phys_early_alloc(0, size); 3093 vm_page_base = moea64_map(mmu, &vm_page_base, 3094 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3095 vm_page_array_size = pages; 3096 vm_page_array = (vm_page_t)vm_page_base; 3097 return; 3098 } 3099 3100 page = 0; 3101 for (i = 0; i < MAXMEMDOM; i++) 3102 dom_pages[i] = 0; 3103 3104 /* Now get the number of pages required per domain. */ 3105 for (i = 0; i < vm_phys_nsegs; i++) { 3106 domain = vm_phys_segs[i].domain; 3107 KASSERT(domain < MAXMEMDOM, 3108 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3109 /* Get size of vm_page_array needed for this segment. */ 3110 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3111 dom_pages[domain] += size; 3112 } 3113 3114 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3115 domain = _vm_phys_domain(phys_avail[i]); 3116 KASSERT(domain < MAXMEMDOM, 3117 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3118 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3119 dom_pages[domain] += size; 3120 } 3121 3122 /* 3123 * Map in chunks that can get us all 16MB pages. There will be some 3124 * overlap between domains, but that's acceptable for now. 3125 */ 3126 vm_page_array_size = 0; 3127 va = vm_page_base; 3128 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3129 if (dom_pages[i] == 0) 3130 continue; 3131 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3132 size = round_page(size * sizeof(struct vm_page)); 3133 needed = size; 3134 size = roundup2(size, moea64_large_page_size); 3135 pa = vm_phys_early_alloc(i, size); 3136 vm_page_array_size += size / sizeof(struct vm_page); 3137 moea64_map_range(mmu, va, pa, size >> PAGE_SHIFT); 3138 /* Scoot up domain 0, to reduce the domain page overlap. */ 3139 if (i == 0) 3140 vm_page_base += size - needed; 3141 va += size; 3142 } 3143 vm_page_array = (vm_page_t)vm_page_base; 3144 vm_page_array_size = pages; 3145 } 3146 #endif 3147