1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_map.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_pageout.h> 81 #include <vm/uma.h> 82 83 #include <machine/_inttypes.h> 84 #include <machine/cpu.h> 85 #include <machine/platform.h> 86 #include <machine/frame.h> 87 #include <machine/md_var.h> 88 #include <machine/psl.h> 89 #include <machine/bat.h> 90 #include <machine/hid.h> 91 #include <machine/pte.h> 92 #include <machine/sr.h> 93 #include <machine/trap.h> 94 #include <machine/mmuvar.h> 95 96 #include "mmu_oea64.h" 97 #include "mmu_if.h" 98 #include "moea64_if.h" 99 100 void moea64_release_vsid(uint64_t vsid); 101 uintptr_t moea64_get_unique_vsid(void); 102 103 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 104 #define ENABLE_TRANS(msr) mtmsr(msr) 105 106 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 107 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 108 #define VSID_HASH_MASK 0x0000007fffffffffULL 109 110 /* 111 * Locking semantics: 112 * 113 * There are two locks of interest: the page locks and the pmap locks, which 114 * protect their individual PVO lists and are locked in that order. The contents 115 * of all PVO entries are protected by the locks of their respective pmaps. 116 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 117 * into any list. 118 * 119 */ 120 121 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 122 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 123 124 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 125 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 126 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 127 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 128 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 129 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 130 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 131 132 struct ofw_map { 133 cell_t om_va; 134 cell_t om_len; 135 uint64_t om_pa; 136 cell_t om_mode; 137 }; 138 139 extern unsigned char _etext[]; 140 extern unsigned char _end[]; 141 142 extern void *slbtrap, *slbtrapend; 143 144 /* 145 * Map of physical memory regions. 146 */ 147 static struct mem_region *regions; 148 static struct mem_region *pregions; 149 static u_int phys_avail_count; 150 static int regions_sz, pregions_sz; 151 152 extern void bs_remap_earlyboot(void); 153 154 /* 155 * Lock for the SLB tables. 156 */ 157 struct mtx moea64_slb_mutex; 158 159 /* 160 * PTEG data. 161 */ 162 u_long moea64_pteg_count; 163 u_long moea64_pteg_mask; 164 165 /* 166 * PVO data. 167 */ 168 169 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 170 171 static struct pvo_entry *moea64_bpvo_pool; 172 static int moea64_bpvo_pool_index = 0; 173 static int moea64_bpvo_pool_size = 327680; 174 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 175 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 176 &moea64_bpvo_pool_index, 0, ""); 177 178 #define VSID_NBPW (sizeof(u_int32_t) * 8) 179 #ifdef __powerpc64__ 180 #define NVSIDS (NPMAPS * 16) 181 #define VSID_HASHMASK 0xffffffffUL 182 #else 183 #define NVSIDS NPMAPS 184 #define VSID_HASHMASK 0xfffffUL 185 #endif 186 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 187 188 static boolean_t moea64_initialized = FALSE; 189 190 /* 191 * Statistics. 192 */ 193 u_int moea64_pte_valid = 0; 194 u_int moea64_pte_overflow = 0; 195 u_int moea64_pvo_entries = 0; 196 u_int moea64_pvo_enter_calls = 0; 197 u_int moea64_pvo_remove_calls = 0; 198 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 199 &moea64_pte_valid, 0, ""); 200 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 201 &moea64_pte_overflow, 0, ""); 202 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 203 &moea64_pvo_entries, 0, ""); 204 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 205 &moea64_pvo_enter_calls, 0, ""); 206 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 207 &moea64_pvo_remove_calls, 0, ""); 208 209 vm_offset_t moea64_scratchpage_va[2]; 210 struct pvo_entry *moea64_scratchpage_pvo[2]; 211 struct mtx moea64_scratchpage_mtx; 212 213 uint64_t moea64_large_page_mask = 0; 214 uint64_t moea64_large_page_size = 0; 215 int moea64_large_page_shift = 0; 216 217 /* 218 * PVO calls. 219 */ 220 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 221 struct pvo_head *pvo_head); 222 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 223 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 224 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 225 226 /* 227 * Utility routines. 228 */ 229 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 230 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 231 static void moea64_kremove(mmu_t, vm_offset_t); 232 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 233 vm_paddr_t pa, vm_size_t sz); 234 static void moea64_pmap_init_qpages(void); 235 236 /* 237 * Kernel MMU interface 238 */ 239 void moea64_clear_modify(mmu_t, vm_page_t); 240 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 241 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 242 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 243 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 244 u_int flags, int8_t psind); 245 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 246 vm_prot_t); 247 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 248 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 249 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 250 void moea64_init(mmu_t); 251 boolean_t moea64_is_modified(mmu_t, vm_page_t); 252 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 253 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 254 int moea64_ts_referenced(mmu_t, vm_page_t); 255 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 256 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 257 void moea64_page_init(mmu_t, vm_page_t); 258 int moea64_page_wired_mappings(mmu_t, vm_page_t); 259 void moea64_pinit(mmu_t, pmap_t); 260 void moea64_pinit0(mmu_t, pmap_t); 261 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 262 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 263 void moea64_qremove(mmu_t, vm_offset_t, int); 264 void moea64_release(mmu_t, pmap_t); 265 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 266 void moea64_remove_pages(mmu_t, pmap_t); 267 void moea64_remove_all(mmu_t, vm_page_t); 268 void moea64_remove_write(mmu_t, vm_page_t); 269 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 270 void moea64_zero_page(mmu_t, vm_page_t); 271 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 272 void moea64_activate(mmu_t, struct thread *); 273 void moea64_deactivate(mmu_t, struct thread *); 274 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 275 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 276 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 277 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 278 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 279 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 280 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 281 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 282 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 283 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 284 void **va); 285 void moea64_scan_init(mmu_t mmu); 286 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 287 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 288 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 289 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 290 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 291 int *is_user, vm_offset_t *decoded_addr); 292 293 294 static mmu_method_t moea64_methods[] = { 295 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 296 MMUMETHOD(mmu_copy_page, moea64_copy_page), 297 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 298 MMUMETHOD(mmu_enter, moea64_enter), 299 MMUMETHOD(mmu_enter_object, moea64_enter_object), 300 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 301 MMUMETHOD(mmu_extract, moea64_extract), 302 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 303 MMUMETHOD(mmu_init, moea64_init), 304 MMUMETHOD(mmu_is_modified, moea64_is_modified), 305 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 306 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 307 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 308 MMUMETHOD(mmu_map, moea64_map), 309 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 310 MMUMETHOD(mmu_page_init, moea64_page_init), 311 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 312 MMUMETHOD(mmu_pinit, moea64_pinit), 313 MMUMETHOD(mmu_pinit0, moea64_pinit0), 314 MMUMETHOD(mmu_protect, moea64_protect), 315 MMUMETHOD(mmu_qenter, moea64_qenter), 316 MMUMETHOD(mmu_qremove, moea64_qremove), 317 MMUMETHOD(mmu_release, moea64_release), 318 MMUMETHOD(mmu_remove, moea64_remove), 319 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 320 MMUMETHOD(mmu_remove_all, moea64_remove_all), 321 MMUMETHOD(mmu_remove_write, moea64_remove_write), 322 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 323 MMUMETHOD(mmu_unwire, moea64_unwire), 324 MMUMETHOD(mmu_zero_page, moea64_zero_page), 325 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 326 MMUMETHOD(mmu_activate, moea64_activate), 327 MMUMETHOD(mmu_deactivate, moea64_deactivate), 328 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 329 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 330 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 331 332 /* Internal interfaces */ 333 MMUMETHOD(mmu_mapdev, moea64_mapdev), 334 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 335 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 336 MMUMETHOD(mmu_kextract, moea64_kextract), 337 MMUMETHOD(mmu_kenter, moea64_kenter), 338 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 339 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 340 MMUMETHOD(mmu_scan_init, moea64_scan_init), 341 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 342 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 343 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 344 345 { 0, 0 } 346 }; 347 348 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 349 350 static struct pvo_head * 351 vm_page_to_pvoh(vm_page_t m) 352 { 353 354 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 355 return (&m->md.mdpg_pvoh); 356 } 357 358 static struct pvo_entry * 359 alloc_pvo_entry(int bootstrap) 360 { 361 struct pvo_entry *pvo; 362 363 if (!moea64_initialized || bootstrap) { 364 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 365 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 366 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 367 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 368 } 369 pvo = &moea64_bpvo_pool[ 370 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 371 bzero(pvo, sizeof(*pvo)); 372 pvo->pvo_vaddr = PVO_BOOTSTRAP; 373 } else { 374 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 375 bzero(pvo, sizeof(*pvo)); 376 } 377 378 return (pvo); 379 } 380 381 382 static void 383 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 384 { 385 uint64_t vsid; 386 uint64_t hash; 387 int shift; 388 389 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 390 391 pvo->pvo_pmap = pmap; 392 va &= ~ADDR_POFF; 393 pvo->pvo_vaddr |= va; 394 vsid = va_to_vsid(pmap, va); 395 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 396 | (vsid << 16); 397 398 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 399 ADDR_PIDX_SHFT; 400 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 401 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 402 } 403 404 static void 405 free_pvo_entry(struct pvo_entry *pvo) 406 { 407 408 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 409 uma_zfree(moea64_pvo_zone, pvo); 410 } 411 412 void 413 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 414 { 415 416 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 417 LPTE_AVPN_MASK; 418 lpte->pte_hi |= LPTE_VALID; 419 420 if (pvo->pvo_vaddr & PVO_LARGE) 421 lpte->pte_hi |= LPTE_BIG; 422 if (pvo->pvo_vaddr & PVO_WIRED) 423 lpte->pte_hi |= LPTE_WIRED; 424 if (pvo->pvo_vaddr & PVO_HID) 425 lpte->pte_hi |= LPTE_HID; 426 427 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 428 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 429 lpte->pte_lo |= LPTE_BW; 430 else 431 lpte->pte_lo |= LPTE_BR; 432 433 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 434 lpte->pte_lo |= LPTE_NOEXEC; 435 } 436 437 static __inline uint64_t 438 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 439 { 440 uint64_t pte_lo; 441 int i; 442 443 if (ma != VM_MEMATTR_DEFAULT) { 444 switch (ma) { 445 case VM_MEMATTR_UNCACHEABLE: 446 return (LPTE_I | LPTE_G); 447 case VM_MEMATTR_CACHEABLE: 448 return (LPTE_M); 449 case VM_MEMATTR_WRITE_COMBINING: 450 case VM_MEMATTR_WRITE_BACK: 451 case VM_MEMATTR_PREFETCHABLE: 452 return (LPTE_I); 453 case VM_MEMATTR_WRITE_THROUGH: 454 return (LPTE_W | LPTE_M); 455 } 456 } 457 458 /* 459 * Assume the page is cache inhibited and access is guarded unless 460 * it's in our available memory array. 461 */ 462 pte_lo = LPTE_I | LPTE_G; 463 for (i = 0; i < pregions_sz; i++) { 464 if ((pa >= pregions[i].mr_start) && 465 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 466 pte_lo &= ~(LPTE_I | LPTE_G); 467 pte_lo |= LPTE_M; 468 break; 469 } 470 } 471 472 return pte_lo; 473 } 474 475 /* 476 * Quick sort callout for comparing memory regions. 477 */ 478 static int om_cmp(const void *a, const void *b); 479 480 static int 481 om_cmp(const void *a, const void *b) 482 { 483 const struct ofw_map *mapa; 484 const struct ofw_map *mapb; 485 486 mapa = a; 487 mapb = b; 488 if (mapa->om_pa < mapb->om_pa) 489 return (-1); 490 else if (mapa->om_pa > mapb->om_pa) 491 return (1); 492 else 493 return (0); 494 } 495 496 static void 497 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 498 { 499 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 500 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 501 struct pvo_entry *pvo; 502 register_t msr; 503 vm_offset_t off; 504 vm_paddr_t pa_base; 505 int i, j; 506 507 bzero(translations, sz); 508 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 509 sizeof(acells)); 510 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 511 panic("moea64_bootstrap: can't get ofw translations"); 512 513 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 514 sz /= sizeof(cell_t); 515 for (i = 0, j = 0; i < sz; j++) { 516 translations[j].om_va = trans_cells[i++]; 517 translations[j].om_len = trans_cells[i++]; 518 translations[j].om_pa = trans_cells[i++]; 519 if (acells == 2) { 520 translations[j].om_pa <<= 32; 521 translations[j].om_pa |= trans_cells[i++]; 522 } 523 translations[j].om_mode = trans_cells[i++]; 524 } 525 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 526 i, sz)); 527 528 sz = j; 529 qsort(translations, sz, sizeof (*translations), om_cmp); 530 531 for (i = 0; i < sz; i++) { 532 pa_base = translations[i].om_pa; 533 #ifndef __powerpc64__ 534 if ((translations[i].om_pa >> 32) != 0) 535 panic("OFW translations above 32-bit boundary!"); 536 #endif 537 538 if (pa_base % PAGE_SIZE) 539 panic("OFW translation not page-aligned (phys)!"); 540 if (translations[i].om_va % PAGE_SIZE) 541 panic("OFW translation not page-aligned (virt)!"); 542 543 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 544 pa_base, translations[i].om_va, translations[i].om_len); 545 546 /* Now enter the pages for this mapping */ 547 548 DISABLE_TRANS(msr); 549 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 550 /* If this address is direct-mapped, skip remapping */ 551 if (hw_direct_map && 552 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 553 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 554 == LPTE_M) 555 continue; 556 557 PMAP_LOCK(kernel_pmap); 558 pvo = moea64_pvo_find_va(kernel_pmap, 559 translations[i].om_va + off); 560 PMAP_UNLOCK(kernel_pmap); 561 if (pvo != NULL) 562 continue; 563 564 moea64_kenter(mmup, translations[i].om_va + off, 565 pa_base + off); 566 } 567 ENABLE_TRANS(msr); 568 } 569 } 570 571 #ifdef __powerpc64__ 572 static void 573 moea64_probe_large_page(void) 574 { 575 uint16_t pvr = mfpvr() >> 16; 576 577 switch (pvr) { 578 case IBM970: 579 case IBM970FX: 580 case IBM970MP: 581 powerpc_sync(); isync(); 582 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 583 powerpc_sync(); isync(); 584 585 /* FALLTHROUGH */ 586 default: 587 if (moea64_large_page_size == 0) { 588 moea64_large_page_size = 0x1000000; /* 16 MB */ 589 moea64_large_page_shift = 24; 590 } 591 } 592 593 moea64_large_page_mask = moea64_large_page_size - 1; 594 } 595 596 static void 597 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 598 { 599 struct slb *cache; 600 struct slb entry; 601 uint64_t esid, slbe; 602 uint64_t i; 603 604 cache = PCPU_GET(aim.slb); 605 esid = va >> ADDR_SR_SHFT; 606 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 607 608 for (i = 0; i < 64; i++) { 609 if (cache[i].slbe == (slbe | i)) 610 return; 611 } 612 613 entry.slbe = slbe; 614 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 615 if (large) 616 entry.slbv |= SLBV_L; 617 618 slb_insert_kernel(entry.slbe, entry.slbv); 619 } 620 #endif 621 622 static void 623 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 624 vm_offset_t kernelend) 625 { 626 struct pvo_entry *pvo; 627 register_t msr; 628 vm_paddr_t pa; 629 vm_offset_t size, off; 630 uint64_t pte_lo; 631 int i; 632 633 if (moea64_large_page_size == 0) 634 hw_direct_map = 0; 635 636 DISABLE_TRANS(msr); 637 if (hw_direct_map) { 638 PMAP_LOCK(kernel_pmap); 639 for (i = 0; i < pregions_sz; i++) { 640 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 641 pregions[i].mr_size; pa += moea64_large_page_size) { 642 pte_lo = LPTE_M; 643 644 pvo = alloc_pvo_entry(1 /* bootstrap */); 645 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 646 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 647 648 /* 649 * Set memory access as guarded if prefetch within 650 * the page could exit the available physmem area. 651 */ 652 if (pa & moea64_large_page_mask) { 653 pa &= moea64_large_page_mask; 654 pte_lo |= LPTE_G; 655 } 656 if (pa + moea64_large_page_size > 657 pregions[i].mr_start + pregions[i].mr_size) 658 pte_lo |= LPTE_G; 659 660 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 661 VM_PROT_EXECUTE; 662 pvo->pvo_pte.pa = pa | pte_lo; 663 moea64_pvo_enter(mmup, pvo, NULL); 664 } 665 } 666 PMAP_UNLOCK(kernel_pmap); 667 } 668 669 /* 670 * Make sure the kernel and BPVO pool stay mapped on systems either 671 * without a direct map or on which the kernel is not already executing 672 * out of the direct-mapped region. 673 */ 674 675 if (!hw_direct_map || kernelstart < DMAP_BASE_ADDRESS) { 676 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 677 pa += PAGE_SIZE) 678 moea64_kenter(mmup, pa, pa); 679 } 680 681 if (!hw_direct_map) { 682 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 683 off = (vm_offset_t)(moea64_bpvo_pool); 684 for (pa = off; pa < off + size; pa += PAGE_SIZE) 685 moea64_kenter(mmup, pa, pa); 686 } 687 ENABLE_TRANS(msr); 688 689 /* 690 * Allow user to override unmapped_buf_allowed for testing. 691 * XXXKIB Only direct map implementation was tested. 692 */ 693 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 694 &unmapped_buf_allowed)) 695 unmapped_buf_allowed = hw_direct_map; 696 } 697 698 /* Quick sort callout for comparing physical addresses. */ 699 static int 700 pa_cmp(const void *a, const void *b) 701 { 702 const vm_paddr_t *pa = a, *pb = b; 703 704 if (*pa < *pb) 705 return (-1); 706 else if (*pa > *pb) 707 return (1); 708 else 709 return (0); 710 } 711 712 void 713 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 714 { 715 int i, j; 716 vm_size_t physsz, hwphyssz; 717 vm_paddr_t kernelphysstart, kernelphysend; 718 int rm_pavail; 719 720 #ifndef __powerpc64__ 721 /* We don't have a direct map since there is no BAT */ 722 hw_direct_map = 0; 723 724 /* Make sure battable is zero, since we have no BAT */ 725 for (i = 0; i < 16; i++) { 726 battable[i].batu = 0; 727 battable[i].batl = 0; 728 } 729 #else 730 moea64_probe_large_page(); 731 732 /* Use a direct map if we have large page support */ 733 if (moea64_large_page_size > 0) 734 hw_direct_map = 1; 735 else 736 hw_direct_map = 0; 737 738 /* Install trap handlers for SLBs */ 739 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 740 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 741 __syncicache((void *)EXC_DSE, 0x80); 742 __syncicache((void *)EXC_ISE, 0x80); 743 #endif 744 745 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 746 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 747 748 /* Get physical memory regions from firmware */ 749 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 750 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 751 752 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 753 panic("moea64_bootstrap: phys_avail too small"); 754 755 phys_avail_count = 0; 756 physsz = 0; 757 hwphyssz = 0; 758 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 759 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 760 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 761 regions[i].mr_start, regions[i].mr_start + 762 regions[i].mr_size, regions[i].mr_size); 763 if (hwphyssz != 0 && 764 (physsz + regions[i].mr_size) >= hwphyssz) { 765 if (physsz < hwphyssz) { 766 phys_avail[j] = regions[i].mr_start; 767 phys_avail[j + 1] = regions[i].mr_start + 768 hwphyssz - physsz; 769 physsz = hwphyssz; 770 phys_avail_count++; 771 } 772 break; 773 } 774 phys_avail[j] = regions[i].mr_start; 775 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 776 phys_avail_count++; 777 physsz += regions[i].mr_size; 778 } 779 780 /* Check for overlap with the kernel and exception vectors */ 781 rm_pavail = 0; 782 for (j = 0; j < 2*phys_avail_count; j+=2) { 783 if (phys_avail[j] < EXC_LAST) 784 phys_avail[j] += EXC_LAST; 785 786 if (phys_avail[j] >= kernelphysstart && 787 phys_avail[j+1] <= kernelphysend) { 788 phys_avail[j] = phys_avail[j+1] = ~0; 789 rm_pavail++; 790 continue; 791 } 792 793 if (kernelphysstart >= phys_avail[j] && 794 kernelphysstart < phys_avail[j+1]) { 795 if (kernelphysend < phys_avail[j+1]) { 796 phys_avail[2*phys_avail_count] = 797 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 798 phys_avail[2*phys_avail_count + 1] = 799 phys_avail[j+1]; 800 phys_avail_count++; 801 } 802 803 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 804 } 805 806 if (kernelphysend >= phys_avail[j] && 807 kernelphysend < phys_avail[j+1]) { 808 if (kernelphysstart > phys_avail[j]) { 809 phys_avail[2*phys_avail_count] = phys_avail[j]; 810 phys_avail[2*phys_avail_count + 1] = 811 kernelphysstart & ~PAGE_MASK; 812 phys_avail_count++; 813 } 814 815 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 816 PAGE_SIZE; 817 } 818 } 819 820 /* Remove physical available regions marked for removal (~0) */ 821 if (rm_pavail) { 822 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 823 pa_cmp); 824 phys_avail_count -= rm_pavail; 825 for (i = 2*phys_avail_count; 826 i < 2*(phys_avail_count + rm_pavail); i+=2) 827 phys_avail[i] = phys_avail[i+1] = 0; 828 } 829 830 physmem = btoc(physsz); 831 832 #ifdef PTEGCOUNT 833 moea64_pteg_count = PTEGCOUNT; 834 #else 835 moea64_pteg_count = 0x1000; 836 837 while (moea64_pteg_count < physmem) 838 moea64_pteg_count <<= 1; 839 840 moea64_pteg_count >>= 1; 841 #endif /* PTEGCOUNT */ 842 } 843 844 void 845 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 846 { 847 int i; 848 849 /* 850 * Set PTEG mask 851 */ 852 moea64_pteg_mask = moea64_pteg_count - 1; 853 854 /* 855 * Initialize SLB table lock and page locks 856 */ 857 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 858 for (i = 0; i < PV_LOCK_COUNT; i++) 859 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 860 861 /* 862 * Initialise the bootstrap pvo pool. 863 */ 864 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 865 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 866 moea64_bpvo_pool_index = 0; 867 868 /* Place at address usable through the direct map */ 869 if (hw_direct_map) 870 moea64_bpvo_pool = (struct pvo_entry *) 871 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 872 873 /* 874 * Make sure kernel vsid is allocated as well as VSID 0. 875 */ 876 #ifndef __powerpc64__ 877 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 878 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 879 moea64_vsid_bitmap[0] |= 1; 880 #endif 881 882 /* 883 * Initialize the kernel pmap (which is statically allocated). 884 */ 885 #ifdef __powerpc64__ 886 for (i = 0; i < 64; i++) { 887 pcpup->pc_aim.slb[i].slbv = 0; 888 pcpup->pc_aim.slb[i].slbe = 0; 889 } 890 #else 891 for (i = 0; i < 16; i++) 892 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 893 #endif 894 895 kernel_pmap->pmap_phys = kernel_pmap; 896 CPU_FILL(&kernel_pmap->pm_active); 897 RB_INIT(&kernel_pmap->pmap_pvo); 898 899 PMAP_LOCK_INIT(kernel_pmap); 900 901 /* 902 * Now map in all the other buffers we allocated earlier 903 */ 904 905 moea64_setup_direct_map(mmup, kernelstart, kernelend); 906 } 907 908 void 909 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 910 { 911 ihandle_t mmui; 912 phandle_t chosen; 913 phandle_t mmu; 914 ssize_t sz; 915 int i; 916 vm_offset_t pa, va; 917 void *dpcpu; 918 919 /* 920 * Set up the Open Firmware pmap and add its mappings if not in real 921 * mode. 922 */ 923 924 chosen = OF_finddevice("/chosen"); 925 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 926 mmu = OF_instance_to_package(mmui); 927 if (mmu == -1 || 928 (sz = OF_getproplen(mmu, "translations")) == -1) 929 sz = 0; 930 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 931 panic("moea64_bootstrap: too many ofw translations"); 932 933 if (sz > 0) 934 moea64_add_ofw_mappings(mmup, mmu, sz); 935 } 936 937 /* 938 * Calculate the last available physical address. 939 */ 940 Maxmem = 0; 941 for (i = 0; phys_avail[i + 2] != 0; i += 2) 942 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 943 944 /* 945 * Initialize MMU. 946 */ 947 MMU_CPU_BOOTSTRAP(mmup,0); 948 mtmsr(mfmsr() | PSL_DR | PSL_IR); 949 pmap_bootstrapped++; 950 951 /* 952 * Set the start and end of kva. 953 */ 954 virtual_avail = VM_MIN_KERNEL_ADDRESS; 955 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 956 957 /* 958 * Map the entire KVA range into the SLB. We must not fault there. 959 */ 960 #ifdef __powerpc64__ 961 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 962 moea64_bootstrap_slb_prefault(va, 0); 963 #endif 964 965 /* 966 * Remap any early IO mappings (console framebuffer, etc.) 967 */ 968 bs_remap_earlyboot(); 969 970 /* 971 * Figure out how far we can extend virtual_end into segment 16 972 * without running into existing mappings. Segment 16 is guaranteed 973 * to contain neither RAM nor devices (at least on Apple hardware), 974 * but will generally contain some OFW mappings we should not 975 * step on. 976 */ 977 978 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 979 PMAP_LOCK(kernel_pmap); 980 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 981 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 982 virtual_end += PAGE_SIZE; 983 PMAP_UNLOCK(kernel_pmap); 984 #endif 985 986 /* 987 * Allocate a kernel stack with a guard page for thread0 and map it 988 * into the kernel page map. 989 */ 990 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 991 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 992 virtual_avail = va + kstack_pages * PAGE_SIZE; 993 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 994 thread0.td_kstack = va; 995 thread0.td_kstack_pages = kstack_pages; 996 for (i = 0; i < kstack_pages; i++) { 997 moea64_kenter(mmup, va, pa); 998 pa += PAGE_SIZE; 999 va += PAGE_SIZE; 1000 } 1001 1002 /* 1003 * Allocate virtual address space for the message buffer. 1004 */ 1005 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1006 msgbufp = (struct msgbuf *)virtual_avail; 1007 va = virtual_avail; 1008 virtual_avail += round_page(msgbufsize); 1009 while (va < virtual_avail) { 1010 moea64_kenter(mmup, va, pa); 1011 pa += PAGE_SIZE; 1012 va += PAGE_SIZE; 1013 } 1014 1015 /* 1016 * Allocate virtual address space for the dynamic percpu area. 1017 */ 1018 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1019 dpcpu = (void *)virtual_avail; 1020 va = virtual_avail; 1021 virtual_avail += DPCPU_SIZE; 1022 while (va < virtual_avail) { 1023 moea64_kenter(mmup, va, pa); 1024 pa += PAGE_SIZE; 1025 va += PAGE_SIZE; 1026 } 1027 dpcpu_init(dpcpu, curcpu); 1028 1029 /* 1030 * Allocate some things for page zeroing. We put this directly 1031 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1032 * of the PVO book-keeping or other parts of the VM system 1033 * from even knowing that this hack exists. 1034 */ 1035 1036 if (!hw_direct_map) { 1037 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1038 MTX_DEF); 1039 for (i = 0; i < 2; i++) { 1040 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1041 virtual_end -= PAGE_SIZE; 1042 1043 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1044 1045 PMAP_LOCK(kernel_pmap); 1046 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1047 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1048 PMAP_UNLOCK(kernel_pmap); 1049 } 1050 } 1051 } 1052 1053 static void 1054 moea64_pmap_init_qpages(void) 1055 { 1056 struct pcpu *pc; 1057 int i; 1058 1059 if (hw_direct_map) 1060 return; 1061 1062 CPU_FOREACH(i) { 1063 pc = pcpu_find(i); 1064 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1065 if (pc->pc_qmap_addr == 0) 1066 panic("pmap_init_qpages: unable to allocate KVA"); 1067 PMAP_LOCK(kernel_pmap); 1068 pc->pc_aim.qmap_pvo = 1069 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1070 PMAP_UNLOCK(kernel_pmap); 1071 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1072 } 1073 } 1074 1075 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1076 1077 /* 1078 * Activate a user pmap. This mostly involves setting some non-CPU 1079 * state. 1080 */ 1081 void 1082 moea64_activate(mmu_t mmu, struct thread *td) 1083 { 1084 pmap_t pm; 1085 1086 pm = &td->td_proc->p_vmspace->vm_pmap; 1087 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1088 1089 #ifdef __powerpc64__ 1090 PCPU_SET(aim.userslb, pm->pm_slb); 1091 __asm __volatile("slbmte %0, %1; isync" :: 1092 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1093 #else 1094 PCPU_SET(curpmap, pm->pmap_phys); 1095 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1096 #endif 1097 } 1098 1099 void 1100 moea64_deactivate(mmu_t mmu, struct thread *td) 1101 { 1102 pmap_t pm; 1103 1104 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1105 1106 pm = &td->td_proc->p_vmspace->vm_pmap; 1107 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1108 #ifdef __powerpc64__ 1109 PCPU_SET(aim.userslb, NULL); 1110 #else 1111 PCPU_SET(curpmap, NULL); 1112 #endif 1113 } 1114 1115 void 1116 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1117 { 1118 struct pvo_entry key, *pvo; 1119 vm_page_t m; 1120 int64_t refchg; 1121 1122 key.pvo_vaddr = sva; 1123 PMAP_LOCK(pm); 1124 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1125 pvo != NULL && PVO_VADDR(pvo) < eva; 1126 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1127 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1128 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1129 pvo); 1130 pvo->pvo_vaddr &= ~PVO_WIRED; 1131 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1132 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1133 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1134 if (refchg < 0) 1135 refchg = LPTE_CHG; 1136 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1137 1138 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1139 if (refchg & LPTE_CHG) 1140 vm_page_dirty(m); 1141 if (refchg & LPTE_REF) 1142 vm_page_aflag_set(m, PGA_REFERENCED); 1143 } 1144 pm->pm_stats.wired_count--; 1145 } 1146 PMAP_UNLOCK(pm); 1147 } 1148 1149 /* 1150 * This goes through and sets the physical address of our 1151 * special scratch PTE to the PA we want to zero or copy. Because 1152 * of locking issues (this can get called in pvo_enter() by 1153 * the UMA allocator), we can't use most other utility functions here 1154 */ 1155 1156 static __inline 1157 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1158 1159 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1160 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1161 1162 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1163 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1164 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1165 MOEA64_PTE_INVALIDATE); 1166 isync(); 1167 } 1168 1169 void 1170 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1171 { 1172 vm_offset_t dst; 1173 vm_offset_t src; 1174 1175 dst = VM_PAGE_TO_PHYS(mdst); 1176 src = VM_PAGE_TO_PHYS(msrc); 1177 1178 if (hw_direct_map) { 1179 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1180 PAGE_SIZE); 1181 } else { 1182 mtx_lock(&moea64_scratchpage_mtx); 1183 1184 moea64_set_scratchpage_pa(mmu, 0, src); 1185 moea64_set_scratchpage_pa(mmu, 1, dst); 1186 1187 bcopy((void *)moea64_scratchpage_va[0], 1188 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1189 1190 mtx_unlock(&moea64_scratchpage_mtx); 1191 } 1192 } 1193 1194 static inline void 1195 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1196 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1197 { 1198 void *a_cp, *b_cp; 1199 vm_offset_t a_pg_offset, b_pg_offset; 1200 int cnt; 1201 1202 while (xfersize > 0) { 1203 a_pg_offset = a_offset & PAGE_MASK; 1204 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1205 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1206 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1207 a_pg_offset; 1208 b_pg_offset = b_offset & PAGE_MASK; 1209 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1210 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1211 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1212 b_pg_offset; 1213 bcopy(a_cp, b_cp, cnt); 1214 a_offset += cnt; 1215 b_offset += cnt; 1216 xfersize -= cnt; 1217 } 1218 } 1219 1220 static inline void 1221 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1222 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1223 { 1224 void *a_cp, *b_cp; 1225 vm_offset_t a_pg_offset, b_pg_offset; 1226 int cnt; 1227 1228 mtx_lock(&moea64_scratchpage_mtx); 1229 while (xfersize > 0) { 1230 a_pg_offset = a_offset & PAGE_MASK; 1231 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1232 moea64_set_scratchpage_pa(mmu, 0, 1233 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1234 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1235 b_pg_offset = b_offset & PAGE_MASK; 1236 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1237 moea64_set_scratchpage_pa(mmu, 1, 1238 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1239 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1240 bcopy(a_cp, b_cp, cnt); 1241 a_offset += cnt; 1242 b_offset += cnt; 1243 xfersize -= cnt; 1244 } 1245 mtx_unlock(&moea64_scratchpage_mtx); 1246 } 1247 1248 void 1249 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1250 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1251 { 1252 1253 if (hw_direct_map) { 1254 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1255 xfersize); 1256 } else { 1257 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1258 xfersize); 1259 } 1260 } 1261 1262 void 1263 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1264 { 1265 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1266 1267 if (size + off > PAGE_SIZE) 1268 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1269 1270 if (hw_direct_map) { 1271 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1272 } else { 1273 mtx_lock(&moea64_scratchpage_mtx); 1274 moea64_set_scratchpage_pa(mmu, 0, pa); 1275 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1276 mtx_unlock(&moea64_scratchpage_mtx); 1277 } 1278 } 1279 1280 /* 1281 * Zero a page of physical memory by temporarily mapping it 1282 */ 1283 void 1284 moea64_zero_page(mmu_t mmu, vm_page_t m) 1285 { 1286 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1287 vm_offset_t va, off; 1288 1289 if (!hw_direct_map) { 1290 mtx_lock(&moea64_scratchpage_mtx); 1291 1292 moea64_set_scratchpage_pa(mmu, 0, pa); 1293 va = moea64_scratchpage_va[0]; 1294 } else { 1295 va = PHYS_TO_DMAP(pa); 1296 } 1297 1298 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1299 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1300 1301 if (!hw_direct_map) 1302 mtx_unlock(&moea64_scratchpage_mtx); 1303 } 1304 1305 vm_offset_t 1306 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1307 { 1308 struct pvo_entry *pvo; 1309 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1310 1311 if (hw_direct_map) 1312 return (PHYS_TO_DMAP(pa)); 1313 1314 /* 1315 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1316 * a critical section and access the PCPU data like on i386. 1317 * Instead, pin the thread and grab the PCPU lock to prevent 1318 * a preempting thread from using the same PCPU data. 1319 */ 1320 sched_pin(); 1321 1322 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1323 pvo = PCPU_GET(aim.qmap_pvo); 1324 1325 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1326 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1327 (uint64_t)pa; 1328 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1329 isync(); 1330 1331 return (PCPU_GET(qmap_addr)); 1332 } 1333 1334 void 1335 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1336 { 1337 if (hw_direct_map) 1338 return; 1339 1340 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1341 KASSERT(PCPU_GET(qmap_addr) == addr, 1342 ("moea64_quick_remove_page: invalid address")); 1343 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1344 sched_unpin(); 1345 } 1346 1347 /* 1348 * Map the given physical page at the specified virtual address in the 1349 * target pmap with the protection requested. If specified the page 1350 * will be wired down. 1351 */ 1352 1353 int 1354 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1355 vm_prot_t prot, u_int flags, int8_t psind) 1356 { 1357 struct pvo_entry *pvo, *oldpvo; 1358 struct pvo_head *pvo_head; 1359 uint64_t pte_lo; 1360 int error; 1361 1362 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1363 VM_OBJECT_ASSERT_LOCKED(m->object); 1364 1365 pvo = alloc_pvo_entry(0); 1366 pvo->pvo_pmap = NULL; /* to be filled in later */ 1367 pvo->pvo_pte.prot = prot; 1368 1369 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1370 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1371 1372 if ((flags & PMAP_ENTER_WIRED) != 0) 1373 pvo->pvo_vaddr |= PVO_WIRED; 1374 1375 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1376 pvo_head = NULL; 1377 } else { 1378 pvo_head = &m->md.mdpg_pvoh; 1379 pvo->pvo_vaddr |= PVO_MANAGED; 1380 } 1381 1382 for (;;) { 1383 PV_PAGE_LOCK(m); 1384 PMAP_LOCK(pmap); 1385 if (pvo->pvo_pmap == NULL) 1386 init_pvo_entry(pvo, pmap, va); 1387 if (prot & VM_PROT_WRITE) 1388 if (pmap_bootstrapped && 1389 (m->oflags & VPO_UNMANAGED) == 0) 1390 vm_page_aflag_set(m, PGA_WRITEABLE); 1391 1392 oldpvo = moea64_pvo_find_va(pmap, va); 1393 if (oldpvo != NULL) { 1394 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1395 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1396 oldpvo->pvo_pte.prot == prot) { 1397 /* Identical mapping already exists */ 1398 error = 0; 1399 1400 /* If not in page table, reinsert it */ 1401 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1402 moea64_pte_overflow--; 1403 MOEA64_PTE_INSERT(mmu, oldpvo); 1404 } 1405 1406 /* Then just clean up and go home */ 1407 PV_PAGE_UNLOCK(m); 1408 PMAP_UNLOCK(pmap); 1409 free_pvo_entry(pvo); 1410 break; 1411 } 1412 1413 /* Otherwise, need to kill it first */ 1414 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1415 "mapping does not match new mapping")); 1416 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1417 } 1418 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1419 PV_PAGE_UNLOCK(m); 1420 PMAP_UNLOCK(pmap); 1421 1422 /* Free any dead pages */ 1423 if (oldpvo != NULL) { 1424 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1425 moea64_pvo_remove_from_page(mmu, oldpvo); 1426 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1427 free_pvo_entry(oldpvo); 1428 } 1429 1430 if (error != ENOMEM) 1431 break; 1432 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1433 return (KERN_RESOURCE_SHORTAGE); 1434 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1435 vm_wait(NULL); 1436 } 1437 1438 /* 1439 * Flush the page from the instruction cache if this page is 1440 * mapped executable and cacheable. 1441 */ 1442 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1443 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1444 vm_page_aflag_set(m, PGA_EXECUTABLE); 1445 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1446 } 1447 return (KERN_SUCCESS); 1448 } 1449 1450 static void 1451 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1452 vm_size_t sz) 1453 { 1454 1455 /* 1456 * This is much trickier than on older systems because 1457 * we can't sync the icache on physical addresses directly 1458 * without a direct map. Instead we check a couple of cases 1459 * where the memory is already mapped in and, failing that, 1460 * use the same trick we use for page zeroing to create 1461 * a temporary mapping for this physical address. 1462 */ 1463 1464 if (!pmap_bootstrapped) { 1465 /* 1466 * If PMAP is not bootstrapped, we are likely to be 1467 * in real mode. 1468 */ 1469 __syncicache((void *)(uintptr_t)pa, sz); 1470 } else if (pmap == kernel_pmap) { 1471 __syncicache((void *)va, sz); 1472 } else if (hw_direct_map) { 1473 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1474 } else { 1475 /* Use the scratch page to set up a temp mapping */ 1476 1477 mtx_lock(&moea64_scratchpage_mtx); 1478 1479 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1480 __syncicache((void *)(moea64_scratchpage_va[1] + 1481 (va & ADDR_POFF)), sz); 1482 1483 mtx_unlock(&moea64_scratchpage_mtx); 1484 } 1485 } 1486 1487 /* 1488 * Maps a sequence of resident pages belonging to the same object. 1489 * The sequence begins with the given page m_start. This page is 1490 * mapped at the given virtual address start. Each subsequent page is 1491 * mapped at a virtual address that is offset from start by the same 1492 * amount as the page is offset from m_start within the object. The 1493 * last page in the sequence is the page with the largest offset from 1494 * m_start that can be mapped at a virtual address less than the given 1495 * virtual address end. Not every virtual page between start and end 1496 * is mapped; only those for which a resident page exists with the 1497 * corresponding offset from m_start are mapped. 1498 */ 1499 void 1500 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1501 vm_page_t m_start, vm_prot_t prot) 1502 { 1503 vm_page_t m; 1504 vm_pindex_t diff, psize; 1505 1506 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1507 1508 psize = atop(end - start); 1509 m = m_start; 1510 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1511 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1512 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1513 m = TAILQ_NEXT(m, listq); 1514 } 1515 } 1516 1517 void 1518 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1519 vm_prot_t prot) 1520 { 1521 1522 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1523 PMAP_ENTER_NOSLEEP, 0); 1524 } 1525 1526 vm_paddr_t 1527 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1528 { 1529 struct pvo_entry *pvo; 1530 vm_paddr_t pa; 1531 1532 PMAP_LOCK(pm); 1533 pvo = moea64_pvo_find_va(pm, va); 1534 if (pvo == NULL) 1535 pa = 0; 1536 else 1537 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1538 PMAP_UNLOCK(pm); 1539 1540 return (pa); 1541 } 1542 1543 /* 1544 * Atomically extract and hold the physical page with the given 1545 * pmap and virtual address pair if that mapping permits the given 1546 * protection. 1547 */ 1548 vm_page_t 1549 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1550 { 1551 struct pvo_entry *pvo; 1552 vm_page_t m; 1553 vm_paddr_t pa; 1554 1555 m = NULL; 1556 pa = 0; 1557 PMAP_LOCK(pmap); 1558 retry: 1559 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1560 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1561 if (vm_page_pa_tryrelock(pmap, 1562 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1563 goto retry; 1564 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1565 vm_page_hold(m); 1566 } 1567 PA_UNLOCK_COND(pa); 1568 PMAP_UNLOCK(pmap); 1569 return (m); 1570 } 1571 1572 static mmu_t installed_mmu; 1573 1574 static void * 1575 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1576 uint8_t *flags, int wait) 1577 { 1578 struct pvo_entry *pvo; 1579 vm_offset_t va; 1580 vm_page_t m; 1581 int needed_lock; 1582 1583 /* 1584 * This entire routine is a horrible hack to avoid bothering kmem 1585 * for new KVA addresses. Because this can get called from inside 1586 * kmem allocation routines, calling kmem for a new address here 1587 * can lead to multiply locking non-recursive mutexes. 1588 */ 1589 1590 *flags = UMA_SLAB_PRIV; 1591 needed_lock = !PMAP_LOCKED(kernel_pmap); 1592 1593 m = vm_page_alloc_domain(NULL, 0, domain, 1594 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1595 if (m == NULL) 1596 return (NULL); 1597 1598 va = VM_PAGE_TO_PHYS(m); 1599 1600 pvo = alloc_pvo_entry(1 /* bootstrap */); 1601 1602 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1603 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1604 1605 if (needed_lock) 1606 PMAP_LOCK(kernel_pmap); 1607 1608 init_pvo_entry(pvo, kernel_pmap, va); 1609 pvo->pvo_vaddr |= PVO_WIRED; 1610 1611 moea64_pvo_enter(installed_mmu, pvo, NULL); 1612 1613 if (needed_lock) 1614 PMAP_UNLOCK(kernel_pmap); 1615 1616 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1617 bzero((void *)va, PAGE_SIZE); 1618 1619 return (void *)va; 1620 } 1621 1622 extern int elf32_nxstack; 1623 1624 void 1625 moea64_init(mmu_t mmu) 1626 { 1627 1628 CTR0(KTR_PMAP, "moea64_init"); 1629 1630 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1631 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1632 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1633 1634 if (!hw_direct_map) { 1635 installed_mmu = mmu; 1636 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1637 } 1638 1639 #ifdef COMPAT_FREEBSD32 1640 elf32_nxstack = 1; 1641 #endif 1642 1643 moea64_initialized = TRUE; 1644 } 1645 1646 boolean_t 1647 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1648 { 1649 1650 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1651 ("moea64_is_referenced: page %p is not managed", m)); 1652 1653 return (moea64_query_bit(mmu, m, LPTE_REF)); 1654 } 1655 1656 boolean_t 1657 moea64_is_modified(mmu_t mmu, vm_page_t m) 1658 { 1659 1660 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1661 ("moea64_is_modified: page %p is not managed", m)); 1662 1663 /* 1664 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1665 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1666 * is clear, no PTEs can have LPTE_CHG set. 1667 */ 1668 VM_OBJECT_ASSERT_LOCKED(m->object); 1669 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1670 return (FALSE); 1671 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1672 } 1673 1674 boolean_t 1675 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1676 { 1677 struct pvo_entry *pvo; 1678 boolean_t rv = TRUE; 1679 1680 PMAP_LOCK(pmap); 1681 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1682 if (pvo != NULL) 1683 rv = FALSE; 1684 PMAP_UNLOCK(pmap); 1685 return (rv); 1686 } 1687 1688 void 1689 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1690 { 1691 1692 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1693 ("moea64_clear_modify: page %p is not managed", m)); 1694 VM_OBJECT_ASSERT_WLOCKED(m->object); 1695 KASSERT(!vm_page_xbusied(m), 1696 ("moea64_clear_modify: page %p is exclusive busied", m)); 1697 1698 /* 1699 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1700 * set. If the object containing the page is locked and the page is 1701 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1702 */ 1703 if ((m->aflags & PGA_WRITEABLE) == 0) 1704 return; 1705 moea64_clear_bit(mmu, m, LPTE_CHG); 1706 } 1707 1708 /* 1709 * Clear the write and modified bits in each of the given page's mappings. 1710 */ 1711 void 1712 moea64_remove_write(mmu_t mmu, vm_page_t m) 1713 { 1714 struct pvo_entry *pvo; 1715 int64_t refchg, ret; 1716 pmap_t pmap; 1717 1718 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1719 ("moea64_remove_write: page %p is not managed", m)); 1720 1721 /* 1722 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1723 * set by another thread while the object is locked. Thus, 1724 * if PGA_WRITEABLE is clear, no page table entries need updating. 1725 */ 1726 VM_OBJECT_ASSERT_WLOCKED(m->object); 1727 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1728 return; 1729 powerpc_sync(); 1730 PV_PAGE_LOCK(m); 1731 refchg = 0; 1732 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1733 pmap = pvo->pvo_pmap; 1734 PMAP_LOCK(pmap); 1735 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1736 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1737 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1738 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1739 MOEA64_PTE_PROT_UPDATE); 1740 if (ret < 0) 1741 ret = LPTE_CHG; 1742 refchg |= ret; 1743 if (pvo->pvo_pmap == kernel_pmap) 1744 isync(); 1745 } 1746 PMAP_UNLOCK(pmap); 1747 } 1748 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1749 vm_page_dirty(m); 1750 vm_page_aflag_clear(m, PGA_WRITEABLE); 1751 PV_PAGE_UNLOCK(m); 1752 } 1753 1754 /* 1755 * moea64_ts_referenced: 1756 * 1757 * Return a count of reference bits for a page, clearing those bits. 1758 * It is not necessary for every reference bit to be cleared, but it 1759 * is necessary that 0 only be returned when there are truly no 1760 * reference bits set. 1761 * 1762 * XXX: The exact number of bits to check and clear is a matter that 1763 * should be tested and standardized at some point in the future for 1764 * optimal aging of shared pages. 1765 */ 1766 int 1767 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1768 { 1769 1770 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1771 ("moea64_ts_referenced: page %p is not managed", m)); 1772 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1773 } 1774 1775 /* 1776 * Modify the WIMG settings of all mappings for a page. 1777 */ 1778 void 1779 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1780 { 1781 struct pvo_entry *pvo; 1782 int64_t refchg; 1783 pmap_t pmap; 1784 uint64_t lo; 1785 1786 if ((m->oflags & VPO_UNMANAGED) != 0) { 1787 m->md.mdpg_cache_attrs = ma; 1788 return; 1789 } 1790 1791 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1792 1793 PV_PAGE_LOCK(m); 1794 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1795 pmap = pvo->pvo_pmap; 1796 PMAP_LOCK(pmap); 1797 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1798 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1799 pvo->pvo_pte.pa |= lo; 1800 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1801 MOEA64_PTE_INVALIDATE); 1802 if (refchg < 0) 1803 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1804 LPTE_CHG : 0; 1805 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1806 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1807 refchg |= 1808 atomic_readandclear_32(&m->md.mdpg_attrs); 1809 if (refchg & LPTE_CHG) 1810 vm_page_dirty(m); 1811 if (refchg & LPTE_REF) 1812 vm_page_aflag_set(m, PGA_REFERENCED); 1813 } 1814 if (pvo->pvo_pmap == kernel_pmap) 1815 isync(); 1816 } 1817 PMAP_UNLOCK(pmap); 1818 } 1819 m->md.mdpg_cache_attrs = ma; 1820 PV_PAGE_UNLOCK(m); 1821 } 1822 1823 /* 1824 * Map a wired page into kernel virtual address space. 1825 */ 1826 void 1827 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1828 { 1829 int error; 1830 struct pvo_entry *pvo, *oldpvo; 1831 1832 pvo = alloc_pvo_entry(0); 1833 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1834 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1835 pvo->pvo_vaddr |= PVO_WIRED; 1836 1837 PMAP_LOCK(kernel_pmap); 1838 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1839 if (oldpvo != NULL) 1840 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1841 init_pvo_entry(pvo, kernel_pmap, va); 1842 error = moea64_pvo_enter(mmu, pvo, NULL); 1843 PMAP_UNLOCK(kernel_pmap); 1844 1845 /* Free any dead pages */ 1846 if (oldpvo != NULL) { 1847 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1848 moea64_pvo_remove_from_page(mmu, oldpvo); 1849 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1850 free_pvo_entry(oldpvo); 1851 } 1852 1853 if (error != 0 && error != ENOENT) 1854 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1855 (uintmax_t)pa, error); 1856 } 1857 1858 void 1859 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1860 { 1861 1862 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1863 } 1864 1865 /* 1866 * Extract the physical page address associated with the given kernel virtual 1867 * address. 1868 */ 1869 vm_paddr_t 1870 moea64_kextract(mmu_t mmu, vm_offset_t va) 1871 { 1872 struct pvo_entry *pvo; 1873 vm_paddr_t pa; 1874 1875 /* 1876 * Shortcut the direct-mapped case when applicable. We never put 1877 * anything but 1:1 (or 62-bit aliased) mappings below 1878 * VM_MIN_KERNEL_ADDRESS. 1879 */ 1880 if (va < VM_MIN_KERNEL_ADDRESS) 1881 return (va & ~DMAP_BASE_ADDRESS); 1882 1883 PMAP_LOCK(kernel_pmap); 1884 pvo = moea64_pvo_find_va(kernel_pmap, va); 1885 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1886 va)); 1887 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1888 PMAP_UNLOCK(kernel_pmap); 1889 return (pa); 1890 } 1891 1892 /* 1893 * Remove a wired page from kernel virtual address space. 1894 */ 1895 void 1896 moea64_kremove(mmu_t mmu, vm_offset_t va) 1897 { 1898 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1899 } 1900 1901 /* 1902 * Provide a kernel pointer corresponding to a given userland pointer. 1903 * The returned pointer is valid until the next time this function is 1904 * called in this thread. This is used internally in copyin/copyout. 1905 */ 1906 static int 1907 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1908 void **kaddr, size_t ulen, size_t *klen) 1909 { 1910 size_t l; 1911 #ifdef __powerpc64__ 1912 struct slb *slb; 1913 #endif 1914 register_t slbv; 1915 1916 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1917 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1918 if (l > ulen) 1919 l = ulen; 1920 if (klen) 1921 *klen = l; 1922 else if (l != ulen) 1923 return (EFAULT); 1924 1925 #ifdef __powerpc64__ 1926 /* Try lockless look-up first */ 1927 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1928 1929 if (slb == NULL) { 1930 /* If it isn't there, we need to pre-fault the VSID */ 1931 PMAP_LOCK(pm); 1932 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1933 PMAP_UNLOCK(pm); 1934 } else { 1935 slbv = slb->slbv; 1936 } 1937 1938 /* Mark segment no-execute */ 1939 slbv |= SLBV_N; 1940 #else 1941 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1942 1943 /* Mark segment no-execute */ 1944 slbv |= SR_N; 1945 #endif 1946 1947 /* If we have already set this VSID, we can just return */ 1948 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1949 return (0); 1950 1951 __asm __volatile("isync"); 1952 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1953 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1954 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1955 #ifdef __powerpc64__ 1956 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1957 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1958 #else 1959 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1960 #endif 1961 1962 return (0); 1963 } 1964 1965 /* 1966 * Figure out where a given kernel pointer (usually in a fault) points 1967 * to from the VM's perspective, potentially remapping into userland's 1968 * address space. 1969 */ 1970 static int 1971 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1972 vm_offset_t *decoded_addr) 1973 { 1974 vm_offset_t user_sr; 1975 1976 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1977 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1978 addr &= ADDR_PIDX | ADDR_POFF; 1979 addr |= user_sr << ADDR_SR_SHFT; 1980 *decoded_addr = addr; 1981 *is_user = 1; 1982 } else { 1983 *decoded_addr = addr; 1984 *is_user = 0; 1985 } 1986 1987 return (0); 1988 } 1989 1990 /* 1991 * Map a range of physical addresses into kernel virtual address space. 1992 * 1993 * The value passed in *virt is a suggested virtual address for the mapping. 1994 * Architectures which can support a direct-mapped physical to virtual region 1995 * can return the appropriate address within that region, leaving '*virt' 1996 * unchanged. Other architectures should map the pages starting at '*virt' and 1997 * update '*virt' with the first usable address after the mapped region. 1998 */ 1999 vm_offset_t 2000 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2001 vm_paddr_t pa_end, int prot) 2002 { 2003 vm_offset_t sva, va; 2004 2005 if (hw_direct_map) { 2006 /* 2007 * Check if every page in the region is covered by the direct 2008 * map. The direct map covers all of physical memory. Use 2009 * moea64_calc_wimg() as a shortcut to see if the page is in 2010 * physical memory as a way to see if the direct map covers it. 2011 */ 2012 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2013 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2014 break; 2015 if (va == pa_end) 2016 return (PHYS_TO_DMAP(pa_start)); 2017 } 2018 sva = *virt; 2019 va = sva; 2020 /* XXX respect prot argument */ 2021 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2022 moea64_kenter(mmu, va, pa_start); 2023 *virt = va; 2024 2025 return (sva); 2026 } 2027 2028 /* 2029 * Returns true if the pmap's pv is one of the first 2030 * 16 pvs linked to from this page. This count may 2031 * be changed upwards or downwards in the future; it 2032 * is only necessary that true be returned for a small 2033 * subset of pmaps for proper page aging. 2034 */ 2035 boolean_t 2036 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2037 { 2038 int loops; 2039 struct pvo_entry *pvo; 2040 boolean_t rv; 2041 2042 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2043 ("moea64_page_exists_quick: page %p is not managed", m)); 2044 loops = 0; 2045 rv = FALSE; 2046 PV_PAGE_LOCK(m); 2047 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2048 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2049 rv = TRUE; 2050 break; 2051 } 2052 if (++loops >= 16) 2053 break; 2054 } 2055 PV_PAGE_UNLOCK(m); 2056 return (rv); 2057 } 2058 2059 void 2060 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2061 { 2062 2063 m->md.mdpg_attrs = 0; 2064 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2065 LIST_INIT(&m->md.mdpg_pvoh); 2066 } 2067 2068 /* 2069 * Return the number of managed mappings to the given physical page 2070 * that are wired. 2071 */ 2072 int 2073 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2074 { 2075 struct pvo_entry *pvo; 2076 int count; 2077 2078 count = 0; 2079 if ((m->oflags & VPO_UNMANAGED) != 0) 2080 return (count); 2081 PV_PAGE_LOCK(m); 2082 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2083 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2084 count++; 2085 PV_PAGE_UNLOCK(m); 2086 return (count); 2087 } 2088 2089 static uintptr_t moea64_vsidcontext; 2090 2091 uintptr_t 2092 moea64_get_unique_vsid(void) { 2093 u_int entropy; 2094 register_t hash; 2095 uint32_t mask; 2096 int i; 2097 2098 entropy = 0; 2099 __asm __volatile("mftb %0" : "=r"(entropy)); 2100 2101 mtx_lock(&moea64_slb_mutex); 2102 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2103 u_int n; 2104 2105 /* 2106 * Create a new value by mutiplying by a prime and adding in 2107 * entropy from the timebase register. This is to make the 2108 * VSID more random so that the PT hash function collides 2109 * less often. (Note that the prime casues gcc to do shifts 2110 * instead of a multiply.) 2111 */ 2112 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2113 hash = moea64_vsidcontext & (NVSIDS - 1); 2114 if (hash == 0) /* 0 is special, avoid it */ 2115 continue; 2116 n = hash >> 5; 2117 mask = 1 << (hash & (VSID_NBPW - 1)); 2118 hash = (moea64_vsidcontext & VSID_HASHMASK); 2119 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2120 /* anything free in this bucket? */ 2121 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2122 entropy = (moea64_vsidcontext >> 20); 2123 continue; 2124 } 2125 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2126 mask = 1 << i; 2127 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2128 hash |= i; 2129 } 2130 if (hash == VSID_VRMA) /* also special, avoid this too */ 2131 continue; 2132 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2133 ("Allocating in-use VSID %#zx\n", hash)); 2134 moea64_vsid_bitmap[n] |= mask; 2135 mtx_unlock(&moea64_slb_mutex); 2136 return (hash); 2137 } 2138 2139 mtx_unlock(&moea64_slb_mutex); 2140 panic("%s: out of segments",__func__); 2141 } 2142 2143 #ifdef __powerpc64__ 2144 void 2145 moea64_pinit(mmu_t mmu, pmap_t pmap) 2146 { 2147 2148 RB_INIT(&pmap->pmap_pvo); 2149 2150 pmap->pm_slb_tree_root = slb_alloc_tree(); 2151 pmap->pm_slb = slb_alloc_user_cache(); 2152 pmap->pm_slb_len = 0; 2153 } 2154 #else 2155 void 2156 moea64_pinit(mmu_t mmu, pmap_t pmap) 2157 { 2158 int i; 2159 uint32_t hash; 2160 2161 RB_INIT(&pmap->pmap_pvo); 2162 2163 if (pmap_bootstrapped) 2164 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2165 (vm_offset_t)pmap); 2166 else 2167 pmap->pmap_phys = pmap; 2168 2169 /* 2170 * Allocate some segment registers for this pmap. 2171 */ 2172 hash = moea64_get_unique_vsid(); 2173 2174 for (i = 0; i < 16; i++) 2175 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2176 2177 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2178 } 2179 #endif 2180 2181 /* 2182 * Initialize the pmap associated with process 0. 2183 */ 2184 void 2185 moea64_pinit0(mmu_t mmu, pmap_t pm) 2186 { 2187 2188 PMAP_LOCK_INIT(pm); 2189 moea64_pinit(mmu, pm); 2190 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2191 } 2192 2193 /* 2194 * Set the physical protection on the specified range of this map as requested. 2195 */ 2196 static void 2197 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2198 { 2199 struct vm_page *pg; 2200 vm_prot_t oldprot; 2201 int32_t refchg; 2202 2203 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2204 2205 /* 2206 * Change the protection of the page. 2207 */ 2208 oldprot = pvo->pvo_pte.prot; 2209 pvo->pvo_pte.prot = prot; 2210 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2211 2212 /* 2213 * If the PVO is in the page table, update mapping 2214 */ 2215 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2216 if (refchg < 0) 2217 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2218 2219 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2220 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2221 if ((pg->oflags & VPO_UNMANAGED) == 0) 2222 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2223 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2224 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2225 } 2226 2227 /* 2228 * Update vm about the REF/CHG bits if the page is managed and we have 2229 * removed write access. 2230 */ 2231 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2232 (oldprot & VM_PROT_WRITE)) { 2233 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2234 if (refchg & LPTE_CHG) 2235 vm_page_dirty(pg); 2236 if (refchg & LPTE_REF) 2237 vm_page_aflag_set(pg, PGA_REFERENCED); 2238 } 2239 } 2240 2241 void 2242 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2243 vm_prot_t prot) 2244 { 2245 struct pvo_entry *pvo, *tpvo, key; 2246 2247 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2248 sva, eva, prot); 2249 2250 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2251 ("moea64_protect: non current pmap")); 2252 2253 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2254 moea64_remove(mmu, pm, sva, eva); 2255 return; 2256 } 2257 2258 PMAP_LOCK(pm); 2259 key.pvo_vaddr = sva; 2260 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2261 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2262 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2263 moea64_pvo_protect(mmu, pm, pvo, prot); 2264 } 2265 PMAP_UNLOCK(pm); 2266 } 2267 2268 /* 2269 * Map a list of wired pages into kernel virtual address space. This is 2270 * intended for temporary mappings which do not need page modification or 2271 * references recorded. Existing mappings in the region are overwritten. 2272 */ 2273 void 2274 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2275 { 2276 while (count-- > 0) { 2277 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2278 va += PAGE_SIZE; 2279 m++; 2280 } 2281 } 2282 2283 /* 2284 * Remove page mappings from kernel virtual address space. Intended for 2285 * temporary mappings entered by moea64_qenter. 2286 */ 2287 void 2288 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2289 { 2290 while (count-- > 0) { 2291 moea64_kremove(mmu, va); 2292 va += PAGE_SIZE; 2293 } 2294 } 2295 2296 void 2297 moea64_release_vsid(uint64_t vsid) 2298 { 2299 int idx, mask; 2300 2301 mtx_lock(&moea64_slb_mutex); 2302 idx = vsid & (NVSIDS-1); 2303 mask = 1 << (idx % VSID_NBPW); 2304 idx /= VSID_NBPW; 2305 KASSERT(moea64_vsid_bitmap[idx] & mask, 2306 ("Freeing unallocated VSID %#jx", vsid)); 2307 moea64_vsid_bitmap[idx] &= ~mask; 2308 mtx_unlock(&moea64_slb_mutex); 2309 } 2310 2311 2312 void 2313 moea64_release(mmu_t mmu, pmap_t pmap) 2314 { 2315 2316 /* 2317 * Free segment registers' VSIDs 2318 */ 2319 #ifdef __powerpc64__ 2320 slb_free_tree(pmap); 2321 slb_free_user_cache(pmap->pm_slb); 2322 #else 2323 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2324 2325 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2326 #endif 2327 } 2328 2329 /* 2330 * Remove all pages mapped by the specified pmap 2331 */ 2332 void 2333 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2334 { 2335 struct pvo_entry *pvo, *tpvo; 2336 struct pvo_tree tofree; 2337 2338 RB_INIT(&tofree); 2339 2340 PMAP_LOCK(pm); 2341 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2342 if (pvo->pvo_vaddr & PVO_WIRED) 2343 continue; 2344 2345 /* 2346 * For locking reasons, remove this from the page table and 2347 * pmap, but save delinking from the vm_page for a second 2348 * pass 2349 */ 2350 moea64_pvo_remove_from_pmap(mmu, pvo); 2351 RB_INSERT(pvo_tree, &tofree, pvo); 2352 } 2353 PMAP_UNLOCK(pm); 2354 2355 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2356 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2357 moea64_pvo_remove_from_page(mmu, pvo); 2358 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2359 RB_REMOVE(pvo_tree, &tofree, pvo); 2360 free_pvo_entry(pvo); 2361 } 2362 } 2363 2364 /* 2365 * Remove the given range of addresses from the specified map. 2366 */ 2367 void 2368 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2369 { 2370 struct pvo_entry *pvo, *tpvo, key; 2371 struct pvo_tree tofree; 2372 2373 /* 2374 * Perform an unsynchronized read. This is, however, safe. 2375 */ 2376 if (pm->pm_stats.resident_count == 0) 2377 return; 2378 2379 key.pvo_vaddr = sva; 2380 2381 RB_INIT(&tofree); 2382 2383 PMAP_LOCK(pm); 2384 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2385 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2386 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2387 2388 /* 2389 * For locking reasons, remove this from the page table and 2390 * pmap, but save delinking from the vm_page for a second 2391 * pass 2392 */ 2393 moea64_pvo_remove_from_pmap(mmu, pvo); 2394 RB_INSERT(pvo_tree, &tofree, pvo); 2395 } 2396 PMAP_UNLOCK(pm); 2397 2398 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2399 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2400 moea64_pvo_remove_from_page(mmu, pvo); 2401 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2402 RB_REMOVE(pvo_tree, &tofree, pvo); 2403 free_pvo_entry(pvo); 2404 } 2405 } 2406 2407 /* 2408 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2409 * will reflect changes in pte's back to the vm_page. 2410 */ 2411 void 2412 moea64_remove_all(mmu_t mmu, vm_page_t m) 2413 { 2414 struct pvo_entry *pvo, *next_pvo; 2415 struct pvo_head freequeue; 2416 int wasdead; 2417 pmap_t pmap; 2418 2419 LIST_INIT(&freequeue); 2420 2421 PV_PAGE_LOCK(m); 2422 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2423 pmap = pvo->pvo_pmap; 2424 PMAP_LOCK(pmap); 2425 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2426 if (!wasdead) 2427 moea64_pvo_remove_from_pmap(mmu, pvo); 2428 moea64_pvo_remove_from_page(mmu, pvo); 2429 if (!wasdead) 2430 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2431 PMAP_UNLOCK(pmap); 2432 2433 } 2434 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2435 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2436 PV_PAGE_UNLOCK(m); 2437 2438 /* Clean up UMA allocations */ 2439 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2440 free_pvo_entry(pvo); 2441 } 2442 2443 /* 2444 * Allocate a physical page of memory directly from the phys_avail map. 2445 * Can only be called from moea64_bootstrap before avail start and end are 2446 * calculated. 2447 */ 2448 vm_offset_t 2449 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2450 { 2451 vm_offset_t s, e; 2452 int i, j; 2453 2454 size = round_page(size); 2455 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2456 if (align != 0) 2457 s = roundup2(phys_avail[i], align); 2458 else 2459 s = phys_avail[i]; 2460 e = s + size; 2461 2462 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2463 continue; 2464 2465 if (s + size > platform_real_maxaddr()) 2466 continue; 2467 2468 if (s == phys_avail[i]) { 2469 phys_avail[i] += size; 2470 } else if (e == phys_avail[i + 1]) { 2471 phys_avail[i + 1] -= size; 2472 } else { 2473 for (j = phys_avail_count * 2; j > i; j -= 2) { 2474 phys_avail[j] = phys_avail[j - 2]; 2475 phys_avail[j + 1] = phys_avail[j - 1]; 2476 } 2477 2478 phys_avail[i + 3] = phys_avail[i + 1]; 2479 phys_avail[i + 1] = s; 2480 phys_avail[i + 2] = e; 2481 phys_avail_count++; 2482 } 2483 2484 return (s); 2485 } 2486 panic("moea64_bootstrap_alloc: could not allocate memory"); 2487 } 2488 2489 static int 2490 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2491 { 2492 int first, err; 2493 2494 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2495 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2496 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2497 2498 moea64_pvo_enter_calls++; 2499 2500 /* 2501 * Add to pmap list 2502 */ 2503 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2504 2505 /* 2506 * Remember if the list was empty and therefore will be the first 2507 * item. 2508 */ 2509 if (pvo_head != NULL) { 2510 if (LIST_FIRST(pvo_head) == NULL) 2511 first = 1; 2512 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2513 } 2514 2515 if (pvo->pvo_vaddr & PVO_WIRED) 2516 pvo->pvo_pmap->pm_stats.wired_count++; 2517 pvo->pvo_pmap->pm_stats.resident_count++; 2518 2519 /* 2520 * Insert it into the hardware page table 2521 */ 2522 err = MOEA64_PTE_INSERT(mmu, pvo); 2523 if (err != 0) { 2524 panic("moea64_pvo_enter: overflow"); 2525 } 2526 2527 moea64_pvo_entries++; 2528 2529 if (pvo->pvo_pmap == kernel_pmap) 2530 isync(); 2531 2532 #ifdef __powerpc64__ 2533 /* 2534 * Make sure all our bootstrap mappings are in the SLB as soon 2535 * as virtual memory is switched on. 2536 */ 2537 if (!pmap_bootstrapped) 2538 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2539 pvo->pvo_vaddr & PVO_LARGE); 2540 #endif 2541 2542 return (first ? ENOENT : 0); 2543 } 2544 2545 static void 2546 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2547 { 2548 struct vm_page *pg; 2549 int32_t refchg; 2550 2551 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2552 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2553 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2554 2555 /* 2556 * If there is an active pte entry, we need to deactivate it 2557 */ 2558 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2559 if (refchg < 0) { 2560 /* 2561 * If it was evicted from the page table, be pessimistic and 2562 * dirty the page. 2563 */ 2564 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2565 refchg = LPTE_CHG; 2566 else 2567 refchg = 0; 2568 } 2569 2570 /* 2571 * Update our statistics. 2572 */ 2573 pvo->pvo_pmap->pm_stats.resident_count--; 2574 if (pvo->pvo_vaddr & PVO_WIRED) 2575 pvo->pvo_pmap->pm_stats.wired_count--; 2576 2577 /* 2578 * Remove this PVO from the pmap list. 2579 */ 2580 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2581 2582 /* 2583 * Mark this for the next sweep 2584 */ 2585 pvo->pvo_vaddr |= PVO_DEAD; 2586 2587 /* Send RC bits to VM */ 2588 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2589 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2590 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2591 if (pg != NULL) { 2592 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2593 if (refchg & LPTE_CHG) 2594 vm_page_dirty(pg); 2595 if (refchg & LPTE_REF) 2596 vm_page_aflag_set(pg, PGA_REFERENCED); 2597 } 2598 } 2599 } 2600 2601 static void 2602 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2603 { 2604 struct vm_page *pg; 2605 2606 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2607 2608 /* Use NULL pmaps as a sentinel for races in page deletion */ 2609 if (pvo->pvo_pmap == NULL) 2610 return; 2611 pvo->pvo_pmap = NULL; 2612 2613 /* 2614 * Update vm about page writeability/executability if managed 2615 */ 2616 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2617 if (pvo->pvo_vaddr & PVO_MANAGED) { 2618 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2619 2620 if (pg != NULL) { 2621 LIST_REMOVE(pvo, pvo_vlink); 2622 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2623 vm_page_aflag_clear(pg, 2624 PGA_WRITEABLE | PGA_EXECUTABLE); 2625 } 2626 } 2627 2628 moea64_pvo_entries--; 2629 moea64_pvo_remove_calls++; 2630 } 2631 2632 static struct pvo_entry * 2633 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2634 { 2635 struct pvo_entry key; 2636 2637 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2638 2639 key.pvo_vaddr = va & ~ADDR_POFF; 2640 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2641 } 2642 2643 static boolean_t 2644 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2645 { 2646 struct pvo_entry *pvo; 2647 int64_t ret; 2648 boolean_t rv; 2649 2650 /* 2651 * See if this bit is stored in the page already. 2652 */ 2653 if (m->md.mdpg_attrs & ptebit) 2654 return (TRUE); 2655 2656 /* 2657 * Examine each PTE. Sync so that any pending REF/CHG bits are 2658 * flushed to the PTEs. 2659 */ 2660 rv = FALSE; 2661 powerpc_sync(); 2662 PV_PAGE_LOCK(m); 2663 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2664 ret = 0; 2665 2666 /* 2667 * See if this pvo has a valid PTE. if so, fetch the 2668 * REF/CHG bits from the valid PTE. If the appropriate 2669 * ptebit is set, return success. 2670 */ 2671 PMAP_LOCK(pvo->pvo_pmap); 2672 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2673 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2674 PMAP_UNLOCK(pvo->pvo_pmap); 2675 2676 if (ret > 0) { 2677 atomic_set_32(&m->md.mdpg_attrs, 2678 ret & (LPTE_CHG | LPTE_REF)); 2679 if (ret & ptebit) { 2680 rv = TRUE; 2681 break; 2682 } 2683 } 2684 } 2685 PV_PAGE_UNLOCK(m); 2686 2687 return (rv); 2688 } 2689 2690 static u_int 2691 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2692 { 2693 u_int count; 2694 struct pvo_entry *pvo; 2695 int64_t ret; 2696 2697 /* 2698 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2699 * we can reset the right ones). 2700 */ 2701 powerpc_sync(); 2702 2703 /* 2704 * For each pvo entry, clear the pte's ptebit. 2705 */ 2706 count = 0; 2707 PV_PAGE_LOCK(m); 2708 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2709 ret = 0; 2710 2711 PMAP_LOCK(pvo->pvo_pmap); 2712 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2713 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2714 PMAP_UNLOCK(pvo->pvo_pmap); 2715 2716 if (ret > 0 && (ret & ptebit)) 2717 count++; 2718 } 2719 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2720 PV_PAGE_UNLOCK(m); 2721 2722 return (count); 2723 } 2724 2725 boolean_t 2726 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2727 { 2728 struct pvo_entry *pvo, key; 2729 vm_offset_t ppa; 2730 int error = 0; 2731 2732 if (hw_direct_map && mem_valid(pa, size) == 0) 2733 return (0); 2734 2735 PMAP_LOCK(kernel_pmap); 2736 ppa = pa & ~ADDR_POFF; 2737 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2738 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2739 ppa < pa + size; ppa += PAGE_SIZE, 2740 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2741 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2742 error = EFAULT; 2743 break; 2744 } 2745 } 2746 PMAP_UNLOCK(kernel_pmap); 2747 2748 return (error); 2749 } 2750 2751 /* 2752 * Map a set of physical memory pages into the kernel virtual 2753 * address space. Return a pointer to where it is mapped. This 2754 * routine is intended to be used for mapping device memory, 2755 * NOT real memory. 2756 */ 2757 void * 2758 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2759 { 2760 vm_offset_t va, tmpva, ppa, offset; 2761 2762 ppa = trunc_page(pa); 2763 offset = pa & PAGE_MASK; 2764 size = roundup2(offset + size, PAGE_SIZE); 2765 2766 va = kva_alloc(size); 2767 2768 if (!va) 2769 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2770 2771 for (tmpva = va; size > 0;) { 2772 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2773 size -= PAGE_SIZE; 2774 tmpva += PAGE_SIZE; 2775 ppa += PAGE_SIZE; 2776 } 2777 2778 return ((void *)(va + offset)); 2779 } 2780 2781 void * 2782 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2783 { 2784 2785 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2786 } 2787 2788 void 2789 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2790 { 2791 vm_offset_t base, offset; 2792 2793 base = trunc_page(va); 2794 offset = va & PAGE_MASK; 2795 size = roundup2(offset + size, PAGE_SIZE); 2796 2797 kva_free(base, size); 2798 } 2799 2800 void 2801 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2802 { 2803 struct pvo_entry *pvo; 2804 vm_offset_t lim; 2805 vm_paddr_t pa; 2806 vm_size_t len; 2807 2808 PMAP_LOCK(pm); 2809 while (sz > 0) { 2810 lim = round_page(va+1); 2811 len = MIN(lim - va, sz); 2812 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2813 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2814 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2815 moea64_syncicache(mmu, pm, va, pa, len); 2816 } 2817 va += len; 2818 sz -= len; 2819 } 2820 PMAP_UNLOCK(pm); 2821 } 2822 2823 void 2824 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2825 { 2826 2827 *va = (void *)(uintptr_t)pa; 2828 } 2829 2830 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2831 2832 void 2833 moea64_scan_init(mmu_t mmu) 2834 { 2835 struct pvo_entry *pvo; 2836 vm_offset_t va; 2837 int i; 2838 2839 if (!do_minidump) { 2840 /* Initialize phys. segments for dumpsys(). */ 2841 memset(&dump_map, 0, sizeof(dump_map)); 2842 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2843 for (i = 0; i < pregions_sz; i++) { 2844 dump_map[i].pa_start = pregions[i].mr_start; 2845 dump_map[i].pa_size = pregions[i].mr_size; 2846 } 2847 return; 2848 } 2849 2850 /* Virtual segments for minidumps: */ 2851 memset(&dump_map, 0, sizeof(dump_map)); 2852 2853 /* 1st: kernel .data and .bss. */ 2854 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2855 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2856 dump_map[0].pa_start; 2857 2858 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2859 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2860 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2861 2862 /* 3rd: kernel VM. */ 2863 va = dump_map[1].pa_start + dump_map[1].pa_size; 2864 /* Find start of next chunk (from va). */ 2865 while (va < virtual_end) { 2866 /* Don't dump the buffer cache. */ 2867 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2868 va = kmi.buffer_eva; 2869 continue; 2870 } 2871 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2872 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2873 break; 2874 va += PAGE_SIZE; 2875 } 2876 if (va < virtual_end) { 2877 dump_map[2].pa_start = va; 2878 va += PAGE_SIZE; 2879 /* Find last page in chunk. */ 2880 while (va < virtual_end) { 2881 /* Don't run into the buffer cache. */ 2882 if (va == kmi.buffer_sva) 2883 break; 2884 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2885 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2886 break; 2887 va += PAGE_SIZE; 2888 } 2889 dump_map[2].pa_size = va - dump_map[2].pa_start; 2890 } 2891 } 2892 2893