1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_compat.h" 106 #include "opt_kstack_pages.h" 107 108 #include <sys/param.h> 109 #include <sys/kernel.h> 110 #include <sys/conf.h> 111 #include <sys/queue.h> 112 #include <sys/cpuset.h> 113 #include <sys/kerneldump.h> 114 #include <sys/ktr.h> 115 #include <sys/lock.h> 116 #include <sys/msgbuf.h> 117 #include <sys/malloc.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <sys/kdb.h> 127 128 #include <dev/ofw/openfirm.h> 129 130 #include <vm/vm.h> 131 #include <vm/vm_param.h> 132 #include <vm/vm_kern.h> 133 #include <vm/vm_page.h> 134 #include <vm/vm_map.h> 135 #include <vm/vm_object.h> 136 #include <vm/vm_extern.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/_inttypes.h> 141 #include <machine/cpu.h> 142 #include <machine/platform.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/bat.h> 147 #include <machine/hid.h> 148 #include <machine/pte.h> 149 #include <machine/sr.h> 150 #include <machine/trap.h> 151 #include <machine/mmuvar.h> 152 153 #include "mmu_oea64.h" 154 #include "mmu_if.h" 155 #include "moea64_if.h" 156 157 void moea64_release_vsid(uint64_t vsid); 158 uintptr_t moea64_get_unique_vsid(void); 159 160 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 161 #define ENABLE_TRANS(msr) mtmsr(msr) 162 163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 165 #define VSID_HASH_MASK 0x0000007fffffffffULL 166 167 /* 168 * Locking semantics: 169 * -- Read lock: if no modifications are being made to either the PVO lists 170 * or page table or if any modifications being made result in internal 171 * changes (e.g. wiring, protection) such that the existence of the PVOs 172 * is unchanged and they remain associated with the same pmap (in which 173 * case the changes should be protected by the pmap lock) 174 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 175 */ 176 177 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 178 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 179 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 180 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 181 182 struct ofw_map { 183 cell_t om_va; 184 cell_t om_len; 185 uint64_t om_pa; 186 cell_t om_mode; 187 }; 188 189 extern unsigned char _etext[]; 190 extern unsigned char _end[]; 191 192 extern int ofw_real_mode; 193 194 /* 195 * Map of physical memory regions. 196 */ 197 static struct mem_region *regions; 198 static struct mem_region *pregions; 199 static u_int phys_avail_count; 200 static int regions_sz, pregions_sz; 201 202 extern void bs_remap_earlyboot(void); 203 204 /* 205 * Lock for the pteg and pvo tables. 206 */ 207 struct rwlock moea64_table_lock; 208 struct mtx moea64_slb_mutex; 209 210 /* 211 * PTEG data. 212 */ 213 u_int moea64_pteg_count; 214 u_int moea64_pteg_mask; 215 216 /* 217 * PVO data. 218 */ 219 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 220 221 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 222 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 223 224 static struct pvo_entry *moea64_bpvo_pool; 225 static int moea64_bpvo_pool_index = 0; 226 static int moea64_bpvo_pool_size = 327680; 227 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 228 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 229 &moea64_bpvo_pool_index, 0, ""); 230 231 #define VSID_NBPW (sizeof(u_int32_t) * 8) 232 #ifdef __powerpc64__ 233 #define NVSIDS (NPMAPS * 16) 234 #define VSID_HASHMASK 0xffffffffUL 235 #else 236 #define NVSIDS NPMAPS 237 #define VSID_HASHMASK 0xfffffUL 238 #endif 239 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 240 241 static boolean_t moea64_initialized = FALSE; 242 243 /* 244 * Statistics. 245 */ 246 u_int moea64_pte_valid = 0; 247 u_int moea64_pte_overflow = 0; 248 u_int moea64_pvo_entries = 0; 249 u_int moea64_pvo_enter_calls = 0; 250 u_int moea64_pvo_remove_calls = 0; 251 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 252 &moea64_pte_valid, 0, ""); 253 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 254 &moea64_pte_overflow, 0, ""); 255 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 256 &moea64_pvo_entries, 0, ""); 257 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 258 &moea64_pvo_enter_calls, 0, ""); 259 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 260 &moea64_pvo_remove_calls, 0, ""); 261 262 vm_offset_t moea64_scratchpage_va[2]; 263 struct pvo_entry *moea64_scratchpage_pvo[2]; 264 uintptr_t moea64_scratchpage_pte[2]; 265 struct mtx moea64_scratchpage_mtx; 266 267 uint64_t moea64_large_page_mask = 0; 268 uint64_t moea64_large_page_size = 0; 269 int moea64_large_page_shift = 0; 270 271 /* 272 * PVO calls. 273 */ 274 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 275 vm_offset_t, vm_offset_t, uint64_t, int, int8_t); 276 static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 277 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 278 279 /* 280 * Utility routines. 281 */ 282 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 283 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 284 static void moea64_kremove(mmu_t, vm_offset_t); 285 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 286 vm_offset_t pa, vm_size_t sz); 287 288 /* 289 * Kernel MMU interface 290 */ 291 void moea64_clear_modify(mmu_t, vm_page_t); 292 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 293 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 294 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 295 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 296 u_int flags, int8_t psind); 297 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 298 vm_prot_t); 299 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 300 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 301 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 302 void moea64_init(mmu_t); 303 boolean_t moea64_is_modified(mmu_t, vm_page_t); 304 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 305 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 306 int moea64_ts_referenced(mmu_t, vm_page_t); 307 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 308 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 309 int moea64_page_wired_mappings(mmu_t, vm_page_t); 310 void moea64_pinit(mmu_t, pmap_t); 311 void moea64_pinit0(mmu_t, pmap_t); 312 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 313 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 314 void moea64_qremove(mmu_t, vm_offset_t, int); 315 void moea64_release(mmu_t, pmap_t); 316 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 317 void moea64_remove_pages(mmu_t, pmap_t); 318 void moea64_remove_all(mmu_t, vm_page_t); 319 void moea64_remove_write(mmu_t, vm_page_t); 320 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 321 void moea64_zero_page(mmu_t, vm_page_t); 322 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 323 void moea64_zero_page_idle(mmu_t, vm_page_t); 324 void moea64_activate(mmu_t, struct thread *); 325 void moea64_deactivate(mmu_t, struct thread *); 326 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 327 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 328 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 329 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 330 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 331 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 332 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 333 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 334 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 335 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 336 void **va); 337 void moea64_scan_init(mmu_t mmu); 338 339 static mmu_method_t moea64_methods[] = { 340 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 341 MMUMETHOD(mmu_copy_page, moea64_copy_page), 342 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 343 MMUMETHOD(mmu_enter, moea64_enter), 344 MMUMETHOD(mmu_enter_object, moea64_enter_object), 345 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 346 MMUMETHOD(mmu_extract, moea64_extract), 347 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 348 MMUMETHOD(mmu_init, moea64_init), 349 MMUMETHOD(mmu_is_modified, moea64_is_modified), 350 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 351 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 352 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 353 MMUMETHOD(mmu_map, moea64_map), 354 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 355 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 356 MMUMETHOD(mmu_pinit, moea64_pinit), 357 MMUMETHOD(mmu_pinit0, moea64_pinit0), 358 MMUMETHOD(mmu_protect, moea64_protect), 359 MMUMETHOD(mmu_qenter, moea64_qenter), 360 MMUMETHOD(mmu_qremove, moea64_qremove), 361 MMUMETHOD(mmu_release, moea64_release), 362 MMUMETHOD(mmu_remove, moea64_remove), 363 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 364 MMUMETHOD(mmu_remove_all, moea64_remove_all), 365 MMUMETHOD(mmu_remove_write, moea64_remove_write), 366 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 367 MMUMETHOD(mmu_unwire, moea64_unwire), 368 MMUMETHOD(mmu_zero_page, moea64_zero_page), 369 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 370 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 371 MMUMETHOD(mmu_activate, moea64_activate), 372 MMUMETHOD(mmu_deactivate, moea64_deactivate), 373 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 374 375 /* Internal interfaces */ 376 MMUMETHOD(mmu_mapdev, moea64_mapdev), 377 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 378 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 379 MMUMETHOD(mmu_kextract, moea64_kextract), 380 MMUMETHOD(mmu_kenter, moea64_kenter), 381 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 382 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 383 MMUMETHOD(mmu_scan_init, moea64_scan_init), 384 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 385 386 { 0, 0 } 387 }; 388 389 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 390 391 static __inline u_int 392 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 393 { 394 uint64_t hash; 395 int shift; 396 397 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 398 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 399 shift); 400 return (hash & moea64_pteg_mask); 401 } 402 403 static __inline struct pvo_head * 404 vm_page_to_pvoh(vm_page_t m) 405 { 406 407 return (&m->md.mdpg_pvoh); 408 } 409 410 static __inline void 411 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 412 uint64_t pte_lo, int flags) 413 { 414 415 /* 416 * Construct a PTE. Default to IMB initially. Valid bit only gets 417 * set when the real pte is set in memory. 418 * 419 * Note: Don't set the valid bit for correct operation of tlb update. 420 */ 421 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 422 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 423 424 if (flags & PVO_LARGE) 425 pt->pte_hi |= LPTE_BIG; 426 427 pt->pte_lo = pte_lo; 428 } 429 430 static __inline uint64_t 431 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 432 { 433 uint64_t pte_lo; 434 int i; 435 436 if (ma != VM_MEMATTR_DEFAULT) { 437 switch (ma) { 438 case VM_MEMATTR_UNCACHEABLE: 439 return (LPTE_I | LPTE_G); 440 case VM_MEMATTR_WRITE_COMBINING: 441 case VM_MEMATTR_WRITE_BACK: 442 case VM_MEMATTR_PREFETCHABLE: 443 return (LPTE_I); 444 case VM_MEMATTR_WRITE_THROUGH: 445 return (LPTE_W | LPTE_M); 446 } 447 } 448 449 /* 450 * Assume the page is cache inhibited and access is guarded unless 451 * it's in our available memory array. 452 */ 453 pte_lo = LPTE_I | LPTE_G; 454 for (i = 0; i < pregions_sz; i++) { 455 if ((pa >= pregions[i].mr_start) && 456 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 457 pte_lo &= ~(LPTE_I | LPTE_G); 458 pte_lo |= LPTE_M; 459 break; 460 } 461 } 462 463 return pte_lo; 464 } 465 466 /* 467 * Quick sort callout for comparing memory regions. 468 */ 469 static int om_cmp(const void *a, const void *b); 470 471 static int 472 om_cmp(const void *a, const void *b) 473 { 474 const struct ofw_map *mapa; 475 const struct ofw_map *mapb; 476 477 mapa = a; 478 mapb = b; 479 if (mapa->om_pa < mapb->om_pa) 480 return (-1); 481 else if (mapa->om_pa > mapb->om_pa) 482 return (1); 483 else 484 return (0); 485 } 486 487 static void 488 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 489 { 490 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 491 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 492 register_t msr; 493 vm_offset_t off; 494 vm_paddr_t pa_base; 495 int i, j; 496 497 bzero(translations, sz); 498 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 499 sizeof(acells)); 500 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 501 panic("moea64_bootstrap: can't get ofw translations"); 502 503 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 504 sz /= sizeof(cell_t); 505 for (i = 0, j = 0; i < sz; j++) { 506 translations[j].om_va = trans_cells[i++]; 507 translations[j].om_len = trans_cells[i++]; 508 translations[j].om_pa = trans_cells[i++]; 509 if (acells == 2) { 510 translations[j].om_pa <<= 32; 511 translations[j].om_pa |= trans_cells[i++]; 512 } 513 translations[j].om_mode = trans_cells[i++]; 514 } 515 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 516 i, sz)); 517 518 sz = j; 519 qsort(translations, sz, sizeof (*translations), om_cmp); 520 521 for (i = 0; i < sz; i++) { 522 pa_base = translations[i].om_pa; 523 #ifndef __powerpc64__ 524 if ((translations[i].om_pa >> 32) != 0) 525 panic("OFW translations above 32-bit boundary!"); 526 #endif 527 528 if (pa_base % PAGE_SIZE) 529 panic("OFW translation not page-aligned (phys)!"); 530 if (translations[i].om_va % PAGE_SIZE) 531 panic("OFW translation not page-aligned (virt)!"); 532 533 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 534 pa_base, translations[i].om_va, translations[i].om_len); 535 536 /* Now enter the pages for this mapping */ 537 538 DISABLE_TRANS(msr); 539 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 540 /* If this address is direct-mapped, skip remapping */ 541 if (hw_direct_map && translations[i].om_va == pa_base && 542 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 543 continue; 544 545 if (moea64_pvo_find_va(kernel_pmap, 546 translations[i].om_va + off) != NULL) 547 continue; 548 549 moea64_kenter(mmup, translations[i].om_va + off, 550 pa_base + off); 551 } 552 ENABLE_TRANS(msr); 553 } 554 } 555 556 #ifdef __powerpc64__ 557 static void 558 moea64_probe_large_page(void) 559 { 560 uint16_t pvr = mfpvr() >> 16; 561 562 switch (pvr) { 563 case IBM970: 564 case IBM970FX: 565 case IBM970MP: 566 powerpc_sync(); isync(); 567 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 568 powerpc_sync(); isync(); 569 570 /* FALLTHROUGH */ 571 default: 572 moea64_large_page_size = 0x1000000; /* 16 MB */ 573 moea64_large_page_shift = 24; 574 } 575 576 moea64_large_page_mask = moea64_large_page_size - 1; 577 } 578 579 static void 580 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 581 { 582 struct slb *cache; 583 struct slb entry; 584 uint64_t esid, slbe; 585 uint64_t i; 586 587 cache = PCPU_GET(slb); 588 esid = va >> ADDR_SR_SHFT; 589 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 590 591 for (i = 0; i < 64; i++) { 592 if (cache[i].slbe == (slbe | i)) 593 return; 594 } 595 596 entry.slbe = slbe; 597 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 598 if (large) 599 entry.slbv |= SLBV_L; 600 601 slb_insert_kernel(entry.slbe, entry.slbv); 602 } 603 #endif 604 605 static void 606 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 607 vm_offset_t kernelend) 608 { 609 register_t msr; 610 vm_paddr_t pa; 611 vm_offset_t size, off; 612 uint64_t pte_lo; 613 int i; 614 615 if (moea64_large_page_size == 0) 616 hw_direct_map = 0; 617 618 DISABLE_TRANS(msr); 619 if (hw_direct_map) { 620 LOCK_TABLE_WR(); 621 PMAP_LOCK(kernel_pmap); 622 for (i = 0; i < pregions_sz; i++) { 623 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 624 pregions[i].mr_size; pa += moea64_large_page_size) { 625 pte_lo = LPTE_M; 626 627 /* 628 * Set memory access as guarded if prefetch within 629 * the page could exit the available physmem area. 630 */ 631 if (pa & moea64_large_page_mask) { 632 pa &= moea64_large_page_mask; 633 pte_lo |= LPTE_G; 634 } 635 if (pa + moea64_large_page_size > 636 pregions[i].mr_start + pregions[i].mr_size) 637 pte_lo |= LPTE_G; 638 639 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 640 NULL, pa, pa, pte_lo, 641 PVO_WIRED | PVO_LARGE, 0); 642 } 643 } 644 PMAP_UNLOCK(kernel_pmap); 645 UNLOCK_TABLE_WR(); 646 } else { 647 size = sizeof(struct pvo_head) * moea64_pteg_count; 648 off = (vm_offset_t)(moea64_pvo_table); 649 for (pa = off; pa < off + size; pa += PAGE_SIZE) 650 moea64_kenter(mmup, pa, pa); 651 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 652 off = (vm_offset_t)(moea64_bpvo_pool); 653 for (pa = off; pa < off + size; pa += PAGE_SIZE) 654 moea64_kenter(mmup, pa, pa); 655 656 /* 657 * Map certain important things, like ourselves. 658 * 659 * NOTE: We do not map the exception vector space. That code is 660 * used only in real mode, and leaving it unmapped allows us to 661 * catch NULL pointer deferences, instead of making NULL a valid 662 * address. 663 */ 664 665 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 666 pa += PAGE_SIZE) 667 moea64_kenter(mmup, pa, pa); 668 } 669 ENABLE_TRANS(msr); 670 671 /* 672 * Allow user to override unmapped_buf_allowed for testing. 673 * XXXKIB Only direct map implementation was tested. 674 */ 675 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 676 &unmapped_buf_allowed)) 677 unmapped_buf_allowed = hw_direct_map; 678 } 679 680 void 681 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 682 { 683 int i, j; 684 vm_size_t physsz, hwphyssz; 685 686 #ifndef __powerpc64__ 687 /* We don't have a direct map since there is no BAT */ 688 hw_direct_map = 0; 689 690 /* Make sure battable is zero, since we have no BAT */ 691 for (i = 0; i < 16; i++) { 692 battable[i].batu = 0; 693 battable[i].batl = 0; 694 } 695 #else 696 moea64_probe_large_page(); 697 698 /* Use a direct map if we have large page support */ 699 if (moea64_large_page_size > 0) 700 hw_direct_map = 1; 701 else 702 hw_direct_map = 0; 703 #endif 704 705 /* Get physical memory regions from firmware */ 706 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 707 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 708 709 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 710 panic("moea64_bootstrap: phys_avail too small"); 711 712 phys_avail_count = 0; 713 physsz = 0; 714 hwphyssz = 0; 715 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 716 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 717 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 718 regions[i].mr_start, regions[i].mr_start + 719 regions[i].mr_size, regions[i].mr_size); 720 if (hwphyssz != 0 && 721 (physsz + regions[i].mr_size) >= hwphyssz) { 722 if (physsz < hwphyssz) { 723 phys_avail[j] = regions[i].mr_start; 724 phys_avail[j + 1] = regions[i].mr_start + 725 hwphyssz - physsz; 726 physsz = hwphyssz; 727 phys_avail_count++; 728 } 729 break; 730 } 731 phys_avail[j] = regions[i].mr_start; 732 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 733 phys_avail_count++; 734 physsz += regions[i].mr_size; 735 } 736 737 /* Check for overlap with the kernel and exception vectors */ 738 for (j = 0; j < 2*phys_avail_count; j+=2) { 739 if (phys_avail[j] < EXC_LAST) 740 phys_avail[j] += EXC_LAST; 741 742 if (kernelstart >= phys_avail[j] && 743 kernelstart < phys_avail[j+1]) { 744 if (kernelend < phys_avail[j+1]) { 745 phys_avail[2*phys_avail_count] = 746 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 747 phys_avail[2*phys_avail_count + 1] = 748 phys_avail[j+1]; 749 phys_avail_count++; 750 } 751 752 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 753 } 754 755 if (kernelend >= phys_avail[j] && 756 kernelend < phys_avail[j+1]) { 757 if (kernelstart > phys_avail[j]) { 758 phys_avail[2*phys_avail_count] = phys_avail[j]; 759 phys_avail[2*phys_avail_count + 1] = 760 kernelstart & ~PAGE_MASK; 761 phys_avail_count++; 762 } 763 764 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 765 } 766 } 767 768 physmem = btoc(physsz); 769 770 #ifdef PTEGCOUNT 771 moea64_pteg_count = PTEGCOUNT; 772 #else 773 moea64_pteg_count = 0x1000; 774 775 while (moea64_pteg_count < physmem) 776 moea64_pteg_count <<= 1; 777 778 moea64_pteg_count >>= 1; 779 #endif /* PTEGCOUNT */ 780 } 781 782 void 783 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 784 { 785 vm_size_t size; 786 register_t msr; 787 int i; 788 789 /* 790 * Set PTEG mask 791 */ 792 moea64_pteg_mask = moea64_pteg_count - 1; 793 794 /* 795 * Allocate pv/overflow lists. 796 */ 797 size = sizeof(struct pvo_head) * moea64_pteg_count; 798 799 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 800 PAGE_SIZE); 801 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 802 803 DISABLE_TRANS(msr); 804 for (i = 0; i < moea64_pteg_count; i++) 805 LIST_INIT(&moea64_pvo_table[i]); 806 ENABLE_TRANS(msr); 807 808 /* 809 * Initialize the lock that synchronizes access to the pteg and pvo 810 * tables. 811 */ 812 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 813 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 814 815 /* 816 * Initialise the unmanaged pvo pool. 817 */ 818 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 819 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 820 moea64_bpvo_pool_index = 0; 821 822 /* 823 * Make sure kernel vsid is allocated as well as VSID 0. 824 */ 825 #ifndef __powerpc64__ 826 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 827 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 828 moea64_vsid_bitmap[0] |= 1; 829 #endif 830 831 /* 832 * Initialize the kernel pmap (which is statically allocated). 833 */ 834 #ifdef __powerpc64__ 835 for (i = 0; i < 64; i++) { 836 pcpup->pc_slb[i].slbv = 0; 837 pcpup->pc_slb[i].slbe = 0; 838 } 839 #else 840 for (i = 0; i < 16; i++) 841 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 842 #endif 843 844 kernel_pmap->pmap_phys = kernel_pmap; 845 CPU_FILL(&kernel_pmap->pm_active); 846 RB_INIT(&kernel_pmap->pmap_pvo); 847 848 PMAP_LOCK_INIT(kernel_pmap); 849 850 /* 851 * Now map in all the other buffers we allocated earlier 852 */ 853 854 moea64_setup_direct_map(mmup, kernelstart, kernelend); 855 } 856 857 void 858 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 859 { 860 ihandle_t mmui; 861 phandle_t chosen; 862 phandle_t mmu; 863 ssize_t sz; 864 int i; 865 vm_offset_t pa, va; 866 void *dpcpu; 867 868 /* 869 * Set up the Open Firmware pmap and add its mappings if not in real 870 * mode. 871 */ 872 873 chosen = OF_finddevice("/chosen"); 874 if (!ofw_real_mode && chosen != -1 && 875 OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 876 mmu = OF_instance_to_package(mmui); 877 if (mmu == -1 || 878 (sz = OF_getproplen(mmu, "translations")) == -1) 879 sz = 0; 880 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 881 panic("moea64_bootstrap: too many ofw translations"); 882 883 if (sz > 0) 884 moea64_add_ofw_mappings(mmup, mmu, sz); 885 } 886 887 /* 888 * Calculate the last available physical address. 889 */ 890 for (i = 0; phys_avail[i + 2] != 0; i += 2) 891 ; 892 Maxmem = powerpc_btop(phys_avail[i + 1]); 893 894 /* 895 * Initialize MMU and remap early physical mappings 896 */ 897 MMU_CPU_BOOTSTRAP(mmup,0); 898 mtmsr(mfmsr() | PSL_DR | PSL_IR); 899 pmap_bootstrapped++; 900 bs_remap_earlyboot(); 901 902 /* 903 * Set the start and end of kva. 904 */ 905 virtual_avail = VM_MIN_KERNEL_ADDRESS; 906 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 907 908 /* 909 * Map the entire KVA range into the SLB. We must not fault there. 910 */ 911 #ifdef __powerpc64__ 912 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 913 moea64_bootstrap_slb_prefault(va, 0); 914 #endif 915 916 /* 917 * Figure out how far we can extend virtual_end into segment 16 918 * without running into existing mappings. Segment 16 is guaranteed 919 * to contain neither RAM nor devices (at least on Apple hardware), 920 * but will generally contain some OFW mappings we should not 921 * step on. 922 */ 923 924 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 925 PMAP_LOCK(kernel_pmap); 926 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 927 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 928 virtual_end += PAGE_SIZE; 929 PMAP_UNLOCK(kernel_pmap); 930 #endif 931 932 /* 933 * Allocate a kernel stack with a guard page for thread0 and map it 934 * into the kernel page map. 935 */ 936 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 937 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 938 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 939 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 940 thread0.td_kstack = va; 941 thread0.td_kstack_pages = KSTACK_PAGES; 942 for (i = 0; i < KSTACK_PAGES; i++) { 943 moea64_kenter(mmup, va, pa); 944 pa += PAGE_SIZE; 945 va += PAGE_SIZE; 946 } 947 948 /* 949 * Allocate virtual address space for the message buffer. 950 */ 951 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 952 msgbufp = (struct msgbuf *)virtual_avail; 953 va = virtual_avail; 954 virtual_avail += round_page(msgbufsize); 955 while (va < virtual_avail) { 956 moea64_kenter(mmup, va, pa); 957 pa += PAGE_SIZE; 958 va += PAGE_SIZE; 959 } 960 961 /* 962 * Allocate virtual address space for the dynamic percpu area. 963 */ 964 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 965 dpcpu = (void *)virtual_avail; 966 va = virtual_avail; 967 virtual_avail += DPCPU_SIZE; 968 while (va < virtual_avail) { 969 moea64_kenter(mmup, va, pa); 970 pa += PAGE_SIZE; 971 va += PAGE_SIZE; 972 } 973 dpcpu_init(dpcpu, 0); 974 975 /* 976 * Allocate some things for page zeroing. We put this directly 977 * in the page table, marked with LPTE_LOCKED, to avoid any 978 * of the PVO book-keeping or other parts of the VM system 979 * from even knowing that this hack exists. 980 */ 981 982 if (!hw_direct_map) { 983 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 984 MTX_DEF); 985 for (i = 0; i < 2; i++) { 986 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 987 virtual_end -= PAGE_SIZE; 988 989 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 990 991 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 992 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 993 LOCK_TABLE_RD(); 994 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 995 mmup, moea64_scratchpage_pvo[i]); 996 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 997 |= LPTE_LOCKED; 998 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 999 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 1000 moea64_scratchpage_pvo[i]->pvo_vpn); 1001 UNLOCK_TABLE_RD(); 1002 } 1003 } 1004 } 1005 1006 /* 1007 * Activate a user pmap. The pmap must be activated before its address 1008 * space can be accessed in any way. 1009 */ 1010 void 1011 moea64_activate(mmu_t mmu, struct thread *td) 1012 { 1013 pmap_t pm; 1014 1015 pm = &td->td_proc->p_vmspace->vm_pmap; 1016 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1017 1018 #ifdef __powerpc64__ 1019 PCPU_SET(userslb, pm->pm_slb); 1020 #else 1021 PCPU_SET(curpmap, pm->pmap_phys); 1022 #endif 1023 } 1024 1025 void 1026 moea64_deactivate(mmu_t mmu, struct thread *td) 1027 { 1028 pmap_t pm; 1029 1030 pm = &td->td_proc->p_vmspace->vm_pmap; 1031 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1032 #ifdef __powerpc64__ 1033 PCPU_SET(userslb, NULL); 1034 #else 1035 PCPU_SET(curpmap, NULL); 1036 #endif 1037 } 1038 1039 void 1040 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1041 { 1042 struct pvo_entry key, *pvo; 1043 uintptr_t pt; 1044 1045 LOCK_TABLE_RD(); 1046 PMAP_LOCK(pm); 1047 key.pvo_vaddr = sva; 1048 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1049 pvo != NULL && PVO_VADDR(pvo) < eva; 1050 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1051 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1052 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1053 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1054 pvo); 1055 pvo->pvo_vaddr &= ~PVO_WIRED; 1056 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_WIRED) == 0) 1057 panic("moea64_unwire: pte %p is missing LPTE_WIRED", 1058 &pvo->pvo_pte.lpte); 1059 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1060 if (pt != -1) { 1061 /* 1062 * The PTE's wired attribute is not a hardware 1063 * feature, so there is no need to invalidate any TLB 1064 * entries. 1065 */ 1066 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1067 pvo->pvo_vpn); 1068 } 1069 pm->pm_stats.wired_count--; 1070 } 1071 UNLOCK_TABLE_RD(); 1072 PMAP_UNLOCK(pm); 1073 } 1074 1075 /* 1076 * This goes through and sets the physical address of our 1077 * special scratch PTE to the PA we want to zero or copy. Because 1078 * of locking issues (this can get called in pvo_enter() by 1079 * the UMA allocator), we can't use most other utility functions here 1080 */ 1081 1082 static __inline 1083 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1084 1085 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1086 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1087 1088 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1089 ~(LPTE_WIMG | LPTE_RPGN); 1090 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1091 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1092 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1093 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1094 moea64_scratchpage_pvo[which]->pvo_vpn); 1095 isync(); 1096 } 1097 1098 void 1099 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1100 { 1101 vm_offset_t dst; 1102 vm_offset_t src; 1103 1104 dst = VM_PAGE_TO_PHYS(mdst); 1105 src = VM_PAGE_TO_PHYS(msrc); 1106 1107 if (hw_direct_map) { 1108 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1109 } else { 1110 mtx_lock(&moea64_scratchpage_mtx); 1111 1112 moea64_set_scratchpage_pa(mmu, 0, src); 1113 moea64_set_scratchpage_pa(mmu, 1, dst); 1114 1115 bcopy((void *)moea64_scratchpage_va[0], 1116 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1117 1118 mtx_unlock(&moea64_scratchpage_mtx); 1119 } 1120 } 1121 1122 static inline void 1123 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1124 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1125 { 1126 void *a_cp, *b_cp; 1127 vm_offset_t a_pg_offset, b_pg_offset; 1128 int cnt; 1129 1130 while (xfersize > 0) { 1131 a_pg_offset = a_offset & PAGE_MASK; 1132 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1133 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1134 a_pg_offset; 1135 b_pg_offset = b_offset & PAGE_MASK; 1136 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1137 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1138 b_pg_offset; 1139 bcopy(a_cp, b_cp, cnt); 1140 a_offset += cnt; 1141 b_offset += cnt; 1142 xfersize -= cnt; 1143 } 1144 } 1145 1146 static inline void 1147 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1148 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1149 { 1150 void *a_cp, *b_cp; 1151 vm_offset_t a_pg_offset, b_pg_offset; 1152 int cnt; 1153 1154 mtx_lock(&moea64_scratchpage_mtx); 1155 while (xfersize > 0) { 1156 a_pg_offset = a_offset & PAGE_MASK; 1157 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1158 moea64_set_scratchpage_pa(mmu, 0, 1159 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1160 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1161 b_pg_offset = b_offset & PAGE_MASK; 1162 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1163 moea64_set_scratchpage_pa(mmu, 1, 1164 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1165 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1166 bcopy(a_cp, b_cp, cnt); 1167 a_offset += cnt; 1168 b_offset += cnt; 1169 xfersize -= cnt; 1170 } 1171 mtx_unlock(&moea64_scratchpage_mtx); 1172 } 1173 1174 void 1175 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1176 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1177 { 1178 1179 if (hw_direct_map) { 1180 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1181 xfersize); 1182 } else { 1183 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1184 xfersize); 1185 } 1186 } 1187 1188 void 1189 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1190 { 1191 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1192 1193 if (size + off > PAGE_SIZE) 1194 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1195 1196 if (hw_direct_map) { 1197 bzero((caddr_t)pa + off, size); 1198 } else { 1199 mtx_lock(&moea64_scratchpage_mtx); 1200 moea64_set_scratchpage_pa(mmu, 0, pa); 1201 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1202 mtx_unlock(&moea64_scratchpage_mtx); 1203 } 1204 } 1205 1206 /* 1207 * Zero a page of physical memory by temporarily mapping it 1208 */ 1209 void 1210 moea64_zero_page(mmu_t mmu, vm_page_t m) 1211 { 1212 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1213 vm_offset_t va, off; 1214 1215 if (!hw_direct_map) { 1216 mtx_lock(&moea64_scratchpage_mtx); 1217 1218 moea64_set_scratchpage_pa(mmu, 0, pa); 1219 va = moea64_scratchpage_va[0]; 1220 } else { 1221 va = pa; 1222 } 1223 1224 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1225 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1226 1227 if (!hw_direct_map) 1228 mtx_unlock(&moea64_scratchpage_mtx); 1229 } 1230 1231 void 1232 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1233 { 1234 1235 moea64_zero_page(mmu, m); 1236 } 1237 1238 /* 1239 * Map the given physical page at the specified virtual address in the 1240 * target pmap with the protection requested. If specified the page 1241 * will be wired down. 1242 */ 1243 1244 int 1245 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1246 vm_prot_t prot, u_int flags, int8_t psind) 1247 { 1248 struct pvo_head *pvo_head; 1249 uma_zone_t zone; 1250 uint64_t pte_lo; 1251 u_int pvo_flags; 1252 int error; 1253 1254 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1255 VM_OBJECT_ASSERT_LOCKED(m->object); 1256 1257 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1258 pvo_head = NULL; 1259 zone = moea64_upvo_zone; 1260 pvo_flags = 0; 1261 } else { 1262 pvo_head = vm_page_to_pvoh(m); 1263 zone = moea64_mpvo_zone; 1264 pvo_flags = PVO_MANAGED; 1265 } 1266 1267 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1268 1269 if (prot & VM_PROT_WRITE) { 1270 pte_lo |= LPTE_BW; 1271 if (pmap_bootstrapped && 1272 (m->oflags & VPO_UNMANAGED) == 0) 1273 vm_page_aflag_set(m, PGA_WRITEABLE); 1274 } else 1275 pte_lo |= LPTE_BR; 1276 1277 if ((prot & VM_PROT_EXECUTE) == 0) 1278 pte_lo |= LPTE_NOEXEC; 1279 1280 if ((flags & PMAP_ENTER_WIRED) != 0) 1281 pvo_flags |= PVO_WIRED; 1282 1283 for (;;) { 1284 LOCK_TABLE_WR(); 1285 PMAP_LOCK(pmap); 1286 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1287 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags, psind); 1288 PMAP_UNLOCK(pmap); 1289 UNLOCK_TABLE_WR(); 1290 if (error != ENOMEM) 1291 break; 1292 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1293 return (KERN_RESOURCE_SHORTAGE); 1294 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1295 VM_WAIT; 1296 } 1297 1298 /* 1299 * Flush the page from the instruction cache if this page is 1300 * mapped executable and cacheable. 1301 */ 1302 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1303 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1304 vm_page_aflag_set(m, PGA_EXECUTABLE); 1305 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1306 } 1307 return (KERN_SUCCESS); 1308 } 1309 1310 static void 1311 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1312 vm_size_t sz) 1313 { 1314 1315 /* 1316 * This is much trickier than on older systems because 1317 * we can't sync the icache on physical addresses directly 1318 * without a direct map. Instead we check a couple of cases 1319 * where the memory is already mapped in and, failing that, 1320 * use the same trick we use for page zeroing to create 1321 * a temporary mapping for this physical address. 1322 */ 1323 1324 if (!pmap_bootstrapped) { 1325 /* 1326 * If PMAP is not bootstrapped, we are likely to be 1327 * in real mode. 1328 */ 1329 __syncicache((void *)pa, sz); 1330 } else if (pmap == kernel_pmap) { 1331 __syncicache((void *)va, sz); 1332 } else if (hw_direct_map) { 1333 __syncicache((void *)pa, sz); 1334 } else { 1335 /* Use the scratch page to set up a temp mapping */ 1336 1337 mtx_lock(&moea64_scratchpage_mtx); 1338 1339 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1340 __syncicache((void *)(moea64_scratchpage_va[1] + 1341 (va & ADDR_POFF)), sz); 1342 1343 mtx_unlock(&moea64_scratchpage_mtx); 1344 } 1345 } 1346 1347 /* 1348 * Maps a sequence of resident pages belonging to the same object. 1349 * The sequence begins with the given page m_start. This page is 1350 * mapped at the given virtual address start. Each subsequent page is 1351 * mapped at a virtual address that is offset from start by the same 1352 * amount as the page is offset from m_start within the object. The 1353 * last page in the sequence is the page with the largest offset from 1354 * m_start that can be mapped at a virtual address less than the given 1355 * virtual address end. Not every virtual page between start and end 1356 * is mapped; only those for which a resident page exists with the 1357 * corresponding offset from m_start are mapped. 1358 */ 1359 void 1360 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1361 vm_page_t m_start, vm_prot_t prot) 1362 { 1363 vm_page_t m; 1364 vm_pindex_t diff, psize; 1365 1366 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1367 1368 psize = atop(end - start); 1369 m = m_start; 1370 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1371 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1372 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1373 m = TAILQ_NEXT(m, listq); 1374 } 1375 } 1376 1377 void 1378 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1379 vm_prot_t prot) 1380 { 1381 1382 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1383 PMAP_ENTER_NOSLEEP, 0); 1384 } 1385 1386 vm_paddr_t 1387 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1388 { 1389 struct pvo_entry *pvo; 1390 vm_paddr_t pa; 1391 1392 PMAP_LOCK(pm); 1393 pvo = moea64_pvo_find_va(pm, va); 1394 if (pvo == NULL) 1395 pa = 0; 1396 else 1397 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1398 (va - PVO_VADDR(pvo)); 1399 PMAP_UNLOCK(pm); 1400 return (pa); 1401 } 1402 1403 /* 1404 * Atomically extract and hold the physical page with the given 1405 * pmap and virtual address pair if that mapping permits the given 1406 * protection. 1407 */ 1408 vm_page_t 1409 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1410 { 1411 struct pvo_entry *pvo; 1412 vm_page_t m; 1413 vm_paddr_t pa; 1414 1415 m = NULL; 1416 pa = 0; 1417 PMAP_LOCK(pmap); 1418 retry: 1419 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1420 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1421 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1422 (prot & VM_PROT_WRITE) == 0)) { 1423 if (vm_page_pa_tryrelock(pmap, 1424 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1425 goto retry; 1426 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1427 vm_page_hold(m); 1428 } 1429 PA_UNLOCK_COND(pa); 1430 PMAP_UNLOCK(pmap); 1431 return (m); 1432 } 1433 1434 static mmu_t installed_mmu; 1435 1436 static void * 1437 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1438 { 1439 /* 1440 * This entire routine is a horrible hack to avoid bothering kmem 1441 * for new KVA addresses. Because this can get called from inside 1442 * kmem allocation routines, calling kmem for a new address here 1443 * can lead to multiply locking non-recursive mutexes. 1444 */ 1445 vm_offset_t va; 1446 1447 vm_page_t m; 1448 int pflags, needed_lock; 1449 1450 *flags = UMA_SLAB_PRIV; 1451 needed_lock = !PMAP_LOCKED(kernel_pmap); 1452 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1453 1454 for (;;) { 1455 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1456 if (m == NULL) { 1457 if (wait & M_NOWAIT) 1458 return (NULL); 1459 VM_WAIT; 1460 } else 1461 break; 1462 } 1463 1464 va = VM_PAGE_TO_PHYS(m); 1465 1466 LOCK_TABLE_WR(); 1467 if (needed_lock) 1468 PMAP_LOCK(kernel_pmap); 1469 1470 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1471 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP, 1472 0); 1473 1474 if (needed_lock) 1475 PMAP_UNLOCK(kernel_pmap); 1476 UNLOCK_TABLE_WR(); 1477 1478 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1479 bzero((void *)va, PAGE_SIZE); 1480 1481 return (void *)va; 1482 } 1483 1484 extern int elf32_nxstack; 1485 1486 void 1487 moea64_init(mmu_t mmu) 1488 { 1489 1490 CTR0(KTR_PMAP, "moea64_init"); 1491 1492 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1493 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1494 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1495 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1496 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1497 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1498 1499 if (!hw_direct_map) { 1500 installed_mmu = mmu; 1501 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1502 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1503 } 1504 1505 #ifdef COMPAT_FREEBSD32 1506 elf32_nxstack = 1; 1507 #endif 1508 1509 moea64_initialized = TRUE; 1510 } 1511 1512 boolean_t 1513 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1514 { 1515 1516 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1517 ("moea64_is_referenced: page %p is not managed", m)); 1518 return (moea64_query_bit(mmu, m, PTE_REF)); 1519 } 1520 1521 boolean_t 1522 moea64_is_modified(mmu_t mmu, vm_page_t m) 1523 { 1524 1525 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1526 ("moea64_is_modified: page %p is not managed", m)); 1527 1528 /* 1529 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1530 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1531 * is clear, no PTEs can have LPTE_CHG set. 1532 */ 1533 VM_OBJECT_ASSERT_LOCKED(m->object); 1534 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1535 return (FALSE); 1536 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1537 } 1538 1539 boolean_t 1540 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1541 { 1542 struct pvo_entry *pvo; 1543 boolean_t rv; 1544 1545 PMAP_LOCK(pmap); 1546 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1547 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1548 PMAP_UNLOCK(pmap); 1549 return (rv); 1550 } 1551 1552 void 1553 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1554 { 1555 1556 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1557 ("moea64_clear_modify: page %p is not managed", m)); 1558 VM_OBJECT_ASSERT_WLOCKED(m->object); 1559 KASSERT(!vm_page_xbusied(m), 1560 ("moea64_clear_modify: page %p is exclusive busied", m)); 1561 1562 /* 1563 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1564 * set. If the object containing the page is locked and the page is 1565 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1566 */ 1567 if ((m->aflags & PGA_WRITEABLE) == 0) 1568 return; 1569 moea64_clear_bit(mmu, m, LPTE_CHG); 1570 } 1571 1572 /* 1573 * Clear the write and modified bits in each of the given page's mappings. 1574 */ 1575 void 1576 moea64_remove_write(mmu_t mmu, vm_page_t m) 1577 { 1578 struct pvo_entry *pvo; 1579 uintptr_t pt; 1580 pmap_t pmap; 1581 uint64_t lo = 0; 1582 1583 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1584 ("moea64_remove_write: page %p is not managed", m)); 1585 1586 /* 1587 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1588 * set by another thread while the object is locked. Thus, 1589 * if PGA_WRITEABLE is clear, no page table entries need updating. 1590 */ 1591 VM_OBJECT_ASSERT_WLOCKED(m->object); 1592 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1593 return; 1594 powerpc_sync(); 1595 LOCK_TABLE_RD(); 1596 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1597 pmap = pvo->pvo_pmap; 1598 PMAP_LOCK(pmap); 1599 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1600 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1601 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1602 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1603 if (pt != -1) { 1604 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1605 lo |= pvo->pvo_pte.lpte.pte_lo; 1606 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1607 MOEA64_PTE_CHANGE(mmu, pt, 1608 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1609 if (pvo->pvo_pmap == kernel_pmap) 1610 isync(); 1611 } 1612 } 1613 if ((lo & LPTE_CHG) != 0) 1614 vm_page_dirty(m); 1615 PMAP_UNLOCK(pmap); 1616 } 1617 UNLOCK_TABLE_RD(); 1618 vm_page_aflag_clear(m, PGA_WRITEABLE); 1619 } 1620 1621 /* 1622 * moea64_ts_referenced: 1623 * 1624 * Return a count of reference bits for a page, clearing those bits. 1625 * It is not necessary for every reference bit to be cleared, but it 1626 * is necessary that 0 only be returned when there are truly no 1627 * reference bits set. 1628 * 1629 * XXX: The exact number of bits to check and clear is a matter that 1630 * should be tested and standardized at some point in the future for 1631 * optimal aging of shared pages. 1632 */ 1633 int 1634 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1635 { 1636 1637 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1638 ("moea64_ts_referenced: page %p is not managed", m)); 1639 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1640 } 1641 1642 /* 1643 * Modify the WIMG settings of all mappings for a page. 1644 */ 1645 void 1646 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1647 { 1648 struct pvo_entry *pvo; 1649 struct pvo_head *pvo_head; 1650 uintptr_t pt; 1651 pmap_t pmap; 1652 uint64_t lo; 1653 1654 if ((m->oflags & VPO_UNMANAGED) != 0) { 1655 m->md.mdpg_cache_attrs = ma; 1656 return; 1657 } 1658 1659 pvo_head = vm_page_to_pvoh(m); 1660 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1661 LOCK_TABLE_RD(); 1662 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1663 pmap = pvo->pvo_pmap; 1664 PMAP_LOCK(pmap); 1665 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1666 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1667 pvo->pvo_pte.lpte.pte_lo |= lo; 1668 if (pt != -1) { 1669 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1670 pvo->pvo_vpn); 1671 if (pvo->pvo_pmap == kernel_pmap) 1672 isync(); 1673 } 1674 PMAP_UNLOCK(pmap); 1675 } 1676 UNLOCK_TABLE_RD(); 1677 m->md.mdpg_cache_attrs = ma; 1678 } 1679 1680 /* 1681 * Map a wired page into kernel virtual address space. 1682 */ 1683 void 1684 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1685 { 1686 uint64_t pte_lo; 1687 int error; 1688 1689 pte_lo = moea64_calc_wimg(pa, ma); 1690 1691 LOCK_TABLE_WR(); 1692 PMAP_LOCK(kernel_pmap); 1693 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1694 NULL, va, pa, pte_lo, PVO_WIRED, 0); 1695 PMAP_UNLOCK(kernel_pmap); 1696 UNLOCK_TABLE_WR(); 1697 1698 if (error != 0 && error != ENOENT) 1699 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1700 pa, error); 1701 } 1702 1703 void 1704 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1705 { 1706 1707 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1708 } 1709 1710 /* 1711 * Extract the physical page address associated with the given kernel virtual 1712 * address. 1713 */ 1714 vm_paddr_t 1715 moea64_kextract(mmu_t mmu, vm_offset_t va) 1716 { 1717 struct pvo_entry *pvo; 1718 vm_paddr_t pa; 1719 1720 /* 1721 * Shortcut the direct-mapped case when applicable. We never put 1722 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1723 */ 1724 if (va < VM_MIN_KERNEL_ADDRESS) 1725 return (va); 1726 1727 PMAP_LOCK(kernel_pmap); 1728 pvo = moea64_pvo_find_va(kernel_pmap, va); 1729 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1730 va)); 1731 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1732 PMAP_UNLOCK(kernel_pmap); 1733 return (pa); 1734 } 1735 1736 /* 1737 * Remove a wired page from kernel virtual address space. 1738 */ 1739 void 1740 moea64_kremove(mmu_t mmu, vm_offset_t va) 1741 { 1742 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1743 } 1744 1745 /* 1746 * Map a range of physical addresses into kernel virtual address space. 1747 * 1748 * The value passed in *virt is a suggested virtual address for the mapping. 1749 * Architectures which can support a direct-mapped physical to virtual region 1750 * can return the appropriate address within that region, leaving '*virt' 1751 * unchanged. We cannot and therefore do not; *virt is updated with the 1752 * first usable address after the mapped region. 1753 */ 1754 vm_offset_t 1755 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1756 vm_paddr_t pa_end, int prot) 1757 { 1758 vm_offset_t sva, va; 1759 1760 sva = *virt; 1761 va = sva; 1762 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1763 moea64_kenter(mmu, va, pa_start); 1764 *virt = va; 1765 1766 return (sva); 1767 } 1768 1769 /* 1770 * Returns true if the pmap's pv is one of the first 1771 * 16 pvs linked to from this page. This count may 1772 * be changed upwards or downwards in the future; it 1773 * is only necessary that true be returned for a small 1774 * subset of pmaps for proper page aging. 1775 */ 1776 boolean_t 1777 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1778 { 1779 int loops; 1780 struct pvo_entry *pvo; 1781 boolean_t rv; 1782 1783 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1784 ("moea64_page_exists_quick: page %p is not managed", m)); 1785 loops = 0; 1786 rv = FALSE; 1787 LOCK_TABLE_RD(); 1788 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1789 if (pvo->pvo_pmap == pmap) { 1790 rv = TRUE; 1791 break; 1792 } 1793 if (++loops >= 16) 1794 break; 1795 } 1796 UNLOCK_TABLE_RD(); 1797 return (rv); 1798 } 1799 1800 /* 1801 * Return the number of managed mappings to the given physical page 1802 * that are wired. 1803 */ 1804 int 1805 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1806 { 1807 struct pvo_entry *pvo; 1808 int count; 1809 1810 count = 0; 1811 if ((m->oflags & VPO_UNMANAGED) != 0) 1812 return (count); 1813 LOCK_TABLE_RD(); 1814 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1815 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1816 count++; 1817 UNLOCK_TABLE_RD(); 1818 return (count); 1819 } 1820 1821 static uintptr_t moea64_vsidcontext; 1822 1823 uintptr_t 1824 moea64_get_unique_vsid(void) { 1825 u_int entropy; 1826 register_t hash; 1827 uint32_t mask; 1828 int i; 1829 1830 entropy = 0; 1831 __asm __volatile("mftb %0" : "=r"(entropy)); 1832 1833 mtx_lock(&moea64_slb_mutex); 1834 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1835 u_int n; 1836 1837 /* 1838 * Create a new value by mutiplying by a prime and adding in 1839 * entropy from the timebase register. This is to make the 1840 * VSID more random so that the PT hash function collides 1841 * less often. (Note that the prime casues gcc to do shifts 1842 * instead of a multiply.) 1843 */ 1844 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1845 hash = moea64_vsidcontext & (NVSIDS - 1); 1846 if (hash == 0) /* 0 is special, avoid it */ 1847 continue; 1848 n = hash >> 5; 1849 mask = 1 << (hash & (VSID_NBPW - 1)); 1850 hash = (moea64_vsidcontext & VSID_HASHMASK); 1851 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1852 /* anything free in this bucket? */ 1853 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1854 entropy = (moea64_vsidcontext >> 20); 1855 continue; 1856 } 1857 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1858 mask = 1 << i; 1859 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1860 hash |= i; 1861 } 1862 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1863 ("Allocating in-use VSID %#zx\n", hash)); 1864 moea64_vsid_bitmap[n] |= mask; 1865 mtx_unlock(&moea64_slb_mutex); 1866 return (hash); 1867 } 1868 1869 mtx_unlock(&moea64_slb_mutex); 1870 panic("%s: out of segments",__func__); 1871 } 1872 1873 #ifdef __powerpc64__ 1874 void 1875 moea64_pinit(mmu_t mmu, pmap_t pmap) 1876 { 1877 1878 RB_INIT(&pmap->pmap_pvo); 1879 1880 pmap->pm_slb_tree_root = slb_alloc_tree(); 1881 pmap->pm_slb = slb_alloc_user_cache(); 1882 pmap->pm_slb_len = 0; 1883 } 1884 #else 1885 void 1886 moea64_pinit(mmu_t mmu, pmap_t pmap) 1887 { 1888 int i; 1889 uint32_t hash; 1890 1891 RB_INIT(&pmap->pmap_pvo); 1892 1893 if (pmap_bootstrapped) 1894 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1895 (vm_offset_t)pmap); 1896 else 1897 pmap->pmap_phys = pmap; 1898 1899 /* 1900 * Allocate some segment registers for this pmap. 1901 */ 1902 hash = moea64_get_unique_vsid(); 1903 1904 for (i = 0; i < 16; i++) 1905 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1906 1907 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1908 } 1909 #endif 1910 1911 /* 1912 * Initialize the pmap associated with process 0. 1913 */ 1914 void 1915 moea64_pinit0(mmu_t mmu, pmap_t pm) 1916 { 1917 1918 PMAP_LOCK_INIT(pm); 1919 moea64_pinit(mmu, pm); 1920 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1921 } 1922 1923 /* 1924 * Set the physical protection on the specified range of this map as requested. 1925 */ 1926 static void 1927 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1928 { 1929 uintptr_t pt; 1930 struct vm_page *pg; 1931 uint64_t oldlo; 1932 1933 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1934 1935 /* 1936 * Grab the PTE pointer before we diddle with the cached PTE 1937 * copy. 1938 */ 1939 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1940 1941 /* 1942 * Change the protection of the page. 1943 */ 1944 oldlo = pvo->pvo_pte.lpte.pte_lo; 1945 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1946 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1947 if ((prot & VM_PROT_EXECUTE) == 0) 1948 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1949 if (prot & VM_PROT_WRITE) 1950 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1951 else 1952 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1953 1954 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1955 1956 /* 1957 * If the PVO is in the page table, update that pte as well. 1958 */ 1959 if (pt != -1) 1960 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1961 pvo->pvo_vpn); 1962 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1963 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1964 if ((pg->oflags & VPO_UNMANAGED) == 0) 1965 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1966 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1967 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1968 } 1969 1970 /* 1971 * Update vm about the REF/CHG bits if the page is managed and we have 1972 * removed write access. 1973 */ 1974 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1975 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1976 if (pg != NULL) { 1977 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1978 vm_page_dirty(pg); 1979 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1980 vm_page_aflag_set(pg, PGA_REFERENCED); 1981 } 1982 } 1983 } 1984 1985 void 1986 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1987 vm_prot_t prot) 1988 { 1989 struct pvo_entry *pvo, *tpvo, key; 1990 1991 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1992 sva, eva, prot); 1993 1994 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1995 ("moea64_protect: non current pmap")); 1996 1997 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1998 moea64_remove(mmu, pm, sva, eva); 1999 return; 2000 } 2001 2002 LOCK_TABLE_RD(); 2003 PMAP_LOCK(pm); 2004 key.pvo_vaddr = sva; 2005 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2006 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2007 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2008 moea64_pvo_protect(mmu, pm, pvo, prot); 2009 } 2010 UNLOCK_TABLE_RD(); 2011 PMAP_UNLOCK(pm); 2012 } 2013 2014 /* 2015 * Map a list of wired pages into kernel virtual address space. This is 2016 * intended for temporary mappings which do not need page modification or 2017 * references recorded. Existing mappings in the region are overwritten. 2018 */ 2019 void 2020 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2021 { 2022 while (count-- > 0) { 2023 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2024 va += PAGE_SIZE; 2025 m++; 2026 } 2027 } 2028 2029 /* 2030 * Remove page mappings from kernel virtual address space. Intended for 2031 * temporary mappings entered by moea64_qenter. 2032 */ 2033 void 2034 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2035 { 2036 while (count-- > 0) { 2037 moea64_kremove(mmu, va); 2038 va += PAGE_SIZE; 2039 } 2040 } 2041 2042 void 2043 moea64_release_vsid(uint64_t vsid) 2044 { 2045 int idx, mask; 2046 2047 mtx_lock(&moea64_slb_mutex); 2048 idx = vsid & (NVSIDS-1); 2049 mask = 1 << (idx % VSID_NBPW); 2050 idx /= VSID_NBPW; 2051 KASSERT(moea64_vsid_bitmap[idx] & mask, 2052 ("Freeing unallocated VSID %#jx", vsid)); 2053 moea64_vsid_bitmap[idx] &= ~mask; 2054 mtx_unlock(&moea64_slb_mutex); 2055 } 2056 2057 2058 void 2059 moea64_release(mmu_t mmu, pmap_t pmap) 2060 { 2061 2062 /* 2063 * Free segment registers' VSIDs 2064 */ 2065 #ifdef __powerpc64__ 2066 slb_free_tree(pmap); 2067 slb_free_user_cache(pmap->pm_slb); 2068 #else 2069 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2070 2071 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2072 #endif 2073 } 2074 2075 /* 2076 * Remove all pages mapped by the specified pmap 2077 */ 2078 void 2079 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2080 { 2081 struct pvo_entry *pvo, *tpvo; 2082 2083 LOCK_TABLE_WR(); 2084 PMAP_LOCK(pm); 2085 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2086 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2087 moea64_pvo_remove(mmu, pvo); 2088 } 2089 UNLOCK_TABLE_WR(); 2090 PMAP_UNLOCK(pm); 2091 } 2092 2093 /* 2094 * Remove the given range of addresses from the specified map. 2095 */ 2096 void 2097 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2098 { 2099 struct pvo_entry *pvo, *tpvo, key; 2100 2101 /* 2102 * Perform an unsynchronized read. This is, however, safe. 2103 */ 2104 if (pm->pm_stats.resident_count == 0) 2105 return; 2106 2107 LOCK_TABLE_WR(); 2108 PMAP_LOCK(pm); 2109 key.pvo_vaddr = sva; 2110 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2111 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2112 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2113 moea64_pvo_remove(mmu, pvo); 2114 } 2115 UNLOCK_TABLE_WR(); 2116 PMAP_UNLOCK(pm); 2117 } 2118 2119 /* 2120 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2121 * will reflect changes in pte's back to the vm_page. 2122 */ 2123 void 2124 moea64_remove_all(mmu_t mmu, vm_page_t m) 2125 { 2126 struct pvo_entry *pvo, *next_pvo; 2127 pmap_t pmap; 2128 2129 LOCK_TABLE_WR(); 2130 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2131 pmap = pvo->pvo_pmap; 2132 PMAP_LOCK(pmap); 2133 moea64_pvo_remove(mmu, pvo); 2134 PMAP_UNLOCK(pmap); 2135 } 2136 UNLOCK_TABLE_WR(); 2137 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2138 vm_page_dirty(m); 2139 vm_page_aflag_clear(m, PGA_WRITEABLE); 2140 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2141 } 2142 2143 /* 2144 * Allocate a physical page of memory directly from the phys_avail map. 2145 * Can only be called from moea64_bootstrap before avail start and end are 2146 * calculated. 2147 */ 2148 vm_offset_t 2149 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2150 { 2151 vm_offset_t s, e; 2152 int i, j; 2153 2154 size = round_page(size); 2155 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2156 if (align != 0) 2157 s = (phys_avail[i] + align - 1) & ~(align - 1); 2158 else 2159 s = phys_avail[i]; 2160 e = s + size; 2161 2162 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2163 continue; 2164 2165 if (s + size > platform_real_maxaddr()) 2166 continue; 2167 2168 if (s == phys_avail[i]) { 2169 phys_avail[i] += size; 2170 } else if (e == phys_avail[i + 1]) { 2171 phys_avail[i + 1] -= size; 2172 } else { 2173 for (j = phys_avail_count * 2; j > i; j -= 2) { 2174 phys_avail[j] = phys_avail[j - 2]; 2175 phys_avail[j + 1] = phys_avail[j - 1]; 2176 } 2177 2178 phys_avail[i + 3] = phys_avail[i + 1]; 2179 phys_avail[i + 1] = s; 2180 phys_avail[i + 2] = e; 2181 phys_avail_count++; 2182 } 2183 2184 return (s); 2185 } 2186 panic("moea64_bootstrap_alloc: could not allocate memory"); 2187 } 2188 2189 static int 2190 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2191 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2192 uint64_t pte_lo, int flags, int8_t psind __unused) 2193 { 2194 struct pvo_entry *pvo; 2195 uintptr_t pt; 2196 uint64_t vsid; 2197 int first; 2198 u_int ptegidx; 2199 int i; 2200 int bootstrap; 2201 2202 /* 2203 * One nasty thing that can happen here is that the UMA calls to 2204 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2205 * which calls UMA... 2206 * 2207 * We break the loop by detecting recursion and allocating out of 2208 * the bootstrap pool. 2209 */ 2210 2211 first = 0; 2212 bootstrap = (flags & PVO_BOOTSTRAP); 2213 2214 if (!moea64_initialized) 2215 bootstrap = 1; 2216 2217 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2218 rw_assert(&moea64_table_lock, RA_WLOCKED); 2219 2220 /* 2221 * Compute the PTE Group index. 2222 */ 2223 va &= ~ADDR_POFF; 2224 vsid = va_to_vsid(pm, va); 2225 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2226 2227 /* 2228 * Remove any existing mapping for this page. Reuse the pvo entry if 2229 * there is a mapping. 2230 */ 2231 moea64_pvo_enter_calls++; 2232 2233 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2234 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2235 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2236 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2237 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2238 /* 2239 * The physical page and protection are not 2240 * changing. Instead, this may be a request 2241 * to change the mapping's wired attribute. 2242 */ 2243 pt = -1; 2244 if ((flags & PVO_WIRED) != 0 && 2245 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2246 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2247 pvo->pvo_vaddr |= PVO_WIRED; 2248 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2249 pm->pm_stats.wired_count++; 2250 } else if ((flags & PVO_WIRED) == 0 && 2251 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2252 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2253 pvo->pvo_vaddr &= ~PVO_WIRED; 2254 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 2255 pm->pm_stats.wired_count--; 2256 } 2257 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2258 KASSERT(pt == -1, 2259 ("moea64_pvo_enter: valid pt")); 2260 /* Re-insert if spilled */ 2261 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2262 &pvo->pvo_pte.lpte); 2263 if (i >= 0) 2264 PVO_PTEGIDX_SET(pvo, i); 2265 moea64_pte_overflow--; 2266 } else if (pt != -1) { 2267 /* 2268 * The PTE's wired attribute is not a 2269 * hardware feature, so there is no 2270 * need to invalidate any TLB entries. 2271 */ 2272 MOEA64_PTE_CHANGE(mmu, pt, 2273 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2274 } 2275 return (0); 2276 } 2277 moea64_pvo_remove(mmu, pvo); 2278 break; 2279 } 2280 } 2281 2282 /* 2283 * If we aren't overwriting a mapping, try to allocate. 2284 */ 2285 if (bootstrap) { 2286 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 2287 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2288 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 2289 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 2290 } 2291 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2292 moea64_bpvo_pool_index++; 2293 bootstrap = 1; 2294 } else { 2295 pvo = uma_zalloc(zone, M_NOWAIT); 2296 } 2297 2298 if (pvo == NULL) 2299 return (ENOMEM); 2300 2301 moea64_pvo_entries++; 2302 pvo->pvo_vaddr = va; 2303 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2304 | (vsid << 16); 2305 pvo->pvo_pmap = pm; 2306 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2307 pvo->pvo_vaddr &= ~ADDR_POFF; 2308 2309 if (flags & PVO_WIRED) 2310 pvo->pvo_vaddr |= PVO_WIRED; 2311 if (pvo_head != NULL) 2312 pvo->pvo_vaddr |= PVO_MANAGED; 2313 if (bootstrap) 2314 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2315 if (flags & PVO_LARGE) 2316 pvo->pvo_vaddr |= PVO_LARGE; 2317 2318 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2319 (uint64_t)(pa) | pte_lo, flags); 2320 2321 /* 2322 * Add to pmap list 2323 */ 2324 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2325 2326 /* 2327 * Remember if the list was empty and therefore will be the first 2328 * item. 2329 */ 2330 if (pvo_head != NULL) { 2331 if (LIST_FIRST(pvo_head) == NULL) 2332 first = 1; 2333 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2334 } 2335 2336 if (pvo->pvo_vaddr & PVO_WIRED) { 2337 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2338 pm->pm_stats.wired_count++; 2339 } 2340 pm->pm_stats.resident_count++; 2341 2342 /* 2343 * We hope this succeeds but it isn't required. 2344 */ 2345 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2346 if (i >= 0) { 2347 PVO_PTEGIDX_SET(pvo, i); 2348 } else { 2349 panic("moea64_pvo_enter: overflow"); 2350 moea64_pte_overflow++; 2351 } 2352 2353 if (pm == kernel_pmap) 2354 isync(); 2355 2356 #ifdef __powerpc64__ 2357 /* 2358 * Make sure all our bootstrap mappings are in the SLB as soon 2359 * as virtual memory is switched on. 2360 */ 2361 if (!pmap_bootstrapped) 2362 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2363 #endif 2364 2365 return (first ? ENOENT : 0); 2366 } 2367 2368 static void 2369 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2370 { 2371 struct vm_page *pg; 2372 uintptr_t pt; 2373 2374 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2375 rw_assert(&moea64_table_lock, RA_WLOCKED); 2376 2377 /* 2378 * If there is an active pte entry, we need to deactivate it (and 2379 * save the ref & cfg bits). 2380 */ 2381 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2382 if (pt != -1) { 2383 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2384 PVO_PTEGIDX_CLR(pvo); 2385 } else { 2386 moea64_pte_overflow--; 2387 } 2388 2389 /* 2390 * Update our statistics. 2391 */ 2392 pvo->pvo_pmap->pm_stats.resident_count--; 2393 if (pvo->pvo_vaddr & PVO_WIRED) 2394 pvo->pvo_pmap->pm_stats.wired_count--; 2395 2396 /* 2397 * Remove this PVO from the pmap list. 2398 */ 2399 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2400 2401 /* 2402 * Remove this from the overflow list and return it to the pool 2403 * if we aren't going to reuse it. 2404 */ 2405 LIST_REMOVE(pvo, pvo_olink); 2406 2407 /* 2408 * Update vm about the REF/CHG bits if the page is managed. 2409 */ 2410 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2411 2412 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2413 LIST_REMOVE(pvo, pvo_vlink); 2414 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2415 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2416 vm_page_dirty(pg); 2417 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2418 vm_page_aflag_set(pg, PGA_REFERENCED); 2419 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2420 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2421 } 2422 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2423 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2424 } 2425 2426 moea64_pvo_entries--; 2427 moea64_pvo_remove_calls++; 2428 2429 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2430 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2431 moea64_upvo_zone, pvo); 2432 } 2433 2434 static struct pvo_entry * 2435 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2436 { 2437 struct pvo_entry key; 2438 2439 key.pvo_vaddr = va & ~ADDR_POFF; 2440 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2441 } 2442 2443 static boolean_t 2444 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2445 { 2446 struct pvo_entry *pvo; 2447 uintptr_t pt; 2448 2449 LOCK_TABLE_RD(); 2450 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2451 /* 2452 * See if we saved the bit off. If so, return success. 2453 */ 2454 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2455 UNLOCK_TABLE_RD(); 2456 return (TRUE); 2457 } 2458 } 2459 2460 /* 2461 * No luck, now go through the hard part of looking at the PTEs 2462 * themselves. Sync so that any pending REF/CHG bits are flushed to 2463 * the PTEs. 2464 */ 2465 powerpc_sync(); 2466 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2467 2468 /* 2469 * See if this pvo has a valid PTE. if so, fetch the 2470 * REF/CHG bits from the valid PTE. If the appropriate 2471 * ptebit is set, return success. 2472 */ 2473 PMAP_LOCK(pvo->pvo_pmap); 2474 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2475 if (pt != -1) { 2476 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2477 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2478 PMAP_UNLOCK(pvo->pvo_pmap); 2479 UNLOCK_TABLE_RD(); 2480 return (TRUE); 2481 } 2482 } 2483 PMAP_UNLOCK(pvo->pvo_pmap); 2484 } 2485 2486 UNLOCK_TABLE_RD(); 2487 return (FALSE); 2488 } 2489 2490 static u_int 2491 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2492 { 2493 u_int count; 2494 struct pvo_entry *pvo; 2495 uintptr_t pt; 2496 2497 /* 2498 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2499 * we can reset the right ones). note that since the pvo entries and 2500 * list heads are accessed via BAT0 and are never placed in the page 2501 * table, we don't have to worry about further accesses setting the 2502 * REF/CHG bits. 2503 */ 2504 powerpc_sync(); 2505 2506 /* 2507 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2508 * valid pte clear the ptebit from the valid pte. 2509 */ 2510 count = 0; 2511 LOCK_TABLE_RD(); 2512 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2513 PMAP_LOCK(pvo->pvo_pmap); 2514 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2515 if (pt != -1) { 2516 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2517 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2518 count++; 2519 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2520 pvo->pvo_vpn, ptebit); 2521 } 2522 } 2523 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2524 PMAP_UNLOCK(pvo->pvo_pmap); 2525 } 2526 2527 UNLOCK_TABLE_RD(); 2528 return (count); 2529 } 2530 2531 boolean_t 2532 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2533 { 2534 struct pvo_entry *pvo, key; 2535 vm_offset_t ppa; 2536 int error = 0; 2537 2538 PMAP_LOCK(kernel_pmap); 2539 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2540 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2541 ppa < pa + size; ppa += PAGE_SIZE, 2542 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2543 if (pvo == NULL || 2544 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2545 error = EFAULT; 2546 break; 2547 } 2548 } 2549 PMAP_UNLOCK(kernel_pmap); 2550 2551 return (error); 2552 } 2553 2554 /* 2555 * Map a set of physical memory pages into the kernel virtual 2556 * address space. Return a pointer to where it is mapped. This 2557 * routine is intended to be used for mapping device memory, 2558 * NOT real memory. 2559 */ 2560 void * 2561 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2562 { 2563 vm_offset_t va, tmpva, ppa, offset; 2564 2565 ppa = trunc_page(pa); 2566 offset = pa & PAGE_MASK; 2567 size = roundup2(offset + size, PAGE_SIZE); 2568 2569 va = kva_alloc(size); 2570 2571 if (!va) 2572 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2573 2574 for (tmpva = va; size > 0;) { 2575 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2576 size -= PAGE_SIZE; 2577 tmpva += PAGE_SIZE; 2578 ppa += PAGE_SIZE; 2579 } 2580 2581 return ((void *)(va + offset)); 2582 } 2583 2584 void * 2585 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2586 { 2587 2588 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2589 } 2590 2591 void 2592 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2593 { 2594 vm_offset_t base, offset; 2595 2596 base = trunc_page(va); 2597 offset = va & PAGE_MASK; 2598 size = roundup2(offset + size, PAGE_SIZE); 2599 2600 kva_free(base, size); 2601 } 2602 2603 void 2604 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2605 { 2606 struct pvo_entry *pvo; 2607 vm_offset_t lim; 2608 vm_paddr_t pa; 2609 vm_size_t len; 2610 2611 PMAP_LOCK(pm); 2612 while (sz > 0) { 2613 lim = round_page(va); 2614 len = MIN(lim - va, sz); 2615 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2616 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2617 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2618 (va & ADDR_POFF); 2619 moea64_syncicache(mmu, pm, va, pa, len); 2620 } 2621 va += len; 2622 sz -= len; 2623 } 2624 PMAP_UNLOCK(pm); 2625 } 2626 2627 void 2628 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2629 { 2630 2631 *va = (void *)pa; 2632 } 2633 2634 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2635 2636 void 2637 moea64_scan_init(mmu_t mmu) 2638 { 2639 struct pvo_entry *pvo; 2640 vm_offset_t va; 2641 int i; 2642 2643 if (!do_minidump) { 2644 /* Initialize phys. segments for dumpsys(). */ 2645 memset(&dump_map, 0, sizeof(dump_map)); 2646 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2647 for (i = 0; i < pregions_sz; i++) { 2648 dump_map[i].pa_start = pregions[i].mr_start; 2649 dump_map[i].pa_size = pregions[i].mr_size; 2650 } 2651 return; 2652 } 2653 2654 /* Virtual segments for minidumps: */ 2655 memset(&dump_map, 0, sizeof(dump_map)); 2656 2657 /* 1st: kernel .data and .bss. */ 2658 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2659 dump_map[0].pa_size = round_page((uintptr_t)_end) - dump_map[0].pa_start; 2660 2661 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2662 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2663 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2664 2665 /* 3rd: kernel VM. */ 2666 va = dump_map[1].pa_start + dump_map[1].pa_size; 2667 /* Find start of next chunk (from va). */ 2668 while (va < virtual_end) { 2669 /* Don't dump the buffer cache. */ 2670 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2671 va = kmi.buffer_eva; 2672 continue; 2673 } 2674 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2675 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2676 break; 2677 va += PAGE_SIZE; 2678 } 2679 if (va < virtual_end) { 2680 dump_map[2].pa_start = va; 2681 va += PAGE_SIZE; 2682 /* Find last page in chunk. */ 2683 while (va < virtual_end) { 2684 /* Don't run into the buffer cache. */ 2685 if (va == kmi.buffer_sva) 2686 break; 2687 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2688 if (pvo == NULL || 2689 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2690 break; 2691 va += PAGE_SIZE; 2692 } 2693 dump_map[2].pa_size = va - dump_map[2].pa_start; 2694 } 2695 } 2696