1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mman.h> 61 #include <sys/mutex.h> 62 #include <sys/proc.h> 63 #include <sys/rwlock.h> 64 #include <sys/sched.h> 65 #include <sys/sysctl.h> 66 #include <sys/systm.h> 67 #include <sys/vmmeter.h> 68 #include <sys/smp.h> 69 #include <sys/reboot.h> 70 71 #include <sys/kdb.h> 72 73 #include <dev/ofw/openfirm.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 #include <vm/vm_param.h> 78 #include <vm/vm_kern.h> 79 #include <vm/vm_page.h> 80 #include <vm/vm_phys.h> 81 #include <vm/vm_map.h> 82 #include <vm/vm_object.h> 83 #include <vm/vm_extern.h> 84 #include <vm/vm_pageout.h> 85 #include <vm/vm_dumpset.h> 86 #include <vm/vm_reserv.h> 87 #include <vm/uma.h> 88 89 #include <machine/_inttypes.h> 90 #include <machine/cpu.h> 91 #include <machine/ifunc.h> 92 #include <machine/platform.h> 93 #include <machine/frame.h> 94 #include <machine/md_var.h> 95 #include <machine/psl.h> 96 #include <machine/bat.h> 97 #include <machine/hid.h> 98 #include <machine/pte.h> 99 #include <machine/sr.h> 100 #include <machine/trap.h> 101 #include <machine/mmuvar.h> 102 103 #include "mmu_oea64.h" 104 105 void moea64_release_vsid(uint64_t vsid); 106 uintptr_t moea64_get_unique_vsid(void); 107 108 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 109 #define ENABLE_TRANS(msr) mtmsr(msr) 110 111 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 112 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 113 #define VSID_HASH_MASK 0x0000007fffffffffULL 114 115 /* 116 * Locking semantics: 117 * 118 * There are two locks of interest: the page locks and the pmap locks, which 119 * protect their individual PVO lists and are locked in that order. The contents 120 * of all PVO entries are protected by the locks of their respective pmaps. 121 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 122 * into any list. 123 * 124 */ 125 126 #define PV_LOCK_COUNT PA_LOCK_COUNT 127 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 128 129 /* 130 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 131 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 132 * index at (N << 45). 133 */ 134 #ifdef __powerpc64__ 135 #define PV_LOCK_IDX(pa) ((pa_index(pa) * (((pa) >> 45) + 1)) % PV_LOCK_COUNT) 136 #else 137 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 138 #endif 139 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 140 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 141 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 142 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 143 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 144 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 145 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 146 147 /* Superpage PV lock */ 148 149 #define PV_LOCK_SIZE (1<<PDRSHIFT) 150 151 static __always_inline void 152 moea64_sp_pv_lock(vm_paddr_t pa) 153 { 154 vm_paddr_t pa_end; 155 156 /* Note: breaking when pa_end is reached to avoid overflows */ 157 pa_end = pa + (HPT_SP_SIZE - PV_LOCK_SIZE); 158 for (;;) { 159 mtx_lock_flags(PV_LOCKPTR(pa), MTX_DUPOK); 160 if (pa == pa_end) 161 break; 162 pa += PV_LOCK_SIZE; 163 } 164 } 165 166 static __always_inline void 167 moea64_sp_pv_unlock(vm_paddr_t pa) 168 { 169 vm_paddr_t pa_end; 170 171 /* Note: breaking when pa_end is reached to avoid overflows */ 172 pa_end = pa; 173 pa += HPT_SP_SIZE - PV_LOCK_SIZE; 174 for (;;) { 175 mtx_unlock_flags(PV_LOCKPTR(pa), MTX_DUPOK); 176 if (pa == pa_end) 177 break; 178 pa -= PV_LOCK_SIZE; 179 } 180 } 181 182 #define SP_PV_LOCK_ALIGNED(pa) moea64_sp_pv_lock(pa) 183 #define SP_PV_UNLOCK_ALIGNED(pa) moea64_sp_pv_unlock(pa) 184 #define SP_PV_LOCK(pa) moea64_sp_pv_lock((pa) & ~HPT_SP_MASK) 185 #define SP_PV_UNLOCK(pa) moea64_sp_pv_unlock((pa) & ~HPT_SP_MASK) 186 #define SP_PV_PAGE_LOCK(m) SP_PV_LOCK(VM_PAGE_TO_PHYS(m)) 187 #define SP_PV_PAGE_UNLOCK(m) SP_PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 188 189 struct ofw_map { 190 cell_t om_va; 191 cell_t om_len; 192 uint64_t om_pa; 193 cell_t om_mode; 194 }; 195 196 extern unsigned char _etext[]; 197 extern unsigned char _end[]; 198 199 extern void *slbtrap, *slbtrapend; 200 201 /* 202 * Map of physical memory regions. 203 */ 204 static struct mem_region *regions; 205 static struct mem_region *pregions; 206 static struct numa_mem_region *numa_pregions; 207 static u_int phys_avail_count; 208 static int regions_sz, pregions_sz, numapregions_sz; 209 210 extern void bs_remap_earlyboot(void); 211 212 /* 213 * Lock for the SLB tables. 214 */ 215 struct mtx moea64_slb_mutex; 216 217 /* 218 * PTEG data. 219 */ 220 u_long moea64_pteg_count; 221 u_long moea64_pteg_mask; 222 223 /* 224 * PVO data. 225 */ 226 227 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 228 229 static struct pvo_entry *moea64_bpvo_pool; 230 static int moea64_bpvo_pool_index = 0; 231 static int moea64_bpvo_pool_size = 0; 232 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 233 &moea64_bpvo_pool_index, 0, ""); 234 235 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */ 236 #define BPVO_POOL_EXPANSION_FACTOR 3 237 #define VSID_NBPW (sizeof(u_int32_t) * 8) 238 #ifdef __powerpc64__ 239 #define NVSIDS (NPMAPS * 16) 240 #define VSID_HASHMASK 0xffffffffUL 241 #else 242 #define NVSIDS NPMAPS 243 #define VSID_HASHMASK 0xfffffUL 244 #endif 245 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 246 247 static boolean_t moea64_initialized = FALSE; 248 249 #ifdef MOEA64_STATS 250 /* 251 * Statistics. 252 */ 253 u_int moea64_pte_valid = 0; 254 u_int moea64_pte_overflow = 0; 255 u_int moea64_pvo_entries = 0; 256 u_int moea64_pvo_enter_calls = 0; 257 u_int moea64_pvo_remove_calls = 0; 258 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 259 &moea64_pte_valid, 0, ""); 260 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 261 &moea64_pte_overflow, 0, ""); 262 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 263 &moea64_pvo_entries, 0, ""); 264 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 265 &moea64_pvo_enter_calls, 0, ""); 266 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 267 &moea64_pvo_remove_calls, 0, ""); 268 #endif 269 270 vm_offset_t moea64_scratchpage_va[2]; 271 struct pvo_entry *moea64_scratchpage_pvo[2]; 272 struct mtx moea64_scratchpage_mtx; 273 274 uint64_t moea64_large_page_mask = 0; 275 uint64_t moea64_large_page_size = 0; 276 int moea64_large_page_shift = 0; 277 bool moea64_has_lp_4k_16m = false; 278 279 /* 280 * PVO calls. 281 */ 282 static int moea64_pvo_enter(struct pvo_entry *pvo, 283 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 284 static void moea64_pvo_remove_from_pmap(struct pvo_entry *pvo); 285 static void moea64_pvo_remove_from_page(struct pvo_entry *pvo); 286 static void moea64_pvo_remove_from_page_locked( 287 struct pvo_entry *pvo, vm_page_t m); 288 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 289 290 /* 291 * Utility routines. 292 */ 293 static boolean_t moea64_query_bit(vm_page_t, uint64_t); 294 static u_int moea64_clear_bit(vm_page_t, uint64_t); 295 static void moea64_kremove(vm_offset_t); 296 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 297 vm_paddr_t pa, vm_size_t sz); 298 static void moea64_pmap_init_qpages(void); 299 static void moea64_remove_locked(pmap_t, vm_offset_t, 300 vm_offset_t, struct pvo_dlist *); 301 302 /* 303 * Superpages data and routines. 304 */ 305 306 /* 307 * PVO flags (in vaddr) that must match for promotion to succeed. 308 * Note that protection bits are checked separately, as they reside in 309 * another field. 310 */ 311 #define PVO_FLAGS_PROMOTE (PVO_WIRED | PVO_MANAGED | PVO_PTEGIDX_VALID) 312 313 #define PVO_IS_SP(pvo) (((pvo)->pvo_vaddr & PVO_LARGE) && \ 314 (pvo)->pvo_pmap != kernel_pmap) 315 316 /* Get physical address from PVO. */ 317 #define PVO_PADDR(pvo) moea64_pvo_paddr(pvo) 318 319 /* MD page flag indicating that the page is a superpage. */ 320 #define MDPG_ATTR_SP 0x40000000 321 322 SYSCTL_DECL(_vm_pmap); 323 324 static SYSCTL_NODE(_vm_pmap, OID_AUTO, sp, CTLFLAG_RD, 0, 325 "SP page mapping counters"); 326 327 static u_long sp_demotions; 328 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, demotions, CTLFLAG_RD, 329 &sp_demotions, 0, "SP page demotions"); 330 331 static u_long sp_mappings; 332 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, mappings, CTLFLAG_RD, 333 &sp_mappings, 0, "SP page mappings"); 334 335 static u_long sp_p_failures; 336 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_failures, CTLFLAG_RD, 337 &sp_p_failures, 0, "SP page promotion failures"); 338 339 static u_long sp_p_fail_pa; 340 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_pa, CTLFLAG_RD, 341 &sp_p_fail_pa, 0, "SP page promotion failure: PAs don't match"); 342 343 static u_long sp_p_fail_flags; 344 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_flags, CTLFLAG_RD, 345 &sp_p_fail_flags, 0, "SP page promotion failure: page flags don't match"); 346 347 static u_long sp_p_fail_prot; 348 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_prot, CTLFLAG_RD, 349 &sp_p_fail_prot, 0, 350 "SP page promotion failure: page protections don't match"); 351 352 static u_long sp_p_fail_wimg; 353 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, p_fail_wimg, CTLFLAG_RD, 354 &sp_p_fail_wimg, 0, "SP page promotion failure: WIMG bits don't match"); 355 356 static u_long sp_promotions; 357 SYSCTL_ULONG(_vm_pmap_sp, OID_AUTO, promotions, CTLFLAG_RD, 358 &sp_promotions, 0, "SP page promotions"); 359 360 static bool moea64_ps_enabled(pmap_t); 361 static void moea64_align_superpage(vm_object_t, vm_ooffset_t, 362 vm_offset_t *, vm_size_t); 363 364 static int moea64_sp_enter(pmap_t pmap, vm_offset_t va, 365 vm_page_t m, vm_prot_t prot, u_int flags, int8_t psind); 366 static struct pvo_entry *moea64_sp_remove(struct pvo_entry *sp, 367 struct pvo_dlist *tofree); 368 369 static void moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m); 370 static void moea64_sp_demote_aligned(struct pvo_entry *sp); 371 static void moea64_sp_demote(struct pvo_entry *pvo); 372 373 static struct pvo_entry *moea64_sp_unwire(struct pvo_entry *sp); 374 static struct pvo_entry *moea64_sp_protect(struct pvo_entry *sp, 375 vm_prot_t prot); 376 377 static int64_t moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit); 378 static int64_t moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, 379 uint64_t ptebit); 380 381 static __inline bool moea64_sp_pvo_in_range(struct pvo_entry *pvo, 382 vm_offset_t sva, vm_offset_t eva); 383 384 /* 385 * Kernel MMU interface 386 */ 387 void moea64_clear_modify(vm_page_t); 388 void moea64_copy_page(vm_page_t, vm_page_t); 389 void moea64_copy_page_dmap(vm_page_t, vm_page_t); 390 void moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 391 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 392 void moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 393 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 394 int moea64_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 395 u_int flags, int8_t psind); 396 void moea64_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 397 vm_prot_t); 398 void moea64_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 399 vm_paddr_t moea64_extract(pmap_t, vm_offset_t); 400 vm_page_t moea64_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 401 void moea64_init(void); 402 boolean_t moea64_is_modified(vm_page_t); 403 boolean_t moea64_is_prefaultable(pmap_t, vm_offset_t); 404 boolean_t moea64_is_referenced(vm_page_t); 405 int moea64_ts_referenced(vm_page_t); 406 vm_offset_t moea64_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 407 boolean_t moea64_page_exists_quick(pmap_t, vm_page_t); 408 void moea64_page_init(vm_page_t); 409 int moea64_page_wired_mappings(vm_page_t); 410 int moea64_pinit(pmap_t); 411 void moea64_pinit0(pmap_t); 412 void moea64_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 413 void moea64_qenter(vm_offset_t, vm_page_t *, int); 414 void moea64_qremove(vm_offset_t, int); 415 void moea64_release(pmap_t); 416 void moea64_remove(pmap_t, vm_offset_t, vm_offset_t); 417 void moea64_remove_pages(pmap_t); 418 void moea64_remove_all(vm_page_t); 419 void moea64_remove_write(vm_page_t); 420 void moea64_unwire(pmap_t, vm_offset_t, vm_offset_t); 421 void moea64_zero_page(vm_page_t); 422 void moea64_zero_page_dmap(vm_page_t); 423 void moea64_zero_page_area(vm_page_t, int, int); 424 void moea64_activate(struct thread *); 425 void moea64_deactivate(struct thread *); 426 void *moea64_mapdev(vm_paddr_t, vm_size_t); 427 void *moea64_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 428 void moea64_unmapdev(vm_offset_t, vm_size_t); 429 vm_paddr_t moea64_kextract(vm_offset_t); 430 void moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma); 431 void moea64_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t ma); 432 void moea64_kenter(vm_offset_t, vm_paddr_t); 433 boolean_t moea64_dev_direct_mapped(vm_paddr_t, vm_size_t); 434 static void moea64_sync_icache(pmap_t, vm_offset_t, vm_size_t); 435 void moea64_dumpsys_map(vm_paddr_t pa, size_t sz, 436 void **va); 437 void moea64_scan_init(void); 438 vm_offset_t moea64_quick_enter_page(vm_page_t m); 439 vm_offset_t moea64_quick_enter_page_dmap(vm_page_t m); 440 void moea64_quick_remove_page(vm_offset_t addr); 441 boolean_t moea64_page_is_mapped(vm_page_t m); 442 static int moea64_map_user_ptr(pmap_t pm, 443 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 444 static int moea64_decode_kernel_ptr(vm_offset_t addr, 445 int *is_user, vm_offset_t *decoded_addr); 446 static size_t moea64_scan_pmap(void); 447 static void *moea64_dump_pmap_init(unsigned blkpgs); 448 #ifdef __powerpc64__ 449 static void moea64_page_array_startup(long); 450 #endif 451 static int moea64_mincore(pmap_t, vm_offset_t, vm_paddr_t *); 452 453 static struct pmap_funcs moea64_methods = { 454 .clear_modify = moea64_clear_modify, 455 .copy_page = moea64_copy_page, 456 .copy_pages = moea64_copy_pages, 457 .enter = moea64_enter, 458 .enter_object = moea64_enter_object, 459 .enter_quick = moea64_enter_quick, 460 .extract = moea64_extract, 461 .extract_and_hold = moea64_extract_and_hold, 462 .init = moea64_init, 463 .is_modified = moea64_is_modified, 464 .is_prefaultable = moea64_is_prefaultable, 465 .is_referenced = moea64_is_referenced, 466 .ts_referenced = moea64_ts_referenced, 467 .map = moea64_map, 468 .mincore = moea64_mincore, 469 .page_exists_quick = moea64_page_exists_quick, 470 .page_init = moea64_page_init, 471 .page_wired_mappings = moea64_page_wired_mappings, 472 .pinit = moea64_pinit, 473 .pinit0 = moea64_pinit0, 474 .protect = moea64_protect, 475 .qenter = moea64_qenter, 476 .qremove = moea64_qremove, 477 .release = moea64_release, 478 .remove = moea64_remove, 479 .remove_pages = moea64_remove_pages, 480 .remove_all = moea64_remove_all, 481 .remove_write = moea64_remove_write, 482 .sync_icache = moea64_sync_icache, 483 .unwire = moea64_unwire, 484 .zero_page = moea64_zero_page, 485 .zero_page_area = moea64_zero_page_area, 486 .activate = moea64_activate, 487 .deactivate = moea64_deactivate, 488 .page_set_memattr = moea64_page_set_memattr, 489 .quick_enter_page = moea64_quick_enter_page, 490 .quick_remove_page = moea64_quick_remove_page, 491 .page_is_mapped = moea64_page_is_mapped, 492 #ifdef __powerpc64__ 493 .page_array_startup = moea64_page_array_startup, 494 #endif 495 .ps_enabled = moea64_ps_enabled, 496 .align_superpage = moea64_align_superpage, 497 498 /* Internal interfaces */ 499 .mapdev = moea64_mapdev, 500 .mapdev_attr = moea64_mapdev_attr, 501 .unmapdev = moea64_unmapdev, 502 .kextract = moea64_kextract, 503 .kenter = moea64_kenter, 504 .kenter_attr = moea64_kenter_attr, 505 .dev_direct_mapped = moea64_dev_direct_mapped, 506 .dumpsys_pa_init = moea64_scan_init, 507 .dumpsys_scan_pmap = moea64_scan_pmap, 508 .dumpsys_dump_pmap_init = moea64_dump_pmap_init, 509 .dumpsys_map_chunk = moea64_dumpsys_map, 510 .map_user_ptr = moea64_map_user_ptr, 511 .decode_kernel_ptr = moea64_decode_kernel_ptr, 512 }; 513 514 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods); 515 516 /* 517 * Get physical address from PVO. 518 * 519 * For superpages, the lower bits are not stored on pvo_pte.pa and must be 520 * obtained from VA. 521 */ 522 static __always_inline vm_paddr_t 523 moea64_pvo_paddr(struct pvo_entry *pvo) 524 { 525 vm_paddr_t pa; 526 527 pa = (pvo)->pvo_pte.pa & LPTE_RPGN; 528 529 if (PVO_IS_SP(pvo)) { 530 pa &= ~HPT_SP_MASK; /* This is needed to clear LPTE_LP bits. */ 531 pa |= PVO_VADDR(pvo) & HPT_SP_MASK; 532 } 533 return (pa); 534 } 535 536 static struct pvo_head * 537 vm_page_to_pvoh(vm_page_t m) 538 { 539 540 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 541 return (&m->md.mdpg_pvoh); 542 } 543 544 static struct pvo_entry * 545 alloc_pvo_entry(int bootstrap) 546 { 547 struct pvo_entry *pvo; 548 549 if (!moea64_initialized || bootstrap) { 550 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 551 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 552 "Try setting machdep.moea64_bpvo_pool_size tunable", 553 __func__, moea64_bpvo_pool_index, 554 moea64_bpvo_pool_size, 555 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 556 } 557 pvo = &moea64_bpvo_pool[ 558 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 559 bzero(pvo, sizeof(*pvo)); 560 pvo->pvo_vaddr = PVO_BOOTSTRAP; 561 } else 562 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 563 564 return (pvo); 565 } 566 567 static void 568 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 569 { 570 uint64_t vsid; 571 uint64_t hash; 572 int shift; 573 574 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 575 576 pvo->pvo_pmap = pmap; 577 va &= ~ADDR_POFF; 578 pvo->pvo_vaddr |= va; 579 vsid = va_to_vsid(pmap, va); 580 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 581 | (vsid << 16); 582 583 if (pmap == kernel_pmap && (pvo->pvo_vaddr & PVO_LARGE) != 0) 584 shift = moea64_large_page_shift; 585 else 586 shift = ADDR_PIDX_SHFT; 587 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 588 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 589 } 590 591 static void 592 free_pvo_entry(struct pvo_entry *pvo) 593 { 594 595 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 596 uma_zfree(moea64_pvo_zone, pvo); 597 } 598 599 void 600 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 601 { 602 603 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 604 lpte->pte_hi |= LPTE_VALID; 605 606 if (pvo->pvo_vaddr & PVO_LARGE) 607 lpte->pte_hi |= LPTE_BIG; 608 if (pvo->pvo_vaddr & PVO_WIRED) 609 lpte->pte_hi |= LPTE_WIRED; 610 if (pvo->pvo_vaddr & PVO_HID) 611 lpte->pte_hi |= LPTE_HID; 612 613 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 614 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 615 lpte->pte_lo |= LPTE_BW; 616 else 617 lpte->pte_lo |= LPTE_BR; 618 619 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 620 lpte->pte_lo |= LPTE_NOEXEC; 621 } 622 623 static __inline uint64_t 624 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 625 { 626 uint64_t pte_lo; 627 int i; 628 629 if (ma != VM_MEMATTR_DEFAULT) { 630 switch (ma) { 631 case VM_MEMATTR_UNCACHEABLE: 632 return (LPTE_I | LPTE_G); 633 case VM_MEMATTR_CACHEABLE: 634 return (LPTE_M); 635 case VM_MEMATTR_WRITE_COMBINING: 636 case VM_MEMATTR_WRITE_BACK: 637 case VM_MEMATTR_PREFETCHABLE: 638 return (LPTE_I); 639 case VM_MEMATTR_WRITE_THROUGH: 640 return (LPTE_W | LPTE_M); 641 } 642 } 643 644 /* 645 * Assume the page is cache inhibited and access is guarded unless 646 * it's in our available memory array. 647 */ 648 pte_lo = LPTE_I | LPTE_G; 649 for (i = 0; i < pregions_sz; i++) { 650 if ((pa >= pregions[i].mr_start) && 651 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 652 pte_lo &= ~(LPTE_I | LPTE_G); 653 pte_lo |= LPTE_M; 654 break; 655 } 656 } 657 658 return pte_lo; 659 } 660 661 /* 662 * Quick sort callout for comparing memory regions. 663 */ 664 static int om_cmp(const void *a, const void *b); 665 666 static int 667 om_cmp(const void *a, const void *b) 668 { 669 const struct ofw_map *mapa; 670 const struct ofw_map *mapb; 671 672 mapa = a; 673 mapb = b; 674 if (mapa->om_pa < mapb->om_pa) 675 return (-1); 676 else if (mapa->om_pa > mapb->om_pa) 677 return (1); 678 else 679 return (0); 680 } 681 682 static void 683 moea64_add_ofw_mappings(phandle_t mmu, size_t sz) 684 { 685 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 686 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 687 struct pvo_entry *pvo; 688 register_t msr; 689 vm_offset_t off; 690 vm_paddr_t pa_base; 691 int i, j; 692 693 bzero(translations, sz); 694 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 695 sizeof(acells)); 696 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 697 panic("moea64_bootstrap: can't get ofw translations"); 698 699 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 700 sz /= sizeof(cell_t); 701 for (i = 0, j = 0; i < sz; j++) { 702 translations[j].om_va = trans_cells[i++]; 703 translations[j].om_len = trans_cells[i++]; 704 translations[j].om_pa = trans_cells[i++]; 705 if (acells == 2) { 706 translations[j].om_pa <<= 32; 707 translations[j].om_pa |= trans_cells[i++]; 708 } 709 translations[j].om_mode = trans_cells[i++]; 710 } 711 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 712 i, sz)); 713 714 sz = j; 715 qsort(translations, sz, sizeof (*translations), om_cmp); 716 717 for (i = 0; i < sz; i++) { 718 pa_base = translations[i].om_pa; 719 #ifndef __powerpc64__ 720 if ((translations[i].om_pa >> 32) != 0) 721 panic("OFW translations above 32-bit boundary!"); 722 #endif 723 724 if (pa_base % PAGE_SIZE) 725 panic("OFW translation not page-aligned (phys)!"); 726 if (translations[i].om_va % PAGE_SIZE) 727 panic("OFW translation not page-aligned (virt)!"); 728 729 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 730 pa_base, translations[i].om_va, translations[i].om_len); 731 732 /* Now enter the pages for this mapping */ 733 734 DISABLE_TRANS(msr); 735 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 736 /* If this address is direct-mapped, skip remapping */ 737 if (hw_direct_map && 738 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 739 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 740 == LPTE_M) 741 continue; 742 743 PMAP_LOCK(kernel_pmap); 744 pvo = moea64_pvo_find_va(kernel_pmap, 745 translations[i].om_va + off); 746 PMAP_UNLOCK(kernel_pmap); 747 if (pvo != NULL) 748 continue; 749 750 moea64_kenter(translations[i].om_va + off, 751 pa_base + off); 752 } 753 ENABLE_TRANS(msr); 754 } 755 } 756 757 #ifdef __powerpc64__ 758 static void 759 moea64_probe_large_page(void) 760 { 761 uint16_t pvr = mfpvr() >> 16; 762 763 switch (pvr) { 764 case IBM970: 765 case IBM970FX: 766 case IBM970MP: 767 powerpc_sync(); isync(); 768 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 769 powerpc_sync(); isync(); 770 771 /* FALLTHROUGH */ 772 default: 773 if (moea64_large_page_size == 0) { 774 moea64_large_page_size = 0x1000000; /* 16 MB */ 775 moea64_large_page_shift = 24; 776 } 777 } 778 779 moea64_large_page_mask = moea64_large_page_size - 1; 780 } 781 782 static void 783 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 784 { 785 struct slb *cache; 786 struct slb entry; 787 uint64_t esid, slbe; 788 uint64_t i; 789 790 cache = PCPU_GET(aim.slb); 791 esid = va >> ADDR_SR_SHFT; 792 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 793 794 for (i = 0; i < 64; i++) { 795 if (cache[i].slbe == (slbe | i)) 796 return; 797 } 798 799 entry.slbe = slbe; 800 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 801 if (large) 802 entry.slbv |= SLBV_L; 803 804 slb_insert_kernel(entry.slbe, entry.slbv); 805 } 806 #endif 807 808 static int 809 moea64_kenter_large(vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 810 { 811 struct pvo_entry *pvo; 812 uint64_t pte_lo; 813 int error; 814 815 pte_lo = LPTE_M; 816 pte_lo |= attr; 817 818 pvo = alloc_pvo_entry(bootstrap); 819 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 820 init_pvo_entry(pvo, kernel_pmap, va); 821 822 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 823 VM_PROT_EXECUTE; 824 pvo->pvo_pte.pa = pa | pte_lo; 825 error = moea64_pvo_enter(pvo, NULL, NULL); 826 if (error != 0) 827 panic("Error %d inserting large page\n", error); 828 return (0); 829 } 830 831 static void 832 moea64_setup_direct_map(vm_offset_t kernelstart, 833 vm_offset_t kernelend) 834 { 835 register_t msr; 836 vm_paddr_t pa, pkernelstart, pkernelend; 837 vm_offset_t size, off; 838 uint64_t pte_lo; 839 int i; 840 841 if (moea64_large_page_size == 0) 842 hw_direct_map = 0; 843 844 DISABLE_TRANS(msr); 845 if (hw_direct_map) { 846 PMAP_LOCK(kernel_pmap); 847 for (i = 0; i < pregions_sz; i++) { 848 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 849 pregions[i].mr_size; pa += moea64_large_page_size) { 850 pte_lo = LPTE_M; 851 if (pa & moea64_large_page_mask) { 852 pa &= moea64_large_page_mask; 853 pte_lo |= LPTE_G; 854 } 855 if (pa + moea64_large_page_size > 856 pregions[i].mr_start + pregions[i].mr_size) 857 pte_lo |= LPTE_G; 858 859 moea64_kenter_large(PHYS_TO_DMAP(pa), pa, pte_lo, 1); 860 } 861 } 862 PMAP_UNLOCK(kernel_pmap); 863 } 864 865 /* 866 * Make sure the kernel and BPVO pool stay mapped on systems either 867 * without a direct map or on which the kernel is not already executing 868 * out of the direct-mapped region. 869 */ 870 if (kernelstart < DMAP_BASE_ADDRESS) { 871 /* 872 * For pre-dmap execution, we need to use identity mapping 873 * because we will be operating with the mmu on but in the 874 * wrong address configuration until we __restartkernel(). 875 */ 876 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 877 pa += PAGE_SIZE) 878 moea64_kenter(pa, pa); 879 } else if (!hw_direct_map) { 880 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 881 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 882 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 883 pa += PAGE_SIZE) 884 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 885 } 886 887 if (!hw_direct_map) { 888 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 889 off = (vm_offset_t)(moea64_bpvo_pool); 890 for (pa = off; pa < off + size; pa += PAGE_SIZE) 891 moea64_kenter(pa, pa); 892 893 /* Map exception vectors */ 894 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 895 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 896 } 897 ENABLE_TRANS(msr); 898 899 /* 900 * Allow user to override unmapped_buf_allowed for testing. 901 * XXXKIB Only direct map implementation was tested. 902 */ 903 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 904 &unmapped_buf_allowed)) 905 unmapped_buf_allowed = hw_direct_map; 906 } 907 908 /* Quick sort callout for comparing physical addresses. */ 909 static int 910 pa_cmp(const void *a, const void *b) 911 { 912 const vm_paddr_t *pa = a, *pb = b; 913 914 if (*pa < *pb) 915 return (-1); 916 else if (*pa > *pb) 917 return (1); 918 else 919 return (0); 920 } 921 922 void 923 moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 924 { 925 int i, j; 926 vm_size_t physsz, hwphyssz; 927 vm_paddr_t kernelphysstart, kernelphysend; 928 int rm_pavail; 929 930 /* Level 0 reservations consist of 4096 pages (16MB superpage). */ 931 vm_level_0_order = 12; 932 933 #ifndef __powerpc64__ 934 /* We don't have a direct map since there is no BAT */ 935 hw_direct_map = 0; 936 937 /* Make sure battable is zero, since we have no BAT */ 938 for (i = 0; i < 16; i++) { 939 battable[i].batu = 0; 940 battable[i].batl = 0; 941 } 942 #else 943 /* Install trap handlers for SLBs */ 944 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 945 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 946 __syncicache((void *)EXC_DSE, 0x80); 947 __syncicache((void *)EXC_ISE, 0x80); 948 #endif 949 950 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 951 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 952 953 /* Get physical memory regions from firmware */ 954 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 955 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 956 957 if (PHYS_AVAIL_ENTRIES < regions_sz) 958 panic("moea64_bootstrap: phys_avail too small"); 959 960 phys_avail_count = 0; 961 physsz = 0; 962 hwphyssz = 0; 963 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 964 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 965 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 966 regions[i].mr_start, regions[i].mr_start + 967 regions[i].mr_size, regions[i].mr_size); 968 if (hwphyssz != 0 && 969 (physsz + regions[i].mr_size) >= hwphyssz) { 970 if (physsz < hwphyssz) { 971 phys_avail[j] = regions[i].mr_start; 972 phys_avail[j + 1] = regions[i].mr_start + 973 hwphyssz - physsz; 974 physsz = hwphyssz; 975 phys_avail_count++; 976 dump_avail[j] = phys_avail[j]; 977 dump_avail[j + 1] = phys_avail[j + 1]; 978 } 979 break; 980 } 981 phys_avail[j] = regions[i].mr_start; 982 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 983 phys_avail_count++; 984 physsz += regions[i].mr_size; 985 dump_avail[j] = phys_avail[j]; 986 dump_avail[j + 1] = phys_avail[j + 1]; 987 } 988 989 /* Check for overlap with the kernel and exception vectors */ 990 rm_pavail = 0; 991 for (j = 0; j < 2*phys_avail_count; j+=2) { 992 if (phys_avail[j] < EXC_LAST) 993 phys_avail[j] += EXC_LAST; 994 995 if (phys_avail[j] >= kernelphysstart && 996 phys_avail[j+1] <= kernelphysend) { 997 phys_avail[j] = phys_avail[j+1] = ~0; 998 rm_pavail++; 999 continue; 1000 } 1001 1002 if (kernelphysstart >= phys_avail[j] && 1003 kernelphysstart < phys_avail[j+1]) { 1004 if (kernelphysend < phys_avail[j+1]) { 1005 phys_avail[2*phys_avail_count] = 1006 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 1007 phys_avail[2*phys_avail_count + 1] = 1008 phys_avail[j+1]; 1009 phys_avail_count++; 1010 } 1011 1012 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 1013 } 1014 1015 if (kernelphysend >= phys_avail[j] && 1016 kernelphysend < phys_avail[j+1]) { 1017 if (kernelphysstart > phys_avail[j]) { 1018 phys_avail[2*phys_avail_count] = phys_avail[j]; 1019 phys_avail[2*phys_avail_count + 1] = 1020 kernelphysstart & ~PAGE_MASK; 1021 phys_avail_count++; 1022 } 1023 1024 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 1025 PAGE_SIZE; 1026 } 1027 } 1028 1029 /* Remove physical available regions marked for removal (~0) */ 1030 if (rm_pavail) { 1031 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 1032 pa_cmp); 1033 phys_avail_count -= rm_pavail; 1034 for (i = 2*phys_avail_count; 1035 i < 2*(phys_avail_count + rm_pavail); i+=2) 1036 phys_avail[i] = phys_avail[i+1] = 0; 1037 } 1038 1039 physmem = btoc(physsz); 1040 1041 #ifdef PTEGCOUNT 1042 moea64_pteg_count = PTEGCOUNT; 1043 #else 1044 moea64_pteg_count = 0x1000; 1045 1046 while (moea64_pteg_count < physmem) 1047 moea64_pteg_count <<= 1; 1048 1049 moea64_pteg_count >>= 1; 1050 #endif /* PTEGCOUNT */ 1051 } 1052 1053 void 1054 moea64_mid_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 1055 { 1056 int i; 1057 1058 /* 1059 * Set PTEG mask 1060 */ 1061 moea64_pteg_mask = moea64_pteg_count - 1; 1062 1063 /* 1064 * Initialize SLB table lock and page locks 1065 */ 1066 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 1067 for (i = 0; i < PV_LOCK_COUNT; i++) 1068 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 1069 1070 /* 1071 * Initialise the bootstrap pvo pool. 1072 */ 1073 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 1074 if (moea64_bpvo_pool_size == 0) { 1075 if (!hw_direct_map) 1076 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) / 1077 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR; 1078 else 1079 moea64_bpvo_pool_size = BPVO_POOL_SIZE; 1080 } 1081 1082 if (boothowto & RB_VERBOSE) { 1083 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n", 1084 moea64_bpvo_pool_size, 1085 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576); 1086 } 1087 1088 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 1089 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 1090 moea64_bpvo_pool_index = 0; 1091 1092 /* Place at address usable through the direct map */ 1093 if (hw_direct_map) 1094 moea64_bpvo_pool = (struct pvo_entry *) 1095 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 1096 1097 /* 1098 * Make sure kernel vsid is allocated as well as VSID 0. 1099 */ 1100 #ifndef __powerpc64__ 1101 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 1102 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 1103 moea64_vsid_bitmap[0] |= 1; 1104 #endif 1105 1106 /* 1107 * Initialize the kernel pmap (which is statically allocated). 1108 */ 1109 #ifdef __powerpc64__ 1110 for (i = 0; i < 64; i++) { 1111 pcpup->pc_aim.slb[i].slbv = 0; 1112 pcpup->pc_aim.slb[i].slbe = 0; 1113 } 1114 #else 1115 for (i = 0; i < 16; i++) 1116 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 1117 #endif 1118 1119 kernel_pmap->pmap_phys = kernel_pmap; 1120 CPU_FILL(&kernel_pmap->pm_active); 1121 RB_INIT(&kernel_pmap->pmap_pvo); 1122 1123 PMAP_LOCK_INIT(kernel_pmap); 1124 1125 /* 1126 * Now map in all the other buffers we allocated earlier 1127 */ 1128 1129 moea64_setup_direct_map(kernelstart, kernelend); 1130 } 1131 1132 void 1133 moea64_late_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 1134 { 1135 ihandle_t mmui; 1136 phandle_t chosen; 1137 phandle_t mmu; 1138 ssize_t sz; 1139 int i; 1140 vm_offset_t pa, va; 1141 void *dpcpu; 1142 1143 /* 1144 * Set up the Open Firmware pmap and add its mappings if not in real 1145 * mode. 1146 */ 1147 1148 chosen = OF_finddevice("/chosen"); 1149 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 1150 mmu = OF_instance_to_package(mmui); 1151 if (mmu == -1 || 1152 (sz = OF_getproplen(mmu, "translations")) == -1) 1153 sz = 0; 1154 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1155 panic("moea64_bootstrap: too many ofw translations"); 1156 1157 if (sz > 0) 1158 moea64_add_ofw_mappings(mmu, sz); 1159 } 1160 1161 /* 1162 * Calculate the last available physical address. 1163 */ 1164 Maxmem = 0; 1165 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1166 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 1167 1168 /* 1169 * Initialize MMU. 1170 */ 1171 pmap_cpu_bootstrap(0); 1172 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1173 pmap_bootstrapped++; 1174 1175 /* 1176 * Set the start and end of kva. 1177 */ 1178 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1179 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1180 1181 /* 1182 * Map the entire KVA range into the SLB. We must not fault there. 1183 */ 1184 #ifdef __powerpc64__ 1185 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1186 moea64_bootstrap_slb_prefault(va, 0); 1187 #endif 1188 1189 /* 1190 * Remap any early IO mappings (console framebuffer, etc.) 1191 */ 1192 bs_remap_earlyboot(); 1193 1194 /* 1195 * Figure out how far we can extend virtual_end into segment 16 1196 * without running into existing mappings. Segment 16 is guaranteed 1197 * to contain neither RAM nor devices (at least on Apple hardware), 1198 * but will generally contain some OFW mappings we should not 1199 * step on. 1200 */ 1201 1202 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1203 PMAP_LOCK(kernel_pmap); 1204 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1205 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1206 virtual_end += PAGE_SIZE; 1207 PMAP_UNLOCK(kernel_pmap); 1208 #endif 1209 1210 /* 1211 * Allocate a kernel stack with a guard page for thread0 and map it 1212 * into the kernel page map. 1213 */ 1214 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1215 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1216 virtual_avail = va + kstack_pages * PAGE_SIZE; 1217 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1218 thread0.td_kstack = va; 1219 thread0.td_kstack_pages = kstack_pages; 1220 for (i = 0; i < kstack_pages; i++) { 1221 moea64_kenter(va, pa); 1222 pa += PAGE_SIZE; 1223 va += PAGE_SIZE; 1224 } 1225 1226 /* 1227 * Allocate virtual address space for the message buffer. 1228 */ 1229 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1230 msgbufp = (struct msgbuf *)virtual_avail; 1231 va = virtual_avail; 1232 virtual_avail += round_page(msgbufsize); 1233 while (va < virtual_avail) { 1234 moea64_kenter(va, pa); 1235 pa += PAGE_SIZE; 1236 va += PAGE_SIZE; 1237 } 1238 1239 /* 1240 * Allocate virtual address space for the dynamic percpu area. 1241 */ 1242 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1243 dpcpu = (void *)virtual_avail; 1244 va = virtual_avail; 1245 virtual_avail += DPCPU_SIZE; 1246 while (va < virtual_avail) { 1247 moea64_kenter(va, pa); 1248 pa += PAGE_SIZE; 1249 va += PAGE_SIZE; 1250 } 1251 dpcpu_init(dpcpu, curcpu); 1252 1253 crashdumpmap = (caddr_t)virtual_avail; 1254 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1255 1256 /* 1257 * Allocate some things for page zeroing. We put this directly 1258 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1259 * of the PVO book-keeping or other parts of the VM system 1260 * from even knowing that this hack exists. 1261 */ 1262 1263 if (!hw_direct_map) { 1264 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1265 MTX_DEF); 1266 for (i = 0; i < 2; i++) { 1267 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1268 virtual_end -= PAGE_SIZE; 1269 1270 moea64_kenter(moea64_scratchpage_va[i], 0); 1271 1272 PMAP_LOCK(kernel_pmap); 1273 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1274 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1275 PMAP_UNLOCK(kernel_pmap); 1276 } 1277 } 1278 1279 numa_mem_regions(&numa_pregions, &numapregions_sz); 1280 } 1281 1282 static void 1283 moea64_pmap_init_qpages(void) 1284 { 1285 struct pcpu *pc; 1286 int i; 1287 1288 if (hw_direct_map) 1289 return; 1290 1291 CPU_FOREACH(i) { 1292 pc = pcpu_find(i); 1293 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1294 if (pc->pc_qmap_addr == 0) 1295 panic("pmap_init_qpages: unable to allocate KVA"); 1296 PMAP_LOCK(kernel_pmap); 1297 pc->pc_aim.qmap_pvo = 1298 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1299 PMAP_UNLOCK(kernel_pmap); 1300 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1301 } 1302 } 1303 1304 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1305 1306 /* 1307 * Activate a user pmap. This mostly involves setting some non-CPU 1308 * state. 1309 */ 1310 void 1311 moea64_activate(struct thread *td) 1312 { 1313 pmap_t pm; 1314 1315 pm = &td->td_proc->p_vmspace->vm_pmap; 1316 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1317 1318 #ifdef __powerpc64__ 1319 PCPU_SET(aim.userslb, pm->pm_slb); 1320 __asm __volatile("slbmte %0, %1; isync" :: 1321 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1322 #else 1323 PCPU_SET(curpmap, pm->pmap_phys); 1324 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1325 #endif 1326 } 1327 1328 void 1329 moea64_deactivate(struct thread *td) 1330 { 1331 pmap_t pm; 1332 1333 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1334 1335 pm = &td->td_proc->p_vmspace->vm_pmap; 1336 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1337 #ifdef __powerpc64__ 1338 PCPU_SET(aim.userslb, NULL); 1339 #else 1340 PCPU_SET(curpmap, NULL); 1341 #endif 1342 } 1343 1344 void 1345 moea64_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1346 { 1347 struct pvo_entry key, *pvo; 1348 vm_page_t m; 1349 int64_t refchg; 1350 1351 key.pvo_vaddr = sva; 1352 PMAP_LOCK(pm); 1353 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1354 pvo != NULL && PVO_VADDR(pvo) < eva; 1355 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1356 if (PVO_IS_SP(pvo)) { 1357 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 1358 pvo = moea64_sp_unwire(pvo); 1359 continue; 1360 } else { 1361 CTR1(KTR_PMAP, "%s: demote before unwire", 1362 __func__); 1363 moea64_sp_demote(pvo); 1364 } 1365 } 1366 1367 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1368 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1369 pvo); 1370 pvo->pvo_vaddr &= ~PVO_WIRED; 1371 refchg = moea64_pte_replace(pvo, 0 /* No invalidation */); 1372 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1373 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1374 if (refchg < 0) 1375 refchg = LPTE_CHG; 1376 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1377 1378 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1379 if (refchg & LPTE_CHG) 1380 vm_page_dirty(m); 1381 if (refchg & LPTE_REF) 1382 vm_page_aflag_set(m, PGA_REFERENCED); 1383 } 1384 pm->pm_stats.wired_count--; 1385 } 1386 PMAP_UNLOCK(pm); 1387 } 1388 1389 static int 1390 moea64_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 1391 { 1392 struct pvo_entry *pvo; 1393 vm_paddr_t pa; 1394 vm_page_t m; 1395 int val; 1396 bool managed; 1397 1398 PMAP_LOCK(pmap); 1399 1400 pvo = moea64_pvo_find_va(pmap, addr); 1401 if (pvo != NULL) { 1402 pa = PVO_PADDR(pvo); 1403 m = PHYS_TO_VM_PAGE(pa); 1404 managed = (pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED; 1405 if (PVO_IS_SP(pvo)) 1406 val = MINCORE_INCORE | MINCORE_PSIND(1); 1407 else 1408 val = MINCORE_INCORE; 1409 } else { 1410 PMAP_UNLOCK(pmap); 1411 return (0); 1412 } 1413 1414 PMAP_UNLOCK(pmap); 1415 1416 if (m == NULL) 1417 return (0); 1418 1419 if (managed) { 1420 if (moea64_is_modified(m)) 1421 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 1422 1423 if (moea64_is_referenced(m)) 1424 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 1425 } 1426 1427 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 1428 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 1429 managed) { 1430 *pap = pa; 1431 } 1432 1433 return (val); 1434 } 1435 1436 /* 1437 * This goes through and sets the physical address of our 1438 * special scratch PTE to the PA we want to zero or copy. Because 1439 * of locking issues (this can get called in pvo_enter() by 1440 * the UMA allocator), we can't use most other utility functions here 1441 */ 1442 1443 static __inline 1444 void moea64_set_scratchpage_pa(int which, vm_paddr_t pa) 1445 { 1446 struct pvo_entry *pvo; 1447 1448 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1449 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1450 1451 pvo = moea64_scratchpage_pvo[which]; 1452 PMAP_LOCK(pvo->pvo_pmap); 1453 pvo->pvo_pte.pa = 1454 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1455 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1456 PMAP_UNLOCK(pvo->pvo_pmap); 1457 isync(); 1458 } 1459 1460 void 1461 moea64_copy_page(vm_page_t msrc, vm_page_t mdst) 1462 { 1463 mtx_lock(&moea64_scratchpage_mtx); 1464 1465 moea64_set_scratchpage_pa(0, VM_PAGE_TO_PHYS(msrc)); 1466 moea64_set_scratchpage_pa(1, VM_PAGE_TO_PHYS(mdst)); 1467 1468 bcopy((void *)moea64_scratchpage_va[0], 1469 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1470 1471 mtx_unlock(&moea64_scratchpage_mtx); 1472 } 1473 1474 void 1475 moea64_copy_page_dmap(vm_page_t msrc, vm_page_t mdst) 1476 { 1477 vm_offset_t dst; 1478 vm_offset_t src; 1479 1480 dst = VM_PAGE_TO_PHYS(mdst); 1481 src = VM_PAGE_TO_PHYS(msrc); 1482 1483 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1484 PAGE_SIZE); 1485 } 1486 1487 inline void 1488 moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 1489 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1490 { 1491 void *a_cp, *b_cp; 1492 vm_offset_t a_pg_offset, b_pg_offset; 1493 int cnt; 1494 1495 while (xfersize > 0) { 1496 a_pg_offset = a_offset & PAGE_MASK; 1497 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1498 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1499 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1500 a_pg_offset; 1501 b_pg_offset = b_offset & PAGE_MASK; 1502 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1503 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1504 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1505 b_pg_offset; 1506 bcopy(a_cp, b_cp, cnt); 1507 a_offset += cnt; 1508 b_offset += cnt; 1509 xfersize -= cnt; 1510 } 1511 } 1512 1513 void 1514 moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1515 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1516 { 1517 void *a_cp, *b_cp; 1518 vm_offset_t a_pg_offset, b_pg_offset; 1519 int cnt; 1520 1521 mtx_lock(&moea64_scratchpage_mtx); 1522 while (xfersize > 0) { 1523 a_pg_offset = a_offset & PAGE_MASK; 1524 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1525 moea64_set_scratchpage_pa(0, 1526 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1527 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1528 b_pg_offset = b_offset & PAGE_MASK; 1529 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1530 moea64_set_scratchpage_pa(1, 1531 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1532 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1533 bcopy(a_cp, b_cp, cnt); 1534 a_offset += cnt; 1535 b_offset += cnt; 1536 xfersize -= cnt; 1537 } 1538 mtx_unlock(&moea64_scratchpage_mtx); 1539 } 1540 1541 void 1542 moea64_zero_page_area(vm_page_t m, int off, int size) 1543 { 1544 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1545 1546 if (size + off > PAGE_SIZE) 1547 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1548 1549 if (hw_direct_map) { 1550 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1551 } else { 1552 mtx_lock(&moea64_scratchpage_mtx); 1553 moea64_set_scratchpage_pa(0, pa); 1554 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1555 mtx_unlock(&moea64_scratchpage_mtx); 1556 } 1557 } 1558 1559 /* 1560 * Zero a page of physical memory by temporarily mapping it 1561 */ 1562 void 1563 moea64_zero_page(vm_page_t m) 1564 { 1565 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1566 vm_offset_t va, off; 1567 1568 mtx_lock(&moea64_scratchpage_mtx); 1569 1570 moea64_set_scratchpage_pa(0, pa); 1571 va = moea64_scratchpage_va[0]; 1572 1573 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1574 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1575 1576 mtx_unlock(&moea64_scratchpage_mtx); 1577 } 1578 1579 void 1580 moea64_zero_page_dmap(vm_page_t m) 1581 { 1582 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1583 vm_offset_t va, off; 1584 1585 va = PHYS_TO_DMAP(pa); 1586 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1587 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1588 } 1589 1590 vm_offset_t 1591 moea64_quick_enter_page(vm_page_t m) 1592 { 1593 struct pvo_entry *pvo; 1594 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1595 1596 /* 1597 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1598 * a critical section and access the PCPU data like on i386. 1599 * Instead, pin the thread and grab the PCPU lock to prevent 1600 * a preempting thread from using the same PCPU data. 1601 */ 1602 sched_pin(); 1603 1604 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1605 pvo = PCPU_GET(aim.qmap_pvo); 1606 1607 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1608 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1609 (uint64_t)pa; 1610 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1611 isync(); 1612 1613 return (PCPU_GET(qmap_addr)); 1614 } 1615 1616 vm_offset_t 1617 moea64_quick_enter_page_dmap(vm_page_t m) 1618 { 1619 1620 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 1621 } 1622 1623 void 1624 moea64_quick_remove_page(vm_offset_t addr) 1625 { 1626 1627 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1628 KASSERT(PCPU_GET(qmap_addr) == addr, 1629 ("moea64_quick_remove_page: invalid address")); 1630 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1631 sched_unpin(); 1632 } 1633 1634 boolean_t 1635 moea64_page_is_mapped(vm_page_t m) 1636 { 1637 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1638 } 1639 1640 /* 1641 * Map the given physical page at the specified virtual address in the 1642 * target pmap with the protection requested. If specified the page 1643 * will be wired down. 1644 */ 1645 1646 int 1647 moea64_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1648 vm_prot_t prot, u_int flags, int8_t psind) 1649 { 1650 struct pvo_entry *pvo, *oldpvo, *tpvo; 1651 struct pvo_head *pvo_head; 1652 uint64_t pte_lo; 1653 int error; 1654 vm_paddr_t pa; 1655 1656 if ((m->oflags & VPO_UNMANAGED) == 0) { 1657 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1658 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1659 else 1660 VM_OBJECT_ASSERT_LOCKED(m->object); 1661 } 1662 1663 if (psind > 0) 1664 return (moea64_sp_enter(pmap, va, m, prot, flags, psind)); 1665 1666 pvo = alloc_pvo_entry(0); 1667 if (pvo == NULL) 1668 return (KERN_RESOURCE_SHORTAGE); 1669 pvo->pvo_pmap = NULL; /* to be filled in later */ 1670 pvo->pvo_pte.prot = prot; 1671 1672 pa = VM_PAGE_TO_PHYS(m); 1673 pte_lo = moea64_calc_wimg(pa, pmap_page_get_memattr(m)); 1674 pvo->pvo_pte.pa = pa | pte_lo; 1675 1676 if ((flags & PMAP_ENTER_WIRED) != 0) 1677 pvo->pvo_vaddr |= PVO_WIRED; 1678 1679 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1680 pvo_head = NULL; 1681 } else { 1682 pvo_head = &m->md.mdpg_pvoh; 1683 pvo->pvo_vaddr |= PVO_MANAGED; 1684 } 1685 1686 PV_LOCK(pa); 1687 PMAP_LOCK(pmap); 1688 if (pvo->pvo_pmap == NULL) 1689 init_pvo_entry(pvo, pmap, va); 1690 1691 if (moea64_ps_enabled(pmap) && 1692 (tpvo = moea64_pvo_find_va(pmap, va & ~HPT_SP_MASK)) != NULL && 1693 PVO_IS_SP(tpvo)) { 1694 /* Demote SP before entering a regular page */ 1695 CTR2(KTR_PMAP, "%s: demote before enter: va=%#jx", 1696 __func__, (uintmax_t)va); 1697 moea64_sp_demote_aligned(tpvo); 1698 } 1699 1700 if (prot & VM_PROT_WRITE) 1701 if (pmap_bootstrapped && 1702 (m->oflags & VPO_UNMANAGED) == 0) 1703 vm_page_aflag_set(m, PGA_WRITEABLE); 1704 1705 error = moea64_pvo_enter(pvo, pvo_head, &oldpvo); 1706 if (error == EEXIST) { 1707 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1708 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1709 oldpvo->pvo_pte.prot == prot) { 1710 /* Identical mapping already exists */ 1711 error = 0; 1712 1713 /* If not in page table, reinsert it */ 1714 if (moea64_pte_synch(oldpvo) < 0) { 1715 STAT_MOEA64(moea64_pte_overflow--); 1716 moea64_pte_insert(oldpvo); 1717 } 1718 1719 /* Then just clean up and go home */ 1720 PMAP_UNLOCK(pmap); 1721 PV_UNLOCK(pa); 1722 free_pvo_entry(pvo); 1723 pvo = NULL; 1724 goto out; 1725 } else { 1726 /* Otherwise, need to kill it first */ 1727 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1728 "mapping does not match new mapping")); 1729 moea64_pvo_remove_from_pmap(oldpvo); 1730 moea64_pvo_enter(pvo, pvo_head, NULL); 1731 } 1732 } 1733 PMAP_UNLOCK(pmap); 1734 PV_UNLOCK(pa); 1735 1736 /* Free any dead pages */ 1737 if (error == EEXIST) { 1738 moea64_pvo_remove_from_page(oldpvo); 1739 free_pvo_entry(oldpvo); 1740 } 1741 1742 out: 1743 /* 1744 * Flush the page from the instruction cache if this page is 1745 * mapped executable and cacheable. 1746 */ 1747 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1748 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1749 vm_page_aflag_set(m, PGA_EXECUTABLE); 1750 moea64_syncicache(pmap, va, pa, PAGE_SIZE); 1751 } 1752 1753 #if VM_NRESERVLEVEL > 0 1754 /* 1755 * Try to promote pages. 1756 * 1757 * If the VA of the entered page is not aligned with its PA, 1758 * don't try page promotion as it is not possible. 1759 * This reduces the number of promotion failures dramatically. 1760 */ 1761 if (moea64_ps_enabled(pmap) && pmap != kernel_pmap && pvo != NULL && 1762 (pvo->pvo_vaddr & PVO_MANAGED) != 0 && 1763 (va & HPT_SP_MASK) == (pa & HPT_SP_MASK) && 1764 (m->flags & PG_FICTITIOUS) == 0 && 1765 vm_reserv_level_iffullpop(m) == 0) 1766 moea64_sp_promote(pmap, va, m); 1767 #endif 1768 1769 return (KERN_SUCCESS); 1770 } 1771 1772 static void 1773 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1774 vm_size_t sz) 1775 { 1776 1777 /* 1778 * This is much trickier than on older systems because 1779 * we can't sync the icache on physical addresses directly 1780 * without a direct map. Instead we check a couple of cases 1781 * where the memory is already mapped in and, failing that, 1782 * use the same trick we use for page zeroing to create 1783 * a temporary mapping for this physical address. 1784 */ 1785 1786 if (!pmap_bootstrapped) { 1787 /* 1788 * If PMAP is not bootstrapped, we are likely to be 1789 * in real mode. 1790 */ 1791 __syncicache((void *)(uintptr_t)pa, sz); 1792 } else if (pmap == kernel_pmap) { 1793 __syncicache((void *)va, sz); 1794 } else if (hw_direct_map) { 1795 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1796 } else { 1797 /* Use the scratch page to set up a temp mapping */ 1798 1799 mtx_lock(&moea64_scratchpage_mtx); 1800 1801 moea64_set_scratchpage_pa(1, pa & ~ADDR_POFF); 1802 __syncicache((void *)(moea64_scratchpage_va[1] + 1803 (va & ADDR_POFF)), sz); 1804 1805 mtx_unlock(&moea64_scratchpage_mtx); 1806 } 1807 } 1808 1809 /* 1810 * Maps a sequence of resident pages belonging to the same object. 1811 * The sequence begins with the given page m_start. This page is 1812 * mapped at the given virtual address start. Each subsequent page is 1813 * mapped at a virtual address that is offset from start by the same 1814 * amount as the page is offset from m_start within the object. The 1815 * last page in the sequence is the page with the largest offset from 1816 * m_start that can be mapped at a virtual address less than the given 1817 * virtual address end. Not every virtual page between start and end 1818 * is mapped; only those for which a resident page exists with the 1819 * corresponding offset from m_start are mapped. 1820 */ 1821 void 1822 moea64_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1823 vm_page_t m_start, vm_prot_t prot) 1824 { 1825 vm_page_t m; 1826 vm_pindex_t diff, psize; 1827 vm_offset_t va; 1828 int8_t psind; 1829 1830 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1831 1832 psize = atop(end - start); 1833 m = m_start; 1834 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1835 va = start + ptoa(diff); 1836 if ((va & HPT_SP_MASK) == 0 && va + HPT_SP_SIZE <= end && 1837 m->psind == 1 && moea64_ps_enabled(pm)) 1838 psind = 1; 1839 else 1840 psind = 0; 1841 moea64_enter(pm, va, m, prot & 1842 (VM_PROT_READ | VM_PROT_EXECUTE), 1843 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, psind); 1844 if (psind == 1) 1845 m = &m[HPT_SP_SIZE / PAGE_SIZE - 1]; 1846 m = TAILQ_NEXT(m, listq); 1847 } 1848 } 1849 1850 void 1851 moea64_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1852 vm_prot_t prot) 1853 { 1854 1855 moea64_enter(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1856 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1857 } 1858 1859 vm_paddr_t 1860 moea64_extract(pmap_t pm, vm_offset_t va) 1861 { 1862 struct pvo_entry *pvo; 1863 vm_paddr_t pa; 1864 1865 PMAP_LOCK(pm); 1866 pvo = moea64_pvo_find_va(pm, va); 1867 if (pvo == NULL) 1868 pa = 0; 1869 else 1870 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 1871 PMAP_UNLOCK(pm); 1872 1873 return (pa); 1874 } 1875 1876 /* 1877 * Atomically extract and hold the physical page with the given 1878 * pmap and virtual address pair if that mapping permits the given 1879 * protection. 1880 */ 1881 vm_page_t 1882 moea64_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1883 { 1884 struct pvo_entry *pvo; 1885 vm_page_t m; 1886 1887 m = NULL; 1888 PMAP_LOCK(pmap); 1889 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1890 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1891 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1892 if (!vm_page_wire_mapped(m)) 1893 m = NULL; 1894 } 1895 PMAP_UNLOCK(pmap); 1896 return (m); 1897 } 1898 1899 static void * 1900 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1901 uint8_t *flags, int wait) 1902 { 1903 struct pvo_entry *pvo; 1904 vm_offset_t va; 1905 vm_page_t m; 1906 int needed_lock; 1907 1908 /* 1909 * This entire routine is a horrible hack to avoid bothering kmem 1910 * for new KVA addresses. Because this can get called from inside 1911 * kmem allocation routines, calling kmem for a new address here 1912 * can lead to multiply locking non-recursive mutexes. 1913 */ 1914 1915 *flags = UMA_SLAB_PRIV; 1916 needed_lock = !PMAP_LOCKED(kernel_pmap); 1917 1918 m = vm_page_alloc_domain(NULL, 0, domain, 1919 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1920 if (m == NULL) 1921 return (NULL); 1922 1923 va = VM_PAGE_TO_PHYS(m); 1924 1925 pvo = alloc_pvo_entry(1 /* bootstrap */); 1926 1927 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1928 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1929 1930 if (needed_lock) 1931 PMAP_LOCK(kernel_pmap); 1932 1933 init_pvo_entry(pvo, kernel_pmap, va); 1934 pvo->pvo_vaddr |= PVO_WIRED; 1935 1936 moea64_pvo_enter(pvo, NULL, NULL); 1937 1938 if (needed_lock) 1939 PMAP_UNLOCK(kernel_pmap); 1940 1941 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1942 bzero((void *)va, PAGE_SIZE); 1943 1944 return (void *)va; 1945 } 1946 1947 extern int elf32_nxstack; 1948 1949 void 1950 moea64_init() 1951 { 1952 1953 CTR0(KTR_PMAP, "moea64_init"); 1954 1955 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1956 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1957 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1958 1959 /* 1960 * Are large page mappings enabled? 1961 * 1962 * While HPT superpages are not better tested, leave it disabled by 1963 * default. 1964 */ 1965 superpages_enabled = 0; 1966 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 1967 if (superpages_enabled) { 1968 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1969 ("moea64_init: can't assign to pagesizes[1]")); 1970 1971 if (moea64_large_page_size == 0) { 1972 printf("mmu_oea64: HW does not support large pages. " 1973 "Disabling superpages...\n"); 1974 superpages_enabled = 0; 1975 } else if (!moea64_has_lp_4k_16m) { 1976 printf("mmu_oea64: " 1977 "HW does not support mixed 4KB/16MB page sizes. " 1978 "Disabling superpages...\n"); 1979 superpages_enabled = 0; 1980 } else 1981 pagesizes[1] = HPT_SP_SIZE; 1982 } 1983 1984 if (!hw_direct_map) { 1985 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1986 } 1987 1988 #ifdef COMPAT_FREEBSD32 1989 elf32_nxstack = 1; 1990 #endif 1991 1992 moea64_initialized = TRUE; 1993 } 1994 1995 boolean_t 1996 moea64_is_referenced(vm_page_t m) 1997 { 1998 1999 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2000 ("moea64_is_referenced: page %p is not managed", m)); 2001 2002 return (moea64_query_bit(m, LPTE_REF)); 2003 } 2004 2005 boolean_t 2006 moea64_is_modified(vm_page_t m) 2007 { 2008 2009 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2010 ("moea64_is_modified: page %p is not managed", m)); 2011 2012 /* 2013 * If the page is not busied then this check is racy. 2014 */ 2015 if (!pmap_page_is_write_mapped(m)) 2016 return (FALSE); 2017 2018 return (moea64_query_bit(m, LPTE_CHG)); 2019 } 2020 2021 boolean_t 2022 moea64_is_prefaultable(pmap_t pmap, vm_offset_t va) 2023 { 2024 struct pvo_entry *pvo; 2025 boolean_t rv = TRUE; 2026 2027 PMAP_LOCK(pmap); 2028 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 2029 if (pvo != NULL) 2030 rv = FALSE; 2031 PMAP_UNLOCK(pmap); 2032 return (rv); 2033 } 2034 2035 void 2036 moea64_clear_modify(vm_page_t m) 2037 { 2038 2039 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2040 ("moea64_clear_modify: page %p is not managed", m)); 2041 vm_page_assert_busied(m); 2042 2043 if (!pmap_page_is_write_mapped(m)) 2044 return; 2045 moea64_clear_bit(m, LPTE_CHG); 2046 } 2047 2048 /* 2049 * Clear the write and modified bits in each of the given page's mappings. 2050 */ 2051 void 2052 moea64_remove_write(vm_page_t m) 2053 { 2054 struct pvo_entry *pvo; 2055 int64_t refchg, ret; 2056 pmap_t pmap; 2057 2058 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2059 ("moea64_remove_write: page %p is not managed", m)); 2060 vm_page_assert_busied(m); 2061 2062 if (!pmap_page_is_write_mapped(m)) 2063 return; 2064 2065 powerpc_sync(); 2066 PV_PAGE_LOCK(m); 2067 refchg = 0; 2068 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2069 pmap = pvo->pvo_pmap; 2070 PMAP_LOCK(pmap); 2071 if (!(pvo->pvo_vaddr & PVO_DEAD) && 2072 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2073 if (PVO_IS_SP(pvo)) { 2074 CTR1(KTR_PMAP, "%s: demote before remwr", 2075 __func__); 2076 moea64_sp_demote(pvo); 2077 } 2078 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 2079 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2080 if (ret < 0) 2081 ret = LPTE_CHG; 2082 refchg |= ret; 2083 if (pvo->pvo_pmap == kernel_pmap) 2084 isync(); 2085 } 2086 PMAP_UNLOCK(pmap); 2087 } 2088 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 2089 vm_page_dirty(m); 2090 vm_page_aflag_clear(m, PGA_WRITEABLE); 2091 PV_PAGE_UNLOCK(m); 2092 } 2093 2094 /* 2095 * moea64_ts_referenced: 2096 * 2097 * Return a count of reference bits for a page, clearing those bits. 2098 * It is not necessary for every reference bit to be cleared, but it 2099 * is necessary that 0 only be returned when there are truly no 2100 * reference bits set. 2101 * 2102 * XXX: The exact number of bits to check and clear is a matter that 2103 * should be tested and standardized at some point in the future for 2104 * optimal aging of shared pages. 2105 */ 2106 int 2107 moea64_ts_referenced(vm_page_t m) 2108 { 2109 2110 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2111 ("moea64_ts_referenced: page %p is not managed", m)); 2112 return (moea64_clear_bit(m, LPTE_REF)); 2113 } 2114 2115 /* 2116 * Modify the WIMG settings of all mappings for a page. 2117 */ 2118 void 2119 moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma) 2120 { 2121 struct pvo_entry *pvo; 2122 int64_t refchg; 2123 pmap_t pmap; 2124 uint64_t lo; 2125 2126 CTR3(KTR_PMAP, "%s: pa=%#jx, ma=%#x", 2127 __func__, (uintmax_t)VM_PAGE_TO_PHYS(m), ma); 2128 2129 if ((m->oflags & VPO_UNMANAGED) != 0) { 2130 m->md.mdpg_cache_attrs = ma; 2131 return; 2132 } 2133 2134 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 2135 2136 PV_PAGE_LOCK(m); 2137 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2138 pmap = pvo->pvo_pmap; 2139 PMAP_LOCK(pmap); 2140 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 2141 if (PVO_IS_SP(pvo)) { 2142 CTR1(KTR_PMAP, 2143 "%s: demote before set_memattr", __func__); 2144 moea64_sp_demote(pvo); 2145 } 2146 pvo->pvo_pte.pa &= ~LPTE_WIMG; 2147 pvo->pvo_pte.pa |= lo; 2148 refchg = moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 2149 if (refchg < 0) 2150 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 2151 LPTE_CHG : 0; 2152 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2153 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2154 refchg |= 2155 atomic_readandclear_32(&m->md.mdpg_attrs); 2156 if (refchg & LPTE_CHG) 2157 vm_page_dirty(m); 2158 if (refchg & LPTE_REF) 2159 vm_page_aflag_set(m, PGA_REFERENCED); 2160 } 2161 if (pvo->pvo_pmap == kernel_pmap) 2162 isync(); 2163 } 2164 PMAP_UNLOCK(pmap); 2165 } 2166 m->md.mdpg_cache_attrs = ma; 2167 PV_PAGE_UNLOCK(m); 2168 } 2169 2170 /* 2171 * Map a wired page into kernel virtual address space. 2172 */ 2173 void 2174 moea64_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 2175 { 2176 int error; 2177 struct pvo_entry *pvo, *oldpvo; 2178 2179 do { 2180 pvo = alloc_pvo_entry(0); 2181 if (pvo == NULL) 2182 vm_wait(NULL); 2183 } while (pvo == NULL); 2184 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 2185 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 2186 pvo->pvo_vaddr |= PVO_WIRED; 2187 2188 PMAP_LOCK(kernel_pmap); 2189 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 2190 if (oldpvo != NULL) 2191 moea64_pvo_remove_from_pmap(oldpvo); 2192 init_pvo_entry(pvo, kernel_pmap, va); 2193 error = moea64_pvo_enter(pvo, NULL, NULL); 2194 PMAP_UNLOCK(kernel_pmap); 2195 2196 /* Free any dead pages */ 2197 if (oldpvo != NULL) { 2198 moea64_pvo_remove_from_page(oldpvo); 2199 free_pvo_entry(oldpvo); 2200 } 2201 2202 if (error != 0) 2203 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 2204 (uintmax_t)pa, error); 2205 } 2206 2207 void 2208 moea64_kenter(vm_offset_t va, vm_paddr_t pa) 2209 { 2210 2211 moea64_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 2212 } 2213 2214 /* 2215 * Extract the physical page address associated with the given kernel virtual 2216 * address. 2217 */ 2218 vm_paddr_t 2219 moea64_kextract(vm_offset_t va) 2220 { 2221 struct pvo_entry *pvo; 2222 vm_paddr_t pa; 2223 2224 /* 2225 * Shortcut the direct-mapped case when applicable. We never put 2226 * anything but 1:1 (or 62-bit aliased) mappings below 2227 * VM_MIN_KERNEL_ADDRESS. 2228 */ 2229 if (va < VM_MIN_KERNEL_ADDRESS) 2230 return (va & ~DMAP_BASE_ADDRESS); 2231 2232 PMAP_LOCK(kernel_pmap); 2233 pvo = moea64_pvo_find_va(kernel_pmap, va); 2234 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 2235 va)); 2236 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 2237 PMAP_UNLOCK(kernel_pmap); 2238 return (pa); 2239 } 2240 2241 /* 2242 * Remove a wired page from kernel virtual address space. 2243 */ 2244 void 2245 moea64_kremove(vm_offset_t va) 2246 { 2247 moea64_remove(kernel_pmap, va, va + PAGE_SIZE); 2248 } 2249 2250 /* 2251 * Provide a kernel pointer corresponding to a given userland pointer. 2252 * The returned pointer is valid until the next time this function is 2253 * called in this thread. This is used internally in copyin/copyout. 2254 */ 2255 static int 2256 moea64_map_user_ptr(pmap_t pm, volatile const void *uaddr, 2257 void **kaddr, size_t ulen, size_t *klen) 2258 { 2259 size_t l; 2260 #ifdef __powerpc64__ 2261 struct slb *slb; 2262 #endif 2263 register_t slbv; 2264 2265 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 2266 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 2267 if (l > ulen) 2268 l = ulen; 2269 if (klen) 2270 *klen = l; 2271 else if (l != ulen) 2272 return (EFAULT); 2273 2274 #ifdef __powerpc64__ 2275 /* Try lockless look-up first */ 2276 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 2277 2278 if (slb == NULL) { 2279 /* If it isn't there, we need to pre-fault the VSID */ 2280 PMAP_LOCK(pm); 2281 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 2282 PMAP_UNLOCK(pm); 2283 } else { 2284 slbv = slb->slbv; 2285 } 2286 2287 /* Mark segment no-execute */ 2288 slbv |= SLBV_N; 2289 #else 2290 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 2291 2292 /* Mark segment no-execute */ 2293 slbv |= SR_N; 2294 #endif 2295 2296 /* If we have already set this VSID, we can just return */ 2297 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 2298 return (0); 2299 2300 __asm __volatile("isync"); 2301 curthread->td_pcb->pcb_cpu.aim.usr_segm = 2302 (uintptr_t)uaddr >> ADDR_SR_SHFT; 2303 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 2304 #ifdef __powerpc64__ 2305 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2306 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2307 #else 2308 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2309 #endif 2310 2311 return (0); 2312 } 2313 2314 /* 2315 * Figure out where a given kernel pointer (usually in a fault) points 2316 * to from the VM's perspective, potentially remapping into userland's 2317 * address space. 2318 */ 2319 static int 2320 moea64_decode_kernel_ptr(vm_offset_t addr, int *is_user, 2321 vm_offset_t *decoded_addr) 2322 { 2323 vm_offset_t user_sr; 2324 2325 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2326 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2327 addr &= ADDR_PIDX | ADDR_POFF; 2328 addr |= user_sr << ADDR_SR_SHFT; 2329 *decoded_addr = addr; 2330 *is_user = 1; 2331 } else { 2332 *decoded_addr = addr; 2333 *is_user = 0; 2334 } 2335 2336 return (0); 2337 } 2338 2339 /* 2340 * Map a range of physical addresses into kernel virtual address space. 2341 * 2342 * The value passed in *virt is a suggested virtual address for the mapping. 2343 * Architectures which can support a direct-mapped physical to virtual region 2344 * can return the appropriate address within that region, leaving '*virt' 2345 * unchanged. Other architectures should map the pages starting at '*virt' and 2346 * update '*virt' with the first usable address after the mapped region. 2347 */ 2348 vm_offset_t 2349 moea64_map(vm_offset_t *virt, vm_paddr_t pa_start, 2350 vm_paddr_t pa_end, int prot) 2351 { 2352 vm_offset_t sva, va; 2353 2354 if (hw_direct_map) { 2355 /* 2356 * Check if every page in the region is covered by the direct 2357 * map. The direct map covers all of physical memory. Use 2358 * moea64_calc_wimg() as a shortcut to see if the page is in 2359 * physical memory as a way to see if the direct map covers it. 2360 */ 2361 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2362 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2363 break; 2364 if (va == pa_end) 2365 return (PHYS_TO_DMAP(pa_start)); 2366 } 2367 sva = *virt; 2368 va = sva; 2369 /* XXX respect prot argument */ 2370 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2371 moea64_kenter(va, pa_start); 2372 *virt = va; 2373 2374 return (sva); 2375 } 2376 2377 /* 2378 * Returns true if the pmap's pv is one of the first 2379 * 16 pvs linked to from this page. This count may 2380 * be changed upwards or downwards in the future; it 2381 * is only necessary that true be returned for a small 2382 * subset of pmaps for proper page aging. 2383 */ 2384 boolean_t 2385 moea64_page_exists_quick(pmap_t pmap, vm_page_t m) 2386 { 2387 int loops; 2388 struct pvo_entry *pvo; 2389 boolean_t rv; 2390 2391 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2392 ("moea64_page_exists_quick: page %p is not managed", m)); 2393 loops = 0; 2394 rv = FALSE; 2395 PV_PAGE_LOCK(m); 2396 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2397 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2398 rv = TRUE; 2399 break; 2400 } 2401 if (++loops >= 16) 2402 break; 2403 } 2404 PV_PAGE_UNLOCK(m); 2405 return (rv); 2406 } 2407 2408 void 2409 moea64_page_init(vm_page_t m) 2410 { 2411 2412 m->md.mdpg_attrs = 0; 2413 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2414 LIST_INIT(&m->md.mdpg_pvoh); 2415 } 2416 2417 /* 2418 * Return the number of managed mappings to the given physical page 2419 * that are wired. 2420 */ 2421 int 2422 moea64_page_wired_mappings(vm_page_t m) 2423 { 2424 struct pvo_entry *pvo; 2425 int count; 2426 2427 count = 0; 2428 if ((m->oflags & VPO_UNMANAGED) != 0) 2429 return (count); 2430 PV_PAGE_LOCK(m); 2431 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2432 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2433 count++; 2434 PV_PAGE_UNLOCK(m); 2435 return (count); 2436 } 2437 2438 static uintptr_t moea64_vsidcontext; 2439 2440 uintptr_t 2441 moea64_get_unique_vsid(void) { 2442 u_int entropy; 2443 register_t hash; 2444 uint32_t mask; 2445 int i; 2446 2447 entropy = 0; 2448 __asm __volatile("mftb %0" : "=r"(entropy)); 2449 2450 mtx_lock(&moea64_slb_mutex); 2451 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2452 u_int n; 2453 2454 /* 2455 * Create a new value by mutiplying by a prime and adding in 2456 * entropy from the timebase register. This is to make the 2457 * VSID more random so that the PT hash function collides 2458 * less often. (Note that the prime casues gcc to do shifts 2459 * instead of a multiply.) 2460 */ 2461 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2462 hash = moea64_vsidcontext & (NVSIDS - 1); 2463 if (hash == 0) /* 0 is special, avoid it */ 2464 continue; 2465 n = hash >> 5; 2466 mask = 1 << (hash & (VSID_NBPW - 1)); 2467 hash = (moea64_vsidcontext & VSID_HASHMASK); 2468 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2469 /* anything free in this bucket? */ 2470 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2471 entropy = (moea64_vsidcontext >> 20); 2472 continue; 2473 } 2474 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2475 mask = 1 << i; 2476 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2477 hash |= i; 2478 } 2479 if (hash == VSID_VRMA) /* also special, avoid this too */ 2480 continue; 2481 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2482 ("Allocating in-use VSID %#zx\n", hash)); 2483 moea64_vsid_bitmap[n] |= mask; 2484 mtx_unlock(&moea64_slb_mutex); 2485 return (hash); 2486 } 2487 2488 mtx_unlock(&moea64_slb_mutex); 2489 panic("%s: out of segments",__func__); 2490 } 2491 2492 #ifdef __powerpc64__ 2493 int 2494 moea64_pinit(pmap_t pmap) 2495 { 2496 2497 RB_INIT(&pmap->pmap_pvo); 2498 2499 pmap->pm_slb_tree_root = slb_alloc_tree(); 2500 pmap->pm_slb = slb_alloc_user_cache(); 2501 pmap->pm_slb_len = 0; 2502 2503 return (1); 2504 } 2505 #else 2506 int 2507 moea64_pinit(pmap_t pmap) 2508 { 2509 int i; 2510 uint32_t hash; 2511 2512 RB_INIT(&pmap->pmap_pvo); 2513 2514 if (pmap_bootstrapped) 2515 pmap->pmap_phys = (pmap_t)moea64_kextract((vm_offset_t)pmap); 2516 else 2517 pmap->pmap_phys = pmap; 2518 2519 /* 2520 * Allocate some segment registers for this pmap. 2521 */ 2522 hash = moea64_get_unique_vsid(); 2523 2524 for (i = 0; i < 16; i++) 2525 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2526 2527 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2528 2529 return (1); 2530 } 2531 #endif 2532 2533 /* 2534 * Initialize the pmap associated with process 0. 2535 */ 2536 void 2537 moea64_pinit0(pmap_t pm) 2538 { 2539 2540 PMAP_LOCK_INIT(pm); 2541 moea64_pinit(pm); 2542 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2543 } 2544 2545 /* 2546 * Set the physical protection on the specified range of this map as requested. 2547 */ 2548 static void 2549 moea64_pvo_protect( pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2550 { 2551 struct vm_page *pg; 2552 vm_prot_t oldprot; 2553 int32_t refchg; 2554 2555 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2556 2557 /* 2558 * Change the protection of the page. 2559 */ 2560 oldprot = pvo->pvo_pte.prot; 2561 pvo->pvo_pte.prot = prot; 2562 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2563 2564 /* 2565 * If the PVO is in the page table, update mapping 2566 */ 2567 refchg = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2568 if (refchg < 0) 2569 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2570 2571 if (pm != kernel_pmap && pg != NULL && 2572 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2573 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2574 if ((pg->oflags & VPO_UNMANAGED) == 0) 2575 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2576 moea64_syncicache(pm, PVO_VADDR(pvo), 2577 PVO_PADDR(pvo), PAGE_SIZE); 2578 } 2579 2580 /* 2581 * Update vm about the REF/CHG bits if the page is managed and we have 2582 * removed write access. 2583 */ 2584 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2585 (oldprot & VM_PROT_WRITE)) { 2586 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2587 if (refchg & LPTE_CHG) 2588 vm_page_dirty(pg); 2589 if (refchg & LPTE_REF) 2590 vm_page_aflag_set(pg, PGA_REFERENCED); 2591 } 2592 } 2593 2594 void 2595 moea64_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2596 vm_prot_t prot) 2597 { 2598 struct pvo_entry *pvo, key; 2599 2600 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2601 sva, eva, prot); 2602 2603 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2604 ("moea64_protect: non current pmap")); 2605 2606 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2607 moea64_remove(pm, sva, eva); 2608 return; 2609 } 2610 2611 PMAP_LOCK(pm); 2612 key.pvo_vaddr = sva; 2613 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2614 pvo != NULL && PVO_VADDR(pvo) < eva; 2615 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 2616 if (PVO_IS_SP(pvo)) { 2617 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 2618 pvo = moea64_sp_protect(pvo, prot); 2619 continue; 2620 } else { 2621 CTR1(KTR_PMAP, "%s: demote before protect", 2622 __func__); 2623 moea64_sp_demote(pvo); 2624 } 2625 } 2626 moea64_pvo_protect(pm, pvo, prot); 2627 } 2628 PMAP_UNLOCK(pm); 2629 } 2630 2631 /* 2632 * Map a list of wired pages into kernel virtual address space. This is 2633 * intended for temporary mappings which do not need page modification or 2634 * references recorded. Existing mappings in the region are overwritten. 2635 */ 2636 void 2637 moea64_qenter(vm_offset_t va, vm_page_t *m, int count) 2638 { 2639 while (count-- > 0) { 2640 moea64_kenter(va, VM_PAGE_TO_PHYS(*m)); 2641 va += PAGE_SIZE; 2642 m++; 2643 } 2644 } 2645 2646 /* 2647 * Remove page mappings from kernel virtual address space. Intended for 2648 * temporary mappings entered by moea64_qenter. 2649 */ 2650 void 2651 moea64_qremove(vm_offset_t va, int count) 2652 { 2653 while (count-- > 0) { 2654 moea64_kremove(va); 2655 va += PAGE_SIZE; 2656 } 2657 } 2658 2659 void 2660 moea64_release_vsid(uint64_t vsid) 2661 { 2662 int idx, mask; 2663 2664 mtx_lock(&moea64_slb_mutex); 2665 idx = vsid & (NVSIDS-1); 2666 mask = 1 << (idx % VSID_NBPW); 2667 idx /= VSID_NBPW; 2668 KASSERT(moea64_vsid_bitmap[idx] & mask, 2669 ("Freeing unallocated VSID %#jx", vsid)); 2670 moea64_vsid_bitmap[idx] &= ~mask; 2671 mtx_unlock(&moea64_slb_mutex); 2672 } 2673 2674 void 2675 moea64_release(pmap_t pmap) 2676 { 2677 2678 /* 2679 * Free segment registers' VSIDs 2680 */ 2681 #ifdef __powerpc64__ 2682 slb_free_tree(pmap); 2683 slb_free_user_cache(pmap->pm_slb); 2684 #else 2685 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2686 2687 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2688 #endif 2689 } 2690 2691 /* 2692 * Remove all pages mapped by the specified pmap 2693 */ 2694 void 2695 moea64_remove_pages(pmap_t pm) 2696 { 2697 struct pvo_entry *pvo, *tpvo; 2698 struct pvo_dlist tofree; 2699 2700 SLIST_INIT(&tofree); 2701 2702 PMAP_LOCK(pm); 2703 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2704 if (pvo->pvo_vaddr & PVO_WIRED) 2705 continue; 2706 2707 /* 2708 * For locking reasons, remove this from the page table and 2709 * pmap, but save delinking from the vm_page for a second 2710 * pass 2711 */ 2712 moea64_pvo_remove_from_pmap(pvo); 2713 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2714 } 2715 PMAP_UNLOCK(pm); 2716 2717 while (!SLIST_EMPTY(&tofree)) { 2718 pvo = SLIST_FIRST(&tofree); 2719 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2720 moea64_pvo_remove_from_page(pvo); 2721 free_pvo_entry(pvo); 2722 } 2723 } 2724 2725 static void 2726 moea64_remove_locked(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2727 struct pvo_dlist *tofree) 2728 { 2729 struct pvo_entry *pvo, *tpvo, key; 2730 2731 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2732 2733 key.pvo_vaddr = sva; 2734 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2735 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2736 if (PVO_IS_SP(pvo)) { 2737 if (moea64_sp_pvo_in_range(pvo, sva, eva)) { 2738 tpvo = moea64_sp_remove(pvo, tofree); 2739 continue; 2740 } else { 2741 CTR1(KTR_PMAP, "%s: demote before remove", 2742 __func__); 2743 moea64_sp_demote(pvo); 2744 } 2745 } 2746 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2747 2748 /* 2749 * For locking reasons, remove this from the page table and 2750 * pmap, but save delinking from the vm_page for a second 2751 * pass 2752 */ 2753 moea64_pvo_remove_from_pmap(pvo); 2754 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink); 2755 } 2756 } 2757 2758 /* 2759 * Remove the given range of addresses from the specified map. 2760 */ 2761 void 2762 moea64_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2763 { 2764 struct pvo_entry *pvo; 2765 struct pvo_dlist tofree; 2766 2767 /* 2768 * Perform an unsynchronized read. This is, however, safe. 2769 */ 2770 if (pm->pm_stats.resident_count == 0) 2771 return; 2772 2773 SLIST_INIT(&tofree); 2774 PMAP_LOCK(pm); 2775 moea64_remove_locked(pm, sva, eva, &tofree); 2776 PMAP_UNLOCK(pm); 2777 2778 while (!SLIST_EMPTY(&tofree)) { 2779 pvo = SLIST_FIRST(&tofree); 2780 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2781 moea64_pvo_remove_from_page(pvo); 2782 free_pvo_entry(pvo); 2783 } 2784 } 2785 2786 /* 2787 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2788 * will reflect changes in pte's back to the vm_page. 2789 */ 2790 void 2791 moea64_remove_all(vm_page_t m) 2792 { 2793 struct pvo_entry *pvo, *next_pvo; 2794 struct pvo_head freequeue; 2795 int wasdead; 2796 pmap_t pmap; 2797 2798 LIST_INIT(&freequeue); 2799 2800 PV_PAGE_LOCK(m); 2801 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2802 pmap = pvo->pvo_pmap; 2803 PMAP_LOCK(pmap); 2804 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2805 if (!wasdead) { 2806 if (PVO_IS_SP(pvo)) { 2807 CTR1(KTR_PMAP, "%s: demote before remove_all", 2808 __func__); 2809 moea64_sp_demote(pvo); 2810 } 2811 moea64_pvo_remove_from_pmap(pvo); 2812 } 2813 moea64_pvo_remove_from_page_locked(pvo, m); 2814 if (!wasdead) 2815 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2816 PMAP_UNLOCK(pmap); 2817 2818 } 2819 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2820 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2821 PV_PAGE_UNLOCK(m); 2822 2823 /* Clean up UMA allocations */ 2824 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2825 free_pvo_entry(pvo); 2826 } 2827 2828 /* 2829 * Allocate a physical page of memory directly from the phys_avail map. 2830 * Can only be called from moea64_bootstrap before avail start and end are 2831 * calculated. 2832 */ 2833 vm_offset_t 2834 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2835 { 2836 vm_offset_t s, e; 2837 int i, j; 2838 2839 size = round_page(size); 2840 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2841 if (align != 0) 2842 s = roundup2(phys_avail[i], align); 2843 else 2844 s = phys_avail[i]; 2845 e = s + size; 2846 2847 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2848 continue; 2849 2850 if (s + size > platform_real_maxaddr()) 2851 continue; 2852 2853 if (s == phys_avail[i]) { 2854 phys_avail[i] += size; 2855 } else if (e == phys_avail[i + 1]) { 2856 phys_avail[i + 1] -= size; 2857 } else { 2858 for (j = phys_avail_count * 2; j > i; j -= 2) { 2859 phys_avail[j] = phys_avail[j - 2]; 2860 phys_avail[j + 1] = phys_avail[j - 1]; 2861 } 2862 2863 phys_avail[i + 3] = phys_avail[i + 1]; 2864 phys_avail[i + 1] = s; 2865 phys_avail[i + 2] = e; 2866 phys_avail_count++; 2867 } 2868 2869 return (s); 2870 } 2871 panic("moea64_bootstrap_alloc: could not allocate memory"); 2872 } 2873 2874 static int 2875 moea64_pvo_enter(struct pvo_entry *pvo, struct pvo_head *pvo_head, 2876 struct pvo_entry **oldpvop) 2877 { 2878 struct pvo_entry *old_pvo; 2879 int err; 2880 2881 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2882 2883 STAT_MOEA64(moea64_pvo_enter_calls++); 2884 2885 /* 2886 * Add to pmap list 2887 */ 2888 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2889 2890 if (old_pvo != NULL) { 2891 if (oldpvop != NULL) 2892 *oldpvop = old_pvo; 2893 return (EEXIST); 2894 } 2895 2896 if (pvo_head != NULL) { 2897 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2898 } 2899 2900 if (pvo->pvo_vaddr & PVO_WIRED) 2901 pvo->pvo_pmap->pm_stats.wired_count++; 2902 pvo->pvo_pmap->pm_stats.resident_count++; 2903 2904 /* 2905 * Insert it into the hardware page table 2906 */ 2907 err = moea64_pte_insert(pvo); 2908 if (err != 0) { 2909 panic("moea64_pvo_enter: overflow"); 2910 } 2911 2912 STAT_MOEA64(moea64_pvo_entries++); 2913 2914 if (pvo->pvo_pmap == kernel_pmap) 2915 isync(); 2916 2917 #ifdef __powerpc64__ 2918 /* 2919 * Make sure all our bootstrap mappings are in the SLB as soon 2920 * as virtual memory is switched on. 2921 */ 2922 if (!pmap_bootstrapped) 2923 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2924 pvo->pvo_vaddr & PVO_LARGE); 2925 #endif 2926 2927 return (0); 2928 } 2929 2930 static void 2931 moea64_pvo_remove_from_pmap(struct pvo_entry *pvo) 2932 { 2933 struct vm_page *pg; 2934 int32_t refchg; 2935 2936 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2937 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2938 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2939 2940 /* 2941 * If there is an active pte entry, we need to deactivate it 2942 */ 2943 refchg = moea64_pte_unset(pvo); 2944 if (refchg < 0) { 2945 /* 2946 * If it was evicted from the page table, be pessimistic and 2947 * dirty the page. 2948 */ 2949 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2950 refchg = LPTE_CHG; 2951 else 2952 refchg = 0; 2953 } 2954 2955 /* 2956 * Update our statistics. 2957 */ 2958 pvo->pvo_pmap->pm_stats.resident_count--; 2959 if (pvo->pvo_vaddr & PVO_WIRED) 2960 pvo->pvo_pmap->pm_stats.wired_count--; 2961 2962 /* 2963 * Remove this PVO from the pmap list. 2964 */ 2965 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2966 2967 /* 2968 * Mark this for the next sweep 2969 */ 2970 pvo->pvo_vaddr |= PVO_DEAD; 2971 2972 /* Send RC bits to VM */ 2973 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2974 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2975 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2976 if (pg != NULL) { 2977 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2978 if (refchg & LPTE_CHG) 2979 vm_page_dirty(pg); 2980 if (refchg & LPTE_REF) 2981 vm_page_aflag_set(pg, PGA_REFERENCED); 2982 } 2983 } 2984 } 2985 2986 static inline void 2987 moea64_pvo_remove_from_page_locked(struct pvo_entry *pvo, 2988 vm_page_t m) 2989 { 2990 2991 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2992 2993 /* Use NULL pmaps as a sentinel for races in page deletion */ 2994 if (pvo->pvo_pmap == NULL) 2995 return; 2996 pvo->pvo_pmap = NULL; 2997 2998 /* 2999 * Update vm about page writeability/executability if managed 3000 */ 3001 PV_LOCKASSERT(PVO_PADDR(pvo)); 3002 if (pvo->pvo_vaddr & PVO_MANAGED) { 3003 if (m != NULL) { 3004 LIST_REMOVE(pvo, pvo_vlink); 3005 if (LIST_EMPTY(vm_page_to_pvoh(m))) 3006 vm_page_aflag_clear(m, 3007 PGA_WRITEABLE | PGA_EXECUTABLE); 3008 } 3009 } 3010 3011 STAT_MOEA64(moea64_pvo_entries--); 3012 STAT_MOEA64(moea64_pvo_remove_calls++); 3013 } 3014 3015 static void 3016 moea64_pvo_remove_from_page(struct pvo_entry *pvo) 3017 { 3018 vm_page_t pg = NULL; 3019 3020 if (pvo->pvo_vaddr & PVO_MANAGED) 3021 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 3022 3023 PV_LOCK(PVO_PADDR(pvo)); 3024 moea64_pvo_remove_from_page_locked(pvo, pg); 3025 PV_UNLOCK(PVO_PADDR(pvo)); 3026 } 3027 3028 static struct pvo_entry * 3029 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 3030 { 3031 struct pvo_entry key; 3032 3033 PMAP_LOCK_ASSERT(pm, MA_OWNED); 3034 3035 key.pvo_vaddr = va & ~ADDR_POFF; 3036 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 3037 } 3038 3039 static boolean_t 3040 moea64_query_bit(vm_page_t m, uint64_t ptebit) 3041 { 3042 struct pvo_entry *pvo; 3043 int64_t ret; 3044 boolean_t rv; 3045 vm_page_t sp; 3046 3047 /* 3048 * See if this bit is stored in the page already. 3049 * 3050 * For superpages, the bit is stored in the first vm page. 3051 */ 3052 if ((m->md.mdpg_attrs & ptebit) != 0 || 3053 ((sp = PHYS_TO_VM_PAGE(VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK)) != NULL && 3054 (sp->md.mdpg_attrs & (ptebit | MDPG_ATTR_SP)) == 3055 (ptebit | MDPG_ATTR_SP))) 3056 return (TRUE); 3057 3058 /* 3059 * Examine each PTE. Sync so that any pending REF/CHG bits are 3060 * flushed to the PTEs. 3061 */ 3062 rv = FALSE; 3063 powerpc_sync(); 3064 PV_PAGE_LOCK(m); 3065 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 3066 if (PVO_IS_SP(pvo)) { 3067 ret = moea64_sp_query(pvo, ptebit); 3068 /* 3069 * If SP was not demoted, check its REF/CHG bits here. 3070 */ 3071 if (ret != -1) { 3072 if ((ret & ptebit) != 0) { 3073 rv = TRUE; 3074 break; 3075 } 3076 continue; 3077 } 3078 /* else, fallthrough */ 3079 } 3080 3081 ret = 0; 3082 3083 /* 3084 * See if this pvo has a valid PTE. if so, fetch the 3085 * REF/CHG bits from the valid PTE. If the appropriate 3086 * ptebit is set, return success. 3087 */ 3088 PMAP_LOCK(pvo->pvo_pmap); 3089 if (!(pvo->pvo_vaddr & PVO_DEAD)) 3090 ret = moea64_pte_synch(pvo); 3091 PMAP_UNLOCK(pvo->pvo_pmap); 3092 3093 if (ret > 0) { 3094 atomic_set_32(&m->md.mdpg_attrs, 3095 ret & (LPTE_CHG | LPTE_REF)); 3096 if (ret & ptebit) { 3097 rv = TRUE; 3098 break; 3099 } 3100 } 3101 } 3102 PV_PAGE_UNLOCK(m); 3103 3104 return (rv); 3105 } 3106 3107 static u_int 3108 moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 3109 { 3110 u_int count; 3111 struct pvo_entry *pvo; 3112 int64_t ret; 3113 3114 /* 3115 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 3116 * we can reset the right ones). 3117 */ 3118 powerpc_sync(); 3119 3120 /* 3121 * For each pvo entry, clear the pte's ptebit. 3122 */ 3123 count = 0; 3124 PV_PAGE_LOCK(m); 3125 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 3126 if (PVO_IS_SP(pvo)) { 3127 if ((ret = moea64_sp_clear(pvo, m, ptebit)) != -1) { 3128 count += ret; 3129 continue; 3130 } 3131 } 3132 ret = 0; 3133 3134 PMAP_LOCK(pvo->pvo_pmap); 3135 if (!(pvo->pvo_vaddr & PVO_DEAD)) 3136 ret = moea64_pte_clear(pvo, ptebit); 3137 PMAP_UNLOCK(pvo->pvo_pmap); 3138 3139 if (ret > 0 && (ret & ptebit)) 3140 count++; 3141 } 3142 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 3143 PV_PAGE_UNLOCK(m); 3144 3145 return (count); 3146 } 3147 3148 boolean_t 3149 moea64_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 3150 { 3151 struct pvo_entry *pvo, key; 3152 vm_offset_t ppa; 3153 int error = 0; 3154 3155 if (hw_direct_map && mem_valid(pa, size) == 0) 3156 return (0); 3157 3158 PMAP_LOCK(kernel_pmap); 3159 ppa = pa & ~ADDR_POFF; 3160 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 3161 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 3162 ppa < pa + size; ppa += PAGE_SIZE, 3163 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 3164 if (pvo == NULL || PVO_PADDR(pvo) != ppa) { 3165 error = EFAULT; 3166 break; 3167 } 3168 } 3169 PMAP_UNLOCK(kernel_pmap); 3170 3171 return (error); 3172 } 3173 3174 /* 3175 * Map a set of physical memory pages into the kernel virtual 3176 * address space. Return a pointer to where it is mapped. This 3177 * routine is intended to be used for mapping device memory, 3178 * NOT real memory. 3179 */ 3180 void * 3181 moea64_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 3182 { 3183 vm_offset_t va, tmpva, ppa, offset; 3184 3185 ppa = trunc_page(pa); 3186 offset = pa & PAGE_MASK; 3187 size = roundup2(offset + size, PAGE_SIZE); 3188 3189 va = kva_alloc(size); 3190 3191 if (!va) 3192 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 3193 3194 for (tmpva = va; size > 0;) { 3195 moea64_kenter_attr(tmpva, ppa, ma); 3196 size -= PAGE_SIZE; 3197 tmpva += PAGE_SIZE; 3198 ppa += PAGE_SIZE; 3199 } 3200 3201 return ((void *)(va + offset)); 3202 } 3203 3204 void * 3205 moea64_mapdev(vm_paddr_t pa, vm_size_t size) 3206 { 3207 3208 return moea64_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT); 3209 } 3210 3211 void 3212 moea64_unmapdev(vm_offset_t va, vm_size_t size) 3213 { 3214 vm_offset_t base, offset; 3215 3216 base = trunc_page(va); 3217 offset = va & PAGE_MASK; 3218 size = roundup2(offset + size, PAGE_SIZE); 3219 3220 moea64_qremove(base, atop(size)); 3221 kva_free(base, size); 3222 } 3223 3224 void 3225 moea64_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3226 { 3227 struct pvo_entry *pvo; 3228 vm_offset_t lim; 3229 vm_paddr_t pa; 3230 vm_size_t len; 3231 3232 if (__predict_false(pm == NULL)) 3233 pm = &curthread->td_proc->p_vmspace->vm_pmap; 3234 3235 PMAP_LOCK(pm); 3236 while (sz > 0) { 3237 lim = round_page(va+1); 3238 len = MIN(lim - va, sz); 3239 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 3240 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 3241 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 3242 moea64_syncicache(pm, va, pa, len); 3243 } 3244 va += len; 3245 sz -= len; 3246 } 3247 PMAP_UNLOCK(pm); 3248 } 3249 3250 void 3251 moea64_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 3252 { 3253 3254 *va = (void *)(uintptr_t)pa; 3255 } 3256 3257 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 3258 3259 void 3260 moea64_scan_init() 3261 { 3262 struct pvo_entry *pvo; 3263 vm_offset_t va; 3264 int i; 3265 3266 if (!do_minidump) { 3267 /* Initialize phys. segments for dumpsys(). */ 3268 memset(&dump_map, 0, sizeof(dump_map)); 3269 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 3270 for (i = 0; i < pregions_sz; i++) { 3271 dump_map[i].pa_start = pregions[i].mr_start; 3272 dump_map[i].pa_size = pregions[i].mr_size; 3273 } 3274 return; 3275 } 3276 3277 /* Virtual segments for minidumps: */ 3278 memset(&dump_map, 0, sizeof(dump_map)); 3279 3280 /* 1st: kernel .data and .bss. */ 3281 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 3282 dump_map[0].pa_size = round_page((uintptr_t)_end) - 3283 dump_map[0].pa_start; 3284 3285 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 3286 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 3287 dump_map[1].pa_size = round_page(msgbufp->msg_size); 3288 3289 /* 3rd: kernel VM. */ 3290 va = dump_map[1].pa_start + dump_map[1].pa_size; 3291 /* Find start of next chunk (from va). */ 3292 while (va < virtual_end) { 3293 /* Don't dump the buffer cache. */ 3294 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 3295 va = kmi.buffer_eva; 3296 continue; 3297 } 3298 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 3299 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 3300 break; 3301 va += PAGE_SIZE; 3302 } 3303 if (va < virtual_end) { 3304 dump_map[2].pa_start = va; 3305 va += PAGE_SIZE; 3306 /* Find last page in chunk. */ 3307 while (va < virtual_end) { 3308 /* Don't run into the buffer cache. */ 3309 if (va == kmi.buffer_sva) 3310 break; 3311 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 3312 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 3313 break; 3314 va += PAGE_SIZE; 3315 } 3316 dump_map[2].pa_size = va - dump_map[2].pa_start; 3317 } 3318 } 3319 3320 #ifdef __powerpc64__ 3321 3322 static size_t 3323 moea64_scan_pmap() 3324 { 3325 struct pvo_entry *pvo; 3326 vm_paddr_t pa, pa_end; 3327 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 3328 uint64_t lpsize; 3329 3330 lpsize = moea64_large_page_size; 3331 kstart = trunc_page((vm_offset_t)_etext); 3332 kend = round_page((vm_offset_t)_end); 3333 kstart_lp = kstart & ~moea64_large_page_mask; 3334 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 3335 3336 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 3337 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 3338 kstart, kend, kstart_lp, kend_lp); 3339 3340 PMAP_LOCK(kernel_pmap); 3341 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 3342 va = pvo->pvo_vaddr; 3343 3344 if (va & PVO_DEAD) 3345 continue; 3346 3347 /* Skip DMAP (except kernel area) */ 3348 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 3349 if (va & PVO_LARGE) { 3350 pgva = va & ~moea64_large_page_mask; 3351 if (pgva < kstart_lp || pgva >= kend_lp) 3352 continue; 3353 } else { 3354 pgva = trunc_page(va); 3355 if (pgva < kstart || pgva >= kend) 3356 continue; 3357 } 3358 } 3359 3360 pa = PVO_PADDR(pvo); 3361 3362 if (va & PVO_LARGE) { 3363 pa_end = pa + lpsize; 3364 for (; pa < pa_end; pa += PAGE_SIZE) { 3365 if (is_dumpable(pa)) 3366 dump_add_page(pa); 3367 } 3368 } else { 3369 if (is_dumpable(pa)) 3370 dump_add_page(pa); 3371 } 3372 } 3373 PMAP_UNLOCK(kernel_pmap); 3374 3375 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3376 } 3377 3378 static struct dump_context dump_ctx; 3379 3380 static void * 3381 moea64_dump_pmap_init(unsigned blkpgs) 3382 { 3383 dump_ctx.ptex = 0; 3384 dump_ctx.ptex_end = moea64_pteg_count * 8; 3385 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3386 return (&dump_ctx); 3387 } 3388 3389 #else 3390 3391 static size_t 3392 moea64_scan_pmap() 3393 { 3394 return (0); 3395 } 3396 3397 static void * 3398 moea64_dump_pmap_init(unsigned blkpgs) 3399 { 3400 return (NULL); 3401 } 3402 3403 #endif 3404 3405 #ifdef __powerpc64__ 3406 static void 3407 moea64_map_range(vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3408 { 3409 3410 for (; npages > 0; --npages) { 3411 if (moea64_large_page_size != 0 && 3412 (pa & moea64_large_page_mask) == 0 && 3413 (va & moea64_large_page_mask) == 0 && 3414 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3415 PMAP_LOCK(kernel_pmap); 3416 moea64_kenter_large(va, pa, 0, 0); 3417 PMAP_UNLOCK(kernel_pmap); 3418 pa += moea64_large_page_size; 3419 va += moea64_large_page_size; 3420 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3421 } else { 3422 moea64_kenter(va, pa); 3423 pa += PAGE_SIZE; 3424 va += PAGE_SIZE; 3425 } 3426 } 3427 } 3428 3429 static void 3430 moea64_page_array_startup(long pages) 3431 { 3432 long dom_pages[MAXMEMDOM]; 3433 vm_paddr_t pa; 3434 vm_offset_t va, vm_page_base; 3435 vm_size_t needed, size; 3436 long page; 3437 int domain; 3438 int i; 3439 3440 vm_page_base = 0xd000000000000000ULL; 3441 3442 /* Short-circuit single-domain systems. */ 3443 if (vm_ndomains == 1) { 3444 size = round_page(pages * sizeof(struct vm_page)); 3445 pa = vm_phys_early_alloc(0, size); 3446 vm_page_base = moea64_map(&vm_page_base, 3447 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3448 vm_page_array_size = pages; 3449 vm_page_array = (vm_page_t)vm_page_base; 3450 return; 3451 } 3452 3453 page = 0; 3454 for (i = 0; i < MAXMEMDOM; i++) 3455 dom_pages[i] = 0; 3456 3457 /* Now get the number of pages required per domain. */ 3458 for (i = 0; i < vm_phys_nsegs; i++) { 3459 domain = vm_phys_segs[i].domain; 3460 KASSERT(domain < MAXMEMDOM, 3461 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3462 /* Get size of vm_page_array needed for this segment. */ 3463 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3464 dom_pages[domain] += size; 3465 } 3466 3467 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3468 domain = vm_phys_domain(phys_avail[i]); 3469 KASSERT(domain < MAXMEMDOM, 3470 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3471 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3472 dom_pages[domain] += size; 3473 } 3474 3475 /* 3476 * Map in chunks that can get us all 16MB pages. There will be some 3477 * overlap between domains, but that's acceptable for now. 3478 */ 3479 vm_page_array_size = 0; 3480 va = vm_page_base; 3481 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3482 if (dom_pages[i] == 0) 3483 continue; 3484 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3485 size = round_page(size * sizeof(struct vm_page)); 3486 needed = size; 3487 size = roundup2(size, moea64_large_page_size); 3488 pa = vm_phys_early_alloc(i, size); 3489 vm_page_array_size += size / sizeof(struct vm_page); 3490 moea64_map_range(va, pa, size >> PAGE_SHIFT); 3491 /* Scoot up domain 0, to reduce the domain page overlap. */ 3492 if (i == 0) 3493 vm_page_base += size - needed; 3494 va += size; 3495 } 3496 vm_page_array = (vm_page_t)vm_page_base; 3497 vm_page_array_size = pages; 3498 } 3499 #endif 3500 3501 static int64_t 3502 moea64_null_method(void) 3503 { 3504 return (0); 3505 } 3506 3507 static int64_t moea64_pte_replace_default(struct pvo_entry *pvo, int flags) 3508 { 3509 int64_t refchg; 3510 3511 refchg = moea64_pte_unset(pvo); 3512 moea64_pte_insert(pvo); 3513 3514 return (refchg); 3515 } 3516 3517 struct moea64_funcs *moea64_ops; 3518 3519 #define DEFINE_OEA64_IFUNC(ret, func, args, def) \ 3520 DEFINE_IFUNC(, ret, moea64_##func, args) { \ 3521 moea64_##func##_t f; \ 3522 if (moea64_ops == NULL) \ 3523 return ((moea64_##func##_t)def); \ 3524 f = moea64_ops->func; \ 3525 return (f != NULL ? f : (moea64_##func##_t)def);\ 3526 } 3527 3528 void 3529 moea64_install(void) 3530 { 3531 #ifdef __powerpc64__ 3532 if (hw_direct_map == -1) { 3533 moea64_probe_large_page(); 3534 3535 /* Use a direct map if we have large page support */ 3536 if (moea64_large_page_size > 0) 3537 hw_direct_map = 1; 3538 else 3539 hw_direct_map = 0; 3540 } 3541 #endif 3542 3543 /* 3544 * Default to non-DMAP, and switch over to DMAP functions once we know 3545 * we have DMAP. 3546 */ 3547 if (hw_direct_map) { 3548 moea64_methods.quick_enter_page = moea64_quick_enter_page_dmap; 3549 moea64_methods.quick_remove_page = NULL; 3550 moea64_methods.copy_page = moea64_copy_page_dmap; 3551 moea64_methods.zero_page = moea64_zero_page_dmap; 3552 moea64_methods.copy_pages = moea64_copy_pages_dmap; 3553 } 3554 } 3555 3556 DEFINE_OEA64_IFUNC(int64_t, pte_replace, (struct pvo_entry *, int), 3557 moea64_pte_replace_default) 3558 DEFINE_OEA64_IFUNC(int64_t, pte_insert, (struct pvo_entry *), moea64_null_method) 3559 DEFINE_OEA64_IFUNC(int64_t, pte_unset, (struct pvo_entry *), moea64_null_method) 3560 DEFINE_OEA64_IFUNC(int64_t, pte_clear, (struct pvo_entry *, uint64_t), 3561 moea64_null_method) 3562 DEFINE_OEA64_IFUNC(int64_t, pte_synch, (struct pvo_entry *), moea64_null_method) 3563 DEFINE_OEA64_IFUNC(int64_t, pte_insert_sp, (struct pvo_entry *), moea64_null_method) 3564 DEFINE_OEA64_IFUNC(int64_t, pte_unset_sp, (struct pvo_entry *), moea64_null_method) 3565 DEFINE_OEA64_IFUNC(int64_t, pte_replace_sp, (struct pvo_entry *), moea64_null_method) 3566 3567 /* Superpage functions */ 3568 3569 /* MMU interface */ 3570 3571 static bool 3572 moea64_ps_enabled(pmap_t pmap) 3573 { 3574 return (superpages_enabled); 3575 } 3576 3577 static void 3578 moea64_align_superpage(vm_object_t object, vm_ooffset_t offset, 3579 vm_offset_t *addr, vm_size_t size) 3580 { 3581 vm_offset_t sp_offset; 3582 3583 if (size < HPT_SP_SIZE) 3584 return; 3585 3586 CTR4(KTR_PMAP, "%s: offs=%#jx, addr=%p, size=%#jx", 3587 __func__, (uintmax_t)offset, addr, (uintmax_t)size); 3588 3589 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3590 offset += ptoa(object->pg_color); 3591 sp_offset = offset & HPT_SP_MASK; 3592 if (size - ((HPT_SP_SIZE - sp_offset) & HPT_SP_MASK) < HPT_SP_SIZE || 3593 (*addr & HPT_SP_MASK) == sp_offset) 3594 return; 3595 if ((*addr & HPT_SP_MASK) < sp_offset) 3596 *addr = (*addr & ~HPT_SP_MASK) + sp_offset; 3597 else 3598 *addr = ((*addr + HPT_SP_MASK) & ~HPT_SP_MASK) + sp_offset; 3599 } 3600 3601 /* Helpers */ 3602 3603 static __inline void 3604 moea64_pvo_cleanup(struct pvo_dlist *tofree) 3605 { 3606 struct pvo_entry *pvo; 3607 3608 /* clean up */ 3609 while (!SLIST_EMPTY(tofree)) { 3610 pvo = SLIST_FIRST(tofree); 3611 SLIST_REMOVE_HEAD(tofree, pvo_dlink); 3612 if (pvo->pvo_vaddr & PVO_DEAD) 3613 moea64_pvo_remove_from_page(pvo); 3614 free_pvo_entry(pvo); 3615 } 3616 } 3617 3618 static __inline uint16_t 3619 pvo_to_vmpage_flags(struct pvo_entry *pvo) 3620 { 3621 uint16_t flags; 3622 3623 flags = 0; 3624 if ((pvo->pvo_pte.prot & VM_PROT_WRITE) != 0) 3625 flags |= PGA_WRITEABLE; 3626 if ((pvo->pvo_pte.prot & VM_PROT_EXECUTE) != 0) 3627 flags |= PGA_EXECUTABLE; 3628 3629 return (flags); 3630 } 3631 3632 /* 3633 * Check if the given pvo and its superpage are in sva-eva range. 3634 */ 3635 static __inline bool 3636 moea64_sp_pvo_in_range(struct pvo_entry *pvo, vm_offset_t sva, vm_offset_t eva) 3637 { 3638 vm_offset_t spva; 3639 3640 spva = PVO_VADDR(pvo) & ~HPT_SP_MASK; 3641 if (spva >= sva && spva + HPT_SP_SIZE <= eva) { 3642 /* 3643 * Because this function is intended to be called from loops 3644 * that iterate over ordered pvo entries, if the condition 3645 * above is true then the pvo must be the first of its 3646 * superpage. 3647 */ 3648 KASSERT(PVO_VADDR(pvo) == spva, 3649 ("%s: unexpected unaligned superpage pvo", __func__)); 3650 return (true); 3651 } 3652 return (false); 3653 } 3654 3655 /* 3656 * Update vm about the REF/CHG bits if the superpage is managed and 3657 * has (or had) write access. 3658 */ 3659 static void 3660 moea64_sp_refchg_process(struct pvo_entry *sp, vm_page_t m, 3661 int64_t sp_refchg, vm_prot_t prot) 3662 { 3663 vm_page_t m_end; 3664 int64_t refchg; 3665 3666 if ((sp->pvo_vaddr & PVO_MANAGED) != 0 && (prot & VM_PROT_WRITE) != 0) { 3667 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) { 3668 refchg = sp_refchg | 3669 atomic_readandclear_32(&m->md.mdpg_attrs); 3670 if (refchg & LPTE_CHG) 3671 vm_page_dirty(m); 3672 if (refchg & LPTE_REF) 3673 vm_page_aflag_set(m, PGA_REFERENCED); 3674 } 3675 } 3676 } 3677 3678 /* Superpage ops */ 3679 3680 static int 3681 moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 3682 vm_prot_t prot, u_int flags, int8_t psind) 3683 { 3684 struct pvo_entry *pvo, **pvos; 3685 struct pvo_head *pvo_head; 3686 vm_offset_t sva; 3687 vm_page_t sm; 3688 vm_paddr_t pa, spa; 3689 bool sync; 3690 struct pvo_dlist tofree; 3691 int error, i; 3692 uint16_t aflags; 3693 3694 KASSERT((va & HPT_SP_MASK) == 0, ("%s: va %#jx unaligned", 3695 __func__, (uintmax_t)va)); 3696 KASSERT(psind == 1, ("%s: invalid psind: %d", __func__, psind)); 3697 KASSERT(m->psind == 1, ("%s: invalid m->psind: %d", 3698 __func__, m->psind)); 3699 KASSERT(pmap != kernel_pmap, 3700 ("%s: function called with kernel pmap", __func__)); 3701 3702 CTR5(KTR_PMAP, "%s: va=%#jx, pa=%#jx, prot=%#x, flags=%#x, psind=1", 3703 __func__, (uintmax_t)va, (uintmax_t)VM_PAGE_TO_PHYS(m), 3704 prot, flags); 3705 3706 SLIST_INIT(&tofree); 3707 3708 sva = va; 3709 sm = m; 3710 spa = pa = VM_PAGE_TO_PHYS(sm); 3711 3712 /* Try to allocate all PVOs first, to make failure handling easier. */ 3713 pvos = malloc(HPT_SP_PAGES * sizeof(struct pvo_entry *), M_TEMP, 3714 M_NOWAIT); 3715 if (pvos == NULL) { 3716 CTR1(KTR_PMAP, "%s: failed to alloc pvo array", __func__); 3717 return (KERN_RESOURCE_SHORTAGE); 3718 } 3719 3720 for (i = 0; i < HPT_SP_PAGES; i++) { 3721 pvos[i] = alloc_pvo_entry(0); 3722 if (pvos[i] == NULL) { 3723 CTR1(KTR_PMAP, "%s: failed to alloc pvo", __func__); 3724 for (i = i - 1; i >= 0; i--) 3725 free_pvo_entry(pvos[i]); 3726 free(pvos, M_TEMP); 3727 return (KERN_RESOURCE_SHORTAGE); 3728 } 3729 } 3730 3731 SP_PV_LOCK_ALIGNED(spa); 3732 PMAP_LOCK(pmap); 3733 3734 /* Note: moea64_remove_locked() also clears cached REF/CHG bits. */ 3735 moea64_remove_locked(pmap, va, va + HPT_SP_SIZE, &tofree); 3736 3737 /* Enter pages */ 3738 for (i = 0; i < HPT_SP_PAGES; 3739 i++, va += PAGE_SIZE, pa += PAGE_SIZE, m++) { 3740 pvo = pvos[i]; 3741 3742 pvo->pvo_pte.prot = prot; 3743 pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M | 3744 moea64_calc_wimg(pa, pmap_page_get_memattr(m)); 3745 3746 if ((flags & PMAP_ENTER_WIRED) != 0) 3747 pvo->pvo_vaddr |= PVO_WIRED; 3748 pvo->pvo_vaddr |= PVO_LARGE; 3749 3750 if ((m->oflags & VPO_UNMANAGED) != 0) 3751 pvo_head = NULL; 3752 else { 3753 pvo_head = &m->md.mdpg_pvoh; 3754 pvo->pvo_vaddr |= PVO_MANAGED; 3755 } 3756 3757 init_pvo_entry(pvo, pmap, va); 3758 3759 error = moea64_pvo_enter(pvo, pvo_head, NULL); 3760 /* 3761 * All superpage PVOs were previously removed, so no errors 3762 * should occur while inserting the new ones. 3763 */ 3764 KASSERT(error == 0, ("%s: unexpected error " 3765 "when inserting superpage PVO: %d", 3766 __func__, error)); 3767 } 3768 3769 PMAP_UNLOCK(pmap); 3770 SP_PV_UNLOCK_ALIGNED(spa); 3771 3772 sync = (sm->a.flags & PGA_EXECUTABLE) == 0; 3773 /* Note: moea64_pvo_cleanup() also clears page prot. flags. */ 3774 moea64_pvo_cleanup(&tofree); 3775 pvo = pvos[0]; 3776 3777 /* Set vm page flags */ 3778 aflags = pvo_to_vmpage_flags(pvo); 3779 if (aflags != 0) 3780 for (m = sm; m < &sm[HPT_SP_PAGES]; m++) 3781 vm_page_aflag_set(m, aflags); 3782 3783 /* 3784 * Flush the page from the instruction cache if this page is 3785 * mapped executable and cacheable. 3786 */ 3787 if (sync && (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) 3788 moea64_syncicache(pmap, sva, spa, HPT_SP_SIZE); 3789 3790 atomic_add_long(&sp_mappings, 1); 3791 CTR3(KTR_PMAP, "%s: SP success for va %#jx in pmap %p", 3792 __func__, (uintmax_t)sva, pmap); 3793 3794 free(pvos, M_TEMP); 3795 return (KERN_SUCCESS); 3796 } 3797 3798 static void 3799 moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m) 3800 { 3801 struct pvo_entry *first, *pvo; 3802 vm_paddr_t pa, pa_end; 3803 vm_offset_t sva, va_end; 3804 int64_t sp_refchg; 3805 3806 /* This CTR may generate a lot of output. */ 3807 /* CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)va); */ 3808 3809 va &= ~HPT_SP_MASK; 3810 sva = va; 3811 /* Get superpage */ 3812 pa = VM_PAGE_TO_PHYS(m) & ~HPT_SP_MASK; 3813 m = PHYS_TO_VM_PAGE(pa); 3814 3815 PMAP_LOCK(pmap); 3816 3817 /* 3818 * Check if all pages meet promotion criteria. 3819 * 3820 * XXX In some cases the loop below may be executed for each or most 3821 * of the entered pages of a superpage, which can be expensive 3822 * (although it was not profiled) and need some optimization. 3823 * 3824 * Some cases where this seems to happen are: 3825 * - When a superpage is first entered read-only and later becomes 3826 * read-write. 3827 * - When some of the superpage's virtual addresses map to previously 3828 * wired/cached pages while others map to pages allocated from a 3829 * different physical address range. A common scenario where this 3830 * happens is when mmap'ing a file that is already present in FS 3831 * block cache and doesn't fill a superpage. 3832 */ 3833 first = pvo = moea64_pvo_find_va(pmap, sva); 3834 for (pa_end = pa + HPT_SP_SIZE; 3835 pa < pa_end; pa += PAGE_SIZE, va += PAGE_SIZE) { 3836 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 3837 CTR3(KTR_PMAP, 3838 "%s: NULL or dead PVO: pmap=%p, va=%#jx", 3839 __func__, pmap, (uintmax_t)va); 3840 goto error; 3841 } 3842 if (PVO_PADDR(pvo) != pa) { 3843 CTR5(KTR_PMAP, "%s: PAs don't match: " 3844 "pmap=%p, va=%#jx, pvo_pa=%#jx, exp_pa=%#jx", 3845 __func__, pmap, (uintmax_t)va, 3846 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)pa); 3847 atomic_add_long(&sp_p_fail_pa, 1); 3848 goto error; 3849 } 3850 if ((first->pvo_vaddr & PVO_FLAGS_PROMOTE) != 3851 (pvo->pvo_vaddr & PVO_FLAGS_PROMOTE)) { 3852 CTR5(KTR_PMAP, "%s: PVO flags don't match: " 3853 "pmap=%p, va=%#jx, pvo_flags=%#jx, exp_flags=%#jx", 3854 __func__, pmap, (uintmax_t)va, 3855 (uintmax_t)(pvo->pvo_vaddr & PVO_FLAGS_PROMOTE), 3856 (uintmax_t)(first->pvo_vaddr & PVO_FLAGS_PROMOTE)); 3857 atomic_add_long(&sp_p_fail_flags, 1); 3858 goto error; 3859 } 3860 if (first->pvo_pte.prot != pvo->pvo_pte.prot) { 3861 CTR5(KTR_PMAP, "%s: PVO protections don't match: " 3862 "pmap=%p, va=%#jx, pvo_prot=%#x, exp_prot=%#x", 3863 __func__, pmap, (uintmax_t)va, 3864 pvo->pvo_pte.prot, first->pvo_pte.prot); 3865 atomic_add_long(&sp_p_fail_prot, 1); 3866 goto error; 3867 } 3868 if ((first->pvo_pte.pa & LPTE_WIMG) != 3869 (pvo->pvo_pte.pa & LPTE_WIMG)) { 3870 CTR5(KTR_PMAP, "%s: WIMG bits don't match: " 3871 "pmap=%p, va=%#jx, pvo_wimg=%#jx, exp_wimg=%#jx", 3872 __func__, pmap, (uintmax_t)va, 3873 (uintmax_t)(pvo->pvo_pte.pa & LPTE_WIMG), 3874 (uintmax_t)(first->pvo_pte.pa & LPTE_WIMG)); 3875 atomic_add_long(&sp_p_fail_wimg, 1); 3876 goto error; 3877 } 3878 3879 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo); 3880 } 3881 3882 /* All OK, promote. */ 3883 3884 /* 3885 * Handle superpage REF/CHG bits. If REF or CHG is set in 3886 * any page, then it must be set in the superpage. 3887 * 3888 * Instead of querying each page, we take advantage of two facts: 3889 * 1- If a page is being promoted, it was referenced. 3890 * 2- If promoted pages are writable, they were modified. 3891 */ 3892 sp_refchg = LPTE_REF | 3893 ((first->pvo_pte.prot & VM_PROT_WRITE) != 0 ? LPTE_CHG : 0); 3894 3895 /* Promote pages */ 3896 3897 for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE; 3898 pvo != NULL && PVO_VADDR(pvo) < va_end; 3899 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 3900 pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK; 3901 pvo->pvo_pte.pa |= LPTE_LP_4K_16M; 3902 pvo->pvo_vaddr |= PVO_LARGE; 3903 } 3904 moea64_pte_replace_sp(first); 3905 3906 /* Send REF/CHG bits to VM */ 3907 moea64_sp_refchg_process(first, m, sp_refchg, first->pvo_pte.prot); 3908 3909 /* Use first page to cache REF/CHG bits */ 3910 atomic_set_32(&m->md.mdpg_attrs, sp_refchg | MDPG_ATTR_SP); 3911 3912 PMAP_UNLOCK(pmap); 3913 3914 atomic_add_long(&sp_mappings, 1); 3915 atomic_add_long(&sp_promotions, 1); 3916 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p", 3917 __func__, (uintmax_t)sva, pmap); 3918 return; 3919 3920 error: 3921 atomic_add_long(&sp_p_failures, 1); 3922 PMAP_UNLOCK(pmap); 3923 } 3924 3925 static void 3926 moea64_sp_demote_aligned(struct pvo_entry *sp) 3927 { 3928 struct pvo_entry *pvo; 3929 vm_offset_t va, va_end; 3930 vm_paddr_t pa; 3931 vm_page_t m; 3932 pmap_t pmap; 3933 int64_t refchg; 3934 3935 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 3936 3937 pmap = sp->pvo_pmap; 3938 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3939 3940 pvo = sp; 3941 3942 /* Demote pages */ 3943 3944 va = PVO_VADDR(pvo); 3945 pa = PVO_PADDR(pvo); 3946 m = PHYS_TO_VM_PAGE(pa); 3947 3948 for (pvo = sp, va_end = va + HPT_SP_SIZE; 3949 pvo != NULL && PVO_VADDR(pvo) < va_end; 3950 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo), 3951 va += PAGE_SIZE, pa += PAGE_SIZE) { 3952 KASSERT(pvo && PVO_VADDR(pvo) == va, 3953 ("%s: missing PVO for va %#jx", __func__, (uintmax_t)va)); 3954 3955 pvo->pvo_vaddr &= ~PVO_LARGE; 3956 pvo->pvo_pte.pa &= ~LPTE_RPGN; 3957 pvo->pvo_pte.pa |= pa; 3958 3959 } 3960 refchg = moea64_pte_replace_sp(sp); 3961 3962 /* 3963 * Clear SP flag 3964 * 3965 * XXX It is possible that another pmap has this page mapped as 3966 * part of a superpage, but as the SP flag is used only for 3967 * caching SP REF/CHG bits, that will be queried if not set 3968 * in cache, it should be ok to clear it here. 3969 */ 3970 atomic_clear_32(&m->md.mdpg_attrs, MDPG_ATTR_SP); 3971 3972 /* 3973 * Handle superpage REF/CHG bits. A bit set in the superpage 3974 * means all pages should consider it set. 3975 */ 3976 moea64_sp_refchg_process(sp, m, refchg, sp->pvo_pte.prot); 3977 3978 atomic_add_long(&sp_demotions, 1); 3979 CTR3(KTR_PMAP, "%s: success for va %#jx in pmap %p", 3980 __func__, (uintmax_t)PVO_VADDR(sp), pmap); 3981 } 3982 3983 static void 3984 moea64_sp_demote(struct pvo_entry *pvo) 3985 { 3986 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 3987 3988 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 3989 pvo = moea64_pvo_find_va(pvo->pvo_pmap, 3990 PVO_VADDR(pvo) & ~HPT_SP_MASK); 3991 KASSERT(pvo != NULL, ("%s: missing PVO for va %#jx", 3992 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 3993 } 3994 moea64_sp_demote_aligned(pvo); 3995 } 3996 3997 static struct pvo_entry * 3998 moea64_sp_unwire(struct pvo_entry *sp) 3999 { 4000 struct pvo_entry *pvo, *prev; 4001 vm_offset_t eva; 4002 pmap_t pm; 4003 int64_t ret, refchg; 4004 4005 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 4006 4007 pm = sp->pvo_pmap; 4008 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4009 4010 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4011 refchg = 0; 4012 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4013 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 4014 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 4015 panic("%s: pvo %p is missing PVO_WIRED", 4016 __func__, pvo); 4017 pvo->pvo_vaddr &= ~PVO_WIRED; 4018 4019 ret = moea64_pte_replace(pvo, 0 /* No invalidation */); 4020 if (ret < 0) 4021 refchg |= LPTE_CHG; 4022 else 4023 refchg |= ret; 4024 4025 pm->pm_stats.wired_count--; 4026 } 4027 4028 /* Send REF/CHG bits to VM */ 4029 moea64_sp_refchg_process(sp, PHYS_TO_VM_PAGE(PVO_PADDR(sp)), 4030 refchg, sp->pvo_pte.prot); 4031 4032 return (prev); 4033 } 4034 4035 static struct pvo_entry * 4036 moea64_sp_protect(struct pvo_entry *sp, vm_prot_t prot) 4037 { 4038 struct pvo_entry *pvo, *prev; 4039 vm_offset_t eva; 4040 pmap_t pm; 4041 vm_page_t m, m_end; 4042 int64_t ret, refchg; 4043 vm_prot_t oldprot; 4044 4045 CTR3(KTR_PMAP, "%s: va=%#jx, prot=%x", 4046 __func__, (uintmax_t)PVO_VADDR(sp), prot); 4047 4048 pm = sp->pvo_pmap; 4049 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4050 4051 oldprot = sp->pvo_pte.prot; 4052 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4053 KASSERT(m != NULL, ("%s: missing vm page for pa %#jx", 4054 __func__, (uintmax_t)PVO_PADDR(sp))); 4055 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4056 refchg = 0; 4057 4058 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4059 prev = pvo, pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 4060 pvo->pvo_pte.prot = prot; 4061 /* 4062 * If the PVO is in the page table, update mapping 4063 */ 4064 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 4065 if (ret < 0) 4066 refchg |= LPTE_CHG; 4067 else 4068 refchg |= ret; 4069 } 4070 4071 /* Send REF/CHG bits to VM */ 4072 moea64_sp_refchg_process(sp, m, refchg, oldprot); 4073 4074 /* Handle pages that became executable */ 4075 if ((m->a.flags & PGA_EXECUTABLE) == 0 && 4076 (sp->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 4077 if ((m->oflags & VPO_UNMANAGED) == 0) 4078 for (m_end = &m[HPT_SP_PAGES]; m < m_end; m++) 4079 vm_page_aflag_set(m, PGA_EXECUTABLE); 4080 moea64_syncicache(pm, PVO_VADDR(sp), PVO_PADDR(sp), 4081 HPT_SP_SIZE); 4082 } 4083 4084 return (prev); 4085 } 4086 4087 static struct pvo_entry * 4088 moea64_sp_remove(struct pvo_entry *sp, struct pvo_dlist *tofree) 4089 { 4090 struct pvo_entry *pvo, *tpvo; 4091 vm_offset_t eva; 4092 pmap_t pm; 4093 4094 CTR2(KTR_PMAP, "%s: va=%#jx", __func__, (uintmax_t)PVO_VADDR(sp)); 4095 4096 pm = sp->pvo_pmap; 4097 PMAP_LOCK_ASSERT(pm, MA_OWNED); 4098 4099 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4100 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 4101 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 4102 4103 /* 4104 * For locking reasons, remove this from the page table and 4105 * pmap, but save delinking from the vm_page for a second 4106 * pass 4107 */ 4108 moea64_pvo_remove_from_pmap(pvo); 4109 SLIST_INSERT_HEAD(tofree, pvo, pvo_dlink); 4110 } 4111 4112 /* 4113 * Clear SP bit 4114 * 4115 * XXX See comment in moea64_sp_demote_aligned() for why it's 4116 * ok to always clear the SP bit on remove/demote. 4117 */ 4118 atomic_clear_32(&PHYS_TO_VM_PAGE(PVO_PADDR(sp))->md.mdpg_attrs, 4119 MDPG_ATTR_SP); 4120 4121 return (tpvo); 4122 } 4123 4124 static int64_t 4125 moea64_sp_query_locked(struct pvo_entry *pvo, uint64_t ptebit) 4126 { 4127 int64_t refchg, ret; 4128 vm_offset_t eva; 4129 vm_page_t m; 4130 pmap_t pmap; 4131 struct pvo_entry *sp; 4132 4133 pmap = pvo->pvo_pmap; 4134 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4135 4136 /* Get first SP PVO */ 4137 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 4138 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK); 4139 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx", 4140 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4141 } else 4142 sp = pvo; 4143 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4144 4145 refchg = 0; 4146 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4147 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 4148 ret = moea64_pte_synch(pvo); 4149 if (ret > 0) { 4150 refchg |= ret & (LPTE_CHG | LPTE_REF); 4151 if ((refchg & ptebit) != 0) 4152 break; 4153 } 4154 } 4155 4156 /* Save results */ 4157 if (refchg != 0) { 4158 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4159 atomic_set_32(&m->md.mdpg_attrs, refchg | MDPG_ATTR_SP); 4160 } 4161 4162 return (refchg); 4163 } 4164 4165 static int64_t 4166 moea64_sp_query(struct pvo_entry *pvo, uint64_t ptebit) 4167 { 4168 int64_t refchg; 4169 pmap_t pmap; 4170 4171 pmap = pvo->pvo_pmap; 4172 PMAP_LOCK(pmap); 4173 4174 /* 4175 * Check if SP was demoted/removed before pmap lock was acquired. 4176 */ 4177 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4178 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4179 __func__, (uintmax_t)PVO_PADDR(pvo)); 4180 PMAP_UNLOCK(pmap); 4181 return (-1); 4182 } 4183 4184 refchg = moea64_sp_query_locked(pvo, ptebit); 4185 PMAP_UNLOCK(pmap); 4186 4187 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx", 4188 __func__, (uintmax_t)PVO_VADDR(pvo), 4189 (uintmax_t)PVO_PADDR(pvo), (uintmax_t)refchg); 4190 4191 return (refchg); 4192 } 4193 4194 static int64_t 4195 moea64_sp_pvo_clear(struct pvo_entry *pvo, uint64_t ptebit) 4196 { 4197 int64_t refchg, ret; 4198 pmap_t pmap; 4199 struct pvo_entry *sp; 4200 vm_offset_t eva; 4201 vm_page_t m; 4202 4203 pmap = pvo->pvo_pmap; 4204 PMAP_LOCK(pmap); 4205 4206 /* 4207 * Check if SP was demoted/removed before pmap lock was acquired. 4208 */ 4209 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4210 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4211 __func__, (uintmax_t)PVO_PADDR(pvo)); 4212 PMAP_UNLOCK(pmap); 4213 return (-1); 4214 } 4215 4216 /* Get first SP PVO */ 4217 if ((PVO_VADDR(pvo) & HPT_SP_MASK) != 0) { 4218 sp = moea64_pvo_find_va(pmap, PVO_VADDR(pvo) & ~HPT_SP_MASK); 4219 KASSERT(sp != NULL, ("%s: missing PVO for va %#jx", 4220 __func__, (uintmax_t)(PVO_VADDR(pvo) & ~HPT_SP_MASK))); 4221 } else 4222 sp = pvo; 4223 eva = PVO_VADDR(sp) + HPT_SP_SIZE; 4224 4225 refchg = 0; 4226 for (pvo = sp; pvo != NULL && PVO_VADDR(pvo) < eva; 4227 pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { 4228 ret = moea64_pte_clear(pvo, ptebit); 4229 if (ret > 0) 4230 refchg |= ret & (LPTE_CHG | LPTE_REF); 4231 } 4232 4233 m = PHYS_TO_VM_PAGE(PVO_PADDR(sp)); 4234 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 4235 PMAP_UNLOCK(pmap); 4236 4237 CTR4(KTR_PMAP, "%s: va=%#jx, pa=%#jx: refchg=%#jx", 4238 __func__, (uintmax_t)PVO_VADDR(sp), 4239 (uintmax_t)PVO_PADDR(sp), (uintmax_t)refchg); 4240 4241 return (refchg); 4242 } 4243 4244 static int64_t 4245 moea64_sp_clear(struct pvo_entry *pvo, vm_page_t m, uint64_t ptebit) 4246 { 4247 int64_t count, ret; 4248 pmap_t pmap; 4249 4250 count = 0; 4251 pmap = pvo->pvo_pmap; 4252 4253 /* 4254 * Since this reference bit is shared by 4096 4KB pages, it 4255 * should not be cleared every time it is tested. Apply a 4256 * simple "hash" function on the physical page number, the 4257 * virtual superpage number, and the pmap address to select 4258 * one 4KB page out of the 4096 on which testing the 4259 * reference bit will result in clearing that reference bit. 4260 * This function is designed to avoid the selection of the 4261 * same 4KB page for every 16MB page mapping. 4262 * 4263 * Always leave the reference bit of a wired mapping set, as 4264 * the current state of its reference bit won't affect page 4265 * replacement. 4266 */ 4267 if (ptebit == LPTE_REF && (((VM_PAGE_TO_PHYS(m) >> PAGE_SHIFT) ^ 4268 (PVO_VADDR(pvo) >> HPT_SP_SHIFT) ^ (uintptr_t)pmap) & 4269 (HPT_SP_PAGES - 1)) == 0 && (pvo->pvo_vaddr & PVO_WIRED) == 0) { 4270 if ((ret = moea64_sp_pvo_clear(pvo, ptebit)) == -1) 4271 return (-1); 4272 4273 if ((ret & ptebit) != 0) 4274 count++; 4275 4276 /* 4277 * If this page was not selected by the hash function, then assume 4278 * its REF bit was set. 4279 */ 4280 } else if (ptebit == LPTE_REF) { 4281 count++; 4282 4283 /* 4284 * To clear the CHG bit of a single SP page, first it must be demoted. 4285 * But if no CHG bit is set, no bit clear and thus no SP demotion is 4286 * needed. 4287 */ 4288 } else { 4289 CTR4(KTR_PMAP, "%s: ptebit=%#jx, va=%#jx, pa=%#jx", 4290 __func__, (uintmax_t)ptebit, (uintmax_t)PVO_VADDR(pvo), 4291 (uintmax_t)PVO_PADDR(pvo)); 4292 4293 PMAP_LOCK(pmap); 4294 4295 /* 4296 * Make sure SP wasn't demoted/removed before pmap lock 4297 * was acquired. 4298 */ 4299 if (!PVO_IS_SP(pvo) || (pvo->pvo_vaddr & PVO_DEAD) != 0) { 4300 CTR2(KTR_PMAP, "%s: demoted/removed: pa=%#jx", 4301 __func__, (uintmax_t)PVO_PADDR(pvo)); 4302 PMAP_UNLOCK(pmap); 4303 return (-1); 4304 } 4305 4306 ret = moea64_sp_query_locked(pvo, ptebit); 4307 if ((ret & ptebit) != 0) 4308 count++; 4309 else { 4310 PMAP_UNLOCK(pmap); 4311 return (0); 4312 } 4313 4314 moea64_sp_demote(pvo); 4315 moea64_pte_clear(pvo, ptebit); 4316 4317 /* 4318 * Write protect the mapping to a single page so that a 4319 * subsequent write access may repromote. 4320 */ 4321 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 4322 moea64_pvo_protect(pmap, pvo, 4323 pvo->pvo_pte.prot & ~VM_PROT_WRITE); 4324 4325 PMAP_UNLOCK(pmap); 4326 } 4327 4328 return (count); 4329 } 4330