1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_compat.h" 49 #include "opt_kstack_pages.h" 50 51 #include <sys/param.h> 52 #include <sys/kernel.h> 53 #include <sys/conf.h> 54 #include <sys/queue.h> 55 #include <sys/cpuset.h> 56 #include <sys/kerneldump.h> 57 #include <sys/ktr.h> 58 #include <sys/lock.h> 59 #include <sys/msgbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/proc.h> 63 #include <sys/rwlock.h> 64 #include <sys/sched.h> 65 #include <sys/sysctl.h> 66 #include <sys/systm.h> 67 #include <sys/vmmeter.h> 68 #include <sys/smp.h> 69 70 #include <sys/kdb.h> 71 72 #include <dev/ofw/openfirm.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_kern.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 124 125 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 126 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 127 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 128 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 129 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 130 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 131 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 132 133 struct ofw_map { 134 cell_t om_va; 135 cell_t om_len; 136 uint64_t om_pa; 137 cell_t om_mode; 138 }; 139 140 extern unsigned char _etext[]; 141 extern unsigned char _end[]; 142 143 extern void *slbtrap, *slbtrapend; 144 145 /* 146 * Map of physical memory regions. 147 */ 148 static struct mem_region *regions; 149 static struct mem_region *pregions; 150 static u_int phys_avail_count; 151 static int regions_sz, pregions_sz; 152 153 extern void bs_remap_earlyboot(void); 154 155 /* 156 * Lock for the SLB tables. 157 */ 158 struct mtx moea64_slb_mutex; 159 160 /* 161 * PTEG data. 162 */ 163 u_int moea64_pteg_count; 164 u_int moea64_pteg_mask; 165 166 /* 167 * PVO data. 168 */ 169 170 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 171 172 static struct pvo_entry *moea64_bpvo_pool; 173 static int moea64_bpvo_pool_index = 0; 174 static int moea64_bpvo_pool_size = 327680; 175 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 176 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 177 &moea64_bpvo_pool_index, 0, ""); 178 179 #define VSID_NBPW (sizeof(u_int32_t) * 8) 180 #ifdef __powerpc64__ 181 #define NVSIDS (NPMAPS * 16) 182 #define VSID_HASHMASK 0xffffffffUL 183 #else 184 #define NVSIDS NPMAPS 185 #define VSID_HASHMASK 0xfffffUL 186 #endif 187 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 188 189 static boolean_t moea64_initialized = FALSE; 190 191 /* 192 * Statistics. 193 */ 194 u_int moea64_pte_valid = 0; 195 u_int moea64_pte_overflow = 0; 196 u_int moea64_pvo_entries = 0; 197 u_int moea64_pvo_enter_calls = 0; 198 u_int moea64_pvo_remove_calls = 0; 199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 200 &moea64_pte_valid, 0, ""); 201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 202 &moea64_pte_overflow, 0, ""); 203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 204 &moea64_pvo_entries, 0, ""); 205 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 206 &moea64_pvo_enter_calls, 0, ""); 207 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 208 &moea64_pvo_remove_calls, 0, ""); 209 210 vm_offset_t moea64_scratchpage_va[2]; 211 struct pvo_entry *moea64_scratchpage_pvo[2]; 212 struct mtx moea64_scratchpage_mtx; 213 214 uint64_t moea64_large_page_mask = 0; 215 uint64_t moea64_large_page_size = 0; 216 int moea64_large_page_shift = 0; 217 218 /* 219 * PVO calls. 220 */ 221 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 222 struct pvo_head *pvo_head); 223 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 224 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 225 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 226 227 /* 228 * Utility routines. 229 */ 230 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 231 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 232 static void moea64_kremove(mmu_t, vm_offset_t); 233 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 234 vm_paddr_t pa, vm_size_t sz); 235 static void moea64_pmap_init_qpages(void); 236 237 /* 238 * Kernel MMU interface 239 */ 240 void moea64_clear_modify(mmu_t, vm_page_t); 241 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 242 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 243 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 244 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 245 u_int flags, int8_t psind); 246 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 247 vm_prot_t); 248 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 249 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 250 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 251 void moea64_init(mmu_t); 252 boolean_t moea64_is_modified(mmu_t, vm_page_t); 253 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 254 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 255 int moea64_ts_referenced(mmu_t, vm_page_t); 256 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 257 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 258 void moea64_page_init(mmu_t, vm_page_t); 259 int moea64_page_wired_mappings(mmu_t, vm_page_t); 260 void moea64_pinit(mmu_t, pmap_t); 261 void moea64_pinit0(mmu_t, pmap_t); 262 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 263 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 264 void moea64_qremove(mmu_t, vm_offset_t, int); 265 void moea64_release(mmu_t, pmap_t); 266 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 267 void moea64_remove_pages(mmu_t, pmap_t); 268 void moea64_remove_all(mmu_t, vm_page_t); 269 void moea64_remove_write(mmu_t, vm_page_t); 270 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 271 void moea64_zero_page(mmu_t, vm_page_t); 272 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 273 void moea64_activate(mmu_t, struct thread *); 274 void moea64_deactivate(mmu_t, struct thread *); 275 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 276 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 277 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 278 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 279 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 280 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 281 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 282 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 283 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 284 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 285 void **va); 286 void moea64_scan_init(mmu_t mmu); 287 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 288 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 289 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 290 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 291 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 292 int *is_user, vm_offset_t *decoded_addr); 293 294 295 static mmu_method_t moea64_methods[] = { 296 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 297 MMUMETHOD(mmu_copy_page, moea64_copy_page), 298 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 299 MMUMETHOD(mmu_enter, moea64_enter), 300 MMUMETHOD(mmu_enter_object, moea64_enter_object), 301 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 302 MMUMETHOD(mmu_extract, moea64_extract), 303 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 304 MMUMETHOD(mmu_init, moea64_init), 305 MMUMETHOD(mmu_is_modified, moea64_is_modified), 306 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 307 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 308 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 309 MMUMETHOD(mmu_map, moea64_map), 310 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 311 MMUMETHOD(mmu_page_init, moea64_page_init), 312 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 313 MMUMETHOD(mmu_pinit, moea64_pinit), 314 MMUMETHOD(mmu_pinit0, moea64_pinit0), 315 MMUMETHOD(mmu_protect, moea64_protect), 316 MMUMETHOD(mmu_qenter, moea64_qenter), 317 MMUMETHOD(mmu_qremove, moea64_qremove), 318 MMUMETHOD(mmu_release, moea64_release), 319 MMUMETHOD(mmu_remove, moea64_remove), 320 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 321 MMUMETHOD(mmu_remove_all, moea64_remove_all), 322 MMUMETHOD(mmu_remove_write, moea64_remove_write), 323 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 324 MMUMETHOD(mmu_unwire, moea64_unwire), 325 MMUMETHOD(mmu_zero_page, moea64_zero_page), 326 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 327 MMUMETHOD(mmu_activate, moea64_activate), 328 MMUMETHOD(mmu_deactivate, moea64_deactivate), 329 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 330 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 331 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 332 333 /* Internal interfaces */ 334 MMUMETHOD(mmu_mapdev, moea64_mapdev), 335 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 336 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 337 MMUMETHOD(mmu_kextract, moea64_kextract), 338 MMUMETHOD(mmu_kenter, moea64_kenter), 339 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 340 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 341 MMUMETHOD(mmu_scan_init, moea64_scan_init), 342 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 343 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 344 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 345 346 { 0, 0 } 347 }; 348 349 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 350 351 static struct pvo_head * 352 vm_page_to_pvoh(vm_page_t m) 353 { 354 355 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 356 return (&m->md.mdpg_pvoh); 357 } 358 359 static struct pvo_entry * 360 alloc_pvo_entry(int bootstrap) 361 { 362 struct pvo_entry *pvo; 363 364 if (!moea64_initialized || bootstrap) { 365 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 366 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 367 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 368 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 369 } 370 pvo = &moea64_bpvo_pool[ 371 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 372 bzero(pvo, sizeof(*pvo)); 373 pvo->pvo_vaddr = PVO_BOOTSTRAP; 374 } else { 375 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 376 bzero(pvo, sizeof(*pvo)); 377 } 378 379 return (pvo); 380 } 381 382 383 static void 384 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 385 { 386 uint64_t vsid; 387 uint64_t hash; 388 int shift; 389 390 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 391 392 pvo->pvo_pmap = pmap; 393 va &= ~ADDR_POFF; 394 pvo->pvo_vaddr |= va; 395 vsid = va_to_vsid(pmap, va); 396 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 397 | (vsid << 16); 398 399 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 400 ADDR_PIDX_SHFT; 401 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 402 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 403 } 404 405 static void 406 free_pvo_entry(struct pvo_entry *pvo) 407 { 408 409 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 410 uma_zfree(moea64_pvo_zone, pvo); 411 } 412 413 void 414 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 415 { 416 417 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 418 LPTE_AVPN_MASK; 419 lpte->pte_hi |= LPTE_VALID; 420 421 if (pvo->pvo_vaddr & PVO_LARGE) 422 lpte->pte_hi |= LPTE_BIG; 423 if (pvo->pvo_vaddr & PVO_WIRED) 424 lpte->pte_hi |= LPTE_WIRED; 425 if (pvo->pvo_vaddr & PVO_HID) 426 lpte->pte_hi |= LPTE_HID; 427 428 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 429 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 430 lpte->pte_lo |= LPTE_BW; 431 else 432 lpte->pte_lo |= LPTE_BR; 433 434 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 435 lpte->pte_lo |= LPTE_NOEXEC; 436 } 437 438 static __inline uint64_t 439 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 440 { 441 uint64_t pte_lo; 442 int i; 443 444 if (ma != VM_MEMATTR_DEFAULT) { 445 switch (ma) { 446 case VM_MEMATTR_UNCACHEABLE: 447 return (LPTE_I | LPTE_G); 448 case VM_MEMATTR_CACHEABLE: 449 return (LPTE_M); 450 case VM_MEMATTR_WRITE_COMBINING: 451 case VM_MEMATTR_WRITE_BACK: 452 case VM_MEMATTR_PREFETCHABLE: 453 return (LPTE_I); 454 case VM_MEMATTR_WRITE_THROUGH: 455 return (LPTE_W | LPTE_M); 456 } 457 } 458 459 /* 460 * Assume the page is cache inhibited and access is guarded unless 461 * it's in our available memory array. 462 */ 463 pte_lo = LPTE_I | LPTE_G; 464 for (i = 0; i < pregions_sz; i++) { 465 if ((pa >= pregions[i].mr_start) && 466 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 467 pte_lo &= ~(LPTE_I | LPTE_G); 468 pte_lo |= LPTE_M; 469 break; 470 } 471 } 472 473 return pte_lo; 474 } 475 476 /* 477 * Quick sort callout for comparing memory regions. 478 */ 479 static int om_cmp(const void *a, const void *b); 480 481 static int 482 om_cmp(const void *a, const void *b) 483 { 484 const struct ofw_map *mapa; 485 const struct ofw_map *mapb; 486 487 mapa = a; 488 mapb = b; 489 if (mapa->om_pa < mapb->om_pa) 490 return (-1); 491 else if (mapa->om_pa > mapb->om_pa) 492 return (1); 493 else 494 return (0); 495 } 496 497 static void 498 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 499 { 500 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 501 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 502 struct pvo_entry *pvo; 503 register_t msr; 504 vm_offset_t off; 505 vm_paddr_t pa_base; 506 int i, j; 507 508 bzero(translations, sz); 509 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 510 sizeof(acells)); 511 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 512 panic("moea64_bootstrap: can't get ofw translations"); 513 514 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 515 sz /= sizeof(cell_t); 516 for (i = 0, j = 0; i < sz; j++) { 517 translations[j].om_va = trans_cells[i++]; 518 translations[j].om_len = trans_cells[i++]; 519 translations[j].om_pa = trans_cells[i++]; 520 if (acells == 2) { 521 translations[j].om_pa <<= 32; 522 translations[j].om_pa |= trans_cells[i++]; 523 } 524 translations[j].om_mode = trans_cells[i++]; 525 } 526 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 527 i, sz)); 528 529 sz = j; 530 qsort(translations, sz, sizeof (*translations), om_cmp); 531 532 for (i = 0; i < sz; i++) { 533 pa_base = translations[i].om_pa; 534 #ifndef __powerpc64__ 535 if ((translations[i].om_pa >> 32) != 0) 536 panic("OFW translations above 32-bit boundary!"); 537 #endif 538 539 if (pa_base % PAGE_SIZE) 540 panic("OFW translation not page-aligned (phys)!"); 541 if (translations[i].om_va % PAGE_SIZE) 542 panic("OFW translation not page-aligned (virt)!"); 543 544 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 545 pa_base, translations[i].om_va, translations[i].om_len); 546 547 /* Now enter the pages for this mapping */ 548 549 DISABLE_TRANS(msr); 550 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 551 /* If this address is direct-mapped, skip remapping */ 552 if (hw_direct_map && 553 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 554 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 555 == LPTE_M) 556 continue; 557 558 PMAP_LOCK(kernel_pmap); 559 pvo = moea64_pvo_find_va(kernel_pmap, 560 translations[i].om_va + off); 561 PMAP_UNLOCK(kernel_pmap); 562 if (pvo != NULL) 563 continue; 564 565 moea64_kenter(mmup, translations[i].om_va + off, 566 pa_base + off); 567 } 568 ENABLE_TRANS(msr); 569 } 570 } 571 572 #ifdef __powerpc64__ 573 static void 574 moea64_probe_large_page(void) 575 { 576 uint16_t pvr = mfpvr() >> 16; 577 578 switch (pvr) { 579 case IBM970: 580 case IBM970FX: 581 case IBM970MP: 582 powerpc_sync(); isync(); 583 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 584 powerpc_sync(); isync(); 585 586 /* FALLTHROUGH */ 587 default: 588 if (moea64_large_page_size == 0) { 589 moea64_large_page_size = 0x1000000; /* 16 MB */ 590 moea64_large_page_shift = 24; 591 } 592 } 593 594 moea64_large_page_mask = moea64_large_page_size - 1; 595 } 596 597 static void 598 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 599 { 600 struct slb *cache; 601 struct slb entry; 602 uint64_t esid, slbe; 603 uint64_t i; 604 605 cache = PCPU_GET(aim.slb); 606 esid = va >> ADDR_SR_SHFT; 607 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 608 609 for (i = 0; i < 64; i++) { 610 if (cache[i].slbe == (slbe | i)) 611 return; 612 } 613 614 entry.slbe = slbe; 615 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 616 if (large) 617 entry.slbv |= SLBV_L; 618 619 slb_insert_kernel(entry.slbe, entry.slbv); 620 } 621 #endif 622 623 static void 624 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 625 vm_offset_t kernelend) 626 { 627 struct pvo_entry *pvo; 628 register_t msr; 629 vm_paddr_t pa; 630 vm_offset_t size, off; 631 uint64_t pte_lo; 632 int i; 633 634 if (moea64_large_page_size == 0) 635 hw_direct_map = 0; 636 637 DISABLE_TRANS(msr); 638 if (hw_direct_map) { 639 PMAP_LOCK(kernel_pmap); 640 for (i = 0; i < pregions_sz; i++) { 641 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 642 pregions[i].mr_size; pa += moea64_large_page_size) { 643 pte_lo = LPTE_M; 644 645 pvo = alloc_pvo_entry(1 /* bootstrap */); 646 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 647 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 648 649 /* 650 * Set memory access as guarded if prefetch within 651 * the page could exit the available physmem area. 652 */ 653 if (pa & moea64_large_page_mask) { 654 pa &= moea64_large_page_mask; 655 pte_lo |= LPTE_G; 656 } 657 if (pa + moea64_large_page_size > 658 pregions[i].mr_start + pregions[i].mr_size) 659 pte_lo |= LPTE_G; 660 661 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 662 VM_PROT_EXECUTE; 663 pvo->pvo_pte.pa = pa | pte_lo; 664 moea64_pvo_enter(mmup, pvo, NULL); 665 } 666 } 667 PMAP_UNLOCK(kernel_pmap); 668 } 669 670 /* 671 * Make sure the kernel and BPVO pool stay mapped on systems either 672 * without a direct map or on which the kernel is not already executing 673 * out of the direct-mapped region. 674 */ 675 676 if (!hw_direct_map || kernelstart < DMAP_BASE_ADDRESS) { 677 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 678 pa += PAGE_SIZE) 679 moea64_kenter(mmup, pa, pa); 680 } 681 682 if (!hw_direct_map) { 683 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 684 off = (vm_offset_t)(moea64_bpvo_pool); 685 for (pa = off; pa < off + size; pa += PAGE_SIZE) 686 moea64_kenter(mmup, pa, pa); 687 } 688 ENABLE_TRANS(msr); 689 690 /* 691 * Allow user to override unmapped_buf_allowed for testing. 692 * XXXKIB Only direct map implementation was tested. 693 */ 694 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 695 &unmapped_buf_allowed)) 696 unmapped_buf_allowed = hw_direct_map; 697 } 698 699 void 700 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 701 { 702 int i, j; 703 vm_size_t physsz, hwphyssz; 704 vm_paddr_t kernelphysstart, kernelphysend; 705 706 #ifndef __powerpc64__ 707 /* We don't have a direct map since there is no BAT */ 708 hw_direct_map = 0; 709 710 /* Make sure battable is zero, since we have no BAT */ 711 for (i = 0; i < 16; i++) { 712 battable[i].batu = 0; 713 battable[i].batl = 0; 714 } 715 #else 716 moea64_probe_large_page(); 717 718 /* Use a direct map if we have large page support */ 719 if (moea64_large_page_size > 0) 720 hw_direct_map = 1; 721 else 722 hw_direct_map = 0; 723 724 /* Install trap handlers for SLBs */ 725 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 726 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 727 __syncicache((void *)EXC_DSE, 0x80); 728 __syncicache((void *)EXC_ISE, 0x80); 729 #endif 730 731 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 732 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 733 734 /* Get physical memory regions from firmware */ 735 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 736 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 737 738 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 739 panic("moea64_bootstrap: phys_avail too small"); 740 741 phys_avail_count = 0; 742 physsz = 0; 743 hwphyssz = 0; 744 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 745 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 746 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 747 regions[i].mr_start, regions[i].mr_start + 748 regions[i].mr_size, regions[i].mr_size); 749 if (hwphyssz != 0 && 750 (physsz + regions[i].mr_size) >= hwphyssz) { 751 if (physsz < hwphyssz) { 752 phys_avail[j] = regions[i].mr_start; 753 phys_avail[j + 1] = regions[i].mr_start + 754 hwphyssz - physsz; 755 physsz = hwphyssz; 756 phys_avail_count++; 757 } 758 break; 759 } 760 phys_avail[j] = regions[i].mr_start; 761 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 762 phys_avail_count++; 763 physsz += regions[i].mr_size; 764 } 765 766 /* Check for overlap with the kernel and exception vectors */ 767 for (j = 0; j < 2*phys_avail_count; j+=2) { 768 if (phys_avail[j] < EXC_LAST) 769 phys_avail[j] += EXC_LAST; 770 771 if (kernelphysstart >= phys_avail[j] && 772 kernelphysstart < phys_avail[j+1]) { 773 if (kernelphysend < phys_avail[j+1]) { 774 phys_avail[2*phys_avail_count] = 775 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 776 phys_avail[2*phys_avail_count + 1] = 777 phys_avail[j+1]; 778 phys_avail_count++; 779 } 780 781 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 782 } 783 784 if (kernelphysend >= phys_avail[j] && 785 kernelphysend < phys_avail[j+1]) { 786 if (kernelphysstart > phys_avail[j]) { 787 phys_avail[2*phys_avail_count] = phys_avail[j]; 788 phys_avail[2*phys_avail_count + 1] = 789 kernelphysstart & ~PAGE_MASK; 790 phys_avail_count++; 791 } 792 793 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 794 PAGE_SIZE; 795 } 796 } 797 798 physmem = btoc(physsz); 799 800 #ifdef PTEGCOUNT 801 moea64_pteg_count = PTEGCOUNT; 802 #else 803 moea64_pteg_count = 0x1000; 804 805 while (moea64_pteg_count < physmem) 806 moea64_pteg_count <<= 1; 807 808 moea64_pteg_count >>= 1; 809 #endif /* PTEGCOUNT */ 810 } 811 812 void 813 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 814 { 815 int i; 816 817 /* 818 * Set PTEG mask 819 */ 820 moea64_pteg_mask = moea64_pteg_count - 1; 821 822 /* 823 * Initialize SLB table lock and page locks 824 */ 825 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 826 for (i = 0; i < PV_LOCK_COUNT; i++) 827 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 828 829 /* 830 * Initialise the bootstrap pvo pool. 831 */ 832 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 833 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 834 moea64_bpvo_pool_index = 0; 835 836 /* Place at address usable through the direct map */ 837 if (hw_direct_map) 838 moea64_bpvo_pool = (struct pvo_entry *) 839 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 840 841 /* 842 * Make sure kernel vsid is allocated as well as VSID 0. 843 */ 844 #ifndef __powerpc64__ 845 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 846 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 847 moea64_vsid_bitmap[0] |= 1; 848 #endif 849 850 /* 851 * Initialize the kernel pmap (which is statically allocated). 852 */ 853 #ifdef __powerpc64__ 854 for (i = 0; i < 64; i++) { 855 pcpup->pc_aim.slb[i].slbv = 0; 856 pcpup->pc_aim.slb[i].slbe = 0; 857 } 858 #else 859 for (i = 0; i < 16; i++) 860 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 861 #endif 862 863 kernel_pmap->pmap_phys = kernel_pmap; 864 CPU_FILL(&kernel_pmap->pm_active); 865 RB_INIT(&kernel_pmap->pmap_pvo); 866 867 PMAP_LOCK_INIT(kernel_pmap); 868 869 /* 870 * Now map in all the other buffers we allocated earlier 871 */ 872 873 moea64_setup_direct_map(mmup, kernelstart, kernelend); 874 } 875 876 void 877 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 878 { 879 ihandle_t mmui; 880 phandle_t chosen; 881 phandle_t mmu; 882 ssize_t sz; 883 int i; 884 vm_offset_t pa, va; 885 void *dpcpu; 886 887 /* 888 * Set up the Open Firmware pmap and add its mappings if not in real 889 * mode. 890 */ 891 892 chosen = OF_finddevice("/chosen"); 893 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 894 mmu = OF_instance_to_package(mmui); 895 if (mmu == -1 || 896 (sz = OF_getproplen(mmu, "translations")) == -1) 897 sz = 0; 898 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 899 panic("moea64_bootstrap: too many ofw translations"); 900 901 if (sz > 0) 902 moea64_add_ofw_mappings(mmup, mmu, sz); 903 } 904 905 /* 906 * Calculate the last available physical address. 907 */ 908 Maxmem = 0; 909 for (i = 0; phys_avail[i + 2] != 0; i += 2) 910 Maxmem = max(Maxmem, powerpc_btop(phys_avail[i + 1])); 911 912 /* 913 * Initialize MMU. 914 */ 915 MMU_CPU_BOOTSTRAP(mmup,0); 916 mtmsr(mfmsr() | PSL_DR | PSL_IR); 917 pmap_bootstrapped++; 918 919 /* 920 * Set the start and end of kva. 921 */ 922 virtual_avail = VM_MIN_KERNEL_ADDRESS; 923 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 924 925 /* 926 * Map the entire KVA range into the SLB. We must not fault there. 927 */ 928 #ifdef __powerpc64__ 929 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 930 moea64_bootstrap_slb_prefault(va, 0); 931 #endif 932 933 /* 934 * Remap any early IO mappings (console framebuffer, etc.) 935 */ 936 bs_remap_earlyboot(); 937 938 /* 939 * Figure out how far we can extend virtual_end into segment 16 940 * without running into existing mappings. Segment 16 is guaranteed 941 * to contain neither RAM nor devices (at least on Apple hardware), 942 * but will generally contain some OFW mappings we should not 943 * step on. 944 */ 945 946 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 947 PMAP_LOCK(kernel_pmap); 948 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 949 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 950 virtual_end += PAGE_SIZE; 951 PMAP_UNLOCK(kernel_pmap); 952 #endif 953 954 /* 955 * Allocate a kernel stack with a guard page for thread0 and map it 956 * into the kernel page map. 957 */ 958 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 959 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 960 virtual_avail = va + kstack_pages * PAGE_SIZE; 961 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 962 thread0.td_kstack = va; 963 thread0.td_kstack_pages = kstack_pages; 964 for (i = 0; i < kstack_pages; i++) { 965 moea64_kenter(mmup, va, pa); 966 pa += PAGE_SIZE; 967 va += PAGE_SIZE; 968 } 969 970 /* 971 * Allocate virtual address space for the message buffer. 972 */ 973 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 974 msgbufp = (struct msgbuf *)virtual_avail; 975 va = virtual_avail; 976 virtual_avail += round_page(msgbufsize); 977 while (va < virtual_avail) { 978 moea64_kenter(mmup, va, pa); 979 pa += PAGE_SIZE; 980 va += PAGE_SIZE; 981 } 982 983 /* 984 * Allocate virtual address space for the dynamic percpu area. 985 */ 986 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 987 dpcpu = (void *)virtual_avail; 988 va = virtual_avail; 989 virtual_avail += DPCPU_SIZE; 990 while (va < virtual_avail) { 991 moea64_kenter(mmup, va, pa); 992 pa += PAGE_SIZE; 993 va += PAGE_SIZE; 994 } 995 dpcpu_init(dpcpu, curcpu); 996 997 /* 998 * Allocate some things for page zeroing. We put this directly 999 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1000 * of the PVO book-keeping or other parts of the VM system 1001 * from even knowing that this hack exists. 1002 */ 1003 1004 if (!hw_direct_map) { 1005 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1006 MTX_DEF); 1007 for (i = 0; i < 2; i++) { 1008 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1009 virtual_end -= PAGE_SIZE; 1010 1011 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1012 1013 PMAP_LOCK(kernel_pmap); 1014 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1015 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1016 PMAP_UNLOCK(kernel_pmap); 1017 } 1018 } 1019 } 1020 1021 static void 1022 moea64_pmap_init_qpages(void) 1023 { 1024 struct pcpu *pc; 1025 int i; 1026 1027 if (hw_direct_map) 1028 return; 1029 1030 CPU_FOREACH(i) { 1031 pc = pcpu_find(i); 1032 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1033 if (pc->pc_qmap_addr == 0) 1034 panic("pmap_init_qpages: unable to allocate KVA"); 1035 PMAP_LOCK(kernel_pmap); 1036 pc->pc_aim.qmap_pvo = 1037 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1038 PMAP_UNLOCK(kernel_pmap); 1039 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1040 } 1041 } 1042 1043 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1044 1045 /* 1046 * Activate a user pmap. This mostly involves setting some non-CPU 1047 * state. 1048 */ 1049 void 1050 moea64_activate(mmu_t mmu, struct thread *td) 1051 { 1052 pmap_t pm; 1053 1054 pm = &td->td_proc->p_vmspace->vm_pmap; 1055 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1056 1057 #ifdef __powerpc64__ 1058 PCPU_SET(aim.userslb, pm->pm_slb); 1059 __asm __volatile("slbmte %0, %1; isync" :: 1060 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1061 #else 1062 PCPU_SET(curpmap, pm->pmap_phys); 1063 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1064 #endif 1065 } 1066 1067 void 1068 moea64_deactivate(mmu_t mmu, struct thread *td) 1069 { 1070 pmap_t pm; 1071 1072 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1073 1074 pm = &td->td_proc->p_vmspace->vm_pmap; 1075 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1076 #ifdef __powerpc64__ 1077 PCPU_SET(aim.userslb, NULL); 1078 #else 1079 PCPU_SET(curpmap, NULL); 1080 #endif 1081 } 1082 1083 void 1084 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1085 { 1086 struct pvo_entry key, *pvo; 1087 vm_page_t m; 1088 int64_t refchg; 1089 1090 key.pvo_vaddr = sva; 1091 PMAP_LOCK(pm); 1092 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1093 pvo != NULL && PVO_VADDR(pvo) < eva; 1094 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1095 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1096 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1097 pvo); 1098 pvo->pvo_vaddr &= ~PVO_WIRED; 1099 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1100 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1101 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1102 if (refchg < 0) 1103 refchg = LPTE_CHG; 1104 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1105 1106 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1107 if (refchg & LPTE_CHG) 1108 vm_page_dirty(m); 1109 if (refchg & LPTE_REF) 1110 vm_page_aflag_set(m, PGA_REFERENCED); 1111 } 1112 pm->pm_stats.wired_count--; 1113 } 1114 PMAP_UNLOCK(pm); 1115 } 1116 1117 /* 1118 * This goes through and sets the physical address of our 1119 * special scratch PTE to the PA we want to zero or copy. Because 1120 * of locking issues (this can get called in pvo_enter() by 1121 * the UMA allocator), we can't use most other utility functions here 1122 */ 1123 1124 static __inline 1125 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1126 1127 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1128 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1129 1130 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1131 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1132 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1133 MOEA64_PTE_INVALIDATE); 1134 isync(); 1135 } 1136 1137 void 1138 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1139 { 1140 vm_offset_t dst; 1141 vm_offset_t src; 1142 1143 dst = VM_PAGE_TO_PHYS(mdst); 1144 src = VM_PAGE_TO_PHYS(msrc); 1145 1146 if (hw_direct_map) { 1147 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1148 PAGE_SIZE); 1149 } else { 1150 mtx_lock(&moea64_scratchpage_mtx); 1151 1152 moea64_set_scratchpage_pa(mmu, 0, src); 1153 moea64_set_scratchpage_pa(mmu, 1, dst); 1154 1155 bcopy((void *)moea64_scratchpage_va[0], 1156 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1157 1158 mtx_unlock(&moea64_scratchpage_mtx); 1159 } 1160 } 1161 1162 static inline void 1163 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1164 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1165 { 1166 void *a_cp, *b_cp; 1167 vm_offset_t a_pg_offset, b_pg_offset; 1168 int cnt; 1169 1170 while (xfersize > 0) { 1171 a_pg_offset = a_offset & PAGE_MASK; 1172 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1173 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1174 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1175 a_pg_offset; 1176 b_pg_offset = b_offset & PAGE_MASK; 1177 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1178 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1179 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1180 b_pg_offset; 1181 bcopy(a_cp, b_cp, cnt); 1182 a_offset += cnt; 1183 b_offset += cnt; 1184 xfersize -= cnt; 1185 } 1186 } 1187 1188 static inline void 1189 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1190 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1191 { 1192 void *a_cp, *b_cp; 1193 vm_offset_t a_pg_offset, b_pg_offset; 1194 int cnt; 1195 1196 mtx_lock(&moea64_scratchpage_mtx); 1197 while (xfersize > 0) { 1198 a_pg_offset = a_offset & PAGE_MASK; 1199 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1200 moea64_set_scratchpage_pa(mmu, 0, 1201 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1202 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1203 b_pg_offset = b_offset & PAGE_MASK; 1204 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1205 moea64_set_scratchpage_pa(mmu, 1, 1206 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1207 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1208 bcopy(a_cp, b_cp, cnt); 1209 a_offset += cnt; 1210 b_offset += cnt; 1211 xfersize -= cnt; 1212 } 1213 mtx_unlock(&moea64_scratchpage_mtx); 1214 } 1215 1216 void 1217 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1218 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1219 { 1220 1221 if (hw_direct_map) { 1222 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1223 xfersize); 1224 } else { 1225 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1226 xfersize); 1227 } 1228 } 1229 1230 void 1231 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1232 { 1233 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1234 1235 if (size + off > PAGE_SIZE) 1236 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1237 1238 if (hw_direct_map) { 1239 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1240 } else { 1241 mtx_lock(&moea64_scratchpage_mtx); 1242 moea64_set_scratchpage_pa(mmu, 0, pa); 1243 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1244 mtx_unlock(&moea64_scratchpage_mtx); 1245 } 1246 } 1247 1248 /* 1249 * Zero a page of physical memory by temporarily mapping it 1250 */ 1251 void 1252 moea64_zero_page(mmu_t mmu, vm_page_t m) 1253 { 1254 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1255 vm_offset_t va, off; 1256 1257 if (!hw_direct_map) { 1258 mtx_lock(&moea64_scratchpage_mtx); 1259 1260 moea64_set_scratchpage_pa(mmu, 0, pa); 1261 va = moea64_scratchpage_va[0]; 1262 } else { 1263 va = PHYS_TO_DMAP(pa); 1264 } 1265 1266 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1267 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1268 1269 if (!hw_direct_map) 1270 mtx_unlock(&moea64_scratchpage_mtx); 1271 } 1272 1273 vm_offset_t 1274 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1275 { 1276 struct pvo_entry *pvo; 1277 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1278 1279 if (hw_direct_map) 1280 return (PHYS_TO_DMAP(pa)); 1281 1282 /* 1283 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1284 * a critical section and access the PCPU data like on i386. 1285 * Instead, pin the thread and grab the PCPU lock to prevent 1286 * a preempting thread from using the same PCPU data. 1287 */ 1288 sched_pin(); 1289 1290 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1291 pvo = PCPU_GET(aim.qmap_pvo); 1292 1293 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1294 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1295 (uint64_t)pa; 1296 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1297 isync(); 1298 1299 return (PCPU_GET(qmap_addr)); 1300 } 1301 1302 void 1303 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1304 { 1305 if (hw_direct_map) 1306 return; 1307 1308 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1309 KASSERT(PCPU_GET(qmap_addr) == addr, 1310 ("moea64_quick_remove_page: invalid address")); 1311 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1312 sched_unpin(); 1313 } 1314 1315 /* 1316 * Map the given physical page at the specified virtual address in the 1317 * target pmap with the protection requested. If specified the page 1318 * will be wired down. 1319 */ 1320 1321 int 1322 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1323 vm_prot_t prot, u_int flags, int8_t psind) 1324 { 1325 struct pvo_entry *pvo, *oldpvo; 1326 struct pvo_head *pvo_head; 1327 uint64_t pte_lo; 1328 int error; 1329 1330 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1331 VM_OBJECT_ASSERT_LOCKED(m->object); 1332 1333 pvo = alloc_pvo_entry(0); 1334 pvo->pvo_pmap = NULL; /* to be filled in later */ 1335 pvo->pvo_pte.prot = prot; 1336 1337 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1338 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1339 1340 if ((flags & PMAP_ENTER_WIRED) != 0) 1341 pvo->pvo_vaddr |= PVO_WIRED; 1342 1343 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1344 pvo_head = NULL; 1345 } else { 1346 pvo_head = &m->md.mdpg_pvoh; 1347 pvo->pvo_vaddr |= PVO_MANAGED; 1348 } 1349 1350 for (;;) { 1351 PV_PAGE_LOCK(m); 1352 PMAP_LOCK(pmap); 1353 if (pvo->pvo_pmap == NULL) 1354 init_pvo_entry(pvo, pmap, va); 1355 if (prot & VM_PROT_WRITE) 1356 if (pmap_bootstrapped && 1357 (m->oflags & VPO_UNMANAGED) == 0) 1358 vm_page_aflag_set(m, PGA_WRITEABLE); 1359 1360 oldpvo = moea64_pvo_find_va(pmap, va); 1361 if (oldpvo != NULL) { 1362 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1363 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1364 oldpvo->pvo_pte.prot == prot) { 1365 /* Identical mapping already exists */ 1366 error = 0; 1367 1368 /* If not in page table, reinsert it */ 1369 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1370 moea64_pte_overflow--; 1371 MOEA64_PTE_INSERT(mmu, oldpvo); 1372 } 1373 1374 /* Then just clean up and go home */ 1375 PV_PAGE_UNLOCK(m); 1376 PMAP_UNLOCK(pmap); 1377 free_pvo_entry(pvo); 1378 break; 1379 } 1380 1381 /* Otherwise, need to kill it first */ 1382 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1383 "mapping does not match new mapping")); 1384 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1385 } 1386 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1387 PV_PAGE_UNLOCK(m); 1388 PMAP_UNLOCK(pmap); 1389 1390 /* Free any dead pages */ 1391 if (oldpvo != NULL) { 1392 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1393 moea64_pvo_remove_from_page(mmu, oldpvo); 1394 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1395 free_pvo_entry(oldpvo); 1396 } 1397 1398 if (error != ENOMEM) 1399 break; 1400 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1401 return (KERN_RESOURCE_SHORTAGE); 1402 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1403 vm_wait(NULL); 1404 } 1405 1406 /* 1407 * Flush the page from the instruction cache if this page is 1408 * mapped executable and cacheable. 1409 */ 1410 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1411 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1412 vm_page_aflag_set(m, PGA_EXECUTABLE); 1413 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1414 } 1415 return (KERN_SUCCESS); 1416 } 1417 1418 static void 1419 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1420 vm_size_t sz) 1421 { 1422 1423 /* 1424 * This is much trickier than on older systems because 1425 * we can't sync the icache on physical addresses directly 1426 * without a direct map. Instead we check a couple of cases 1427 * where the memory is already mapped in and, failing that, 1428 * use the same trick we use for page zeroing to create 1429 * a temporary mapping for this physical address. 1430 */ 1431 1432 if (!pmap_bootstrapped) { 1433 /* 1434 * If PMAP is not bootstrapped, we are likely to be 1435 * in real mode. 1436 */ 1437 __syncicache((void *)(uintptr_t)pa, sz); 1438 } else if (pmap == kernel_pmap) { 1439 __syncicache((void *)va, sz); 1440 } else if (hw_direct_map) { 1441 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1442 } else { 1443 /* Use the scratch page to set up a temp mapping */ 1444 1445 mtx_lock(&moea64_scratchpage_mtx); 1446 1447 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1448 __syncicache((void *)(moea64_scratchpage_va[1] + 1449 (va & ADDR_POFF)), sz); 1450 1451 mtx_unlock(&moea64_scratchpage_mtx); 1452 } 1453 } 1454 1455 /* 1456 * Maps a sequence of resident pages belonging to the same object. 1457 * The sequence begins with the given page m_start. This page is 1458 * mapped at the given virtual address start. Each subsequent page is 1459 * mapped at a virtual address that is offset from start by the same 1460 * amount as the page is offset from m_start within the object. The 1461 * last page in the sequence is the page with the largest offset from 1462 * m_start that can be mapped at a virtual address less than the given 1463 * virtual address end. Not every virtual page between start and end 1464 * is mapped; only those for which a resident page exists with the 1465 * corresponding offset from m_start are mapped. 1466 */ 1467 void 1468 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1469 vm_page_t m_start, vm_prot_t prot) 1470 { 1471 vm_page_t m; 1472 vm_pindex_t diff, psize; 1473 1474 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1475 1476 psize = atop(end - start); 1477 m = m_start; 1478 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1479 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1480 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1481 m = TAILQ_NEXT(m, listq); 1482 } 1483 } 1484 1485 void 1486 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1487 vm_prot_t prot) 1488 { 1489 1490 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1491 PMAP_ENTER_NOSLEEP, 0); 1492 } 1493 1494 vm_paddr_t 1495 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1496 { 1497 struct pvo_entry *pvo; 1498 vm_paddr_t pa; 1499 1500 PMAP_LOCK(pm); 1501 pvo = moea64_pvo_find_va(pm, va); 1502 if (pvo == NULL) 1503 pa = 0; 1504 else 1505 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1506 PMAP_UNLOCK(pm); 1507 1508 return (pa); 1509 } 1510 1511 /* 1512 * Atomically extract and hold the physical page with the given 1513 * pmap and virtual address pair if that mapping permits the given 1514 * protection. 1515 */ 1516 vm_page_t 1517 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1518 { 1519 struct pvo_entry *pvo; 1520 vm_page_t m; 1521 vm_paddr_t pa; 1522 1523 m = NULL; 1524 pa = 0; 1525 PMAP_LOCK(pmap); 1526 retry: 1527 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1528 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1529 if (vm_page_pa_tryrelock(pmap, 1530 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1531 goto retry; 1532 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1533 vm_page_hold(m); 1534 } 1535 PA_UNLOCK_COND(pa); 1536 PMAP_UNLOCK(pmap); 1537 return (m); 1538 } 1539 1540 static mmu_t installed_mmu; 1541 1542 static void * 1543 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1544 uint8_t *flags, int wait) 1545 { 1546 struct pvo_entry *pvo; 1547 vm_offset_t va; 1548 vm_page_t m; 1549 int needed_lock; 1550 1551 /* 1552 * This entire routine is a horrible hack to avoid bothering kmem 1553 * for new KVA addresses. Because this can get called from inside 1554 * kmem allocation routines, calling kmem for a new address here 1555 * can lead to multiply locking non-recursive mutexes. 1556 */ 1557 1558 *flags = UMA_SLAB_PRIV; 1559 needed_lock = !PMAP_LOCKED(kernel_pmap); 1560 1561 m = vm_page_alloc_domain(NULL, 0, domain, 1562 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1563 if (m == NULL) 1564 return (NULL); 1565 1566 va = VM_PAGE_TO_PHYS(m); 1567 1568 pvo = alloc_pvo_entry(1 /* bootstrap */); 1569 1570 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1571 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1572 1573 if (needed_lock) 1574 PMAP_LOCK(kernel_pmap); 1575 1576 init_pvo_entry(pvo, kernel_pmap, va); 1577 pvo->pvo_vaddr |= PVO_WIRED; 1578 1579 moea64_pvo_enter(installed_mmu, pvo, NULL); 1580 1581 if (needed_lock) 1582 PMAP_UNLOCK(kernel_pmap); 1583 1584 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1585 bzero((void *)va, PAGE_SIZE); 1586 1587 return (void *)va; 1588 } 1589 1590 extern int elf32_nxstack; 1591 1592 void 1593 moea64_init(mmu_t mmu) 1594 { 1595 1596 CTR0(KTR_PMAP, "moea64_init"); 1597 1598 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1599 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1600 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1601 1602 if (!hw_direct_map) { 1603 installed_mmu = mmu; 1604 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1605 } 1606 1607 #ifdef COMPAT_FREEBSD32 1608 elf32_nxstack = 1; 1609 #endif 1610 1611 moea64_initialized = TRUE; 1612 } 1613 1614 boolean_t 1615 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1616 { 1617 1618 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1619 ("moea64_is_referenced: page %p is not managed", m)); 1620 1621 return (moea64_query_bit(mmu, m, LPTE_REF)); 1622 } 1623 1624 boolean_t 1625 moea64_is_modified(mmu_t mmu, vm_page_t m) 1626 { 1627 1628 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1629 ("moea64_is_modified: page %p is not managed", m)); 1630 1631 /* 1632 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1633 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1634 * is clear, no PTEs can have LPTE_CHG set. 1635 */ 1636 VM_OBJECT_ASSERT_LOCKED(m->object); 1637 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1638 return (FALSE); 1639 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1640 } 1641 1642 boolean_t 1643 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1644 { 1645 struct pvo_entry *pvo; 1646 boolean_t rv = TRUE; 1647 1648 PMAP_LOCK(pmap); 1649 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1650 if (pvo != NULL) 1651 rv = FALSE; 1652 PMAP_UNLOCK(pmap); 1653 return (rv); 1654 } 1655 1656 void 1657 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1658 { 1659 1660 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1661 ("moea64_clear_modify: page %p is not managed", m)); 1662 VM_OBJECT_ASSERT_WLOCKED(m->object); 1663 KASSERT(!vm_page_xbusied(m), 1664 ("moea64_clear_modify: page %p is exclusive busied", m)); 1665 1666 /* 1667 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1668 * set. If the object containing the page is locked and the page is 1669 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1670 */ 1671 if ((m->aflags & PGA_WRITEABLE) == 0) 1672 return; 1673 moea64_clear_bit(mmu, m, LPTE_CHG); 1674 } 1675 1676 /* 1677 * Clear the write and modified bits in each of the given page's mappings. 1678 */ 1679 void 1680 moea64_remove_write(mmu_t mmu, vm_page_t m) 1681 { 1682 struct pvo_entry *pvo; 1683 int64_t refchg, ret; 1684 pmap_t pmap; 1685 1686 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1687 ("moea64_remove_write: page %p is not managed", m)); 1688 1689 /* 1690 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1691 * set by another thread while the object is locked. Thus, 1692 * if PGA_WRITEABLE is clear, no page table entries need updating. 1693 */ 1694 VM_OBJECT_ASSERT_WLOCKED(m->object); 1695 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1696 return; 1697 powerpc_sync(); 1698 PV_PAGE_LOCK(m); 1699 refchg = 0; 1700 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1701 pmap = pvo->pvo_pmap; 1702 PMAP_LOCK(pmap); 1703 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1704 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1705 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1706 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1707 MOEA64_PTE_PROT_UPDATE); 1708 if (ret < 0) 1709 ret = LPTE_CHG; 1710 refchg |= ret; 1711 if (pvo->pvo_pmap == kernel_pmap) 1712 isync(); 1713 } 1714 PMAP_UNLOCK(pmap); 1715 } 1716 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1717 vm_page_dirty(m); 1718 vm_page_aflag_clear(m, PGA_WRITEABLE); 1719 PV_PAGE_UNLOCK(m); 1720 } 1721 1722 /* 1723 * moea64_ts_referenced: 1724 * 1725 * Return a count of reference bits for a page, clearing those bits. 1726 * It is not necessary for every reference bit to be cleared, but it 1727 * is necessary that 0 only be returned when there are truly no 1728 * reference bits set. 1729 * 1730 * XXX: The exact number of bits to check and clear is a matter that 1731 * should be tested and standardized at some point in the future for 1732 * optimal aging of shared pages. 1733 */ 1734 int 1735 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1736 { 1737 1738 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1739 ("moea64_ts_referenced: page %p is not managed", m)); 1740 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1741 } 1742 1743 /* 1744 * Modify the WIMG settings of all mappings for a page. 1745 */ 1746 void 1747 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1748 { 1749 struct pvo_entry *pvo; 1750 int64_t refchg; 1751 pmap_t pmap; 1752 uint64_t lo; 1753 1754 if ((m->oflags & VPO_UNMANAGED) != 0) { 1755 m->md.mdpg_cache_attrs = ma; 1756 return; 1757 } 1758 1759 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1760 1761 PV_PAGE_LOCK(m); 1762 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1763 pmap = pvo->pvo_pmap; 1764 PMAP_LOCK(pmap); 1765 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1766 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1767 pvo->pvo_pte.pa |= lo; 1768 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1769 MOEA64_PTE_INVALIDATE); 1770 if (refchg < 0) 1771 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1772 LPTE_CHG : 0; 1773 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1774 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1775 refchg |= 1776 atomic_readandclear_32(&m->md.mdpg_attrs); 1777 if (refchg & LPTE_CHG) 1778 vm_page_dirty(m); 1779 if (refchg & LPTE_REF) 1780 vm_page_aflag_set(m, PGA_REFERENCED); 1781 } 1782 if (pvo->pvo_pmap == kernel_pmap) 1783 isync(); 1784 } 1785 PMAP_UNLOCK(pmap); 1786 } 1787 m->md.mdpg_cache_attrs = ma; 1788 PV_PAGE_UNLOCK(m); 1789 } 1790 1791 /* 1792 * Map a wired page into kernel virtual address space. 1793 */ 1794 void 1795 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1796 { 1797 int error; 1798 struct pvo_entry *pvo, *oldpvo; 1799 1800 pvo = alloc_pvo_entry(0); 1801 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1802 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1803 pvo->pvo_vaddr |= PVO_WIRED; 1804 1805 PMAP_LOCK(kernel_pmap); 1806 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1807 if (oldpvo != NULL) 1808 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1809 init_pvo_entry(pvo, kernel_pmap, va); 1810 error = moea64_pvo_enter(mmu, pvo, NULL); 1811 PMAP_UNLOCK(kernel_pmap); 1812 1813 /* Free any dead pages */ 1814 if (oldpvo != NULL) { 1815 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1816 moea64_pvo_remove_from_page(mmu, oldpvo); 1817 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1818 free_pvo_entry(oldpvo); 1819 } 1820 1821 if (error != 0 && error != ENOENT) 1822 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1823 (uintmax_t)pa, error); 1824 } 1825 1826 void 1827 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1828 { 1829 1830 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1831 } 1832 1833 /* 1834 * Extract the physical page address associated with the given kernel virtual 1835 * address. 1836 */ 1837 vm_paddr_t 1838 moea64_kextract(mmu_t mmu, vm_offset_t va) 1839 { 1840 struct pvo_entry *pvo; 1841 vm_paddr_t pa; 1842 1843 /* 1844 * Shortcut the direct-mapped case when applicable. We never put 1845 * anything but 1:1 (or 62-bit aliased) mappings below 1846 * VM_MIN_KERNEL_ADDRESS. 1847 */ 1848 if (va < VM_MIN_KERNEL_ADDRESS) 1849 return (va & ~DMAP_BASE_ADDRESS); 1850 1851 PMAP_LOCK(kernel_pmap); 1852 pvo = moea64_pvo_find_va(kernel_pmap, va); 1853 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1854 va)); 1855 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1856 PMAP_UNLOCK(kernel_pmap); 1857 return (pa); 1858 } 1859 1860 /* 1861 * Remove a wired page from kernel virtual address space. 1862 */ 1863 void 1864 moea64_kremove(mmu_t mmu, vm_offset_t va) 1865 { 1866 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1867 } 1868 1869 /* 1870 * Provide a kernel pointer corresponding to a given userland pointer. 1871 * The returned pointer is valid until the next time this function is 1872 * called in this thread. This is used internally in copyin/copyout. 1873 */ 1874 static int 1875 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1876 void **kaddr, size_t ulen, size_t *klen) 1877 { 1878 size_t l; 1879 #ifdef __powerpc64__ 1880 struct slb *slb; 1881 #endif 1882 register_t slbv; 1883 1884 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1885 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1886 if (l > ulen) 1887 l = ulen; 1888 if (klen) 1889 *klen = l; 1890 else if (l != ulen) 1891 return (EFAULT); 1892 1893 #ifdef __powerpc64__ 1894 /* Try lockless look-up first */ 1895 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1896 1897 if (slb == NULL) { 1898 /* If it isn't there, we need to pre-fault the VSID */ 1899 PMAP_LOCK(pm); 1900 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1901 PMAP_UNLOCK(pm); 1902 } else { 1903 slbv = slb->slbv; 1904 } 1905 1906 /* Mark segment no-execute */ 1907 slbv |= SLBV_N; 1908 #else 1909 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1910 1911 /* Mark segment no-execute */ 1912 slbv |= SR_N; 1913 #endif 1914 1915 /* If we have already set this VSID, we can just return */ 1916 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1917 return (0); 1918 1919 __asm __volatile("isync"); 1920 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1921 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1922 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1923 #ifdef __powerpc64__ 1924 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1925 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1926 #else 1927 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1928 #endif 1929 1930 return (0); 1931 } 1932 1933 /* 1934 * Figure out where a given kernel pointer (usually in a fault) points 1935 * to from the VM's perspective, potentially remapping into userland's 1936 * address space. 1937 */ 1938 static int 1939 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1940 vm_offset_t *decoded_addr) 1941 { 1942 vm_offset_t user_sr; 1943 1944 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1945 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1946 addr &= ADDR_PIDX | ADDR_POFF; 1947 addr |= user_sr << ADDR_SR_SHFT; 1948 *decoded_addr = addr; 1949 *is_user = 1; 1950 } else { 1951 *decoded_addr = addr; 1952 *is_user = 0; 1953 } 1954 1955 return (0); 1956 } 1957 1958 /* 1959 * Map a range of physical addresses into kernel virtual address space. 1960 * 1961 * The value passed in *virt is a suggested virtual address for the mapping. 1962 * Architectures which can support a direct-mapped physical to virtual region 1963 * can return the appropriate address within that region, leaving '*virt' 1964 * unchanged. Other architectures should map the pages starting at '*virt' and 1965 * update '*virt' with the first usable address after the mapped region. 1966 */ 1967 vm_offset_t 1968 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1969 vm_paddr_t pa_end, int prot) 1970 { 1971 vm_offset_t sva, va; 1972 1973 if (hw_direct_map) { 1974 /* 1975 * Check if every page in the region is covered by the direct 1976 * map. The direct map covers all of physical memory. Use 1977 * moea64_calc_wimg() as a shortcut to see if the page is in 1978 * physical memory as a way to see if the direct map covers it. 1979 */ 1980 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1981 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1982 break; 1983 if (va == pa_end) 1984 return (PHYS_TO_DMAP(pa_start)); 1985 } 1986 sva = *virt; 1987 va = sva; 1988 /* XXX respect prot argument */ 1989 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1990 moea64_kenter(mmu, va, pa_start); 1991 *virt = va; 1992 1993 return (sva); 1994 } 1995 1996 /* 1997 * Returns true if the pmap's pv is one of the first 1998 * 16 pvs linked to from this page. This count may 1999 * be changed upwards or downwards in the future; it 2000 * is only necessary that true be returned for a small 2001 * subset of pmaps for proper page aging. 2002 */ 2003 boolean_t 2004 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2005 { 2006 int loops; 2007 struct pvo_entry *pvo; 2008 boolean_t rv; 2009 2010 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2011 ("moea64_page_exists_quick: page %p is not managed", m)); 2012 loops = 0; 2013 rv = FALSE; 2014 PV_PAGE_LOCK(m); 2015 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2016 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2017 rv = TRUE; 2018 break; 2019 } 2020 if (++loops >= 16) 2021 break; 2022 } 2023 PV_PAGE_UNLOCK(m); 2024 return (rv); 2025 } 2026 2027 void 2028 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2029 { 2030 2031 m->md.mdpg_attrs = 0; 2032 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2033 LIST_INIT(&m->md.mdpg_pvoh); 2034 } 2035 2036 /* 2037 * Return the number of managed mappings to the given physical page 2038 * that are wired. 2039 */ 2040 int 2041 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2042 { 2043 struct pvo_entry *pvo; 2044 int count; 2045 2046 count = 0; 2047 if ((m->oflags & VPO_UNMANAGED) != 0) 2048 return (count); 2049 PV_PAGE_LOCK(m); 2050 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2051 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2052 count++; 2053 PV_PAGE_UNLOCK(m); 2054 return (count); 2055 } 2056 2057 static uintptr_t moea64_vsidcontext; 2058 2059 uintptr_t 2060 moea64_get_unique_vsid(void) { 2061 u_int entropy; 2062 register_t hash; 2063 uint32_t mask; 2064 int i; 2065 2066 entropy = 0; 2067 __asm __volatile("mftb %0" : "=r"(entropy)); 2068 2069 mtx_lock(&moea64_slb_mutex); 2070 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2071 u_int n; 2072 2073 /* 2074 * Create a new value by mutiplying by a prime and adding in 2075 * entropy from the timebase register. This is to make the 2076 * VSID more random so that the PT hash function collides 2077 * less often. (Note that the prime casues gcc to do shifts 2078 * instead of a multiply.) 2079 */ 2080 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2081 hash = moea64_vsidcontext & (NVSIDS - 1); 2082 if (hash == 0) /* 0 is special, avoid it */ 2083 continue; 2084 n = hash >> 5; 2085 mask = 1 << (hash & (VSID_NBPW - 1)); 2086 hash = (moea64_vsidcontext & VSID_HASHMASK); 2087 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2088 /* anything free in this bucket? */ 2089 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2090 entropy = (moea64_vsidcontext >> 20); 2091 continue; 2092 } 2093 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2094 mask = 1 << i; 2095 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2096 hash |= i; 2097 } 2098 if (hash == VSID_VRMA) /* also special, avoid this too */ 2099 continue; 2100 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2101 ("Allocating in-use VSID %#zx\n", hash)); 2102 moea64_vsid_bitmap[n] |= mask; 2103 mtx_unlock(&moea64_slb_mutex); 2104 return (hash); 2105 } 2106 2107 mtx_unlock(&moea64_slb_mutex); 2108 panic("%s: out of segments",__func__); 2109 } 2110 2111 #ifdef __powerpc64__ 2112 void 2113 moea64_pinit(mmu_t mmu, pmap_t pmap) 2114 { 2115 2116 RB_INIT(&pmap->pmap_pvo); 2117 2118 pmap->pm_slb_tree_root = slb_alloc_tree(); 2119 pmap->pm_slb = slb_alloc_user_cache(); 2120 pmap->pm_slb_len = 0; 2121 } 2122 #else 2123 void 2124 moea64_pinit(mmu_t mmu, pmap_t pmap) 2125 { 2126 int i; 2127 uint32_t hash; 2128 2129 RB_INIT(&pmap->pmap_pvo); 2130 2131 if (pmap_bootstrapped) 2132 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2133 (vm_offset_t)pmap); 2134 else 2135 pmap->pmap_phys = pmap; 2136 2137 /* 2138 * Allocate some segment registers for this pmap. 2139 */ 2140 hash = moea64_get_unique_vsid(); 2141 2142 for (i = 0; i < 16; i++) 2143 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2144 2145 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2146 } 2147 #endif 2148 2149 /* 2150 * Initialize the pmap associated with process 0. 2151 */ 2152 void 2153 moea64_pinit0(mmu_t mmu, pmap_t pm) 2154 { 2155 2156 PMAP_LOCK_INIT(pm); 2157 moea64_pinit(mmu, pm); 2158 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2159 } 2160 2161 /* 2162 * Set the physical protection on the specified range of this map as requested. 2163 */ 2164 static void 2165 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2166 { 2167 struct vm_page *pg; 2168 vm_prot_t oldprot; 2169 int32_t refchg; 2170 2171 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2172 2173 /* 2174 * Change the protection of the page. 2175 */ 2176 oldprot = pvo->pvo_pte.prot; 2177 pvo->pvo_pte.prot = prot; 2178 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2179 2180 /* 2181 * If the PVO is in the page table, update mapping 2182 */ 2183 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2184 if (refchg < 0) 2185 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2186 2187 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2188 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2189 if ((pg->oflags & VPO_UNMANAGED) == 0) 2190 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2191 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2192 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2193 } 2194 2195 /* 2196 * Update vm about the REF/CHG bits if the page is managed and we have 2197 * removed write access. 2198 */ 2199 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2200 (oldprot & VM_PROT_WRITE)) { 2201 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2202 if (refchg & LPTE_CHG) 2203 vm_page_dirty(pg); 2204 if (refchg & LPTE_REF) 2205 vm_page_aflag_set(pg, PGA_REFERENCED); 2206 } 2207 } 2208 2209 void 2210 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2211 vm_prot_t prot) 2212 { 2213 struct pvo_entry *pvo, *tpvo, key; 2214 2215 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2216 sva, eva, prot); 2217 2218 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2219 ("moea64_protect: non current pmap")); 2220 2221 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2222 moea64_remove(mmu, pm, sva, eva); 2223 return; 2224 } 2225 2226 PMAP_LOCK(pm); 2227 key.pvo_vaddr = sva; 2228 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2229 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2230 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2231 moea64_pvo_protect(mmu, pm, pvo, prot); 2232 } 2233 PMAP_UNLOCK(pm); 2234 } 2235 2236 /* 2237 * Map a list of wired pages into kernel virtual address space. This is 2238 * intended for temporary mappings which do not need page modification or 2239 * references recorded. Existing mappings in the region are overwritten. 2240 */ 2241 void 2242 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2243 { 2244 while (count-- > 0) { 2245 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2246 va += PAGE_SIZE; 2247 m++; 2248 } 2249 } 2250 2251 /* 2252 * Remove page mappings from kernel virtual address space. Intended for 2253 * temporary mappings entered by moea64_qenter. 2254 */ 2255 void 2256 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2257 { 2258 while (count-- > 0) { 2259 moea64_kremove(mmu, va); 2260 va += PAGE_SIZE; 2261 } 2262 } 2263 2264 void 2265 moea64_release_vsid(uint64_t vsid) 2266 { 2267 int idx, mask; 2268 2269 mtx_lock(&moea64_slb_mutex); 2270 idx = vsid & (NVSIDS-1); 2271 mask = 1 << (idx % VSID_NBPW); 2272 idx /= VSID_NBPW; 2273 KASSERT(moea64_vsid_bitmap[idx] & mask, 2274 ("Freeing unallocated VSID %#jx", vsid)); 2275 moea64_vsid_bitmap[idx] &= ~mask; 2276 mtx_unlock(&moea64_slb_mutex); 2277 } 2278 2279 2280 void 2281 moea64_release(mmu_t mmu, pmap_t pmap) 2282 { 2283 2284 /* 2285 * Free segment registers' VSIDs 2286 */ 2287 #ifdef __powerpc64__ 2288 slb_free_tree(pmap); 2289 slb_free_user_cache(pmap->pm_slb); 2290 #else 2291 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2292 2293 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2294 #endif 2295 } 2296 2297 /* 2298 * Remove all pages mapped by the specified pmap 2299 */ 2300 void 2301 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2302 { 2303 struct pvo_entry *pvo, *tpvo; 2304 struct pvo_tree tofree; 2305 2306 RB_INIT(&tofree); 2307 2308 PMAP_LOCK(pm); 2309 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2310 if (pvo->pvo_vaddr & PVO_WIRED) 2311 continue; 2312 2313 /* 2314 * For locking reasons, remove this from the page table and 2315 * pmap, but save delinking from the vm_page for a second 2316 * pass 2317 */ 2318 moea64_pvo_remove_from_pmap(mmu, pvo); 2319 RB_INSERT(pvo_tree, &tofree, pvo); 2320 } 2321 PMAP_UNLOCK(pm); 2322 2323 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2324 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2325 moea64_pvo_remove_from_page(mmu, pvo); 2326 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2327 RB_REMOVE(pvo_tree, &tofree, pvo); 2328 free_pvo_entry(pvo); 2329 } 2330 } 2331 2332 /* 2333 * Remove the given range of addresses from the specified map. 2334 */ 2335 void 2336 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2337 { 2338 struct pvo_entry *pvo, *tpvo, key; 2339 struct pvo_tree tofree; 2340 2341 /* 2342 * Perform an unsynchronized read. This is, however, safe. 2343 */ 2344 if (pm->pm_stats.resident_count == 0) 2345 return; 2346 2347 key.pvo_vaddr = sva; 2348 2349 RB_INIT(&tofree); 2350 2351 PMAP_LOCK(pm); 2352 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2353 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2354 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2355 2356 /* 2357 * For locking reasons, remove this from the page table and 2358 * pmap, but save delinking from the vm_page for a second 2359 * pass 2360 */ 2361 moea64_pvo_remove_from_pmap(mmu, pvo); 2362 RB_INSERT(pvo_tree, &tofree, pvo); 2363 } 2364 PMAP_UNLOCK(pm); 2365 2366 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2367 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2368 moea64_pvo_remove_from_page(mmu, pvo); 2369 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2370 RB_REMOVE(pvo_tree, &tofree, pvo); 2371 free_pvo_entry(pvo); 2372 } 2373 } 2374 2375 /* 2376 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2377 * will reflect changes in pte's back to the vm_page. 2378 */ 2379 void 2380 moea64_remove_all(mmu_t mmu, vm_page_t m) 2381 { 2382 struct pvo_entry *pvo, *next_pvo; 2383 struct pvo_head freequeue; 2384 int wasdead; 2385 pmap_t pmap; 2386 2387 LIST_INIT(&freequeue); 2388 2389 PV_PAGE_LOCK(m); 2390 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2391 pmap = pvo->pvo_pmap; 2392 PMAP_LOCK(pmap); 2393 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2394 if (!wasdead) 2395 moea64_pvo_remove_from_pmap(mmu, pvo); 2396 moea64_pvo_remove_from_page(mmu, pvo); 2397 if (!wasdead) 2398 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2399 PMAP_UNLOCK(pmap); 2400 2401 } 2402 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2403 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2404 PV_PAGE_UNLOCK(m); 2405 2406 /* Clean up UMA allocations */ 2407 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2408 free_pvo_entry(pvo); 2409 } 2410 2411 /* 2412 * Allocate a physical page of memory directly from the phys_avail map. 2413 * Can only be called from moea64_bootstrap before avail start and end are 2414 * calculated. 2415 */ 2416 vm_offset_t 2417 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2418 { 2419 vm_offset_t s, e; 2420 int i, j; 2421 2422 size = round_page(size); 2423 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2424 if (align != 0) 2425 s = roundup2(phys_avail[i], align); 2426 else 2427 s = phys_avail[i]; 2428 e = s + size; 2429 2430 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2431 continue; 2432 2433 if (s + size > platform_real_maxaddr()) 2434 continue; 2435 2436 if (s == phys_avail[i]) { 2437 phys_avail[i] += size; 2438 } else if (e == phys_avail[i + 1]) { 2439 phys_avail[i + 1] -= size; 2440 } else { 2441 for (j = phys_avail_count * 2; j > i; j -= 2) { 2442 phys_avail[j] = phys_avail[j - 2]; 2443 phys_avail[j + 1] = phys_avail[j - 1]; 2444 } 2445 2446 phys_avail[i + 3] = phys_avail[i + 1]; 2447 phys_avail[i + 1] = s; 2448 phys_avail[i + 2] = e; 2449 phys_avail_count++; 2450 } 2451 2452 return (s); 2453 } 2454 panic("moea64_bootstrap_alloc: could not allocate memory"); 2455 } 2456 2457 static int 2458 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2459 { 2460 int first, err; 2461 2462 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2463 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2464 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2465 2466 moea64_pvo_enter_calls++; 2467 2468 /* 2469 * Add to pmap list 2470 */ 2471 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2472 2473 /* 2474 * Remember if the list was empty and therefore will be the first 2475 * item. 2476 */ 2477 if (pvo_head != NULL) { 2478 if (LIST_FIRST(pvo_head) == NULL) 2479 first = 1; 2480 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2481 } 2482 2483 if (pvo->pvo_vaddr & PVO_WIRED) 2484 pvo->pvo_pmap->pm_stats.wired_count++; 2485 pvo->pvo_pmap->pm_stats.resident_count++; 2486 2487 /* 2488 * Insert it into the hardware page table 2489 */ 2490 err = MOEA64_PTE_INSERT(mmu, pvo); 2491 if (err != 0) { 2492 panic("moea64_pvo_enter: overflow"); 2493 } 2494 2495 moea64_pvo_entries++; 2496 2497 if (pvo->pvo_pmap == kernel_pmap) 2498 isync(); 2499 2500 #ifdef __powerpc64__ 2501 /* 2502 * Make sure all our bootstrap mappings are in the SLB as soon 2503 * as virtual memory is switched on. 2504 */ 2505 if (!pmap_bootstrapped) 2506 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2507 pvo->pvo_vaddr & PVO_LARGE); 2508 #endif 2509 2510 return (first ? ENOENT : 0); 2511 } 2512 2513 static void 2514 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2515 { 2516 struct vm_page *pg; 2517 int32_t refchg; 2518 2519 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2520 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2521 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2522 2523 /* 2524 * If there is an active pte entry, we need to deactivate it 2525 */ 2526 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2527 if (refchg < 0) { 2528 /* 2529 * If it was evicted from the page table, be pessimistic and 2530 * dirty the page. 2531 */ 2532 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2533 refchg = LPTE_CHG; 2534 else 2535 refchg = 0; 2536 } 2537 2538 /* 2539 * Update our statistics. 2540 */ 2541 pvo->pvo_pmap->pm_stats.resident_count--; 2542 if (pvo->pvo_vaddr & PVO_WIRED) 2543 pvo->pvo_pmap->pm_stats.wired_count--; 2544 2545 /* 2546 * Remove this PVO from the pmap list. 2547 */ 2548 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2549 2550 /* 2551 * Mark this for the next sweep 2552 */ 2553 pvo->pvo_vaddr |= PVO_DEAD; 2554 2555 /* Send RC bits to VM */ 2556 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2557 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2558 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2559 if (pg != NULL) { 2560 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2561 if (refchg & LPTE_CHG) 2562 vm_page_dirty(pg); 2563 if (refchg & LPTE_REF) 2564 vm_page_aflag_set(pg, PGA_REFERENCED); 2565 } 2566 } 2567 } 2568 2569 static void 2570 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2571 { 2572 struct vm_page *pg; 2573 2574 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2575 2576 /* Use NULL pmaps as a sentinel for races in page deletion */ 2577 if (pvo->pvo_pmap == NULL) 2578 return; 2579 pvo->pvo_pmap = NULL; 2580 2581 /* 2582 * Update vm about page writeability/executability if managed 2583 */ 2584 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2585 if (pvo->pvo_vaddr & PVO_MANAGED) { 2586 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2587 2588 if (pg != NULL) { 2589 LIST_REMOVE(pvo, pvo_vlink); 2590 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2591 vm_page_aflag_clear(pg, 2592 PGA_WRITEABLE | PGA_EXECUTABLE); 2593 } 2594 } 2595 2596 moea64_pvo_entries--; 2597 moea64_pvo_remove_calls++; 2598 } 2599 2600 static struct pvo_entry * 2601 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2602 { 2603 struct pvo_entry key; 2604 2605 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2606 2607 key.pvo_vaddr = va & ~ADDR_POFF; 2608 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2609 } 2610 2611 static boolean_t 2612 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2613 { 2614 struct pvo_entry *pvo; 2615 int64_t ret; 2616 boolean_t rv; 2617 2618 /* 2619 * See if this bit is stored in the page already. 2620 */ 2621 if (m->md.mdpg_attrs & ptebit) 2622 return (TRUE); 2623 2624 /* 2625 * Examine each PTE. Sync so that any pending REF/CHG bits are 2626 * flushed to the PTEs. 2627 */ 2628 rv = FALSE; 2629 powerpc_sync(); 2630 PV_PAGE_LOCK(m); 2631 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2632 ret = 0; 2633 2634 /* 2635 * See if this pvo has a valid PTE. if so, fetch the 2636 * REF/CHG bits from the valid PTE. If the appropriate 2637 * ptebit is set, return success. 2638 */ 2639 PMAP_LOCK(pvo->pvo_pmap); 2640 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2641 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2642 PMAP_UNLOCK(pvo->pvo_pmap); 2643 2644 if (ret > 0) { 2645 atomic_set_32(&m->md.mdpg_attrs, 2646 ret & (LPTE_CHG | LPTE_REF)); 2647 if (ret & ptebit) { 2648 rv = TRUE; 2649 break; 2650 } 2651 } 2652 } 2653 PV_PAGE_UNLOCK(m); 2654 2655 return (rv); 2656 } 2657 2658 static u_int 2659 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2660 { 2661 u_int count; 2662 struct pvo_entry *pvo; 2663 int64_t ret; 2664 2665 /* 2666 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2667 * we can reset the right ones). 2668 */ 2669 powerpc_sync(); 2670 2671 /* 2672 * For each pvo entry, clear the pte's ptebit. 2673 */ 2674 count = 0; 2675 PV_PAGE_LOCK(m); 2676 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2677 ret = 0; 2678 2679 PMAP_LOCK(pvo->pvo_pmap); 2680 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2681 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2682 PMAP_UNLOCK(pvo->pvo_pmap); 2683 2684 if (ret > 0 && (ret & ptebit)) 2685 count++; 2686 } 2687 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2688 PV_PAGE_UNLOCK(m); 2689 2690 return (count); 2691 } 2692 2693 boolean_t 2694 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2695 { 2696 struct pvo_entry *pvo, key; 2697 vm_offset_t ppa; 2698 int error = 0; 2699 2700 if (hw_direct_map && mem_valid(pa, size) == 0) 2701 return (0); 2702 2703 PMAP_LOCK(kernel_pmap); 2704 ppa = pa & ~ADDR_POFF; 2705 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2706 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2707 ppa < pa + size; ppa += PAGE_SIZE, 2708 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2709 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2710 error = EFAULT; 2711 break; 2712 } 2713 } 2714 PMAP_UNLOCK(kernel_pmap); 2715 2716 return (error); 2717 } 2718 2719 /* 2720 * Map a set of physical memory pages into the kernel virtual 2721 * address space. Return a pointer to where it is mapped. This 2722 * routine is intended to be used for mapping device memory, 2723 * NOT real memory. 2724 */ 2725 void * 2726 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2727 { 2728 vm_offset_t va, tmpva, ppa, offset; 2729 2730 ppa = trunc_page(pa); 2731 offset = pa & PAGE_MASK; 2732 size = roundup2(offset + size, PAGE_SIZE); 2733 2734 va = kva_alloc(size); 2735 2736 if (!va) 2737 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2738 2739 for (tmpva = va; size > 0;) { 2740 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2741 size -= PAGE_SIZE; 2742 tmpva += PAGE_SIZE; 2743 ppa += PAGE_SIZE; 2744 } 2745 2746 return ((void *)(va + offset)); 2747 } 2748 2749 void * 2750 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2751 { 2752 2753 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2754 } 2755 2756 void 2757 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2758 { 2759 vm_offset_t base, offset; 2760 2761 base = trunc_page(va); 2762 offset = va & PAGE_MASK; 2763 size = roundup2(offset + size, PAGE_SIZE); 2764 2765 kva_free(base, size); 2766 } 2767 2768 void 2769 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2770 { 2771 struct pvo_entry *pvo; 2772 vm_offset_t lim; 2773 vm_paddr_t pa; 2774 vm_size_t len; 2775 2776 PMAP_LOCK(pm); 2777 while (sz > 0) { 2778 lim = round_page(va); 2779 len = MIN(lim - va, sz); 2780 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2781 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2782 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2783 moea64_syncicache(mmu, pm, va, pa, len); 2784 } 2785 va += len; 2786 sz -= len; 2787 } 2788 PMAP_UNLOCK(pm); 2789 } 2790 2791 void 2792 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2793 { 2794 2795 *va = (void *)(uintptr_t)pa; 2796 } 2797 2798 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2799 2800 void 2801 moea64_scan_init(mmu_t mmu) 2802 { 2803 struct pvo_entry *pvo; 2804 vm_offset_t va; 2805 int i; 2806 2807 if (!do_minidump) { 2808 /* Initialize phys. segments for dumpsys(). */ 2809 memset(&dump_map, 0, sizeof(dump_map)); 2810 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2811 for (i = 0; i < pregions_sz; i++) { 2812 dump_map[i].pa_start = pregions[i].mr_start; 2813 dump_map[i].pa_size = pregions[i].mr_size; 2814 } 2815 return; 2816 } 2817 2818 /* Virtual segments for minidumps: */ 2819 memset(&dump_map, 0, sizeof(dump_map)); 2820 2821 /* 1st: kernel .data and .bss. */ 2822 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2823 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2824 dump_map[0].pa_start; 2825 2826 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2827 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2828 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2829 2830 /* 3rd: kernel VM. */ 2831 va = dump_map[1].pa_start + dump_map[1].pa_size; 2832 /* Find start of next chunk (from va). */ 2833 while (va < virtual_end) { 2834 /* Don't dump the buffer cache. */ 2835 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2836 va = kmi.buffer_eva; 2837 continue; 2838 } 2839 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2840 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2841 break; 2842 va += PAGE_SIZE; 2843 } 2844 if (va < virtual_end) { 2845 dump_map[2].pa_start = va; 2846 va += PAGE_SIZE; 2847 /* Find last page in chunk. */ 2848 while (va < virtual_end) { 2849 /* Don't run into the buffer cache. */ 2850 if (va == kmi.buffer_sva) 2851 break; 2852 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2853 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2854 break; 2855 va += PAGE_SIZE; 2856 } 2857 dump_map[2].pa_size = va - dump_map[2].pa_start; 2858 } 2859 } 2860 2861